| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.65 | 99.36 | 98.73 | 100.00 | 100.00 | 100.00 | 99.77 |
| T343 | /workspace/coverage/default/178.rv_timer_random.1830959704 | Jan 14 01:26:29 PM PST 24 | Jan 14 01:33:54 PM PST 24 | 131440307721 ps | ||
| T346 | /workspace/coverage/default/56.rv_timer_random.2090738622 | Jan 14 01:25:23 PM PST 24 | Jan 14 01:26:25 PM PST 24 | 68745617340 ps | ||
| T284 | /workspace/coverage/default/19.rv_timer_random.2539296672 | Jan 14 01:24:29 PM PST 24 | Jan 14 01:38:13 PM PST 24 | 823682017594 ps | ||
| T135 | /workspace/coverage/default/124.rv_timer_random.3258677076 | Jan 14 01:25:41 PM PST 24 | Jan 14 01:51:15 PM PST 24 | 271259352854 ps | ||
| T266 | /workspace/coverage/default/59.rv_timer_random.3219034517 | Jan 14 01:25:23 PM PST 24 | Jan 14 01:29:59 PM PST 24 | 467833846546 ps | ||
| T567 | /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.1473098492 | Jan 14 01:24:11 PM PST 24 | Jan 14 01:35:06 PM PST 24 | 66310358516 ps | ||
| T335 | /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.322245245 | Jan 14 01:25:19 PM PST 24 | Jan 14 01:27:17 PM PST 24 | 74971862572 ps | ||
| T362 | /workspace/coverage/default/6.rv_timer_random.683872169 | Jan 14 01:24:05 PM PST 24 | Jan 14 01:26:25 PM PST 24 | 80056978555 ps | ||
| T191 | /workspace/coverage/default/171.rv_timer_random.500153574 | Jan 14 01:26:20 PM PST 24 | Jan 14 01:27:11 PM PST 24 | 28683578874 ps | ||
| T294 | /workspace/coverage/default/198.rv_timer_random.803453111 | Jan 14 01:26:43 PM PST 24 | Jan 14 01:30:08 PM PST 24 | 116311969260 ps | ||
| T568 | /workspace/coverage/default/3.rv_timer_random.3839173547 | Jan 14 01:24:00 PM PST 24 | Jan 14 01:27:32 PM PST 24 | 324125430931 ps | ||
| T569 | /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.622474692 | Jan 14 01:25:18 PM PST 24 | Jan 14 01:40:17 PM PST 24 | 407062170794 ps | ||
| T216 | /workspace/coverage/default/118.rv_timer_random.3821023392 | Jan 14 01:25:38 PM PST 24 | Jan 14 01:32:40 PM PST 24 | 871120806047 ps | ||
| T157 | /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.2944579362 | Jan 14 01:24:37 PM PST 24 | Jan 14 01:36:20 PM PST 24 | 103882107253 ps | ||
| T238 | /workspace/coverage/default/35.rv_timer_random_reset.4031438616 | Jan 14 01:24:52 PM PST 24 | Jan 14 01:30:23 PM PST 24 | 20717713918 ps | ||
| T570 | /workspace/coverage/default/44.rv_timer_random_reset.3001257730 | Jan 14 01:25:12 PM PST 24 | Jan 14 01:32:10 PM PST 24 | 36467296185 ps | ||
| T571 | /workspace/coverage/default/23.rv_timer_random_reset.2292342797 | Jan 14 01:24:29 PM PST 24 | Jan 14 01:24:37 PM PST 24 | 6703961263 ps | ||
| T572 | /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.2344688768 | Jan 14 01:23:59 PM PST 24 | Jan 14 01:27:41 PM PST 24 | 26850669218 ps | ||
| T287 | /workspace/coverage/default/50.rv_timer_random.681765237 | Jan 14 01:25:35 PM PST 24 | Jan 14 01:29:00 PM PST 24 | 94656372884 ps | ||
| T344 | /workspace/coverage/default/95.rv_timer_random.2173354162 | Jan 14 01:25:43 PM PST 24 | Jan 14 01:27:18 PM PST 24 | 60064053691 ps | ||
| T573 | /workspace/coverage/default/48.rv_timer_disabled.1275065097 | Jan 14 01:25:20 PM PST 24 | Jan 14 01:25:48 PM PST 24 | 68118131476 ps | ||
| T251 | /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.4283135714 | Jan 14 01:25:02 PM PST 24 | Jan 14 01:42:56 PM PST 24 | 203918947886 ps | ||
| T574 | /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.1927594979 | Jan 14 01:24:36 PM PST 24 | Jan 14 01:40:30 PM PST 24 | 834915753688 ps | ||
| T18 | /workspace/coverage/default/0.rv_timer_sec_cm.3005694767 | Jan 14 01:23:54 PM PST 24 | Jan 14 01:23:55 PM PST 24 | 83630119 ps | ||
| T348 | /workspace/coverage/default/138.rv_timer_random.1500038247 | Jan 14 01:25:54 PM PST 24 | Jan 14 01:33:50 PM PST 24 | 627867681863 ps | ||
| T575 | /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.2768513222 | Jan 14 01:24:25 PM PST 24 | Jan 14 01:34:10 PM PST 24 | 142296069367 ps | ||
| T350 | /workspace/coverage/default/160.rv_timer_random.1703088667 | Jan 14 01:26:09 PM PST 24 | Jan 14 01:29:22 PM PST 24 | 83392058990 ps | ||
| T576 | /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.699266660 | Jan 14 01:25:20 PM PST 24 | Jan 14 01:35:15 PM PST 24 | 351964089035 ps | ||
| T132 | /workspace/coverage/default/139.rv_timer_random.1502013967 | Jan 14 01:25:52 PM PST 24 | Jan 14 01:32:19 PM PST 24 | 450620084786 ps | ||
| T577 | /workspace/coverage/default/38.rv_timer_disabled.2250349598 | Jan 14 01:24:54 PM PST 24 | Jan 14 01:27:17 PM PST 24 | 203591395660 ps | ||
| T578 | /workspace/coverage/default/18.rv_timer_disabled.2921934374 | Jan 14 01:24:32 PM PST 24 | Jan 14 01:29:52 PM PST 24 | 197522687617 ps | ||
| T579 | /workspace/coverage/default/37.rv_timer_disabled.1155121015 | Jan 14 01:24:55 PM PST 24 | Jan 14 01:26:26 PM PST 24 | 56079750731 ps | ||
| T129 | /workspace/coverage/default/37.rv_timer_random.731194875 | Jan 14 01:24:57 PM PST 24 | Jan 14 01:29:09 PM PST 24 | 142669046086 ps | ||
| T580 | /workspace/coverage/default/22.rv_timer_random_reset.2959399422 | Jan 14 01:24:33 PM PST 24 | Jan 14 01:24:46 PM PST 24 | 19270238548 ps | ||
| T311 | /workspace/coverage/default/64.rv_timer_random.925683294 | Jan 14 01:25:19 PM PST 24 | Jan 14 01:28:55 PM PST 24 | 125259706062 ps | ||
| T354 | /workspace/coverage/default/186.rv_timer_random.2975407244 | Jan 14 01:26:34 PM PST 24 | Jan 14 01:47:11 PM PST 24 | 846848220888 ps | ||
| T581 | /workspace/coverage/default/3.rv_timer_disabled.3263680953 | Jan 14 01:23:55 PM PST 24 | Jan 14 01:25:38 PM PST 24 | 70719178939 ps | ||
| T582 | /workspace/coverage/default/46.rv_timer_random_reset.2851161145 | Jan 14 01:25:22 PM PST 24 | Jan 14 01:26:46 PM PST 24 | 10926305379 ps | ||
| T140 | /workspace/coverage/default/86.rv_timer_random.3712757190 | Jan 14 01:25:36 PM PST 24 | Jan 14 01:40:39 PM PST 24 | 429909624098 ps | ||
| T583 | /workspace/coverage/default/25.rv_timer_random_reset.477652014 | Jan 14 01:24:36 PM PST 24 | Jan 14 01:24:42 PM PST 24 | 118141207 ps | ||
| T290 | /workspace/coverage/default/113.rv_timer_random.1256846481 | Jan 14 01:25:36 PM PST 24 | Jan 14 01:36:52 PM PST 24 | 109526877072 ps | ||
| T584 | /workspace/coverage/default/40.rv_timer_disabled.2811934180 | Jan 14 01:25:02 PM PST 24 | Jan 14 01:25:25 PM PST 24 | 46785175389 ps | ||
| T319 | /workspace/coverage/default/133.rv_timer_random.662470878 | Jan 14 01:25:47 PM PST 24 | Jan 14 01:36:10 PM PST 24 | 450457549891 ps | ||
| T331 | /workspace/coverage/default/37.rv_timer_stress_all.3054883071 | Jan 14 01:24:59 PM PST 24 | Jan 14 02:01:46 PM PST 24 | 2071416156167 ps | ||
| T340 | /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.3591585336 | Jan 14 01:24:26 PM PST 24 | Jan 14 01:30:17 PM PST 24 | 1026117679333 ps | ||
| T163 | /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.4038513282 | Jan 14 01:24:45 PM PST 24 | Jan 14 01:39:58 PM PST 24 | 480755351473 ps | ||
| T330 | /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2838383497 | Jan 14 01:24:24 PM PST 24 | Jan 14 01:38:11 PM PST 24 | 456866291929 ps | ||
| T126 | /workspace/coverage/default/28.rv_timer_stress_all.3450518114 | Jan 14 01:24:44 PM PST 24 | Jan 14 01:37:25 PM PST 24 | 665685147610 ps | ||
| T239 | /workspace/coverage/default/175.rv_timer_random.3304928331 | Jan 14 01:26:28 PM PST 24 | Jan 14 01:29:06 PM PST 24 | 98001431515 ps | ||
| T585 | /workspace/coverage/default/7.rv_timer_stress_all.4084223128 | Jan 14 01:24:06 PM PST 24 | Jan 14 01:27:26 PM PST 24 | 377052156704 ps | ||
| T253 | /workspace/coverage/default/12.rv_timer_stress_all.2184999289 | Jan 14 01:24:24 PM PST 24 | Jan 14 01:36:32 PM PST 24 | 487000994049 ps | ||
| T358 | /workspace/coverage/default/108.rv_timer_random.1796245289 | Jan 14 01:25:36 PM PST 24 | Jan 14 01:30:22 PM PST 24 | 143271769025 ps | ||
| T347 | /workspace/coverage/default/190.rv_timer_random.2738013953 | Jan 14 01:26:40 PM PST 24 | Jan 14 01:33:04 PM PST 24 | 745369371794 ps | ||
| T586 | /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.716580922 | Jan 14 01:24:18 PM PST 24 | Jan 14 01:28:19 PM PST 24 | 111657699179 ps | ||
| T304 | /workspace/coverage/default/176.rv_timer_random.1117139489 | Jan 14 01:26:28 PM PST 24 | Jan 14 01:34:25 PM PST 24 | 257881685066 ps | ||
| T227 | /workspace/coverage/default/5.rv_timer_stress_all.2033173994 | Jan 14 01:23:58 PM PST 24 | Jan 14 01:36:56 PM PST 24 | 468854668361 ps | ||
| T196 | /workspace/coverage/default/131.rv_timer_random.1391215552 | Jan 14 01:25:51 PM PST 24 | Jan 14 01:27:50 PM PST 24 | 134689634542 ps | ||
| T587 | /workspace/coverage/default/22.rv_timer_random.3283541941 | Jan 14 01:24:33 PM PST 24 | Jan 14 01:25:45 PM PST 24 | 42899644100 ps | ||
| T588 | /workspace/coverage/default/38.rv_timer_random.1013237236 | Jan 14 01:24:59 PM PST 24 | Jan 14 02:09:30 PM PST 24 | 449873092459 ps | ||
| T232 | /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3836826457 | Jan 14 01:25:11 PM PST 24 | Jan 14 01:37:19 PM PST 24 | 1342934097662 ps | ||
| T589 | /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.4010898689 | Jan 14 01:24:02 PM PST 24 | Jan 14 01:31:14 PM PST 24 | 1127902949087 ps | ||
| T590 | /workspace/coverage/default/4.rv_timer_stress_all.1468214493 | Jan 14 01:24:00 PM PST 24 | Jan 14 01:48:09 PM PST 24 | 314819925155 ps | ||
| T349 | /workspace/coverage/default/174.rv_timer_random.1186247748 | Jan 14 01:26:18 PM PST 24 | Jan 14 01:31:44 PM PST 24 | 84862078749 ps | ||
| T240 | /workspace/coverage/default/168.rv_timer_random.8757528 | Jan 14 01:26:17 PM PST 24 | Jan 14 01:37:36 PM PST 24 | 538423731743 ps | ||
| T591 | /workspace/coverage/default/21.rv_timer_random.2562481796 | Jan 14 01:24:33 PM PST 24 | Jan 14 01:54:33 PM PST 24 | 108682635109 ps | ||
| T217 | /workspace/coverage/default/172.rv_timer_random.4184806624 | Jan 14 01:26:19 PM PST 24 | Jan 14 01:29:49 PM PST 24 | 323359568169 ps | ||
| T341 | /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.2128204726 | Jan 14 01:23:52 PM PST 24 | Jan 14 01:27:33 PM PST 24 | 78587316185 ps | ||
| T297 | /workspace/coverage/default/94.rv_timer_random.3399931626 | Jan 14 01:25:41 PM PST 24 | Jan 14 01:37:45 PM PST 24 | 885402498842 ps | ||
| T202 | /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.4073383895 | Jan 14 01:24:42 PM PST 24 | Jan 14 01:38:11 PM PST 24 | 397570052215 ps | ||
| T230 | /workspace/coverage/default/15.rv_timer_stress_all.3335442844 | Jan 14 01:24:34 PM PST 24 | Jan 14 01:44:58 PM PST 24 | 762455181776 ps | ||
| T592 | /workspace/coverage/default/111.rv_timer_random.621092448 | Jan 14 01:25:30 PM PST 24 | Jan 14 01:28:26 PM PST 24 | 71131677224 ps | ||
| T364 | /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.2149967773 | Jan 14 01:23:52 PM PST 24 | Jan 14 01:41:03 PM PST 24 | 454323565908 ps | ||
| T593 | /workspace/coverage/default/187.rv_timer_random.195696384 | Jan 14 01:26:36 PM PST 24 | Jan 14 01:32:38 PM PST 24 | 113010588591 ps | ||
| T594 | /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3418915900 | Jan 14 01:24:17 PM PST 24 | Jan 14 01:56:51 PM PST 24 | 7982245795648 ps | ||
| T332 | /workspace/coverage/default/51.rv_timer_random.2550678584 | Jan 14 01:25:34 PM PST 24 | Jan 14 01:35:07 PM PST 24 | 303178090897 ps | ||
| T363 | /workspace/coverage/default/34.rv_timer_stress_all.99680431 | Jan 14 01:24:52 PM PST 24 | Jan 14 01:28:10 PM PST 24 | 115717112521 ps | ||
| T595 | /workspace/coverage/default/46.rv_timer_stress_all.2211416729 | Jan 14 01:25:19 PM PST 24 | Jan 14 01:26:03 PM PST 24 | 76219160667 ps | ||
| T596 | /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3767702255 | Jan 14 01:24:08 PM PST 24 | Jan 14 01:28:10 PM PST 24 | 266867567180 ps | ||
| T228 | /workspace/coverage/default/127.rv_timer_random.1823932676 | Jan 14 01:25:37 PM PST 24 | Jan 14 01:29:35 PM PST 24 | 139023341248 ps | ||
| T597 | /workspace/coverage/default/119.rv_timer_random.1571211066 | Jan 14 01:25:37 PM PST 24 | Jan 14 01:28:18 PM PST 24 | 107714360763 ps | ||
| T598 | /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.382450325 | Jan 14 01:24:30 PM PST 24 | Jan 14 01:27:25 PM PST 24 | 50820780855 ps | ||
| T213 | /workspace/coverage/default/54.rv_timer_random.3653767424 | Jan 14 01:25:23 PM PST 24 | Jan 14 01:27:31 PM PST 24 | 60228774869 ps | ||
| T599 | /workspace/coverage/default/149.rv_timer_random.3512687543 | Jan 14 01:25:58 PM PST 24 | Jan 14 01:46:43 PM PST 24 | 222909947586 ps | ||
| T600 | /workspace/coverage/default/89.rv_timer_random.3595031436 | Jan 14 01:25:41 PM PST 24 | Jan 14 01:30:06 PM PST 24 | 127846515386 ps | ||
| T145 | /workspace/coverage/default/76.rv_timer_random.537398770 | Jan 14 01:25:22 PM PST 24 | Jan 14 01:55:01 PM PST 24 | 165694313292 ps | ||
| T601 | /workspace/coverage/default/39.rv_timer_disabled.3871033085 | Jan 14 01:25:00 PM PST 24 | Jan 14 01:27:57 PM PST 24 | 235628003283 ps | ||
| T602 | /workspace/coverage/default/134.rv_timer_random.1248261847 | Jan 14 01:25:49 PM PST 24 | Jan 14 01:28:29 PM PST 24 | 203879590115 ps | ||
| T299 | /workspace/coverage/default/188.rv_timer_random.3195339259 | Jan 14 01:26:35 PM PST 24 | Jan 14 01:28:43 PM PST 24 | 127601755829 ps | ||
| T603 | /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3579443786 | Jan 14 01:24:21 PM PST 24 | Jan 14 01:24:52 PM PST 24 | 31696295506 ps | ||
| T359 | /workspace/coverage/default/40.rv_timer_random.557237572 | Jan 14 01:25:02 PM PST 24 | Jan 14 01:55:13 PM PST 24 | 49793809633 ps | ||
| T245 | /workspace/coverage/default/53.rv_timer_random.2902896386 | Jan 14 01:25:23 PM PST 24 | Jan 14 01:31:19 PM PST 24 | 196745619975 ps | ||
| T324 | /workspace/coverage/default/39.rv_timer_random_reset.2657883014 | Jan 14 01:25:01 PM PST 24 | Jan 14 01:42:52 PM PST 24 | 66733121343 ps | ||
| T148 | /workspace/coverage/default/27.rv_timer_stress_all.1318549697 | Jan 14 01:24:41 PM PST 24 | Jan 14 01:54:08 PM PST 24 | 2381622573920 ps | ||
| T604 | /workspace/coverage/default/1.rv_timer_disabled.1014103974 | Jan 14 01:23:59 PM PST 24 | Jan 14 01:24:19 PM PST 24 | 66642991142 ps | ||
| T605 | /workspace/coverage/default/34.rv_timer_random.1504250544 | Jan 14 01:24:53 PM PST 24 | Jan 14 01:25:28 PM PST 24 | 35222473657 ps | ||
| T360 | /workspace/coverage/default/52.rv_timer_random.3366148091 | Jan 14 01:25:36 PM PST 24 | Jan 14 01:38:35 PM PST 24 | 126924293840 ps | ||
| T307 | /workspace/coverage/default/181.rv_timer_random.316103947 | Jan 14 01:26:30 PM PST 24 | Jan 14 01:42:18 PM PST 24 | 347159681045 ps | ||
| T353 | /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1883700384 | Jan 14 01:25:06 PM PST 24 | Jan 14 01:31:54 PM PST 24 | 423793313801 ps | ||
| T606 | /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.4194202807 | Jan 14 01:25:04 PM PST 24 | Jan 14 01:27:26 PM PST 24 | 410034744133 ps | ||
| T607 | /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1951460835 | Jan 14 01:24:38 PM PST 24 | Jan 14 01:25:13 PM PST 24 | 75630713639 ps | ||
| T246 | /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1316052130 | Jan 14 01:24:51 PM PST 24 | Jan 14 01:35:50 PM PST 24 | 1337789903141 ps | ||
| T608 | /workspace/coverage/default/57.rv_timer_random.3816037371 | Jan 14 01:25:34 PM PST 24 | Jan 14 01:29:51 PM PST 24 | 368427232429 ps | ||
| T203 | /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3871666157 | Jan 14 01:23:59 PM PST 24 | Jan 14 01:28:52 PM PST 24 | 169413760637 ps | ||
| T325 | /workspace/coverage/default/16.rv_timer_stress_all.1425093239 | Jan 14 01:24:35 PM PST 24 | Jan 14 02:04:08 PM PST 24 | 2028271383442 ps | ||
| T336 | /workspace/coverage/default/69.rv_timer_random.2877206684 | Jan 14 01:25:17 PM PST 24 | Jan 14 01:34:02 PM PST 24 | 638711695577 ps | ||
| T609 | /workspace/coverage/default/115.rv_timer_random.1274535256 | Jan 14 01:25:38 PM PST 24 | Jan 14 01:27:55 PM PST 24 | 413009901213 ps | ||
| T610 | /workspace/coverage/default/136.rv_timer_random.2529042040 | Jan 14 01:25:48 PM PST 24 | Jan 14 01:27:03 PM PST 24 | 42726886543 ps | ||
| T19 | /workspace/coverage/default/1.rv_timer_sec_cm.3748475791 | Jan 14 01:23:58 PM PST 24 | Jan 14 01:24:00 PM PST 24 | 40844067 ps | ||
| T611 | /workspace/coverage/default/3.rv_timer_random_reset.823222219 | Jan 14 01:24:00 PM PST 24 | Jan 14 01:24:14 PM PST 24 | 10688954474 ps | ||
| T612 | /workspace/coverage/default/12.rv_timer_disabled.2763902854 | Jan 14 01:24:17 PM PST 24 | Jan 14 01:25:44 PM PST 24 | 193458543568 ps | ||
| T264 | /workspace/coverage/default/24.rv_timer_stress_all.2159948640 | Jan 14 01:24:39 PM PST 24 | Jan 14 01:28:58 PM PST 24 | 432899262729 ps | ||
| T613 | /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.1074627916 | Jan 14 01:25:20 PM PST 24 | Jan 14 01:35:03 PM PST 24 | 143225429089 ps | ||
| T614 | /workspace/coverage/default/154.rv_timer_random.3225509999 | Jan 14 01:25:57 PM PST 24 | Jan 14 01:28:38 PM PST 24 | 97521453221 ps | ||
| T220 | /workspace/coverage/default/48.rv_timer_stress_all.1634373917 | Jan 14 01:25:19 PM PST 24 | Jan 14 01:50:59 PM PST 24 | 214995855841 ps | ||
| T615 | /workspace/coverage/default/37.rv_timer_random_reset.3072104965 | Jan 14 01:24:58 PM PST 24 | Jan 14 01:25:00 PM PST 24 | 59823748 ps |
| Test location | /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.2920860221 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 58315190102 ps |
| CPU time | 348.72 seconds |
| Started | Jan 14 01:25:12 PM PST 24 |
| Finished | Jan 14 01:31:02 PM PST 24 |
| Peak memory | 197648 kb |
| Host | smart-67a3a0b3-a0bc-4e62-8443-d83d47dc8bc7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920860221 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.2920860221 |
| Directory | /workspace/45.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/74.rv_timer_random.3461828954 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 161205233162 ps |
| CPU time | 343.83 seconds |
| Started | Jan 14 01:25:31 PM PST 24 |
| Finished | Jan 14 01:31:15 PM PST 24 |
| Peak memory | 191256 kb |
| Host | smart-776a1b2a-ec0b-4678-a66f-af3858bf71a5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461828954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3461828954 |
| Directory | /workspace/74.rv_timer_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1492948870 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 325207506 ps |
| CPU time | 0.83 seconds |
| Started | Jan 14 01:13:01 PM PST 24 |
| Finished | Jan 14 01:13:06 PM PST 24 |
| Peak memory | 194100 kb |
| Host | smart-9607ee84-a94b-4bb6-9852-89c2ee3dc359 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492948870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i ntg_err.1492948870 |
| Directory | /workspace/15.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/19.rv_timer_stress_all.523526363 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 709798941130 ps |
| CPU time | 2488.31 seconds |
| Started | Jan 14 01:24:35 PM PST 24 |
| Finished | Jan 14 02:06:06 PM PST 24 |
| Peak memory | 194868 kb |
| Host | smart-6e58d621-f60f-4989-9122-3ebca24121f7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523526363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all. 523526363 |
| Directory | /workspace/19.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/3.rv_timer_stress_all.439949425 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 2459891083614 ps |
| CPU time | 6221.78 seconds |
| Started | Jan 14 01:23:59 PM PST 24 |
| Finished | Jan 14 03:07:42 PM PST 24 |
| Peak memory | 191052 kb |
| Host | smart-a365f87a-87b5-485d-993d-7dc84463bddf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439949425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.439949425 |
| Directory | /workspace/3.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/0.rv_timer_stress_all.1833886451 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1173477487401 ps |
| CPU time | 1151.6 seconds |
| Started | Jan 14 01:23:51 PM PST 24 |
| Finished | Jan 14 01:43:03 PM PST 24 |
| Peak memory | 191188 kb |
| Host | smart-50b79923-3f8b-4198-a319-d7dd8e9c27f7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833886451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all. 1833886451 |
| Directory | /workspace/0.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/42.rv_timer_stress_all.3303189790 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1171489159143 ps |
| CPU time | 1357.74 seconds |
| Started | Jan 14 01:25:09 PM PST 24 |
| Finished | Jan 14 01:47:48 PM PST 24 |
| Peak memory | 191156 kb |
| Host | smart-b94ae74f-acdb-492e-8468-b673356ff6f5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303189790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all .3303189790 |
| Directory | /workspace/42.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/49.rv_timer_stress_all.3665038463 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 2705853858578 ps |
| CPU time | 5294.11 seconds |
| Started | Jan 14 01:25:35 PM PST 24 |
| Finished | Jan 14 02:53:50 PM PST 24 |
| Peak memory | 191048 kb |
| Host | smart-434de438-253a-478b-9214-612484f180a4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665038463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all .3665038463 |
| Directory | /workspace/49.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.3595406030 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 355029450314 ps |
| CPU time | 446.91 seconds |
| Started | Jan 14 01:24:31 PM PST 24 |
| Finished | Jan 14 01:31:59 PM PST 24 |
| Peak memory | 205820 kb |
| Host | smart-c7f239c3-d7d3-4009-a3d5-7d2f6fa2dded |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595406030 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.3595406030 |
| Directory | /workspace/20.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.rv_timer_stress_all.4025552104 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 376805535376 ps |
| CPU time | 1229.27 seconds |
| Started | Jan 14 01:24:33 PM PST 24 |
| Finished | Jan 14 01:45:03 PM PST 24 |
| Peak memory | 191036 kb |
| Host | smart-64316f6a-f333-4a8d-a55f-757095be98c7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025552104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all .4025552104 |
| Directory | /workspace/20.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/6.rv_timer_stress_all.4245276740 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 867116403694 ps |
| CPU time | 2331.34 seconds |
| Started | Jan 14 01:24:11 PM PST 24 |
| Finished | Jan 14 02:03:03 PM PST 24 |
| Peak memory | 191212 kb |
| Host | smart-c63746c1-8ddd-4217-8a40-bbe7001980cc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245276740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all. 4245276740 |
| Directory | /workspace/6.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/27.rv_timer_stress_all.1318549697 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 2381622573920 ps |
| CPU time | 1764.01 seconds |
| Started | Jan 14 01:24:41 PM PST 24 |
| Finished | Jan 14 01:54:08 PM PST 24 |
| Peak memory | 191048 kb |
| Host | smart-49c6dcae-0e5d-47b7-9bbc-bd22cd676ac8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318549697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all .1318549697 |
| Directory | /workspace/27.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/30.rv_timer_stress_all.3341823998 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 2376275824386 ps |
| CPU time | 1194.28 seconds |
| Started | Jan 14 01:24:50 PM PST 24 |
| Finished | Jan 14 01:44:47 PM PST 24 |
| Peak memory | 191152 kb |
| Host | smart-5258e794-8821-465c-884f-2900e1c029c5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341823998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all .3341823998 |
| Directory | /workspace/30.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/0.rv_timer_sec_cm.3005694767 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 83630119 ps |
| CPU time | 0.9 seconds |
| Started | Jan 14 01:23:54 PM PST 24 |
| Finished | Jan 14 01:23:55 PM PST 24 |
| Peak memory | 213652 kb |
| Host | smart-e31bc233-81f5-4d16-aa8f-eafc56ad0cb9 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005694767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.3005694767 |
| Directory | /workspace/0.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/37.rv_timer_stress_all.3054883071 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 2071416156167 ps |
| CPU time | 2201.27 seconds |
| Started | Jan 14 01:24:59 PM PST 24 |
| Finished | Jan 14 02:01:46 PM PST 24 |
| Peak memory | 191240 kb |
| Host | smart-011ce70d-b45b-45a5-96a2-b0639ab47f6a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054883071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all .3054883071 |
| Directory | /workspace/37.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/195.rv_timer_random.3984884998 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 851470443733 ps |
| CPU time | 946.35 seconds |
| Started | Jan 14 01:26:49 PM PST 24 |
| Finished | Jan 14 01:42:36 PM PST 24 |
| Peak memory | 191184 kb |
| Host | smart-ccdcb614-c890-4621-96b1-6300b4806335 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984884998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3984884998 |
| Directory | /workspace/195.rv_timer_random/latest |
| Test location | /workspace/coverage/default/100.rv_timer_random.280863225 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 713195385590 ps |
| CPU time | 612.58 seconds |
| Started | Jan 14 01:25:30 PM PST 24 |
| Finished | Jan 14 01:35:44 PM PST 24 |
| Peak memory | 191196 kb |
| Host | smart-72fe1451-ac33-4489-b6a1-19292246796f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280863225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.280863225 |
| Directory | /workspace/100.rv_timer_random/latest |
| Test location | /workspace/coverage/default/39.rv_timer_stress_all.1720285469 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 418773622879 ps |
| CPU time | 643.21 seconds |
| Started | Jan 14 01:25:00 PM PST 24 |
| Finished | Jan 14 01:35:49 PM PST 24 |
| Peak memory | 191164 kb |
| Host | smart-ca28a0a7-6d3a-4edf-b10c-1c32f51380c8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720285469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all .1720285469 |
| Directory | /workspace/39.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/5.rv_timer_stress_all.2033173994 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 468854668361 ps |
| CPU time | 777.22 seconds |
| Started | Jan 14 01:23:58 PM PST 24 |
| Finished | Jan 14 01:36:56 PM PST 24 |
| Peak memory | 191156 kb |
| Host | smart-eed1afe8-eecb-4dfa-a3af-61804ea33e66 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033173994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all. 2033173994 |
| Directory | /workspace/5.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/15.rv_timer_random.716804762 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 466206848123 ps |
| CPU time | 674.26 seconds |
| Started | Jan 14 01:24:35 PM PST 24 |
| Finished | Jan 14 01:35:51 PM PST 24 |
| Peak memory | 191036 kb |
| Host | smart-29af1d29-fd78-4eaa-9887-b6cb549104a1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716804762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.716804762 |
| Directory | /workspace/15.rv_timer_random/latest |
| Test location | /workspace/coverage/default/31.rv_timer_stress_all.485069268 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 2004336007292 ps |
| CPU time | 1028.32 seconds |
| Started | Jan 14 01:24:42 PM PST 24 |
| Finished | Jan 14 01:41:52 PM PST 24 |
| Peak memory | 191116 kb |
| Host | smart-4ce9cfe5-a090-4b16-b497-43803749651a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485069268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all. 485069268 |
| Directory | /workspace/31.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/38.rv_timer_stress_all.2135349277 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 2117064538685 ps |
| CPU time | 1045.48 seconds |
| Started | Jan 14 01:24:59 PM PST 24 |
| Finished | Jan 14 01:42:32 PM PST 24 |
| Peak memory | 191168 kb |
| Host | smart-0a0ba35f-653e-4342-be84-15084f6a19e5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135349277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all .2135349277 |
| Directory | /workspace/38.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/123.rv_timer_random.2156056792 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 786456227138 ps |
| CPU time | 391.48 seconds |
| Started | Jan 14 01:25:38 PM PST 24 |
| Finished | Jan 14 01:32:10 PM PST 24 |
| Peak memory | 194488 kb |
| Host | smart-264f1ee5-2879-4ac1-93f6-c6ab39d18fc2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156056792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.2156056792 |
| Directory | /workspace/123.rv_timer_random/latest |
| Test location | /workspace/coverage/default/142.rv_timer_random.4086196999 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 158429013895 ps |
| CPU time | 264.56 seconds |
| Started | Jan 14 01:25:54 PM PST 24 |
| Finished | Jan 14 01:30:19 PM PST 24 |
| Peak memory | 191068 kb |
| Host | smart-4a0cde1f-8f00-4f88-8228-2644a2824ad8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086196999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.4086196999 |
| Directory | /workspace/142.rv_timer_random/latest |
| Test location | /workspace/coverage/default/145.rv_timer_random.2515047259 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 176692012921 ps |
| CPU time | 554.55 seconds |
| Started | Jan 14 01:25:53 PM PST 24 |
| Finished | Jan 14 01:35:08 PM PST 24 |
| Peak memory | 191128 kb |
| Host | smart-a07d8ef6-b324-4ac6-a452-c7632c4212fc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515047259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2515047259 |
| Directory | /workspace/145.rv_timer_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2161535436 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 21895868 ps |
| CPU time | 0.53 seconds |
| Started | Jan 14 01:12:40 PM PST 24 |
| Finished | Jan 14 01:12:42 PM PST 24 |
| Peak memory | 182868 kb |
| Host | smart-44e494af-0df4-4f5d-9efe-f747a6857f52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161535436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2161535436 |
| Directory | /workspace/3.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/default/15.rv_timer_stress_all.3335442844 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 762455181776 ps |
| CPU time | 1223 seconds |
| Started | Jan 14 01:24:34 PM PST 24 |
| Finished | Jan 14 01:44:58 PM PST 24 |
| Peak memory | 191096 kb |
| Host | smart-5d3af6ae-fb54-43ae-951d-a62452add141 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335442844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all .3335442844 |
| Directory | /workspace/15.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/35.rv_timer_stress_all.3942175267 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 3221725355810 ps |
| CPU time | 1630.48 seconds |
| Started | Jan 14 01:24:52 PM PST 24 |
| Finished | Jan 14 01:52:06 PM PST 24 |
| Peak memory | 194248 kb |
| Host | smart-c5ce703d-771e-4301-8832-350b2aa6d1c6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942175267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all .3942175267 |
| Directory | /workspace/35.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/139.rv_timer_random.1502013967 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 450620084786 ps |
| CPU time | 386.29 seconds |
| Started | Jan 14 01:25:52 PM PST 24 |
| Finished | Jan 14 01:32:19 PM PST 24 |
| Peak memory | 191208 kb |
| Host | smart-cd77d2c1-720f-4d4b-a929-856531fe50e0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502013967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.1502013967 |
| Directory | /workspace/139.rv_timer_random/latest |
| Test location | /workspace/coverage/default/61.rv_timer_random.3855296797 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 211077594869 ps |
| CPU time | 2076.4 seconds |
| Started | Jan 14 01:25:22 PM PST 24 |
| Finished | Jan 14 02:00:00 PM PST 24 |
| Peak memory | 191136 kb |
| Host | smart-295bdd05-3b0d-4938-8464-841a116718bb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855296797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3855296797 |
| Directory | /workspace/61.rv_timer_random/latest |
| Test location | /workspace/coverage/default/64.rv_timer_random.925683294 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 125259706062 ps |
| CPU time | 214.97 seconds |
| Started | Jan 14 01:25:19 PM PST 24 |
| Finished | Jan 14 01:28:55 PM PST 24 |
| Peak memory | 191072 kb |
| Host | smart-d060c94b-9a5a-4800-acf9-9c05746b5851 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925683294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.925683294 |
| Directory | /workspace/64.rv_timer_random/latest |
| Test location | /workspace/coverage/default/10.rv_timer_random.1686185908 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 95629842418 ps |
| CPU time | 158.19 seconds |
| Started | Jan 14 01:24:15 PM PST 24 |
| Finished | Jan 14 01:26:54 PM PST 24 |
| Peak memory | 191180 kb |
| Host | smart-078b7153-aa40-456c-998b-6231bc448df5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686185908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1686185908 |
| Directory | /workspace/10.rv_timer_random/latest |
| Test location | /workspace/coverage/default/109.rv_timer_random.3483025138 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 422463115929 ps |
| CPU time | 1874.11 seconds |
| Started | Jan 14 01:25:34 PM PST 24 |
| Finished | Jan 14 01:56:49 PM PST 24 |
| Peak memory | 191152 kb |
| Host | smart-b34209ca-13eb-4936-8640-9f2a0b436541 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483025138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3483025138 |
| Directory | /workspace/109.rv_timer_random/latest |
| Test location | /workspace/coverage/default/107.rv_timer_random.826817733 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 644263067401 ps |
| CPU time | 320.09 seconds |
| Started | Jan 14 01:25:30 PM PST 24 |
| Finished | Jan 14 01:30:50 PM PST 24 |
| Peak memory | 191080 kb |
| Host | smart-a6466f8e-5f5d-4632-93e7-651d26490588 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826817733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.826817733 |
| Directory | /workspace/107.rv_timer_random/latest |
| Test location | /workspace/coverage/default/116.rv_timer_random.1488862926 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 318856164989 ps |
| CPU time | 168.93 seconds |
| Started | Jan 14 01:25:43 PM PST 24 |
| Finished | Jan 14 01:28:33 PM PST 24 |
| Peak memory | 194516 kb |
| Host | smart-d0c15e4d-a06c-423c-8a20-88daee1002c2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488862926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1488862926 |
| Directory | /workspace/116.rv_timer_random/latest |
| Test location | /workspace/coverage/default/168.rv_timer_random.8757528 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 538423731743 ps |
| CPU time | 678.15 seconds |
| Started | Jan 14 01:26:17 PM PST 24 |
| Finished | Jan 14 01:37:36 PM PST 24 |
| Peak memory | 191212 kb |
| Host | smart-9621ce8c-0b79-4c7d-9189-9e885dedb438 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8757528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.8757528 |
| Directory | /workspace/168.rv_timer_random/latest |
| Test location | /workspace/coverage/default/26.rv_timer_stress_all.2554866674 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 569500741460 ps |
| CPU time | 1809.01 seconds |
| Started | Jan 14 01:24:37 PM PST 24 |
| Finished | Jan 14 01:54:52 PM PST 24 |
| Peak memory | 191036 kb |
| Host | smart-b3939df6-0230-452d-a3c5-ddd8e36062e3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554866674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all .2554866674 |
| Directory | /workspace/26.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1773440067 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 1501350045665 ps |
| CPU time | 753.28 seconds |
| Started | Jan 14 01:24:53 PM PST 24 |
| Finished | Jan 14 01:37:29 PM PST 24 |
| Peak memory | 182932 kb |
| Host | smart-2bb82aa0-71dd-4f27-a15e-cd80da45837c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773440067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.1773440067 |
| Directory | /workspace/35.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/46.rv_timer_random.1660239147 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 1252964783882 ps |
| CPU time | 425.11 seconds |
| Started | Jan 14 01:25:12 PM PST 24 |
| Finished | Jan 14 01:32:18 PM PST 24 |
| Peak memory | 191200 kb |
| Host | smart-dbed49c3-3236-4c3a-a0f2-c4ffde01fdd6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660239147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1660239147 |
| Directory | /workspace/46.rv_timer_random/latest |
| Test location | /workspace/coverage/default/106.rv_timer_random.90259280 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 142320091159 ps |
| CPU time | 236.24 seconds |
| Started | Jan 14 01:25:34 PM PST 24 |
| Finished | Jan 14 01:29:31 PM PST 24 |
| Peak memory | 191184 kb |
| Host | smart-c9acfbfe-579b-4050-97be-53d1272a3ef6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90259280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.90259280 |
| Directory | /workspace/106.rv_timer_random/latest |
| Test location | /workspace/coverage/default/138.rv_timer_random.1500038247 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 627867681863 ps |
| CPU time | 475.24 seconds |
| Started | Jan 14 01:25:54 PM PST 24 |
| Finished | Jan 14 01:33:50 PM PST 24 |
| Peak memory | 191148 kb |
| Host | smart-317ff7a2-660c-4d25-9af0-b638d1627bd1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500038247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1500038247 |
| Directory | /workspace/138.rv_timer_random/latest |
| Test location | /workspace/coverage/default/179.rv_timer_random.1481620381 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 518487242383 ps |
| CPU time | 1778.13 seconds |
| Started | Jan 14 01:26:29 PM PST 24 |
| Finished | Jan 14 01:56:08 PM PST 24 |
| Peak memory | 194068 kb |
| Host | smart-b22d044f-5374-4c74-8ff3-f0fd63bb86f1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481620381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1481620381 |
| Directory | /workspace/179.rv_timer_random/latest |
| Test location | /workspace/coverage/default/184.rv_timer_random.1810933761 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 55384703192 ps |
| CPU time | 99.76 seconds |
| Started | Jan 14 01:26:38 PM PST 24 |
| Finished | Jan 14 01:28:19 PM PST 24 |
| Peak memory | 191116 kb |
| Host | smart-7943e873-a864-49a5-8788-6b9d2c7a10ca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810933761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1810933761 |
| Directory | /workspace/184.rv_timer_random/latest |
| Test location | /workspace/coverage/default/19.rv_timer_random.2539296672 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 823682017594 ps |
| CPU time | 823.15 seconds |
| Started | Jan 14 01:24:29 PM PST 24 |
| Finished | Jan 14 01:38:13 PM PST 24 |
| Peak memory | 193240 kb |
| Host | smart-2d4b5e29-541e-4d0f-b744-12e1faec5456 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539296672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2539296672 |
| Directory | /workspace/19.rv_timer_random/latest |
| Test location | /workspace/coverage/default/40.rv_timer_stress_all.489128765 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 60872908666 ps |
| CPU time | 112.6 seconds |
| Started | Jan 14 01:25:02 PM PST 24 |
| Finished | Jan 14 01:26:59 PM PST 24 |
| Peak memory | 191060 kb |
| Host | smart-a17835eb-43a6-4996-9b13-711ce6476f70 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489128765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all. 489128765 |
| Directory | /workspace/40.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/76.rv_timer_random.537398770 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 165694313292 ps |
| CPU time | 1778.43 seconds |
| Started | Jan 14 01:25:22 PM PST 24 |
| Finished | Jan 14 01:55:01 PM PST 24 |
| Peak memory | 191148 kb |
| Host | smart-70f0231c-1701-4e88-9ecb-d52d77402063 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537398770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.537398770 |
| Directory | /workspace/76.rv_timer_random/latest |
| Test location | /workspace/coverage/default/81.rv_timer_random.1784647461 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 134420403774 ps |
| CPU time | 363.1 seconds |
| Started | Jan 14 01:25:24 PM PST 24 |
| Finished | Jan 14 01:31:28 PM PST 24 |
| Peak memory | 191148 kb |
| Host | smart-ac51644f-7e80-4af7-b1d2-d8aa18bbf5cf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784647461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1784647461 |
| Directory | /workspace/81.rv_timer_random/latest |
| Test location | /workspace/coverage/default/0.rv_timer_random.830884505 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 87587150581 ps |
| CPU time | 1728.51 seconds |
| Started | Jan 14 01:23:59 PM PST 24 |
| Finished | Jan 14 01:52:48 PM PST 24 |
| Peak memory | 191164 kb |
| Host | smart-06880319-d412-4f83-95e9-80f4ec96d2f8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830884505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.830884505 |
| Directory | /workspace/0.rv_timer_random/latest |
| Test location | /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.4226021534 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 241257247887 ps |
| CPU time | 244.42 seconds |
| Started | Jan 14 01:23:59 PM PST 24 |
| Finished | Jan 14 01:28:04 PM PST 24 |
| Peak memory | 182988 kb |
| Host | smart-98d617e7-0461-4550-9157-96110faec345 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226021534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_cfg_update_on_fly.4226021534 |
| Directory | /workspace/1.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/1.rv_timer_stress_all.2377464503 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1263260515046 ps |
| CPU time | 772.65 seconds |
| Started | Jan 14 01:23:59 PM PST 24 |
| Finished | Jan 14 01:36:52 PM PST 24 |
| Peak memory | 191140 kb |
| Host | smart-37b2b055-c2f0-4534-8773-0efe85e13d0f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377464503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all. 2377464503 |
| Directory | /workspace/1.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/159.rv_timer_random.3011263930 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 536076467164 ps |
| CPU time | 604.96 seconds |
| Started | Jan 14 01:26:09 PM PST 24 |
| Finished | Jan 14 01:36:14 PM PST 24 |
| Peak memory | 194136 kb |
| Host | smart-a6c145f6-ca59-414f-bd72-f316e5293978 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011263930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3011263930 |
| Directory | /workspace/159.rv_timer_random/latest |
| Test location | /workspace/coverage/default/177.rv_timer_random.1910563703 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 1059633405010 ps |
| CPU time | 451.13 seconds |
| Started | Jan 14 01:26:29 PM PST 24 |
| Finished | Jan 14 01:34:01 PM PST 24 |
| Peak memory | 191068 kb |
| Host | smart-5f722225-73b3-452c-832e-8c6797e48f42 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910563703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1910563703 |
| Directory | /workspace/177.rv_timer_random/latest |
| Test location | /workspace/coverage/default/18.rv_timer_stress_all.4230849454 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 336564904990 ps |
| CPU time | 1371.61 seconds |
| Started | Jan 14 01:24:24 PM PST 24 |
| Finished | Jan 14 01:47:16 PM PST 24 |
| Peak memory | 195548 kb |
| Host | smart-0e16e600-9ff6-4fcf-8415-e546c01e22e6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230849454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all .4230849454 |
| Directory | /workspace/18.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3871666157 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 169413760637 ps |
| CPU time | 292.67 seconds |
| Started | Jan 14 01:23:59 PM PST 24 |
| Finished | Jan 14 01:28:52 PM PST 24 |
| Peak memory | 182956 kb |
| Host | smart-5dfe8262-9c37-4ac3-8560-207236d67e5a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871666157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_cfg_update_on_fly.3871666157 |
| Directory | /workspace/2.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3864489819 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 1016827088406 ps |
| CPU time | 573.63 seconds |
| Started | Jan 14 01:24:41 PM PST 24 |
| Finished | Jan 14 01:34:18 PM PST 24 |
| Peak memory | 182968 kb |
| Host | smart-00feeea5-53a5-429e-bbcd-8898620adc92 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864489819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_cfg_update_on_fly.3864489819 |
| Directory | /workspace/24.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2358752986 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 322881254 ps |
| CPU time | 1.28 seconds |
| Started | Jan 14 01:12:43 PM PST 24 |
| Finished | Jan 14 01:12:45 PM PST 24 |
| Peak memory | 195556 kb |
| Host | smart-ddfd08b9-e594-4cfd-80ab-1136ecb8c86b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358752986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in tg_err.2358752986 |
| Directory | /workspace/4.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.rv_timer_random_reset.2712005843 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 711993774424 ps |
| CPU time | 245.92 seconds |
| Started | Jan 14 01:23:54 PM PST 24 |
| Finished | Jan 14 01:28:01 PM PST 24 |
| Peak memory | 193684 kb |
| Host | smart-1cd8bc95-2cda-44e0-87aa-0616de68e56c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2712005843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2712005843 |
| Directory | /workspace/0.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/1.rv_timer_random_reset.2994950075 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 58964280375 ps |
| CPU time | 95.68 seconds |
| Started | Jan 14 01:23:57 PM PST 24 |
| Finished | Jan 14 01:25:34 PM PST 24 |
| Peak memory | 182932 kb |
| Host | smart-7058f66b-7461-4f21-873d-0b16cd96fdfd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2994950075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2994950075 |
| Directory | /workspace/1.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/101.rv_timer_random.3491510127 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 463185987668 ps |
| CPU time | 170.3 seconds |
| Started | Jan 14 01:25:31 PM PST 24 |
| Finished | Jan 14 01:28:22 PM PST 24 |
| Peak memory | 191152 kb |
| Host | smart-18275333-8740-4752-8b31-8045ee8ce2ba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491510127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3491510127 |
| Directory | /workspace/101.rv_timer_random/latest |
| Test location | /workspace/coverage/default/12.rv_timer_stress_all.2184999289 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 487000994049 ps |
| CPU time | 727.18 seconds |
| Started | Jan 14 01:24:24 PM PST 24 |
| Finished | Jan 14 01:36:32 PM PST 24 |
| Peak memory | 191144 kb |
| Host | smart-bcddcc3e-6db8-44b7-a403-d1cc307b7b3d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184999289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all .2184999289 |
| Directory | /workspace/12.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/124.rv_timer_random.3258677076 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 271259352854 ps |
| CPU time | 1533.17 seconds |
| Started | Jan 14 01:25:41 PM PST 24 |
| Finished | Jan 14 01:51:15 PM PST 24 |
| Peak memory | 191164 kb |
| Host | smart-0d1b61d3-d992-4ab7-9f21-ad0db1dcc021 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258677076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3258677076 |
| Directory | /workspace/124.rv_timer_random/latest |
| Test location | /workspace/coverage/default/132.rv_timer_random.2281936191 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 345941019980 ps |
| CPU time | 251.41 seconds |
| Started | Jan 14 01:25:50 PM PST 24 |
| Finished | Jan 14 01:30:02 PM PST 24 |
| Peak memory | 191164 kb |
| Host | smart-588c7265-643e-4000-9148-61ffa66fcb0a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281936191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2281936191 |
| Directory | /workspace/132.rv_timer_random/latest |
| Test location | /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2838383497 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 456866291929 ps |
| CPU time | 826.99 seconds |
| Started | Jan 14 01:24:24 PM PST 24 |
| Finished | Jan 14 01:38:11 PM PST 24 |
| Peak memory | 182964 kb |
| Host | smart-83f52a5d-5113-4513-acba-7b34748aa92f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838383497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_cfg_update_on_fly.2838383497 |
| Directory | /workspace/18.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/186.rv_timer_random.2975407244 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 846848220888 ps |
| CPU time | 1235.89 seconds |
| Started | Jan 14 01:26:34 PM PST 24 |
| Finished | Jan 14 01:47:11 PM PST 24 |
| Peak memory | 191160 kb |
| Host | smart-cc6578c2-91b8-4cb1-92ea-4d461f9d50d9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975407244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2975407244 |
| Directory | /workspace/186.rv_timer_random/latest |
| Test location | /workspace/coverage/default/27.rv_timer_random_reset.1902764477 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 41687312075 ps |
| CPU time | 67.64 seconds |
| Started | Jan 14 01:24:45 PM PST 24 |
| Finished | Jan 14 01:25:59 PM PST 24 |
| Peak memory | 194664 kb |
| Host | smart-36bce5e7-8dc1-4875-9bcb-3b36c0cc1824 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1902764477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1902764477 |
| Directory | /workspace/27.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/28.rv_timer_stress_all.3450518114 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 665685147610 ps |
| CPU time | 753.89 seconds |
| Started | Jan 14 01:24:44 PM PST 24 |
| Finished | Jan 14 01:37:25 PM PST 24 |
| Peak memory | 191180 kb |
| Host | smart-8823c0b2-f075-41f3-8cb8-c825f16bf5d3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450518114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all .3450518114 |
| Directory | /workspace/28.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/5.rv_timer_random.2218068067 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 116675086643 ps |
| CPU time | 742.78 seconds |
| Started | Jan 14 01:24:06 PM PST 24 |
| Finished | Jan 14 01:36:29 PM PST 24 |
| Peak memory | 191076 kb |
| Host | smart-8d2eadb0-30fa-4ded-ba22-25ec573c484a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218068067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2218068067 |
| Directory | /workspace/5.rv_timer_random/latest |
| Test location | /workspace/coverage/default/67.rv_timer_random.511394655 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 99972057382 ps |
| CPU time | 108.05 seconds |
| Started | Jan 14 01:25:21 PM PST 24 |
| Finished | Jan 14 01:27:09 PM PST 24 |
| Peak memory | 194172 kb |
| Host | smart-0e0b8a8f-9630-4885-aeae-365dd22f144f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511394655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.511394655 |
| Directory | /workspace/67.rv_timer_random/latest |
| Test location | /workspace/coverage/default/80.rv_timer_random.12385778 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 163954633330 ps |
| CPU time | 414.68 seconds |
| Started | Jan 14 01:25:24 PM PST 24 |
| Finished | Jan 14 01:32:20 PM PST 24 |
| Peak memory | 191148 kb |
| Host | smart-22b2a062-3306-4ec0-aa4f-275bf6ddd513 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12385778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.12385778 |
| Directory | /workspace/80.rv_timer_random/latest |
| Test location | /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.515851819 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 41902926405 ps |
| CPU time | 73.68 seconds |
| Started | Jan 14 01:23:53 PM PST 24 |
| Finished | Jan 14 01:25:07 PM PST 24 |
| Peak memory | 183000 kb |
| Host | smart-fde9b635-cfcb-40e7-b5f2-0813d2825ee7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515851819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .rv_timer_cfg_update_on_fly.515851819 |
| Directory | /workspace/0.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.2149967773 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 454323565908 ps |
| CPU time | 1030.83 seconds |
| Started | Jan 14 01:23:52 PM PST 24 |
| Finished | Jan 14 01:41:03 PM PST 24 |
| Peak memory | 211184 kb |
| Host | smart-83c96bc6-48a5-436c-bd9e-6b175c7d5ca4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149967773 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.2149967773 |
| Directory | /workspace/1.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.1676938676 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 89509504952 ps |
| CPU time | 418.88 seconds |
| Started | Jan 14 01:24:15 PM PST 24 |
| Finished | Jan 14 01:31:14 PM PST 24 |
| Peak memory | 205744 kb |
| Host | smart-5ee26637-5681-4b08-b81a-5ef6ac5f8363 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676938676 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.1676938676 |
| Directory | /workspace/11.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/112.rv_timer_random.3570989270 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1245817473924 ps |
| CPU time | 385.15 seconds |
| Started | Jan 14 01:25:33 PM PST 24 |
| Finished | Jan 14 01:31:59 PM PST 24 |
| Peak memory | 191184 kb |
| Host | smart-358cfb43-1ae1-4cc4-ad35-ef992adf3acd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570989270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3570989270 |
| Directory | /workspace/112.rv_timer_random/latest |
| Test location | /workspace/coverage/default/114.rv_timer_random.2294756360 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 186739220811 ps |
| CPU time | 176.87 seconds |
| Started | Jan 14 01:25:36 PM PST 24 |
| Finished | Jan 14 01:28:34 PM PST 24 |
| Peak memory | 191152 kb |
| Host | smart-769ddd69-5030-4fbd-b1e6-9d7fe7448cab |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294756360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2294756360 |
| Directory | /workspace/114.rv_timer_random/latest |
| Test location | /workspace/coverage/default/120.rv_timer_random.1413750855 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 204865176535 ps |
| CPU time | 186.97 seconds |
| Started | Jan 14 01:25:39 PM PST 24 |
| Finished | Jan 14 01:28:47 PM PST 24 |
| Peak memory | 191164 kb |
| Host | smart-2bb2fb5f-e89d-4d11-b4f1-69c2e23b221c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413750855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1413750855 |
| Directory | /workspace/120.rv_timer_random/latest |
| Test location | /workspace/coverage/default/130.rv_timer_random.2297458247 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 109844264050 ps |
| CPU time | 414.79 seconds |
| Started | Jan 14 01:25:39 PM PST 24 |
| Finished | Jan 14 01:32:34 PM PST 24 |
| Peak memory | 191056 kb |
| Host | smart-eb5d43fd-a3e4-46e0-b949-3b5e98eb2fc5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297458247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2297458247 |
| Directory | /workspace/130.rv_timer_random/latest |
| Test location | /workspace/coverage/default/14.rv_timer_random.2717963546 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 404103262657 ps |
| CPU time | 764.31 seconds |
| Started | Jan 14 01:24:35 PM PST 24 |
| Finished | Jan 14 01:37:20 PM PST 24 |
| Peak memory | 191168 kb |
| Host | smart-8228fe7a-195e-4999-baa3-e65c568475f5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717963546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2717963546 |
| Directory | /workspace/14.rv_timer_random/latest |
| Test location | /workspace/coverage/default/14.rv_timer_stress_all.2781506361 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 2597117354665 ps |
| CPU time | 657.25 seconds |
| Started | Jan 14 01:24:28 PM PST 24 |
| Finished | Jan 14 01:35:26 PM PST 24 |
| Peak memory | 195536 kb |
| Host | smart-b6652cfc-de70-48bb-8d78-e65c2d4ce1c9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781506361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all .2781506361 |
| Directory | /workspace/14.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/153.rv_timer_random.1530747704 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 285603616634 ps |
| CPU time | 157.72 seconds |
| Started | Jan 14 01:26:03 PM PST 24 |
| Finished | Jan 14 01:28:42 PM PST 24 |
| Peak memory | 191204 kb |
| Host | smart-e33abef1-cf10-41fa-889f-7d78f47e1c5c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530747704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1530747704 |
| Directory | /workspace/153.rv_timer_random/latest |
| Test location | /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2102524037 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 763539865677 ps |
| CPU time | 443.79 seconds |
| Started | Jan 14 01:24:32 PM PST 24 |
| Finished | Jan 14 01:31:57 PM PST 24 |
| Peak memory | 182988 kb |
| Host | smart-750beccb-ac79-4239-9e4f-39b05bebcf0f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102524037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.2102524037 |
| Directory | /workspace/16.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/175.rv_timer_random.3304928331 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 98001431515 ps |
| CPU time | 157.34 seconds |
| Started | Jan 14 01:26:28 PM PST 24 |
| Finished | Jan 14 01:29:06 PM PST 24 |
| Peak memory | 191276 kb |
| Host | smart-a40443ec-ba11-4cb4-86f0-6ed89713e2d4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304928331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3304928331 |
| Directory | /workspace/175.rv_timer_random/latest |
| Test location | /workspace/coverage/default/182.rv_timer_random.2181882574 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 416952301676 ps |
| CPU time | 373.36 seconds |
| Started | Jan 14 01:26:29 PM PST 24 |
| Finished | Jan 14 01:32:43 PM PST 24 |
| Peak memory | 191168 kb |
| Host | smart-cb88d2af-9868-48dd-b1a7-e936d3f0b0ea |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181882574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.2181882574 |
| Directory | /workspace/182.rv_timer_random/latest |
| Test location | /workspace/coverage/default/185.rv_timer_random.1517553518 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 344163004087 ps |
| CPU time | 1005.19 seconds |
| Started | Jan 14 01:26:38 PM PST 24 |
| Finished | Jan 14 01:43:24 PM PST 24 |
| Peak memory | 193764 kb |
| Host | smart-4e85f5b1-6287-4684-b060-9b932d42a946 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517553518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1517553518 |
| Directory | /workspace/185.rv_timer_random/latest |
| Test location | /workspace/coverage/default/25.rv_timer_random.2294523719 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 602532575295 ps |
| CPU time | 180.43 seconds |
| Started | Jan 14 01:24:36 PM PST 24 |
| Finished | Jan 14 01:27:41 PM PST 24 |
| Peak memory | 191132 kb |
| Host | smart-0cdb1b48-f70d-487b-89df-e2cbd33110d8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294523719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2294523719 |
| Directory | /workspace/25.rv_timer_random/latest |
| Test location | /workspace/coverage/default/28.rv_timer_random.1023247186 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 16157618278 ps |
| CPU time | 39.73 seconds |
| Started | Jan 14 01:24:44 PM PST 24 |
| Finished | Jan 14 01:25:31 PM PST 24 |
| Peak memory | 194436 kb |
| Host | smart-09011f12-e3f7-4faa-9ed3-c04c893580bf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023247186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1023247186 |
| Directory | /workspace/28.rv_timer_random/latest |
| Test location | /workspace/coverage/default/37.rv_timer_random.731194875 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 142669046086 ps |
| CPU time | 251.34 seconds |
| Started | Jan 14 01:24:57 PM PST 24 |
| Finished | Jan 14 01:29:09 PM PST 24 |
| Peak memory | 191148 kb |
| Host | smart-ca9cd691-393d-440e-8764-492015bae694 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731194875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.731194875 |
| Directory | /workspace/37.rv_timer_random/latest |
| Test location | /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.2882936785 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 101322337296 ps |
| CPU time | 185.8 seconds |
| Started | Jan 14 01:25:00 PM PST 24 |
| Finished | Jan 14 01:28:12 PM PST 24 |
| Peak memory | 182956 kb |
| Host | smart-cdd958c8-d4b2-4c87-b957-dc9c72374d83 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882936785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_cfg_update_on_fly.2882936785 |
| Directory | /workspace/38.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/41.rv_timer_stress_all.777221857 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 3317955740368 ps |
| CPU time | 1470.25 seconds |
| Started | Jan 14 01:25:03 PM PST 24 |
| Finished | Jan 14 01:49:37 PM PST 24 |
| Peak memory | 191124 kb |
| Host | smart-78606ad3-b9d9-49b3-810a-f6cdbdcb82ec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777221857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all. 777221857 |
| Directory | /workspace/41.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.20241275 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 184101078815 ps |
| CPU time | 320.28 seconds |
| Started | Jan 14 01:25:23 PM PST 24 |
| Finished | Jan 14 01:30:44 PM PST 24 |
| Peak memory | 182904 kb |
| Host | smart-2a3d328b-23d4-4363-9a51-e0733c0b5da0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20241275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45 .rv_timer_cfg_update_on_fly.20241275 |
| Directory | /workspace/45.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2150393490 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 1757920275002 ps |
| CPU time | 503.38 seconds |
| Started | Jan 14 01:25:12 PM PST 24 |
| Finished | Jan 14 01:33:36 PM PST 24 |
| Peak memory | 182996 kb |
| Host | smart-8e45378e-f90f-4ffe-8e60-b5541ce647c3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150393490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_cfg_update_on_fly.2150393490 |
| Directory | /workspace/46.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3901744410 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 397703511338 ps |
| CPU time | 733.61 seconds |
| Started | Jan 14 01:23:57 PM PST 24 |
| Finished | Jan 14 01:36:11 PM PST 24 |
| Peak memory | 182932 kb |
| Host | smart-40409289-8e76-447a-9df2-a9d9a3612ee0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901744410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.3901744410 |
| Directory | /workspace/6.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.157844899 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 36369514 ps |
| CPU time | 0.83 seconds |
| Started | Jan 14 01:12:39 PM PST 24 |
| Finished | Jan 14 01:12:42 PM PST 24 |
| Peak memory | 193020 kb |
| Host | smart-29c1f007-7885-49e2-964a-8ba16202de7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157844899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alias ing.157844899 |
| Directory | /workspace/0.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3775359181 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 254096894 ps |
| CPU time | 2.69 seconds |
| Started | Jan 14 01:12:41 PM PST 24 |
| Finished | Jan 14 01:12:45 PM PST 24 |
| Peak memory | 183384 kb |
| Host | smart-0249ce50-c498-4812-8695-b22a37ed88cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775359181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_ bash.3775359181 |
| Directory | /workspace/0.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.917840403 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 57190858 ps |
| CPU time | 0.57 seconds |
| Started | Jan 14 01:12:41 PM PST 24 |
| Finished | Jan 14 01:12:43 PM PST 24 |
| Peak memory | 183228 kb |
| Host | smart-c1158682-8d8b-4596-8084-b3827c535128 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917840403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_re set.917840403 |
| Directory | /workspace/0.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.712278011 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 94944608 ps |
| CPU time | 0.76 seconds |
| Started | Jan 14 01:12:40 PM PST 24 |
| Finished | Jan 14 01:12:42 PM PST 24 |
| Peak memory | 195928 kb |
| Host | smart-9ac127da-a8da-4750-81f6-e29f200fa76f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712278011 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.712278011 |
| Directory | /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.4178926731 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 13798715 ps |
| CPU time | 0.55 seconds |
| Started | Jan 14 01:12:38 PM PST 24 |
| Finished | Jan 14 01:12:41 PM PST 24 |
| Peak memory | 182852 kb |
| Host | smart-4f18ec8b-93be-403f-9d18-b1e3d734573a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178926731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.4178926731 |
| Directory | /workspace/0.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1755610674 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 18936517 ps |
| CPU time | 0.59 seconds |
| Started | Jan 14 01:12:40 PM PST 24 |
| Finished | Jan 14 01:12:42 PM PST 24 |
| Peak memory | 182896 kb |
| Host | smart-2da11c21-6e2f-4a8c-adf5-898ed2bf8bb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755610674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1755610674 |
| Directory | /workspace/0.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.4240715078 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 44811936 ps |
| CPU time | 0.65 seconds |
| Started | Jan 14 01:12:41 PM PST 24 |
| Finished | Jan 14 01:12:43 PM PST 24 |
| Peak memory | 192488 kb |
| Host | smart-8ed3f25d-5335-467f-a2b6-fb3928549d37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240715078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti mer_same_csr_outstanding.4240715078 |
| Directory | /workspace/0.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.177083467 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 65224972 ps |
| CPU time | 1.55 seconds |
| Started | Jan 14 01:12:34 PM PST 24 |
| Finished | Jan 14 01:12:38 PM PST 24 |
| Peak memory | 197852 kb |
| Host | smart-e585e5b9-cd4d-495d-9db3-1f908e10433b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177083467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.177083467 |
| Directory | /workspace/0.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2036148072 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 77660770 ps |
| CPU time | 0.79 seconds |
| Started | Jan 14 01:12:41 PM PST 24 |
| Finished | Jan 14 01:12:44 PM PST 24 |
| Peak memory | 193720 kb |
| Host | smart-921081b7-c44d-4c65-9da2-989b284353a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036148072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in tg_err.2036148072 |
| Directory | /workspace/0.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2057152915 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 27929476 ps |
| CPU time | 0.74 seconds |
| Started | Jan 14 01:12:45 PM PST 24 |
| Finished | Jan 14 01:12:47 PM PST 24 |
| Peak memory | 183340 kb |
| Host | smart-392ecf00-0ee1-4726-87ab-0a20fbf296c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057152915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia sing.2057152915 |
| Directory | /workspace/1.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2401231835 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 247709533 ps |
| CPU time | 2.29 seconds |
| Started | Jan 14 01:12:40 PM PST 24 |
| Finished | Jan 14 01:12:43 PM PST 24 |
| Peak memory | 191644 kb |
| Host | smart-02bc36c5-1093-49bc-ae4a-f9fbfc992abb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401231835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_ bash.2401231835 |
| Directory | /workspace/1.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2925080828 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 40349518 ps |
| CPU time | 0.57 seconds |
| Started | Jan 14 01:12:37 PM PST 24 |
| Finished | Jan 14 01:12:41 PM PST 24 |
| Peak memory | 183300 kb |
| Host | smart-429d26b6-0d46-49e3-ad30-f8006fe449c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925080828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r eset.2925080828 |
| Directory | /workspace/1.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.461852670 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 30535898 ps |
| CPU time | 1.44 seconds |
| Started | Jan 14 01:12:38 PM PST 24 |
| Finished | Jan 14 01:12:42 PM PST 24 |
| Peak memory | 198088 kb |
| Host | smart-26c6b84c-0ef8-455e-aa65-85f9a8896cbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461852670 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.461852670 |
| Directory | /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1968993854 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 44630133 ps |
| CPU time | 0.58 seconds |
| Started | Jan 14 01:12:45 PM PST 24 |
| Finished | Jan 14 01:12:47 PM PST 24 |
| Peak memory | 183344 kb |
| Host | smart-b73a0282-4a0c-4953-a4a1-9c44032ee228 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968993854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1968993854 |
| Directory | /workspace/1.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2059738033 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 20604639 ps |
| CPU time | 0.52 seconds |
| Started | Jan 14 01:12:39 PM PST 24 |
| Finished | Jan 14 01:12:41 PM PST 24 |
| Peak memory | 182068 kb |
| Host | smart-84cc67d9-14b2-43e8-9854-24023d6204e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059738033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2059738033 |
| Directory | /workspace/1.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3458720751 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 20633186 ps |
| CPU time | 0.61 seconds |
| Started | Jan 14 01:12:41 PM PST 24 |
| Finished | Jan 14 01:12:43 PM PST 24 |
| Peak memory | 191880 kb |
| Host | smart-9f8c3305-61bd-423c-84f1-69641a9b50a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458720751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti mer_same_csr_outstanding.3458720751 |
| Directory | /workspace/1.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.391795732 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 28159131 ps |
| CPU time | 1.41 seconds |
| Started | Jan 14 01:12:40 PM PST 24 |
| Finished | Jan 14 01:12:42 PM PST 24 |
| Peak memory | 198028 kb |
| Host | smart-e2740180-942f-42d3-bf56-cbbdae23a3a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391795732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.391795732 |
| Directory | /workspace/1.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.125578321 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 162224296 ps |
| CPU time | 1.15 seconds |
| Started | Jan 14 01:12:41 PM PST 24 |
| Finished | Jan 14 01:12:44 PM PST 24 |
| Peak memory | 195124 kb |
| Host | smart-bfea15f4-f2dc-40e8-9b86-404e3932544a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125578321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int g_err.125578321 |
| Directory | /workspace/1.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.372917980 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 15681655 ps |
| CPU time | 0.8 seconds |
| Started | Jan 14 01:12:52 PM PST 24 |
| Finished | Jan 14 01:12:54 PM PST 24 |
| Peak memory | 195680 kb |
| Host | smart-6660320a-d347-4e96-9fc6-d7e6ab15ac55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372917980 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.372917980 |
| Directory | /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1582747253 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 15146461 ps |
| CPU time | 0.6 seconds |
| Started | Jan 14 01:12:56 PM PST 24 |
| Finished | Jan 14 01:12:58 PM PST 24 |
| Peak memory | 183220 kb |
| Host | smart-35823dfb-40b9-4643-b7d6-fd76ab7891d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582747253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1582747253 |
| Directory | /workspace/10.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2760096808 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 12330556 ps |
| CPU time | 0.56 seconds |
| Started | Jan 14 01:12:51 PM PST 24 |
| Finished | Jan 14 01:12:53 PM PST 24 |
| Peak memory | 183000 kb |
| Host | smart-88b8707b-e11a-4a74-beb1-73379d378b43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760096808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2760096808 |
| Directory | /workspace/10.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3309819560 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 86334553 ps |
| CPU time | 0.73 seconds |
| Started | Jan 14 01:12:50 PM PST 24 |
| Finished | Jan 14 01:12:52 PM PST 24 |
| Peak memory | 192068 kb |
| Host | smart-052edc60-8953-441c-9ecf-24a2621d0bf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309819560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t imer_same_csr_outstanding.3309819560 |
| Directory | /workspace/10.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3900477795 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 61689241 ps |
| CPU time | 1.62 seconds |
| Started | Jan 14 01:12:56 PM PST 24 |
| Finished | Jan 14 01:12:58 PM PST 24 |
| Peak memory | 197968 kb |
| Host | smart-5b13da37-ad92-46e8-90aa-ea552368de24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900477795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3900477795 |
| Directory | /workspace/10.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3440952306 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 198631360 ps |
| CPU time | 1.26 seconds |
| Started | Jan 14 01:12:56 PM PST 24 |
| Finished | Jan 14 01:13:00 PM PST 24 |
| Peak memory | 195580 kb |
| Host | smart-4002a461-44e4-45d2-bb94-8c16430be4f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440952306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i ntg_err.3440952306 |
| Directory | /workspace/10.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1366213356 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 25884486 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 01:12:57 PM PST 24 |
| Finished | Jan 14 01:13:00 PM PST 24 |
| Peak memory | 195496 kb |
| Host | smart-f009e61e-20b7-42f9-8e36-9feab11bd2a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366213356 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1366213356 |
| Directory | /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3720716658 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 16153331 ps |
| CPU time | 0.58 seconds |
| Started | Jan 14 01:12:55 PM PST 24 |
| Finished | Jan 14 01:12:57 PM PST 24 |
| Peak memory | 183276 kb |
| Host | smart-999ccd2a-f911-4e83-a930-c1aaee911b75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720716658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3720716658 |
| Directory | /workspace/11.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2238823283 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 27411196 ps |
| CPU time | 0.54 seconds |
| Started | Jan 14 01:12:57 PM PST 24 |
| Finished | Jan 14 01:12:59 PM PST 24 |
| Peak memory | 181948 kb |
| Host | smart-d1178f6c-1214-4e21-968c-02e9a5bf0bf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238823283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2238823283 |
| Directory | /workspace/11.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1975146324 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 77429512 ps |
| CPU time | 0.64 seconds |
| Started | Jan 14 01:12:57 PM PST 24 |
| Finished | Jan 14 01:12:59 PM PST 24 |
| Peak memory | 191884 kb |
| Host | smart-ff476f20-72bf-4fa0-b0c1-cfda5c3f3f94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975146324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t imer_same_csr_outstanding.1975146324 |
| Directory | /workspace/11.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1638125659 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 208872627 ps |
| CPU time | 2.15 seconds |
| Started | Jan 14 01:12:56 PM PST 24 |
| Finished | Jan 14 01:12:59 PM PST 24 |
| Peak memory | 197852 kb |
| Host | smart-81f32387-22b7-46e3-930b-e6960b8b42a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638125659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1638125659 |
| Directory | /workspace/11.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.686702417 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 151067111 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 01:12:56 PM PST 24 |
| Finished | Jan 14 01:12:59 PM PST 24 |
| Peak memory | 193984 kb |
| Host | smart-fc047e3f-852a-44ca-be93-13b48b366df5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686702417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in tg_err.686702417 |
| Directory | /workspace/11.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3650134954 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 75528672 ps |
| CPU time | 0.72 seconds |
| Started | Jan 14 01:12:56 PM PST 24 |
| Finished | Jan 14 01:12:58 PM PST 24 |
| Peak memory | 195344 kb |
| Host | smart-518bb404-5319-482c-839b-e9aed1464456 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650134954 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3650134954 |
| Directory | /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1366604892 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 44710188 ps |
| CPU time | 0.58 seconds |
| Started | Jan 14 01:12:53 PM PST 24 |
| Finished | Jan 14 01:12:54 PM PST 24 |
| Peak memory | 183336 kb |
| Host | smart-7669a7d7-1d42-4000-ba22-41c607a3804f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366604892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1366604892 |
| Directory | /workspace/12.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3153442681 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 15473117 ps |
| CPU time | 0.62 seconds |
| Started | Jan 14 01:12:58 PM PST 24 |
| Finished | Jan 14 01:13:00 PM PST 24 |
| Peak memory | 182844 kb |
| Host | smart-12275e58-1487-445e-97e3-cd3e991c78e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153442681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3153442681 |
| Directory | /workspace/12.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2809341133 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 32510348 ps |
| CPU time | 0.79 seconds |
| Started | Jan 14 01:12:55 PM PST 24 |
| Finished | Jan 14 01:12:57 PM PST 24 |
| Peak memory | 193832 kb |
| Host | smart-ad821296-3cc3-4dbd-8646-ad3bc2a9ee02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809341133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t imer_same_csr_outstanding.2809341133 |
| Directory | /workspace/12.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2335035106 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 57427669 ps |
| CPU time | 2.75 seconds |
| Started | Jan 14 01:12:56 PM PST 24 |
| Finished | Jan 14 01:12:59 PM PST 24 |
| Peak memory | 197936 kb |
| Host | smart-9d7c46ce-1af9-4d39-b361-e2efd03739bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335035106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2335035106 |
| Directory | /workspace/12.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2016006788 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 78366553 ps |
| CPU time | 1.12 seconds |
| Started | Jan 14 01:12:55 PM PST 24 |
| Finished | Jan 14 01:12:58 PM PST 24 |
| Peak memory | 195528 kb |
| Host | smart-055fae4e-3574-411a-8ae9-3352d48f3618 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016006788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i ntg_err.2016006788 |
| Directory | /workspace/12.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1845851677 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 41376746 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 01:12:55 PM PST 24 |
| Finished | Jan 14 01:12:58 PM PST 24 |
| Peak memory | 197544 kb |
| Host | smart-137869c6-a1af-4989-aeed-c6c3b0d6edba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845851677 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.1845851677 |
| Directory | /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2801419288 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 39373010 ps |
| CPU time | 0.54 seconds |
| Started | Jan 14 01:13:06 PM PST 24 |
| Finished | Jan 14 01:13:10 PM PST 24 |
| Peak memory | 182724 kb |
| Host | smart-2743c73e-ec68-4ba3-bff0-eadd19c6c624 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801419288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2801419288 |
| Directory | /workspace/13.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.441141524 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 33445393 ps |
| CPU time | 0.54 seconds |
| Started | Jan 14 01:12:56 PM PST 24 |
| Finished | Jan 14 01:12:58 PM PST 24 |
| Peak memory | 182788 kb |
| Host | smart-653c601f-2d1c-4ef5-87f5-2674ec4eb20c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441141524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.441141524 |
| Directory | /workspace/13.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3484407410 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 70208753 ps |
| CPU time | 0.79 seconds |
| Started | Jan 14 01:12:53 PM PST 24 |
| Finished | Jan 14 01:12:55 PM PST 24 |
| Peak memory | 192276 kb |
| Host | smart-743492d4-2986-4cd4-93b9-02083a9068ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484407410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t imer_same_csr_outstanding.3484407410 |
| Directory | /workspace/13.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3142632043 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 169897426 ps |
| CPU time | 2.77 seconds |
| Started | Jan 14 01:12:53 PM PST 24 |
| Finished | Jan 14 01:12:57 PM PST 24 |
| Peak memory | 198048 kb |
| Host | smart-e4353c63-38a1-48c5-a9b5-93cbf413705d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142632043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3142632043 |
| Directory | /workspace/13.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3889814950 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 339495181 ps |
| CPU time | 1.11 seconds |
| Started | Jan 14 01:13:06 PM PST 24 |
| Finished | Jan 14 01:13:10 PM PST 24 |
| Peak memory | 195332 kb |
| Host | smart-61a209ad-0b19-4398-b4af-7e32b99a772e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889814950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i ntg_err.3889814950 |
| Directory | /workspace/13.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1315844689 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 28204096 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 01:13:03 PM PST 24 |
| Finished | Jan 14 01:13:07 PM PST 24 |
| Peak memory | 197776 kb |
| Host | smart-755fbaac-69fe-4eea-97a3-dc822ba83bd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315844689 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.1315844689 |
| Directory | /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1214059710 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 14791644 ps |
| CPU time | 0.58 seconds |
| Started | Jan 14 01:13:08 PM PST 24 |
| Finished | Jan 14 01:13:10 PM PST 24 |
| Peak memory | 183276 kb |
| Host | smart-e8af2e4a-36e5-47d1-87c6-1a763c3f401b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214059710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1214059710 |
| Directory | /workspace/14.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1275069544 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 13528936 ps |
| CPU time | 0.52 seconds |
| Started | Jan 14 01:13:09 PM PST 24 |
| Finished | Jan 14 01:13:10 PM PST 24 |
| Peak memory | 182552 kb |
| Host | smart-120cba85-a3b5-4bae-836e-e51e3d9ae98a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275069544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1275069544 |
| Directory | /workspace/14.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2649534691 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 19414675 ps |
| CPU time | 0.72 seconds |
| Started | Jan 14 01:13:04 PM PST 24 |
| Finished | Jan 14 01:13:07 PM PST 24 |
| Peak memory | 193660 kb |
| Host | smart-26809e3f-fdf0-4893-bb4b-2b8afa67fee3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649534691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t imer_same_csr_outstanding.2649534691 |
| Directory | /workspace/14.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.195115213 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 108403802 ps |
| CPU time | 2.34 seconds |
| Started | Jan 14 01:12:58 PM PST 24 |
| Finished | Jan 14 01:13:02 PM PST 24 |
| Peak memory | 198100 kb |
| Host | smart-fa2801c6-417e-4f18-8404-1176cf90e6cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195115213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.195115213 |
| Directory | /workspace/14.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3321462773 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 97749900 ps |
| CPU time | 1.1 seconds |
| Started | Jan 14 01:13:10 PM PST 24 |
| Finished | Jan 14 01:13:12 PM PST 24 |
| Peak memory | 183660 kb |
| Host | smart-1d50e2ae-5183-4b09-a2c2-0da5f9a96486 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321462773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i ntg_err.3321462773 |
| Directory | /workspace/14.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2121368891 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 44923931 ps |
| CPU time | 0.83 seconds |
| Started | Jan 14 01:13:04 PM PST 24 |
| Finished | Jan 14 01:13:07 PM PST 24 |
| Peak memory | 196412 kb |
| Host | smart-18794f91-8733-45ff-b401-87e6da7baac3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121368891 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2121368891 |
| Directory | /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1323840843 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 34333759 ps |
| CPU time | 0.54 seconds |
| Started | Jan 14 01:13:03 PM PST 24 |
| Finished | Jan 14 01:13:06 PM PST 24 |
| Peak memory | 182732 kb |
| Host | smart-7d6df444-3834-4fb3-a333-37f92b5c3e76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323840843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1323840843 |
| Directory | /workspace/15.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2102127251 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 33920873 ps |
| CPU time | 0.53 seconds |
| Started | Jan 14 01:13:04 PM PST 24 |
| Finished | Jan 14 01:13:06 PM PST 24 |
| Peak memory | 182060 kb |
| Host | smart-41a6f5c8-068b-492b-9184-a433b6f5122d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102127251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2102127251 |
| Directory | /workspace/15.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3536922290 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 24189798 ps |
| CPU time | 0.69 seconds |
| Started | Jan 14 01:13:02 PM PST 24 |
| Finished | Jan 14 01:13:06 PM PST 24 |
| Peak memory | 192604 kb |
| Host | smart-f150dad4-5de2-44f8-a577-3ff7aa464746 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536922290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t imer_same_csr_outstanding.3536922290 |
| Directory | /workspace/15.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1952603154 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 114619172 ps |
| CPU time | 1.44 seconds |
| Started | Jan 14 01:13:08 PM PST 24 |
| Finished | Jan 14 01:13:11 PM PST 24 |
| Peak memory | 198024 kb |
| Host | smart-fbef5dd0-b027-4a9e-8791-da17eccc2ddf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952603154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1952603154 |
| Directory | /workspace/15.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1128666385 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 15496454 ps |
| CPU time | 0.81 seconds |
| Started | Jan 14 01:13:05 PM PST 24 |
| Finished | Jan 14 01:13:09 PM PST 24 |
| Peak memory | 195500 kb |
| Host | smart-624cfa24-163c-4936-b632-3681bfb97b02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128666385 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.1128666385 |
| Directory | /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.4097570988 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 20055507 ps |
| CPU time | 0.55 seconds |
| Started | Jan 14 01:13:07 PM PST 24 |
| Finished | Jan 14 01:13:10 PM PST 24 |
| Peak memory | 183320 kb |
| Host | smart-bd644784-eea0-4ba3-a61b-d7ee756e4d6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097570988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.4097570988 |
| Directory | /workspace/16.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2697033830 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 223878702 ps |
| CPU time | 0.59 seconds |
| Started | Jan 14 01:13:04 PM PST 24 |
| Finished | Jan 14 01:13:06 PM PST 24 |
| Peak memory | 182976 kb |
| Host | smart-88abb853-e724-4eae-abaf-0936e48795b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697033830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2697033830 |
| Directory | /workspace/16.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1032378556 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 35440431 ps |
| CPU time | 0.8 seconds |
| Started | Jan 14 01:13:07 PM PST 24 |
| Finished | Jan 14 01:13:10 PM PST 24 |
| Peak memory | 193876 kb |
| Host | smart-cec3889d-4b03-4806-9f62-440f28d8a24c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032378556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t imer_same_csr_outstanding.1032378556 |
| Directory | /workspace/16.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.706810580 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 114486082 ps |
| CPU time | 1.9 seconds |
| Started | Jan 14 01:13:02 PM PST 24 |
| Finished | Jan 14 01:13:08 PM PST 24 |
| Peak memory | 198000 kb |
| Host | smart-8dbf9aea-15b5-44bc-a494-34e84c3d3e82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706810580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.706810580 |
| Directory | /workspace/16.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1554552235 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 190245884 ps |
| CPU time | 1.36 seconds |
| Started | Jan 14 01:13:04 PM PST 24 |
| Finished | Jan 14 01:13:07 PM PST 24 |
| Peak memory | 183784 kb |
| Host | smart-1badaecf-4061-4ed1-bf3c-7f84025c0248 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554552235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i ntg_err.1554552235 |
| Directory | /workspace/16.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3699557588 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 100029244 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 01:13:08 PM PST 24 |
| Finished | Jan 14 01:13:10 PM PST 24 |
| Peak memory | 196620 kb |
| Host | smart-0d6d9a75-9ff5-4cf1-b782-b264a1bdb316 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699557588 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3699557588 |
| Directory | /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2090175551 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 23913787 ps |
| CPU time | 0.53 seconds |
| Started | Jan 14 01:13:02 PM PST 24 |
| Finished | Jan 14 01:13:06 PM PST 24 |
| Peak memory | 183144 kb |
| Host | smart-b093c8b8-39e7-4b40-b8e7-89860d93abf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090175551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2090175551 |
| Directory | /workspace/17.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.614963140 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 25510665 ps |
| CPU time | 0.56 seconds |
| Started | Jan 14 01:13:06 PM PST 24 |
| Finished | Jan 14 01:13:09 PM PST 24 |
| Peak memory | 182940 kb |
| Host | smart-5cc6d052-8ef8-4967-9786-5e3b16786070 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614963140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.614963140 |
| Directory | /workspace/17.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.174171354 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 130808144 ps |
| CPU time | 0.84 seconds |
| Started | Jan 14 01:13:09 PM PST 24 |
| Finished | Jan 14 01:13:11 PM PST 24 |
| Peak memory | 192240 kb |
| Host | smart-ff8d51b8-8bf6-48d8-a916-52dd6a3101fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174171354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti mer_same_csr_outstanding.174171354 |
| Directory | /workspace/17.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.201559364 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 137141348 ps |
| CPU time | 2.75 seconds |
| Started | Jan 14 01:13:04 PM PST 24 |
| Finished | Jan 14 01:13:09 PM PST 24 |
| Peak memory | 197972 kb |
| Host | smart-ee3ca7ea-bb6e-43fb-83a8-b141653d8c74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201559364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.201559364 |
| Directory | /workspace/17.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.314954122 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 183475045 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 01:13:07 PM PST 24 |
| Finished | Jan 14 01:13:10 PM PST 24 |
| Peak memory | 193872 kb |
| Host | smart-5f58a349-2e48-4cb9-b26d-199c00300ec9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314954122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in tg_err.314954122 |
| Directory | /workspace/17.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3507755807 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 20777932 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 01:13:16 PM PST 24 |
| Finished | Jan 14 01:13:19 PM PST 24 |
| Peak memory | 197960 kb |
| Host | smart-38fe2b0c-12fe-4032-b7a6-818770315376 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507755807 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3507755807 |
| Directory | /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1450649156 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 14853228 ps |
| CPU time | 0.59 seconds |
| Started | Jan 14 01:13:16 PM PST 24 |
| Finished | Jan 14 01:13:18 PM PST 24 |
| Peak memory | 192496 kb |
| Host | smart-37fd523b-a00a-41a9-b51f-038c313bbc94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450649156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1450649156 |
| Directory | /workspace/18.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3363888273 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 120676591 ps |
| CPU time | 0.52 seconds |
| Started | Jan 14 01:13:06 PM PST 24 |
| Finished | Jan 14 01:13:10 PM PST 24 |
| Peak memory | 182100 kb |
| Host | smart-197c5274-1234-4f94-891c-7bc54ca6ba43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363888273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3363888273 |
| Directory | /workspace/18.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.4155624689 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 62217939 ps |
| CPU time | 0.62 seconds |
| Started | Jan 14 01:13:20 PM PST 24 |
| Finished | Jan 14 01:13:22 PM PST 24 |
| Peak memory | 191932 kb |
| Host | smart-d910a819-608b-4bf5-9808-363cd66b0c0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155624689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t imer_same_csr_outstanding.4155624689 |
| Directory | /workspace/18.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3233173754 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 102711463 ps |
| CPU time | 2.12 seconds |
| Started | Jan 14 01:13:05 PM PST 24 |
| Finished | Jan 14 01:13:09 PM PST 24 |
| Peak memory | 198004 kb |
| Host | smart-b2d4485c-48ed-4f19-a6c5-69990f81422d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233173754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3233173754 |
| Directory | /workspace/18.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.157491454 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 41629760 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 01:13:05 PM PST 24 |
| Finished | Jan 14 01:13:09 PM PST 24 |
| Peak memory | 193744 kb |
| Host | smart-df82781e-695d-4768-adf3-043a0022182a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157491454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_in tg_err.157491454 |
| Directory | /workspace/18.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1906457341 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 69118342 ps |
| CPU time | 1.12 seconds |
| Started | Jan 14 01:13:16 PM PST 24 |
| Finished | Jan 14 01:13:19 PM PST 24 |
| Peak memory | 197124 kb |
| Host | smart-bf501476-dbf0-4bb1-b53f-a1f97fc17e43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906457341 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1906457341 |
| Directory | /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.10446318 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 17850833 ps |
| CPU time | 0.59 seconds |
| Started | Jan 14 01:13:16 PM PST 24 |
| Finished | Jan 14 01:13:18 PM PST 24 |
| Peak memory | 183232 kb |
| Host | smart-496c657c-3e3f-440c-a4a7-fe11637f775e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10446318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.10446318 |
| Directory | /workspace/19.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3975933712 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 13812110 ps |
| CPU time | 0.54 seconds |
| Started | Jan 14 01:13:14 PM PST 24 |
| Finished | Jan 14 01:13:15 PM PST 24 |
| Peak memory | 182516 kb |
| Host | smart-a22c4873-3581-42e7-bf95-bff3e2d4e66d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975933712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3975933712 |
| Directory | /workspace/19.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1223183205 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 157837142 ps |
| CPU time | 0.73 seconds |
| Started | Jan 14 01:13:16 PM PST 24 |
| Finished | Jan 14 01:13:18 PM PST 24 |
| Peak memory | 193444 kb |
| Host | smart-b8326216-1e80-4264-a0ef-32e223ea9ce7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223183205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t imer_same_csr_outstanding.1223183205 |
| Directory | /workspace/19.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.823443452 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 430911385 ps |
| CPU time | 2.46 seconds |
| Started | Jan 14 01:13:20 PM PST 24 |
| Finished | Jan 14 01:13:23 PM PST 24 |
| Peak memory | 198056 kb |
| Host | smart-1742c399-01ac-4dd0-9974-acbffc67d22d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823443452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.823443452 |
| Directory | /workspace/19.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2404848369 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 404764984 ps |
| CPU time | 1.35 seconds |
| Started | Jan 14 01:13:16 PM PST 24 |
| Finished | Jan 14 01:13:18 PM PST 24 |
| Peak memory | 195676 kb |
| Host | smart-40823d19-9721-4377-8ce7-b591aaebd7a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404848369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i ntg_err.2404848369 |
| Directory | /workspace/19.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2523582392 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 98653339 ps |
| CPU time | 0.73 seconds |
| Started | Jan 14 01:12:40 PM PST 24 |
| Finished | Jan 14 01:12:41 PM PST 24 |
| Peak memory | 183240 kb |
| Host | smart-0d8a6baf-7d97-437d-b72b-3ff84ebe30d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523582392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia sing.2523582392 |
| Directory | /workspace/2.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2016515705 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 423016372 ps |
| CPU time | 3.14 seconds |
| Started | Jan 14 01:12:45 PM PST 24 |
| Finished | Jan 14 01:12:49 PM PST 24 |
| Peak memory | 192900 kb |
| Host | smart-5980d5bd-3588-47e3-a4a7-2b8c4e2e543e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016515705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_ bash.2016515705 |
| Directory | /workspace/2.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1952874660 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 116229872 ps |
| CPU time | 0.56 seconds |
| Started | Jan 14 01:12:40 PM PST 24 |
| Finished | Jan 14 01:12:42 PM PST 24 |
| Peak memory | 183336 kb |
| Host | smart-cd35b882-c54e-4ae1-91ea-cf8ab6868963 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952874660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r eset.1952874660 |
| Directory | /workspace/2.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2340594706 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 26640884 ps |
| CPU time | 1 seconds |
| Started | Jan 14 01:12:42 PM PST 24 |
| Finished | Jan 14 01:12:45 PM PST 24 |
| Peak memory | 197840 kb |
| Host | smart-aef4da83-5973-4316-8549-29325f6f5e4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340594706 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2340594706 |
| Directory | /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2418748711 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 57914382 ps |
| CPU time | 0.54 seconds |
| Started | Jan 14 01:12:47 PM PST 24 |
| Finished | Jan 14 01:12:48 PM PST 24 |
| Peak memory | 183344 kb |
| Host | smart-6c191486-ccb2-4837-8708-a1eb38674c11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418748711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2418748711 |
| Directory | /workspace/2.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2477976722 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 40911241 ps |
| CPU time | 0.54 seconds |
| Started | Jan 14 01:12:39 PM PST 24 |
| Finished | Jan 14 01:12:41 PM PST 24 |
| Peak memory | 182104 kb |
| Host | smart-03d9af44-077d-4fb9-93d4-d0450fab0fc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477976722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2477976722 |
| Directory | /workspace/2.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.646469351 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 60472133 ps |
| CPU time | 0.72 seconds |
| Started | Jan 14 01:12:40 PM PST 24 |
| Finished | Jan 14 01:12:43 PM PST 24 |
| Peak memory | 192136 kb |
| Host | smart-93d9b1e7-4e12-42ea-b3f6-06d93e2d36d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646469351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_tim er_same_csr_outstanding.646469351 |
| Directory | /workspace/2.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1264203877 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 96416192 ps |
| CPU time | 1.74 seconds |
| Started | Jan 14 01:12:38 PM PST 24 |
| Finished | Jan 14 01:12:42 PM PST 24 |
| Peak memory | 197748 kb |
| Host | smart-c6cb335a-60dc-46a1-a743-94afb84bc8ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264203877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1264203877 |
| Directory | /workspace/2.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3537383458 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 522313901 ps |
| CPU time | 1.28 seconds |
| Started | Jan 14 01:12:36 PM PST 24 |
| Finished | Jan 14 01:12:39 PM PST 24 |
| Peak memory | 183632 kb |
| Host | smart-87f9466b-70cd-4b79-8e62-829b858e06d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537383458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in tg_err.3537383458 |
| Directory | /workspace/2.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.4136995410 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 39480898 ps |
| CPU time | 0.55 seconds |
| Started | Jan 14 01:13:19 PM PST 24 |
| Finished | Jan 14 01:13:21 PM PST 24 |
| Peak memory | 182880 kb |
| Host | smart-2964107e-bc96-4b2f-8bc6-669ea684cada |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136995410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.4136995410 |
| Directory | /workspace/20.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1641372663 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 66087695 ps |
| CPU time | 0.55 seconds |
| Started | Jan 14 01:13:17 PM PST 24 |
| Finished | Jan 14 01:13:19 PM PST 24 |
| Peak memory | 182900 kb |
| Host | smart-d74ab374-5824-4a2d-be34-fa32c4651b5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641372663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1641372663 |
| Directory | /workspace/21.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.4270892316 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 164820180 ps |
| CPU time | 0.54 seconds |
| Started | Jan 14 01:13:17 PM PST 24 |
| Finished | Jan 14 01:13:19 PM PST 24 |
| Peak memory | 182880 kb |
| Host | smart-8483aa55-ff31-46cf-a7b7-7c08b150e56a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270892316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.4270892316 |
| Directory | /workspace/22.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.593233860 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 32052733 ps |
| CPU time | 0.57 seconds |
| Started | Jan 14 01:13:16 PM PST 24 |
| Finished | Jan 14 01:13:18 PM PST 24 |
| Peak memory | 182444 kb |
| Host | smart-866dde20-18b7-4c2d-a6bd-6d83bf944753 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593233860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.593233860 |
| Directory | /workspace/23.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2982862566 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 21626398 ps |
| CPU time | 0.55 seconds |
| Started | Jan 14 01:13:18 PM PST 24 |
| Finished | Jan 14 01:13:20 PM PST 24 |
| Peak memory | 182832 kb |
| Host | smart-10d6af1b-e9e9-4287-94f3-533a0aa8ca26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982862566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2982862566 |
| Directory | /workspace/24.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.4262849218 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 46577592 ps |
| CPU time | 0.55 seconds |
| Started | Jan 14 01:13:16 PM PST 24 |
| Finished | Jan 14 01:13:18 PM PST 24 |
| Peak memory | 182004 kb |
| Host | smart-132996a9-e79d-4f11-930c-a4bcc2fb199a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262849218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.4262849218 |
| Directory | /workspace/25.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3200345882 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 14343189 ps |
| CPU time | 0.56 seconds |
| Started | Jan 14 01:13:15 PM PST 24 |
| Finished | Jan 14 01:13:16 PM PST 24 |
| Peak memory | 182996 kb |
| Host | smart-cdaaccf6-0ffb-4315-b26d-83581ad600a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200345882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.3200345882 |
| Directory | /workspace/26.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3690088469 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 42906230 ps |
| CPU time | 0.59 seconds |
| Started | Jan 14 01:13:17 PM PST 24 |
| Finished | Jan 14 01:13:19 PM PST 24 |
| Peak memory | 182916 kb |
| Host | smart-a70a8d7d-c33b-4315-9e7e-cc06b1f9771d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690088469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3690088469 |
| Directory | /workspace/27.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1893859983 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 48751288 ps |
| CPU time | 0.61 seconds |
| Started | Jan 14 01:13:19 PM PST 24 |
| Finished | Jan 14 01:13:21 PM PST 24 |
| Peak memory | 182916 kb |
| Host | smart-3ca5f77e-4209-4f12-9ec1-702a5d506f00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893859983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1893859983 |
| Directory | /workspace/28.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2598425568 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 31024979 ps |
| CPU time | 0.55 seconds |
| Started | Jan 14 01:13:16 PM PST 24 |
| Finished | Jan 14 01:13:19 PM PST 24 |
| Peak memory | 182064 kb |
| Host | smart-accec844-648f-4f1e-b2ab-37e437848314 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598425568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2598425568 |
| Directory | /workspace/29.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1529494131 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 31226606 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 01:12:49 PM PST 24 |
| Finished | Jan 14 01:12:51 PM PST 24 |
| Peak memory | 192808 kb |
| Host | smart-0ee9eff9-e9e6-49f9-8300-0926e7aa6553 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529494131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia sing.1529494131 |
| Directory | /workspace/3.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.4085240739 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 196237514 ps |
| CPU time | 1.5 seconds |
| Started | Jan 14 01:12:40 PM PST 24 |
| Finished | Jan 14 01:12:44 PM PST 24 |
| Peak memory | 183444 kb |
| Host | smart-906b488e-f97b-43e2-949c-6f1082686f64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085240739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_ bash.4085240739 |
| Directory | /workspace/3.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2175032700 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 51096844 ps |
| CPU time | 0.54 seconds |
| Started | Jan 14 01:12:42 PM PST 24 |
| Finished | Jan 14 01:12:44 PM PST 24 |
| Peak memory | 183176 kb |
| Host | smart-43fe4cbe-525f-4826-b363-3f1bbdfaea68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175032700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r eset.2175032700 |
| Directory | /workspace/3.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3670569679 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 101919861 ps |
| CPU time | 0.79 seconds |
| Started | Jan 14 01:12:42 PM PST 24 |
| Finished | Jan 14 01:12:45 PM PST 24 |
| Peak memory | 196368 kb |
| Host | smart-8b6f623e-2070-4d4b-a2fd-2f15949b43db |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670569679 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.3670569679 |
| Directory | /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1659061450 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 22503071 ps |
| CPU time | 0.55 seconds |
| Started | Jan 14 01:12:42 PM PST 24 |
| Finished | Jan 14 01:12:44 PM PST 24 |
| Peak memory | 182952 kb |
| Host | smart-9639b7ef-cfcb-44a5-9e4f-179b3969808b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659061450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1659061450 |
| Directory | /workspace/3.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1379475952 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 24575339 ps |
| CPU time | 0.64 seconds |
| Started | Jan 14 01:12:41 PM PST 24 |
| Finished | Jan 14 01:12:43 PM PST 24 |
| Peak memory | 191936 kb |
| Host | smart-1bd30795-f783-4962-8e9f-d93f4883b7a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379475952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti mer_same_csr_outstanding.1379475952 |
| Directory | /workspace/3.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2492604555 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 204327139 ps |
| CPU time | 2.8 seconds |
| Started | Jan 14 01:12:44 PM PST 24 |
| Finished | Jan 14 01:12:48 PM PST 24 |
| Peak memory | 198008 kb |
| Host | smart-895434ad-2881-4401-8964-6eed9dd70315 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492604555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2492604555 |
| Directory | /workspace/3.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3555920694 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 269807587 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 01:12:42 PM PST 24 |
| Finished | Jan 14 01:12:44 PM PST 24 |
| Peak memory | 193904 kb |
| Host | smart-a839e8c3-0646-49cd-ad20-3c0ea09bee31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555920694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in tg_err.3555920694 |
| Directory | /workspace/3.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.679154878 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 39347085 ps |
| CPU time | 0.56 seconds |
| Started | Jan 14 01:13:16 PM PST 24 |
| Finished | Jan 14 01:13:17 PM PST 24 |
| Peak memory | 182924 kb |
| Host | smart-28d745ad-f231-43f1-8259-cf04b247483f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679154878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.679154878 |
| Directory | /workspace/30.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.552823762 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 203249748 ps |
| CPU time | 0.57 seconds |
| Started | Jan 14 01:13:21 PM PST 24 |
| Finished | Jan 14 01:13:22 PM PST 24 |
| Peak memory | 182980 kb |
| Host | smart-99385213-503f-42a4-b027-a2c24beede6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552823762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.552823762 |
| Directory | /workspace/31.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.487478495 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 58485225 ps |
| CPU time | 0.59 seconds |
| Started | Jan 14 01:13:25 PM PST 24 |
| Finished | Jan 14 01:13:27 PM PST 24 |
| Peak memory | 182916 kb |
| Host | smart-9784b51c-b824-4a24-93f0-d790138f4710 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487478495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.487478495 |
| Directory | /workspace/32.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3558473103 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 202684741 ps |
| CPU time | 0.57 seconds |
| Started | Jan 14 01:13:25 PM PST 24 |
| Finished | Jan 14 01:13:27 PM PST 24 |
| Peak memory | 182852 kb |
| Host | smart-f8a3f596-c340-4e9b-ad39-7d7ea254a9a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558473103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3558473103 |
| Directory | /workspace/33.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2348144253 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 63845578 ps |
| CPU time | 0.58 seconds |
| Started | Jan 14 01:13:25 PM PST 24 |
| Finished | Jan 14 01:13:28 PM PST 24 |
| Peak memory | 182924 kb |
| Host | smart-f36ca12c-3c35-426e-bff5-d272dcce7d96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348144253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2348144253 |
| Directory | /workspace/34.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.4180796182 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 52605250 ps |
| CPU time | 0.53 seconds |
| Started | Jan 14 01:13:24 PM PST 24 |
| Finished | Jan 14 01:13:26 PM PST 24 |
| Peak memory | 182052 kb |
| Host | smart-391da8ce-47f6-446c-8e62-85e9cad9c53c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180796182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.4180796182 |
| Directory | /workspace/35.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.4098000362 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 47542533 ps |
| CPU time | 0.56 seconds |
| Started | Jan 14 01:13:17 PM PST 24 |
| Finished | Jan 14 01:13:20 PM PST 24 |
| Peak memory | 182928 kb |
| Host | smart-5aab6b92-7451-4fe3-ae3b-24379e8dd016 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098000362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.4098000362 |
| Directory | /workspace/36.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.914320438 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 21646820 ps |
| CPU time | 0.56 seconds |
| Started | Jan 14 01:13:25 PM PST 24 |
| Finished | Jan 14 01:13:27 PM PST 24 |
| Peak memory | 182948 kb |
| Host | smart-13814135-fec4-4483-a255-8aa2aa1d4e83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914320438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.914320438 |
| Directory | /workspace/37.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3301874 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 14087673 ps |
| CPU time | 0.55 seconds |
| Started | Jan 14 01:13:21 PM PST 24 |
| Finished | Jan 14 01:13:22 PM PST 24 |
| Peak memory | 182968 kb |
| Host | smart-3463edda-2402-46a0-9fd7-f71571a509a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3301874 |
| Directory | /workspace/38.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3798864467 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 82868544 ps |
| CPU time | 0.57 seconds |
| Started | Jan 14 01:13:16 PM PST 24 |
| Finished | Jan 14 01:13:17 PM PST 24 |
| Peak memory | 182912 kb |
| Host | smart-8e7709da-e5ac-464e-96bd-894818d8730c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798864467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3798864467 |
| Directory | /workspace/39.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1799162800 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 38309226 ps |
| CPU time | 0.62 seconds |
| Started | Jan 14 01:12:46 PM PST 24 |
| Finished | Jan 14 01:12:47 PM PST 24 |
| Peak memory | 183324 kb |
| Host | smart-94658e05-35d7-4c89-864b-d63b31412e1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799162800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia sing.1799162800 |
| Directory | /workspace/4.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1693685537 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 631020492 ps |
| CPU time | 1.38 seconds |
| Started | Jan 14 01:12:45 PM PST 24 |
| Finished | Jan 14 01:12:48 PM PST 24 |
| Peak memory | 191700 kb |
| Host | smart-3cde1f50-7ab8-43d9-a243-010821060075 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693685537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_ bash.1693685537 |
| Directory | /workspace/4.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2372962734 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 95590532 ps |
| CPU time | 0.6 seconds |
| Started | Jan 14 01:12:42 PM PST 24 |
| Finished | Jan 14 01:12:44 PM PST 24 |
| Peak memory | 183332 kb |
| Host | smart-6c3d295a-f92c-4e46-8567-8cd9175bf8a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372962734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r eset.2372962734 |
| Directory | /workspace/4.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3257059165 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 21246801 ps |
| CPU time | 1.13 seconds |
| Started | Jan 14 01:12:49 PM PST 24 |
| Finished | Jan 14 01:12:51 PM PST 24 |
| Peak memory | 198140 kb |
| Host | smart-b16ace76-059e-44de-aed8-11a84c98905d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257059165 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3257059165 |
| Directory | /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1007002225 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 35553664 ps |
| CPU time | 0.56 seconds |
| Started | Jan 14 01:12:45 PM PST 24 |
| Finished | Jan 14 01:12:47 PM PST 24 |
| Peak memory | 183288 kb |
| Host | smart-21c3555f-341d-4bfd-a12d-26e5bc43eaa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007002225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1007002225 |
| Directory | /workspace/4.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1381592730 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 113450625 ps |
| CPU time | 0.54 seconds |
| Started | Jan 14 01:12:42 PM PST 24 |
| Finished | Jan 14 01:12:44 PM PST 24 |
| Peak memory | 182124 kb |
| Host | smart-bb571354-ce36-4626-98a7-a9e40477db94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381592730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1381592730 |
| Directory | /workspace/4.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.599219357 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 56762099 ps |
| CPU time | 0.64 seconds |
| Started | Jan 14 01:12:43 PM PST 24 |
| Finished | Jan 14 01:12:45 PM PST 24 |
| Peak memory | 192464 kb |
| Host | smart-4410513b-de0b-4272-b8e4-f298f37de63e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599219357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim er_same_csr_outstanding.599219357 |
| Directory | /workspace/4.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.4286217662 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 90356722 ps |
| CPU time | 1.89 seconds |
| Started | Jan 14 01:12:48 PM PST 24 |
| Finished | Jan 14 01:12:51 PM PST 24 |
| Peak memory | 198020 kb |
| Host | smart-61fba84c-900a-4870-bb60-f11f35012f56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286217662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.4286217662 |
| Directory | /workspace/4.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.4210270884 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 47239894 ps |
| CPU time | 0.52 seconds |
| Started | Jan 14 01:13:26 PM PST 24 |
| Finished | Jan 14 01:13:28 PM PST 24 |
| Peak memory | 182084 kb |
| Host | smart-629e6e86-765d-4bd0-a521-6799bf76844b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210270884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.4210270884 |
| Directory | /workspace/40.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2435068170 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 81607163 ps |
| CPU time | 0.53 seconds |
| Started | Jan 14 01:13:18 PM PST 24 |
| Finished | Jan 14 01:13:20 PM PST 24 |
| Peak memory | 182056 kb |
| Host | smart-3cbe531c-ef07-4d2f-b815-d32dd553f6e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435068170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2435068170 |
| Directory | /workspace/41.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.872549263 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 12097302 ps |
| CPU time | 0.56 seconds |
| Started | Jan 14 01:13:22 PM PST 24 |
| Finished | Jan 14 01:13:24 PM PST 24 |
| Peak memory | 182948 kb |
| Host | smart-a0b06091-3339-41fd-925f-65c9e7567289 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872549263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.872549263 |
| Directory | /workspace/42.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2268339312 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 14710290 ps |
| CPU time | 0.58 seconds |
| Started | Jan 14 01:13:23 PM PST 24 |
| Finished | Jan 14 01:13:25 PM PST 24 |
| Peak memory | 182880 kb |
| Host | smart-76ffe068-7eb9-43bf-bca6-d31ae9d37634 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268339312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2268339312 |
| Directory | /workspace/43.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1485981357 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 25828461 ps |
| CPU time | 0.56 seconds |
| Started | Jan 14 01:13:26 PM PST 24 |
| Finished | Jan 14 01:13:28 PM PST 24 |
| Peak memory | 182988 kb |
| Host | smart-6bb029d7-da79-48be-9994-9904b11f58f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485981357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1485981357 |
| Directory | /workspace/44.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.99661194 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 24584305 ps |
| CPU time | 0.57 seconds |
| Started | Jan 14 01:13:21 PM PST 24 |
| Finished | Jan 14 01:13:22 PM PST 24 |
| Peak memory | 182088 kb |
| Host | smart-864512a2-ae48-47d7-927d-0b39a9765358 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99661194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.99661194 |
| Directory | /workspace/45.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3822020620 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 35714136 ps |
| CPU time | 0.56 seconds |
| Started | Jan 14 01:13:26 PM PST 24 |
| Finished | Jan 14 01:13:28 PM PST 24 |
| Peak memory | 182924 kb |
| Host | smart-5f2ed5c2-acf4-4164-a56f-72ad53092dfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822020620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3822020620 |
| Directory | /workspace/46.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1988461734 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 43743109 ps |
| CPU time | 0.54 seconds |
| Started | Jan 14 01:13:24 PM PST 24 |
| Finished | Jan 14 01:13:26 PM PST 24 |
| Peak memory | 182964 kb |
| Host | smart-9718f05f-1398-4f39-bd19-de85aacff9b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988461734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1988461734 |
| Directory | /workspace/47.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3840043176 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 13331252 ps |
| CPU time | 0.55 seconds |
| Started | Jan 14 01:13:27 PM PST 24 |
| Finished | Jan 14 01:13:29 PM PST 24 |
| Peak memory | 182844 kb |
| Host | smart-a8a7a03f-3424-44c9-9e1e-7de1ec893bb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840043176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3840043176 |
| Directory | /workspace/48.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2068901178 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 140177810 ps |
| CPU time | 0.53 seconds |
| Started | Jan 14 01:13:27 PM PST 24 |
| Finished | Jan 14 01:13:29 PM PST 24 |
| Peak memory | 182140 kb |
| Host | smart-7d5d55aa-199e-429c-ac68-2a7801f6251f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068901178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2068901178 |
| Directory | /workspace/49.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3800552225 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 34950490 ps |
| CPU time | 1.6 seconds |
| Started | Jan 14 01:12:53 PM PST 24 |
| Finished | Jan 14 01:12:55 PM PST 24 |
| Peak memory | 198080 kb |
| Host | smart-8e228764-6bc3-4a10-a67a-5b60faf60f95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800552225 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.3800552225 |
| Directory | /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.789566747 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 13732564 ps |
| CPU time | 0.53 seconds |
| Started | Jan 14 01:12:44 PM PST 24 |
| Finished | Jan 14 01:12:46 PM PST 24 |
| Peak memory | 182712 kb |
| Host | smart-939e2025-a77b-434f-abfb-6785c050758b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789566747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.789566747 |
| Directory | /workspace/5.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.636677040 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 28535180 ps |
| CPU time | 0.54 seconds |
| Started | Jan 14 01:12:47 PM PST 24 |
| Finished | Jan 14 01:12:49 PM PST 24 |
| Peak memory | 182964 kb |
| Host | smart-49e208c4-18a9-40b6-88a5-e1613abdfd4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636677040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.636677040 |
| Directory | /workspace/5.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3970162958 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 35207441 ps |
| CPU time | 0.61 seconds |
| Started | Jan 14 01:12:43 PM PST 24 |
| Finished | Jan 14 01:12:45 PM PST 24 |
| Peak memory | 192568 kb |
| Host | smart-bff982bd-326a-4f42-b93b-eda2818808d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970162958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti mer_same_csr_outstanding.3970162958 |
| Directory | /workspace/5.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3432823022 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 86662170 ps |
| CPU time | 1.32 seconds |
| Started | Jan 14 01:12:44 PM PST 24 |
| Finished | Jan 14 01:12:46 PM PST 24 |
| Peak memory | 197956 kb |
| Host | smart-da78b3b3-8ced-4087-8a83-2646bcd1835d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432823022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3432823022 |
| Directory | /workspace/5.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.506354354 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 83701330 ps |
| CPU time | 1.19 seconds |
| Started | Jan 14 01:12:44 PM PST 24 |
| Finished | Jan 14 01:12:46 PM PST 24 |
| Peak memory | 195252 kb |
| Host | smart-5d1bdb04-e6ec-4a80-a8fa-126c54943734 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506354354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int g_err.506354354 |
| Directory | /workspace/5.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3884306826 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 67349922 ps |
| CPU time | 1 seconds |
| Started | Jan 14 01:12:51 PM PST 24 |
| Finished | Jan 14 01:12:53 PM PST 24 |
| Peak memory | 197636 kb |
| Host | smart-bc851aed-105a-4cd3-aa3d-94182836ffe3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884306826 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3884306826 |
| Directory | /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1523153905 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 109396356 ps |
| CPU time | 0.56 seconds |
| Started | Jan 14 01:12:51 PM PST 24 |
| Finished | Jan 14 01:12:52 PM PST 24 |
| Peak memory | 182828 kb |
| Host | smart-0337c0a9-4757-4e1a-b80e-73e7c62ac9dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523153905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1523153905 |
| Directory | /workspace/6.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.4279207939 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 11186645 ps |
| CPU time | 0.53 seconds |
| Started | Jan 14 01:12:52 PM PST 24 |
| Finished | Jan 14 01:12:53 PM PST 24 |
| Peak memory | 182488 kb |
| Host | smart-64fa64ae-9fd0-4cdc-9ba4-ef5293de2f34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279207939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.4279207939 |
| Directory | /workspace/6.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1430569514 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 40516246 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 01:12:50 PM PST 24 |
| Finished | Jan 14 01:12:52 PM PST 24 |
| Peak memory | 192272 kb |
| Host | smart-26ea6b38-9537-49d2-bf80-739947f24b6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430569514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti mer_same_csr_outstanding.1430569514 |
| Directory | /workspace/6.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2949929239 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 590237477 ps |
| CPU time | 1.18 seconds |
| Started | Jan 14 01:12:49 PM PST 24 |
| Finished | Jan 14 01:12:51 PM PST 24 |
| Peak memory | 198020 kb |
| Host | smart-a73d34eb-2669-4ec4-9b73-df6e9e1dfe2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949929239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2949929239 |
| Directory | /workspace/6.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1236118144 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 153451791 ps |
| CPU time | 0.81 seconds |
| Started | Jan 14 01:12:53 PM PST 24 |
| Finished | Jan 14 01:12:55 PM PST 24 |
| Peak memory | 193928 kb |
| Host | smart-a17c8d7b-0add-46eb-aa8d-23467f44ea35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236118144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in tg_err.1236118144 |
| Directory | /workspace/6.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.194850672 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 29571800 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 01:12:53 PM PST 24 |
| Finished | Jan 14 01:12:55 PM PST 24 |
| Peak memory | 197888 kb |
| Host | smart-83793597-655e-48f5-95a6-8078d8d9e6f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194850672 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.194850672 |
| Directory | /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3597264798 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 13738544 ps |
| CPU time | 0.62 seconds |
| Started | Jan 14 01:12:49 PM PST 24 |
| Finished | Jan 14 01:12:50 PM PST 24 |
| Peak memory | 183276 kb |
| Host | smart-1cc85ec5-a3a9-47f3-9dfe-afa6d63f85db |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597264798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3597264798 |
| Directory | /workspace/7.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.237013175 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 11635908 ps |
| CPU time | 0.58 seconds |
| Started | Jan 14 01:12:52 PM PST 24 |
| Finished | Jan 14 01:12:53 PM PST 24 |
| Peak memory | 182876 kb |
| Host | smart-814c1a6a-6ddb-433d-8401-516721c9cf3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237013175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.237013175 |
| Directory | /workspace/7.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1484078679 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 25726397 ps |
| CPU time | 0.66 seconds |
| Started | Jan 14 01:13:04 PM PST 24 |
| Finished | Jan 14 01:13:06 PM PST 24 |
| Peak memory | 192564 kb |
| Host | smart-3dffba8c-c25b-484e-9294-0c4e0b233915 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484078679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti mer_same_csr_outstanding.1484078679 |
| Directory | /workspace/7.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.957199672 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 378451072 ps |
| CPU time | 3.24 seconds |
| Started | Jan 14 01:12:54 PM PST 24 |
| Finished | Jan 14 01:12:59 PM PST 24 |
| Peak memory | 197972 kb |
| Host | smart-8b06bf4d-e50c-4abb-b7f7-b0c9ba86f51c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957199672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.957199672 |
| Directory | /workspace/7.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2715696920 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 42944938 ps |
| CPU time | 0.83 seconds |
| Started | Jan 14 01:12:53 PM PST 24 |
| Finished | Jan 14 01:12:55 PM PST 24 |
| Peak memory | 194012 kb |
| Host | smart-505b478e-7f5a-41ae-a93e-669439753468 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715696920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in tg_err.2715696920 |
| Directory | /workspace/7.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3074060074 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 37772031 ps |
| CPU time | 0.73 seconds |
| Started | Jan 14 01:13:05 PM PST 24 |
| Finished | Jan 14 01:13:09 PM PST 24 |
| Peak memory | 195460 kb |
| Host | smart-42ca2fb0-e67f-4537-bf82-07ecb451ec72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074060074 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3074060074 |
| Directory | /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2432512251 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 18638311 ps |
| CPU time | 0.56 seconds |
| Started | Jan 14 01:12:49 PM PST 24 |
| Finished | Jan 14 01:12:50 PM PST 24 |
| Peak memory | 183268 kb |
| Host | smart-371e9687-2e46-400c-8396-4082fa46e10a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432512251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2432512251 |
| Directory | /workspace/8.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2989312888 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 65460234 ps |
| CPU time | 0.54 seconds |
| Started | Jan 14 01:13:04 PM PST 24 |
| Finished | Jan 14 01:13:06 PM PST 24 |
| Peak memory | 182888 kb |
| Host | smart-5d8c70fe-7248-49e1-8f0b-0b140197c412 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989312888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2989312888 |
| Directory | /workspace/8.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.4195545391 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 98840692 ps |
| CPU time | 0.71 seconds |
| Started | Jan 14 01:13:04 PM PST 24 |
| Finished | Jan 14 01:13:07 PM PST 24 |
| Peak memory | 193704 kb |
| Host | smart-c14cf4fc-285a-428b-92a9-680f175deedb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195545391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti mer_same_csr_outstanding.4195545391 |
| Directory | /workspace/8.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.214603915 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 843419992 ps |
| CPU time | 3.3 seconds |
| Started | Jan 14 01:12:54 PM PST 24 |
| Finished | Jan 14 01:12:59 PM PST 24 |
| Peak memory | 197968 kb |
| Host | smart-a624bad1-d4ef-41af-bf5a-effaf0885de3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214603915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.214603915 |
| Directory | /workspace/8.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2896070151 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 220796289 ps |
| CPU time | 1.43 seconds |
| Started | Jan 14 01:13:05 PM PST 24 |
| Finished | Jan 14 01:13:10 PM PST 24 |
| Peak memory | 183492 kb |
| Host | smart-eecaa49a-c9e3-48ef-a942-c01ae180c71b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896070151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in tg_err.2896070151 |
| Directory | /workspace/8.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.23487538 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 26402836 ps |
| CPU time | 0.83 seconds |
| Started | Jan 14 01:12:51 PM PST 24 |
| Finished | Jan 14 01:12:53 PM PST 24 |
| Peak memory | 195160 kb |
| Host | smart-d8f33250-3cb2-4c98-9e13-ef357e12418c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23487538 -assert nopostproc +UVM_TESTNAME=r v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.23487538 |
| Directory | /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3754890077 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 18615723 ps |
| CPU time | 0.58 seconds |
| Started | Jan 14 01:12:48 PM PST 24 |
| Finished | Jan 14 01:12:50 PM PST 24 |
| Peak memory | 183276 kb |
| Host | smart-567b0d32-69a4-4f0a-b4e0-030ddcbae729 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754890077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3754890077 |
| Directory | /workspace/9.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1671707973 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 31221094 ps |
| CPU time | 0.54 seconds |
| Started | Jan 14 01:13:04 PM PST 24 |
| Finished | Jan 14 01:13:06 PM PST 24 |
| Peak memory | 182824 kb |
| Host | smart-b0954152-7450-4f2f-b02b-b4674790057c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671707973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1671707973 |
| Directory | /workspace/9.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1515385578 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 17346487 ps |
| CPU time | 0.65 seconds |
| Started | Jan 14 01:13:04 PM PST 24 |
| Finished | Jan 14 01:13:07 PM PST 24 |
| Peak memory | 192024 kb |
| Host | smart-938fc647-8623-46fc-b466-f02f0133a9f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515385578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti mer_same_csr_outstanding.1515385578 |
| Directory | /workspace/9.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.4239430676 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 133230340 ps |
| CPU time | 1.33 seconds |
| Started | Jan 14 01:12:49 PM PST 24 |
| Finished | Jan 14 01:12:51 PM PST 24 |
| Peak memory | 198012 kb |
| Host | smart-ded3cf33-e20e-404d-9950-4413fed8b880 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239430676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.4239430676 |
| Directory | /workspace/9.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3980772113 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 494620392 ps |
| CPU time | 1.32 seconds |
| Started | Jan 14 01:12:56 PM PST 24 |
| Finished | Jan 14 01:12:59 PM PST 24 |
| Peak memory | 183428 kb |
| Host | smart-4e0d1a46-0df4-4f6c-a319-544f84e7ef29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980772113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in tg_err.3980772113 |
| Directory | /workspace/9.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.rv_timer_disabled.3680449466 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 127290425548 ps |
| CPU time | 97.56 seconds |
| Started | Jan 14 01:23:59 PM PST 24 |
| Finished | Jan 14 01:25:37 PM PST 24 |
| Peak memory | 182924 kb |
| Host | smart-cec45ffb-5785-4e94-8741-ca3f6238665d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3680449466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3680449466 |
| Directory | /workspace/0.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.2886367384 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 31879203468 ps |
| CPU time | 172.06 seconds |
| Started | Jan 14 01:23:52 PM PST 24 |
| Finished | Jan 14 01:26:45 PM PST 24 |
| Peak memory | 197704 kb |
| Host | smart-cdc331da-c705-41a1-92dc-057de76e6372 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886367384 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.2886367384 |
| Directory | /workspace/0.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.rv_timer_disabled.1014103974 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 66642991142 ps |
| CPU time | 18.11 seconds |
| Started | Jan 14 01:23:59 PM PST 24 |
| Finished | Jan 14 01:24:19 PM PST 24 |
| Peak memory | 182884 kb |
| Host | smart-dac8a76f-9674-4e8e-84f7-c9c5c66b3129 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1014103974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1014103974 |
| Directory | /workspace/1.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/1.rv_timer_random.1044086623 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 2255212299310 ps |
| CPU time | 501.5 seconds |
| Started | Jan 14 01:23:52 PM PST 24 |
| Finished | Jan 14 01:32:14 PM PST 24 |
| Peak memory | 191284 kb |
| Host | smart-9d0add46-3dae-4cfa-bb3e-f2625cdd50bc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044086623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1044086623 |
| Directory | /workspace/1.rv_timer_random/latest |
| Test location | /workspace/coverage/default/1.rv_timer_sec_cm.3748475791 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 40844067 ps |
| CPU time | 0.75 seconds |
| Started | Jan 14 01:23:58 PM PST 24 |
| Finished | Jan 14 01:24:00 PM PST 24 |
| Peak memory | 212804 kb |
| Host | smart-ad5aeea6-2cb6-4a50-9243-69260c65797e |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748475791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3748475791 |
| Directory | /workspace/1.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3579443786 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 31696295506 ps |
| CPU time | 30.21 seconds |
| Started | Jan 14 01:24:21 PM PST 24 |
| Finished | Jan 14 01:24:52 PM PST 24 |
| Peak memory | 183004 kb |
| Host | smart-d2791b6f-18fb-4bca-8ff5-58dab04105ef |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579443786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_cfg_update_on_fly.3579443786 |
| Directory | /workspace/10.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/10.rv_timer_disabled.3017811991 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 269292863588 ps |
| CPU time | 118.05 seconds |
| Started | Jan 14 01:24:17 PM PST 24 |
| Finished | Jan 14 01:26:15 PM PST 24 |
| Peak memory | 182956 kb |
| Host | smart-eadc62ea-4b07-4230-8e80-d5365ff16884 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3017811991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3017811991 |
| Directory | /workspace/10.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/10.rv_timer_random_reset.2234853336 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 15132639 ps |
| CPU time | 0.55 seconds |
| Started | Jan 14 01:24:20 PM PST 24 |
| Finished | Jan 14 01:24:21 PM PST 24 |
| Peak memory | 182308 kb |
| Host | smart-e60eb3cc-4b19-4862-b036-2ce3947dd720 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2234853336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2234853336 |
| Directory | /workspace/10.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/10.rv_timer_stress_all.2641011573 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 1081962471373 ps |
| CPU time | 414.3 seconds |
| Started | Jan 14 01:24:18 PM PST 24 |
| Finished | Jan 14 01:31:13 PM PST 24 |
| Peak memory | 194716 kb |
| Host | smart-108f8a3b-30ed-4a9d-b97f-4a05a2b56b9e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641011573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all .2641011573 |
| Directory | /workspace/10.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.716580922 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 111657699179 ps |
| CPU time | 240.47 seconds |
| Started | Jan 14 01:24:18 PM PST 24 |
| Finished | Jan 14 01:28:19 PM PST 24 |
| Peak memory | 205892 kb |
| Host | smart-8b28ea14-4890-4bf5-8fe2-de7240b8e6b4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716580922 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.716580922 |
| Directory | /workspace/10.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/102.rv_timer_random.2247006004 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 394878345798 ps |
| CPU time | 291.54 seconds |
| Started | Jan 14 01:25:36 PM PST 24 |
| Finished | Jan 14 01:30:28 PM PST 24 |
| Peak memory | 191188 kb |
| Host | smart-d23ce135-7105-4d89-b8a8-53c3f50b00ad |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247006004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2247006004 |
| Directory | /workspace/102.rv_timer_random/latest |
| Test location | /workspace/coverage/default/103.rv_timer_random.1822229262 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 40157851939 ps |
| CPU time | 36.81 seconds |
| Started | Jan 14 01:25:30 PM PST 24 |
| Finished | Jan 14 01:26:07 PM PST 24 |
| Peak memory | 182924 kb |
| Host | smart-24217d18-8607-44dd-902a-bf07583b04c8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822229262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1822229262 |
| Directory | /workspace/103.rv_timer_random/latest |
| Test location | /workspace/coverage/default/104.rv_timer_random.2862816183 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 34887390048 ps |
| CPU time | 53.22 seconds |
| Started | Jan 14 01:25:34 PM PST 24 |
| Finished | Jan 14 01:26:28 PM PST 24 |
| Peak memory | 191148 kb |
| Host | smart-9e133577-fc3d-405b-9404-cf6d24b49943 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862816183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2862816183 |
| Directory | /workspace/104.rv_timer_random/latest |
| Test location | /workspace/coverage/default/105.rv_timer_random.3208866754 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 332663027345 ps |
| CPU time | 745.44 seconds |
| Started | Jan 14 01:25:36 PM PST 24 |
| Finished | Jan 14 01:38:03 PM PST 24 |
| Peak memory | 194036 kb |
| Host | smart-34870d3d-2331-448f-8f9a-86c582fddc8f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208866754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3208866754 |
| Directory | /workspace/105.rv_timer_random/latest |
| Test location | /workspace/coverage/default/108.rv_timer_random.1796245289 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 143271769025 ps |
| CPU time | 285.11 seconds |
| Started | Jan 14 01:25:36 PM PST 24 |
| Finished | Jan 14 01:30:22 PM PST 24 |
| Peak memory | 191156 kb |
| Host | smart-1b502fc0-b842-4f07-a559-9301042261c7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796245289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1796245289 |
| Directory | /workspace/108.rv_timer_random/latest |
| Test location | /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3490074210 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 63558570701 ps |
| CPU time | 33.55 seconds |
| Started | Jan 14 01:24:17 PM PST 24 |
| Finished | Jan 14 01:24:51 PM PST 24 |
| Peak memory | 183000 kb |
| Host | smart-ad49d8e6-516b-481a-b4fa-31d242831b3f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490074210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.3490074210 |
| Directory | /workspace/11.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/11.rv_timer_disabled.202764192 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 140765992931 ps |
| CPU time | 230.62 seconds |
| Started | Jan 14 01:24:19 PM PST 24 |
| Finished | Jan 14 01:28:11 PM PST 24 |
| Peak memory | 182908 kb |
| Host | smart-f6485bf6-34c9-4d00-834f-5816151c507c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=202764192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.202764192 |
| Directory | /workspace/11.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/11.rv_timer_random.3513119643 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 136260689750 ps |
| CPU time | 109.64 seconds |
| Started | Jan 14 01:24:17 PM PST 24 |
| Finished | Jan 14 01:26:08 PM PST 24 |
| Peak memory | 191212 kb |
| Host | smart-6befa051-f7dd-443f-825a-a013021d05b5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513119643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.3513119643 |
| Directory | /workspace/11.rv_timer_random/latest |
| Test location | /workspace/coverage/default/11.rv_timer_random_reset.1080291697 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 903801010 ps |
| CPU time | 2.09 seconds |
| Started | Jan 14 01:24:16 PM PST 24 |
| Finished | Jan 14 01:24:19 PM PST 24 |
| Peak memory | 182900 kb |
| Host | smart-3f345164-0a38-4b38-8855-7cffaed64f37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1080291697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1080291697 |
| Directory | /workspace/11.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/11.rv_timer_stress_all.2305347582 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 658039377902 ps |
| CPU time | 157.16 seconds |
| Started | Jan 14 01:24:17 PM PST 24 |
| Finished | Jan 14 01:26:55 PM PST 24 |
| Peak memory | 182964 kb |
| Host | smart-2b89e2c2-5a0a-41fa-adcb-ba338c740b44 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305347582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all .2305347582 |
| Directory | /workspace/11.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/110.rv_timer_random.3961053803 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 259125732139 ps |
| CPU time | 259.86 seconds |
| Started | Jan 14 01:25:32 PM PST 24 |
| Finished | Jan 14 01:29:52 PM PST 24 |
| Peak memory | 190980 kb |
| Host | smart-94ae96b8-95b8-4b97-9295-7cb41ab52be0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961053803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3961053803 |
| Directory | /workspace/110.rv_timer_random/latest |
| Test location | /workspace/coverage/default/111.rv_timer_random.621092448 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 71131677224 ps |
| CPU time | 175.78 seconds |
| Started | Jan 14 01:25:30 PM PST 24 |
| Finished | Jan 14 01:28:26 PM PST 24 |
| Peak memory | 182900 kb |
| Host | smart-1fead773-5210-4327-8e6e-711b9e6b4513 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621092448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.621092448 |
| Directory | /workspace/111.rv_timer_random/latest |
| Test location | /workspace/coverage/default/113.rv_timer_random.1256846481 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 109526877072 ps |
| CPU time | 674.85 seconds |
| Started | Jan 14 01:25:36 PM PST 24 |
| Finished | Jan 14 01:36:52 PM PST 24 |
| Peak memory | 191152 kb |
| Host | smart-885e4957-3f27-4cf9-99c2-d302d84cf4c0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256846481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1256846481 |
| Directory | /workspace/113.rv_timer_random/latest |
| Test location | /workspace/coverage/default/115.rv_timer_random.1274535256 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 413009901213 ps |
| CPU time | 136.74 seconds |
| Started | Jan 14 01:25:38 PM PST 24 |
| Finished | Jan 14 01:27:55 PM PST 24 |
| Peak memory | 193668 kb |
| Host | smart-59ba953f-68f3-4c81-a902-7ea8c18125e3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274535256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1274535256 |
| Directory | /workspace/115.rv_timer_random/latest |
| Test location | /workspace/coverage/default/117.rv_timer_random.1441197627 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 35295704052 ps |
| CPU time | 78.73 seconds |
| Started | Jan 14 01:25:42 PM PST 24 |
| Finished | Jan 14 01:27:01 PM PST 24 |
| Peak memory | 193808 kb |
| Host | smart-fee47021-4e43-4b8f-8552-ebb258e905c2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441197627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1441197627 |
| Directory | /workspace/117.rv_timer_random/latest |
| Test location | /workspace/coverage/default/118.rv_timer_random.3821023392 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 871120806047 ps |
| CPU time | 421.23 seconds |
| Started | Jan 14 01:25:38 PM PST 24 |
| Finished | Jan 14 01:32:40 PM PST 24 |
| Peak memory | 191088 kb |
| Host | smart-3e3de740-9b4a-4813-ba26-1c1a72165832 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821023392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3821023392 |
| Directory | /workspace/118.rv_timer_random/latest |
| Test location | /workspace/coverage/default/119.rv_timer_random.1571211066 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 107714360763 ps |
| CPU time | 160.22 seconds |
| Started | Jan 14 01:25:37 PM PST 24 |
| Finished | Jan 14 01:28:18 PM PST 24 |
| Peak memory | 191240 kb |
| Host | smart-a4266367-e139-48d3-850c-9a6696c08a22 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571211066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1571211066 |
| Directory | /workspace/119.rv_timer_random/latest |
| Test location | /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3418915900 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 7982245795648 ps |
| CPU time | 1953 seconds |
| Started | Jan 14 01:24:17 PM PST 24 |
| Finished | Jan 14 01:56:51 PM PST 24 |
| Peak memory | 182884 kb |
| Host | smart-75ef565a-30f1-44e5-b6c7-446e3a688b22 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418915900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_cfg_update_on_fly.3418915900 |
| Directory | /workspace/12.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/12.rv_timer_disabled.2763902854 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 193458543568 ps |
| CPU time | 85.79 seconds |
| Started | Jan 14 01:24:17 PM PST 24 |
| Finished | Jan 14 01:25:44 PM PST 24 |
| Peak memory | 182928 kb |
| Host | smart-99c0012e-ca67-40f0-a68e-8b68ac02ea4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2763902854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.2763902854 |
| Directory | /workspace/12.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/12.rv_timer_random.939995891 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 518951838319 ps |
| CPU time | 368.89 seconds |
| Started | Jan 14 01:24:17 PM PST 24 |
| Finished | Jan 14 01:30:27 PM PST 24 |
| Peak memory | 191140 kb |
| Host | smart-5c16d99c-3c9c-42be-aa72-b632ace0f596 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939995891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.939995891 |
| Directory | /workspace/12.rv_timer_random/latest |
| Test location | /workspace/coverage/default/12.rv_timer_random_reset.2469477505 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 173932332685 ps |
| CPU time | 87.73 seconds |
| Started | Jan 14 01:24:17 PM PST 24 |
| Finished | Jan 14 01:25:45 PM PST 24 |
| Peak memory | 182932 kb |
| Host | smart-144eb014-f0fb-493d-afcc-3a4d01bd4460 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2469477505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2469477505 |
| Directory | /workspace/12.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.535613355 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 141134086824 ps |
| CPU time | 1002.96 seconds |
| Started | Jan 14 01:24:26 PM PST 24 |
| Finished | Jan 14 01:41:09 PM PST 24 |
| Peak memory | 210420 kb |
| Host | smart-fd446f65-7baf-4d63-8f24-54064b5e5a49 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535613355 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.535613355 |
| Directory | /workspace/12.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/121.rv_timer_random.1719799761 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 175852722301 ps |
| CPU time | 155.75 seconds |
| Started | Jan 14 01:25:44 PM PST 24 |
| Finished | Jan 14 01:28:20 PM PST 24 |
| Peak memory | 193728 kb |
| Host | smart-417b5de9-be63-4a88-ac21-94bad2431da8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719799761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1719799761 |
| Directory | /workspace/121.rv_timer_random/latest |
| Test location | /workspace/coverage/default/122.rv_timer_random.3836377906 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 186644616872 ps |
| CPU time | 99.14 seconds |
| Started | Jan 14 01:25:40 PM PST 24 |
| Finished | Jan 14 01:27:20 PM PST 24 |
| Peak memory | 191164 kb |
| Host | smart-02211dad-7d40-45ba-bf94-f3105fb1ece5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836377906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3836377906 |
| Directory | /workspace/122.rv_timer_random/latest |
| Test location | /workspace/coverage/default/125.rv_timer_random.1470148321 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 176499479981 ps |
| CPU time | 517.96 seconds |
| Started | Jan 14 01:25:39 PM PST 24 |
| Finished | Jan 14 01:34:18 PM PST 24 |
| Peak memory | 191188 kb |
| Host | smart-f8196597-f4d4-4216-9357-1ffebeed936c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470148321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1470148321 |
| Directory | /workspace/125.rv_timer_random/latest |
| Test location | /workspace/coverage/default/126.rv_timer_random.1832217658 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 123523104217 ps |
| CPU time | 173.31 seconds |
| Started | Jan 14 01:25:39 PM PST 24 |
| Finished | Jan 14 01:28:33 PM PST 24 |
| Peak memory | 182988 kb |
| Host | smart-a3f05088-591b-4e50-9afa-4a8386ff048d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832217658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1832217658 |
| Directory | /workspace/126.rv_timer_random/latest |
| Test location | /workspace/coverage/default/127.rv_timer_random.1823932676 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 139023341248 ps |
| CPU time | 236.91 seconds |
| Started | Jan 14 01:25:37 PM PST 24 |
| Finished | Jan 14 01:29:35 PM PST 24 |
| Peak memory | 193360 kb |
| Host | smart-2d7b3933-ff3f-4817-8c87-354e3de2a007 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823932676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1823932676 |
| Directory | /workspace/127.rv_timer_random/latest |
| Test location | /workspace/coverage/default/128.rv_timer_random.2071866832 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 177452492225 ps |
| CPU time | 73.56 seconds |
| Started | Jan 14 01:25:43 PM PST 24 |
| Finished | Jan 14 01:26:57 PM PST 24 |
| Peak memory | 182948 kb |
| Host | smart-673c7f03-2489-4c47-a28f-1af9a4d02f4a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071866832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2071866832 |
| Directory | /workspace/128.rv_timer_random/latest |
| Test location | /workspace/coverage/default/129.rv_timer_random.685811255 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 246256945148 ps |
| CPU time | 245.28 seconds |
| Started | Jan 14 01:25:39 PM PST 24 |
| Finished | Jan 14 01:29:45 PM PST 24 |
| Peak memory | 191200 kb |
| Host | smart-78ff5b1a-8524-4e6b-bfad-4bd021061172 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685811255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.685811255 |
| Directory | /workspace/129.rv_timer_random/latest |
| Test location | /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.291431703 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 290244611906 ps |
| CPU time | 249.59 seconds |
| Started | Jan 14 01:24:24 PM PST 24 |
| Finished | Jan 14 01:28:34 PM PST 24 |
| Peak memory | 182884 kb |
| Host | smart-e312ce22-79c4-457e-ba67-1b82d214876a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291431703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.rv_timer_cfg_update_on_fly.291431703 |
| Directory | /workspace/13.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/13.rv_timer_disabled.1167563728 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 184105575732 ps |
| CPU time | 290.32 seconds |
| Started | Jan 14 01:24:19 PM PST 24 |
| Finished | Jan 14 01:29:10 PM PST 24 |
| Peak memory | 183004 kb |
| Host | smart-0242375c-6c8f-4271-839b-db4137ac5aa0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1167563728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1167563728 |
| Directory | /workspace/13.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/13.rv_timer_random.2207926816 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 74662723309 ps |
| CPU time | 121.1 seconds |
| Started | Jan 14 01:24:17 PM PST 24 |
| Finished | Jan 14 01:26:19 PM PST 24 |
| Peak memory | 191216 kb |
| Host | smart-5bbcb86c-6a41-4a77-8d32-5c703c6e3e26 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207926816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2207926816 |
| Directory | /workspace/13.rv_timer_random/latest |
| Test location | /workspace/coverage/default/13.rv_timer_random_reset.456253675 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 242438860102 ps |
| CPU time | 140.06 seconds |
| Started | Jan 14 01:24:20 PM PST 24 |
| Finished | Jan 14 01:26:41 PM PST 24 |
| Peak memory | 191204 kb |
| Host | smart-27c98e18-7a35-4527-9aa6-945458a9b1b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=456253675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.456253675 |
| Directory | /workspace/13.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/13.rv_timer_stress_all.364061037 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 84817151 ps |
| CPU time | 0.67 seconds |
| Started | Jan 14 01:24:29 PM PST 24 |
| Finished | Jan 14 01:24:31 PM PST 24 |
| Peak memory | 182616 kb |
| Host | smart-b8028493-6068-4dd4-a405-6dd5694fc680 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364061037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all. 364061037 |
| Directory | /workspace/13.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.30975845 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 299592346108 ps |
| CPU time | 822.71 seconds |
| Started | Jan 14 01:24:22 PM PST 24 |
| Finished | Jan 14 01:38:05 PM PST 24 |
| Peak memory | 208968 kb |
| Host | smart-dbe2c3e0-425b-4cd0-aaa7-5944215eeba2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30975845 -assert nopos tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.30975845 |
| Directory | /workspace/13.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/131.rv_timer_random.1391215552 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 134689634542 ps |
| CPU time | 118.28 seconds |
| Started | Jan 14 01:25:51 PM PST 24 |
| Finished | Jan 14 01:27:50 PM PST 24 |
| Peak memory | 194316 kb |
| Host | smart-162f4e63-2bd9-4747-91c2-ccaa8e277528 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391215552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1391215552 |
| Directory | /workspace/131.rv_timer_random/latest |
| Test location | /workspace/coverage/default/133.rv_timer_random.662470878 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 450457549891 ps |
| CPU time | 621.46 seconds |
| Started | Jan 14 01:25:47 PM PST 24 |
| Finished | Jan 14 01:36:10 PM PST 24 |
| Peak memory | 191072 kb |
| Host | smart-26c81641-3f8c-4556-8b3d-466775f07d60 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662470878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.662470878 |
| Directory | /workspace/133.rv_timer_random/latest |
| Test location | /workspace/coverage/default/134.rv_timer_random.1248261847 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 203879590115 ps |
| CPU time | 159.36 seconds |
| Started | Jan 14 01:25:49 PM PST 24 |
| Finished | Jan 14 01:28:29 PM PST 24 |
| Peak memory | 191152 kb |
| Host | smart-c3aba748-0a30-478f-8106-2c2cc44af350 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248261847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1248261847 |
| Directory | /workspace/134.rv_timer_random/latest |
| Test location | /workspace/coverage/default/135.rv_timer_random.594712346 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 46614457880 ps |
| CPU time | 70.56 seconds |
| Started | Jan 14 01:25:51 PM PST 24 |
| Finished | Jan 14 01:27:02 PM PST 24 |
| Peak memory | 182652 kb |
| Host | smart-e38a44f6-9af0-4d73-a966-b9f8e2794a12 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594712346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.594712346 |
| Directory | /workspace/135.rv_timer_random/latest |
| Test location | /workspace/coverage/default/136.rv_timer_random.2529042040 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 42726886543 ps |
| CPU time | 74.61 seconds |
| Started | Jan 14 01:25:48 PM PST 24 |
| Finished | Jan 14 01:27:03 PM PST 24 |
| Peak memory | 182928 kb |
| Host | smart-2d05e55a-88db-401b-8e7d-6ce38f2a3d65 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529042040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2529042040 |
| Directory | /workspace/136.rv_timer_random/latest |
| Test location | /workspace/coverage/default/137.rv_timer_random.2722265023 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 955052293457 ps |
| CPU time | 508.28 seconds |
| Started | Jan 14 01:25:53 PM PST 24 |
| Finished | Jan 14 01:34:22 PM PST 24 |
| Peak memory | 191208 kb |
| Host | smart-3d36631d-700b-412f-9aed-13e45b4c69e2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722265023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2722265023 |
| Directory | /workspace/137.rv_timer_random/latest |
| Test location | /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.1925180842 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 134307932750 ps |
| CPU time | 200.52 seconds |
| Started | Jan 14 01:24:30 PM PST 24 |
| Finished | Jan 14 01:27:51 PM PST 24 |
| Peak memory | 182904 kb |
| Host | smart-fe841781-ceae-4feb-b2da-536ce177e24d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925180842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.1925180842 |
| Directory | /workspace/14.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/14.rv_timer_disabled.90696738 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 140780187348 ps |
| CPU time | 67.49 seconds |
| Started | Jan 14 01:24:23 PM PST 24 |
| Finished | Jan 14 01:25:31 PM PST 24 |
| Peak memory | 182996 kb |
| Host | smart-a5211fcf-7184-4763-a6c3-c807ba9563c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=90696738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.90696738 |
| Directory | /workspace/14.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/14.rv_timer_random_reset.1251199823 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 233025037644 ps |
| CPU time | 210.5 seconds |
| Started | Jan 14 01:24:34 PM PST 24 |
| Finished | Jan 14 01:28:06 PM PST 24 |
| Peak memory | 193808 kb |
| Host | smart-b775c079-ef85-4871-b4db-eb41559be522 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1251199823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1251199823 |
| Directory | /workspace/14.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.2076441080 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 34216310474 ps |
| CPU time | 265.66 seconds |
| Started | Jan 14 01:24:36 PM PST 24 |
| Finished | Jan 14 01:29:08 PM PST 24 |
| Peak memory | 206100 kb |
| Host | smart-457e2220-8392-46ba-acc9-6dadfe69d9ec |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076441080 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.2076441080 |
| Directory | /workspace/14.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/140.rv_timer_random.4182836959 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 121121245850 ps |
| CPU time | 53.01 seconds |
| Started | Jan 14 01:25:51 PM PST 24 |
| Finished | Jan 14 01:26:44 PM PST 24 |
| Peak memory | 193672 kb |
| Host | smart-3d372caa-e1b9-42e6-832b-18f9aba55913 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182836959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.4182836959 |
| Directory | /workspace/140.rv_timer_random/latest |
| Test location | /workspace/coverage/default/141.rv_timer_random.3144775627 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 37055540752 ps |
| CPU time | 68.07 seconds |
| Started | Jan 14 01:25:54 PM PST 24 |
| Finished | Jan 14 01:27:03 PM PST 24 |
| Peak memory | 191032 kb |
| Host | smart-9f78a0b5-6e84-4a82-9e34-99964652b038 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144775627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3144775627 |
| Directory | /workspace/141.rv_timer_random/latest |
| Test location | /workspace/coverage/default/143.rv_timer_random.1049977394 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 81783473653 ps |
| CPU time | 391.78 seconds |
| Started | Jan 14 01:25:54 PM PST 24 |
| Finished | Jan 14 01:32:26 PM PST 24 |
| Peak memory | 191172 kb |
| Host | smart-a2185c12-b3e8-4b54-88cf-7c0a86d5373b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049977394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1049977394 |
| Directory | /workspace/143.rv_timer_random/latest |
| Test location | /workspace/coverage/default/144.rv_timer_random.1757081940 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 299689761681 ps |
| CPU time | 175.28 seconds |
| Started | Jan 14 01:25:54 PM PST 24 |
| Finished | Jan 14 01:28:50 PM PST 24 |
| Peak memory | 191284 kb |
| Host | smart-48719c5e-fb00-4e4a-93c6-1e1bed30ac97 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757081940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1757081940 |
| Directory | /workspace/144.rv_timer_random/latest |
| Test location | /workspace/coverage/default/146.rv_timer_random.3181400082 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 25050249849 ps |
| CPU time | 41.56 seconds |
| Started | Jan 14 01:25:54 PM PST 24 |
| Finished | Jan 14 01:26:36 PM PST 24 |
| Peak memory | 182972 kb |
| Host | smart-5a4c2af0-1fec-4be7-8013-d8616ec797ad |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181400082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3181400082 |
| Directory | /workspace/146.rv_timer_random/latest |
| Test location | /workspace/coverage/default/147.rv_timer_random.356936124 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 1543715001830 ps |
| CPU time | 578.56 seconds |
| Started | Jan 14 01:25:57 PM PST 24 |
| Finished | Jan 14 01:35:36 PM PST 24 |
| Peak memory | 191256 kb |
| Host | smart-dfd237b6-b6c9-43a5-80c0-24ecab663cfa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356936124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.356936124 |
| Directory | /workspace/147.rv_timer_random/latest |
| Test location | /workspace/coverage/default/148.rv_timer_random.1573705788 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 153789177120 ps |
| CPU time | 459.72 seconds |
| Started | Jan 14 01:25:53 PM PST 24 |
| Finished | Jan 14 01:33:33 PM PST 24 |
| Peak memory | 191020 kb |
| Host | smart-d86c08ff-6496-4051-9f0b-8c046c19001a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573705788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1573705788 |
| Directory | /workspace/148.rv_timer_random/latest |
| Test location | /workspace/coverage/default/149.rv_timer_random.3512687543 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 222909947586 ps |
| CPU time | 1244.43 seconds |
| Started | Jan 14 01:25:58 PM PST 24 |
| Finished | Jan 14 01:46:43 PM PST 24 |
| Peak memory | 182820 kb |
| Host | smart-ac450853-0d66-45b3-8047-9b1417e9d41c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512687543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3512687543 |
| Directory | /workspace/149.rv_timer_random/latest |
| Test location | /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.3721802814 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 954162068 ps |
| CPU time | 2.12 seconds |
| Started | Jan 14 01:24:33 PM PST 24 |
| Finished | Jan 14 01:24:35 PM PST 24 |
| Peak memory | 182568 kb |
| Host | smart-b4cb9d5d-5684-4d31-ac46-29f7be1d45ef |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721802814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.3721802814 |
| Directory | /workspace/15.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/15.rv_timer_disabled.3994282332 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 858104466158 ps |
| CPU time | 369.76 seconds |
| Started | Jan 14 01:24:37 PM PST 24 |
| Finished | Jan 14 01:30:52 PM PST 24 |
| Peak memory | 182924 kb |
| Host | smart-c62212d3-5ca2-4584-9554-22522683f5e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3994282332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3994282332 |
| Directory | /workspace/15.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/15.rv_timer_random_reset.2300509375 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 104804272863 ps |
| CPU time | 150.35 seconds |
| Started | Jan 14 01:24:32 PM PST 24 |
| Finished | Jan 14 01:27:03 PM PST 24 |
| Peak memory | 182932 kb |
| Host | smart-6165e5d9-c8cd-4e71-b207-3af124d6bd36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2300509375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.2300509375 |
| Directory | /workspace/15.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.2768513222 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 142296069367 ps |
| CPU time | 583.92 seconds |
| Started | Jan 14 01:24:25 PM PST 24 |
| Finished | Jan 14 01:34:10 PM PST 24 |
| Peak memory | 197464 kb |
| Host | smart-9a12c8bd-87e4-4fa7-9410-bc6bac294bbc |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768513222 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.2768513222 |
| Directory | /workspace/15.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/150.rv_timer_random.954000126 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 548809392544 ps |
| CPU time | 276.76 seconds |
| Started | Jan 14 01:25:57 PM PST 24 |
| Finished | Jan 14 01:30:35 PM PST 24 |
| Peak memory | 191112 kb |
| Host | smart-d66d76d2-1bcb-401c-ab5f-0e7eb68a126c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954000126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.954000126 |
| Directory | /workspace/150.rv_timer_random/latest |
| Test location | /workspace/coverage/default/151.rv_timer_random.955180919 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 329626080075 ps |
| CPU time | 279.46 seconds |
| Started | Jan 14 01:26:03 PM PST 24 |
| Finished | Jan 14 01:30:44 PM PST 24 |
| Peak memory | 191164 kb |
| Host | smart-ff851ce2-d6e6-4c38-b7c5-4e8b44a2ff53 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955180919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.955180919 |
| Directory | /workspace/151.rv_timer_random/latest |
| Test location | /workspace/coverage/default/152.rv_timer_random.2125742344 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 1536492076560 ps |
| CPU time | 700.76 seconds |
| Started | Jan 14 01:26:04 PM PST 24 |
| Finished | Jan 14 01:37:45 PM PST 24 |
| Peak memory | 191152 kb |
| Host | smart-49aa21b1-3c69-40e7-bba3-065ee98caf9a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125742344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2125742344 |
| Directory | /workspace/152.rv_timer_random/latest |
| Test location | /workspace/coverage/default/154.rv_timer_random.3225509999 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 97521453221 ps |
| CPU time | 160.02 seconds |
| Started | Jan 14 01:25:57 PM PST 24 |
| Finished | Jan 14 01:28:38 PM PST 24 |
| Peak memory | 191092 kb |
| Host | smart-ceb326e5-baed-4517-874d-2ae1011b72e3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225509999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3225509999 |
| Directory | /workspace/154.rv_timer_random/latest |
| Test location | /workspace/coverage/default/155.rv_timer_random.3563036404 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 51416008885 ps |
| CPU time | 114.38 seconds |
| Started | Jan 14 01:25:57 PM PST 24 |
| Finished | Jan 14 01:27:52 PM PST 24 |
| Peak memory | 191088 kb |
| Host | smart-e9b53216-aa06-4843-8375-91d182e80b7c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563036404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3563036404 |
| Directory | /workspace/155.rv_timer_random/latest |
| Test location | /workspace/coverage/default/156.rv_timer_random.1713230207 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 1212033368922 ps |
| CPU time | 549.21 seconds |
| Started | Jan 14 01:26:04 PM PST 24 |
| Finished | Jan 14 01:35:14 PM PST 24 |
| Peak memory | 191188 kb |
| Host | smart-c13279b9-e903-4777-b34a-a8cb17038296 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713230207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1713230207 |
| Directory | /workspace/156.rv_timer_random/latest |
| Test location | /workspace/coverage/default/157.rv_timer_random.692871756 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 180800955710 ps |
| CPU time | 192.07 seconds |
| Started | Jan 14 01:26:08 PM PST 24 |
| Finished | Jan 14 01:29:21 PM PST 24 |
| Peak memory | 191200 kb |
| Host | smart-7a6741d0-8a23-4827-ab9b-8ef38dcdb139 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692871756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.692871756 |
| Directory | /workspace/157.rv_timer_random/latest |
| Test location | /workspace/coverage/default/158.rv_timer_random.1909409998 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 743356569627 ps |
| CPU time | 687.76 seconds |
| Started | Jan 14 01:26:09 PM PST 24 |
| Finished | Jan 14 01:37:37 PM PST 24 |
| Peak memory | 191196 kb |
| Host | smart-29bdcbc4-fbb0-42a8-8ffb-2835058d0250 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909409998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1909409998 |
| Directory | /workspace/158.rv_timer_random/latest |
| Test location | /workspace/coverage/default/16.rv_timer_disabled.1078461202 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 15117861282 ps |
| CPU time | 17.53 seconds |
| Started | Jan 14 01:24:21 PM PST 24 |
| Finished | Jan 14 01:24:39 PM PST 24 |
| Peak memory | 182976 kb |
| Host | smart-e694bd33-3f31-402f-a873-ddb89392f708 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1078461202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1078461202 |
| Directory | /workspace/16.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/16.rv_timer_random.268834329 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 113687736060 ps |
| CPU time | 178.85 seconds |
| Started | Jan 14 01:24:24 PM PST 24 |
| Finished | Jan 14 01:27:24 PM PST 24 |
| Peak memory | 191168 kb |
| Host | smart-9d83547c-b1b7-49db-9929-4201a77e5483 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268834329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.268834329 |
| Directory | /workspace/16.rv_timer_random/latest |
| Test location | /workspace/coverage/default/16.rv_timer_random_reset.3818518142 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 35330372111 ps |
| CPU time | 63.67 seconds |
| Started | Jan 14 01:24:19 PM PST 24 |
| Finished | Jan 14 01:25:23 PM PST 24 |
| Peak memory | 191124 kb |
| Host | smart-88d55244-a693-4ed9-88f8-b738935055b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3818518142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.3818518142 |
| Directory | /workspace/16.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/16.rv_timer_stress_all.1425093239 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 2028271383442 ps |
| CPU time | 2371.22 seconds |
| Started | Jan 14 01:24:35 PM PST 24 |
| Finished | Jan 14 02:04:08 PM PST 24 |
| Peak memory | 190972 kb |
| Host | smart-49cf5001-6173-4b58-81cf-b39357c74d5d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425093239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all .1425093239 |
| Directory | /workspace/16.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.2921235253 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 25743523890 ps |
| CPU time | 225.79 seconds |
| Started | Jan 14 01:24:21 PM PST 24 |
| Finished | Jan 14 01:28:08 PM PST 24 |
| Peak memory | 197676 kb |
| Host | smart-9f5a849a-d10c-4744-a9c0-53582e215cc7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921235253 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.2921235253 |
| Directory | /workspace/16.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/160.rv_timer_random.1703088667 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 83392058990 ps |
| CPU time | 192.31 seconds |
| Started | Jan 14 01:26:09 PM PST 24 |
| Finished | Jan 14 01:29:22 PM PST 24 |
| Peak memory | 182992 kb |
| Host | smart-0bf522ab-81f2-4bbc-b9ee-0cee851fc6aa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703088667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1703088667 |
| Directory | /workspace/160.rv_timer_random/latest |
| Test location | /workspace/coverage/default/161.rv_timer_random.3336303904 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 255175350044 ps |
| CPU time | 528.43 seconds |
| Started | Jan 14 01:26:10 PM PST 24 |
| Finished | Jan 14 01:35:00 PM PST 24 |
| Peak memory | 182896 kb |
| Host | smart-540a0082-a7de-450c-a765-be599fa6fecc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336303904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3336303904 |
| Directory | /workspace/161.rv_timer_random/latest |
| Test location | /workspace/coverage/default/162.rv_timer_random.2210595670 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 80219447380 ps |
| CPU time | 135.97 seconds |
| Started | Jan 14 01:26:09 PM PST 24 |
| Finished | Jan 14 01:28:26 PM PST 24 |
| Peak memory | 191152 kb |
| Host | smart-cb9c9744-af47-41f2-aa46-8150ba7bc8ba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210595670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2210595670 |
| Directory | /workspace/162.rv_timer_random/latest |
| Test location | /workspace/coverage/default/163.rv_timer_random.139497521 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 167010756175 ps |
| CPU time | 412.28 seconds |
| Started | Jan 14 01:26:14 PM PST 24 |
| Finished | Jan 14 01:33:07 PM PST 24 |
| Peak memory | 182968 kb |
| Host | smart-4329933a-c515-41ca-9e20-c043d484be89 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139497521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.139497521 |
| Directory | /workspace/163.rv_timer_random/latest |
| Test location | /workspace/coverage/default/164.rv_timer_random.820581718 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 132253333990 ps |
| CPU time | 282.58 seconds |
| Started | Jan 14 01:26:17 PM PST 24 |
| Finished | Jan 14 01:31:00 PM PST 24 |
| Peak memory | 191216 kb |
| Host | smart-9756758c-73d1-475d-a63d-b21df74022b0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820581718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.820581718 |
| Directory | /workspace/164.rv_timer_random/latest |
| Test location | /workspace/coverage/default/165.rv_timer_random.3378605949 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 293049154403 ps |
| CPU time | 127.37 seconds |
| Started | Jan 14 01:26:17 PM PST 24 |
| Finished | Jan 14 01:28:25 PM PST 24 |
| Peak memory | 191168 kb |
| Host | smart-13c3b305-219a-4305-ade8-35d3d13d193e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378605949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3378605949 |
| Directory | /workspace/165.rv_timer_random/latest |
| Test location | /workspace/coverage/default/166.rv_timer_random.902960132 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1725601672431 ps |
| CPU time | 928.32 seconds |
| Started | Jan 14 01:26:17 PM PST 24 |
| Finished | Jan 14 01:41:47 PM PST 24 |
| Peak memory | 193224 kb |
| Host | smart-70501378-b1e7-4c69-a78e-f3cdc2e95ebc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902960132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.902960132 |
| Directory | /workspace/166.rv_timer_random/latest |
| Test location | /workspace/coverage/default/167.rv_timer_random.3908758487 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 50486121378 ps |
| CPU time | 104.71 seconds |
| Started | Jan 14 01:26:11 PM PST 24 |
| Finished | Jan 14 01:27:57 PM PST 24 |
| Peak memory | 182964 kb |
| Host | smart-c6b0f703-8016-4f87-8acf-ce32bffd036e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908758487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3908758487 |
| Directory | /workspace/167.rv_timer_random/latest |
| Test location | /workspace/coverage/default/169.rv_timer_random.925921168 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 105242588657 ps |
| CPU time | 241.94 seconds |
| Started | Jan 14 01:26:18 PM PST 24 |
| Finished | Jan 14 01:30:20 PM PST 24 |
| Peak memory | 191180 kb |
| Host | smart-07ce2a89-09ae-4f1f-98a6-365e14b31527 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925921168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.925921168 |
| Directory | /workspace/169.rv_timer_random/latest |
| Test location | /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1256591332 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 20401501698 ps |
| CPU time | 8.48 seconds |
| Started | Jan 14 01:24:32 PM PST 24 |
| Finished | Jan 14 01:24:41 PM PST 24 |
| Peak memory | 182960 kb |
| Host | smart-d55f6604-cafe-4f48-bcd9-930a927f473f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256591332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.1256591332 |
| Directory | /workspace/17.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/17.rv_timer_disabled.1063237752 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 2952234826 ps |
| CPU time | 5.5 seconds |
| Started | Jan 14 01:24:25 PM PST 24 |
| Finished | Jan 14 01:24:31 PM PST 24 |
| Peak memory | 182584 kb |
| Host | smart-de767cc6-bad7-4366-8a35-0458cc41b3b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1063237752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1063237752 |
| Directory | /workspace/17.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/17.rv_timer_random.2167273650 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 151555551647 ps |
| CPU time | 857.88 seconds |
| Started | Jan 14 01:24:35 PM PST 24 |
| Finished | Jan 14 01:38:54 PM PST 24 |
| Peak memory | 191076 kb |
| Host | smart-249d2dc7-8cc3-4be4-8027-9a0209283a78 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167273650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2167273650 |
| Directory | /workspace/17.rv_timer_random/latest |
| Test location | /workspace/coverage/default/17.rv_timer_random_reset.1085017051 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 19776689 ps |
| CPU time | 0.55 seconds |
| Started | Jan 14 01:24:22 PM PST 24 |
| Finished | Jan 14 01:24:23 PM PST 24 |
| Peak memory | 182472 kb |
| Host | smart-5cd6d24a-798d-4fcd-90f9-da19e222a9bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1085017051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1085017051 |
| Directory | /workspace/17.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/17.rv_timer_stress_all.1622453293 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1355800262745 ps |
| CPU time | 439.47 seconds |
| Started | Jan 14 01:24:31 PM PST 24 |
| Finished | Jan 14 01:31:51 PM PST 24 |
| Peak memory | 191196 kb |
| Host | smart-03d6f8d0-6c5b-406c-a083-ffc35057b47a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622453293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all .1622453293 |
| Directory | /workspace/17.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.2399904764 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 119616657782 ps |
| CPU time | 997.95 seconds |
| Started | Jan 14 01:24:29 PM PST 24 |
| Finished | Jan 14 01:41:07 PM PST 24 |
| Peak memory | 205872 kb |
| Host | smart-c4470ad1-ba23-4dce-97be-51669a712f0a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399904764 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.2399904764 |
| Directory | /workspace/17.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/170.rv_timer_random.2189600428 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 89178990216 ps |
| CPU time | 256.71 seconds |
| Started | Jan 14 01:26:20 PM PST 24 |
| Finished | Jan 14 01:30:37 PM PST 24 |
| Peak memory | 191156 kb |
| Host | smart-7f8777f9-1711-43db-a88d-2821999b4af4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189600428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2189600428 |
| Directory | /workspace/170.rv_timer_random/latest |
| Test location | /workspace/coverage/default/171.rv_timer_random.500153574 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 28683578874 ps |
| CPU time | 51.04 seconds |
| Started | Jan 14 01:26:20 PM PST 24 |
| Finished | Jan 14 01:27:11 PM PST 24 |
| Peak memory | 183000 kb |
| Host | smart-0fe3a971-94a0-4d97-baf3-f8ca9934623f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500153574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.500153574 |
| Directory | /workspace/171.rv_timer_random/latest |
| Test location | /workspace/coverage/default/172.rv_timer_random.4184806624 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 323359568169 ps |
| CPU time | 209.63 seconds |
| Started | Jan 14 01:26:19 PM PST 24 |
| Finished | Jan 14 01:29:49 PM PST 24 |
| Peak memory | 191200 kb |
| Host | smart-c5a982d2-1a2c-40a5-938f-24d44df6faf5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184806624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.4184806624 |
| Directory | /workspace/172.rv_timer_random/latest |
| Test location | /workspace/coverage/default/173.rv_timer_random.346133076 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 118760273560 ps |
| CPU time | 328.34 seconds |
| Started | Jan 14 01:26:18 PM PST 24 |
| Finished | Jan 14 01:31:47 PM PST 24 |
| Peak memory | 193988 kb |
| Host | smart-de973e19-49a2-4413-8040-9babee720b9c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346133076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.346133076 |
| Directory | /workspace/173.rv_timer_random/latest |
| Test location | /workspace/coverage/default/174.rv_timer_random.1186247748 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 84862078749 ps |
| CPU time | 325.3 seconds |
| Started | Jan 14 01:26:18 PM PST 24 |
| Finished | Jan 14 01:31:44 PM PST 24 |
| Peak memory | 191184 kb |
| Host | smart-5a8ff056-ece7-4dc5-b237-99ac6495c90f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186247748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.1186247748 |
| Directory | /workspace/174.rv_timer_random/latest |
| Test location | /workspace/coverage/default/176.rv_timer_random.1117139489 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 257881685066 ps |
| CPU time | 476.33 seconds |
| Started | Jan 14 01:26:28 PM PST 24 |
| Finished | Jan 14 01:34:25 PM PST 24 |
| Peak memory | 193160 kb |
| Host | smart-7b89d576-78ce-482e-a20f-f384772bfc24 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117139489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1117139489 |
| Directory | /workspace/176.rv_timer_random/latest |
| Test location | /workspace/coverage/default/178.rv_timer_random.1830959704 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 131440307721 ps |
| CPU time | 444.13 seconds |
| Started | Jan 14 01:26:29 PM PST 24 |
| Finished | Jan 14 01:33:54 PM PST 24 |
| Peak memory | 193224 kb |
| Host | smart-7ab973c8-727b-4e99-b4af-f6dbd754c985 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830959704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1830959704 |
| Directory | /workspace/178.rv_timer_random/latest |
| Test location | /workspace/coverage/default/18.rv_timer_disabled.2921934374 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 197522687617 ps |
| CPU time | 318.91 seconds |
| Started | Jan 14 01:24:32 PM PST 24 |
| Finished | Jan 14 01:29:52 PM PST 24 |
| Peak memory | 182996 kb |
| Host | smart-ed3a115f-63b5-4277-817d-be4b82d42370 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2921934374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2921934374 |
| Directory | /workspace/18.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/18.rv_timer_random.3210772239 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 626463407758 ps |
| CPU time | 451.77 seconds |
| Started | Jan 14 01:24:22 PM PST 24 |
| Finished | Jan 14 01:31:55 PM PST 24 |
| Peak memory | 191204 kb |
| Host | smart-7594c726-d68a-4013-85d1-c535ca2a0495 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210772239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3210772239 |
| Directory | /workspace/18.rv_timer_random/latest |
| Test location | /workspace/coverage/default/18.rv_timer_random_reset.2262427768 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 56217630895 ps |
| CPU time | 103.6 seconds |
| Started | Jan 14 01:24:24 PM PST 24 |
| Finished | Jan 14 01:26:08 PM PST 24 |
| Peak memory | 182976 kb |
| Host | smart-ec6b6c5f-46f8-4872-bf65-133d2ae483e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2262427768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2262427768 |
| Directory | /workspace/18.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.382450325 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 50820780855 ps |
| CPU time | 174.2 seconds |
| Started | Jan 14 01:24:30 PM PST 24 |
| Finished | Jan 14 01:27:25 PM PST 24 |
| Peak memory | 197664 kb |
| Host | smart-508604e3-ca29-4615-af6c-e929ca678118 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382450325 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.382450325 |
| Directory | /workspace/18.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/180.rv_timer_random.1899847132 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 738342983019 ps |
| CPU time | 1150.8 seconds |
| Started | Jan 14 01:26:29 PM PST 24 |
| Finished | Jan 14 01:45:41 PM PST 24 |
| Peak memory | 191224 kb |
| Host | smart-458aa1e3-c310-439e-b923-8805fc20f8f1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899847132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1899847132 |
| Directory | /workspace/180.rv_timer_random/latest |
| Test location | /workspace/coverage/default/181.rv_timer_random.316103947 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 347159681045 ps |
| CPU time | 947.31 seconds |
| Started | Jan 14 01:26:30 PM PST 24 |
| Finished | Jan 14 01:42:18 PM PST 24 |
| Peak memory | 191140 kb |
| Host | smart-2eb224bd-0ac8-4c13-8592-4ac5c8f6c780 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316103947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.316103947 |
| Directory | /workspace/181.rv_timer_random/latest |
| Test location | /workspace/coverage/default/183.rv_timer_random.31566524 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 763333218409 ps |
| CPU time | 119.99 seconds |
| Started | Jan 14 01:26:30 PM PST 24 |
| Finished | Jan 14 01:28:31 PM PST 24 |
| Peak memory | 193736 kb |
| Host | smart-df51240c-70ff-4094-bd48-70e54ed5c86e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31566524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.31566524 |
| Directory | /workspace/183.rv_timer_random/latest |
| Test location | /workspace/coverage/default/187.rv_timer_random.195696384 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 113010588591 ps |
| CPU time | 361.45 seconds |
| Started | Jan 14 01:26:36 PM PST 24 |
| Finished | Jan 14 01:32:38 PM PST 24 |
| Peak memory | 191144 kb |
| Host | smart-eb1f74c1-f702-422c-b9e6-d476ec19d715 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195696384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.195696384 |
| Directory | /workspace/187.rv_timer_random/latest |
| Test location | /workspace/coverage/default/188.rv_timer_random.3195339259 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 127601755829 ps |
| CPU time | 126.86 seconds |
| Started | Jan 14 01:26:35 PM PST 24 |
| Finished | Jan 14 01:28:43 PM PST 24 |
| Peak memory | 191156 kb |
| Host | smart-cc8383f7-a1b2-46c0-b21f-4693b506eab8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195339259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3195339259 |
| Directory | /workspace/188.rv_timer_random/latest |
| Test location | /workspace/coverage/default/189.rv_timer_random.1184810646 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 188880367896 ps |
| CPU time | 94.78 seconds |
| Started | Jan 14 01:26:40 PM PST 24 |
| Finished | Jan 14 01:28:15 PM PST 24 |
| Peak memory | 191068 kb |
| Host | smart-ac7fcabf-b07c-4f80-9c6b-33ec8830185e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184810646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1184810646 |
| Directory | /workspace/189.rv_timer_random/latest |
| Test location | /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.3591585336 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1026117679333 ps |
| CPU time | 350.49 seconds |
| Started | Jan 14 01:24:26 PM PST 24 |
| Finished | Jan 14 01:30:17 PM PST 24 |
| Peak memory | 182936 kb |
| Host | smart-33256cf6-6e9a-46f2-b12d-e02066fc9315 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591585336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.3591585336 |
| Directory | /workspace/19.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/19.rv_timer_disabled.61974733 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 50151866711 ps |
| CPU time | 69.97 seconds |
| Started | Jan 14 01:24:29 PM PST 24 |
| Finished | Jan 14 01:25:39 PM PST 24 |
| Peak memory | 182932 kb |
| Host | smart-54a0e02b-4510-474b-9493-ab80d05faca9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=61974733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.61974733 |
| Directory | /workspace/19.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/19.rv_timer_random_reset.4283957428 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 16269518982 ps |
| CPU time | 81.17 seconds |
| Started | Jan 14 01:24:27 PM PST 24 |
| Finished | Jan 14 01:25:49 PM PST 24 |
| Peak memory | 182932 kb |
| Host | smart-0d516042-253f-496f-9a44-c620cd2b2f67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4283957428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.4283957428 |
| Directory | /workspace/19.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.236947389 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 42237023654 ps |
| CPU time | 341.38 seconds |
| Started | Jan 14 01:24:27 PM PST 24 |
| Finished | Jan 14 01:30:09 PM PST 24 |
| Peak memory | 205868 kb |
| Host | smart-d6786e31-f92d-434e-a6e2-d5c0893d4179 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236947389 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.236947389 |
| Directory | /workspace/19.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/190.rv_timer_random.2738013953 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 745369371794 ps |
| CPU time | 383.45 seconds |
| Started | Jan 14 01:26:40 PM PST 24 |
| Finished | Jan 14 01:33:04 PM PST 24 |
| Peak memory | 193856 kb |
| Host | smart-1b149e1c-0081-4f85-8639-128bc45eb005 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738013953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2738013953 |
| Directory | /workspace/190.rv_timer_random/latest |
| Test location | /workspace/coverage/default/191.rv_timer_random.3996844448 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 129132695380 ps |
| CPU time | 239.47 seconds |
| Started | Jan 14 01:26:35 PM PST 24 |
| Finished | Jan 14 01:30:35 PM PST 24 |
| Peak memory | 191188 kb |
| Host | smart-8c5a17a0-53e7-43c2-8b38-0d78325e66fa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996844448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3996844448 |
| Directory | /workspace/191.rv_timer_random/latest |
| Test location | /workspace/coverage/default/192.rv_timer_random.1815150151 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 157582173240 ps |
| CPU time | 250.39 seconds |
| Started | Jan 14 01:26:47 PM PST 24 |
| Finished | Jan 14 01:30:58 PM PST 24 |
| Peak memory | 190964 kb |
| Host | smart-c95e81e7-a8fc-43e4-9dc0-e59074dc0d15 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815150151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1815150151 |
| Directory | /workspace/192.rv_timer_random/latest |
| Test location | /workspace/coverage/default/193.rv_timer_random.2990391855 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 326739841159 ps |
| CPU time | 1030.83 seconds |
| Started | Jan 14 01:26:45 PM PST 24 |
| Finished | Jan 14 01:43:57 PM PST 24 |
| Peak memory | 194528 kb |
| Host | smart-2a9c875d-8fbb-4120-8665-f0b1b1fd3bee |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990391855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2990391855 |
| Directory | /workspace/193.rv_timer_random/latest |
| Test location | /workspace/coverage/default/194.rv_timer_random.2814447512 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 96265672890 ps |
| CPU time | 78.22 seconds |
| Started | Jan 14 01:26:49 PM PST 24 |
| Finished | Jan 14 01:28:08 PM PST 24 |
| Peak memory | 194356 kb |
| Host | smart-502059a9-4ed6-477f-8675-3d340b2e6142 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814447512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2814447512 |
| Directory | /workspace/194.rv_timer_random/latest |
| Test location | /workspace/coverage/default/196.rv_timer_random.1581354973 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 29458280992 ps |
| CPU time | 60.49 seconds |
| Started | Jan 14 01:26:49 PM PST 24 |
| Finished | Jan 14 01:27:50 PM PST 24 |
| Peak memory | 191024 kb |
| Host | smart-4a3b74f8-4e7d-45df-87b1-e9bdcc734102 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581354973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1581354973 |
| Directory | /workspace/196.rv_timer_random/latest |
| Test location | /workspace/coverage/default/197.rv_timer_random.3378310139 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 127973279319 ps |
| CPU time | 238.26 seconds |
| Started | Jan 14 01:26:48 PM PST 24 |
| Finished | Jan 14 01:30:48 PM PST 24 |
| Peak memory | 191044 kb |
| Host | smart-4d2fbeb7-e967-4d64-83aa-5b7e168189f5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378310139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3378310139 |
| Directory | /workspace/197.rv_timer_random/latest |
| Test location | /workspace/coverage/default/198.rv_timer_random.803453111 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 116311969260 ps |
| CPU time | 204.19 seconds |
| Started | Jan 14 01:26:43 PM PST 24 |
| Finished | Jan 14 01:30:08 PM PST 24 |
| Peak memory | 193636 kb |
| Host | smart-457c33d9-9ea2-45eb-a756-047ac8f82efc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803453111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.803453111 |
| Directory | /workspace/198.rv_timer_random/latest |
| Test location | /workspace/coverage/default/199.rv_timer_random.2505286160 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 55180427953 ps |
| CPU time | 28.1 seconds |
| Started | Jan 14 01:26:50 PM PST 24 |
| Finished | Jan 14 01:27:23 PM PST 24 |
| Peak memory | 182916 kb |
| Host | smart-928e01e0-3d21-4309-976f-88c6edefa4ee |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505286160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2505286160 |
| Directory | /workspace/199.rv_timer_random/latest |
| Test location | /workspace/coverage/default/2.rv_timer_disabled.1997249427 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 726933200882 ps |
| CPU time | 280.83 seconds |
| Started | Jan 14 01:23:51 PM PST 24 |
| Finished | Jan 14 01:28:33 PM PST 24 |
| Peak memory | 182876 kb |
| Host | smart-89cbfbec-9d05-4edb-9930-3200281825bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1997249427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1997249427 |
| Directory | /workspace/2.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/2.rv_timer_random.3034199499 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 147362831405 ps |
| CPU time | 248.83 seconds |
| Started | Jan 14 01:24:00 PM PST 24 |
| Finished | Jan 14 01:28:10 PM PST 24 |
| Peak memory | 193308 kb |
| Host | smart-70edc8a8-6697-418e-8f9d-cf5884a96ff7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034199499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3034199499 |
| Directory | /workspace/2.rv_timer_random/latest |
| Test location | /workspace/coverage/default/2.rv_timer_random_reset.494296853 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 1945335631 ps |
| CPU time | 3.86 seconds |
| Started | Jan 14 01:23:59 PM PST 24 |
| Finished | Jan 14 01:24:04 PM PST 24 |
| Peak memory | 182904 kb |
| Host | smart-1619ce1e-f866-41fd-9b46-4c556ae8f672 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=494296853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.494296853 |
| Directory | /workspace/2.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/2.rv_timer_sec_cm.2611767585 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 86153730 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 01:24:06 PM PST 24 |
| Finished | Jan 14 01:24:08 PM PST 24 |
| Peak memory | 213800 kb |
| Host | smart-c7cad0f3-fd1b-4640-96bb-5db0093ff3ec |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611767585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.2611767585 |
| Directory | /workspace/2.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/2.rv_timer_stress_all.3574605680 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 435152975721 ps |
| CPU time | 972.58 seconds |
| Started | Jan 14 01:23:54 PM PST 24 |
| Finished | Jan 14 01:40:08 PM PST 24 |
| Peak memory | 191208 kb |
| Host | smart-1c44edf8-27cf-4536-a99a-d531f1be3ebc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574605680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all. 3574605680 |
| Directory | /workspace/2.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.2128204726 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 78587316185 ps |
| CPU time | 220.67 seconds |
| Started | Jan 14 01:23:52 PM PST 24 |
| Finished | Jan 14 01:27:33 PM PST 24 |
| Peak memory | 207736 kb |
| Host | smart-4a84e98f-721c-462f-9e6a-afd7b31ec2c3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128204726 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.2128204726 |
| Directory | /workspace/2.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1741219787 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 3613760763 ps |
| CPU time | 6.35 seconds |
| Started | Jan 14 01:24:28 PM PST 24 |
| Finished | Jan 14 01:24:35 PM PST 24 |
| Peak memory | 183024 kb |
| Host | smart-d1435003-db52-49c3-b278-b90df6c51d76 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741219787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.1741219787 |
| Directory | /workspace/20.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/20.rv_timer_disabled.3331344245 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 319728915325 ps |
| CPU time | 255.3 seconds |
| Started | Jan 14 01:24:33 PM PST 24 |
| Finished | Jan 14 01:28:49 PM PST 24 |
| Peak memory | 182812 kb |
| Host | smart-f78f5bb0-daaf-496f-a171-5435cf73e375 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3331344245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3331344245 |
| Directory | /workspace/20.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/20.rv_timer_random.1424717041 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 429102269953 ps |
| CPU time | 499.61 seconds |
| Started | Jan 14 01:24:26 PM PST 24 |
| Finished | Jan 14 01:32:47 PM PST 24 |
| Peak memory | 191172 kb |
| Host | smart-fad301b3-2d2e-4a31-a9fb-2881a2a06f2c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424717041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1424717041 |
| Directory | /workspace/20.rv_timer_random/latest |
| Test location | /workspace/coverage/default/20.rv_timer_random_reset.373110600 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 421551666 ps |
| CPU time | 0.78 seconds |
| Started | Jan 14 01:24:34 PM PST 24 |
| Finished | Jan 14 01:24:37 PM PST 24 |
| Peak memory | 191012 kb |
| Host | smart-28ac6d68-8377-4c41-acf9-f7116dce80ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=373110600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.373110600 |
| Directory | /workspace/20.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2516942193 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 250417467651 ps |
| CPU time | 440.15 seconds |
| Started | Jan 14 01:24:34 PM PST 24 |
| Finished | Jan 14 01:31:55 PM PST 24 |
| Peak memory | 182988 kb |
| Host | smart-299188a5-99b9-4bcb-b17c-997ecf1776a0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516942193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_cfg_update_on_fly.2516942193 |
| Directory | /workspace/21.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/21.rv_timer_disabled.3808906724 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 941327541665 ps |
| CPU time | 215.06 seconds |
| Started | Jan 14 01:24:33 PM PST 24 |
| Finished | Jan 14 01:28:09 PM PST 24 |
| Peak memory | 182784 kb |
| Host | smart-cc896c85-fbb1-4c6b-9a89-51c9f5a0a6ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3808906724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3808906724 |
| Directory | /workspace/21.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/21.rv_timer_random.2562481796 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 108682635109 ps |
| CPU time | 1799.63 seconds |
| Started | Jan 14 01:24:33 PM PST 24 |
| Finished | Jan 14 01:54:33 PM PST 24 |
| Peak memory | 191136 kb |
| Host | smart-0b326d00-5fc2-4ff5-8de0-f84fb04bd9ed |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562481796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2562481796 |
| Directory | /workspace/21.rv_timer_random/latest |
| Test location | /workspace/coverage/default/21.rv_timer_random_reset.2727845077 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 46288889012 ps |
| CPU time | 69.97 seconds |
| Started | Jan 14 01:24:29 PM PST 24 |
| Finished | Jan 14 01:25:40 PM PST 24 |
| Peak memory | 191204 kb |
| Host | smart-74fc4f35-0869-4f15-b3df-a73bfc4e0e77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2727845077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2727845077 |
| Directory | /workspace/21.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/21.rv_timer_stress_all.3969384441 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 386063253263 ps |
| CPU time | 481.35 seconds |
| Started | Jan 14 01:24:34 PM PST 24 |
| Finished | Jan 14 01:32:37 PM PST 24 |
| Peak memory | 191112 kb |
| Host | smart-a0ce49ff-d94a-42de-8d23-f6131fc69f59 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969384441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all .3969384441 |
| Directory | /workspace/21.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.2256387426 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 70124083678 ps |
| CPU time | 563.01 seconds |
| Started | Jan 14 01:24:35 PM PST 24 |
| Finished | Jan 14 01:33:59 PM PST 24 |
| Peak memory | 205896 kb |
| Host | smart-39b4d88d-1246-45df-92d7-b31eafe7bff7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256387426 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.2256387426 |
| Directory | /workspace/21.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.2181794751 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 323253893750 ps |
| CPU time | 548.04 seconds |
| Started | Jan 14 01:24:34 PM PST 24 |
| Finished | Jan 14 01:33:44 PM PST 24 |
| Peak memory | 183000 kb |
| Host | smart-e6242bf2-f96b-46a3-a9a6-0f55fb0e4ff5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181794751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_cfg_update_on_fly.2181794751 |
| Directory | /workspace/22.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/22.rv_timer_random.3283541941 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 42899644100 ps |
| CPU time | 71.67 seconds |
| Started | Jan 14 01:24:33 PM PST 24 |
| Finished | Jan 14 01:25:45 PM PST 24 |
| Peak memory | 191116 kb |
| Host | smart-cb26dcb8-d34f-40e0-bb16-43a1ee6ffb40 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283541941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3283541941 |
| Directory | /workspace/22.rv_timer_random/latest |
| Test location | /workspace/coverage/default/22.rv_timer_random_reset.2959399422 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 19270238548 ps |
| CPU time | 11.4 seconds |
| Started | Jan 14 01:24:33 PM PST 24 |
| Finished | Jan 14 01:24:46 PM PST 24 |
| Peak memory | 182872 kb |
| Host | smart-aa628c5c-09ba-4c36-abf4-b931a9142076 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2959399422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2959399422 |
| Directory | /workspace/22.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/22.rv_timer_stress_all.223480818 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 309988780457 ps |
| CPU time | 654.92 seconds |
| Started | Jan 14 01:24:36 PM PST 24 |
| Finished | Jan 14 01:35:37 PM PST 24 |
| Peak memory | 191308 kb |
| Host | smart-013f7a25-a488-4da5-94ad-df20f31eeaa4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223480818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all. 223480818 |
| Directory | /workspace/22.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.3175175014 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 41326019544 ps |
| CPU time | 162.72 seconds |
| Started | Jan 14 01:24:30 PM PST 24 |
| Finished | Jan 14 01:27:13 PM PST 24 |
| Peak memory | 197704 kb |
| Host | smart-a2bfac6c-f724-4a46-938b-36976c4bf7ea |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175175014 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.3175175014 |
| Directory | /workspace/22.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1203230692 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 773527267178 ps |
| CPU time | 878.79 seconds |
| Started | Jan 14 01:24:35 PM PST 24 |
| Finished | Jan 14 01:39:15 PM PST 24 |
| Peak memory | 182840 kb |
| Host | smart-ef438502-1482-4849-9129-ba87c457f8ed |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203230692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.1203230692 |
| Directory | /workspace/23.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/23.rv_timer_disabled.83444428 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 191108936109 ps |
| CPU time | 77.72 seconds |
| Started | Jan 14 01:24:30 PM PST 24 |
| Finished | Jan 14 01:25:48 PM PST 24 |
| Peak memory | 183000 kb |
| Host | smart-bd1c2ea2-a195-409a-9718-a109553fd252 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=83444428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.83444428 |
| Directory | /workspace/23.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/23.rv_timer_random.2971171632 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 91720725834 ps |
| CPU time | 390.33 seconds |
| Started | Jan 14 01:24:35 PM PST 24 |
| Finished | Jan 14 01:31:07 PM PST 24 |
| Peak memory | 194244 kb |
| Host | smart-e52b9ab2-2015-4307-a18b-0677041f8892 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971171632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2971171632 |
| Directory | /workspace/23.rv_timer_random/latest |
| Test location | /workspace/coverage/default/23.rv_timer_random_reset.2292342797 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 6703961263 ps |
| CPU time | 7.73 seconds |
| Started | Jan 14 01:24:29 PM PST 24 |
| Finished | Jan 14 01:24:37 PM PST 24 |
| Peak memory | 182940 kb |
| Host | smart-f6ac7687-00d1-4e73-816b-ca90ef0b1aa8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2292342797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2292342797 |
| Directory | /workspace/23.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/23.rv_timer_stress_all.1660934328 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 375173350342 ps |
| CPU time | 267.76 seconds |
| Started | Jan 14 01:24:33 PM PST 24 |
| Finished | Jan 14 01:29:02 PM PST 24 |
| Peak memory | 191176 kb |
| Host | smart-6b450d8f-8f9e-470f-964a-bf36de8ccb0e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660934328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all .1660934328 |
| Directory | /workspace/23.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.1927594979 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 834915753688 ps |
| CPU time | 948.3 seconds |
| Started | Jan 14 01:24:36 PM PST 24 |
| Finished | Jan 14 01:40:30 PM PST 24 |
| Peak memory | 209252 kb |
| Host | smart-ce46c441-e782-4e94-bfac-bf50b9612927 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927594979 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.1927594979 |
| Directory | /workspace/23.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/24.rv_timer_disabled.2890398801 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 529207553109 ps |
| CPU time | 239.73 seconds |
| Started | Jan 14 01:24:35 PM PST 24 |
| Finished | Jan 14 01:28:37 PM PST 24 |
| Peak memory | 182992 kb |
| Host | smart-e458002d-d972-4eea-a53b-2d068df88335 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2890398801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.2890398801 |
| Directory | /workspace/24.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/24.rv_timer_random.4039984940 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 3115716336 ps |
| CPU time | 2.15 seconds |
| Started | Jan 14 01:24:40 PM PST 24 |
| Finished | Jan 14 01:24:46 PM PST 24 |
| Peak memory | 182780 kb |
| Host | smart-62b4b105-1219-4a47-a72a-51455f0009e4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039984940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.4039984940 |
| Directory | /workspace/24.rv_timer_random/latest |
| Test location | /workspace/coverage/default/24.rv_timer_random_reset.116957411 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 213988103776 ps |
| CPU time | 109.47 seconds |
| Started | Jan 14 01:24:40 PM PST 24 |
| Finished | Jan 14 01:26:33 PM PST 24 |
| Peak memory | 194296 kb |
| Host | smart-ffd04b90-c2a8-4c0e-b215-f8759aae8631 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=116957411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.116957411 |
| Directory | /workspace/24.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/24.rv_timer_stress_all.2159948640 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 432899262729 ps |
| CPU time | 254.39 seconds |
| Started | Jan 14 01:24:39 PM PST 24 |
| Finished | Jan 14 01:28:58 PM PST 24 |
| Peak memory | 191052 kb |
| Host | smart-c29abe1a-4865-4008-bafc-dd6162499c1e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159948640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all .2159948640 |
| Directory | /workspace/24.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.2944579362 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 103882107253 ps |
| CPU time | 696.79 seconds |
| Started | Jan 14 01:24:37 PM PST 24 |
| Finished | Jan 14 01:36:20 PM PST 24 |
| Peak memory | 205868 kb |
| Host | smart-d82becc1-c04c-4e11-bd08-ebcdba436a2f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944579362 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.2944579362 |
| Directory | /workspace/24.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.1842950111 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 237507871902 ps |
| CPU time | 218.76 seconds |
| Started | Jan 14 01:24:38 PM PST 24 |
| Finished | Jan 14 01:28:23 PM PST 24 |
| Peak memory | 182852 kb |
| Host | smart-9461da07-2e5b-443b-b232-b97c1903f99a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842950111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_cfg_update_on_fly.1842950111 |
| Directory | /workspace/25.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/25.rv_timer_disabled.2681339928 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 73346407447 ps |
| CPU time | 121.21 seconds |
| Started | Jan 14 01:24:37 PM PST 24 |
| Finished | Jan 14 01:26:44 PM PST 24 |
| Peak memory | 182952 kb |
| Host | smart-53f38b36-4bba-4bf0-ab64-7237f02a2478 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2681339928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2681339928 |
| Directory | /workspace/25.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/25.rv_timer_random_reset.477652014 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 118141207 ps |
| CPU time | 0.8 seconds |
| Started | Jan 14 01:24:36 PM PST 24 |
| Finished | Jan 14 01:24:42 PM PST 24 |
| Peak memory | 182640 kb |
| Host | smart-c2775c07-46ce-4f7e-b6e4-c4e2f223fe5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=477652014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.477652014 |
| Directory | /workspace/25.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/25.rv_timer_stress_all.3708922317 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 296321455603 ps |
| CPU time | 466.04 seconds |
| Started | Jan 14 01:24:40 PM PST 24 |
| Finished | Jan 14 01:32:30 PM PST 24 |
| Peak memory | 195324 kb |
| Host | smart-996bde27-aa63-498e-a46a-e9731b1459c4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708922317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all .3708922317 |
| Directory | /workspace/25.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.756189655 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 65317512980 ps |
| CPU time | 217.91 seconds |
| Started | Jan 14 01:24:36 PM PST 24 |
| Finished | Jan 14 01:28:15 PM PST 24 |
| Peak memory | 205780 kb |
| Host | smart-a362b124-6069-4930-a7fa-cc7e82058900 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756189655 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.756189655 |
| Directory | /workspace/25.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1951460835 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 75630713639 ps |
| CPU time | 29.35 seconds |
| Started | Jan 14 01:24:38 PM PST 24 |
| Finished | Jan 14 01:25:13 PM PST 24 |
| Peak memory | 182944 kb |
| Host | smart-84a34808-ff4d-4c44-9019-afa2346ac5b2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951460835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_cfg_update_on_fly.1951460835 |
| Directory | /workspace/26.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/26.rv_timer_disabled.624738385 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 231593468993 ps |
| CPU time | 181.5 seconds |
| Started | Jan 14 01:24:37 PM PST 24 |
| Finished | Jan 14 01:27:44 PM PST 24 |
| Peak memory | 182992 kb |
| Host | smart-c401cdb8-ef2d-4d2d-87c1-c55456c40566 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=624738385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.624738385 |
| Directory | /workspace/26.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/26.rv_timer_random.670345144 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 35190391462 ps |
| CPU time | 57.35 seconds |
| Started | Jan 14 01:24:42 PM PST 24 |
| Finished | Jan 14 01:25:42 PM PST 24 |
| Peak memory | 191256 kb |
| Host | smart-8b19568d-53ea-4878-bf09-e5ea5d40d0cc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670345144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.670345144 |
| Directory | /workspace/26.rv_timer_random/latest |
| Test location | /workspace/coverage/default/26.rv_timer_random_reset.1114587871 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 209570569795 ps |
| CPU time | 308.78 seconds |
| Started | Jan 14 01:24:42 PM PST 24 |
| Finished | Jan 14 01:29:54 PM PST 24 |
| Peak memory | 191176 kb |
| Host | smart-0f23049b-01f3-4cbf-87b3-79f14e230dd2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1114587871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1114587871 |
| Directory | /workspace/26.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.4073383895 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 397570052215 ps |
| CPU time | 806.56 seconds |
| Started | Jan 14 01:24:42 PM PST 24 |
| Finished | Jan 14 01:38:11 PM PST 24 |
| Peak memory | 208700 kb |
| Host | smart-bf9adf1a-cfb4-4934-bccc-286da5f70a41 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073383895 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.4073383895 |
| Directory | /workspace/26.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1447068441 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 57699311504 ps |
| CPU time | 26.86 seconds |
| Started | Jan 14 01:24:45 PM PST 24 |
| Finished | Jan 14 01:25:19 PM PST 24 |
| Peak memory | 182984 kb |
| Host | smart-8594cc35-ad03-4002-b99f-af006e6e8890 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447068441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.1447068441 |
| Directory | /workspace/27.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/27.rv_timer_random.4209598600 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 297570753011 ps |
| CPU time | 533.34 seconds |
| Started | Jan 14 01:24:40 PM PST 24 |
| Finished | Jan 14 01:33:37 PM PST 24 |
| Peak memory | 194232 kb |
| Host | smart-07de814d-c695-4b91-9ccb-798c5a0c1fe3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209598600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.4209598600 |
| Directory | /workspace/27.rv_timer_random/latest |
| Test location | /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.4189879482 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 2410833842636 ps |
| CPU time | 1067.75 seconds |
| Started | Jan 14 01:24:44 PM PST 24 |
| Finished | Jan 14 01:42:39 PM PST 24 |
| Peak memory | 211120 kb |
| Host | smart-02f71b68-5354-4eb7-a19e-dcb85c9b2b41 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189879482 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.4189879482 |
| Directory | /workspace/27.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1425745673 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 781151818209 ps |
| CPU time | 686.37 seconds |
| Started | Jan 14 01:24:45 PM PST 24 |
| Finished | Jan 14 01:36:19 PM PST 24 |
| Peak memory | 182992 kb |
| Host | smart-e7941312-171a-407b-8e85-645eb08c5ef9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425745673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_cfg_update_on_fly.1425745673 |
| Directory | /workspace/28.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/28.rv_timer_disabled.3650546433 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 138838714200 ps |
| CPU time | 126.34 seconds |
| Started | Jan 14 01:24:43 PM PST 24 |
| Finished | Jan 14 01:26:51 PM PST 24 |
| Peak memory | 182836 kb |
| Host | smart-1a55abd4-501b-41dc-84a2-143051f5124e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3650546433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3650546433 |
| Directory | /workspace/28.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/28.rv_timer_random_reset.3689623730 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 20947312478 ps |
| CPU time | 26.76 seconds |
| Started | Jan 14 01:24:48 PM PST 24 |
| Finished | Jan 14 01:25:19 PM PST 24 |
| Peak memory | 182600 kb |
| Host | smart-26d600b1-6e30-406f-9437-3c961043849b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3689623730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.3689623730 |
| Directory | /workspace/28.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.2641588191 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 46320177153 ps |
| CPU time | 444.63 seconds |
| Started | Jan 14 01:24:44 PM PST 24 |
| Finished | Jan 14 01:32:16 PM PST 24 |
| Peak memory | 205904 kb |
| Host | smart-73068156-669b-4691-8bcb-708d9e9cb346 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641588191 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.2641588191 |
| Directory | /workspace/28.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2042572322 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 177049447438 ps |
| CPU time | 177.77 seconds |
| Started | Jan 14 01:24:48 PM PST 24 |
| Finished | Jan 14 01:27:50 PM PST 24 |
| Peak memory | 182956 kb |
| Host | smart-1fd023b8-0d7d-4fa9-a752-b095e127295a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042572322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.2042572322 |
| Directory | /workspace/29.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/29.rv_timer_random.1625584679 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1173322062255 ps |
| CPU time | 643.49 seconds |
| Started | Jan 14 01:24:45 PM PST 24 |
| Finished | Jan 14 01:35:36 PM PST 24 |
| Peak memory | 194492 kb |
| Host | smart-0f83b58d-59b4-48c0-81d3-4f135d964aff |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625584679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1625584679 |
| Directory | /workspace/29.rv_timer_random/latest |
| Test location | /workspace/coverage/default/29.rv_timer_random_reset.2702853070 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 96959058313 ps |
| CPU time | 77.87 seconds |
| Started | Jan 14 01:24:41 PM PST 24 |
| Finished | Jan 14 01:26:02 PM PST 24 |
| Peak memory | 182652 kb |
| Host | smart-29dcc8b1-1895-4c8b-8bff-a57bc4bbfb0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2702853070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2702853070 |
| Directory | /workspace/29.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/29.rv_timer_stress_all.3919588023 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 1067137778855 ps |
| CPU time | 902.75 seconds |
| Started | Jan 14 01:24:42 PM PST 24 |
| Finished | Jan 14 01:39:47 PM PST 24 |
| Peak memory | 191084 kb |
| Host | smart-007deb8d-36af-49e8-9b5c-5dfb9a2e23d7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919588023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all .3919588023 |
| Directory | /workspace/29.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.2073176797 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 371951283293 ps |
| CPU time | 1850.96 seconds |
| Started | Jan 14 01:24:41 PM PST 24 |
| Finished | Jan 14 01:55:35 PM PST 24 |
| Peak memory | 212912 kb |
| Host | smart-2c76fdcd-a51f-444b-847e-b8b0bd6a4547 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073176797 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.2073176797 |
| Directory | /workspace/29.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3920185901 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 12759062525 ps |
| CPU time | 25.02 seconds |
| Started | Jan 14 01:23:57 PM PST 24 |
| Finished | Jan 14 01:24:22 PM PST 24 |
| Peak memory | 182924 kb |
| Host | smart-2e3f9839-6eb2-4349-8fb6-cb3427f60445 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920185901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_cfg_update_on_fly.3920185901 |
| Directory | /workspace/3.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/3.rv_timer_disabled.3263680953 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 70719178939 ps |
| CPU time | 101.98 seconds |
| Started | Jan 14 01:23:55 PM PST 24 |
| Finished | Jan 14 01:25:38 PM PST 24 |
| Peak memory | 182820 kb |
| Host | smart-f5c3c6dc-a032-4987-924b-a22f2503c894 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3263680953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3263680953 |
| Directory | /workspace/3.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/3.rv_timer_random.3839173547 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 324125430931 ps |
| CPU time | 210.72 seconds |
| Started | Jan 14 01:24:00 PM PST 24 |
| Finished | Jan 14 01:27:32 PM PST 24 |
| Peak memory | 193740 kb |
| Host | smart-5d13ffc3-a2fc-4c20-8bab-4039911570d5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839173547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3839173547 |
| Directory | /workspace/3.rv_timer_random/latest |
| Test location | /workspace/coverage/default/3.rv_timer_random_reset.823222219 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 10688954474 ps |
| CPU time | 13.16 seconds |
| Started | Jan 14 01:24:00 PM PST 24 |
| Finished | Jan 14 01:24:14 PM PST 24 |
| Peak memory | 182964 kb |
| Host | smart-d57e95ca-9439-4fb8-87dc-1265a5d7e56c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=823222219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.823222219 |
| Directory | /workspace/3.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/3.rv_timer_sec_cm.325454624 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 35896689 ps |
| CPU time | 0.75 seconds |
| Started | Jan 14 01:24:06 PM PST 24 |
| Finished | Jan 14 01:24:08 PM PST 24 |
| Peak memory | 212548 kb |
| Host | smart-fce83992-e66a-4e8c-9b59-4340f687feed |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325454624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.325454624 |
| Directory | /workspace/3.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.2344688768 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 26850669218 ps |
| CPU time | 221.92 seconds |
| Started | Jan 14 01:23:59 PM PST 24 |
| Finished | Jan 14 01:27:41 PM PST 24 |
| Peak memory | 205880 kb |
| Host | smart-9492bf5b-67c4-4075-90a2-34b80dfe1a05 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344688768 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.2344688768 |
| Directory | /workspace/3.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.1262191052 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 388832593404 ps |
| CPU time | 636.54 seconds |
| Started | Jan 14 01:24:52 PM PST 24 |
| Finished | Jan 14 01:35:32 PM PST 24 |
| Peak memory | 182900 kb |
| Host | smart-365beb4c-1fff-484e-832b-1ae9ef525268 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262191052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.1262191052 |
| Directory | /workspace/30.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/30.rv_timer_disabled.2121623516 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 61421641712 ps |
| CPU time | 88.01 seconds |
| Started | Jan 14 01:24:41 PM PST 24 |
| Finished | Jan 14 01:26:12 PM PST 24 |
| Peak memory | 183060 kb |
| Host | smart-5d0de7b5-981f-432c-b5c7-e533581361da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2121623516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2121623516 |
| Directory | /workspace/30.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/30.rv_timer_random.1535478463 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 333296616750 ps |
| CPU time | 1245.59 seconds |
| Started | Jan 14 01:24:43 PM PST 24 |
| Finished | Jan 14 01:45:30 PM PST 24 |
| Peak memory | 191044 kb |
| Host | smart-6d720f8e-87e6-4ef7-ae46-5e5a7e138a9a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535478463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1535478463 |
| Directory | /workspace/30.rv_timer_random/latest |
| Test location | /workspace/coverage/default/30.rv_timer_random_reset.2894447960 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 9307280404 ps |
| CPU time | 87.32 seconds |
| Started | Jan 14 01:24:42 PM PST 24 |
| Finished | Jan 14 01:26:11 PM PST 24 |
| Peak memory | 191192 kb |
| Host | smart-e3995121-5943-4d01-8462-3c79e936743e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2894447960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2894447960 |
| Directory | /workspace/30.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.4038513282 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 480755351473 ps |
| CPU time | 906.33 seconds |
| Started | Jan 14 01:24:45 PM PST 24 |
| Finished | Jan 14 01:39:58 PM PST 24 |
| Peak memory | 209656 kb |
| Host | smart-95db8034-0bd3-40f7-a8f2-da1267550249 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038513282 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.4038513282 |
| Directory | /workspace/30.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2215329921 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 336492779912 ps |
| CPU time | 196.66 seconds |
| Started | Jan 14 01:24:48 PM PST 24 |
| Finished | Jan 14 01:28:09 PM PST 24 |
| Peak memory | 182760 kb |
| Host | smart-f3b5d8da-55d7-4583-9162-698e47f93371 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215329921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_cfg_update_on_fly.2215329921 |
| Directory | /workspace/31.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/31.rv_timer_disabled.3675495963 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 291141854107 ps |
| CPU time | 245.9 seconds |
| Started | Jan 14 01:24:45 PM PST 24 |
| Finished | Jan 14 01:28:58 PM PST 24 |
| Peak memory | 182820 kb |
| Host | smart-71b3c790-5fa1-4314-967d-6e06ba8d6373 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3675495963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3675495963 |
| Directory | /workspace/31.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/31.rv_timer_random.2960744130 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 298571286468 ps |
| CPU time | 649.2 seconds |
| Started | Jan 14 01:24:51 PM PST 24 |
| Finished | Jan 14 01:35:42 PM PST 24 |
| Peak memory | 191172 kb |
| Host | smart-5e0a373d-5ba2-4563-8d3c-e4436d96c84a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960744130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2960744130 |
| Directory | /workspace/31.rv_timer_random/latest |
| Test location | /workspace/coverage/default/31.rv_timer_random_reset.3908585110 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 50576301727 ps |
| CPU time | 60.99 seconds |
| Started | Jan 14 01:24:48 PM PST 24 |
| Finished | Jan 14 01:25:53 PM PST 24 |
| Peak memory | 194000 kb |
| Host | smart-587cadfd-ba38-4846-9189-294b49cf7a23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3908585110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3908585110 |
| Directory | /workspace/31.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.571564281 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 42943967047 ps |
| CPU time | 341.83 seconds |
| Started | Jan 14 01:24:50 PM PST 24 |
| Finished | Jan 14 01:30:34 PM PST 24 |
| Peak memory | 197648 kb |
| Host | smart-c1f1f583-f79a-484f-8491-0ceadeaf436a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571564281 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.571564281 |
| Directory | /workspace/31.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1316052130 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 1337789903141 ps |
| CPU time | 655.51 seconds |
| Started | Jan 14 01:24:51 PM PST 24 |
| Finished | Jan 14 01:35:50 PM PST 24 |
| Peak memory | 182212 kb |
| Host | smart-86fc8a4d-e33d-4bd3-be7a-90b025a4d11b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316052130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_cfg_update_on_fly.1316052130 |
| Directory | /workspace/32.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/32.rv_timer_disabled.1215270025 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 612046861774 ps |
| CPU time | 224.81 seconds |
| Started | Jan 14 01:24:46 PM PST 24 |
| Finished | Jan 14 01:28:37 PM PST 24 |
| Peak memory | 182960 kb |
| Host | smart-cda3d946-b58c-4d22-8976-c1a7966ac08c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1215270025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.1215270025 |
| Directory | /workspace/32.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/32.rv_timer_random.538003687 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 294746105387 ps |
| CPU time | 1311.18 seconds |
| Started | Jan 14 01:24:52 PM PST 24 |
| Finished | Jan 14 01:46:46 PM PST 24 |
| Peak memory | 191080 kb |
| Host | smart-3d677171-db45-4e03-809b-03340d9793cf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538003687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.538003687 |
| Directory | /workspace/32.rv_timer_random/latest |
| Test location | /workspace/coverage/default/32.rv_timer_random_reset.4283535887 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 76150176222 ps |
| CPU time | 525.73 seconds |
| Started | Jan 14 01:24:56 PM PST 24 |
| Finished | Jan 14 01:33:43 PM PST 24 |
| Peak memory | 191204 kb |
| Host | smart-b105bb0a-fbfa-4f1f-a5f4-71309c59ea8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4283535887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.4283535887 |
| Directory | /workspace/32.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/32.rv_timer_stress_all.1191244363 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 794669452170 ps |
| CPU time | 1135.72 seconds |
| Started | Jan 14 01:24:50 PM PST 24 |
| Finished | Jan 14 01:43:48 PM PST 24 |
| Peak memory | 191164 kb |
| Host | smart-2ad9d2d9-d229-4876-a025-9e7522257e8e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191244363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all .1191244363 |
| Directory | /workspace/32.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.2907973008 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 81053345663 ps |
| CPU time | 952.04 seconds |
| Started | Jan 14 01:24:47 PM PST 24 |
| Finished | Jan 14 01:40:44 PM PST 24 |
| Peak memory | 206812 kb |
| Host | smart-6507a986-9535-4ae8-800b-425ec034ab00 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907973008 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.2907973008 |
| Directory | /workspace/32.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3511468630 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 36245460309 ps |
| CPU time | 70.01 seconds |
| Started | Jan 14 01:24:48 PM PST 24 |
| Finished | Jan 14 01:26:02 PM PST 24 |
| Peak memory | 183028 kb |
| Host | smart-2a449cbc-b190-47fc-bb31-a04f0b5646e6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511468630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.3511468630 |
| Directory | /workspace/33.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/33.rv_timer_disabled.2856783625 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 146096127601 ps |
| CPU time | 169.47 seconds |
| Started | Jan 14 01:24:49 PM PST 24 |
| Finished | Jan 14 01:27:42 PM PST 24 |
| Peak memory | 182976 kb |
| Host | smart-f7f82ae7-8e60-48a9-8f1d-148c58b084fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2856783625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2856783625 |
| Directory | /workspace/33.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/33.rv_timer_random.1021339795 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 424675369212 ps |
| CPU time | 699.34 seconds |
| Started | Jan 14 01:24:50 PM PST 24 |
| Finished | Jan 14 01:36:32 PM PST 24 |
| Peak memory | 191172 kb |
| Host | smart-b1904486-ba92-428b-bed8-38c7e6806830 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021339795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1021339795 |
| Directory | /workspace/33.rv_timer_random/latest |
| Test location | /workspace/coverage/default/33.rv_timer_random_reset.886884763 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 200393129007 ps |
| CPU time | 1734.28 seconds |
| Started | Jan 14 01:24:49 PM PST 24 |
| Finished | Jan 14 01:53:47 PM PST 24 |
| Peak memory | 193756 kb |
| Host | smart-bd9b7b61-532c-4097-95ce-01ceaf5099c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=886884763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.886884763 |
| Directory | /workspace/33.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/33.rv_timer_stress_all.2781341504 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 508274747275 ps |
| CPU time | 678.2 seconds |
| Started | Jan 14 01:24:52 PM PST 24 |
| Finished | Jan 14 01:36:13 PM PST 24 |
| Peak memory | 191148 kb |
| Host | smart-26bf7146-d709-4aff-8a20-24d88d1644c8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781341504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all .2781341504 |
| Directory | /workspace/33.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.1861253772 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 265326777700 ps |
| CPU time | 899.82 seconds |
| Started | Jan 14 01:24:48 PM PST 24 |
| Finished | Jan 14 01:39:52 PM PST 24 |
| Peak memory | 205828 kb |
| Host | smart-4fcc83bd-2933-431c-a977-b38351dc440b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861253772 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.1861253772 |
| Directory | /workspace/33.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.661250698 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 384728307374 ps |
| CPU time | 365.26 seconds |
| Started | Jan 14 01:24:51 PM PST 24 |
| Finished | Jan 14 01:31:00 PM PST 24 |
| Peak memory | 182240 kb |
| Host | smart-b7177429-9bb9-4878-8b3d-d4a82c1673e3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661250698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 4.rv_timer_cfg_update_on_fly.661250698 |
| Directory | /workspace/34.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/34.rv_timer_disabled.3988286708 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 157070840405 ps |
| CPU time | 132 seconds |
| Started | Jan 14 01:24:52 PM PST 24 |
| Finished | Jan 14 01:27:07 PM PST 24 |
| Peak memory | 182892 kb |
| Host | smart-4c9308cd-e93f-43e4-ab83-ff74ba938523 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3988286708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3988286708 |
| Directory | /workspace/34.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/34.rv_timer_random.1504250544 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 35222473657 ps |
| CPU time | 32.13 seconds |
| Started | Jan 14 01:24:53 PM PST 24 |
| Finished | Jan 14 01:25:28 PM PST 24 |
| Peak memory | 182968 kb |
| Host | smart-b23bb4b9-74f4-43db-bf5f-a4d6eb9ea227 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504250544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1504250544 |
| Directory | /workspace/34.rv_timer_random/latest |
| Test location | /workspace/coverage/default/34.rv_timer_random_reset.2569272711 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 151636734471 ps |
| CPU time | 124.33 seconds |
| Started | Jan 14 01:24:53 PM PST 24 |
| Finished | Jan 14 01:27:00 PM PST 24 |
| Peak memory | 182904 kb |
| Host | smart-655fabd7-16c8-412b-aab1-73666be78e1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2569272711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2569272711 |
| Directory | /workspace/34.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/34.rv_timer_stress_all.99680431 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 115717112521 ps |
| CPU time | 195.15 seconds |
| Started | Jan 14 01:24:52 PM PST 24 |
| Finished | Jan 14 01:28:10 PM PST 24 |
| Peak memory | 194508 kb |
| Host | smart-83ebbe35-6e6a-49bd-8bfc-f19711e8fb90 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99680431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_ all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.99680431 |
| Directory | /workspace/34.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.3350270031 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 36072079150 ps |
| CPU time | 150.83 seconds |
| Started | Jan 14 01:24:49 PM PST 24 |
| Finished | Jan 14 01:27:23 PM PST 24 |
| Peak memory | 197604 kb |
| Host | smart-6e4bfcd1-ffc0-4407-bad1-010f7ffc067d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350270031 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.3350270031 |
| Directory | /workspace/34.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/35.rv_timer_disabled.4269668576 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 6592754100 ps |
| CPU time | 4.44 seconds |
| Started | Jan 14 01:24:49 PM PST 24 |
| Finished | Jan 14 01:24:57 PM PST 24 |
| Peak memory | 182992 kb |
| Host | smart-3b2b2cf5-cca5-4b65-928a-4b8f1b42e497 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4269668576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.4269668576 |
| Directory | /workspace/35.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/35.rv_timer_random.1632984537 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 127815686954 ps |
| CPU time | 1800.99 seconds |
| Started | Jan 14 01:24:55 PM PST 24 |
| Finished | Jan 14 01:54:57 PM PST 24 |
| Peak memory | 191168 kb |
| Host | smart-68c8502d-06b5-4701-82e9-0c150f83a643 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632984537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1632984537 |
| Directory | /workspace/35.rv_timer_random/latest |
| Test location | /workspace/coverage/default/35.rv_timer_random_reset.4031438616 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 20717713918 ps |
| CPU time | 328.26 seconds |
| Started | Jan 14 01:24:52 PM PST 24 |
| Finished | Jan 14 01:30:23 PM PST 24 |
| Peak memory | 182936 kb |
| Host | smart-95f48b3e-6af2-4d5f-a65c-069793e440bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4031438616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.4031438616 |
| Directory | /workspace/35.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.3842979126 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 133350182138 ps |
| CPU time | 332.42 seconds |
| Started | Jan 14 01:24:54 PM PST 24 |
| Finished | Jan 14 01:30:28 PM PST 24 |
| Peak memory | 197532 kb |
| Host | smart-73677ca0-90c3-4970-9ce0-fa9d0f554181 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842979126 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.3842979126 |
| Directory | /workspace/35.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1790759263 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 6409568472311 ps |
| CPU time | 3125.66 seconds |
| Started | Jan 14 01:24:57 PM PST 24 |
| Finished | Jan 14 02:17:04 PM PST 24 |
| Peak memory | 182856 kb |
| Host | smart-f3659944-b30e-4992-a1d7-b28973822573 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790759263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.1790759263 |
| Directory | /workspace/36.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/36.rv_timer_disabled.3608551872 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 300264723275 ps |
| CPU time | 122.88 seconds |
| Started | Jan 14 01:24:55 PM PST 24 |
| Finished | Jan 14 01:26:59 PM PST 24 |
| Peak memory | 182964 kb |
| Host | smart-65a140c4-5b75-4171-92b8-2cb9e11e6e2c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3608551872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3608551872 |
| Directory | /workspace/36.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/36.rv_timer_random.2265150576 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 136397466083 ps |
| CPU time | 692.8 seconds |
| Started | Jan 14 01:24:50 PM PST 24 |
| Finished | Jan 14 01:36:26 PM PST 24 |
| Peak memory | 191168 kb |
| Host | smart-0796d931-0f7b-49b2-9c5a-4a3da99a0d1d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265150576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2265150576 |
| Directory | /workspace/36.rv_timer_random/latest |
| Test location | /workspace/coverage/default/36.rv_timer_random_reset.1602597017 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 48880147914 ps |
| CPU time | 79.25 seconds |
| Started | Jan 14 01:24:57 PM PST 24 |
| Finished | Jan 14 01:26:17 PM PST 24 |
| Peak memory | 191188 kb |
| Host | smart-8b52d061-b4c8-402e-a25a-9291f67b2a55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1602597017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.1602597017 |
| Directory | /workspace/36.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/36.rv_timer_stress_all.1813727510 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 5925126199 ps |
| CPU time | 3.17 seconds |
| Started | Jan 14 01:25:01 PM PST 24 |
| Finished | Jan 14 01:25:09 PM PST 24 |
| Peak memory | 182956 kb |
| Host | smart-dd51e8b9-845f-4be6-95a5-ea4bc441c603 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813727510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all .1813727510 |
| Directory | /workspace/36.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.3825269215 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 74579021552 ps |
| CPU time | 865.64 seconds |
| Started | Jan 14 01:24:58 PM PST 24 |
| Finished | Jan 14 01:39:25 PM PST 24 |
| Peak memory | 205864 kb |
| Host | smart-228a3685-3a17-475f-a312-6b5425c34b9c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825269215 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.3825269215 |
| Directory | /workspace/36.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3762331897 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 408549420 ps |
| CPU time | 1.09 seconds |
| Started | Jan 14 01:24:57 PM PST 24 |
| Finished | Jan 14 01:24:59 PM PST 24 |
| Peak memory | 182672 kb |
| Host | smart-ddeedd4b-fe6f-4eea-a66c-7332eddaaa14 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762331897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.3762331897 |
| Directory | /workspace/37.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/37.rv_timer_disabled.1155121015 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 56079750731 ps |
| CPU time | 90.12 seconds |
| Started | Jan 14 01:24:55 PM PST 24 |
| Finished | Jan 14 01:26:26 PM PST 24 |
| Peak memory | 182996 kb |
| Host | smart-3ca7a1e5-9bab-422e-b81b-6230918561bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1155121015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1155121015 |
| Directory | /workspace/37.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/37.rv_timer_random_reset.3072104965 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 59823748 ps |
| CPU time | 0.62 seconds |
| Started | Jan 14 01:24:58 PM PST 24 |
| Finished | Jan 14 01:25:00 PM PST 24 |
| Peak memory | 182408 kb |
| Host | smart-5499d6aa-0393-4580-8bed-82228b4add08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3072104965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3072104965 |
| Directory | /workspace/37.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.4208543908 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 99973637778 ps |
| CPU time | 735.81 seconds |
| Started | Jan 14 01:25:00 PM PST 24 |
| Finished | Jan 14 01:37:22 PM PST 24 |
| Peak memory | 207920 kb |
| Host | smart-7314ae4f-cce7-4ab3-a1f7-32979e091f3b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208543908 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.4208543908 |
| Directory | /workspace/37.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.rv_timer_disabled.2250349598 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 203591395660 ps |
| CPU time | 141.43 seconds |
| Started | Jan 14 01:24:54 PM PST 24 |
| Finished | Jan 14 01:27:17 PM PST 24 |
| Peak memory | 182924 kb |
| Host | smart-5bb52303-19c1-4a30-942f-d5f4a4100a22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2250349598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2250349598 |
| Directory | /workspace/38.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/38.rv_timer_random.1013237236 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 449873092459 ps |
| CPU time | 2664.75 seconds |
| Started | Jan 14 01:24:59 PM PST 24 |
| Finished | Jan 14 02:09:30 PM PST 24 |
| Peak memory | 191140 kb |
| Host | smart-20b71ea1-b1d5-4f52-87ef-4263d3a34d29 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013237236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1013237236 |
| Directory | /workspace/38.rv_timer_random/latest |
| Test location | /workspace/coverage/default/38.rv_timer_random_reset.3787637502 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 42622707127 ps |
| CPU time | 438.68 seconds |
| Started | Jan 14 01:25:03 PM PST 24 |
| Finished | Jan 14 01:32:25 PM PST 24 |
| Peak memory | 191176 kb |
| Host | smart-b9c5c31c-d2e9-4016-90e1-f60794467faa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3787637502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.3787637502 |
| Directory | /workspace/38.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.2368718858 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 118327806897 ps |
| CPU time | 1245.41 seconds |
| Started | Jan 14 01:24:58 PM PST 24 |
| Finished | Jan 14 01:45:44 PM PST 24 |
| Peak memory | 211148 kb |
| Host | smart-1a283ec3-5c79-4c1c-a47e-230dce99ab33 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368718858 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.2368718858 |
| Directory | /workspace/38.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3933317023 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 29737009635 ps |
| CPU time | 24.35 seconds |
| Started | Jan 14 01:25:00 PM PST 24 |
| Finished | Jan 14 01:25:30 PM PST 24 |
| Peak memory | 182980 kb |
| Host | smart-fa47443f-fa89-4d4f-958d-f13998ed8fe5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933317023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.3933317023 |
| Directory | /workspace/39.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/39.rv_timer_disabled.3871033085 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 235628003283 ps |
| CPU time | 171.31 seconds |
| Started | Jan 14 01:25:00 PM PST 24 |
| Finished | Jan 14 01:27:57 PM PST 24 |
| Peak memory | 182992 kb |
| Host | smart-4cff8040-6c1d-49d0-bffd-2038ce191d50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3871033085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3871033085 |
| Directory | /workspace/39.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/39.rv_timer_random.767551367 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 207392670043 ps |
| CPU time | 460.26 seconds |
| Started | Jan 14 01:24:54 PM PST 24 |
| Finished | Jan 14 01:32:36 PM PST 24 |
| Peak memory | 191196 kb |
| Host | smart-244b2a52-788f-41b9-b6d5-c0da135aeb81 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767551367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.767551367 |
| Directory | /workspace/39.rv_timer_random/latest |
| Test location | /workspace/coverage/default/39.rv_timer_random_reset.2657883014 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 66733121343 ps |
| CPU time | 1066.29 seconds |
| Started | Jan 14 01:25:01 PM PST 24 |
| Finished | Jan 14 01:42:52 PM PST 24 |
| Peak memory | 182952 kb |
| Host | smart-bc9dff81-18b3-4331-a60c-37a7dc0b64b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2657883014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2657883014 |
| Directory | /workspace/39.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.91775857 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 43594061817 ps |
| CPU time | 238.22 seconds |
| Started | Jan 14 01:24:59 PM PST 24 |
| Finished | Jan 14 01:29:04 PM PST 24 |
| Peak memory | 205948 kb |
| Host | smart-99dfa2a9-6913-43cd-9409-d088bfb3ba63 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91775857 -assert nopos tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.91775857 |
| Directory | /workspace/39.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.4010898689 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 1127902949087 ps |
| CPU time | 430.89 seconds |
| Started | Jan 14 01:24:02 PM PST 24 |
| Finished | Jan 14 01:31:14 PM PST 24 |
| Peak memory | 182932 kb |
| Host | smart-a8b3674a-a186-49e3-894d-ec9dfcd4f797 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010898689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_cfg_update_on_fly.4010898689 |
| Directory | /workspace/4.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/4.rv_timer_random.1857034208 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1275073702 ps |
| CPU time | 1.67 seconds |
| Started | Jan 14 01:23:59 PM PST 24 |
| Finished | Jan 14 01:24:02 PM PST 24 |
| Peak memory | 182960 kb |
| Host | smart-61e8728b-cc34-4213-b761-e7d73b065def |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857034208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.1857034208 |
| Directory | /workspace/4.rv_timer_random/latest |
| Test location | /workspace/coverage/default/4.rv_timer_random_reset.224490871 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 53176860 ps |
| CPU time | 0.62 seconds |
| Started | Jan 14 01:23:59 PM PST 24 |
| Finished | Jan 14 01:24:00 PM PST 24 |
| Peak memory | 182308 kb |
| Host | smart-bd1e2a06-d4be-48a4-bbee-0513882cf184 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=224490871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.224490871 |
| Directory | /workspace/4.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/4.rv_timer_sec_cm.1425882140 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 330765268 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 01:23:55 PM PST 24 |
| Finished | Jan 14 01:23:57 PM PST 24 |
| Peak memory | 212888 kb |
| Host | smart-6ea39739-8e41-4aca-a068-c6e203e962a0 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425882140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1425882140 |
| Directory | /workspace/4.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/4.rv_timer_stress_all.1468214493 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 314819925155 ps |
| CPU time | 1448.04 seconds |
| Started | Jan 14 01:24:00 PM PST 24 |
| Finished | Jan 14 01:48:09 PM PST 24 |
| Peak memory | 191156 kb |
| Host | smart-3281c0ce-dbe3-4a0e-b4e7-8bd60522b8e0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468214493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all. 1468214493 |
| Directory | /workspace/4.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.4219442415 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 429632148892 ps |
| CPU time | 367.77 seconds |
| Started | Jan 14 01:24:02 PM PST 24 |
| Finished | Jan 14 01:30:11 PM PST 24 |
| Peak memory | 205844 kb |
| Host | smart-f66f8259-45c7-49d3-aba8-2c5b2aa68f1d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219442415 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.4219442415 |
| Directory | /workspace/4.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.2379950724 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 267811329925 ps |
| CPU time | 158.3 seconds |
| Started | Jan 14 01:25:04 PM PST 24 |
| Finished | Jan 14 01:27:45 PM PST 24 |
| Peak memory | 182960 kb |
| Host | smart-083a553d-9695-4fd1-9b84-9b5e54b7c0fe |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379950724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.2379950724 |
| Directory | /workspace/40.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/40.rv_timer_disabled.2811934180 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 46785175389 ps |
| CPU time | 18.68 seconds |
| Started | Jan 14 01:25:02 PM PST 24 |
| Finished | Jan 14 01:25:25 PM PST 24 |
| Peak memory | 182916 kb |
| Host | smart-062d362e-5baa-453d-ae91-90c565970c09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2811934180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2811934180 |
| Directory | /workspace/40.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/40.rv_timer_random.557237572 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 49793809633 ps |
| CPU time | 1806.74 seconds |
| Started | Jan 14 01:25:02 PM PST 24 |
| Finished | Jan 14 01:55:13 PM PST 24 |
| Peak memory | 182928 kb |
| Host | smart-bd0bb873-3181-4737-809a-364369a41f84 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557237572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.557237572 |
| Directory | /workspace/40.rv_timer_random/latest |
| Test location | /workspace/coverage/default/40.rv_timer_random_reset.3671397079 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 170474012 ps |
| CPU time | 0.8 seconds |
| Started | Jan 14 01:25:02 PM PST 24 |
| Finished | Jan 14 01:25:07 PM PST 24 |
| Peak memory | 182692 kb |
| Host | smart-aec72da0-8eb9-436e-8bd9-51bac91516b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3671397079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3671397079 |
| Directory | /workspace/40.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.1764649216 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 16660213354 ps |
| CPU time | 140.89 seconds |
| Started | Jan 14 01:25:03 PM PST 24 |
| Finished | Jan 14 01:27:27 PM PST 24 |
| Peak memory | 197536 kb |
| Host | smart-c431db66-f611-41fe-93a7-65a16bbdf6ff |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764649216 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.1764649216 |
| Directory | /workspace/40.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.4194202807 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 410034744133 ps |
| CPU time | 139.07 seconds |
| Started | Jan 14 01:25:04 PM PST 24 |
| Finished | Jan 14 01:27:26 PM PST 24 |
| Peak memory | 182924 kb |
| Host | smart-10f55295-1aad-4824-9ec7-2c13eba38124 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194202807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.4194202807 |
| Directory | /workspace/41.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/41.rv_timer_disabled.3378083426 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 126268095126 ps |
| CPU time | 187.09 seconds |
| Started | Jan 14 01:25:00 PM PST 24 |
| Finished | Jan 14 01:28:13 PM PST 24 |
| Peak memory | 182756 kb |
| Host | smart-affd1b66-f9dd-418e-8a65-4c97c2627113 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3378083426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3378083426 |
| Directory | /workspace/41.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/41.rv_timer_random.1782633325 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 502652139134 ps |
| CPU time | 626.34 seconds |
| Started | Jan 14 01:25:02 PM PST 24 |
| Finished | Jan 14 01:35:32 PM PST 24 |
| Peak memory | 191184 kb |
| Host | smart-97c8bf94-418f-4bd8-9dba-f6330dea8d27 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782633325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1782633325 |
| Directory | /workspace/41.rv_timer_random/latest |
| Test location | /workspace/coverage/default/41.rv_timer_random_reset.2931167165 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 17566290555 ps |
| CPU time | 55.88 seconds |
| Started | Jan 14 01:25:00 PM PST 24 |
| Finished | Jan 14 01:26:02 PM PST 24 |
| Peak memory | 191132 kb |
| Host | smart-389b8d95-c123-4601-a098-fccc28afd130 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2931167165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2931167165 |
| Directory | /workspace/41.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.3988833920 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 58706168202 ps |
| CPU time | 547.82 seconds |
| Started | Jan 14 01:25:01 PM PST 24 |
| Finished | Jan 14 01:34:14 PM PST 24 |
| Peak memory | 205832 kb |
| Host | smart-3cfbd90a-99f8-476c-83bf-c4e261c2b174 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988833920 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.3988833920 |
| Directory | /workspace/41.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1883700384 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 423793313801 ps |
| CPU time | 405.04 seconds |
| Started | Jan 14 01:25:06 PM PST 24 |
| Finished | Jan 14 01:31:54 PM PST 24 |
| Peak memory | 182968 kb |
| Host | smart-a9482a3f-0eb6-4963-b9ed-5af2d0fa5160 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883700384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.1883700384 |
| Directory | /workspace/42.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/42.rv_timer_disabled.3017526268 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 368382340846 ps |
| CPU time | 163.27 seconds |
| Started | Jan 14 01:25:04 PM PST 24 |
| Finished | Jan 14 01:27:50 PM PST 24 |
| Peak memory | 183008 kb |
| Host | smart-5127b665-125e-4379-959e-ee27c99cf1f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3017526268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3017526268 |
| Directory | /workspace/42.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/42.rv_timer_random.1798314958 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 74877469545 ps |
| CPU time | 358.44 seconds |
| Started | Jan 14 01:25:03 PM PST 24 |
| Finished | Jan 14 01:31:05 PM PST 24 |
| Peak memory | 191160 kb |
| Host | smart-e646af5c-951c-44ad-9664-96896e7c83f8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798314958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1798314958 |
| Directory | /workspace/42.rv_timer_random/latest |
| Test location | /workspace/coverage/default/42.rv_timer_random_reset.3520058476 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 101740561309 ps |
| CPU time | 1696.27 seconds |
| Started | Jan 14 01:25:07 PM PST 24 |
| Finished | Jan 14 01:53:26 PM PST 24 |
| Peak memory | 191084 kb |
| Host | smart-5c30133d-df2c-4632-b49e-3bb25f74bb61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3520058476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.3520058476 |
| Directory | /workspace/42.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.4283135714 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 203918947886 ps |
| CPU time | 1069.91 seconds |
| Started | Jan 14 01:25:02 PM PST 24 |
| Finished | Jan 14 01:42:56 PM PST 24 |
| Peak memory | 202888 kb |
| Host | smart-ebedd762-f51d-4cd3-9bd5-5d05b120e205 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283135714 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.4283135714 |
| Directory | /workspace/42.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3836826457 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 1342934097662 ps |
| CPU time | 727.45 seconds |
| Started | Jan 14 01:25:11 PM PST 24 |
| Finished | Jan 14 01:37:19 PM PST 24 |
| Peak memory | 182988 kb |
| Host | smart-18db952e-4d51-41ea-84e2-b0bcf459b13f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836826457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.3836826457 |
| Directory | /workspace/43.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/43.rv_timer_disabled.64019087 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 317995577173 ps |
| CPU time | 253.88 seconds |
| Started | Jan 14 01:25:10 PM PST 24 |
| Finished | Jan 14 01:29:25 PM PST 24 |
| Peak memory | 182920 kb |
| Host | smart-57404dcf-de21-4cc9-afcd-0220b85df280 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=64019087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.64019087 |
| Directory | /workspace/43.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/43.rv_timer_random.3523046434 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 526758685248 ps |
| CPU time | 1634.42 seconds |
| Started | Jan 14 01:25:08 PM PST 24 |
| Finished | Jan 14 01:52:24 PM PST 24 |
| Peak memory | 191168 kb |
| Host | smart-59c58472-00c4-40dd-a6e2-e30315d82fdb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523046434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3523046434 |
| Directory | /workspace/43.rv_timer_random/latest |
| Test location | /workspace/coverage/default/43.rv_timer_random_reset.802163958 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 68074001141 ps |
| CPU time | 117.5 seconds |
| Started | Jan 14 01:25:06 PM PST 24 |
| Finished | Jan 14 01:27:07 PM PST 24 |
| Peak memory | 191176 kb |
| Host | smart-71fca799-3ee9-40bd-9e03-d0803828cb2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=802163958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.802163958 |
| Directory | /workspace/43.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/43.rv_timer_stress_all.1882504202 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 281839554469 ps |
| CPU time | 202.09 seconds |
| Started | Jan 14 01:25:09 PM PST 24 |
| Finished | Jan 14 01:28:32 PM PST 24 |
| Peak memory | 182948 kb |
| Host | smart-02c3e9c1-3d9d-46a8-8f3c-efaff8a4e3ff |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882504202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all .1882504202 |
| Directory | /workspace/43.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.622474692 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 407062170794 ps |
| CPU time | 897.82 seconds |
| Started | Jan 14 01:25:18 PM PST 24 |
| Finished | Jan 14 01:40:17 PM PST 24 |
| Peak memory | 211728 kb |
| Host | smart-8c34cc2a-4834-41d8-ab2c-aa448a6199ab |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622474692 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.622474692 |
| Directory | /workspace/43.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1465874476 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 2887113520872 ps |
| CPU time | 708.78 seconds |
| Started | Jan 14 01:25:21 PM PST 24 |
| Finished | Jan 14 01:37:10 PM PST 24 |
| Peak memory | 182904 kb |
| Host | smart-03edce4a-918f-4f52-8121-68bbc09c4480 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465874476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_cfg_update_on_fly.1465874476 |
| Directory | /workspace/44.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/44.rv_timer_disabled.3389607126 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 396041811678 ps |
| CPU time | 157.49 seconds |
| Started | Jan 14 01:25:11 PM PST 24 |
| Finished | Jan 14 01:27:50 PM PST 24 |
| Peak memory | 182856 kb |
| Host | smart-e2a26030-06aa-4d84-aa9d-7bf9339fd582 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3389607126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3389607126 |
| Directory | /workspace/44.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/44.rv_timer_random.1726498050 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 335143921031 ps |
| CPU time | 235.04 seconds |
| Started | Jan 14 01:25:21 PM PST 24 |
| Finished | Jan 14 01:29:17 PM PST 24 |
| Peak memory | 191080 kb |
| Host | smart-cf9d6e7d-56bc-40eb-9d53-70c12eddcce0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726498050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1726498050 |
| Directory | /workspace/44.rv_timer_random/latest |
| Test location | /workspace/coverage/default/44.rv_timer_random_reset.3001257730 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 36467296185 ps |
| CPU time | 417.53 seconds |
| Started | Jan 14 01:25:12 PM PST 24 |
| Finished | Jan 14 01:32:10 PM PST 24 |
| Peak memory | 191132 kb |
| Host | smart-585499c0-0dce-427b-9ea3-aeaeae5e6cba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3001257730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3001257730 |
| Directory | /workspace/44.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/44.rv_timer_stress_all.772398264 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 1132660855659 ps |
| CPU time | 1306.57 seconds |
| Started | Jan 14 01:25:23 PM PST 24 |
| Finished | Jan 14 01:47:11 PM PST 24 |
| Peak memory | 191096 kb |
| Host | smart-0906ffe0-83b2-4fce-afaf-5175d044da31 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772398264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all. 772398264 |
| Directory | /workspace/44.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.3353040915 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 16171550316 ps |
| CPU time | 117.44 seconds |
| Started | Jan 14 01:25:11 PM PST 24 |
| Finished | Jan 14 01:27:09 PM PST 24 |
| Peak memory | 197660 kb |
| Host | smart-2c7ca67f-da8c-4cf0-80d0-f9fc9e1d49a0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353040915 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.3353040915 |
| Directory | /workspace/44.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/45.rv_timer_disabled.3386272298 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 178595490870 ps |
| CPU time | 64.27 seconds |
| Started | Jan 14 01:25:10 PM PST 24 |
| Finished | Jan 14 01:26:15 PM PST 24 |
| Peak memory | 182996 kb |
| Host | smart-aa44a6e4-0aad-4fb4-9407-4b4034c99ab0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3386272298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3386272298 |
| Directory | /workspace/45.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/45.rv_timer_random.3448401160 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 495384852377 ps |
| CPU time | 218.05 seconds |
| Started | Jan 14 01:25:06 PM PST 24 |
| Finished | Jan 14 01:28:47 PM PST 24 |
| Peak memory | 191196 kb |
| Host | smart-81d2c299-ab4d-42bb-b08b-def1d43c6913 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448401160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3448401160 |
| Directory | /workspace/45.rv_timer_random/latest |
| Test location | /workspace/coverage/default/45.rv_timer_random_reset.1651471491 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 29716104129 ps |
| CPU time | 52.79 seconds |
| Started | Jan 14 01:25:11 PM PST 24 |
| Finished | Jan 14 01:26:05 PM PST 24 |
| Peak memory | 182768 kb |
| Host | smart-27cace46-b7f4-4a82-a8d6-ef4e8025d2b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1651471491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1651471491 |
| Directory | /workspace/45.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/45.rv_timer_stress_all.673394264 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 14058592648 ps |
| CPU time | 19.96 seconds |
| Started | Jan 14 01:25:05 PM PST 24 |
| Finished | Jan 14 01:25:27 PM PST 24 |
| Peak memory | 182960 kb |
| Host | smart-094b2ad3-da66-472b-a572-82554625b87a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673394264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all. 673394264 |
| Directory | /workspace/45.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/46.rv_timer_disabled.1598186703 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 165770582486 ps |
| CPU time | 253.63 seconds |
| Started | Jan 14 01:25:13 PM PST 24 |
| Finished | Jan 14 01:29:28 PM PST 24 |
| Peak memory | 182996 kb |
| Host | smart-9f7366b0-396d-4065-80f1-5cc02f167b88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1598186703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1598186703 |
| Directory | /workspace/46.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/46.rv_timer_random_reset.2851161145 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 10926305379 ps |
| CPU time | 82.46 seconds |
| Started | Jan 14 01:25:22 PM PST 24 |
| Finished | Jan 14 01:26:46 PM PST 24 |
| Peak memory | 182916 kb |
| Host | smart-67843f7b-8b35-4801-9e77-b185b5aed6c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2851161145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2851161145 |
| Directory | /workspace/46.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/46.rv_timer_stress_all.2211416729 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 76219160667 ps |
| CPU time | 43.03 seconds |
| Started | Jan 14 01:25:19 PM PST 24 |
| Finished | Jan 14 01:26:03 PM PST 24 |
| Peak memory | 182976 kb |
| Host | smart-7a7da418-44ce-4b2e-8e64-cc7d830b8a71 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211416729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all .2211416729 |
| Directory | /workspace/46.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.439051811 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 293336165805 ps |
| CPU time | 833.48 seconds |
| Started | Jan 14 01:25:19 PM PST 24 |
| Finished | Jan 14 01:39:14 PM PST 24 |
| Peak memory | 213596 kb |
| Host | smart-796e3738-b3e5-4b35-9d61-c3772ab6eeaf |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439051811 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.439051811 |
| Directory | /workspace/46.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1715336542 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 9311062887 ps |
| CPU time | 17.13 seconds |
| Started | Jan 14 01:25:19 PM PST 24 |
| Finished | Jan 14 01:25:37 PM PST 24 |
| Peak memory | 183000 kb |
| Host | smart-b38205c7-6f30-4b65-8616-9c605ee7c2e4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715336542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_cfg_update_on_fly.1715336542 |
| Directory | /workspace/47.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/47.rv_timer_disabled.1746934766 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 396666365436 ps |
| CPU time | 256.78 seconds |
| Started | Jan 14 01:25:16 PM PST 24 |
| Finished | Jan 14 01:29:33 PM PST 24 |
| Peak memory | 182996 kb |
| Host | smart-2d271f2e-2395-4717-a396-7486a5b83f4e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1746934766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.1746934766 |
| Directory | /workspace/47.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/47.rv_timer_random.3479107381 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 152036246652 ps |
| CPU time | 250.8 seconds |
| Started | Jan 14 01:25:12 PM PST 24 |
| Finished | Jan 14 01:29:24 PM PST 24 |
| Peak memory | 191128 kb |
| Host | smart-1f631bbd-3501-4947-81e9-157fd6803136 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479107381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3479107381 |
| Directory | /workspace/47.rv_timer_random/latest |
| Test location | /workspace/coverage/default/47.rv_timer_random_reset.521852197 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 101677429921 ps |
| CPU time | 187.09 seconds |
| Started | Jan 14 01:25:19 PM PST 24 |
| Finished | Jan 14 01:28:27 PM PST 24 |
| Peak memory | 183000 kb |
| Host | smart-4cceed57-cb85-4970-a82b-603733110be8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=521852197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.521852197 |
| Directory | /workspace/47.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/47.rv_timer_stress_all.3851786528 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 226197967566 ps |
| CPU time | 349.94 seconds |
| Started | Jan 14 01:25:21 PM PST 24 |
| Finished | Jan 14 01:31:12 PM PST 24 |
| Peak memory | 191152 kb |
| Host | smart-561894b8-8ca8-4446-9c40-5e05d3e96f7e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851786528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all .3851786528 |
| Directory | /workspace/47.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.3813503450 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 80640149548 ps |
| CPU time | 961.96 seconds |
| Started | Jan 14 01:25:23 PM PST 24 |
| Finished | Jan 14 01:41:26 PM PST 24 |
| Peak memory | 205708 kb |
| Host | smart-4f078e1e-784e-474f-aacd-f61a010d610a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813503450 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.3813503450 |
| Directory | /workspace/47.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.699266660 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 351964089035 ps |
| CPU time | 594.06 seconds |
| Started | Jan 14 01:25:20 PM PST 24 |
| Finished | Jan 14 01:35:15 PM PST 24 |
| Peak memory | 182920 kb |
| Host | smart-d197b6f1-4721-449a-869f-976ff93f7ae0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699266660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.rv_timer_cfg_update_on_fly.699266660 |
| Directory | /workspace/48.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/48.rv_timer_disabled.1275065097 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 68118131476 ps |
| CPU time | 27.24 seconds |
| Started | Jan 14 01:25:20 PM PST 24 |
| Finished | Jan 14 01:25:48 PM PST 24 |
| Peak memory | 182972 kb |
| Host | smart-06928519-fb66-4509-86ac-9d69e332c667 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1275065097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1275065097 |
| Directory | /workspace/48.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/48.rv_timer_random.2654840803 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 171431146971 ps |
| CPU time | 109.8 seconds |
| Started | Jan 14 01:25:13 PM PST 24 |
| Finished | Jan 14 01:27:04 PM PST 24 |
| Peak memory | 191112 kb |
| Host | smart-805ac5e8-6b0c-4b60-bc60-577e823d3735 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654840803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2654840803 |
| Directory | /workspace/48.rv_timer_random/latest |
| Test location | /workspace/coverage/default/48.rv_timer_random_reset.3253371054 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 34828231 ps |
| CPU time | 0.54 seconds |
| Started | Jan 14 01:25:21 PM PST 24 |
| Finished | Jan 14 01:25:22 PM PST 24 |
| Peak memory | 182540 kb |
| Host | smart-3a245bea-56d7-4667-b07c-449515993d10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3253371054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3253371054 |
| Directory | /workspace/48.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/48.rv_timer_stress_all.1634373917 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 214995855841 ps |
| CPU time | 1538.49 seconds |
| Started | Jan 14 01:25:19 PM PST 24 |
| Finished | Jan 14 01:50:59 PM PST 24 |
| Peak memory | 195072 kb |
| Host | smart-186d6744-e014-49e5-abe1-370107364fa0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634373917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all .1634373917 |
| Directory | /workspace/48.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.1074627916 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 143225429089 ps |
| CPU time | 581.69 seconds |
| Started | Jan 14 01:25:20 PM PST 24 |
| Finished | Jan 14 01:35:03 PM PST 24 |
| Peak memory | 205872 kb |
| Host | smart-321d8d67-00d9-470c-bf22-7894323ebaca |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074627916 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.1074627916 |
| Directory | /workspace/48.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.322245245 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 74971862572 ps |
| CPU time | 116.88 seconds |
| Started | Jan 14 01:25:19 PM PST 24 |
| Finished | Jan 14 01:27:17 PM PST 24 |
| Peak memory | 182796 kb |
| Host | smart-dc066ac6-89f9-4ae1-b625-79e46682181d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322245245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.rv_timer_cfg_update_on_fly.322245245 |
| Directory | /workspace/49.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/49.rv_timer_disabled.4284328279 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 82793132531 ps |
| CPU time | 115.97 seconds |
| Started | Jan 14 01:25:15 PM PST 24 |
| Finished | Jan 14 01:27:12 PM PST 24 |
| Peak memory | 182856 kb |
| Host | smart-ae40e6de-4ff1-4953-a196-635d1bbc7596 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4284328279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.4284328279 |
| Directory | /workspace/49.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/49.rv_timer_random.789058924 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 59651306146 ps |
| CPU time | 117.93 seconds |
| Started | Jan 14 01:25:17 PM PST 24 |
| Finished | Jan 14 01:27:15 PM PST 24 |
| Peak memory | 191184 kb |
| Host | smart-30bfd72a-ad5c-47f9-85df-1355255469d4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789058924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.789058924 |
| Directory | /workspace/49.rv_timer_random/latest |
| Test location | /workspace/coverage/default/49.rv_timer_random_reset.3449702272 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 409062374 ps |
| CPU time | 0.75 seconds |
| Started | Jan 14 01:25:16 PM PST 24 |
| Finished | Jan 14 01:25:17 PM PST 24 |
| Peak memory | 182728 kb |
| Host | smart-81e9aa8d-fd82-4cd8-bee8-4268415dd470 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3449702272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3449702272 |
| Directory | /workspace/49.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.3564024104 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 83244487100 ps |
| CPU time | 785.19 seconds |
| Started | Jan 14 01:25:22 PM PST 24 |
| Finished | Jan 14 01:38:28 PM PST 24 |
| Peak memory | 208260 kb |
| Host | smart-077ac71e-fd53-4383-b4d1-8407462ba888 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564024104 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.3564024104 |
| Directory | /workspace/49.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.16483840 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 62121920000 ps |
| CPU time | 36.96 seconds |
| Started | Jan 14 01:24:07 PM PST 24 |
| Finished | Jan 14 01:24:44 PM PST 24 |
| Peak memory | 182872 kb |
| Host | smart-8bb974f7-7d17-4bca-aba6-ce2471987696 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16483840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5. rv_timer_cfg_update_on_fly.16483840 |
| Directory | /workspace/5.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/5.rv_timer_disabled.1959762249 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 125209508409 ps |
| CPU time | 177.35 seconds |
| Started | Jan 14 01:24:01 PM PST 24 |
| Finished | Jan 14 01:26:59 PM PST 24 |
| Peak memory | 182960 kb |
| Host | smart-fac49fa5-9a22-4d6f-a9f2-9b75e55b19ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1959762249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1959762249 |
| Directory | /workspace/5.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/5.rv_timer_random_reset.2719106501 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 76586695 ps |
| CPU time | 0.64 seconds |
| Started | Jan 14 01:23:59 PM PST 24 |
| Finished | Jan 14 01:24:00 PM PST 24 |
| Peak memory | 182696 kb |
| Host | smart-6e53add7-14a5-47ea-b354-fce99514a913 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2719106501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2719106501 |
| Directory | /workspace/5.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.2544865711 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 283633188187 ps |
| CPU time | 1095.36 seconds |
| Started | Jan 14 01:24:02 PM PST 24 |
| Finished | Jan 14 01:42:19 PM PST 24 |
| Peak memory | 212212 kb |
| Host | smart-00c11ad9-d285-47dc-b594-aa0cf2b0a3b2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544865711 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.2544865711 |
| Directory | /workspace/5.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/50.rv_timer_random.681765237 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 94656372884 ps |
| CPU time | 204.07 seconds |
| Started | Jan 14 01:25:35 PM PST 24 |
| Finished | Jan 14 01:29:00 PM PST 24 |
| Peak memory | 191112 kb |
| Host | smart-c17c0336-ac9d-4131-b9d4-e200da734c58 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681765237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.681765237 |
| Directory | /workspace/50.rv_timer_random/latest |
| Test location | /workspace/coverage/default/51.rv_timer_random.2550678584 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 303178090897 ps |
| CPU time | 572.16 seconds |
| Started | Jan 14 01:25:34 PM PST 24 |
| Finished | Jan 14 01:35:07 PM PST 24 |
| Peak memory | 193156 kb |
| Host | smart-01a48a7f-8860-4ef6-8ce6-d157762dc684 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550678584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2550678584 |
| Directory | /workspace/51.rv_timer_random/latest |
| Test location | /workspace/coverage/default/52.rv_timer_random.3366148091 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 126924293840 ps |
| CPU time | 777.91 seconds |
| Started | Jan 14 01:25:36 PM PST 24 |
| Finished | Jan 14 01:38:35 PM PST 24 |
| Peak memory | 191220 kb |
| Host | smart-bd546d11-e45e-4fb6-a408-51f767b82917 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366148091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3366148091 |
| Directory | /workspace/52.rv_timer_random/latest |
| Test location | /workspace/coverage/default/53.rv_timer_random.2902896386 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 196745619975 ps |
| CPU time | 354.56 seconds |
| Started | Jan 14 01:25:23 PM PST 24 |
| Finished | Jan 14 01:31:19 PM PST 24 |
| Peak memory | 191060 kb |
| Host | smart-d2a03c60-2438-4ba4-89ce-50703ea0a069 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902896386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2902896386 |
| Directory | /workspace/53.rv_timer_random/latest |
| Test location | /workspace/coverage/default/54.rv_timer_random.3653767424 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 60228774869 ps |
| CPU time | 127.05 seconds |
| Started | Jan 14 01:25:23 PM PST 24 |
| Finished | Jan 14 01:27:31 PM PST 24 |
| Peak memory | 193208 kb |
| Host | smart-7f1591ff-d6e2-48b4-9e8d-2d4bfd0e22b3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653767424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3653767424 |
| Directory | /workspace/54.rv_timer_random/latest |
| Test location | /workspace/coverage/default/55.rv_timer_random.1668090824 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 198140637191 ps |
| CPU time | 89.61 seconds |
| Started | Jan 14 01:25:23 PM PST 24 |
| Finished | Jan 14 01:26:53 PM PST 24 |
| Peak memory | 191164 kb |
| Host | smart-f3a5ecc4-29aa-4940-a14e-13a4d086c637 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668090824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1668090824 |
| Directory | /workspace/55.rv_timer_random/latest |
| Test location | /workspace/coverage/default/56.rv_timer_random.2090738622 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 68745617340 ps |
| CPU time | 60.44 seconds |
| Started | Jan 14 01:25:23 PM PST 24 |
| Finished | Jan 14 01:26:25 PM PST 24 |
| Peak memory | 191204 kb |
| Host | smart-2216f0c6-e7db-4c06-8513-8d9cbfec0b15 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090738622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2090738622 |
| Directory | /workspace/56.rv_timer_random/latest |
| Test location | /workspace/coverage/default/57.rv_timer_random.3816037371 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 368427232429 ps |
| CPU time | 255.5 seconds |
| Started | Jan 14 01:25:34 PM PST 24 |
| Finished | Jan 14 01:29:51 PM PST 24 |
| Peak memory | 191096 kb |
| Host | smart-1e189767-541e-4c92-a45c-684c96620102 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816037371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3816037371 |
| Directory | /workspace/57.rv_timer_random/latest |
| Test location | /workspace/coverage/default/58.rv_timer_random.3792404993 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 308523495063 ps |
| CPU time | 722.97 seconds |
| Started | Jan 14 01:25:25 PM PST 24 |
| Finished | Jan 14 01:37:29 PM PST 24 |
| Peak memory | 191176 kb |
| Host | smart-9f3970be-a541-4a6e-b106-469fd75b53b4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792404993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3792404993 |
| Directory | /workspace/58.rv_timer_random/latest |
| Test location | /workspace/coverage/default/59.rv_timer_random.3219034517 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 467833846546 ps |
| CPU time | 275.28 seconds |
| Started | Jan 14 01:25:23 PM PST 24 |
| Finished | Jan 14 01:29:59 PM PST 24 |
| Peak memory | 191176 kb |
| Host | smart-b2d0ef91-e00b-4f26-820b-0adf34e513b9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219034517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3219034517 |
| Directory | /workspace/59.rv_timer_random/latest |
| Test location | /workspace/coverage/default/6.rv_timer_disabled.750037561 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 53419447804 ps |
| CPU time | 9.03 seconds |
| Started | Jan 14 01:23:58 PM PST 24 |
| Finished | Jan 14 01:24:07 PM PST 24 |
| Peak memory | 182944 kb |
| Host | smart-a987f98d-6092-4ed1-9164-2482e674a9ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=750037561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.750037561 |
| Directory | /workspace/6.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/6.rv_timer_random.683872169 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 80056978555 ps |
| CPU time | 139.32 seconds |
| Started | Jan 14 01:24:05 PM PST 24 |
| Finished | Jan 14 01:26:25 PM PST 24 |
| Peak memory | 193908 kb |
| Host | smart-0af70de1-f5ad-4fef-bfa0-3aea84d927ab |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683872169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.683872169 |
| Directory | /workspace/6.rv_timer_random/latest |
| Test location | /workspace/coverage/default/6.rv_timer_random_reset.3746318711 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 1723887938 ps |
| CPU time | 1.05 seconds |
| Started | Jan 14 01:24:05 PM PST 24 |
| Finished | Jan 14 01:24:07 PM PST 24 |
| Peak memory | 192424 kb |
| Host | smart-6ee11d37-eecc-42b7-a2eb-2d254647c993 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3746318711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3746318711 |
| Directory | /workspace/6.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.3191967623 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 224850003295 ps |
| CPU time | 682.04 seconds |
| Started | Jan 14 01:24:06 PM PST 24 |
| Finished | Jan 14 01:35:29 PM PST 24 |
| Peak memory | 212972 kb |
| Host | smart-143ff3a1-dc8a-4863-abec-39587d6abf73 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191967623 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.3191967623 |
| Directory | /workspace/6.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/60.rv_timer_random.1526959747 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 381719244650 ps |
| CPU time | 137.32 seconds |
| Started | Jan 14 01:25:24 PM PST 24 |
| Finished | Jan 14 01:27:42 PM PST 24 |
| Peak memory | 182948 kb |
| Host | smart-c56252d0-285f-4edb-bd39-9cd477e3272c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526959747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.1526959747 |
| Directory | /workspace/60.rv_timer_random/latest |
| Test location | /workspace/coverage/default/62.rv_timer_random.3488239351 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 177930582410 ps |
| CPU time | 675.37 seconds |
| Started | Jan 14 01:25:34 PM PST 24 |
| Finished | Jan 14 01:36:50 PM PST 24 |
| Peak memory | 191132 kb |
| Host | smart-4e258611-3d46-494a-88d3-fc39ff95ebfb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488239351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3488239351 |
| Directory | /workspace/62.rv_timer_random/latest |
| Test location | /workspace/coverage/default/63.rv_timer_random.4049023434 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 136017603819 ps |
| CPU time | 64.31 seconds |
| Started | Jan 14 01:25:18 PM PST 24 |
| Finished | Jan 14 01:26:24 PM PST 24 |
| Peak memory | 183004 kb |
| Host | smart-4ee685c1-b7d8-4cd7-a38e-a40e2ff28fc6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049023434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.4049023434 |
| Directory | /workspace/63.rv_timer_random/latest |
| Test location | /workspace/coverage/default/65.rv_timer_random.1242784799 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 213798004852 ps |
| CPU time | 2256.65 seconds |
| Started | Jan 14 01:25:20 PM PST 24 |
| Finished | Jan 14 02:02:58 PM PST 24 |
| Peak memory | 193772 kb |
| Host | smart-46b1f993-7fc8-4c30-921a-f18d69ee1720 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242784799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1242784799 |
| Directory | /workspace/65.rv_timer_random/latest |
| Test location | /workspace/coverage/default/66.rv_timer_random.3182937224 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 422288272004 ps |
| CPU time | 170.4 seconds |
| Started | Jan 14 01:25:36 PM PST 24 |
| Finished | Jan 14 01:28:27 PM PST 24 |
| Peak memory | 193856 kb |
| Host | smart-3e2352a9-4df2-41be-8ca1-a685405a134c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182937224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.3182937224 |
| Directory | /workspace/66.rv_timer_random/latest |
| Test location | /workspace/coverage/default/68.rv_timer_random.1802795141 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 756428735553 ps |
| CPU time | 1310.07 seconds |
| Started | Jan 14 01:25:21 PM PST 24 |
| Finished | Jan 14 01:47:12 PM PST 24 |
| Peak memory | 191176 kb |
| Host | smart-c500a505-1ea0-4c41-88f6-88687f1657f3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802795141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1802795141 |
| Directory | /workspace/68.rv_timer_random/latest |
| Test location | /workspace/coverage/default/69.rv_timer_random.2877206684 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 638711695577 ps |
| CPU time | 524.43 seconds |
| Started | Jan 14 01:25:17 PM PST 24 |
| Finished | Jan 14 01:34:02 PM PST 24 |
| Peak memory | 194072 kb |
| Host | smart-93bc303f-6ce3-47b1-b1c4-8ed3a5a26207 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877206684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2877206684 |
| Directory | /workspace/69.rv_timer_random/latest |
| Test location | /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3948357595 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 881332689244 ps |
| CPU time | 635.42 seconds |
| Started | Jan 14 01:24:10 PM PST 24 |
| Finished | Jan 14 01:34:46 PM PST 24 |
| Peak memory | 183000 kb |
| Host | smart-51470a1c-5f4a-4002-9e8c-37279421d3a0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948357595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.3948357595 |
| Directory | /workspace/7.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/7.rv_timer_disabled.3786714435 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 213866248778 ps |
| CPU time | 72.85 seconds |
| Started | Jan 14 01:24:09 PM PST 24 |
| Finished | Jan 14 01:25:23 PM PST 24 |
| Peak memory | 182908 kb |
| Host | smart-a23fa8a2-d90b-4c07-be4e-db63b5c16ae2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3786714435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3786714435 |
| Directory | /workspace/7.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/7.rv_timer_random.2491598624 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 367597385225 ps |
| CPU time | 847.13 seconds |
| Started | Jan 14 01:24:11 PM PST 24 |
| Finished | Jan 14 01:38:19 PM PST 24 |
| Peak memory | 190792 kb |
| Host | smart-ecdb30cc-50c8-402d-a991-aa8950433021 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491598624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2491598624 |
| Directory | /workspace/7.rv_timer_random/latest |
| Test location | /workspace/coverage/default/7.rv_timer_random_reset.2976827687 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 36825984258 ps |
| CPU time | 60.97 seconds |
| Started | Jan 14 01:24:10 PM PST 24 |
| Finished | Jan 14 01:25:11 PM PST 24 |
| Peak memory | 183068 kb |
| Host | smart-14adc8bc-9856-4278-aec4-5e75516960c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2976827687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2976827687 |
| Directory | /workspace/7.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/7.rv_timer_stress_all.4084223128 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 377052156704 ps |
| CPU time | 198.96 seconds |
| Started | Jan 14 01:24:06 PM PST 24 |
| Finished | Jan 14 01:27:26 PM PST 24 |
| Peak memory | 191240 kb |
| Host | smart-d019d7ed-6f9d-473f-8193-a4fdad8e504d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084223128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all. 4084223128 |
| Directory | /workspace/7.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.1683988355 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 129584575977 ps |
| CPU time | 967.52 seconds |
| Started | Jan 14 01:24:08 PM PST 24 |
| Finished | Jan 14 01:40:16 PM PST 24 |
| Peak memory | 208136 kb |
| Host | smart-62f1646b-28d3-49bf-8600-e4ae65450087 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683988355 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.1683988355 |
| Directory | /workspace/7.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/70.rv_timer_random.2162093242 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 129808460086 ps |
| CPU time | 417.71 seconds |
| Started | Jan 14 01:25:24 PM PST 24 |
| Finished | Jan 14 01:32:23 PM PST 24 |
| Peak memory | 191160 kb |
| Host | smart-71bfc458-79a7-4a5b-bf6c-ff5c7ecb0e92 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162093242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.2162093242 |
| Directory | /workspace/70.rv_timer_random/latest |
| Test location | /workspace/coverage/default/71.rv_timer_random.2009611950 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 187585591537 ps |
| CPU time | 1190.34 seconds |
| Started | Jan 14 01:25:23 PM PST 24 |
| Finished | Jan 14 01:45:15 PM PST 24 |
| Peak memory | 193796 kb |
| Host | smart-a9da3848-2a9f-40f1-a3d1-00b4db0fa5c8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009611950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2009611950 |
| Directory | /workspace/71.rv_timer_random/latest |
| Test location | /workspace/coverage/default/72.rv_timer_random.1545267480 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 453871187558 ps |
| CPU time | 271.21 seconds |
| Started | Jan 14 01:25:34 PM PST 24 |
| Finished | Jan 14 01:30:06 PM PST 24 |
| Peak memory | 191096 kb |
| Host | smart-18e7d32e-a1a4-452d-a091-f76609269222 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545267480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1545267480 |
| Directory | /workspace/72.rv_timer_random/latest |
| Test location | /workspace/coverage/default/73.rv_timer_random.2629220196 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 238852139264 ps |
| CPU time | 99.01 seconds |
| Started | Jan 14 01:25:25 PM PST 24 |
| Finished | Jan 14 01:27:05 PM PST 24 |
| Peak memory | 193868 kb |
| Host | smart-23cde5ca-2148-41df-8ab3-ca04b5655ea0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629220196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2629220196 |
| Directory | /workspace/73.rv_timer_random/latest |
| Test location | /workspace/coverage/default/75.rv_timer_random.3172271454 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 33259792130 ps |
| CPU time | 411.78 seconds |
| Started | Jan 14 01:25:36 PM PST 24 |
| Finished | Jan 14 01:32:28 PM PST 24 |
| Peak memory | 183020 kb |
| Host | smart-68eb4bc4-48dc-4774-8593-ee7f2b7a1e84 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172271454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3172271454 |
| Directory | /workspace/75.rv_timer_random/latest |
| Test location | /workspace/coverage/default/77.rv_timer_random.623447055 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 118211939690 ps |
| CPU time | 181.35 seconds |
| Started | Jan 14 01:25:22 PM PST 24 |
| Finished | Jan 14 01:28:24 PM PST 24 |
| Peak memory | 193228 kb |
| Host | smart-af255aea-b4f9-4914-adec-f22fdaa5f7e2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623447055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.623447055 |
| Directory | /workspace/77.rv_timer_random/latest |
| Test location | /workspace/coverage/default/78.rv_timer_random.3674167972 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 18369839001 ps |
| CPU time | 117.15 seconds |
| Started | Jan 14 01:25:24 PM PST 24 |
| Finished | Jan 14 01:27:22 PM PST 24 |
| Peak memory | 194436 kb |
| Host | smart-f305c378-d047-433b-b6a7-e42c5334443b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674167972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3674167972 |
| Directory | /workspace/78.rv_timer_random/latest |
| Test location | /workspace/coverage/default/79.rv_timer_random.2290800521 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 165558112863 ps |
| CPU time | 317.77 seconds |
| Started | Jan 14 01:25:35 PM PST 24 |
| Finished | Jan 14 01:30:54 PM PST 24 |
| Peak memory | 191140 kb |
| Host | smart-4db7cabc-85a1-4e65-bf20-e7cab8150005 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290800521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2290800521 |
| Directory | /workspace/79.rv_timer_random/latest |
| Test location | /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3767702255 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 266867567180 ps |
| CPU time | 241.77 seconds |
| Started | Jan 14 01:24:08 PM PST 24 |
| Finished | Jan 14 01:28:10 PM PST 24 |
| Peak memory | 182924 kb |
| Host | smart-e97aaf24-8ede-4901-9b0f-ef403e4381f8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767702255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_cfg_update_on_fly.3767702255 |
| Directory | /workspace/8.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/8.rv_timer_disabled.1425432181 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 101796765199 ps |
| CPU time | 152.41 seconds |
| Started | Jan 14 01:24:08 PM PST 24 |
| Finished | Jan 14 01:26:41 PM PST 24 |
| Peak memory | 183004 kb |
| Host | smart-b059d9b5-b359-44ce-bdbd-076f7efbfc2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1425432181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.1425432181 |
| Directory | /workspace/8.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/8.rv_timer_random.3032207090 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 1057775320908 ps |
| CPU time | 627.24 seconds |
| Started | Jan 14 01:24:08 PM PST 24 |
| Finished | Jan 14 01:34:36 PM PST 24 |
| Peak memory | 193244 kb |
| Host | smart-8fa396f5-29fc-44d2-a60f-0867563dbcf5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032207090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3032207090 |
| Directory | /workspace/8.rv_timer_random/latest |
| Test location | /workspace/coverage/default/8.rv_timer_random_reset.2551661125 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 167914490814 ps |
| CPU time | 63.26 seconds |
| Started | Jan 14 01:24:08 PM PST 24 |
| Finished | Jan 14 01:25:12 PM PST 24 |
| Peak memory | 192564 kb |
| Host | smart-782fa6b0-e0dc-4a3b-b203-a90a3024610e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2551661125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2551661125 |
| Directory | /workspace/8.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/8.rv_timer_stress_all.3385546899 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 3840168577412 ps |
| CPU time | 724.5 seconds |
| Started | Jan 14 01:24:06 PM PST 24 |
| Finished | Jan 14 01:36:11 PM PST 24 |
| Peak memory | 191120 kb |
| Host | smart-3cf76455-5f6d-49f1-a5df-b25a6b7e0e0f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385546899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all. 3385546899 |
| Directory | /workspace/8.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.1473098492 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 66310358516 ps |
| CPU time | 653.27 seconds |
| Started | Jan 14 01:24:11 PM PST 24 |
| Finished | Jan 14 01:35:06 PM PST 24 |
| Peak memory | 206164 kb |
| Host | smart-a0d3cc37-516a-4dac-961a-d99ce185c64b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473098492 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.1473098492 |
| Directory | /workspace/8.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/82.rv_timer_random.2457508812 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 98401489038 ps |
| CPU time | 178.9 seconds |
| Started | Jan 14 01:25:36 PM PST 24 |
| Finished | Jan 14 01:28:35 PM PST 24 |
| Peak memory | 191112 kb |
| Host | smart-128392ce-64b0-415e-ae79-bda7abeebd54 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457508812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2457508812 |
| Directory | /workspace/82.rv_timer_random/latest |
| Test location | /workspace/coverage/default/83.rv_timer_random.1270113856 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 31632375017 ps |
| CPU time | 49.83 seconds |
| Started | Jan 14 01:25:24 PM PST 24 |
| Finished | Jan 14 01:26:14 PM PST 24 |
| Peak memory | 182984 kb |
| Host | smart-19c54978-4452-459f-97e4-8c1d3a3b0778 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270113856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1270113856 |
| Directory | /workspace/83.rv_timer_random/latest |
| Test location | /workspace/coverage/default/84.rv_timer_random.3152881938 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 60828579597 ps |
| CPU time | 28.99 seconds |
| Started | Jan 14 01:25:27 PM PST 24 |
| Finished | Jan 14 01:25:57 PM PST 24 |
| Peak memory | 191092 kb |
| Host | smart-d7af09c5-0320-4276-9003-fb8c2dcd95f6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152881938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3152881938 |
| Directory | /workspace/84.rv_timer_random/latest |
| Test location | /workspace/coverage/default/85.rv_timer_random.534367581 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 39272727399 ps |
| CPU time | 101.92 seconds |
| Started | Jan 14 01:25:34 PM PST 24 |
| Finished | Jan 14 01:27:17 PM PST 24 |
| Peak memory | 182940 kb |
| Host | smart-f58378c5-8cd3-4240-a761-a334ec8e7ae0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534367581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.534367581 |
| Directory | /workspace/85.rv_timer_random/latest |
| Test location | /workspace/coverage/default/86.rv_timer_random.3712757190 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 429909624098 ps |
| CPU time | 901.75 seconds |
| Started | Jan 14 01:25:36 PM PST 24 |
| Finished | Jan 14 01:40:39 PM PST 24 |
| Peak memory | 191164 kb |
| Host | smart-4b8ad214-66fa-44ce-b8c9-57590505493f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712757190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3712757190 |
| Directory | /workspace/86.rv_timer_random/latest |
| Test location | /workspace/coverage/default/87.rv_timer_random.221024169 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 38863605214 ps |
| CPU time | 194.05 seconds |
| Started | Jan 14 01:25:23 PM PST 24 |
| Finished | Jan 14 01:28:38 PM PST 24 |
| Peak memory | 194216 kb |
| Host | smart-5d65b61a-887c-43b0-b493-553086763f62 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221024169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.221024169 |
| Directory | /workspace/87.rv_timer_random/latest |
| Test location | /workspace/coverage/default/88.rv_timer_random.678942713 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 544320365870 ps |
| CPU time | 337.34 seconds |
| Started | Jan 14 01:25:34 PM PST 24 |
| Finished | Jan 14 01:31:12 PM PST 24 |
| Peak memory | 194060 kb |
| Host | smart-853c8e5e-3d0f-4877-8a67-63a1c367eaa7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678942713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.678942713 |
| Directory | /workspace/88.rv_timer_random/latest |
| Test location | /workspace/coverage/default/89.rv_timer_random.3595031436 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 127846515386 ps |
| CPU time | 264.47 seconds |
| Started | Jan 14 01:25:41 PM PST 24 |
| Finished | Jan 14 01:30:06 PM PST 24 |
| Peak memory | 183004 kb |
| Host | smart-011a39dc-900f-448a-9b0a-dfc0499f5b74 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595031436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3595031436 |
| Directory | /workspace/89.rv_timer_random/latest |
| Test location | /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.431706098 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 301680672347 ps |
| CPU time | 257.51 seconds |
| Started | Jan 14 01:24:09 PM PST 24 |
| Finished | Jan 14 01:28:28 PM PST 24 |
| Peak memory | 182908 kb |
| Host | smart-2cf2bb79-ae94-457d-b329-65766a821fb7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431706098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .rv_timer_cfg_update_on_fly.431706098 |
| Directory | /workspace/9.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/9.rv_timer_random.845035080 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 112723927580 ps |
| CPU time | 192.6 seconds |
| Started | Jan 14 01:24:07 PM PST 24 |
| Finished | Jan 14 01:27:20 PM PST 24 |
| Peak memory | 193260 kb |
| Host | smart-6fcb172c-9316-4009-8a81-f746165ec7de |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845035080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.845035080 |
| Directory | /workspace/9.rv_timer_random/latest |
| Test location | /workspace/coverage/default/9.rv_timer_random_reset.2000320312 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 716391789 ps |
| CPU time | 0.83 seconds |
| Started | Jan 14 01:24:11 PM PST 24 |
| Finished | Jan 14 01:24:13 PM PST 24 |
| Peak memory | 182764 kb |
| Host | smart-b6db451a-5547-4a0e-9823-9b07f9147a26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2000320312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2000320312 |
| Directory | /workspace/9.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/9.rv_timer_stress_all.1440491256 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 727090257754 ps |
| CPU time | 561.11 seconds |
| Started | Jan 14 01:24:15 PM PST 24 |
| Finished | Jan 14 01:33:37 PM PST 24 |
| Peak memory | 191168 kb |
| Host | smart-78d07795-9a33-430d-9746-c9cef39b7951 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440491256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all. 1440491256 |
| Directory | /workspace/9.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.2216245513 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 496894774443 ps |
| CPU time | 2287.96 seconds |
| Started | Jan 14 01:24:11 PM PST 24 |
| Finished | Jan 14 02:02:20 PM PST 24 |
| Peak memory | 220740 kb |
| Host | smart-33e3611a-5559-494c-8818-fb1d1f6ff3b4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216245513 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.2216245513 |
| Directory | /workspace/9.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/90.rv_timer_random.1346006877 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 131041339912 ps |
| CPU time | 161.41 seconds |
| Started | Jan 14 01:25:23 PM PST 24 |
| Finished | Jan 14 01:28:05 PM PST 24 |
| Peak memory | 191200 kb |
| Host | smart-af237556-d4a8-4581-b05b-e95841b631c7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346006877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1346006877 |
| Directory | /workspace/90.rv_timer_random/latest |
| Test location | /workspace/coverage/default/91.rv_timer_random.434684041 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 103237418694 ps |
| CPU time | 574.53 seconds |
| Started | Jan 14 01:25:23 PM PST 24 |
| Finished | Jan 14 01:34:58 PM PST 24 |
| Peak memory | 191216 kb |
| Host | smart-e858c185-6578-4651-9002-48dc48693b4d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434684041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.434684041 |
| Directory | /workspace/91.rv_timer_random/latest |
| Test location | /workspace/coverage/default/92.rv_timer_random.1017206802 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 506308136718 ps |
| CPU time | 809.22 seconds |
| Started | Jan 14 01:25:36 PM PST 24 |
| Finished | Jan 14 01:39:07 PM PST 24 |
| Peak memory | 191164 kb |
| Host | smart-0b80a63f-8c75-4560-84b0-3fb6917b115f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017206802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1017206802 |
| Directory | /workspace/92.rv_timer_random/latest |
| Test location | /workspace/coverage/default/93.rv_timer_random.4225846523 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 62198209012 ps |
| CPU time | 52.26 seconds |
| Started | Jan 14 01:25:35 PM PST 24 |
| Finished | Jan 14 01:26:28 PM PST 24 |
| Peak memory | 182976 kb |
| Host | smart-a3afa86c-97fd-4209-897f-57537f881e8a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225846523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.4225846523 |
| Directory | /workspace/93.rv_timer_random/latest |
| Test location | /workspace/coverage/default/94.rv_timer_random.3399931626 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 885402498842 ps |
| CPU time | 723.64 seconds |
| Started | Jan 14 01:25:41 PM PST 24 |
| Finished | Jan 14 01:37:45 PM PST 24 |
| Peak memory | 194000 kb |
| Host | smart-004f3270-f456-4154-a70f-d5241fbbe319 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399931626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3399931626 |
| Directory | /workspace/94.rv_timer_random/latest |
| Test location | /workspace/coverage/default/95.rv_timer_random.2173354162 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 60064053691 ps |
| CPU time | 94.95 seconds |
| Started | Jan 14 01:25:43 PM PST 24 |
| Finished | Jan 14 01:27:18 PM PST 24 |
| Peak memory | 191132 kb |
| Host | smart-e9b07b9c-8549-4e3b-ac90-ecb2812cdb5c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173354162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.2173354162 |
| Directory | /workspace/95.rv_timer_random/latest |
| Test location | /workspace/coverage/default/96.rv_timer_random.519369781 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 299413797225 ps |
| CPU time | 206.45 seconds |
| Started | Jan 14 01:25:41 PM PST 24 |
| Finished | Jan 14 01:29:08 PM PST 24 |
| Peak memory | 191204 kb |
| Host | smart-c6fa2397-4931-44ce-b163-bfe199c8a66e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519369781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.519369781 |
| Directory | /workspace/96.rv_timer_random/latest |
| Test location | /workspace/coverage/default/97.rv_timer_random.3572055105 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 5180307774 ps |
| CPU time | 5.38 seconds |
| Started | Jan 14 01:25:41 PM PST 24 |
| Finished | Jan 14 01:25:47 PM PST 24 |
| Peak memory | 182968 kb |
| Host | smart-c31af104-b63e-4f46-9cc6-4f3290379aba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572055105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3572055105 |
| Directory | /workspace/97.rv_timer_random/latest |
| Test location | /workspace/coverage/default/98.rv_timer_random.1795753287 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 1878839445418 ps |
| CPU time | 2595.28 seconds |
| Started | Jan 14 01:25:24 PM PST 24 |
| Finished | Jan 14 02:08:41 PM PST 24 |
| Peak memory | 191132 kb |
| Host | smart-b0924c21-5675-4c06-a33c-e0f73e60f291 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795753287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1795753287 |
| Directory | /workspace/98.rv_timer_random/latest |
| Test location | /workspace/coverage/default/99.rv_timer_random.3847832483 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 414347481833 ps |
| CPU time | 308.38 seconds |
| Started | Jan 14 01:25:27 PM PST 24 |
| Finished | Jan 14 01:30:36 PM PST 24 |
| Peak memory | 191212 kb |
| Host | smart-71a0192d-cea9-48e2-94eb-1230bbab458c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847832483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3847832483 |
| Directory | /workspace/99.rv_timer_random/latest |
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