Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
2564 |
1 |
|
T1 |
8 |
|
T3 |
7 |
|
T10 |
14 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1303 |
1 |
|
T1 |
6 |
|
T3 |
2 |
|
T10 |
10 |
auto[1] |
1261 |
1 |
|
T1 |
2 |
|
T3 |
5 |
|
T10 |
4 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
954 |
1 |
|
T1 |
3 |
|
T3 |
1 |
|
T10 |
3 |
auto[1] |
1610 |
1 |
|
T1 |
5 |
|
T3 |
6 |
|
T10 |
11 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1482 |
1 |
|
T1 |
4 |
|
T3 |
4 |
|
T10 |
6 |
auto[1] |
1082 |
1 |
|
T1 |
4 |
|
T3 |
3 |
|
T10 |
8 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Bins
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
492 |
1 |
|
T1 |
2 |
|
T10 |
2 |
|
T19 |
1 |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
262 |
1 |
|
T10 |
3 |
|
T89 |
1 |
|
T19 |
8 |
all_values[0] |
auto[0] |
auto[1] |
auto[0] |
462 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T10 |
1 |
all_values[0] |
auto[0] |
auto[1] |
auto[1] |
266 |
1 |
|
T1 |
1 |
|
T3 |
3 |
|
T89 |
1 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
549 |
1 |
|
T1 |
4 |
|
T3 |
2 |
|
T10 |
5 |
all_values[0] |
auto[1] |
auto[1] |
auto[1] |
533 |
1 |
|
T3 |
1 |
|
T10 |
3 |
|
T89 |
2 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |