Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.36 98.73 100.00 100.00 100.00 99.66


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T556 /workspace/coverage/default/12.rv_timer_disabled.4035365871 Jan 17 03:07:54 PM PST 24 Jan 17 03:12:39 PM PST 24 908856367959 ps
T249 /workspace/coverage/default/65.rv_timer_random.432975539 Jan 17 03:11:41 PM PST 24 Jan 17 03:32:02 PM PST 24 2989840764097 ps
T557 /workspace/coverage/default/136.rv_timer_random.2294905679 Jan 17 03:13:28 PM PST 24 Jan 17 03:13:58 PM PST 24 50517494843 ps
T153 /workspace/coverage/default/170.rv_timer_random.534475472 Jan 17 03:14:14 PM PST 24 Jan 17 03:15:28 PM PST 24 44931852879 ps
T218 /workspace/coverage/default/189.rv_timer_random.3381841223 Jan 17 03:14:25 PM PST 24 Jan 17 03:28:18 PM PST 24 740429953125 ps
T558 /workspace/coverage/default/11.rv_timer_disabled.2757681904 Jan 17 03:07:59 PM PST 24 Jan 17 03:12:47 PM PST 24 676874216672 ps
T242 /workspace/coverage/default/23.rv_timer_stress_all.3246577492 Jan 17 03:08:10 PM PST 24 Jan 17 03:33:19 PM PST 24 1411225342393 ps
T559 /workspace/coverage/default/17.rv_timer_random_reset.3485054084 Jan 17 03:08:00 PM PST 24 Jan 17 03:08:04 PM PST 24 900238991 ps
T223 /workspace/coverage/default/184.rv_timer_random.3710466754 Jan 17 03:14:22 PM PST 24 Jan 17 03:16:45 PM PST 24 81269954924 ps
T560 /workspace/coverage/default/3.rv_timer_random_reset.3505654373 Jan 17 03:07:31 PM PST 24 Jan 17 03:08:11 PM PST 24 33545076403 ps
T304 /workspace/coverage/default/12.rv_timer_stress_all.3976610507 Jan 17 03:07:57 PM PST 24 Jan 17 03:23:25 PM PST 24 1510090924945 ps
T561 /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.1338627447 Jan 17 03:07:25 PM PST 24 Jan 17 03:17:51 PM PST 24 343857608364 ps
T254 /workspace/coverage/default/130.rv_timer_random.513118254 Jan 17 03:13:13 PM PST 24 Jan 17 03:16:00 PM PST 24 104484520975 ps
T562 /workspace/coverage/default/38.rv_timer_random_reset.1513525069 Jan 17 03:09:41 PM PST 24 Jan 17 03:09:42 PM PST 24 109175781 ps
T563 /workspace/coverage/default/37.rv_timer_disabled.256350355 Jan 17 03:09:31 PM PST 24 Jan 17 03:13:05 PM PST 24 656714366553 ps
T317 /workspace/coverage/default/140.rv_timer_random.1185410703 Jan 17 03:13:32 PM PST 24 Jan 17 03:15:16 PM PST 24 67314241008 ps
T343 /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1064258559 Jan 17 03:10:49 PM PST 24 Jan 17 03:15:58 PM PST 24 160512227146 ps
T348 /workspace/coverage/default/45.rv_timer_random_reset.851076972 Jan 17 03:10:46 PM PST 24 Jan 17 03:11:38 PM PST 24 53557767993 ps
T168 /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2823543714 Jan 17 03:08:33 PM PST 24 Jan 17 03:10:42 PM PST 24 72849616193 ps
T564 /workspace/coverage/default/3.rv_timer_disabled.83328757 Jan 17 03:07:33 PM PST 24 Jan 17 03:07:45 PM PST 24 40787594464 ps
T565 /workspace/coverage/default/29.rv_timer_disabled.2193976824 Jan 17 03:08:21 PM PST 24 Jan 17 03:13:30 PM PST 24 767583561640 ps
T252 /workspace/coverage/default/5.rv_timer_stress_all.3232555224 Jan 17 03:07:38 PM PST 24 Jan 17 03:41:17 PM PST 24 692344060978 ps
T307 /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.446876971 Jan 17 03:09:36 PM PST 24 Jan 17 03:21:26 PM PST 24 2212533498850 ps
T566 /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.3049891945 Jan 17 03:09:25 PM PST 24 Jan 17 03:28:37 PM PST 24 199860728404 ps
T567 /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2685649026 Jan 17 03:07:42 PM PST 24 Jan 17 03:09:34 PM PST 24 126598899245 ps
T352 /workspace/coverage/default/17.rv_timer_stress_all.3333880279 Jan 17 03:08:05 PM PST 24 Jan 17 03:17:59 PM PST 24 91993747604 ps
T568 /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.2770968581 Jan 17 03:08:49 PM PST 24 Jan 17 03:10:31 PM PST 24 11929135441 ps
T569 /workspace/coverage/default/5.rv_timer_disabled.2860449148 Jan 17 03:07:42 PM PST 24 Jan 17 03:10:28 PM PST 24 125087157595 ps
T570 /workspace/coverage/default/46.rv_timer_random_reset.3466103331 Jan 17 03:10:46 PM PST 24 Jan 17 03:11:56 PM PST 24 77076326403 ps
T318 /workspace/coverage/default/33.rv_timer_random_reset.3150639701 Jan 17 03:08:50 PM PST 24 Jan 17 03:10:12 PM PST 24 76049007164 ps
T571 /workspace/coverage/default/123.rv_timer_random.2083013980 Jan 17 03:13:03 PM PST 24 Jan 17 03:16:36 PM PST 24 780828612711 ps
T305 /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.3996367690 Jan 17 03:08:00 PM PST 24 Jan 17 03:20:49 PM PST 24 88723844906 ps
T154 /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3943301929 Jan 17 03:10:32 PM PST 24 Jan 17 03:23:04 PM PST 24 2783245140596 ps
T572 /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.237492503 Jan 17 03:10:46 PM PST 24 Jan 17 03:21:07 PM PST 24 292969821669 ps
T213 /workspace/coverage/default/171.rv_timer_random.2554552439 Jan 17 03:14:10 PM PST 24 Jan 17 03:22:19 PM PST 24 117158147195 ps
T573 /workspace/coverage/default/15.rv_timer_random.2859857507 Jan 17 03:07:59 PM PST 24 Jan 17 03:10:38 PM PST 24 71326071593 ps
T574 /workspace/coverage/default/137.rv_timer_random.1611036514 Jan 17 03:13:28 PM PST 24 Jan 17 03:14:55 PM PST 24 343617809064 ps
T273 /workspace/coverage/default/24.rv_timer_stress_all.1292366134 Jan 17 03:08:12 PM PST 24 Jan 17 03:15:50 PM PST 24 567130830070 ps
T332 /workspace/coverage/default/87.rv_timer_random.3824621446 Jan 17 03:12:05 PM PST 24 Jan 17 03:22:53 PM PST 24 143868757314 ps
T247 /workspace/coverage/default/25.rv_timer_random_reset.2702822271 Jan 17 03:08:08 PM PST 24 Jan 17 03:09:37 PM PST 24 89282353852 ps
T575 /workspace/coverage/default/115.rv_timer_random.1422823829 Jan 17 03:12:45 PM PST 24 Jan 17 03:12:53 PM PST 24 4258053729 ps
T576 /workspace/coverage/default/10.rv_timer_random_reset.2895758078 Jan 17 03:07:56 PM PST 24 Jan 17 03:08:36 PM PST 24 23388508207 ps
T577 /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.3577883006 Jan 17 03:07:40 PM PST 24 Jan 17 03:08:31 PM PST 24 6754001653 ps
T274 /workspace/coverage/default/47.rv_timer_random.1302287224 Jan 17 03:11:06 PM PST 24 Jan 17 03:21:15 PM PST 24 1655861564073 ps
T228 /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1529647989 Jan 17 03:08:50 PM PST 24 Jan 17 03:13:56 PM PST 24 317589057611 ps
T578 /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2015762319 Jan 17 03:10:47 PM PST 24 Jan 17 03:11:00 PM PST 24 6313747466 ps
T579 /workspace/coverage/default/39.rv_timer_disabled.2663855089 Jan 17 03:09:46 PM PST 24 Jan 17 03:12:40 PM PST 24 300397697678 ps
T312 /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1088839222 Jan 17 03:07:55 PM PST 24 Jan 17 03:12:43 PM PST 24 172415586103 ps
T211 /workspace/coverage/default/106.rv_timer_random.3345103130 Jan 17 03:12:39 PM PST 24 Jan 17 03:13:22 PM PST 24 25825974986 ps
T330 /workspace/coverage/default/107.rv_timer_random.2376601476 Jan 17 03:12:44 PM PST 24 Jan 17 03:13:56 PM PST 24 156046352863 ps
T217 /workspace/coverage/default/18.rv_timer_random.254604316 Jan 17 03:07:58 PM PST 24 Jan 17 03:19:08 PM PST 24 859853898693 ps
T580 /workspace/coverage/default/31.rv_timer_random.4005105942 Jan 17 03:08:47 PM PST 24 Jan 17 03:10:30 PM PST 24 175273895287 ps
T320 /workspace/coverage/default/149.rv_timer_random.1601422912 Jan 17 03:13:40 PM PST 24 Jan 17 03:13:59 PM PST 24 21729121295 ps
T581 /workspace/coverage/default/2.rv_timer_random_reset.3936567994 Jan 17 03:07:33 PM PST 24 Jan 17 03:07:34 PM PST 24 17158534 ps
T214 /workspace/coverage/default/27.rv_timer_stress_all.3111634406 Jan 17 03:08:14 PM PST 24 Jan 17 04:10:49 PM PST 24 9930647896762 ps
T582 /workspace/coverage/default/33.rv_timer_disabled.678204644 Jan 17 03:08:49 PM PST 24 Jan 17 03:12:46 PM PST 24 618985338926 ps
T270 /workspace/coverage/default/133.rv_timer_random.3590507400 Jan 17 03:13:31 PM PST 24 Jan 17 03:18:07 PM PST 24 207972091000 ps
T287 /workspace/coverage/default/128.rv_timer_random.3782778083 Jan 17 03:13:15 PM PST 24 Jan 17 03:35:53 PM PST 24 4129373030109 ps
T280 /workspace/coverage/default/35.rv_timer_random.3769481750 Jan 17 03:08:57 PM PST 24 Jan 17 03:17:12 PM PST 24 111778188474 ps
T583 /workspace/coverage/default/1.rv_timer_disabled.3468605567 Jan 17 03:07:29 PM PST 24 Jan 17 03:10:09 PM PST 24 394079238252 ps
T584 /workspace/coverage/default/15.rv_timer_disabled.605891023 Jan 17 03:08:05 PM PST 24 Jan 17 03:08:56 PM PST 24 114956072034 ps
T286 /workspace/coverage/default/146.rv_timer_random.2535505209 Jan 17 03:13:31 PM PST 24 Jan 17 03:17:28 PM PST 24 91409867654 ps
T285 /workspace/coverage/default/81.rv_timer_random.2760939985 Jan 17 03:11:59 PM PST 24 Jan 17 03:14:37 PM PST 24 79933330041 ps
T585 /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.938158650 Jan 17 03:07:48 PM PST 24 Jan 17 03:10:42 PM PST 24 317730019940 ps
T200 /workspace/coverage/default/19.rv_timer_random.2719631502 Jan 17 03:08:05 PM PST 24 Jan 17 03:16:29 PM PST 24 337324786538 ps
T586 /workspace/coverage/default/180.rv_timer_random.561516597 Jan 17 03:14:15 PM PST 24 Jan 17 03:16:54 PM PST 24 321916851391 ps
T294 /workspace/coverage/default/112.rv_timer_random.818472722 Jan 17 03:12:39 PM PST 24 Jan 17 03:13:35 PM PST 24 40305356765 ps
T587 /workspace/coverage/default/45.rv_timer_disabled.3913257373 Jan 17 03:10:46 PM PST 24 Jan 17 03:13:06 PM PST 24 710724553172 ps
T256 /workspace/coverage/default/72.rv_timer_random.852220944 Jan 17 03:11:42 PM PST 24 Jan 17 03:15:14 PM PST 24 429118348446 ps
T588 /workspace/coverage/default/28.rv_timer_disabled.4253405953 Jan 17 03:08:15 PM PST 24 Jan 17 03:09:13 PM PST 24 66881415036 ps
T589 /workspace/coverage/default/8.rv_timer_random_reset.1398295057 Jan 17 03:07:49 PM PST 24 Jan 17 03:07:51 PM PST 24 632757455 ps
T590 /workspace/coverage/default/29.rv_timer_random_reset.1241627 Jan 17 03:08:21 PM PST 24 Jan 17 03:13:15 PM PST 24 33581771715 ps
T591 /workspace/coverage/default/14.rv_timer_disabled.2766290000 Jan 17 03:07:59 PM PST 24 Jan 17 03:10:49 PM PST 24 106212615516 ps
T592 /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.444949623 Jan 17 03:11:23 PM PST 24 Jan 17 03:19:56 PM PST 24 60119035470 ps
T593 /workspace/coverage/default/191.rv_timer_random.4181801326 Jan 17 03:14:24 PM PST 24 Jan 17 03:16:24 PM PST 24 167304427425 ps
T171 /workspace/coverage/default/85.rv_timer_random.3433986173 Jan 17 03:12:00 PM PST 24 Jan 17 03:29:50 PM PST 24 186102472374 ps
T594 /workspace/coverage/default/62.rv_timer_random.543298310 Jan 17 03:11:40 PM PST 24 Jan 17 03:12:05 PM PST 24 30977721154 ps
T172 /workspace/coverage/default/181.rv_timer_random.4219548060 Jan 17 03:14:13 PM PST 24 Jan 17 03:26:30 PM PST 24 660048048994 ps
T595 /workspace/coverage/default/59.rv_timer_random.2288617164 Jan 17 03:11:32 PM PST 24 Jan 17 03:15:46 PM PST 24 438467417297 ps
T596 /workspace/coverage/default/45.rv_timer_stress_all.2997600566 Jan 17 03:10:47 PM PST 24 Jan 17 03:28:26 PM PST 24 406720525444 ps
T597 /workspace/coverage/default/32.rv_timer_random_reset.747415561 Jan 17 03:08:48 PM PST 24 Jan 17 03:08:56 PM PST 24 13775298629 ps
T598 /workspace/coverage/default/36.rv_timer_random_reset.1604080710 Jan 17 03:09:25 PM PST 24 Jan 17 03:09:58 PM PST 24 142717493511 ps
T599 /workspace/coverage/default/34.rv_timer_random_reset.401437007 Jan 17 03:08:55 PM PST 24 Jan 17 03:08:59 PM PST 24 747217338 ps
T323 /workspace/coverage/default/99.rv_timer_random.152668581 Jan 17 03:12:22 PM PST 24 Jan 17 03:16:32 PM PST 24 124356481673 ps
T600 /workspace/coverage/default/43.rv_timer_stress_all.228689357 Jan 17 03:10:31 PM PST 24 Jan 17 03:12:50 PM PST 24 329648228572 ps
T601 /workspace/coverage/default/43.rv_timer_disabled.4206186709 Jan 17 03:10:29 PM PST 24 Jan 17 03:10:46 PM PST 24 10472222308 ps
T602 /workspace/coverage/default/1.rv_timer_random.3430393809 Jan 17 03:07:27 PM PST 24 Jan 17 03:11:12 PM PST 24 131239316152 ps
T603 /workspace/coverage/default/57.rv_timer_random.1096766574 Jan 17 03:11:30 PM PST 24 Jan 17 03:13:48 PM PST 24 29140762731 ps
T355 /workspace/coverage/default/25.rv_timer_stress_all.1436457340 Jan 17 03:08:08 PM PST 24 Jan 17 04:04:44 PM PST 24 1157641628953 ps
T604 /workspace/coverage/default/40.rv_timer_random_reset.2777202301 Jan 17 03:10:03 PM PST 24 Jan 17 03:10:04 PM PST 24 33105153 ps
T605 /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3364259365 Jan 17 03:10:00 PM PST 24 Jan 17 03:13:38 PM PST 24 354411085511 ps
T606 /workspace/coverage/default/39.rv_timer_random_reset.1223672804 Jan 17 03:09:53 PM PST 24 Jan 17 03:09:59 PM PST 24 1155856849 ps
T322 /workspace/coverage/default/93.rv_timer_random.2224834365 Jan 17 03:12:15 PM PST 24 Jan 17 03:15:09 PM PST 24 297236579900 ps
T277 /workspace/coverage/default/141.rv_timer_random.1802190629 Jan 17 03:13:34 PM PST 24 Jan 17 03:35:33 PM PST 24 513285979640 ps
T607 /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.891288802 Jan 17 03:08:05 PM PST 24 Jan 17 03:08:13 PM PST 24 7389746652 ps
T250 /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2163769603 Jan 17 03:08:06 PM PST 24 Jan 17 03:14:06 PM PST 24 345114547973 ps
T608 /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.975188483 Jan 17 03:09:53 PM PST 24 Jan 17 03:12:00 PM PST 24 412414134284 ps
T319 /workspace/coverage/default/142.rv_timer_random.4138988973 Jan 17 03:13:29 PM PST 24 Jan 17 03:19:02 PM PST 24 602441920618 ps
T609 /workspace/coverage/default/16.rv_timer_disabled.1759248202 Jan 17 03:07:58 PM PST 24 Jan 17 03:10:55 PM PST 24 246567041261 ps
T610 /workspace/coverage/default/114.rv_timer_random.1096741535 Jan 17 03:12:45 PM PST 24 Jan 17 03:18:19 PM PST 24 60483450237 ps
T611 /workspace/coverage/default/32.rv_timer_stress_all.3938882700 Jan 17 03:08:47 PM PST 24 Jan 17 03:12:17 PM PST 24 376923896473 ps
T341 /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.2371871305 Jan 17 03:07:40 PM PST 24 Jan 17 03:07:57 PM PST 24 17601068798 ps
T278 /workspace/coverage/default/176.rv_timer_random.1088387993 Jan 17 03:14:07 PM PST 24 Jan 17 03:21:25 PM PST 24 264430881871 ps
T202 /workspace/coverage/default/0.rv_timer_random.232328650 Jan 17 03:07:27 PM PST 24 Jan 17 03:08:56 PM PST 24 10399659502 ps
T612 /workspace/coverage/default/37.rv_timer_random.3402632725 Jan 17 03:09:29 PM PST 24 Jan 17 03:10:44 PM PST 24 123660074063 ps
T281 /workspace/coverage/default/91.rv_timer_random.2269920329 Jan 17 03:12:11 PM PST 24 Jan 17 03:14:24 PM PST 24 146268368971 ps
T350 /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1101404639 Jan 17 03:08:46 PM PST 24 Jan 17 03:12:54 PM PST 24 444966818298 ps
T613 /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3001279477 Jan 17 03:08:16 PM PST 24 Jan 17 03:08:25 PM PST 24 15067133136 ps
T331 /workspace/coverage/default/18.rv_timer_random_reset.4260381475 Jan 17 03:08:04 PM PST 24 Jan 17 03:09:09 PM PST 24 33965150519 ps
T262 /workspace/coverage/default/178.rv_timer_random.1262026457 Jan 17 03:14:12 PM PST 24 Jan 17 03:16:30 PM PST 24 176724872286 ps
T614 /workspace/coverage/default/34.rv_timer_stress_all.3124638379 Jan 17 03:08:57 PM PST 24 Jan 17 03:11:39 PM PST 24 100439645597 ps
T615 /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.2945243162 Jan 17 03:08:01 PM PST 24 Jan 17 03:10:31 PM PST 24 56515116699 ps
T616 /workspace/coverage/default/51.rv_timer_random.2810703562 Jan 17 03:11:28 PM PST 24 Jan 17 03:35:38 PM PST 24 45885322487 ps
T328 /workspace/coverage/default/86.rv_timer_random.4245163998 Jan 17 03:11:59 PM PST 24 Jan 17 03:22:27 PM PST 24 508089432922 ps
T259 /workspace/coverage/default/186.rv_timer_random.3287650488 Jan 17 03:14:18 PM PST 24 Jan 17 03:16:44 PM PST 24 80395825225 ps
T617 /workspace/coverage/default/20.rv_timer_random.2595593398 Jan 17 03:08:02 PM PST 24 Jan 17 03:09:19 PM PST 24 94987534706 ps
T618 /workspace/coverage/default/22.rv_timer_disabled.3881855752 Jan 17 03:08:04 PM PST 24 Jan 17 03:09:14 PM PST 24 51265910374 ps
T347 /workspace/coverage/default/13.rv_timer_stress_all.1301499008 Jan 17 03:07:52 PM PST 24 Jan 17 03:18:33 PM PST 24 2549117951126 ps
T619 /workspace/coverage/default/11.rv_timer_random_reset.1511673556 Jan 17 03:07:55 PM PST 24 Jan 17 03:07:57 PM PST 24 175631276 ps
T620 /workspace/coverage/default/169.rv_timer_random.4208583228 Jan 17 03:14:09 PM PST 24 Jan 17 03:14:57 PM PST 24 25108695847 ps

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.1162456237
Short name T1
Test name
Test status
Simulation time 153539137949 ps
CPU time 267.65 seconds
Started Jan 17 03:07:48 PM PST 24
Finished Jan 17 03:12:16 PM PST 24
Peak memory 197696 kb
Host smart-1330292f-6081-446c-8782-e1f4f10e2bdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162456237 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.1162456237
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.2927685281
Short name T19
Test name
Test status
Simulation time 1211760090423 ps
CPU time 795.17 seconds
Started Jan 17 03:08:44 PM PST 24
Finished Jan 17 03:22:00 PM PST 24
Peak memory 191072 kb
Host smart-a7408ed9-c3ec-48ca-91ff-767879dc4dc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927685281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.2927685281
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3706965012
Short name T158
Test name
Test status
Simulation time 1787032775747 ps
CPU time 3425.14 seconds
Started Jan 17 03:07:50 PM PST 24
Finished Jan 17 04:04:57 PM PST 24
Peak memory 191156 kb
Host smart-e5289023-d2e6-4271-b8be-0345393de81c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706965012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3706965012
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2121170767
Short name T13
Test name
Test status
Simulation time 692193918 ps
CPU time 1.05 seconds
Started Jan 17 01:01:56 PM PST 24
Finished Jan 17 01:01:57 PM PST 24
Peak memory 183404 kb
Host smart-4d948e56-669c-47de-9eed-c48783bcb0fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121170767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2121170767
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2871680105
Short name T119
Test name
Test status
Simulation time 854045954368 ps
CPU time 3358.97 seconds
Started Jan 17 03:09:36 PM PST 24
Finished Jan 17 04:05:35 PM PST 24
Peak memory 191232 kb
Host smart-f3dd7a3e-ed73-4204-be22-7167b3abe28c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871680105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2871680105
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.1869206341
Short name T89
Test name
Test status
Simulation time 2095233477630 ps
CPU time 1421.64 seconds
Started Jan 17 03:08:20 PM PST 24
Finished Jan 17 03:32:03 PM PST 24
Peak memory 191144 kb
Host smart-5df57134-99ac-48d3-916f-4254899c8177
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869206341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.1869206341
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.389453512
Short name T127
Test name
Test status
Simulation time 566556086622 ps
CPU time 1661.87 seconds
Started Jan 17 03:07:55 PM PST 24
Finished Jan 17 03:35:38 PM PST 24
Peak memory 195624 kb
Host smart-60a5cf89-d495-4528-995e-265567539596
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389453512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
389453512
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1681525066
Short name T160
Test name
Test status
Simulation time 3378111655870 ps
CPU time 2594.66 seconds
Started Jan 17 03:10:24 PM PST 24
Finished Jan 17 03:53:39 PM PST 24
Peak memory 191228 kb
Host smart-af1ee837-c358-4fa7-b1e4-9012a6397c83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681525066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1681525066
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.509951861
Short name T136
Test name
Test status
Simulation time 1442248312277 ps
CPU time 2368.83 seconds
Started Jan 17 03:08:08 PM PST 24
Finished Jan 17 03:47:37 PM PST 24
Peak memory 191236 kb
Host smart-760ce106-5208-4851-a9d6-66237ef79952
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509951861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.
509951861
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1693116892
Short name T53
Test name
Test status
Simulation time 121733983 ps
CPU time 2.34 seconds
Started Jan 17 01:02:09 PM PST 24
Finished Jan 17 01:02:13 PM PST 24
Peak memory 191712 kb
Host smart-8a58d0e0-95e6-44df-82c5-588fb28bcdb2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693116892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1693116892
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.4061009520
Short name T156
Test name
Test status
Simulation time 655632502879 ps
CPU time 3334.3 seconds
Started Jan 17 03:08:04 PM PST 24
Finished Jan 17 04:03:39 PM PST 24
Peak memory 191248 kb
Host smart-2b8d9564-9df7-4904-b765-82dc7c26f099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061009520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.4061009520
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.501437162
Short name T142
Test name
Test status
Simulation time 2725071923447 ps
CPU time 2032.8 seconds
Started Jan 17 03:08:30 PM PST 24
Finished Jan 17 03:42:23 PM PST 24
Peak memory 191276 kb
Host smart-8423a2b2-bbef-446a-9774-73efa1a11eb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501437162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.
501437162
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2599903285
Short name T167
Test name
Test status
Simulation time 2126236158137 ps
CPU time 1123.42 seconds
Started Jan 17 03:07:32 PM PST 24
Finished Jan 17 03:26:16 PM PST 24
Peak memory 191152 kb
Host smart-a0a755c1-d95a-4e1b-81f3-479db24ef3c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599903285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2599903285
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.939929349
Short name T16
Test name
Test status
Simulation time 110485388 ps
CPU time 0.73 seconds
Started Jan 17 03:07:32 PM PST 24
Finished Jan 17 03:07:33 PM PST 24
Peak memory 212816 kb
Host smart-a600a730-7191-4448-95a8-59082f8c293a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939929349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.939929349
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3625565716
Short name T140
Test name
Test status
Simulation time 980131019679 ps
CPU time 477.02 seconds
Started Jan 17 03:08:00 PM PST 24
Finished Jan 17 03:15:59 PM PST 24
Peak memory 190760 kb
Host smart-3307e58b-8fde-4be9-b2fc-bc9221815577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625565716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3625565716
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2342404202
Short name T185
Test name
Test status
Simulation time 1916061265494 ps
CPU time 6447.13 seconds
Started Jan 17 03:08:08 PM PST 24
Finished Jan 17 04:55:36 PM PST 24
Peak memory 191320 kb
Host smart-f0bf2e5f-85e9-491c-a201-59628be6d912
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342404202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2342404202
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2204371067
Short name T135
Test name
Test status
Simulation time 733044504684 ps
CPU time 1712.94 seconds
Started Jan 17 03:07:33 PM PST 24
Finished Jan 17 03:36:06 PM PST 24
Peak memory 191152 kb
Host smart-a4da4775-3e7a-43b5-93ef-f0e279d8e6cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204371067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2204371067
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.3111634406
Short name T214
Test name
Test status
Simulation time 9930647896762 ps
CPU time 3752.68 seconds
Started Jan 17 03:08:14 PM PST 24
Finished Jan 17 04:10:49 PM PST 24
Peak memory 191164 kb
Host smart-6ae308e0-1b28-4db8-bcec-98cdf673c845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111634406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.3111634406
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3991207655
Short name T25
Test name
Test status
Simulation time 2439074151042 ps
CPU time 1454.79 seconds
Started Jan 17 03:07:57 PM PST 24
Finished Jan 17 03:32:17 PM PST 24
Peak memory 182964 kb
Host smart-d76ebc5f-4836-4d54-ae67-adb1fd01e2e0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991207655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3991207655
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3246577492
Short name T242
Test name
Test status
Simulation time 1411225342393 ps
CPU time 1508.13 seconds
Started Jan 17 03:08:10 PM PST 24
Finished Jan 17 03:33:19 PM PST 24
Peak memory 191152 kb
Host smart-9531bcec-021b-43f5-aa8e-a2f6e22cc70b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246577492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3246577492
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/52.rv_timer_random.1790120198
Short name T152
Test name
Test status
Simulation time 186811968803 ps
CPU time 325.95 seconds
Started Jan 17 03:11:27 PM PST 24
Finished Jan 17 03:16:54 PM PST 24
Peak memory 191180 kb
Host smart-10a74486-cbb3-4eb3-a05e-f59f780666ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790120198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1790120198
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.4144079004
Short name T118
Test name
Test status
Simulation time 522849636256 ps
CPU time 505.82 seconds
Started Jan 17 03:12:54 PM PST 24
Finished Jan 17 03:21:21 PM PST 24
Peak memory 191180 kb
Host smart-49f0c534-5626-4b42-a627-6e27d2b695e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144079004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.4144079004
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3232555224
Short name T252
Test name
Test status
Simulation time 692344060978 ps
CPU time 2018.49 seconds
Started Jan 17 03:07:38 PM PST 24
Finished Jan 17 03:41:17 PM PST 24
Peak memory 191136 kb
Host smart-0e8bfc3f-db24-4dff-b2fe-eba2a399f61a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232555224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3232555224
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/69.rv_timer_random.213830261
Short name T282
Test name
Test status
Simulation time 111869358236 ps
CPU time 254.44 seconds
Started Jan 17 03:11:47 PM PST 24
Finished Jan 17 03:16:02 PM PST 24
Peak memory 191192 kb
Host smart-c747a1f3-c707-4571-a802-7ac8326eca52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213830261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.213830261
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.1331999840
Short name T236
Test name
Test status
Simulation time 140173678500 ps
CPU time 653.35 seconds
Started Jan 17 03:13:03 PM PST 24
Finished Jan 17 03:23:57 PM PST 24
Peak memory 193152 kb
Host smart-4462b491-f43c-4ba3-af53-0551abbbad18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331999840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1331999840
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1308642944
Short name T37
Test name
Test status
Simulation time 25846329 ps
CPU time 0.64 seconds
Started Jan 17 01:02:08 PM PST 24
Finished Jan 17 01:02:11 PM PST 24
Peak memory 192068 kb
Host smart-93368822-0d6e-4afa-a252-28faa940f502
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308642944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.1308642944
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/139.rv_timer_random.274131156
Short name T87
Test name
Test status
Simulation time 183247350975 ps
CPU time 182.53 seconds
Started Jan 17 03:13:28 PM PST 24
Finished Jan 17 03:16:35 PM PST 24
Peak memory 191160 kb
Host smart-cb367d97-4422-422b-8d08-de7d25a7958b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274131156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.274131156
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.404809146
Short name T124
Test name
Test status
Simulation time 536055933426 ps
CPU time 413.76 seconds
Started Jan 17 03:13:47 PM PST 24
Finished Jan 17 03:20:41 PM PST 24
Peak memory 194268 kb
Host smart-8e3062a0-5786-4988-9ebb-810a4a116dd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404809146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.404809146
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random.3495595675
Short name T188
Test name
Test status
Simulation time 556867441806 ps
CPU time 840.95 seconds
Started Jan 17 03:08:04 PM PST 24
Finished Jan 17 03:22:05 PM PST 24
Peak memory 191256 kb
Host smart-deaaff0f-d5eb-4222-acef-d27a3f3eaa2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495595675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3495595675
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.1334074922
Short name T169
Test name
Test status
Simulation time 1449425764040 ps
CPU time 2536.21 seconds
Started Jan 17 03:11:06 PM PST 24
Finished Jan 17 03:53:24 PM PST 24
Peak memory 195376 kb
Host smart-df4fb4b0-8307-4517-8156-053728c23d0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334074922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.1334074922
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/64.rv_timer_random.285106054
Short name T23
Test name
Test status
Simulation time 608527549823 ps
CPU time 312.86 seconds
Started Jan 17 03:11:41 PM PST 24
Finished Jan 17 03:16:56 PM PST 24
Peak memory 194500 kb
Host smart-741bdef4-9710-4b24-acef-3f6adfe53474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285106054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.285106054
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/90.rv_timer_random.2196104919
Short name T180
Test name
Test status
Simulation time 181651491274 ps
CPU time 180.01 seconds
Started Jan 17 03:12:12 PM PST 24
Finished Jan 17 03:15:14 PM PST 24
Peak memory 191144 kb
Host smart-e834d186-1907-4b7f-91db-c5537e3f3ea4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196104919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2196104919
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.4049453093
Short name T195
Test name
Test status
Simulation time 320610564904 ps
CPU time 556.77 seconds
Started Jan 17 03:12:38 PM PST 24
Finished Jan 17 03:21:56 PM PST 24
Peak memory 191204 kb
Host smart-67c10a81-dcc9-4486-9232-df55374f0082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049453093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.4049453093
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.4138988973
Short name T319
Test name
Test status
Simulation time 602441920618 ps
CPU time 329.41 seconds
Started Jan 17 03:13:29 PM PST 24
Finished Jan 17 03:19:02 PM PST 24
Peak memory 191076 kb
Host smart-12290bd9-f571-4640-810f-2f301508f9d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138988973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.4138988973
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random.2878121522
Short name T120
Test name
Test status
Simulation time 160047079531 ps
CPU time 1098.88 seconds
Started Jan 17 03:07:40 PM PST 24
Finished Jan 17 03:25:59 PM PST 24
Peak memory 191168 kb
Host smart-919aad54-16f4-4f26-ae57-950cb5d53b3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878121522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2878121522
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.2667049524
Short name T115
Test name
Test status
Simulation time 712338287694 ps
CPU time 378.88 seconds
Started Jan 17 03:07:43 PM PST 24
Finished Jan 17 03:14:03 PM PST 24
Peak memory 182952 kb
Host smart-a4553dd0-afdb-4431-bcb6-1e494dbf2b4a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667049524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.2667049524
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2961271543
Short name T112
Test name
Test status
Simulation time 702882323534 ps
CPU time 363.44 seconds
Started Jan 17 03:07:28 PM PST 24
Finished Jan 17 03:13:32 PM PST 24
Peak memory 193780 kb
Host smart-5eec4e13-c29e-4786-8793-524e5438f323
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961271543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2961271543
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/103.rv_timer_random.2315773984
Short name T222
Test name
Test status
Simulation time 614389744416 ps
CPU time 451.95 seconds
Started Jan 17 03:12:29 PM PST 24
Finished Jan 17 03:20:01 PM PST 24
Peak memory 191168 kb
Host smart-c89330af-b104-4870-9120-718e78b91f13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315773984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2315773984
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3345103130
Short name T211
Test name
Test status
Simulation time 25825974986 ps
CPU time 42.16 seconds
Started Jan 17 03:12:39 PM PST 24
Finished Jan 17 03:13:22 PM PST 24
Peak memory 193696 kb
Host smart-0c301857-916d-4ffc-b1e6-22acf4d2a17e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345103130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3345103130
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.2303314966
Short name T164
Test name
Test status
Simulation time 563891033388 ps
CPU time 632.15 seconds
Started Jan 17 03:12:38 PM PST 24
Finished Jan 17 03:23:11 PM PST 24
Peak memory 191372 kb
Host smart-ceae310b-cbfa-4c7d-bdf9-1e024edeeedc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303314966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2303314966
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.1208690054
Short name T163
Test name
Test status
Simulation time 839454560327 ps
CPU time 357.43 seconds
Started Jan 17 03:07:56 PM PST 24
Finished Jan 17 03:14:00 PM PST 24
Peak memory 191092 kb
Host smart-c47beea9-7728-4aff-9ff2-71e9fe73bdfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208690054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1208690054
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.3939173946
Short name T157
Test name
Test status
Simulation time 555637411904 ps
CPU time 353.66 seconds
Started Jan 17 03:12:52 PM PST 24
Finished Jan 17 03:18:49 PM PST 24
Peak memory 191168 kb
Host smart-f8729e52-8b5f-4411-bf59-0b3db87a5c8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939173946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3939173946
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3976610507
Short name T304
Test name
Test status
Simulation time 1510090924945 ps
CPU time 922.62 seconds
Started Jan 17 03:07:57 PM PST 24
Finished Jan 17 03:23:25 PM PST 24
Peak memory 182884 kb
Host smart-b6f047a8-9cd4-4620-b49e-c05b3f13bcca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976610507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3976610507
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2754694339
Short name T161
Test name
Test status
Simulation time 1940151730804 ps
CPU time 1002.13 seconds
Started Jan 17 03:07:57 PM PST 24
Finished Jan 17 03:24:44 PM PST 24
Peak memory 191132 kb
Host smart-9119759c-2e8e-4e82-b4e8-8f14e514f01b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754694339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2754694339
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3354741577
Short name T100
Test name
Test status
Simulation time 491729512179 ps
CPU time 445.85 seconds
Started Jan 17 03:08:05 PM PST 24
Finished Jan 17 03:15:32 PM PST 24
Peak memory 182928 kb
Host smart-c0c1e342-0a0d-4ea3-919b-6747f4c064c7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354741577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3354741577
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_random.3646584537
Short name T244
Test name
Test status
Simulation time 68194490818 ps
CPU time 146.12 seconds
Started Jan 17 03:08:14 PM PST 24
Finished Jan 17 03:10:41 PM PST 24
Peak memory 191148 kb
Host smart-8d6d0dc4-7572-45de-a2c4-71365009cdd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646584537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3646584537
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.4239850949
Short name T106
Test name
Test status
Simulation time 365474369585 ps
CPU time 814.54 seconds
Started Jan 17 03:08:50 PM PST 24
Finished Jan 17 03:22:26 PM PST 24
Peak memory 191124 kb
Host smart-7ac5c945-9cc1-4b5e-801d-908d149b1a18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239850949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.4239850949
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/85.rv_timer_random.3433986173
Short name T171
Test name
Test status
Simulation time 186102472374 ps
CPU time 1069.39 seconds
Started Jan 17 03:12:00 PM PST 24
Finished Jan 17 03:29:50 PM PST 24
Peak memory 191224 kb
Host smart-ec050c86-6fd6-40d7-914d-8d940c749cea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433986173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3433986173
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random.577262258
Short name T114
Test name
Test status
Simulation time 442024831123 ps
CPU time 446.48 seconds
Started Jan 17 03:07:50 PM PST 24
Finished Jan 17 03:15:18 PM PST 24
Peak memory 191136 kb
Host smart-b50b9e7d-6285-4575-ab56-999282019fda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577262258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.577262258
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.360018380
Short name T90
Test name
Test status
Simulation time 223857332996 ps
CPU time 185.73 seconds
Started Jan 17 03:12:45 PM PST 24
Finished Jan 17 03:15:51 PM PST 24
Peak memory 191204 kb
Host smart-1971a12f-b796-4dc9-b2f6-8615d46f72d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360018380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.360018380
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.2844126994
Short name T176
Test name
Test status
Simulation time 122054017572 ps
CPU time 258.75 seconds
Started Jan 17 03:12:56 PM PST 24
Finished Jan 17 03:17:16 PM PST 24
Peak memory 191104 kb
Host smart-b1850993-b5b9-4c6e-9398-207f1d4244bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844126994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2844126994
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2691099078
Short name T48
Test name
Test status
Simulation time 1150173306137 ps
CPU time 509.35 seconds
Started Jan 17 03:13:14 PM PST 24
Finished Jan 17 03:21:52 PM PST 24
Peak memory 191144 kb
Host smart-4cecbfc1-a7d4-434b-b426-ec7c5d6aac65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691099078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2691099078
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.4286961312
Short name T227
Test name
Test status
Simulation time 86411657820 ps
CPU time 134.78 seconds
Started Jan 17 03:13:32 PM PST 24
Finished Jan 17 03:15:48 PM PST 24
Peak memory 194372 kb
Host smart-db4cfb59-8b6a-42e0-83fa-e5f55b2321c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286961312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.4286961312
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2535505209
Short name T286
Test name
Test status
Simulation time 91409867654 ps
CPU time 234.98 seconds
Started Jan 17 03:13:31 PM PST 24
Finished Jan 17 03:17:28 PM PST 24
Peak memory 191120 kb
Host smart-85c9f515-ddee-4e84-bcb7-95e5271b95ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535505209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2535505209
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.1118531693
Short name T129
Test name
Test status
Simulation time 410152747716 ps
CPU time 669.17 seconds
Started Jan 17 03:13:47 PM PST 24
Finished Jan 17 03:24:57 PM PST 24
Peak memory 191164 kb
Host smart-8221cf64-bbe2-4555-ab2f-169e019bfebc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118531693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1118531693
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.4015270619
Short name T309
Test name
Test status
Simulation time 254225634748 ps
CPU time 2748.79 seconds
Started Jan 17 03:13:50 PM PST 24
Finished Jan 17 03:59:39 PM PST 24
Peak memory 191088 kb
Host smart-475dcb5d-d0c6-4b8f-8900-571a12da22f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015270619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.4015270619
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.2112373360
Short name T251
Test name
Test status
Simulation time 431265701252 ps
CPU time 897.34 seconds
Started Jan 17 03:14:14 PM PST 24
Finished Jan 17 03:29:15 PM PST 24
Peak memory 194432 kb
Host smart-0e41e465-6c57-43a4-b389-6e0a278f6952
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112373360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2112373360
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.4289354313
Short name T137
Test name
Test status
Simulation time 108816594345 ps
CPU time 511.06 seconds
Started Jan 17 03:14:07 PM PST 24
Finished Jan 17 03:22:38 PM PST 24
Peak memory 194312 kb
Host smart-ce2573c2-9d9f-4bbb-84e8-0f3e7ad44808
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289354313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.4289354313
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.2444364691
Short name T98
Test name
Test status
Simulation time 134845220461 ps
CPU time 228.88 seconds
Started Jan 17 03:14:13 PM PST 24
Finished Jan 17 03:18:07 PM PST 24
Peak memory 193692 kb
Host smart-782b6de6-aea9-4a41-904d-01ad19756b0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444364691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2444364691
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.2719631502
Short name T200
Test name
Test status
Simulation time 337324786538 ps
CPU time 504.05 seconds
Started Jan 17 03:08:05 PM PST 24
Finished Jan 17 03:16:29 PM PST 24
Peak memory 191196 kb
Host smart-1bfca4de-0711-4935-94d3-6ba85ea3d6c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719631502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2719631502
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.295376340
Short name T230
Test name
Test status
Simulation time 402079395947 ps
CPU time 246.62 seconds
Started Jan 17 03:14:24 PM PST 24
Finished Jan 17 03:18:36 PM PST 24
Peak memory 191348 kb
Host smart-b7e2f38a-6300-4927-bf1d-f72e6128bd14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295376340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.295376340
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.2148443887
Short name T24
Test name
Test status
Simulation time 337643739228 ps
CPU time 171.94 seconds
Started Jan 17 03:14:30 PM PST 24
Finished Jan 17 03:17:22 PM PST 24
Peak memory 191072 kb
Host smart-763ea44e-445e-4e66-b792-6f7d9ae7813d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148443887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2148443887
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.574688777
Short name T165
Test name
Test status
Simulation time 118484567968 ps
CPU time 210.83 seconds
Started Jan 17 03:14:36 PM PST 24
Finished Jan 17 03:18:07 PM PST 24
Peak memory 191136 kb
Host smart-25075fd7-5e00-4a79-9d73-b32b1087f48b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574688777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.574688777
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.159304172
Short name T86
Test name
Test status
Simulation time 93566475748 ps
CPU time 171.97 seconds
Started Jan 17 03:08:09 PM PST 24
Finished Jan 17 03:11:01 PM PST 24
Peak memory 182956 kb
Host smart-2141e569-f869-474d-89a0-dc434cea9f0a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159304172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.rv_timer_cfg_update_on_fly.159304172
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_random.830955602
Short name T101
Test name
Test status
Simulation time 321947769025 ps
CPU time 179.5 seconds
Started Jan 17 03:08:15 PM PST 24
Finished Jan 17 03:11:16 PM PST 24
Peak memory 194212 kb
Host smart-fef915e9-6597-4c9f-8c11-5c1a048721e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830955602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.830955602
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.1867828750
Short name T264
Test name
Test status
Simulation time 320704688109 ps
CPU time 534.35 seconds
Started Jan 17 03:07:33 PM PST 24
Finished Jan 17 03:16:27 PM PST 24
Peak memory 182948 kb
Host smart-c2f1691e-2479-4d36-b084-7917160e1f24
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867828750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.1867828750
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3352826238
Short name T149
Test name
Test status
Simulation time 930668637914 ps
CPU time 504.88 seconds
Started Jan 17 03:08:59 PM PST 24
Finished Jan 17 03:17:28 PM PST 24
Peak memory 182988 kb
Host smart-9a2e5845-5a26-43fe-ba83-c4a32ae1f0f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352826238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3352826238
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/72.rv_timer_random.852220944
Short name T256
Test name
Test status
Simulation time 429118348446 ps
CPU time 211.05 seconds
Started Jan 17 03:11:42 PM PST 24
Finished Jan 17 03:15:14 PM PST 24
Peak memory 194060 kb
Host smart-909e0938-68d3-4362-ae25-1f27f3d3e4eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852220944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.852220944
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random.2062272871
Short name T354
Test name
Test status
Simulation time 471954971090 ps
CPU time 242.81 seconds
Started Jan 17 03:07:49 PM PST 24
Finished Jan 17 03:11:52 PM PST 24
Peak memory 193776 kb
Host smart-b9f2e7b5-ba40-4c35-bccd-83caf76a47c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062272871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2062272871
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1966201994
Short name T296
Test name
Test status
Simulation time 935088386530 ps
CPU time 312.79 seconds
Started Jan 17 03:07:25 PM PST 24
Finished Jan 17 03:12:39 PM PST 24
Peak memory 182920 kb
Host smart-777c587b-1137-4066-8f32-35dd561b05f5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966201994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1966201994
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.693818886
Short name T159
Test name
Test status
Simulation time 276787201467 ps
CPU time 471.51 seconds
Started Jan 17 03:07:51 PM PST 24
Finished Jan 17 03:15:44 PM PST 24
Peak memory 182960 kb
Host smart-5ecf9727-55ab-4b83-9062-0379c255c17a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693818886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.693818886
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.3777556898
Short name T121
Test name
Test status
Simulation time 389899991227 ps
CPU time 998.22 seconds
Started Jan 17 03:07:55 PM PST 24
Finished Jan 17 03:24:34 PM PST 24
Peak memory 191140 kb
Host smart-d1fe05fc-8ffb-42da-85a2-a448fb610bab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777556898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.3777556898
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/112.rv_timer_random.818472722
Short name T294
Test name
Test status
Simulation time 40305356765 ps
CPU time 55.87 seconds
Started Jan 17 03:12:39 PM PST 24
Finished Jan 17 03:13:35 PM PST 24
Peak memory 182912 kb
Host smart-b3e5eb01-adb8-4c91-b636-993b54409ec3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818472722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.818472722
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.2518922754
Short name T310
Test name
Test status
Simulation time 147048948543 ps
CPU time 720.97 seconds
Started Jan 17 03:13:14 PM PST 24
Finished Jan 17 03:25:23 PM PST 24
Peak memory 191244 kb
Host smart-c9a5c149-fff0-44da-ab58-6e30502f4f4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518922754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2518922754
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.1802190629
Short name T277
Test name
Test status
Simulation time 513285979640 ps
CPU time 1316.2 seconds
Started Jan 17 03:13:34 PM PST 24
Finished Jan 17 03:35:33 PM PST 24
Peak memory 191168 kb
Host smart-33a5469c-efa3-4f9b-b8a5-44cb0532d9be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802190629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1802190629
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.1952990928
Short name T315
Test name
Test status
Simulation time 32370590645 ps
CPU time 327.18 seconds
Started Jan 17 03:13:39 PM PST 24
Finished Jan 17 03:19:06 PM PST 24
Peak memory 182976 kb
Host smart-58a6ebd0-8cb4-4754-bb5a-e8d16243b0ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952990928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1952990928
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.4191141649
Short name T196
Test name
Test status
Simulation time 47369852247 ps
CPU time 68.53 seconds
Started Jan 17 03:13:56 PM PST 24
Finished Jan 17 03:15:05 PM PST 24
Peak memory 191164 kb
Host smart-f8f46c6b-cafd-4df7-865c-2477a64c383e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191141649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.4191141649
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.1512737799
Short name T238
Test name
Test status
Simulation time 146871133515 ps
CPU time 286.27 seconds
Started Jan 17 03:13:55 PM PST 24
Finished Jan 17 03:18:41 PM PST 24
Peak memory 182972 kb
Host smart-346b7458-3de4-4455-809e-c6e34aa2ddfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512737799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.1512737799
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.534475472
Short name T153
Test name
Test status
Simulation time 44931852879 ps
CPU time 70.47 seconds
Started Jan 17 03:14:14 PM PST 24
Finished Jan 17 03:15:28 PM PST 24
Peak memory 190892 kb
Host smart-4e10d5f2-f798-4283-8a5c-a182441f9508
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534475472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.534475472
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.2554552439
Short name T213
Test name
Test status
Simulation time 117158147195 ps
CPU time 487.22 seconds
Started Jan 17 03:14:10 PM PST 24
Finished Jan 17 03:22:19 PM PST 24
Peak memory 193568 kb
Host smart-9d3231de-625d-4f04-b78f-751bf7a835f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554552439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2554552439
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.1262026457
Short name T262
Test name
Test status
Simulation time 176724872286 ps
CPU time 134.71 seconds
Started Jan 17 03:14:12 PM PST 24
Finished Jan 17 03:16:30 PM PST 24
Peak memory 183000 kb
Host smart-109ca0d2-25ad-4866-8f11-93ed7d1e065c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262026457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1262026457
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.254604316
Short name T217
Test name
Test status
Simulation time 859853898693 ps
CPU time 665.44 seconds
Started Jan 17 03:07:58 PM PST 24
Finished Jan 17 03:19:08 PM PST 24
Peak memory 191080 kb
Host smart-2694002d-d5d2-459c-ad37-882d930c2e6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254604316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.254604316
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.3996367690
Short name T305
Test name
Test status
Simulation time 88723844906 ps
CPU time 766.36 seconds
Started Jan 17 03:08:00 PM PST 24
Finished Jan 17 03:20:49 PM PST 24
Peak memory 205828 kb
Host smart-e3a84c32-04e3-46be-b0d0-652b2d3d076b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996367690 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.3996367690
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/186.rv_timer_random.3287650488
Short name T259
Test name
Test status
Simulation time 80395825225 ps
CPU time 135.87 seconds
Started Jan 17 03:14:18 PM PST 24
Finished Jan 17 03:16:44 PM PST 24
Peak memory 191152 kb
Host smart-bd8b8595-4dbc-4a0f-bab3-dff5a5ecf88c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287650488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3287650488
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3381841223
Short name T218
Test name
Test status
Simulation time 740429953125 ps
CPU time 829.21 seconds
Started Jan 17 03:14:25 PM PST 24
Finished Jan 17 03:28:18 PM PST 24
Peak memory 194508 kb
Host smart-bda11062-30da-4d64-92ac-8736217ff94e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381841223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3381841223
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1385445226
Short name T91
Test name
Test status
Simulation time 2695718331691 ps
CPU time 890.44 seconds
Started Jan 17 03:08:04 PM PST 24
Finished Jan 17 03:22:55 PM PST 24
Peak memory 183008 kb
Host smart-efd9f1e5-8567-4d52-b35e-8ecf42d8acc9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385445226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.1385445226
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.1304425538
Short name T104
Test name
Test status
Simulation time 1012454500788 ps
CPU time 951.78 seconds
Started Jan 17 03:08:05 PM PST 24
Finished Jan 17 03:23:57 PM PST 24
Peak memory 191176 kb
Host smart-79b23970-e860-4963-84db-ba38afd99dd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304425538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.1304425538
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2585895940
Short name T139
Test name
Test status
Simulation time 485295994803 ps
CPU time 834.14 seconds
Started Jan 17 03:08:04 PM PST 24
Finished Jan 17 03:21:59 PM PST 24
Peak memory 182892 kb
Host smart-5a82c9db-a6cf-4055-8eb8-cbd4152f5b7a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585895940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.2585895940
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_random.1631337872
Short name T226
Test name
Test status
Simulation time 274202929817 ps
CPU time 257.83 seconds
Started Jan 17 03:08:15 PM PST 24
Finished Jan 17 03:12:34 PM PST 24
Peak memory 191168 kb
Host smart-1e4c2ea2-c812-46bd-892c-db6f3f35ec7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631337872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1631337872
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1809081951
Short name T299
Test name
Test status
Simulation time 6536011750397 ps
CPU time 1262.93 seconds
Started Jan 17 03:09:13 PM PST 24
Finished Jan 17 03:30:18 PM PST 24
Peak memory 191176 kb
Host smart-06a269c7-3a4f-4509-b192-e172425b593a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809081951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1809081951
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2274565199
Short name T298
Test name
Test status
Simulation time 44711149913 ps
CPU time 37.5 seconds
Started Jan 17 03:10:21 PM PST 24
Finished Jan 17 03:11:01 PM PST 24
Peak memory 182944 kb
Host smart-ea396d61-d359-4427-9801-e8e1df311010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274565199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2274565199
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3943301929
Short name T154
Test name
Test status
Simulation time 2783245140596 ps
CPU time 751.75 seconds
Started Jan 17 03:10:32 PM PST 24
Finished Jan 17 03:23:04 PM PST 24
Peak memory 182972 kb
Host smart-8cc33787-857a-48b4-9c90-ca1ff30a22a3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943301929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3943301929
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_random.3688409360
Short name T306
Test name
Test status
Simulation time 60688795721 ps
CPU time 24.09 seconds
Started Jan 17 03:10:47 PM PST 24
Finished Jan 17 03:11:13 PM PST 24
Peak memory 182704 kb
Host smart-d1828da6-3f66-4503-813b-29279783070e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688409360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3688409360
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1573920606
Short name T54
Test name
Test status
Simulation time 45818448 ps
CPU time 0.65 seconds
Started Jan 17 01:02:11 PM PST 24
Finished Jan 17 01:02:13 PM PST 24
Peak memory 183328 kb
Host smart-28a48465-16a4-4c12-9082-52707b404695
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573920606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.1573920606
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.214049639
Short name T368
Test name
Test status
Simulation time 941556633 ps
CPU time 1.49 seconds
Started Jan 17 01:02:05 PM PST 24
Finished Jan 17 01:02:12 PM PST 24
Peak memory 192716 kb
Host smart-b772f4d2-e6c2-4f67-81ca-c0b90af91d5a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214049639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.214049639
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1996115168
Short name T52
Test name
Test status
Simulation time 47650307 ps
CPU time 0.56 seconds
Started Jan 17 01:01:56 PM PST 24
Finished Jan 17 01:01:58 PM PST 24
Peak memory 183248 kb
Host smart-64d28cd1-4939-4805-8d64-5405ddb650a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996115168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.1996115168
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.809327640
Short name T392
Test name
Test status
Simulation time 35537756 ps
CPU time 1.07 seconds
Started Jan 17 01:02:09 PM PST 24
Finished Jan 17 01:02:12 PM PST 24
Peak memory 197856 kb
Host smart-4f0f9237-9bc3-4ea2-833c-788e4459f75e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809327640 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.809327640
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.4038736374
Short name T452
Test name
Test status
Simulation time 12208192 ps
CPU time 0.52 seconds
Started Jan 17 01:01:56 PM PST 24
Finished Jan 17 01:01:57 PM PST 24
Peak memory 183208 kb
Host smart-28f09475-26e3-4b78-8479-1ddd9a229503
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038736374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.4038736374
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1634260863
Short name T64
Test name
Test status
Simulation time 27942720 ps
CPU time 0.59 seconds
Started Jan 17 01:01:55 PM PST 24
Finished Jan 17 01:01:56 PM PST 24
Peak memory 182820 kb
Host smart-3694a7da-815d-4596-a611-6217efba5f13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634260863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1634260863
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2972585182
Short name T420
Test name
Test status
Simulation time 25955455 ps
CPU time 0.72 seconds
Started Jan 17 01:02:13 PM PST 24
Finished Jan 17 01:02:16 PM PST 24
Peak memory 192632 kb
Host smart-1adda38d-e04a-495f-bcb2-04b571ff953a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972585182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2972585182
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1283425043
Short name T386
Test name
Test status
Simulation time 251766618 ps
CPU time 1.5 seconds
Started Jan 17 01:01:57 PM PST 24
Finished Jan 17 01:01:59 PM PST 24
Peak memory 198088 kb
Host smart-8cfc5530-50ff-46d9-a14c-48aafab157a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283425043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1283425043
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1819947664
Short name T448
Test name
Test status
Simulation time 45286993 ps
CPU time 0.73 seconds
Started Jan 17 01:02:14 PM PST 24
Finished Jan 17 01:02:17 PM PST 24
Peak memory 192964 kb
Host smart-30231892-8613-41b8-a312-e85929deefbf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819947664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1819947664
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1288911089
Short name T401
Test name
Test status
Simulation time 171100776 ps
CPU time 3.22 seconds
Started Jan 17 01:02:12 PM PST 24
Finished Jan 17 01:02:18 PM PST 24
Peak memory 183380 kb
Host smart-ea31306d-babd-44a3-a9b1-ddb124d88f9d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288911089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.1288911089
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.4138957479
Short name T396
Test name
Test status
Simulation time 178387872 ps
CPU time 0.55 seconds
Started Jan 17 01:02:12 PM PST 24
Finished Jan 17 01:02:13 PM PST 24
Peak memory 182612 kb
Host smart-16b19046-3371-4223-8985-6133507fd7a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138957479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.4138957479
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.831211526
Short name T423
Test name
Test status
Simulation time 75560031 ps
CPU time 1.03 seconds
Started Jan 17 01:02:15 PM PST 24
Finished Jan 17 01:02:18 PM PST 24
Peak memory 197940 kb
Host smart-de9229eb-e493-4f89-bfb9-e08790209653
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831211526 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.831211526
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2963385747
Short name T451
Test name
Test status
Simulation time 13391636 ps
CPU time 0.56 seconds
Started Jan 17 01:02:10 PM PST 24
Finished Jan 17 01:02:11 PM PST 24
Peak memory 183288 kb
Host smart-110f9edd-e2bc-4926-bff6-8859853418ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963385747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2963385747
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.574428851
Short name T80
Test name
Test status
Simulation time 28279265 ps
CPU time 0.59 seconds
Started Jan 17 01:02:08 PM PST 24
Finished Jan 17 01:02:11 PM PST 24
Peak memory 182936 kb
Host smart-a61c0c6d-acbc-435c-938e-e630b3a19fd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574428851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.574428851
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.4006281690
Short name T362
Test name
Test status
Simulation time 173981305 ps
CPU time 2.31 seconds
Started Jan 17 01:02:12 PM PST 24
Finished Jan 17 01:02:17 PM PST 24
Peak memory 197944 kb
Host smart-1ec47a94-947e-48ba-9993-c0abcad9b9f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006281690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.4006281690
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1890059840
Short name T97
Test name
Test status
Simulation time 404270517 ps
CPU time 1.37 seconds
Started Jan 17 01:02:07 PM PST 24
Finished Jan 17 01:02:12 PM PST 24
Peak memory 195596 kb
Host smart-ded27f18-847a-4488-aa92-cb73ddc3ac82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890059840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1890059840
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.653988489
Short name T382
Test name
Test status
Simulation time 24627124 ps
CPU time 0.79 seconds
Started Jan 17 01:02:20 PM PST 24
Finished Jan 17 01:02:21 PM PST 24
Peak memory 195932 kb
Host smart-cf2119d0-b0e9-4842-b670-f9f076bbfee8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653988489 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.653988489
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1418587632
Short name T56
Test name
Test status
Simulation time 30688919 ps
CPU time 0.59 seconds
Started Jan 17 01:02:27 PM PST 24
Finished Jan 17 01:02:28 PM PST 24
Peak memory 183204 kb
Host smart-d96ed5c1-629c-4db9-8360-6acd40da3c7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418587632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1418587632
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.981687668
Short name T455
Test name
Test status
Simulation time 10814966 ps
CPU time 0.6 seconds
Started Jan 17 01:02:25 PM PST 24
Finished Jan 17 01:02:27 PM PST 24
Peak memory 182128 kb
Host smart-051b6612-5e58-42c7-8725-0270c4d619ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981687668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.981687668
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3145682247
Short name T85
Test name
Test status
Simulation time 143351938 ps
CPU time 0.8 seconds
Started Jan 17 01:02:23 PM PST 24
Finished Jan 17 01:02:24 PM PST 24
Peak memory 192188 kb
Host smart-a3424a02-458a-457a-b071-8d78c91e8ddd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145682247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3145682247
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3822271514
Short name T418
Test name
Test status
Simulation time 92850152 ps
CPU time 1.08 seconds
Started Jan 17 01:02:19 PM PST 24
Finished Jan 17 01:02:21 PM PST 24
Peak memory 197696 kb
Host smart-1766d76e-89ae-4772-b313-2a0a4d15ecca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822271514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3822271514
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1996380099
Short name T408
Test name
Test status
Simulation time 43476564 ps
CPU time 0.84 seconds
Started Jan 17 01:02:23 PM PST 24
Finished Jan 17 01:02:25 PM PST 24
Peak memory 193744 kb
Host smart-df1a82fa-594d-4a38-99d2-8c4bb3c05e0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996380099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1996380099
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2870489233
Short name T82
Test name
Test status
Simulation time 101511471 ps
CPU time 1.43 seconds
Started Jan 17 01:02:30 PM PST 24
Finished Jan 17 01:02:33 PM PST 24
Peak memory 198092 kb
Host smart-deac5bce-fb2c-46a8-9d2e-db8dadf0146f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870489233 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2870489233
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.191479839
Short name T388
Test name
Test status
Simulation time 37549323 ps
CPU time 0.65 seconds
Started Jan 17 01:02:22 PM PST 24
Finished Jan 17 01:02:23 PM PST 24
Peak memory 183316 kb
Host smart-541ba7ef-9435-40d2-9e28-e575746f8f4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191479839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.191479839
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.4242343792
Short name T363
Test name
Test status
Simulation time 42265464 ps
CPU time 0.57 seconds
Started Jan 17 01:02:21 PM PST 24
Finished Jan 17 01:02:22 PM PST 24
Peak memory 182992 kb
Host smart-afa9476a-c9a1-4b7a-be13-a0bf3826787d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242343792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.4242343792
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2673634658
Short name T57
Test name
Test status
Simulation time 146358548 ps
CPU time 0.83 seconds
Started Jan 17 01:02:30 PM PST 24
Finished Jan 17 01:02:32 PM PST 24
Peak memory 192220 kb
Host smart-7edb1f7d-1938-40d5-8bc8-4997a0bd5f5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673634658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2673634658
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.4280893640
Short name T36
Test name
Test status
Simulation time 73683155 ps
CPU time 1.81 seconds
Started Jan 17 01:02:27 PM PST 24
Finished Jan 17 01:02:29 PM PST 24
Peak memory 197616 kb
Host smart-99c9aa10-f596-48e6-86c2-5f76c492e074
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280893640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.4280893640
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.4097608038
Short name T366
Test name
Test status
Simulation time 1597423071 ps
CPU time 1.31 seconds
Started Jan 17 01:02:30 PM PST 24
Finished Jan 17 01:02:32 PM PST 24
Peak memory 183420 kb
Host smart-f1c6b0ad-e358-4789-aeaa-52b70d0bfa33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097608038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.4097608038
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2213514909
Short name T460
Test name
Test status
Simulation time 72243604 ps
CPU time 0.69 seconds
Started Jan 17 01:02:26 PM PST 24
Finished Jan 17 01:02:28 PM PST 24
Peak memory 195396 kb
Host smart-3bbe2d7f-ab1a-412d-bb05-b98666ea6ed2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213514909 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2213514909
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2064428584
Short name T440
Test name
Test status
Simulation time 60439894 ps
CPU time 0.57 seconds
Started Jan 17 01:02:28 PM PST 24
Finished Jan 17 01:02:30 PM PST 24
Peak memory 183300 kb
Host smart-7bc198fe-e68d-4a73-aaf2-5b720876ab35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064428584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2064428584
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.791520963
Short name T409
Test name
Test status
Simulation time 34326331 ps
CPU time 0.56 seconds
Started Jan 17 01:02:27 PM PST 24
Finished Jan 17 01:02:28 PM PST 24
Peak memory 182956 kb
Host smart-e5e76891-5587-4397-ac19-9d59e6cb5548
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791520963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.791520963
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.415013621
Short name T405
Test name
Test status
Simulation time 23040465 ps
CPU time 0.89 seconds
Started Jan 17 01:02:34 PM PST 24
Finished Jan 17 01:02:38 PM PST 24
Peak memory 194452 kb
Host smart-1d08f090-7ad8-492c-8ab7-6bcf11cd9dda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415013621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_ti
mer_same_csr_outstanding.415013621
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1564078211
Short name T406
Test name
Test status
Simulation time 102408005 ps
CPU time 1.02 seconds
Started Jan 17 01:02:30 PM PST 24
Finished Jan 17 01:02:32 PM PST 24
Peak memory 191420 kb
Host smart-fc4ecfbd-e8df-442b-8632-b4724e934e00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564078211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1564078211
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2674877890
Short name T472
Test name
Test status
Simulation time 80617215 ps
CPU time 1.1 seconds
Started Jan 17 01:02:24 PM PST 24
Finished Jan 17 01:02:26 PM PST 24
Peak memory 183612 kb
Host smart-523030cb-6ddc-4f10-8d31-7d8c3e4b67fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674877890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2674877890
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.948635139
Short name T441
Test name
Test status
Simulation time 35959921 ps
CPU time 1.11 seconds
Started Jan 17 01:02:32 PM PST 24
Finished Jan 17 01:02:34 PM PST 24
Peak memory 197952 kb
Host smart-1b62c71a-bf90-402c-9695-2fd2c5b0283a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948635139 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.948635139
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3365048301
Short name T83
Test name
Test status
Simulation time 85576366 ps
CPU time 0.58 seconds
Started Jan 17 01:02:27 PM PST 24
Finished Jan 17 01:02:28 PM PST 24
Peak memory 183324 kb
Host smart-f738e5e6-ae95-40f0-809b-dde406bae0b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365048301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3365048301
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1454945363
Short name T397
Test name
Test status
Simulation time 30792841 ps
CPU time 0.55 seconds
Started Jan 17 01:02:23 PM PST 24
Finished Jan 17 01:02:25 PM PST 24
Peak memory 182832 kb
Host smart-372cb3ba-b719-4d4a-bb50-2165cefe6742
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454945363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1454945363
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3360543071
Short name T471
Test name
Test status
Simulation time 38240638 ps
CPU time 0.76 seconds
Started Jan 17 01:02:22 PM PST 24
Finished Jan 17 01:02:24 PM PST 24
Peak memory 193644 kb
Host smart-cf047ff7-7c47-4334-ab04-4e18731d2e14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360543071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.3360543071
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2490088914
Short name T466
Test name
Test status
Simulation time 378313594 ps
CPU time 2.36 seconds
Started Jan 17 01:02:28 PM PST 24
Finished Jan 17 01:02:31 PM PST 24
Peak memory 198056 kb
Host smart-9407e69d-9fa6-4631-9d25-3ccafe57dd77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490088914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2490088914
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3322385723
Short name T28
Test name
Test status
Simulation time 148760717 ps
CPU time 0.83 seconds
Started Jan 17 01:02:24 PM PST 24
Finished Jan 17 01:02:26 PM PST 24
Peak memory 193940 kb
Host smart-925ca36e-1786-424f-a5bb-ffaa423953cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322385723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3322385723
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1552931256
Short name T77
Test name
Test status
Simulation time 23890482 ps
CPU time 0.71 seconds
Started Jan 17 01:02:32 PM PST 24
Finished Jan 17 01:02:33 PM PST 24
Peak memory 195748 kb
Host smart-46349cf6-cb70-40e9-8ece-7f51c2f4ca7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552931256 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.1552931256
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3227321969
Short name T442
Test name
Test status
Simulation time 23371742 ps
CPU time 0.57 seconds
Started Jan 17 01:02:46 PM PST 24
Finished Jan 17 01:02:48 PM PST 24
Peak memory 183296 kb
Host smart-36a120fc-8ca8-427b-8203-3a6814100ca5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227321969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3227321969
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2234180650
Short name T365
Test name
Test status
Simulation time 52423322 ps
CPU time 0.56 seconds
Started Jan 17 01:02:37 PM PST 24
Finished Jan 17 01:02:40 PM PST 24
Peak memory 182424 kb
Host smart-6bbe4abe-a6c0-4a84-aee7-4a6252c05f5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234180650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2234180650
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3188299703
Short name T414
Test name
Test status
Simulation time 18892285 ps
CPU time 0.6 seconds
Started Jan 17 01:02:26 PM PST 24
Finished Jan 17 01:02:27 PM PST 24
Peak memory 192552 kb
Host smart-664250c4-efbc-4650-a5f7-bc03c3bbdded
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188299703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3188299703
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3117075057
Short name T413
Test name
Test status
Simulation time 151008432 ps
CPU time 2.91 seconds
Started Jan 17 01:02:31 PM PST 24
Finished Jan 17 01:02:35 PM PST 24
Peak memory 198052 kb
Host smart-ff7f86de-578c-4dea-86b5-2810d5b212c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117075057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3117075057
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1005255061
Short name T458
Test name
Test status
Simulation time 142450480 ps
CPU time 0.95 seconds
Started Jan 17 01:02:25 PM PST 24
Finished Jan 17 01:02:27 PM PST 24
Peak memory 183444 kb
Host smart-c929319e-2b29-466b-94c8-a15665fa2f42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005255061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1005255061
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.4050077116
Short name T387
Test name
Test status
Simulation time 20513309 ps
CPU time 0.72 seconds
Started Jan 17 01:02:37 PM PST 24
Finished Jan 17 01:02:40 PM PST 24
Peak memory 195528 kb
Host smart-1b935731-b984-4a40-b7a3-e12621646952
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050077116 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.4050077116
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3392312094
Short name T55
Test name
Test status
Simulation time 54978392 ps
CPU time 0.57 seconds
Started Jan 17 01:02:48 PM PST 24
Finished Jan 17 01:02:50 PM PST 24
Peak memory 183332 kb
Host smart-37e7894a-ce41-4bc5-baab-364fffd9a279
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392312094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3392312094
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.987293124
Short name T428
Test name
Test status
Simulation time 14506289 ps
CPU time 0.56 seconds
Started Jan 17 01:02:35 PM PST 24
Finished Jan 17 01:02:39 PM PST 24
Peak memory 182864 kb
Host smart-6cdf5e81-c061-45fd-a5f6-bc66ccbef1b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987293124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.987293124
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3302796403
Short name T438
Test name
Test status
Simulation time 56573871 ps
CPU time 0.73 seconds
Started Jan 17 01:02:31 PM PST 24
Finished Jan 17 01:02:33 PM PST 24
Peak memory 192008 kb
Host smart-29ed0df9-c900-4bdc-b34d-2927186cbc6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302796403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3302796403
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.4123479115
Short name T383
Test name
Test status
Simulation time 31025735 ps
CPU time 1.52 seconds
Started Jan 17 01:02:31 PM PST 24
Finished Jan 17 01:02:33 PM PST 24
Peak memory 197632 kb
Host smart-f6110aa8-135c-4680-96bf-f8c0be8b655b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123479115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.4123479115
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3816315684
Short name T410
Test name
Test status
Simulation time 795419504 ps
CPU time 1.45 seconds
Started Jan 17 01:02:26 PM PST 24
Finished Jan 17 01:02:28 PM PST 24
Peak memory 183596 kb
Host smart-df1a7426-c44e-4e9f-8077-d74f24295dd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816315684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3816315684
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.618072136
Short name T38
Test name
Test status
Simulation time 17698014 ps
CPU time 0.67 seconds
Started Jan 17 01:02:31 PM PST 24
Finished Jan 17 01:02:32 PM PST 24
Peak memory 194412 kb
Host smart-8e727417-c599-4c20-ac8a-6918104df7c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618072136 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.618072136
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2426485936
Short name T415
Test name
Test status
Simulation time 45382913 ps
CPU time 0.56 seconds
Started Jan 17 01:02:30 PM PST 24
Finished Jan 17 01:02:31 PM PST 24
Peak memory 183240 kb
Host smart-6ded4609-d9ea-497c-8f49-551bb06f52df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426485936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.2426485936
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1050310345
Short name T60
Test name
Test status
Simulation time 11912572 ps
CPU time 0.54 seconds
Started Jan 17 01:02:33 PM PST 24
Finished Jan 17 01:02:35 PM PST 24
Peak memory 182120 kb
Host smart-3e97c555-f13b-4bf2-b3c2-3f0eb7ade1d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050310345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1050310345
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.4124087938
Short name T443
Test name
Test status
Simulation time 76671634 ps
CPU time 0.81 seconds
Started Jan 17 01:02:49 PM PST 24
Finished Jan 17 01:02:51 PM PST 24
Peak memory 193824 kb
Host smart-aeb3d2b4-43b9-4225-b14a-7e5cfe39f9cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124087938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.4124087938
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.4065676998
Short name T76
Test name
Test status
Simulation time 231569804 ps
CPU time 1.5 seconds
Started Jan 17 01:02:34 PM PST 24
Finished Jan 17 01:02:38 PM PST 24
Peak memory 196848 kb
Host smart-dd32536d-db83-4970-bae6-3e71353f5f9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065676998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.4065676998
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1955605507
Short name T384
Test name
Test status
Simulation time 199258273 ps
CPU time 0.97 seconds
Started Jan 17 01:02:31 PM PST 24
Finished Jan 17 01:02:32 PM PST 24
Peak memory 194052 kb
Host smart-9d953c01-f941-4454-bae7-1fe1d6a3ce2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955605507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.1955605507
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2370652412
Short name T367
Test name
Test status
Simulation time 30285676 ps
CPU time 0.95 seconds
Started Jan 17 01:02:34 PM PST 24
Finished Jan 17 01:02:38 PM PST 24
Peak memory 195548 kb
Host smart-c89fb01a-3a6e-434a-be2c-4fc5b59d8dcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370652412 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2370652412
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.883166328
Short name T84
Test name
Test status
Simulation time 11288188 ps
CPU time 0.56 seconds
Started Jan 17 01:02:34 PM PST 24
Finished Jan 17 01:02:37 PM PST 24
Peak memory 183300 kb
Host smart-2b63e15a-383c-4257-b4c5-0ea4fc05c82b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883166328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.883166328
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3290780489
Short name T44
Test name
Test status
Simulation time 15317860 ps
CPU time 0.57 seconds
Started Jan 17 01:02:43 PM PST 24
Finished Jan 17 01:02:48 PM PST 24
Peak memory 182928 kb
Host smart-ab4efa8b-871a-4605-81e9-4aa53658b064
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290780489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3290780489
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3773101449
Short name T390
Test name
Test status
Simulation time 28320347 ps
CPU time 0.7 seconds
Started Jan 17 01:02:37 PM PST 24
Finished Jan 17 01:02:41 PM PST 24
Peak memory 192440 kb
Host smart-130ebaaf-b3d7-4498-b6ad-60a4bfcce282
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773101449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3773101449
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1932037638
Short name T454
Test name
Test status
Simulation time 36240613 ps
CPU time 1.66 seconds
Started Jan 17 01:02:49 PM PST 24
Finished Jan 17 01:02:52 PM PST 24
Peak memory 198012 kb
Host smart-387fa8a3-9dd7-450f-96a6-bc432c3ce29e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932037638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1932037638
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1420258236
Short name T96
Test name
Test status
Simulation time 283836193 ps
CPU time 1.08 seconds
Started Jan 17 01:02:29 PM PST 24
Finished Jan 17 01:02:31 PM PST 24
Peak memory 183488 kb
Host smart-78e65e49-d548-484b-a802-fbee7b71fd6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420258236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1420258236
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2692739089
Short name T393
Test name
Test status
Simulation time 27206424 ps
CPU time 0.86 seconds
Started Jan 17 01:02:32 PM PST 24
Finished Jan 17 01:02:34 PM PST 24
Peak memory 196816 kb
Host smart-414e645e-cce3-492d-9224-f9bd552740bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692739089 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.2692739089
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3684658118
Short name T14
Test name
Test status
Simulation time 18145522 ps
CPU time 0.59 seconds
Started Jan 17 01:02:30 PM PST 24
Finished Jan 17 01:02:31 PM PST 24
Peak memory 192460 kb
Host smart-bca5467b-cdfc-4b33-8883-e5402187c637
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684658118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3684658118
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2705153013
Short name T470
Test name
Test status
Simulation time 42048068 ps
CPU time 0.56 seconds
Started Jan 17 01:02:31 PM PST 24
Finished Jan 17 01:02:32 PM PST 24
Peak memory 182912 kb
Host smart-1d727944-e495-41e6-9381-6856ff952b63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705153013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2705153013
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.4040985108
Short name T29
Test name
Test status
Simulation time 35059972 ps
CPU time 0.81 seconds
Started Jan 17 01:02:31 PM PST 24
Finished Jan 17 01:02:32 PM PST 24
Peak memory 193776 kb
Host smart-ba7ef5f8-c2a2-4d02-a1c1-66e7e9f44c40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040985108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.4040985108
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.38368239
Short name T378
Test name
Test status
Simulation time 225676751 ps
CPU time 1.44 seconds
Started Jan 17 01:02:31 PM PST 24
Finished Jan 17 01:02:33 PM PST 24
Peak memory 197920 kb
Host smart-8e06ee20-06e9-41e8-a5c0-58852132525f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38368239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.38368239
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.4140686627
Short name T416
Test name
Test status
Simulation time 422055859 ps
CPU time 1.56 seconds
Started Jan 17 01:02:32 PM PST 24
Finished Jan 17 01:02:35 PM PST 24
Peak memory 183652 kb
Host smart-bb861143-fa9f-4249-a9be-51407684735e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140686627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.4140686627
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2600893751
Short name T39
Test name
Test status
Simulation time 38289527 ps
CPU time 0.93 seconds
Started Jan 17 01:02:33 PM PST 24
Finished Jan 17 01:02:37 PM PST 24
Peak memory 197644 kb
Host smart-753b7f58-b212-4cfd-8e2f-37e9b3abdbb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600893751 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2600893751
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.775344271
Short name T68
Test name
Test status
Simulation time 32008727 ps
CPU time 0.59 seconds
Started Jan 17 01:02:49 PM PST 24
Finished Jan 17 01:02:50 PM PST 24
Peak memory 183316 kb
Host smart-5772f851-9121-413d-8a75-19f9723f1d6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775344271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.775344271
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3209347727
Short name T436
Test name
Test status
Simulation time 50446090 ps
CPU time 0.58 seconds
Started Jan 17 01:02:34 PM PST 24
Finished Jan 17 01:02:37 PM PST 24
Peak memory 182972 kb
Host smart-a7e2557f-61e3-4cbc-88c6-5887a3acba25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209347727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3209347727
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1348372042
Short name T59
Test name
Test status
Simulation time 96959941 ps
CPU time 0.72 seconds
Started Jan 17 01:02:36 PM PST 24
Finished Jan 17 01:02:40 PM PST 24
Peak memory 193744 kb
Host smart-32fe55b8-97e5-4442-bc08-4b716f626321
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348372042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.1348372042
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1018636989
Short name T62
Test name
Test status
Simulation time 73891009 ps
CPU time 1.09 seconds
Started Jan 17 01:02:34 PM PST 24
Finished Jan 17 01:02:38 PM PST 24
Peak memory 197728 kb
Host smart-b26a7922-30d1-445c-a0a4-c7a8ca40cb0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018636989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1018636989
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1624543315
Short name T364
Test name
Test status
Simulation time 149398181 ps
CPU time 0.81 seconds
Started Jan 17 01:02:31 PM PST 24
Finished Jan 17 01:02:33 PM PST 24
Peak memory 193936 kb
Host smart-8c67276b-db04-492b-8962-b8dad17e61f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624543315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1624543315
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3377910955
Short name T51
Test name
Test status
Simulation time 16346866 ps
CPU time 0.71 seconds
Started Jan 17 01:02:11 PM PST 24
Finished Jan 17 01:02:12 PM PST 24
Peak memory 192568 kb
Host smart-aaabb6c7-779b-4092-b5bb-4c99cb0d444d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377910955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3377910955
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2526332970
Short name T374
Test name
Test status
Simulation time 17289114 ps
CPU time 0.57 seconds
Started Jan 17 01:02:12 PM PST 24
Finished Jan 17 01:02:13 PM PST 24
Peak memory 183352 kb
Host smart-3a3046a6-6bf5-4999-b26b-dfb5dae4c733
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526332970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2526332970
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2224618853
Short name T462
Test name
Test status
Simulation time 46625294 ps
CPU time 0.68 seconds
Started Jan 17 01:02:09 PM PST 24
Finished Jan 17 01:02:11 PM PST 24
Peak memory 194760 kb
Host smart-11ef39e0-995d-40c5-a281-a5d71ed157cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224618853 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2224618853
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.547985449
Short name T72
Test name
Test status
Simulation time 40049888 ps
CPU time 0.6 seconds
Started Jan 17 01:02:13 PM PST 24
Finished Jan 17 01:02:17 PM PST 24
Peak memory 183264 kb
Host smart-ee61b73a-eb49-4fb6-86a1-f01613b27785
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547985449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.547985449
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3467779818
Short name T439
Test name
Test status
Simulation time 17318142 ps
CPU time 0.61 seconds
Started Jan 17 01:02:09 PM PST 24
Finished Jan 17 01:02:11 PM PST 24
Peak memory 182876 kb
Host smart-12bc2547-51fe-41b7-89f8-5e70d0f716ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467779818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3467779818
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.4014010051
Short name T391
Test name
Test status
Simulation time 33129435 ps
CPU time 0.78 seconds
Started Jan 17 01:02:13 PM PST 24
Finished Jan 17 01:02:16 PM PST 24
Peak memory 193656 kb
Host smart-d7f33ff3-c03e-4132-ace9-79a0d1e81dc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014010051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.4014010051
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.294783646
Short name T74
Test name
Test status
Simulation time 78864420 ps
CPU time 2.67 seconds
Started Jan 17 01:02:08 PM PST 24
Finished Jan 17 01:02:13 PM PST 24
Peak memory 198088 kb
Host smart-da3544ca-d737-4235-ac95-be9eab8fa91f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294783646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.294783646
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.660770562
Short name T435
Test name
Test status
Simulation time 96653779 ps
CPU time 1.3 seconds
Started Jan 17 01:02:24 PM PST 24
Finished Jan 17 01:02:26 PM PST 24
Peak memory 183672 kb
Host smart-30d3c114-ca9d-4728-950f-0ab6d01245d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660770562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_int
g_err.660770562
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1097002365
Short name T400
Test name
Test status
Simulation time 18070481 ps
CPU time 0.56 seconds
Started Jan 17 01:02:29 PM PST 24
Finished Jan 17 01:02:31 PM PST 24
Peak memory 182820 kb
Host smart-92479326-a0f8-40ef-a59a-e0ee5ab48873
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097002365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1097002365
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1795759666
Short name T433
Test name
Test status
Simulation time 139534156 ps
CPU time 0.56 seconds
Started Jan 17 01:02:29 PM PST 24
Finished Jan 17 01:02:31 PM PST 24
Peak memory 182856 kb
Host smart-1f1df098-7032-43a9-a7af-c372a38a1a28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795759666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1795759666
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2454237449
Short name T376
Test name
Test status
Simulation time 17544773 ps
CPU time 0.54 seconds
Started Jan 17 01:02:33 PM PST 24
Finished Jan 17 01:02:35 PM PST 24
Peak memory 182932 kb
Host smart-6c99ed15-2334-4dd0-9cf8-431680cc2802
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454237449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2454237449
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1466303525
Short name T398
Test name
Test status
Simulation time 14406899 ps
CPU time 0.53 seconds
Started Jan 17 01:02:36 PM PST 24
Finished Jan 17 01:02:40 PM PST 24
Peak memory 182536 kb
Host smart-0305e971-fb58-487e-b06e-509120669347
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466303525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1466303525
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.67119375
Short name T426
Test name
Test status
Simulation time 17715164 ps
CPU time 0.6 seconds
Started Jan 17 01:02:48 PM PST 24
Finished Jan 17 01:02:50 PM PST 24
Peak memory 182968 kb
Host smart-8778caba-b72e-4f93-82da-5ca2907c9a25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67119375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.67119375
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.351706732
Short name T417
Test name
Test status
Simulation time 43643400 ps
CPU time 0.54 seconds
Started Jan 17 01:02:38 PM PST 24
Finished Jan 17 01:02:40 PM PST 24
Peak memory 182928 kb
Host smart-785aebea-9fb8-4377-a20d-912522522489
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351706732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.351706732
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3607555340
Short name T61
Test name
Test status
Simulation time 25926854 ps
CPU time 0.57 seconds
Started Jan 17 01:02:32 PM PST 24
Finished Jan 17 01:02:33 PM PST 24
Peak memory 182900 kb
Host smart-e908741e-853a-458f-81a8-a07c3f4af032
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607555340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.3607555340
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.357840550
Short name T403
Test name
Test status
Simulation time 82797168 ps
CPU time 0.55 seconds
Started Jan 17 01:02:49 PM PST 24
Finished Jan 17 01:02:50 PM PST 24
Peak memory 182960 kb
Host smart-420a8e6f-07bc-4991-95f9-fef6c22bf2ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357840550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.357840550
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2066633424
Short name T389
Test name
Test status
Simulation time 12216404 ps
CPU time 0.54 seconds
Started Jan 17 01:02:36 PM PST 24
Finished Jan 17 01:02:40 PM PST 24
Peak memory 182296 kb
Host smart-ec193d10-a716-4524-a1d9-efcc4f3d6c93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066633424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2066633424
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.512947628
Short name T371
Test name
Test status
Simulation time 24166044 ps
CPU time 0.54 seconds
Started Jan 17 01:02:31 PM PST 24
Finished Jan 17 01:02:32 PM PST 24
Peak memory 182848 kb
Host smart-4e7e2499-65d9-4493-894b-f809ffd87eed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512947628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.512947628
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.443040034
Short name T444
Test name
Test status
Simulation time 30048249 ps
CPU time 0.72 seconds
Started Jan 17 01:02:08 PM PST 24
Finished Jan 17 01:02:11 PM PST 24
Peak memory 192816 kb
Host smart-62a2808c-e8b5-4d84-a94f-e294130a64d2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443040034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias
ing.443040034
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.4185160618
Short name T73
Test name
Test status
Simulation time 288033529 ps
CPU time 2.77 seconds
Started Jan 17 01:02:24 PM PST 24
Finished Jan 17 01:02:27 PM PST 24
Peak memory 191680 kb
Host smart-7af1e1f2-6196-489d-ba37-139a0a1ac75a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185160618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.4185160618
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.4083084822
Short name T66
Test name
Test status
Simulation time 26234224 ps
CPU time 0.6 seconds
Started Jan 17 01:02:13 PM PST 24
Finished Jan 17 01:02:17 PM PST 24
Peak memory 183296 kb
Host smart-a0160e2a-a416-4987-9bbb-a304f9618b72
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083084822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.4083084822
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2769984885
Short name T394
Test name
Test status
Simulation time 85660027 ps
CPU time 1.33 seconds
Started Jan 17 01:02:09 PM PST 24
Finished Jan 17 01:02:12 PM PST 24
Peak memory 198096 kb
Host smart-163d616d-b6d8-44c0-9761-1c5b19500174
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769984885 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2769984885
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2163351764
Short name T69
Test name
Test status
Simulation time 15977638 ps
CPU time 0.57 seconds
Started Jan 17 01:02:09 PM PST 24
Finished Jan 17 01:02:11 PM PST 24
Peak memory 183196 kb
Host smart-f973ac39-ecf8-478c-85e7-da83489ee874
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163351764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2163351764
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1512611825
Short name T429
Test name
Test status
Simulation time 41875913 ps
CPU time 0.58 seconds
Started Jan 17 01:02:13 PM PST 24
Finished Jan 17 01:02:16 PM PST 24
Peak memory 182572 kb
Host smart-57311457-dc24-4dae-b0d6-856c3314978d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512611825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1512611825
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.938642143
Short name T468
Test name
Test status
Simulation time 617497950 ps
CPU time 0.89 seconds
Started Jan 17 01:02:10 PM PST 24
Finished Jan 17 01:02:12 PM PST 24
Peak memory 194912 kb
Host smart-884eed17-2131-4a5f-9868-a9c592b3d23e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938642143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_tim
er_same_csr_outstanding.938642143
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1135349110
Short name T375
Test name
Test status
Simulation time 130771479 ps
CPU time 2.34 seconds
Started Jan 17 01:02:24 PM PST 24
Finished Jan 17 01:02:27 PM PST 24
Peak memory 198036 kb
Host smart-b1499678-4436-495e-ad7e-a5025d29f228
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135349110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1135349110
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3426370143
Short name T27
Test name
Test status
Simulation time 62070894 ps
CPU time 0.83 seconds
Started Jan 17 01:02:08 PM PST 24
Finished Jan 17 01:02:11 PM PST 24
Peak memory 183468 kb
Host smart-973a188c-aa29-45e2-a476-9737be0d7790
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426370143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3426370143
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2528520268
Short name T372
Test name
Test status
Simulation time 148250546 ps
CPU time 0.57 seconds
Started Jan 17 01:02:49 PM PST 24
Finished Jan 17 01:02:50 PM PST 24
Peak memory 182944 kb
Host smart-e1efe76f-28d1-4868-a9c9-e4eb910a86fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528520268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2528520268
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3587272160
Short name T402
Test name
Test status
Simulation time 40534709 ps
CPU time 0.57 seconds
Started Jan 17 01:02:48 PM PST 24
Finished Jan 17 01:02:50 PM PST 24
Peak memory 182972 kb
Host smart-9da80893-56de-4bd8-9102-09bdb4d29d82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587272160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3587272160
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3334134445
Short name T446
Test name
Test status
Simulation time 85207943 ps
CPU time 0.56 seconds
Started Jan 17 01:02:54 PM PST 24
Finished Jan 17 01:02:55 PM PST 24
Peak memory 182944 kb
Host smart-6d62459e-187e-4758-908c-6501a4c95aeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334134445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.3334134445
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3308409035
Short name T78
Test name
Test status
Simulation time 18884418 ps
CPU time 0.6 seconds
Started Jan 17 01:02:44 PM PST 24
Finished Jan 17 01:02:48 PM PST 24
Peak memory 182984 kb
Host smart-736ff0ff-9c06-4832-8051-19dfd2b0a7c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308409035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3308409035
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2147286710
Short name T373
Test name
Test status
Simulation time 44521742 ps
CPU time 0.59 seconds
Started Jan 17 01:02:53 PM PST 24
Finished Jan 17 01:02:54 PM PST 24
Peak memory 182964 kb
Host smart-9948f540-9954-4ebc-ba20-d4cc3b4909ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147286710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2147286710
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3176646121
Short name T459
Test name
Test status
Simulation time 96995993 ps
CPU time 0.55 seconds
Started Jan 17 01:02:52 PM PST 24
Finished Jan 17 01:02:53 PM PST 24
Peak memory 182892 kb
Host smart-4ca75f55-06ef-4ffa-8305-e0d29e784f11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176646121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3176646121
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3607120822
Short name T81
Test name
Test status
Simulation time 50046352 ps
CPU time 0.53 seconds
Started Jan 17 01:02:52 PM PST 24
Finished Jan 17 01:02:53 PM PST 24
Peak memory 182860 kb
Host smart-806481b5-4fb7-4285-a73e-5c3722e3daf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607120822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3607120822
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.4232402155
Short name T456
Test name
Test status
Simulation time 22257761 ps
CPU time 0.63 seconds
Started Jan 17 01:02:49 PM PST 24
Finished Jan 17 01:02:51 PM PST 24
Peak memory 182940 kb
Host smart-83dc217a-e839-4730-850d-dca736116957
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232402155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.4232402155
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3883840203
Short name T424
Test name
Test status
Simulation time 20504986 ps
CPU time 0.56 seconds
Started Jan 17 01:02:52 PM PST 24
Finished Jan 17 01:02:54 PM PST 24
Peak memory 182836 kb
Host smart-06f80829-c1a2-4ad2-b2d3-06be1dc118c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883840203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3883840203
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.881951236
Short name T377
Test name
Test status
Simulation time 34408096 ps
CPU time 0.52 seconds
Started Jan 17 01:02:47 PM PST 24
Finished Jan 17 01:02:48 PM PST 24
Peak memory 182044 kb
Host smart-da34c453-3658-4570-b53e-5df8e3020313
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881951236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.881951236
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3403079081
Short name T40
Test name
Test status
Simulation time 42727856 ps
CPU time 0.74 seconds
Started Jan 17 01:02:24 PM PST 24
Finished Jan 17 01:02:26 PM PST 24
Peak memory 192472 kb
Host smart-d0931c5b-79b9-40d5-a5b0-0957e3861954
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403079081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3403079081
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1833446783
Short name T94
Test name
Test status
Simulation time 384353185 ps
CPU time 2.6 seconds
Started Jan 17 01:02:26 PM PST 24
Finished Jan 17 01:02:30 PM PST 24
Peak memory 194080 kb
Host smart-6663bf5b-9101-4f5b-ace2-ad2e3974540a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833446783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.1833446783
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1759616700
Short name T381
Test name
Test status
Simulation time 32807025 ps
CPU time 0.57 seconds
Started Jan 17 01:02:10 PM PST 24
Finished Jan 17 01:02:12 PM PST 24
Peak memory 183268 kb
Host smart-0b7e4e35-f991-468a-b11a-e826a0eda4b9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759616700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1759616700
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3095754908
Short name T412
Test name
Test status
Simulation time 58786531 ps
CPU time 0.92 seconds
Started Jan 17 01:02:20 PM PST 24
Finished Jan 17 01:02:21 PM PST 24
Peak memory 197300 kb
Host smart-e1592e6f-3af9-4994-8cdc-01ffa0341dc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095754908 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3095754908
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3450277270
Short name T427
Test name
Test status
Simulation time 49274008 ps
CPU time 0.64 seconds
Started Jan 17 01:02:20 PM PST 24
Finished Jan 17 01:02:21 PM PST 24
Peak memory 183272 kb
Host smart-ba268675-e2c4-459f-a6c1-ad9e09d701ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450277270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3450277270
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1577185122
Short name T411
Test name
Test status
Simulation time 59297528 ps
CPU time 0.56 seconds
Started Jan 17 01:02:18 PM PST 24
Finished Jan 17 01:02:20 PM PST 24
Peak memory 183144 kb
Host smart-ae6b1e79-63a3-42f4-bc4e-9e42c65307d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577185122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1577185122
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3463828194
Short name T75
Test name
Test status
Simulation time 67854221 ps
CPU time 0.72 seconds
Started Jan 17 01:02:25 PM PST 24
Finished Jan 17 01:02:27 PM PST 24
Peak memory 193544 kb
Host smart-bce784bd-4671-43fd-8f8e-e5c406da0e37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463828194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.3463828194
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3754262634
Short name T63
Test name
Test status
Simulation time 190292911 ps
CPU time 2.59 seconds
Started Jan 17 01:02:16 PM PST 24
Finished Jan 17 01:02:21 PM PST 24
Peak memory 198080 kb
Host smart-8a682839-a5b3-4272-a283-7619ca7e427b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754262634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3754262634
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.4240668348
Short name T41
Test name
Test status
Simulation time 306204062 ps
CPU time 0.81 seconds
Started Jan 17 01:02:19 PM PST 24
Finished Jan 17 01:02:20 PM PST 24
Peak memory 183400 kb
Host smart-9403dbb9-3fb1-4b9d-bca7-ad6a130b5e7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240668348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.4240668348
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3040287561
Short name T453
Test name
Test status
Simulation time 33984097 ps
CPU time 0.53 seconds
Started Jan 17 01:02:54 PM PST 24
Finished Jan 17 01:02:55 PM PST 24
Peak memory 182856 kb
Host smart-f80d3162-afaa-4353-a8d8-2cd9a3bc6a81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040287561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3040287561
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2178476335
Short name T407
Test name
Test status
Simulation time 91560419 ps
CPU time 0.61 seconds
Started Jan 17 01:02:51 PM PST 24
Finished Jan 17 01:02:52 PM PST 24
Peak memory 182960 kb
Host smart-78fa61d6-ae79-41c6-b07e-276659953a94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178476335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2178476335
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1166323849
Short name T464
Test name
Test status
Simulation time 38057702 ps
CPU time 0.53 seconds
Started Jan 17 01:02:51 PM PST 24
Finished Jan 17 01:02:52 PM PST 24
Peak memory 182916 kb
Host smart-159e356b-c4a3-4634-a770-e55d1d5165f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166323849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1166323849
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1577197016
Short name T431
Test name
Test status
Simulation time 49458274 ps
CPU time 0.61 seconds
Started Jan 17 01:02:46 PM PST 24
Finished Jan 17 01:02:48 PM PST 24
Peak memory 182892 kb
Host smart-03066160-3a92-4632-a49b-8b06fe2d9019
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577197016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1577197016
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.638934427
Short name T430
Test name
Test status
Simulation time 11903006 ps
CPU time 0.55 seconds
Started Jan 17 01:02:44 PM PST 24
Finished Jan 17 01:02:48 PM PST 24
Peak memory 182072 kb
Host smart-5e9b9a7e-1ca6-4702-884b-bcb8d88e0204
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638934427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.638934427
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1129513835
Short name T49
Test name
Test status
Simulation time 35287291 ps
CPU time 0.52 seconds
Started Jan 17 01:02:54 PM PST 24
Finished Jan 17 01:02:55 PM PST 24
Peak memory 182104 kb
Host smart-2b2479bf-a6e6-422a-a064-cd77003adbc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129513835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1129513835
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1555236962
Short name T369
Test name
Test status
Simulation time 14002847 ps
CPU time 0.53 seconds
Started Jan 17 01:02:47 PM PST 24
Finished Jan 17 01:02:49 PM PST 24
Peak memory 182124 kb
Host smart-be34c8e4-5170-460a-b131-5e0d37249124
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555236962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1555236962
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3028795790
Short name T450
Test name
Test status
Simulation time 13172309 ps
CPU time 0.54 seconds
Started Jan 17 01:02:46 PM PST 24
Finished Jan 17 01:02:48 PM PST 24
Peak memory 182456 kb
Host smart-621584df-e9c6-4aa7-a610-51186e1e3812
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028795790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3028795790
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.37122362
Short name T457
Test name
Test status
Simulation time 31192265 ps
CPU time 0.53 seconds
Started Jan 17 01:02:47 PM PST 24
Finished Jan 17 01:02:48 PM PST 24
Peak memory 182456 kb
Host smart-9944a36e-92ee-45fd-aa6e-d01efbba727d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37122362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.37122362
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1707501350
Short name T361
Test name
Test status
Simulation time 53517718 ps
CPU time 0.56 seconds
Started Jan 17 01:02:43 PM PST 24
Finished Jan 17 01:02:48 PM PST 24
Peak memory 182528 kb
Host smart-f99a4a66-fbb2-4bdf-a55c-f91266b74916
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707501350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1707501350
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1064600291
Short name T434
Test name
Test status
Simulation time 244169903 ps
CPU time 1.07 seconds
Started Jan 17 01:02:22 PM PST 24
Finished Jan 17 01:02:24 PM PST 24
Peak memory 198072 kb
Host smart-70443d78-449d-4fbe-b9c7-82e4fd7e7e56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064600291 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1064600291
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.331629061
Short name T70
Test name
Test status
Simulation time 34906336 ps
CPU time 0.53 seconds
Started Jan 17 01:02:24 PM PST 24
Finished Jan 17 01:02:25 PM PST 24
Peak memory 182624 kb
Host smart-b9438630-0c23-4bad-91d9-ec0e721e2425
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331629061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.331629061
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1552218972
Short name T432
Test name
Test status
Simulation time 51707624 ps
CPU time 0.55 seconds
Started Jan 17 01:02:18 PM PST 24
Finished Jan 17 01:02:20 PM PST 24
Peak memory 182888 kb
Host smart-4f2faea1-94bc-453b-b015-a359543d4540
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552218972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1552218972
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1433693560
Short name T465
Test name
Test status
Simulation time 26034383 ps
CPU time 0.7 seconds
Started Jan 17 01:02:18 PM PST 24
Finished Jan 17 01:02:20 PM PST 24
Peak memory 193588 kb
Host smart-85215b25-d9e1-431f-987b-d94243e14f8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433693560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1433693560
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1759918636
Short name T385
Test name
Test status
Simulation time 136539261 ps
CPU time 1.3 seconds
Started Jan 17 01:02:22 PM PST 24
Finished Jan 17 01:02:24 PM PST 24
Peak memory 198092 kb
Host smart-f2bae1b3-e825-40e6-82b2-7835e3e7a9de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759918636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1759918636
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.80154716
Short name T445
Test name
Test status
Simulation time 160796722 ps
CPU time 0.85 seconds
Started Jan 17 01:02:19 PM PST 24
Finished Jan 17 01:02:20 PM PST 24
Peak memory 194140 kb
Host smart-7469e3da-31f6-448e-a17c-dd83db674adf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80154716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_intg
_err.80154716
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1038425711
Short name T379
Test name
Test status
Simulation time 44068561 ps
CPU time 0.78 seconds
Started Jan 17 01:02:25 PM PST 24
Finished Jan 17 01:02:27 PM PST 24
Peak memory 195576 kb
Host smart-3f48bb90-f835-46b7-8614-9268f46368b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038425711 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1038425711
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.4195297367
Short name T380
Test name
Test status
Simulation time 13263045 ps
CPU time 0.56 seconds
Started Jan 17 01:02:27 PM PST 24
Finished Jan 17 01:02:29 PM PST 24
Peak memory 182812 kb
Host smart-4b80ecb0-c83f-4b62-970a-5509778152f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195297367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.4195297367
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1977131896
Short name T419
Test name
Test status
Simulation time 17180192 ps
CPU time 0.55 seconds
Started Jan 17 01:02:27 PM PST 24
Finished Jan 17 01:02:29 PM PST 24
Peak memory 182116 kb
Host smart-8abbf243-8b19-44a3-b591-c556505d6239
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977131896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1977131896
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1621533952
Short name T461
Test name
Test status
Simulation time 14793183 ps
CPU time 0.71 seconds
Started Jan 17 01:02:20 PM PST 24
Finished Jan 17 01:02:21 PM PST 24
Peak memory 192776 kb
Host smart-88a5cf83-08f3-4cfc-9f25-17f258375342
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621533952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1621533952
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2472419504
Short name T447
Test name
Test status
Simulation time 241428918 ps
CPU time 2.68 seconds
Started Jan 17 01:02:19 PM PST 24
Finished Jan 17 01:02:23 PM PST 24
Peak memory 197948 kb
Host smart-8739d95a-d316-4615-9cb8-8b3ca8123ae4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472419504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2472419504
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2926677263
Short name T395
Test name
Test status
Simulation time 160631408 ps
CPU time 1.12 seconds
Started Jan 17 01:02:25 PM PST 24
Finished Jan 17 01:02:27 PM PST 24
Peak memory 195584 kb
Host smart-fef747a3-513b-4da5-a3e0-62ae579565fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926677263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2926677263
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.645070478
Short name T449
Test name
Test status
Simulation time 117247193 ps
CPU time 0.88 seconds
Started Jan 17 01:02:19 PM PST 24
Finished Jan 17 01:02:20 PM PST 24
Peak memory 197840 kb
Host smart-186d038b-c280-4c0e-85af-8c22cc256bf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645070478 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.645070478
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1439546931
Short name T67
Test name
Test status
Simulation time 59834349 ps
CPU time 0.58 seconds
Started Jan 17 01:02:20 PM PST 24
Finished Jan 17 01:02:21 PM PST 24
Peak memory 183304 kb
Host smart-f226afc3-743e-4784-ad85-7523ee9a78c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439546931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1439546931
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.899983091
Short name T360
Test name
Test status
Simulation time 12755803 ps
CPU time 0.55 seconds
Started Jan 17 01:02:26 PM PST 24
Finished Jan 17 01:02:28 PM PST 24
Peak memory 182452 kb
Host smart-cb42244a-2859-48eb-afac-6f580d69321a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899983091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.899983091
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1864315185
Short name T50
Test name
Test status
Simulation time 121002159 ps
CPU time 0.82 seconds
Started Jan 17 01:02:17 PM PST 24
Finished Jan 17 01:02:20 PM PST 24
Peak memory 193776 kb
Host smart-9ebda853-e92e-4164-8483-b4381ef815c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864315185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1864315185
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.513257602
Short name T42
Test name
Test status
Simulation time 286311430 ps
CPU time 1.6 seconds
Started Jan 17 01:02:18 PM PST 24
Finished Jan 17 01:02:21 PM PST 24
Peak memory 198176 kb
Host smart-c5b385e2-1e6b-4690-88ce-1ea59270db10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513257602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.513257602
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2968298323
Short name T467
Test name
Test status
Simulation time 405784194 ps
CPU time 1.34 seconds
Started Jan 17 01:02:24 PM PST 24
Finished Jan 17 01:02:26 PM PST 24
Peak memory 195640 kb
Host smart-dfc00b15-a1a5-4ea7-b29c-fb9558d8d452
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968298323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.2968298323
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2628839015
Short name T370
Test name
Test status
Simulation time 117177918 ps
CPU time 0.95 seconds
Started Jan 17 01:02:26 PM PST 24
Finished Jan 17 01:02:28 PM PST 24
Peak memory 191604 kb
Host smart-77071a60-f36e-4aaa-b28b-8587eeb32a20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628839015 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2628839015
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1705899280
Short name T71
Test name
Test status
Simulation time 40821662 ps
CPU time 0.58 seconds
Started Jan 17 01:02:20 PM PST 24
Finished Jan 17 01:02:22 PM PST 24
Peak memory 192544 kb
Host smart-3f43ffbf-3fea-4b22-ae71-5ba61c80e524
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705899280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1705899280
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2461849427
Short name T421
Test name
Test status
Simulation time 50299890 ps
CPU time 0.54 seconds
Started Jan 17 01:02:27 PM PST 24
Finished Jan 17 01:02:29 PM PST 24
Peak memory 182128 kb
Host smart-571fd1c3-88de-4dbb-b146-945255623f6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461849427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2461849427
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1745611
Short name T58
Test name
Test status
Simulation time 17677970 ps
CPU time 0.6 seconds
Started Jan 17 01:02:23 PM PST 24
Finished Jan 17 01:02:25 PM PST 24
Peak memory 191696 kb
Host smart-7e754f40-7f16-4950-98f0-fe5210b77d48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_t
imer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer
_same_csr_outstanding.1745611
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3125438384
Short name T469
Test name
Test status
Simulation time 28275572 ps
CPU time 1.4 seconds
Started Jan 17 01:02:23 PM PST 24
Finished Jan 17 01:02:25 PM PST 24
Peak memory 198008 kb
Host smart-2fd0dbea-24b1-45b9-a8c2-b2cb7061d19e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125438384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3125438384
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2873687107
Short name T425
Test name
Test status
Simulation time 96850003 ps
CPU time 0.81 seconds
Started Jan 17 01:02:19 PM PST 24
Finished Jan 17 01:02:21 PM PST 24
Peak memory 183576 kb
Host smart-6e7006c8-70b7-4ce5-a069-2df9486b8dd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873687107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2873687107
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2291496097
Short name T422
Test name
Test status
Simulation time 29635426 ps
CPU time 0.8 seconds
Started Jan 17 01:02:23 PM PST 24
Finished Jan 17 01:02:24 PM PST 24
Peak memory 197680 kb
Host smart-ba7007e5-792f-4b4f-a79d-2515dc1d17ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291496097 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2291496097
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1654159302
Short name T65
Test name
Test status
Simulation time 23505167 ps
CPU time 0.56 seconds
Started Jan 17 01:02:27 PM PST 24
Finished Jan 17 01:02:28 PM PST 24
Peak memory 183252 kb
Host smart-fdb0548d-4332-4b6c-b2cf-a8063d25e18d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654159302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1654159302
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1645561922
Short name T463
Test name
Test status
Simulation time 15022640 ps
CPU time 0.56 seconds
Started Jan 17 01:02:20 PM PST 24
Finished Jan 17 01:02:22 PM PST 24
Peak memory 182888 kb
Host smart-472d7191-599e-4431-908c-e6b4518eebbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645561922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1645561922
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3813276378
Short name T437
Test name
Test status
Simulation time 18737711 ps
CPU time 0.72 seconds
Started Jan 17 01:02:27 PM PST 24
Finished Jan 17 01:02:28 PM PST 24
Peak memory 191736 kb
Host smart-99987508-af5f-4e9e-87de-d54e0bda9406
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813276378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.3813276378
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3117569857
Short name T399
Test name
Test status
Simulation time 80860883 ps
CPU time 1.86 seconds
Started Jan 17 01:02:22 PM PST 24
Finished Jan 17 01:02:25 PM PST 24
Peak memory 198024 kb
Host smart-c4247902-8553-451c-9dfa-29f7e00d41d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117569857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3117569857
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2672256315
Short name T404
Test name
Test status
Simulation time 587030405 ps
CPU time 1.36 seconds
Started Jan 17 01:02:22 PM PST 24
Finished Jan 17 01:02:24 PM PST 24
Peak memory 195708 kb
Host smart-2f527960-700b-43a3-843f-6d62648a89f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672256315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.2672256315
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3073370088
Short name T233
Test name
Test status
Simulation time 65466385408 ps
CPU time 18.16 seconds
Started Jan 17 03:07:29 PM PST 24
Finished Jan 17 03:07:47 PM PST 24
Peak memory 182936 kb
Host smart-f6203269-b12a-4984-8a68-1943449efdac
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073370088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.3073370088
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.596198335
Short name T548
Test name
Test status
Simulation time 223035708064 ps
CPU time 184.64 seconds
Started Jan 17 03:07:27 PM PST 24
Finished Jan 17 03:10:32 PM PST 24
Peak memory 182848 kb
Host smart-e1b02b51-a2d5-4062-8e92-3f07ba152261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596198335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.596198335
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.232328650
Short name T202
Test name
Test status
Simulation time 10399659502 ps
CPU time 88.7 seconds
Started Jan 17 03:07:27 PM PST 24
Finished Jan 17 03:08:56 PM PST 24
Peak memory 191176 kb
Host smart-47ce3048-8c6b-4ef1-a110-5ab7f9deafa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232328650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.232328650
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.794030518
Short name T504
Test name
Test status
Simulation time 214237573940 ps
CPU time 98.02 seconds
Started Jan 17 03:07:29 PM PST 24
Finished Jan 17 03:09:07 PM PST 24
Peak memory 182984 kb
Host smart-bf3b35b3-5ed5-4be5-a9b9-6efceb4ae91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794030518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.794030518
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.604507330
Short name T513
Test name
Test status
Simulation time 31681135303 ps
CPU time 128.1 seconds
Started Jan 17 03:07:29 PM PST 24
Finished Jan 17 03:09:38 PM PST 24
Peak memory 197700 kb
Host smart-f9759ad5-7172-47e9-845d-19656b1a36db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604507330 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.604507330
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3468605567
Short name T583
Test name
Test status
Simulation time 394079238252 ps
CPU time 159.67 seconds
Started Jan 17 03:07:29 PM PST 24
Finished Jan 17 03:10:09 PM PST 24
Peak memory 182916 kb
Host smart-acffcd64-2a6d-408f-973e-e4dd065f117c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468605567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3468605567
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.3430393809
Short name T602
Test name
Test status
Simulation time 131239316152 ps
CPU time 224.56 seconds
Started Jan 17 03:07:27 PM PST 24
Finished Jan 17 03:11:12 PM PST 24
Peak memory 191164 kb
Host smart-9e6d102d-30eb-44b0-8fad-156cc470b19c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430393809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3430393809
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.1290951819
Short name T480
Test name
Test status
Simulation time 509732177 ps
CPU time 1.2 seconds
Started Jan 17 03:07:29 PM PST 24
Finished Jan 17 03:07:30 PM PST 24
Peak memory 182716 kb
Host smart-e31aaa1f-c6dc-4887-b5bb-a1b2f16d90f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290951819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1290951819
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.3941872012
Short name T12
Test name
Test status
Simulation time 32916985 ps
CPU time 0.77 seconds
Started Jan 17 03:07:24 PM PST 24
Finished Jan 17 03:07:26 PM PST 24
Peak memory 212840 kb
Host smart-f62f59e3-9d69-401d-8d12-52e821c8e0e8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941872012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3941872012
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.559324495
Short name T20
Test name
Test status
Simulation time 999808373473 ps
CPU time 1235.26 seconds
Started Jan 17 03:07:30 PM PST 24
Finished Jan 17 03:28:06 PM PST 24
Peak memory 191116 kb
Host smart-d83ae659-94a6-4376-bc1e-018a4b8491d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559324495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.559324495
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.1338627447
Short name T561
Test name
Test status
Simulation time 343857608364 ps
CPU time 624.77 seconds
Started Jan 17 03:07:25 PM PST 24
Finished Jan 17 03:17:51 PM PST 24
Peak memory 205932 kb
Host smart-1015fbaa-5ea7-4eec-8773-dd16356a31b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338627447 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.1338627447
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.1883742202
Short name T527
Test name
Test status
Simulation time 997386173896 ps
CPU time 115.93 seconds
Started Jan 17 03:07:48 PM PST 24
Finished Jan 17 03:09:44 PM PST 24
Peak memory 182860 kb
Host smart-c6a60e3b-608b-4c67-897a-e64e9c83a1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883742202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1883742202
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2895758078
Short name T576
Test name
Test status
Simulation time 23388508207 ps
CPU time 34.02 seconds
Started Jan 17 03:07:56 PM PST 24
Finished Jan 17 03:08:36 PM PST 24
Peak memory 182956 kb
Host smart-ea97f7c2-9025-439c-9ddf-cdda762c86c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895758078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2895758078
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.3800129784
Short name T476
Test name
Test status
Simulation time 65268368354 ps
CPU time 733.91 seconds
Started Jan 17 03:07:56 PM PST 24
Finished Jan 17 03:20:15 PM PST 24
Peak memory 209176 kb
Host smart-57b0b476-1078-42c5-be2e-858bdaa0d76f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800129784 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.3800129784
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.2987030226
Short name T308
Test name
Test status
Simulation time 125965349839 ps
CPU time 509.24 seconds
Started Jan 17 03:12:29 PM PST 24
Finished Jan 17 03:20:59 PM PST 24
Peak memory 182968 kb
Host smart-b99c70dd-572e-4208-85da-76fcf8c70ec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987030226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2987030226
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.2982006020
Short name T174
Test name
Test status
Simulation time 2146266437420 ps
CPU time 461.25 seconds
Started Jan 17 03:12:30 PM PST 24
Finished Jan 17 03:20:12 PM PST 24
Peak memory 191076 kb
Host smart-73126f07-b42e-4768-9989-3690f53c76be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982006020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2982006020
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.3241810064
Short name T132
Test name
Test status
Simulation time 581359747222 ps
CPU time 1639.53 seconds
Started Jan 17 03:12:28 PM PST 24
Finished Jan 17 03:39:49 PM PST 24
Peak memory 191156 kb
Host smart-96bb4d26-8774-4d6a-9746-f413283aeb1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241810064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3241810064
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.3525543703
Short name T253
Test name
Test status
Simulation time 208946697499 ps
CPU time 77.8 seconds
Started Jan 17 03:12:29 PM PST 24
Finished Jan 17 03:13:47 PM PST 24
Peak memory 183056 kb
Host smart-884df980-7e32-4892-88a4-99cfb3196dae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525543703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3525543703
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1512772506
Short name T219
Test name
Test status
Simulation time 744453423128 ps
CPU time 518.08 seconds
Started Jan 17 03:12:33 PM PST 24
Finished Jan 17 03:21:11 PM PST 24
Peak memory 191172 kb
Host smart-f1be85d8-2844-4a2a-8395-0cf975fa0380
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512772506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1512772506
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.2376601476
Short name T330
Test name
Test status
Simulation time 156046352863 ps
CPU time 70.37 seconds
Started Jan 17 03:12:44 PM PST 24
Finished Jan 17 03:13:56 PM PST 24
Peak memory 183024 kb
Host smart-620285f8-e8f3-469e-a464-e620efbda724
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376601476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2376601476
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2757681904
Short name T558
Test name
Test status
Simulation time 676874216672 ps
CPU time 284.71 seconds
Started Jan 17 03:07:59 PM PST 24
Finished Jan 17 03:12:47 PM PST 24
Peak memory 182960 kb
Host smart-b4a7b24a-0d0e-441e-a12d-41331d9881c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757681904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2757681904
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1511673556
Short name T619
Test name
Test status
Simulation time 175631276 ps
CPU time 1.09 seconds
Started Jan 17 03:07:55 PM PST 24
Finished Jan 17 03:07:57 PM PST 24
Peak memory 191120 kb
Host smart-f4c821c8-9c3a-42be-8435-a8c362fe2274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511673556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1511673556
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.1364244412
Short name T492
Test name
Test status
Simulation time 81996026355 ps
CPU time 344.41 seconds
Started Jan 17 03:07:54 PM PST 24
Finished Jan 17 03:13:40 PM PST 24
Peak memory 205836 kb
Host smart-23c1608b-823b-468e-8394-78a0c182bf6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364244412 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.1364244412
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.rv_timer_random.1676699396
Short name T535
Test name
Test status
Simulation time 18453339537 ps
CPU time 51.73 seconds
Started Jan 17 03:12:40 PM PST 24
Finished Jan 17 03:13:32 PM PST 24
Peak memory 182988 kb
Host smart-9fb5b555-5a0f-486f-bb93-107a9e618e96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676699396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1676699396
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2192807207
Short name T2
Test name
Test status
Simulation time 26723714590 ps
CPU time 41.91 seconds
Started Jan 17 03:12:39 PM PST 24
Finished Jan 17 03:13:21 PM PST 24
Peak memory 182952 kb
Host smart-8561d6a0-5507-4527-a59b-d26a58122a5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192807207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2192807207
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.1096741535
Short name T610
Test name
Test status
Simulation time 60483450237 ps
CPU time 333.74 seconds
Started Jan 17 03:12:45 PM PST 24
Finished Jan 17 03:18:19 PM PST 24
Peak memory 191188 kb
Host smart-17ee2dae-d63e-40c9-a021-3a5b82ff969c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096741535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1096741535
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.1422823829
Short name T575
Test name
Test status
Simulation time 4258053729 ps
CPU time 7.01 seconds
Started Jan 17 03:12:45 PM PST 24
Finished Jan 17 03:12:53 PM PST 24
Peak memory 182760 kb
Host smart-af07ae79-aecc-462d-8dc4-cb6071ad03e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422823829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1422823829
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2880622227
Short name T178
Test name
Test status
Simulation time 302176475217 ps
CPU time 303.19 seconds
Started Jan 17 03:12:43 PM PST 24
Finished Jan 17 03:17:47 PM PST 24
Peak memory 191152 kb
Host smart-d0d191aa-ba5a-44b6-b3bc-0485b4e2ca3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880622227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2880622227
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.1465378769
Short name T131
Test name
Test status
Simulation time 2272454040675 ps
CPU time 1078.39 seconds
Started Jan 17 03:12:45 PM PST 24
Finished Jan 17 03:30:45 PM PST 24
Peak memory 191432 kb
Host smart-9fb21ba3-7180-4b95-874e-edf34f1bb609
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465378769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1465378769
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1088839222
Short name T312
Test name
Test status
Simulation time 172415586103 ps
CPU time 287.58 seconds
Started Jan 17 03:07:55 PM PST 24
Finished Jan 17 03:12:43 PM PST 24
Peak memory 182952 kb
Host smart-25c3ee10-3992-4ba1-b432-e114c017b676
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088839222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1088839222
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.4035365871
Short name T556
Test name
Test status
Simulation time 908856367959 ps
CPU time 283.94 seconds
Started Jan 17 03:07:54 PM PST 24
Finished Jan 17 03:12:39 PM PST 24
Peak memory 183148 kb
Host smart-980e8264-c7a8-4c07-9655-883c27375862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035365871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.4035365871
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.3841129614
Short name T148
Test name
Test status
Simulation time 415990946284 ps
CPU time 494.46 seconds
Started Jan 17 03:07:56 PM PST 24
Finished Jan 17 03:16:17 PM PST 24
Peak memory 191140 kb
Host smart-9cb84de8-f685-47a3-af74-b266a3420860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841129614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3841129614
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.965066280
Short name T295
Test name
Test status
Simulation time 185415843708 ps
CPU time 195.53 seconds
Started Jan 17 03:07:59 PM PST 24
Finished Jan 17 03:11:18 PM PST 24
Peak memory 191176 kb
Host smart-1e79c1bc-cbe7-4de0-b614-204d648eea0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965066280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.965066280
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.2810685580
Short name T35
Test name
Test status
Simulation time 94651449883 ps
CPU time 809.56 seconds
Started Jan 17 03:07:57 PM PST 24
Finished Jan 17 03:21:32 PM PST 24
Peak memory 208240 kb
Host smart-8582533a-526e-4b59-8e29-4fa15804eb2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810685580 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.2810685580
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.2795298456
Short name T146
Test name
Test status
Simulation time 10443274233 ps
CPU time 28.91 seconds
Started Jan 17 03:12:56 PM PST 24
Finished Jan 17 03:13:25 PM PST 24
Peak memory 193916 kb
Host smart-6aa0a415-bd91-4725-948a-2d782cbc6fa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795298456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2795298456
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.2108146032
Short name T266
Test name
Test status
Simulation time 22733749966 ps
CPU time 26.34 seconds
Started Jan 17 03:13:04 PM PST 24
Finished Jan 17 03:13:31 PM PST 24
Peak memory 183000 kb
Host smart-75a1be02-d3f1-4e27-ba75-26bbe9cfc4f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108146032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2108146032
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.2083013980
Short name T571
Test name
Test status
Simulation time 780828612711 ps
CPU time 212.37 seconds
Started Jan 17 03:13:03 PM PST 24
Finished Jan 17 03:16:36 PM PST 24
Peak memory 191204 kb
Host smart-6f829d24-1ea5-4bab-9666-389d3052407d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083013980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.2083013980
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.829361940
Short name T182
Test name
Test status
Simulation time 66864956739 ps
CPU time 73.44 seconds
Started Jan 17 03:13:05 PM PST 24
Finished Jan 17 03:14:19 PM PST 24
Peak memory 193732 kb
Host smart-761ed034-1a1a-4d30-b26f-3c89c9c55818
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829361940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.829361940
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.2945978288
Short name T181
Test name
Test status
Simulation time 212630876698 ps
CPU time 820.08 seconds
Started Jan 17 03:13:14 PM PST 24
Finished Jan 17 03:27:02 PM PST 24
Peak memory 191160 kb
Host smart-7162ae30-9dc3-4966-9f8d-ccc0c3dcdbfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945978288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2945978288
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.3782778083
Short name T287
Test name
Test status
Simulation time 4129373030109 ps
CPU time 1350.45 seconds
Started Jan 17 03:13:15 PM PST 24
Finished Jan 17 03:35:53 PM PST 24
Peak memory 191188 kb
Host smart-fcfbccea-5b1f-4a62-93c1-0a89da1bcec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782778083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3782778083
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2535411265
Short name T8
Test name
Test status
Simulation time 710372513004 ps
CPU time 1140.73 seconds
Started Jan 17 03:07:53 PM PST 24
Finished Jan 17 03:26:55 PM PST 24
Peak memory 182976 kb
Host smart-e2d5d9a4-d17c-47cf-89ed-4e1ea36cddb7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535411265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2535411265
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.3928284465
Short name T496
Test name
Test status
Simulation time 12804727213 ps
CPU time 18.48 seconds
Started Jan 17 03:07:54 PM PST 24
Finished Jan 17 03:08:14 PM PST 24
Peak memory 183000 kb
Host smart-503eeff1-de62-4558-8698-870f7b5c8052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928284465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3928284465
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.261814674
Short name T271
Test name
Test status
Simulation time 29650302603 ps
CPU time 44.28 seconds
Started Jan 17 03:07:57 PM PST 24
Finished Jan 17 03:08:46 PM PST 24
Peak memory 182700 kb
Host smart-8c52cc8c-479c-409f-a5fc-42e38f7f37d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261814674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.261814674
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.1874759556
Short name T516
Test name
Test status
Simulation time 48051718 ps
CPU time 0.61 seconds
Started Jan 17 03:07:54 PM PST 24
Finished Jan 17 03:07:56 PM PST 24
Peak memory 182632 kb
Host smart-e0086866-bd10-44ba-a0b6-39d345d6f87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874759556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1874759556
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.1301499008
Short name T347
Test name
Test status
Simulation time 2549117951126 ps
CPU time 638.6 seconds
Started Jan 17 03:07:52 PM PST 24
Finished Jan 17 03:18:33 PM PST 24
Peak memory 191060 kb
Host smart-dcba5952-7342-4214-a02b-7f1acca5065d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301499008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.1301499008
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.1860622709
Short name T554
Test name
Test status
Simulation time 362598069540 ps
CPU time 409.39 seconds
Started Jan 17 03:07:54 PM PST 24
Finished Jan 17 03:14:45 PM PST 24
Peak memory 205884 kb
Host smart-b3ab82ea-6eec-4b23-9792-71b1d9869d22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860622709 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.1860622709
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.513118254
Short name T254
Test name
Test status
Simulation time 104484520975 ps
CPU time 157.43 seconds
Started Jan 17 03:13:13 PM PST 24
Finished Jan 17 03:16:00 PM PST 24
Peak memory 191156 kb
Host smart-10baa5de-6171-4bb1-a2bd-8bdecda19624
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513118254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.513118254
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.140203463
Short name T337
Test name
Test status
Simulation time 300442960143 ps
CPU time 106.49 seconds
Started Jan 17 03:13:15 PM PST 24
Finished Jan 17 03:15:09 PM PST 24
Peak memory 182992 kb
Host smart-f60729cd-ce90-4b87-abd5-e26c758a048c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140203463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.140203463
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.2721653947
Short name T265
Test name
Test status
Simulation time 222205351613 ps
CPU time 1002.8 seconds
Started Jan 17 03:13:13 PM PST 24
Finished Jan 17 03:30:05 PM PST 24
Peak memory 191220 kb
Host smart-24f416b4-ef52-40ae-9c99-af2e3e42d789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721653947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2721653947
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3590507400
Short name T270
Test name
Test status
Simulation time 207972091000 ps
CPU time 274.45 seconds
Started Jan 17 03:13:31 PM PST 24
Finished Jan 17 03:18:07 PM PST 24
Peak memory 193896 kb
Host smart-6f1f369a-5083-4210-b724-d7123b8ddc60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590507400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3590507400
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1807020342
Short name T207
Test name
Test status
Simulation time 5227671621 ps
CPU time 10.03 seconds
Started Jan 17 03:13:31 PM PST 24
Finished Jan 17 03:13:43 PM PST 24
Peak memory 191108 kb
Host smart-58f6d275-527d-4290-b404-f18a324ba50d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807020342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1807020342
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.2294905679
Short name T557
Test name
Test status
Simulation time 50517494843 ps
CPU time 25.61 seconds
Started Jan 17 03:13:28 PM PST 24
Finished Jan 17 03:13:58 PM PST 24
Peak memory 182972 kb
Host smart-84da973e-e9a2-42f4-aacf-d7bc25a3797b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294905679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2294905679
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1611036514
Short name T574
Test name
Test status
Simulation time 343617809064 ps
CPU time 81.73 seconds
Started Jan 17 03:13:28 PM PST 24
Finished Jan 17 03:14:55 PM PST 24
Peak memory 183036 kb
Host smart-4e96a372-bf9a-437e-8cc3-24d1fa55da2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611036514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1611036514
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.445188877
Short name T22
Test name
Test status
Simulation time 360688193213 ps
CPU time 227.65 seconds
Started Jan 17 03:13:34 PM PST 24
Finished Jan 17 03:17:25 PM PST 24
Peak memory 193248 kb
Host smart-c5f397d9-f572-4e33-bdce-44d88426b633
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445188877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.445188877
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.985391792
Short name T192
Test name
Test status
Simulation time 1245617888085 ps
CPU time 652.44 seconds
Started Jan 17 03:07:53 PM PST 24
Finished Jan 17 03:18:48 PM PST 24
Peak memory 182892 kb
Host smart-fd165957-8340-4768-aeea-92e2211c674e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985391792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.985391792
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2766290000
Short name T591
Test name
Test status
Simulation time 106212615516 ps
CPU time 167.29 seconds
Started Jan 17 03:07:59 PM PST 24
Finished Jan 17 03:10:49 PM PST 24
Peak memory 182936 kb
Host smart-5f066f2c-31e0-4966-8ffb-9710af158d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766290000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2766290000
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.142026544
Short name T110
Test name
Test status
Simulation time 97312472806 ps
CPU time 330.98 seconds
Started Jan 17 03:07:55 PM PST 24
Finished Jan 17 03:13:27 PM PST 24
Peak memory 191104 kb
Host smart-7c7a73e9-9e3b-49d6-9624-4cbb8e940f69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142026544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.142026544
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.583329480
Short name T272
Test name
Test status
Simulation time 181378418250 ps
CPU time 1409.2 seconds
Started Jan 17 03:08:00 PM PST 24
Finished Jan 17 03:31:31 PM PST 24
Peak memory 182976 kb
Host smart-43ee7ae7-002e-40fd-aa35-aa250dce2eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583329480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.583329480
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.3490558568
Short name T210
Test name
Test status
Simulation time 484503407994 ps
CPU time 407.42 seconds
Started Jan 17 03:08:00 PM PST 24
Finished Jan 17 03:14:50 PM PST 24
Peak memory 194776 kb
Host smart-f70176ee-3f59-4b9f-b406-6ef1cd479f5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490558568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.3490558568
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.1524783568
Short name T10
Test name
Test status
Simulation time 456324279610 ps
CPU time 342.96 seconds
Started Jan 17 03:08:05 PM PST 24
Finished Jan 17 03:13:48 PM PST 24
Peak memory 208260 kb
Host smart-cd64507d-03b5-4523-9ba9-933ca38ab4d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524783568 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.1524783568
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.1185410703
Short name T317
Test name
Test status
Simulation time 67314241008 ps
CPU time 103.35 seconds
Started Jan 17 03:13:32 PM PST 24
Finished Jan 17 03:15:16 PM PST 24
Peak memory 193216 kb
Host smart-88240969-aff5-455f-80d3-bbcf4695c880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185410703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1185410703
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.2538900519
Short name T346
Test name
Test status
Simulation time 48784109295 ps
CPU time 411.63 seconds
Started Jan 17 03:13:31 PM PST 24
Finished Jan 17 03:20:25 PM PST 24
Peak memory 182920 kb
Host smart-ae6a16db-c862-483a-aa69-0ed31e6351da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538900519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2538900519
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.545968705
Short name T555
Test name
Test status
Simulation time 74250593522 ps
CPU time 34.03 seconds
Started Jan 17 03:13:32 PM PST 24
Finished Jan 17 03:14:07 PM PST 24
Peak memory 183112 kb
Host smart-4c711bdb-649f-4946-96e2-d790a749d63a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545968705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.545968705
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3340015911
Short name T209
Test name
Test status
Simulation time 21435541721 ps
CPU time 47.43 seconds
Started Jan 17 03:13:30 PM PST 24
Finished Jan 17 03:14:20 PM PST 24
Peak memory 191176 kb
Host smart-3e662b6f-1b63-4674-b5c2-72c907d05153
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340015911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3340015911
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.2176777843
Short name T155
Test name
Test status
Simulation time 139186800611 ps
CPU time 284.9 seconds
Started Jan 17 03:13:39 PM PST 24
Finished Jan 17 03:18:24 PM PST 24
Peak memory 191120 kb
Host smart-cd08e538-606e-4704-aac1-68750e33792c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176777843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2176777843
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.3834891212
Short name T203
Test name
Test status
Simulation time 111910523133 ps
CPU time 92 seconds
Started Jan 17 03:13:40 PM PST 24
Finished Jan 17 03:15:12 PM PST 24
Peak memory 191216 kb
Host smart-154b2604-3f29-4e3e-904a-345c93635c41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834891212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3834891212
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1601422912
Short name T320
Test name
Test status
Simulation time 21729121295 ps
CPU time 18.42 seconds
Started Jan 17 03:13:40 PM PST 24
Finished Jan 17 03:13:59 PM PST 24
Peak memory 182980 kb
Host smart-4479a8e9-1c9f-49a2-8eb4-70bef123ef5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601422912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1601422912
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2174664740
Short name T314
Test name
Test status
Simulation time 45944609298 ps
CPU time 41.39 seconds
Started Jan 17 03:08:02 PM PST 24
Finished Jan 17 03:08:44 PM PST 24
Peak memory 182956 kb
Host smart-b6940667-ed49-4a4d-89b8-b3ada0b89826
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174664740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2174664740
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.605891023
Short name T584
Test name
Test status
Simulation time 114956072034 ps
CPU time 50.77 seconds
Started Jan 17 03:08:05 PM PST 24
Finished Jan 17 03:08:56 PM PST 24
Peak memory 182948 kb
Host smart-6896be26-3c06-433b-94f7-d6b5ecb76dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605891023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.605891023
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.2859857507
Short name T573
Test name
Test status
Simulation time 71326071593 ps
CPU time 156.09 seconds
Started Jan 17 03:07:59 PM PST 24
Finished Jan 17 03:10:38 PM PST 24
Peak memory 183000 kb
Host smart-331e85d2-6abb-490e-a94f-d3427ee70d6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859857507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2859857507
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3959532229
Short name T512
Test name
Test status
Simulation time 244160440 ps
CPU time 0.94 seconds
Started Jan 17 03:07:58 PM PST 24
Finished Jan 17 03:08:03 PM PST 24
Peak memory 182708 kb
Host smart-c6aa17c1-07d4-44c5-816f-41fb4fc8c080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959532229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3959532229
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.2945243162
Short name T615
Test name
Test status
Simulation time 56515116699 ps
CPU time 148.89 seconds
Started Jan 17 03:08:01 PM PST 24
Finished Jan 17 03:10:31 PM PST 24
Peak memory 205888 kb
Host smart-231feee9-e8b6-42aa-9c25-b8412022b70c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945243162 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.2945243162
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.3369227915
Short name T111
Test name
Test status
Simulation time 588863078928 ps
CPU time 353.8 seconds
Started Jan 17 03:13:40 PM PST 24
Finished Jan 17 03:19:35 PM PST 24
Peak memory 191172 kb
Host smart-c8897aac-54ad-4ee2-b6e7-9144feeca6c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369227915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3369227915
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.1980825061
Short name T189
Test name
Test status
Simulation time 620484552843 ps
CPU time 1315.64 seconds
Started Jan 17 03:13:40 PM PST 24
Finished Jan 17 03:35:36 PM PST 24
Peak memory 191168 kb
Host smart-cf28bd25-bc71-4a4b-a476-06956b1ba190
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980825061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1980825061
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.12924347
Short name T9
Test name
Test status
Simulation time 302406214919 ps
CPU time 159.68 seconds
Started Jan 17 03:13:47 PM PST 24
Finished Jan 17 03:16:27 PM PST 24
Peak memory 191188 kb
Host smart-faff09a2-fa8a-4b72-ae57-b99b42ce86e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12924347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.12924347
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3828083427
Short name T334
Test name
Test status
Simulation time 324813049978 ps
CPU time 137.16 seconds
Started Jan 17 03:13:46 PM PST 24
Finished Jan 17 03:16:04 PM PST 24
Peak memory 193296 kb
Host smart-7939fe99-1efc-46fd-b588-fe510ab72543
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828083427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3828083427
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3185107257
Short name T335
Test name
Test status
Simulation time 332588362378 ps
CPU time 242.06 seconds
Started Jan 17 03:13:51 PM PST 24
Finished Jan 17 03:17:53 PM PST 24
Peak memory 194408 kb
Host smart-7b53703c-506b-44a6-9f9c-3c864bb2649b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185107257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3185107257
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.4135585329
Short name T534
Test name
Test status
Simulation time 28074267378 ps
CPU time 78.06 seconds
Started Jan 17 03:13:51 PM PST 24
Finished Jan 17 03:15:09 PM PST 24
Peak memory 182988 kb
Host smart-a4c2226f-8dc8-4bd2-b249-2aaf22acb762
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135585329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.4135585329
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2404916732
Short name T235
Test name
Test status
Simulation time 204074865384 ps
CPU time 331.06 seconds
Started Jan 17 03:13:56 PM PST 24
Finished Jan 17 03:19:28 PM PST 24
Peak memory 191140 kb
Host smart-d3277ded-d546-42a8-8602-e89816f29d03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404916732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2404916732
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.741128692
Short name T327
Test name
Test status
Simulation time 19669458377 ps
CPU time 12.01 seconds
Started Jan 17 03:07:59 PM PST 24
Finished Jan 17 03:08:14 PM PST 24
Peak memory 182924 kb
Host smart-7cd0dc6a-1c71-4559-861d-bd5d53592afe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741128692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.rv_timer_cfg_update_on_fly.741128692
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.1759248202
Short name T609
Test name
Test status
Simulation time 246567041261 ps
CPU time 172.63 seconds
Started Jan 17 03:07:58 PM PST 24
Finished Jan 17 03:10:55 PM PST 24
Peak memory 182988 kb
Host smart-54ffa16f-9cbe-4496-ae82-f86238338425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759248202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1759248202
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.2256324305
Short name T46
Test name
Test status
Simulation time 1349251396550 ps
CPU time 212.38 seconds
Started Jan 17 03:08:02 PM PST 24
Finished Jan 17 03:11:35 PM PST 24
Peak memory 191184 kb
Host smart-fd2a7f6c-8e77-4007-8435-d35081500484
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256324305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.2256324305
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.509079744
Short name T128
Test name
Test status
Simulation time 28545448926 ps
CPU time 50.38 seconds
Started Jan 17 03:08:06 PM PST 24
Finished Jan 17 03:08:57 PM PST 24
Peak memory 182840 kb
Host smart-8b86c408-3701-474d-92f1-540a87d8411d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509079744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.509079744
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.1969295252
Short name T520
Test name
Test status
Simulation time 43353032096 ps
CPU time 335.34 seconds
Started Jan 17 03:08:05 PM PST 24
Finished Jan 17 03:13:41 PM PST 24
Peak memory 197660 kb
Host smart-4fda9abf-6cd3-4ddb-a7da-359d981552ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969295252 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.1969295252
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.3422380816
Short name T92
Test name
Test status
Simulation time 158884573161 ps
CPU time 65.41 seconds
Started Jan 17 03:13:51 PM PST 24
Finished Jan 17 03:14:57 PM PST 24
Peak memory 191188 kb
Host smart-cee3384b-27e7-41bc-b3e7-ab4d8b4ea4bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422380816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3422380816
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.3464912233
Short name T543
Test name
Test status
Simulation time 11855856268 ps
CPU time 17.64 seconds
Started Jan 17 03:13:55 PM PST 24
Finished Jan 17 03:14:13 PM PST 24
Peak memory 182992 kb
Host smart-96b53de3-d302-41ab-a2ce-ffb64b0d19f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464912233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3464912233
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2157354670
Short name T47
Test name
Test status
Simulation time 38077675231 ps
CPU time 244.92 seconds
Started Jan 17 03:13:54 PM PST 24
Finished Jan 17 03:18:00 PM PST 24
Peak memory 191152 kb
Host smart-502129a5-e56e-434b-b395-b705ae7517f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157354670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2157354670
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2424638887
Short name T342
Test name
Test status
Simulation time 50727613371 ps
CPU time 41.99 seconds
Started Jan 17 03:14:08 PM PST 24
Finished Jan 17 03:14:54 PM PST 24
Peak memory 191092 kb
Host smart-9186a6e9-d654-48c0-880e-459daf44f999
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424638887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2424638887
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.1080501733
Short name T546
Test name
Test status
Simulation time 113627052224 ps
CPU time 815.7 seconds
Started Jan 17 03:14:06 PM PST 24
Finished Jan 17 03:27:43 PM PST 24
Peak memory 194740 kb
Host smart-7a691efc-15e7-4a6e-8a2f-43420c3f74c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080501733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1080501733
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.4208583228
Short name T620
Test name
Test status
Simulation time 25108695847 ps
CPU time 45.36 seconds
Started Jan 17 03:14:09 PM PST 24
Finished Jan 17 03:14:57 PM PST 24
Peak memory 183024 kb
Host smart-1d573087-0a01-4b81-bcac-76bd8475ea31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208583228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.4208583228
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1274516566
Short name T549
Test name
Test status
Simulation time 130254780027 ps
CPU time 173.23 seconds
Started Jan 17 03:08:00 PM PST 24
Finished Jan 17 03:10:55 PM PST 24
Peak memory 182992 kb
Host smart-d16b02d0-322b-4ba9-9d88-d610ba221001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274516566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1274516566
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.1422115740
Short name T206
Test name
Test status
Simulation time 89145989140 ps
CPU time 140.64 seconds
Started Jan 17 03:08:01 PM PST 24
Finished Jan 17 03:10:23 PM PST 24
Peak memory 191192 kb
Host smart-9b7e8165-2c6e-4787-bf61-24dcfe5db261
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422115740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1422115740
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3485054084
Short name T559
Test name
Test status
Simulation time 900238991 ps
CPU time 1.49 seconds
Started Jan 17 03:08:00 PM PST 24
Finished Jan 17 03:08:04 PM PST 24
Peak memory 182624 kb
Host smart-d2830794-64bb-4548-97ea-f875dc3d4cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485054084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3485054084
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3333880279
Short name T352
Test name
Test status
Simulation time 91993747604 ps
CPU time 593.63 seconds
Started Jan 17 03:08:05 PM PST 24
Finished Jan 17 03:17:59 PM PST 24
Peak memory 191092 kb
Host smart-5642c77d-6814-48f9-9e2f-21b6ca43f38a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333880279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3333880279
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.1081849209
Short name T31
Test name
Test status
Simulation time 357101008200 ps
CPU time 711.36 seconds
Started Jan 17 03:08:02 PM PST 24
Finished Jan 17 03:19:54 PM PST 24
Peak memory 208792 kb
Host smart-34121e72-9192-43c7-ba7e-54dba3753aee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081849209 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.1081849209
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/172.rv_timer_random.62172675
Short name T116
Test name
Test status
Simulation time 66913357137 ps
CPU time 1001.71 seconds
Started Jan 17 03:14:08 PM PST 24
Finished Jan 17 03:30:53 PM PST 24
Peak memory 191188 kb
Host smart-e4bb7764-acb8-49a8-9e7d-1240e7a9ecae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62172675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.62172675
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.2193654167
Short name T145
Test name
Test status
Simulation time 27337857536 ps
CPU time 42.31 seconds
Started Jan 17 03:14:14 PM PST 24
Finished Jan 17 03:15:00 PM PST 24
Peak memory 193564 kb
Host smart-fc945a00-b06e-4c41-9223-1a8dcb637445
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193654167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2193654167
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2712989097
Short name T224
Test name
Test status
Simulation time 355530838116 ps
CPU time 235.68 seconds
Started Jan 17 03:14:15 PM PST 24
Finished Jan 17 03:18:13 PM PST 24
Peak memory 191160 kb
Host smart-aeb48fa0-7108-40b8-bd7a-f28427d2cf76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712989097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2712989097
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.1088387993
Short name T278
Test name
Test status
Simulation time 264430881871 ps
CPU time 435.25 seconds
Started Jan 17 03:14:07 PM PST 24
Finished Jan 17 03:21:25 PM PST 24
Peak memory 191200 kb
Host smart-3352cddf-35f3-4176-b51d-6b79f6333a79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088387993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1088387993
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.353670961
Short name T134
Test name
Test status
Simulation time 74885010775 ps
CPU time 444.91 seconds
Started Jan 17 03:14:13 PM PST 24
Finished Jan 17 03:21:43 PM PST 24
Peak memory 191136 kb
Host smart-300d8a30-59a0-4bbc-850d-d8dc4f77f9c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353670961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.353670961
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2163769603
Short name T250
Test name
Test status
Simulation time 345114547973 ps
CPU time 359.59 seconds
Started Jan 17 03:08:06 PM PST 24
Finished Jan 17 03:14:06 PM PST 24
Peak memory 182832 kb
Host smart-3f248a90-702c-49c8-a0d6-326ec555c7a5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163769603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.2163769603
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.2365463608
Short name T487
Test name
Test status
Simulation time 94821449373 ps
CPU time 154.65 seconds
Started Jan 17 03:08:02 PM PST 24
Finished Jan 17 03:10:37 PM PST 24
Peak memory 182936 kb
Host smart-ab2120e1-600d-44b9-9d53-0cc57f2cc638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365463608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2365463608
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.4260381475
Short name T331
Test name
Test status
Simulation time 33965150519 ps
CPU time 64.91 seconds
Started Jan 17 03:08:04 PM PST 24
Finished Jan 17 03:09:09 PM PST 24
Peak memory 182972 kb
Host smart-3cd485a2-c3b3-4f2d-b416-a0183509fbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260381475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.4260381475
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3701411460
Short name T43
Test name
Test status
Simulation time 67452256867 ps
CPU time 112.35 seconds
Started Jan 17 03:07:59 PM PST 24
Finished Jan 17 03:09:54 PM PST 24
Peak memory 195188 kb
Host smart-b72f1918-39ae-44cf-b20d-165b9ae3cd42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701411460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3701411460
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.561516597
Short name T586
Test name
Test status
Simulation time 321916851391 ps
CPU time 156.04 seconds
Started Jan 17 03:14:15 PM PST 24
Finished Jan 17 03:16:54 PM PST 24
Peak memory 190832 kb
Host smart-293191de-df6c-4a4b-b8e6-193c838883dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561516597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.561516597
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.4219548060
Short name T172
Test name
Test status
Simulation time 660048048994 ps
CPU time 731.84 seconds
Started Jan 17 03:14:13 PM PST 24
Finished Jan 17 03:26:30 PM PST 24
Peak memory 191188 kb
Host smart-76188d74-e452-4f5f-b554-1ef0a9c986d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219548060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.4219548060
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.2127623890
Short name T240
Test name
Test status
Simulation time 39670776538 ps
CPU time 70.6 seconds
Started Jan 17 03:14:13 PM PST 24
Finished Jan 17 03:15:28 PM PST 24
Peak memory 182944 kb
Host smart-f384d5e0-2732-44a3-877d-294542c70a0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127623890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.2127623890
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.2903200901
Short name T177
Test name
Test status
Simulation time 15277709800 ps
CPU time 543.06 seconds
Started Jan 17 03:14:11 PM PST 24
Finished Jan 17 03:23:15 PM PST 24
Peak memory 182876 kb
Host smart-f79dbd77-38d8-407d-b220-5927dbf8ab16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903200901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2903200901
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.3710466754
Short name T223
Test name
Test status
Simulation time 81269954924 ps
CPU time 135.88 seconds
Started Jan 17 03:14:22 PM PST 24
Finished Jan 17 03:16:45 PM PST 24
Peak memory 191168 kb
Host smart-864c13e4-7044-4263-abfd-7eae4b81558c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710466754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3710466754
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.3561423313
Short name T336
Test name
Test status
Simulation time 26403906747 ps
CPU time 30.6 seconds
Started Jan 17 03:14:21 PM PST 24
Finished Jan 17 03:14:59 PM PST 24
Peak memory 182980 kb
Host smart-e3f45778-3b9d-4250-93bc-0a0a49ca2fd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561423313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3561423313
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.723242436
Short name T108
Test name
Test status
Simulation time 238722661521 ps
CPU time 244.81 seconds
Started Jan 17 03:14:23 PM PST 24
Finished Jan 17 03:18:34 PM PST 24
Peak memory 191200 kb
Host smart-44ab409e-d849-437c-8b3a-322affa9f8f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723242436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.723242436
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.989515911
Short name T243
Test name
Test status
Simulation time 98867209201 ps
CPU time 207.61 seconds
Started Jan 17 03:14:19 PM PST 24
Finished Jan 17 03:17:56 PM PST 24
Peak memory 194284 kb
Host smart-965e8bbe-a044-4242-8d82-124259c420f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989515911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.989515911
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2308749984
Short name T205
Test name
Test status
Simulation time 7721316006038 ps
CPU time 2699.61 seconds
Started Jan 17 03:08:05 PM PST 24
Finished Jan 17 03:53:06 PM PST 24
Peak memory 182980 kb
Host smart-8fd8dc90-2bdc-4401-b38f-48ff241d7489
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308749984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2308749984
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1278707625
Short name T514
Test name
Test status
Simulation time 48895420442 ps
CPU time 64.66 seconds
Started Jan 17 03:08:02 PM PST 24
Finished Jan 17 03:09:07 PM PST 24
Peak memory 182980 kb
Host smart-7b8d47e6-30e7-498c-aef3-3b60cff6312b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278707625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1278707625
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.472043539
Short name T288
Test name
Test status
Simulation time 540498563523 ps
CPU time 839.47 seconds
Started Jan 17 03:08:05 PM PST 24
Finished Jan 17 03:22:05 PM PST 24
Peak memory 191104 kb
Host smart-1ed15682-5650-4ec0-aa29-2b4d6094c1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472043539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.472043539
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.1071362046
Short name T338
Test name
Test status
Simulation time 461089456178 ps
CPU time 1439.54 seconds
Started Jan 17 03:08:00 PM PST 24
Finished Jan 17 03:32:02 PM PST 24
Peak memory 206932 kb
Host smart-2bc377ca-a9d1-4c4e-9578-7ce83483fb40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071362046 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.1071362046
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.1153807594
Short name T246
Test name
Test status
Simulation time 1471647863857 ps
CPU time 413.13 seconds
Started Jan 17 03:14:23 PM PST 24
Finished Jan 17 03:21:22 PM PST 24
Peak memory 191140 kb
Host smart-18d81bb4-4542-42fb-aa07-5600c901bf9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153807594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1153807594
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.4181801326
Short name T593
Test name
Test status
Simulation time 167304427425 ps
CPU time 115.37 seconds
Started Jan 17 03:14:24 PM PST 24
Finished Jan 17 03:16:24 PM PST 24
Peak memory 193196 kb
Host smart-825d6424-5961-495d-a92f-c17006655c13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181801326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.4181801326
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.794668271
Short name T290
Test name
Test status
Simulation time 154873357170 ps
CPU time 197.79 seconds
Started Jan 17 03:14:24 PM PST 24
Finished Jan 17 03:17:47 PM PST 24
Peak memory 191152 kb
Host smart-cfe844ae-990e-4110-b36e-bd7157e64de1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794668271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.794668271
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.2216554692
Short name T170
Test name
Test status
Simulation time 51274768377 ps
CPU time 186.38 seconds
Started Jan 17 03:14:24 PM PST 24
Finished Jan 17 03:17:35 PM PST 24
Peak memory 191196 kb
Host smart-30e0c7f9-d968-4a9a-94d2-0a1dc8dce56a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216554692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2216554692
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3659280807
Short name T184
Test name
Test status
Simulation time 111668194032 ps
CPU time 229.86 seconds
Started Jan 17 03:14:24 PM PST 24
Finished Jan 17 03:18:19 PM PST 24
Peak memory 191096 kb
Host smart-8d01c2ea-2a98-43d6-a145-fcc912db6e0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659280807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3659280807
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.2275328065
Short name T340
Test name
Test status
Simulation time 43228637108 ps
CPU time 643.66 seconds
Started Jan 17 03:14:31 PM PST 24
Finished Jan 17 03:25:16 PM PST 24
Peak memory 194248 kb
Host smart-0f6ed607-37d7-4ced-bba7-dff3dd05898e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275328065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2275328065
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2208152375
Short name T326
Test name
Test status
Simulation time 34558148167 ps
CPU time 25.33 seconds
Started Jan 17 03:14:30 PM PST 24
Finished Jan 17 03:14:56 PM PST 24
Peak memory 182936 kb
Host smart-7ac16e26-d3fd-4359-8b44-71f648f4f7ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208152375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2208152375
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3496322913
Short name T302
Test name
Test status
Simulation time 10057242774 ps
CPU time 18.75 seconds
Started Jan 17 03:07:28 PM PST 24
Finished Jan 17 03:07:47 PM PST 24
Peak memory 182980 kb
Host smart-e472b524-2f94-4c05-b97b-7b4f002a2f11
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496322913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3496322913
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1146583820
Short name T475
Test name
Test status
Simulation time 86984306422 ps
CPU time 34.51 seconds
Started Jan 17 03:07:25 PM PST 24
Finished Jan 17 03:08:00 PM PST 24
Peak memory 182992 kb
Host smart-f6a7ea8f-e1e1-40ea-9c3f-83356d59f483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146583820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1146583820
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3648885980
Short name T267
Test name
Test status
Simulation time 174014416146 ps
CPU time 518.05 seconds
Started Jan 17 03:07:32 PM PST 24
Finished Jan 17 03:16:10 PM PST 24
Peak memory 193932 kb
Host smart-f5bf4271-0554-4aef-86de-12c9611c8465
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648885980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3648885980
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3936567994
Short name T581
Test name
Test status
Simulation time 17158534 ps
CPU time 0.55 seconds
Started Jan 17 03:07:33 PM PST 24
Finished Jan 17 03:07:34 PM PST 24
Peak memory 182508 kb
Host smart-a6c913da-fa84-4c35-ae54-9684af28d8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936567994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3936567994
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3354306179
Short name T18
Test name
Test status
Simulation time 219446105 ps
CPU time 0.85 seconds
Started Jan 17 03:07:33 PM PST 24
Finished Jan 17 03:07:35 PM PST 24
Peak memory 212928 kb
Host smart-e0771990-b20a-48b4-9682-dac6963fe46e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354306179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3354306179
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.3568195274
Short name T521
Test name
Test status
Simulation time 75819341440 ps
CPU time 811.26 seconds
Started Jan 17 03:07:30 PM PST 24
Finished Jan 17 03:21:02 PM PST 24
Peak memory 212132 kb
Host smart-e4a9e250-0868-4616-a31e-84f092c1d765
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568195274 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.3568195274
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.891288802
Short name T607
Test name
Test status
Simulation time 7389746652 ps
CPU time 7.57 seconds
Started Jan 17 03:08:05 PM PST 24
Finished Jan 17 03:08:13 PM PST 24
Peak memory 182908 kb
Host smart-fb517d23-f464-47b2-b2e6-8e4e219bc920
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891288802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.rv_timer_cfg_update_on_fly.891288802
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.3102534842
Short name T483
Test name
Test status
Simulation time 111822216574 ps
CPU time 152.19 seconds
Started Jan 17 03:08:09 PM PST 24
Finished Jan 17 03:10:42 PM PST 24
Peak memory 183060 kb
Host smart-1fc58b52-310f-4f3d-977b-2104dba02d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102534842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3102534842
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.2595593398
Short name T617
Test name
Test status
Simulation time 94987534706 ps
CPU time 76.25 seconds
Started Jan 17 03:08:02 PM PST 24
Finished Jan 17 03:09:19 PM PST 24
Peak memory 191156 kb
Host smart-ac7ab99a-a7fe-4342-b3c3-87897d6ec850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595593398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2595593398
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.677987308
Short name T547
Test name
Test status
Simulation time 154966883 ps
CPU time 0.64 seconds
Started Jan 17 03:08:06 PM PST 24
Finished Jan 17 03:08:07 PM PST 24
Peak memory 182708 kb
Host smart-57c58678-f3d4-4a3d-a947-09bb4e66e258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677987308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.677987308
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.789331290
Short name T329
Test name
Test status
Simulation time 283633808926 ps
CPU time 485.08 seconds
Started Jan 17 03:08:03 PM PST 24
Finished Jan 17 03:16:09 PM PST 24
Peak memory 205888 kb
Host smart-1821dd5e-8e0f-4771-88e4-3c8b847334f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789331290 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.789331290
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3768583181
Short name T95
Test name
Test status
Simulation time 330282482195 ps
CPU time 81.06 seconds
Started Jan 17 03:08:08 PM PST 24
Finished Jan 17 03:09:30 PM PST 24
Peak memory 182900 kb
Host smart-5028b72d-4703-4434-8bca-130cd1610f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768583181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3768583181
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.4277259475
Short name T505
Test name
Test status
Simulation time 1290358364 ps
CPU time 1.27 seconds
Started Jan 17 03:08:04 PM PST 24
Finished Jan 17 03:08:05 PM PST 24
Peak memory 191108 kb
Host smart-9848bb92-364d-4cad-b2f7-81765dbf9e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277259475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.4277259475
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.4226015668
Short name T517
Test name
Test status
Simulation time 414472463314 ps
CPU time 1650.15 seconds
Started Jan 17 03:08:09 PM PST 24
Finished Jan 17 03:35:40 PM PST 24
Peak memory 213888 kb
Host smart-8bc2ce27-9c4a-45dd-9db8-3d30237f548f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226015668 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.4226015668
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1948355900
Short name T536
Test name
Test status
Simulation time 1267607833537 ps
CPU time 344.87 seconds
Started Jan 17 03:08:07 PM PST 24
Finished Jan 17 03:13:52 PM PST 24
Peak memory 182932 kb
Host smart-b2e300c8-7cdb-46c5-bc84-614121a2fd9f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948355900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1948355900
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3881855752
Short name T618
Test name
Test status
Simulation time 51265910374 ps
CPU time 70.2 seconds
Started Jan 17 03:08:04 PM PST 24
Finished Jan 17 03:09:14 PM PST 24
Peak memory 182896 kb
Host smart-07c3049d-a2ab-4fd9-93b4-9a5913dccb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881855752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3881855752
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.1196663675
Short name T130
Test name
Test status
Simulation time 528953459133 ps
CPU time 638.66 seconds
Started Jan 17 03:08:04 PM PST 24
Finished Jan 17 03:18:43 PM PST 24
Peak memory 191172 kb
Host smart-569c6d38-0624-4927-a728-22e3e2055e1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196663675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1196663675
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2860883604
Short name T489
Test name
Test status
Simulation time 350428371 ps
CPU time 0.93 seconds
Started Jan 17 03:08:13 PM PST 24
Finished Jan 17 03:08:16 PM PST 24
Peak memory 193544 kb
Host smart-ad0c467d-4219-429b-b0ab-3b588b967f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860883604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2860883604
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.2485578563
Short name T474
Test name
Test status
Simulation time 246921541730 ps
CPU time 1016.67 seconds
Started Jan 17 03:08:03 PM PST 24
Finished Jan 17 03:25:00 PM PST 24
Peak memory 208896 kb
Host smart-657a50dc-1bd2-4423-ad3e-6d35e0102e50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485578563 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.2485578563
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.254644720
Short name T358
Test name
Test status
Simulation time 174809288462 ps
CPU time 73.9 seconds
Started Jan 17 03:08:05 PM PST 24
Finished Jan 17 03:09:19 PM PST 24
Peak memory 182960 kb
Host smart-d1049868-c570-4c23-9b5d-6f0b0d30b579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254644720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.254644720
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.3767957409
Short name T553
Test name
Test status
Simulation time 58220352101 ps
CPU time 290.59 seconds
Started Jan 17 03:08:01 PM PST 24
Finished Jan 17 03:12:53 PM PST 24
Peak memory 191168 kb
Host smart-b480e64d-1cbd-4e3e-ab3b-544f7961bc06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767957409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3767957409
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3441549759
Short name T511
Test name
Test status
Simulation time 1482734172 ps
CPU time 1.3 seconds
Started Jan 17 03:08:06 PM PST 24
Finished Jan 17 03:08:07 PM PST 24
Peak memory 192528 kb
Host smart-69922762-529b-4384-9474-aedfadb3119e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441549759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3441549759
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.2502307879
Short name T503
Test name
Test status
Simulation time 61662414297 ps
CPU time 470.65 seconds
Started Jan 17 03:08:05 PM PST 24
Finished Jan 17 03:15:56 PM PST 24
Peak memory 205880 kb
Host smart-7083c6f4-9292-48bc-9e8c-b1aa374e222b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502307879 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.2502307879
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.2252140395
Short name T357
Test name
Test status
Simulation time 119335132669 ps
CPU time 175.47 seconds
Started Jan 17 03:08:09 PM PST 24
Finished Jan 17 03:11:05 PM PST 24
Peak memory 182992 kb
Host smart-cd975e82-a59d-45e5-824b-8f0c2bb3dc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252140395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.2252140395
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.3673133725
Short name T138
Test name
Test status
Simulation time 107646405047 ps
CPU time 134.2 seconds
Started Jan 17 03:08:10 PM PST 24
Finished Jan 17 03:10:24 PM PST 24
Peak memory 195116 kb
Host smart-4b07c6bf-72f9-47ba-a5fd-0aa0c3f433cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673133725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.3673133725
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.1292366134
Short name T273
Test name
Test status
Simulation time 567130830070 ps
CPU time 456.88 seconds
Started Jan 17 03:08:12 PM PST 24
Finished Jan 17 03:15:50 PM PST 24
Peak memory 191096 kb
Host smart-aaad9420-9919-482c-8f53-c10955750624
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292366134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.1292366134
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.3753454104
Short name T506
Test name
Test status
Simulation time 1369626503838 ps
CPU time 917.18 seconds
Started Jan 17 03:08:10 PM PST 24
Finished Jan 17 03:23:27 PM PST 24
Peak memory 210324 kb
Host smart-5cd8ba94-8700-4afb-8d60-e6b92b83f5ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753454104 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.3753454104
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2023598293
Short name T241
Test name
Test status
Simulation time 25037802564 ps
CPU time 44.94 seconds
Started Jan 17 03:08:09 PM PST 24
Finished Jan 17 03:08:55 PM PST 24
Peak memory 182908 kb
Host smart-7b4d1023-e759-455c-8c25-0385d9d7b488
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023598293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2023598293
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.948023100
Short name T26
Test name
Test status
Simulation time 601544024219 ps
CPU time 254.31 seconds
Started Jan 17 03:08:09 PM PST 24
Finished Jan 17 03:12:24 PM PST 24
Peak memory 182892 kb
Host smart-cc703102-ba07-47e8-b7c5-23598038ad8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948023100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.948023100
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.1438612662
Short name T261
Test name
Test status
Simulation time 65589434242 ps
CPU time 181.04 seconds
Started Jan 17 03:08:10 PM PST 24
Finished Jan 17 03:11:12 PM PST 24
Peak memory 194208 kb
Host smart-a1f2fc65-b0a9-45b1-b86b-51041621e156
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438612662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1438612662
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.2702822271
Short name T247
Test name
Test status
Simulation time 89282353852 ps
CPU time 88.6 seconds
Started Jan 17 03:08:08 PM PST 24
Finished Jan 17 03:09:37 PM PST 24
Peak memory 194412 kb
Host smart-b0c8b883-1903-476c-8e8c-0da08631050c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702822271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2702822271
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1436457340
Short name T355
Test name
Test status
Simulation time 1157641628953 ps
CPU time 3394.82 seconds
Started Jan 17 03:08:08 PM PST 24
Finished Jan 17 04:04:44 PM PST 24
Peak memory 191104 kb
Host smart-8bb3198a-e7b7-429c-ba92-3a2f0e2c1ab0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436457340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1436457340
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.981654912
Short name T30
Test name
Test status
Simulation time 32041935610 ps
CPU time 263.01 seconds
Started Jan 17 03:08:10 PM PST 24
Finished Jan 17 03:12:34 PM PST 24
Peak memory 197672 kb
Host smart-0eba1745-c854-4c37-8d63-e5538d2fbdc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981654912 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.981654912
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3666716098
Short name T208
Test name
Test status
Simulation time 458830030850 ps
CPU time 804.53 seconds
Started Jan 17 03:08:14 PM PST 24
Finished Jan 17 03:21:40 PM PST 24
Peak memory 182968 kb
Host smart-6e8c1d07-40dc-484d-a741-3b2d38555b39
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666716098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3666716098
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.1379147075
Short name T499
Test name
Test status
Simulation time 183987932037 ps
CPU time 73.52 seconds
Started Jan 17 03:08:11 PM PST 24
Finished Jan 17 03:09:26 PM PST 24
Peak memory 183036 kb
Host smart-3a906a13-6831-4b0a-a6d1-deced2b5538c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379147075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1379147075
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.3433222427
Short name T123
Test name
Test status
Simulation time 219858507277 ps
CPU time 407.86 seconds
Started Jan 17 03:08:17 PM PST 24
Finished Jan 17 03:15:09 PM PST 24
Peak memory 191176 kb
Host smart-a7040b21-98fc-42d7-a90d-54591d453b78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433222427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3433222427
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2046409014
Short name T275
Test name
Test status
Simulation time 74852786830 ps
CPU time 1271.13 seconds
Started Jan 17 03:08:16 PM PST 24
Finished Jan 17 03:29:28 PM PST 24
Peak memory 191144 kb
Host smart-ba81bf05-2a0c-4576-89d1-11d8ed8786ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046409014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2046409014
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.367474519
Short name T109
Test name
Test status
Simulation time 3471997631032 ps
CPU time 803.02 seconds
Started Jan 17 03:08:20 PM PST 24
Finished Jan 17 03:21:45 PM PST 24
Peak memory 191044 kb
Host smart-a1c2cbca-f294-41e9-9a9c-68e6a0a6bbe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367474519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.
367474519
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.3424087523
Short name T477
Test name
Test status
Simulation time 154496786994 ps
CPU time 777.15 seconds
Started Jan 17 03:08:15 PM PST 24
Finished Jan 17 03:21:13 PM PST 24
Peak memory 205776 kb
Host smart-be554b84-3c1d-40f3-8169-325ad1f792bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424087523 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.3424087523
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2323500748
Short name T324
Test name
Test status
Simulation time 3443398672985 ps
CPU time 786.23 seconds
Started Jan 17 03:08:19 PM PST 24
Finished Jan 17 03:21:28 PM PST 24
Peak memory 182960 kb
Host smart-f5a57dbe-06f2-4d94-93c8-550f106e3b65
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323500748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.2323500748
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2274343553
Short name T524
Test name
Test status
Simulation time 245946075518 ps
CPU time 221.93 seconds
Started Jan 17 03:08:14 PM PST 24
Finished Jan 17 03:11:57 PM PST 24
Peak memory 182896 kb
Host smart-da665a79-3c88-489b-9c74-2614570d5375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274343553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2274343553
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3719392789
Short name T113
Test name
Test status
Simulation time 130001568590 ps
CPU time 131.74 seconds
Started Jan 17 03:08:17 PM PST 24
Finished Jan 17 03:10:33 PM PST 24
Peak memory 191184 kb
Host smart-323c080b-a324-450a-9422-38a5c154b239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719392789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3719392789
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.222726728
Short name T201
Test name
Test status
Simulation time 670924868181 ps
CPU time 1339.48 seconds
Started Jan 17 03:08:17 PM PST 24
Finished Jan 17 03:30:41 PM PST 24
Peak memory 211644 kb
Host smart-b3431c90-07a1-4140-82e8-0f55be50a24f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222726728 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.222726728
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3001279477
Short name T613
Test name
Test status
Simulation time 15067133136 ps
CPU time 8.95 seconds
Started Jan 17 03:08:16 PM PST 24
Finished Jan 17 03:08:25 PM PST 24
Peak memory 182972 kb
Host smart-362a3612-afc4-4ad8-a54a-9fa2ab517f66
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001279477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.3001279477
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.4253405953
Short name T588
Test name
Test status
Simulation time 66881415036 ps
CPU time 56.75 seconds
Started Jan 17 03:08:15 PM PST 24
Finished Jan 17 03:09:13 PM PST 24
Peak memory 182940 kb
Host smart-2b5ed75d-e1df-4027-baab-4132d05b87b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253405953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.4253405953
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2920607701
Short name T321
Test name
Test status
Simulation time 118973693939 ps
CPU time 66.7 seconds
Started Jan 17 03:08:17 PM PST 24
Finished Jan 17 03:09:28 PM PST 24
Peak memory 191120 kb
Host smart-347b43da-70b1-493e-a24a-e52302a46596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920607701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2920607701
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.3097556404
Short name T537
Test name
Test status
Simulation time 182915337193 ps
CPU time 341.96 seconds
Started Jan 17 03:08:20 PM PST 24
Finished Jan 17 03:14:03 PM PST 24
Peak memory 197680 kb
Host smart-afd6b6cd-47df-4ec0-ab0c-92647c14f8d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097556404 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.3097556404
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.4126391138
Short name T216
Test name
Test status
Simulation time 179152005438 ps
CPU time 176.02 seconds
Started Jan 17 03:08:20 PM PST 24
Finished Jan 17 03:11:17 PM PST 24
Peak memory 182920 kb
Host smart-bc4f1797-1b4c-4ed6-be55-08fd0f416f5d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126391138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.4126391138
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2193976824
Short name T565
Test name
Test status
Simulation time 767583561640 ps
CPU time 308.94 seconds
Started Jan 17 03:08:21 PM PST 24
Finished Jan 17 03:13:30 PM PST 24
Peak memory 182968 kb
Host smart-40e2a569-bd77-46e9-a7ea-1e52998c7b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193976824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2193976824
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.554610619
Short name T540
Test name
Test status
Simulation time 79018026761 ps
CPU time 514.75 seconds
Started Jan 17 03:08:21 PM PST 24
Finished Jan 17 03:16:56 PM PST 24
Peak memory 191204 kb
Host smart-b83d1c23-0069-4070-adad-e7853cbaa92d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554610619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.554610619
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1241627
Short name T590
Test name
Test status
Simulation time 33581771715 ps
CPU time 291.41 seconds
Started Jan 17 03:08:21 PM PST 24
Finished Jan 17 03:13:15 PM PST 24
Peak memory 182940 kb
Host smart-c980c07e-f63f-4492-b610-04ab8bdf26b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1241627
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.3922006712
Short name T484
Test name
Test status
Simulation time 245196980201 ps
CPU time 1136.68 seconds
Started Jan 17 03:08:29 PM PST 24
Finished Jan 17 03:27:26 PM PST 24
Peak memory 212228 kb
Host smart-8ce88a47-f795-4340-a73e-68778470caa2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922006712 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.3922006712
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.83328757
Short name T564
Test name
Test status
Simulation time 40787594464 ps
CPU time 11.1 seconds
Started Jan 17 03:07:33 PM PST 24
Finished Jan 17 03:07:45 PM PST 24
Peak memory 183032 kb
Host smart-d3865d60-b250-4a5e-8579-d827e4732407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83328757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.83328757
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.882821533
Short name T4
Test name
Test status
Simulation time 57658820720 ps
CPU time 115.31 seconds
Started Jan 17 03:07:31 PM PST 24
Finished Jan 17 03:09:27 PM PST 24
Peak memory 191112 kb
Host smart-31bffcb7-3a31-431c-adb5-0de6cb2f980e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882821533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.882821533
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3505654373
Short name T560
Test name
Test status
Simulation time 33545076403 ps
CPU time 39.27 seconds
Started Jan 17 03:07:31 PM PST 24
Finished Jan 17 03:08:11 PM PST 24
Peak memory 191124 kb
Host smart-0a588547-a2d6-4e0d-910c-709d23b59b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505654373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3505654373
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.1981178972
Short name T15
Test name
Test status
Simulation time 114062082 ps
CPU time 0.93 seconds
Started Jan 17 03:07:30 PM PST 24
Finished Jan 17 03:07:32 PM PST 24
Peak memory 212892 kb
Host smart-1ec346d3-8fa7-4dee-9f4a-513f8e83942a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981178972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1981178972
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.4092954505
Short name T263
Test name
Test status
Simulation time 461622899847 ps
CPU time 955.7 seconds
Started Jan 17 03:07:30 PM PST 24
Finished Jan 17 03:23:26 PM PST 24
Peak memory 211096 kb
Host smart-a96403ff-e591-4e4e-acb3-4b758d02b19f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092954505 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.4092954505
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2823543714
Short name T168
Test name
Test status
Simulation time 72849616193 ps
CPU time 128.99 seconds
Started Jan 17 03:08:33 PM PST 24
Finished Jan 17 03:10:42 PM PST 24
Peak memory 182940 kb
Host smart-fb86d135-9eb5-49c5-a54d-ee9be86d4192
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823543714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2823543714
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3781317329
Short name T523
Test name
Test status
Simulation time 20108298502 ps
CPU time 32.53 seconds
Started Jan 17 03:08:28 PM PST 24
Finished Jan 17 03:09:01 PM PST 24
Peak memory 182892 kb
Host smart-261d4ede-0187-48cd-ae22-e039c6e63c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781317329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3781317329
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2699441141
Short name T162
Test name
Test status
Simulation time 810176490261 ps
CPU time 708.3 seconds
Started Jan 17 03:08:35 PM PST 24
Finished Jan 17 03:20:23 PM PST 24
Peak memory 193956 kb
Host smart-042faa01-fa3c-440d-ab36-4a73bd75e636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699441141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2699441141
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2794156488
Short name T231
Test name
Test status
Simulation time 21728644623 ps
CPU time 183.3 seconds
Started Jan 17 03:08:42 PM PST 24
Finished Jan 17 03:11:46 PM PST 24
Peak memory 194380 kb
Host smart-910cc4a5-3664-4119-8a84-c7425a3c5ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794156488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2794156488
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.2885675144
Short name T33
Test name
Test status
Simulation time 351854874203 ps
CPU time 937.32 seconds
Started Jan 17 03:08:31 PM PST 24
Finished Jan 17 03:24:09 PM PST 24
Peak memory 208248 kb
Host smart-f64f4ed1-36b2-4551-b36a-5055c6256fc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885675144 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.2885675144
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1973735416
Short name T344
Test name
Test status
Simulation time 57585071625 ps
CPU time 104.78 seconds
Started Jan 17 03:08:47 PM PST 24
Finished Jan 17 03:10:34 PM PST 24
Peak memory 182976 kb
Host smart-30f74a10-3d65-4139-81ed-281ba52a13fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973735416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1973735416
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.4216075868
Short name T518
Test name
Test status
Simulation time 76630838927 ps
CPU time 115.17 seconds
Started Jan 17 03:08:44 PM PST 24
Finished Jan 17 03:10:40 PM PST 24
Peak memory 183000 kb
Host smart-58ce5b93-f331-4ed6-b6a8-8c0ea130d2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216075868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.4216075868
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.4005105942
Short name T580
Test name
Test status
Simulation time 175273895287 ps
CPU time 100.95 seconds
Started Jan 17 03:08:47 PM PST 24
Finished Jan 17 03:10:30 PM PST 24
Peak memory 191148 kb
Host smart-9698f4ac-b7f3-4f0c-bf5b-3f36c215caf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005105942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.4005105942
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2891882948
Short name T509
Test name
Test status
Simulation time 45299100 ps
CPU time 0.52 seconds
Started Jan 17 03:08:49 PM PST 24
Finished Jan 17 03:08:51 PM PST 24
Peak memory 182384 kb
Host smart-c1edb07b-cb0e-4182-b5b1-0438943841f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891882948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2891882948
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.3420778012
Short name T478
Test name
Test status
Simulation time 340242208742 ps
CPU time 298.26 seconds
Started Jan 17 03:08:47 PM PST 24
Finished Jan 17 03:13:48 PM PST 24
Peak memory 182888 kb
Host smart-e0f1186e-364d-435f-a5de-63ea2070b224
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420778012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.3420778012
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.4009245250
Short name T541
Test name
Test status
Simulation time 415717368642 ps
CPU time 859.27 seconds
Started Jan 17 03:08:50 PM PST 24
Finished Jan 17 03:23:11 PM PST 24
Peak memory 209520 kb
Host smart-2e0fc136-db74-4895-b9fe-daeacc8f303a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009245250 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.4009245250
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1101404639
Short name T350
Test name
Test status
Simulation time 444966818298 ps
CPU time 246.36 seconds
Started Jan 17 03:08:46 PM PST 24
Finished Jan 17 03:12:54 PM PST 24
Peak memory 182972 kb
Host smart-994ec4ef-e253-4bf2-a3f1-ae6896c97a6b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101404639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.1101404639
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3429558157
Short name T473
Test name
Test status
Simulation time 100197900151 ps
CPU time 133 seconds
Started Jan 17 03:08:46 PM PST 24
Finished Jan 17 03:11:01 PM PST 24
Peak memory 182972 kb
Host smart-dbbf0196-ca4f-4fc6-8ea8-e590a53842b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429558157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3429558157
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.2449095876
Short name T545
Test name
Test status
Simulation time 43573656421 ps
CPU time 39.07 seconds
Started Jan 17 03:08:50 PM PST 24
Finished Jan 17 03:09:30 PM PST 24
Peak memory 194192 kb
Host smart-bf5b8ede-b904-485c-a02b-cbbf6b72e0ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449095876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2449095876
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.747415561
Short name T597
Test name
Test status
Simulation time 13775298629 ps
CPU time 5.68 seconds
Started Jan 17 03:08:48 PM PST 24
Finished Jan 17 03:08:56 PM PST 24
Peak memory 182752 kb
Host smart-a8ba0dcc-ba1d-4be7-95db-bc3dacbc4fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747415561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.747415561
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3938882700
Short name T611
Test name
Test status
Simulation time 376923896473 ps
CPU time 207.52 seconds
Started Jan 17 03:08:47 PM PST 24
Finished Jan 17 03:12:17 PM PST 24
Peak memory 191204 kb
Host smart-372c276b-75a2-48d5-b25b-e15ec778c5cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938882700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3938882700
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.2859097004
Short name T32
Test name
Test status
Simulation time 186261896663 ps
CPU time 350.39 seconds
Started Jan 17 03:08:46 PM PST 24
Finished Jan 17 03:14:37 PM PST 24
Peak memory 207132 kb
Host smart-bd6f7242-b93c-49ec-80b2-d5a398441540
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859097004 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.2859097004
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1529647989
Short name T228
Test name
Test status
Simulation time 317589057611 ps
CPU time 304.35 seconds
Started Jan 17 03:08:50 PM PST 24
Finished Jan 17 03:13:56 PM PST 24
Peak memory 182956 kb
Host smart-52b9b299-9958-4d01-8735-8f44b1848160
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529647989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.1529647989
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.678204644
Short name T582
Test name
Test status
Simulation time 618985338926 ps
CPU time 235.78 seconds
Started Jan 17 03:08:49 PM PST 24
Finished Jan 17 03:12:46 PM PST 24
Peak memory 182972 kb
Host smart-738c0e54-d161-4dbc-9f28-0408a4259276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678204644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.678204644
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1174649692
Short name T7
Test name
Test status
Simulation time 382506159338 ps
CPU time 168.19 seconds
Started Jan 17 03:08:49 PM PST 24
Finished Jan 17 03:11:38 PM PST 24
Peak memory 191152 kb
Host smart-7d4fc18d-e04d-41bc-b56e-d7853809feec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174649692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1174649692
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3150639701
Short name T318
Test name
Test status
Simulation time 76049007164 ps
CPU time 80.38 seconds
Started Jan 17 03:08:50 PM PST 24
Finished Jan 17 03:10:12 PM PST 24
Peak memory 191080 kb
Host smart-31adaedd-7e06-4d8b-ab35-6daeae1d3d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150639701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3150639701
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.2770968581
Short name T568
Test name
Test status
Simulation time 11929135441 ps
CPU time 100.68 seconds
Started Jan 17 03:08:49 PM PST 24
Finished Jan 17 03:10:31 PM PST 24
Peak memory 197548 kb
Host smart-ecc03bf1-f98f-46f0-bd14-4b3698bdb4bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770968581 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.2770968581
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.391037737
Short name T485
Test name
Test status
Simulation time 146805251207 ps
CPU time 56.75 seconds
Started Jan 17 03:08:59 PM PST 24
Finished Jan 17 03:10:00 PM PST 24
Peak memory 182988 kb
Host smart-07d9872d-d08c-4b84-8c4a-db2afa5fc525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391037737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.391037737
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.1324511396
Short name T93
Test name
Test status
Simulation time 131079572363 ps
CPU time 105.6 seconds
Started Jan 17 03:08:50 PM PST 24
Finished Jan 17 03:10:37 PM PST 24
Peak memory 191052 kb
Host smart-57307271-278f-4a61-850e-b34771312378
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324511396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1324511396
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.401437007
Short name T599
Test name
Test status
Simulation time 747217338 ps
CPU time 1.71 seconds
Started Jan 17 03:08:55 PM PST 24
Finished Jan 17 03:08:59 PM PST 24
Peak memory 192300 kb
Host smart-2efbde8c-9adb-448b-8fcb-a6b5e27da38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401437007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.401437007
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3124638379
Short name T614
Test name
Test status
Simulation time 100439645597 ps
CPU time 156.52 seconds
Started Jan 17 03:08:57 PM PST 24
Finished Jan 17 03:11:39 PM PST 24
Peak memory 182904 kb
Host smart-a083be79-e309-45d4-acff-b41b6517d34b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124638379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3124638379
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.2709166297
Short name T293
Test name
Test status
Simulation time 424225889457 ps
CPU time 937.83 seconds
Started Jan 17 03:08:59 PM PST 24
Finished Jan 17 03:24:41 PM PST 24
Peak memory 210604 kb
Host smart-a107db7f-b0b7-43ed-8f67-f995468a40da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709166297 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.2709166297
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3642632666
Short name T5
Test name
Test status
Simulation time 536596861703 ps
CPU time 520.95 seconds
Started Jan 17 03:09:01 PM PST 24
Finished Jan 17 03:17:44 PM PST 24
Peak memory 183000 kb
Host smart-308b43b1-ea0e-4feb-944b-142be873d3cb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642632666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3642632666
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1601302977
Short name T519
Test name
Test status
Simulation time 178483678286 ps
CPU time 280.9 seconds
Started Jan 17 03:08:56 PM PST 24
Finished Jan 17 03:13:38 PM PST 24
Peak memory 182948 kb
Host smart-449583bf-598c-4d1e-ad82-7f4a1f863faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601302977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1601302977
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.3769481750
Short name T280
Test name
Test status
Simulation time 111778188474 ps
CPU time 489.8 seconds
Started Jan 17 03:08:57 PM PST 24
Finished Jan 17 03:17:12 PM PST 24
Peak memory 191112 kb
Host smart-9b6479dd-361e-47bc-ae0e-d5ec22a31f48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769481750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3769481750
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.541318296
Short name T531
Test name
Test status
Simulation time 226067848 ps
CPU time 0.64 seconds
Started Jan 17 03:09:10 PM PST 24
Finished Jan 17 03:09:11 PM PST 24
Peak memory 182688 kb
Host smart-38d513cc-ce65-4662-b172-f3e35f9a15d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541318296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.541318296
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.2397529083
Short name T482
Test name
Test status
Simulation time 1407268628552 ps
CPU time 1322.25 seconds
Started Jan 17 03:09:11 PM PST 24
Finished Jan 17 03:31:14 PM PST 24
Peak memory 210248 kb
Host smart-40b6c30c-007a-4e86-b2b5-02f827e97991
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397529083 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.2397529083
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2635927748
Short name T550
Test name
Test status
Simulation time 126102195946 ps
CPU time 236.69 seconds
Started Jan 17 03:09:20 PM PST 24
Finished Jan 17 03:13:17 PM PST 24
Peak memory 182972 kb
Host smart-76fbf440-2460-4b1d-9799-582358b7d96f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635927748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2635927748
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1693826317
Short name T538
Test name
Test status
Simulation time 240306022250 ps
CPU time 101.72 seconds
Started Jan 17 03:09:13 PM PST 24
Finished Jan 17 03:10:57 PM PST 24
Peak memory 183004 kb
Host smart-b618891e-14a6-4a4b-a07f-9898e417f397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693826317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1693826317
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.857467942
Short name T166
Test name
Test status
Simulation time 449907796453 ps
CPU time 995.16 seconds
Started Jan 17 03:09:12 PM PST 24
Finished Jan 17 03:25:49 PM PST 24
Peak memory 191188 kb
Host smart-3ef34f46-b457-4dd3-85a7-17eee8ac858a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857467942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.857467942
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.1604080710
Short name T598
Test name
Test status
Simulation time 142717493511 ps
CPU time 32.77 seconds
Started Jan 17 03:09:25 PM PST 24
Finished Jan 17 03:09:58 PM PST 24
Peak memory 182956 kb
Host smart-10817f03-38f4-4ff7-af9e-35f1ebdcc0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604080710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.1604080710
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3536456018
Short name T187
Test name
Test status
Simulation time 342801999955 ps
CPU time 634.21 seconds
Started Jan 17 03:09:24 PM PST 24
Finished Jan 17 03:19:59 PM PST 24
Peak memory 194500 kb
Host smart-bf4ec269-be80-4355-95ed-d7bfb1b49c6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536456018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3536456018
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.3049891945
Short name T566
Test name
Test status
Simulation time 199860728404 ps
CPU time 1151.55 seconds
Started Jan 17 03:09:25 PM PST 24
Finished Jan 17 03:28:37 PM PST 24
Peak memory 207648 kb
Host smart-cb514d47-9c35-4cd2-9588-e253ae01398b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049891945 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.3049891945
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.446876971
Short name T307
Test name
Test status
Simulation time 2212533498850 ps
CPU time 709.02 seconds
Started Jan 17 03:09:36 PM PST 24
Finished Jan 17 03:21:26 PM PST 24
Peak memory 182988 kb
Host smart-745555c5-389f-48cd-8695-1d19a9d3a341
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446876971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.446876971
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.256350355
Short name T563
Test name
Test status
Simulation time 656714366553 ps
CPU time 213.43 seconds
Started Jan 17 03:09:31 PM PST 24
Finished Jan 17 03:13:05 PM PST 24
Peak memory 182980 kb
Host smart-b1dc78a0-6bf8-476d-b810-bc143749d9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256350355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.256350355
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.3402632725
Short name T612
Test name
Test status
Simulation time 123660074063 ps
CPU time 74.12 seconds
Started Jan 17 03:09:29 PM PST 24
Finished Jan 17 03:10:44 PM PST 24
Peak memory 182876 kb
Host smart-c3473a9d-779d-4aa4-8c15-6425bd4510ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402632725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3402632725
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.112587780
Short name T507
Test name
Test status
Simulation time 205213393909 ps
CPU time 141.91 seconds
Started Jan 17 03:09:29 PM PST 24
Finished Jan 17 03:11:52 PM PST 24
Peak memory 194060 kb
Host smart-1cb545e5-4868-4739-bb7e-86788692a9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112587780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.112587780
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.1809817871
Short name T79
Test name
Test status
Simulation time 227737925588 ps
CPU time 1004.57 seconds
Started Jan 17 03:09:36 PM PST 24
Finished Jan 17 03:26:21 PM PST 24
Peak memory 208120 kb
Host smart-3e77098d-cd6c-405a-986a-672a20365fb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809817871 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.1809817871
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.2905282287
Short name T175
Test name
Test status
Simulation time 21662377318 ps
CPU time 13.36 seconds
Started Jan 17 03:09:41 PM PST 24
Finished Jan 17 03:09:55 PM PST 24
Peak memory 182904 kb
Host smart-4c77946f-25a5-4303-a2ea-5f97345faba4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905282287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.2905282287
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.650759619
Short name T539
Test name
Test status
Simulation time 78611272990 ps
CPU time 106.73 seconds
Started Jan 17 03:09:41 PM PST 24
Finished Jan 17 03:11:28 PM PST 24
Peak memory 182908 kb
Host smart-dba6b87a-26af-4f10-9bd2-d1c746b6ad9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650759619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.650759619
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2998372240
Short name T351
Test name
Test status
Simulation time 118307332713 ps
CPU time 489.79 seconds
Started Jan 17 03:09:43 PM PST 24
Finished Jan 17 03:17:54 PM PST 24
Peak memory 191196 kb
Host smart-bcf88f7c-98a7-4be0-91f1-5e774723d499
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998372240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2998372240
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1513525069
Short name T562
Test name
Test status
Simulation time 109175781 ps
CPU time 0.68 seconds
Started Jan 17 03:09:41 PM PST 24
Finished Jan 17 03:09:42 PM PST 24
Peak memory 182356 kb
Host smart-c495c332-5402-4397-a599-41271925607f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513525069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1513525069
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3885136740
Short name T345
Test name
Test status
Simulation time 606966565983 ps
CPU time 555.42 seconds
Started Jan 17 03:09:46 PM PST 24
Finished Jan 17 03:19:02 PM PST 24
Peak memory 191116 kb
Host smart-6bb9fa59-c24f-41ea-87f6-a1231a056322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885136740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3885136740
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.1680125182
Short name T248
Test name
Test status
Simulation time 364436298238 ps
CPU time 370.05 seconds
Started Jan 17 03:09:43 PM PST 24
Finished Jan 17 03:15:54 PM PST 24
Peak memory 205764 kb
Host smart-fcea0acc-b6c9-4ca7-b763-aa56f6124911
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680125182 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.1680125182
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.975188483
Short name T608
Test name
Test status
Simulation time 412414134284 ps
CPU time 122.43 seconds
Started Jan 17 03:09:53 PM PST 24
Finished Jan 17 03:12:00 PM PST 24
Peak memory 182960 kb
Host smart-4998c186-57d4-4ac2-90a9-7b6000fe64a0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975188483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.rv_timer_cfg_update_on_fly.975188483
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.2663855089
Short name T579
Test name
Test status
Simulation time 300397697678 ps
CPU time 173.47 seconds
Started Jan 17 03:09:46 PM PST 24
Finished Jan 17 03:12:40 PM PST 24
Peak memory 182908 kb
Host smart-57faf9a2-ea03-4241-bad3-bc9111698997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663855089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.2663855089
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.408732602
Short name T198
Test name
Test status
Simulation time 114369362785 ps
CPU time 223.92 seconds
Started Jan 17 03:09:45 PM PST 24
Finished Jan 17 03:13:30 PM PST 24
Peak memory 191204 kb
Host smart-a3fad9bc-2eca-406c-aab0-b97e3a66ac1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408732602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.408732602
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1223672804
Short name T606
Test name
Test status
Simulation time 1155856849 ps
CPU time 1.18 seconds
Started Jan 17 03:09:53 PM PST 24
Finished Jan 17 03:09:59 PM PST 24
Peak memory 182872 kb
Host smart-cb7204f0-08b9-4e38-a6fb-fa7f61106b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223672804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1223672804
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1431112381
Short name T533
Test name
Test status
Simulation time 688228737250 ps
CPU time 195.02 seconds
Started Jan 17 03:09:52 PM PST 24
Finished Jan 17 03:13:12 PM PST 24
Peak memory 194176 kb
Host smart-d647843f-50f0-4a6c-be5d-b9d7b32dcde4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431112381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1431112381
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.2295849794
Short name T515
Test name
Test status
Simulation time 60603157389 ps
CPU time 396.5 seconds
Started Jan 17 03:09:55 PM PST 24
Finished Jan 17 03:16:34 PM PST 24
Peak memory 205848 kb
Host smart-58e3075b-9e13-4436-8231-271fd00e11f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295849794 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.2295849794
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2685649026
Short name T567
Test name
Test status
Simulation time 126598899245 ps
CPU time 110.73 seconds
Started Jan 17 03:07:42 PM PST 24
Finished Jan 17 03:09:34 PM PST 24
Peak memory 182884 kb
Host smart-8fe3fd15-db03-4fef-a018-b81012a69a91
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685649026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.2685649026
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.1591862252
Short name T551
Test name
Test status
Simulation time 298819903986 ps
CPU time 222.81 seconds
Started Jan 17 03:07:41 PM PST 24
Finished Jan 17 03:11:24 PM PST 24
Peak memory 182944 kb
Host smart-79306ae9-aba1-4213-b8c4-d0ce70591dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591862252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1591862252
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.3864164327
Short name T21
Test name
Test status
Simulation time 12039596474 ps
CPU time 21.07 seconds
Started Jan 17 03:07:40 PM PST 24
Finished Jan 17 03:08:01 PM PST 24
Peak memory 182988 kb
Host smart-4b7f7e68-df17-4cb5-a61d-fc6dd91abc8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864164327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3864164327
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3865147674
Short name T269
Test name
Test status
Simulation time 173819059641 ps
CPU time 121.27 seconds
Started Jan 17 03:07:42 PM PST 24
Finished Jan 17 03:09:44 PM PST 24
Peak memory 191068 kb
Host smart-a453a636-6b8a-4d51-b18b-1c266c3101d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865147674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3865147674
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2510472977
Short name T17
Test name
Test status
Simulation time 331986972 ps
CPU time 0.92 seconds
Started Jan 17 03:07:42 PM PST 24
Finished Jan 17 03:07:44 PM PST 24
Peak memory 213976 kb
Host smart-04a11531-f9dc-4289-a782-90bc14b42ed9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510472977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2510472977
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1409713156
Short name T143
Test name
Test status
Simulation time 976004207671 ps
CPU time 360.82 seconds
Started Jan 17 03:07:38 PM PST 24
Finished Jan 17 03:13:39 PM PST 24
Peak memory 191116 kb
Host smart-91cb078a-922b-47f4-bd82-280bf82da7ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409713156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1409713156
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.667679793
Short name T494
Test name
Test status
Simulation time 135952799128 ps
CPU time 2544.13 seconds
Started Jan 17 03:07:38 PM PST 24
Finished Jan 17 03:50:03 PM PST 24
Peak memory 210232 kb
Host smart-37e69576-08bf-49a6-8c5a-f20c19c18776
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667679793 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.667679793
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3364259365
Short name T605
Test name
Test status
Simulation time 354411085511 ps
CPU time 217.51 seconds
Started Jan 17 03:10:00 PM PST 24
Finished Jan 17 03:13:38 PM PST 24
Peak memory 182976 kb
Host smart-a56a4e08-9fa5-4396-9016-a9ccf44a97fe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364259365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3364259365
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.3461065595
Short name T552
Test name
Test status
Simulation time 73105240101 ps
CPU time 116.95 seconds
Started Jan 17 03:10:00 PM PST 24
Finished Jan 17 03:11:58 PM PST 24
Peak memory 182896 kb
Host smart-7d274fc6-ad84-4a47-81c8-0d3e7cae5fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461065595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.3461065595
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3123387118
Short name T291
Test name
Test status
Simulation time 157856559221 ps
CPU time 429.37 seconds
Started Jan 17 03:09:57 PM PST 24
Finished Jan 17 03:17:07 PM PST 24
Peak memory 193964 kb
Host smart-9c460e4f-b03f-4a67-babe-1a95b0a4eff4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123387118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3123387118
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.2777202301
Short name T604
Test name
Test status
Simulation time 33105153 ps
CPU time 0.61 seconds
Started Jan 17 03:10:03 PM PST 24
Finished Jan 17 03:10:04 PM PST 24
Peak memory 182388 kb
Host smart-813699ef-a19c-437e-af9d-4d330484928f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777202301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.2777202301
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.368536944
Short name T3
Test name
Test status
Simulation time 165257247916 ps
CPU time 270.88 seconds
Started Jan 17 03:10:03 PM PST 24
Finished Jan 17 03:14:34 PM PST 24
Peak memory 191156 kb
Host smart-bc67befc-d599-4a37-91c0-8ffe55d5ca05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368536944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.
368536944
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.2165931976
Short name T11
Test name
Test status
Simulation time 76830342146 ps
CPU time 574.91 seconds
Started Jan 17 03:10:05 PM PST 24
Finished Jan 17 03:19:41 PM PST 24
Peak memory 205960 kb
Host smart-5e5cd2b6-45f5-4e37-99cd-d9d9dfee09bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165931976 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.2165931976
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3222379642
Short name T150
Test name
Test status
Simulation time 393130230990 ps
CPU time 647.63 seconds
Started Jan 17 03:10:12 PM PST 24
Finished Jan 17 03:21:04 PM PST 24
Peak memory 182976 kb
Host smart-c85ebb23-5afe-4cbd-b292-cab4becd8404
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222379642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3222379642
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.1611706772
Short name T500
Test name
Test status
Simulation time 742396940631 ps
CPU time 175.3 seconds
Started Jan 17 03:10:03 PM PST 24
Finished Jan 17 03:12:58 PM PST 24
Peak memory 182952 kb
Host smart-4458765b-57f4-43b4-8723-1341d9d666aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611706772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1611706772
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.2995352660
Short name T276
Test name
Test status
Simulation time 305923259457 ps
CPU time 205.99 seconds
Started Jan 17 03:10:05 PM PST 24
Finished Jan 17 03:13:32 PM PST 24
Peak memory 191184 kb
Host smart-c470fa77-fb3e-4080-a347-e9fe5044b70c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995352660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2995352660
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.633067373
Short name T239
Test name
Test status
Simulation time 293689302160 ps
CPU time 158.46 seconds
Started Jan 17 03:10:10 PM PST 24
Finished Jan 17 03:12:49 PM PST 24
Peak memory 191156 kb
Host smart-511a9637-bdf8-4797-80e8-48429e88bc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633067373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.633067373
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2163822395
Short name T501
Test name
Test status
Simulation time 60844435090 ps
CPU time 47.02 seconds
Started Jan 17 03:10:11 PM PST 24
Finished Jan 17 03:11:03 PM PST 24
Peak memory 183020 kb
Host smart-d9f23358-2426-4838-b6ea-c29ff2690634
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163822395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2163822395
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.3340473730
Short name T530
Test name
Test status
Simulation time 85692111572 ps
CPU time 639.9 seconds
Started Jan 17 03:10:10 PM PST 24
Finished Jan 17 03:20:50 PM PST 24
Peak memory 206244 kb
Host smart-20888d23-f801-4897-8202-b8465f7f20c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340473730 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.3340473730
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.441786956
Short name T197
Test name
Test status
Simulation time 959894504199 ps
CPU time 542.86 seconds
Started Jan 17 03:10:14 PM PST 24
Finished Jan 17 03:19:19 PM PST 24
Peak memory 182972 kb
Host smart-24a286fe-cabb-440f-b18f-a1f391ea3dcd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441786956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.441786956
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.3418102542
Short name T502
Test name
Test status
Simulation time 157685924982 ps
CPU time 264.97 seconds
Started Jan 17 03:10:12 PM PST 24
Finished Jan 17 03:14:42 PM PST 24
Peak memory 182896 kb
Host smart-40839353-c072-4ee3-9e67-308191edb069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418102542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3418102542
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.4196136224
Short name T194
Test name
Test status
Simulation time 71660017305 ps
CPU time 303.96 seconds
Started Jan 17 03:10:11 PM PST 24
Finished Jan 17 03:15:21 PM PST 24
Peak memory 192140 kb
Host smart-51f393ef-9aa0-4f7a-aee3-78d144361059
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196136224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.4196136224
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.2721164333
Short name T232
Test name
Test status
Simulation time 416586752216 ps
CPU time 1495.6 seconds
Started Jan 17 03:10:24 PM PST 24
Finished Jan 17 03:35:20 PM PST 24
Peak memory 205864 kb
Host smart-d7931c5b-c522-4cf7-a944-14099f07d085
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721164333 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.2721164333
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.4206186709
Short name T601
Test name
Test status
Simulation time 10472222308 ps
CPU time 16.12 seconds
Started Jan 17 03:10:29 PM PST 24
Finished Jan 17 03:10:46 PM PST 24
Peak memory 182976 kb
Host smart-2599fa63-5e95-4edb-94ef-af5fe795e4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206186709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.4206186709
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.3304070938
Short name T133
Test name
Test status
Simulation time 72630806545 ps
CPU time 68.9 seconds
Started Jan 17 03:10:27 PM PST 24
Finished Jan 17 03:11:36 PM PST 24
Peak memory 182992 kb
Host smart-061995b3-b16b-497b-81c5-9e8a9e26c7b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304070938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3304070938
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.2355820861
Short name T257
Test name
Test status
Simulation time 52381050423 ps
CPU time 112.58 seconds
Started Jan 17 03:10:29 PM PST 24
Finished Jan 17 03:12:22 PM PST 24
Peak memory 193148 kb
Host smart-0a5f0866-dca7-4e02-9eb2-b5be9f8e610e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355820861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2355820861
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.228689357
Short name T600
Test name
Test status
Simulation time 329648228572 ps
CPU time 138.7 seconds
Started Jan 17 03:10:31 PM PST 24
Finished Jan 17 03:12:50 PM PST 24
Peak memory 194320 kb
Host smart-4fd4853e-075c-49bb-a8dc-37f5b9e6a169
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228689357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
228689357
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.3818237707
Short name T255
Test name
Test status
Simulation time 25873590572 ps
CPU time 289.1 seconds
Started Jan 17 03:10:29 PM PST 24
Finished Jan 17 03:15:18 PM PST 24
Peak memory 197628 kb
Host smart-15a573d1-0143-4b96-9dce-8cbc2660eec7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818237707 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.3818237707
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3765111834
Short name T229
Test name
Test status
Simulation time 562712038572 ps
CPU time 569.19 seconds
Started Jan 17 03:10:41 PM PST 24
Finished Jan 17 03:20:11 PM PST 24
Peak memory 182928 kb
Host smart-3ba5fe82-087d-45dd-b21a-23782b452c62
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765111834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3765111834
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.4276685566
Short name T493
Test name
Test status
Simulation time 310478143168 ps
CPU time 162.73 seconds
Started Jan 17 03:10:39 PM PST 24
Finished Jan 17 03:13:22 PM PST 24
Peak memory 182944 kb
Host smart-eabce44f-2165-49df-ba08-ce11729c4cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276685566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.4276685566
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1944195510
Short name T522
Test name
Test status
Simulation time 79250978918 ps
CPU time 79.28 seconds
Started Jan 17 03:10:37 PM PST 24
Finished Jan 17 03:11:56 PM PST 24
Peak memory 182948 kb
Host smart-ff64d323-f561-43f8-bdfa-ae77f98b8a21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944195510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1944195510
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.2526706972
Short name T313
Test name
Test status
Simulation time 53509209538 ps
CPU time 353.75 seconds
Started Jan 17 03:10:39 PM PST 24
Finished Jan 17 03:16:34 PM PST 24
Peak memory 191196 kb
Host smart-95ed1884-0ee8-47d5-adce-dbe97536be6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526706972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2526706972
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1878946975
Short name T279
Test name
Test status
Simulation time 1676906627088 ps
CPU time 1884.31 seconds
Started Jan 17 03:10:39 PM PST 24
Finished Jan 17 03:42:04 PM PST 24
Peak memory 191312 kb
Host smart-320c8549-645d-4dca-88be-d38d260ae829
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878946975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1878946975
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.363195329
Short name T479
Test name
Test status
Simulation time 19033950224 ps
CPU time 226.78 seconds
Started Jan 17 03:10:41 PM PST 24
Finished Jan 17 03:14:28 PM PST 24
Peak memory 197716 kb
Host smart-f5ac5ece-b17e-4607-b5ea-9bf7e8e58942
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363195329 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.363195329
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1064258559
Short name T343
Test name
Test status
Simulation time 160512227146 ps
CPU time 308.84 seconds
Started Jan 17 03:10:49 PM PST 24
Finished Jan 17 03:15:58 PM PST 24
Peak memory 182956 kb
Host smart-ff637cdd-77d6-4961-b996-712afce36bd8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064258559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1064258559
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.3913257373
Short name T587
Test name
Test status
Simulation time 710724553172 ps
CPU time 138.9 seconds
Started Jan 17 03:10:46 PM PST 24
Finished Jan 17 03:13:06 PM PST 24
Peak memory 182940 kb
Host smart-56a9a364-bc96-4bd0-b183-f2ff7ab01600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913257373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3913257373
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.560767106
Short name T103
Test name
Test status
Simulation time 784243115590 ps
CPU time 1329.88 seconds
Started Jan 17 03:10:42 PM PST 24
Finished Jan 17 03:32:52 PM PST 24
Peak memory 191140 kb
Host smart-edf5ead4-3909-4e88-b4fe-ec5eae042e51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560767106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.560767106
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.851076972
Short name T348
Test name
Test status
Simulation time 53557767993 ps
CPU time 50.7 seconds
Started Jan 17 03:10:46 PM PST 24
Finished Jan 17 03:11:38 PM PST 24
Peak memory 191872 kb
Host smart-1ae5748c-b176-4205-ba7d-c09276d27b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851076972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.851076972
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2997600566
Short name T596
Test name
Test status
Simulation time 406720525444 ps
CPU time 1058.11 seconds
Started Jan 17 03:10:47 PM PST 24
Finished Jan 17 03:28:26 PM PST 24
Peak memory 191284 kb
Host smart-b330f405-5a6c-431c-a4b1-fad6d3e4f0c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997600566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2997600566
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.237492503
Short name T572
Test name
Test status
Simulation time 292969821669 ps
CPU time 619.92 seconds
Started Jan 17 03:10:46 PM PST 24
Finished Jan 17 03:21:07 PM PST 24
Peak memory 213328 kb
Host smart-f62d4e8a-e56b-4688-a686-e497ae48e723
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237492503 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.237492503
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2015762319
Short name T578
Test name
Test status
Simulation time 6313747466 ps
CPU time 11.8 seconds
Started Jan 17 03:10:47 PM PST 24
Finished Jan 17 03:11:00 PM PST 24
Peak memory 182896 kb
Host smart-f9588edb-6243-4479-b4b8-42b4abe1bb11
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015762319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.2015762319
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.2312653278
Short name T544
Test name
Test status
Simulation time 729235129526 ps
CPU time 328.88 seconds
Started Jan 17 03:10:48 PM PST 24
Finished Jan 17 03:16:18 PM PST 24
Peak memory 182992 kb
Host smart-b2717ca1-1357-45d2-a559-b80186266325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312653278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2312653278
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3466103331
Short name T570
Test name
Test status
Simulation time 77076326403 ps
CPU time 69.16 seconds
Started Jan 17 03:10:46 PM PST 24
Finished Jan 17 03:11:56 PM PST 24
Peak memory 194456 kb
Host smart-bc86dd3c-599c-42d8-9e94-d6f327b54c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466103331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3466103331
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.2982398436
Short name T292
Test name
Test status
Simulation time 68763201476 ps
CPU time 519.4 seconds
Started Jan 17 03:10:59 PM PST 24
Finished Jan 17 03:19:39 PM PST 24
Peak memory 205852 kb
Host smart-411ef393-ee3a-48b1-97e0-a09493cb804f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982398436 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.2982398436
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1175200297
Short name T283
Test name
Test status
Simulation time 686671925785 ps
CPU time 632.01 seconds
Started Jan 17 03:11:13 PM PST 24
Finished Jan 17 03:21:48 PM PST 24
Peak memory 182968 kb
Host smart-db4be7f6-a38a-4771-91eb-3d78a550c133
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175200297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1175200297
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.886699690
Short name T359
Test name
Test status
Simulation time 802115833207 ps
CPU time 204.26 seconds
Started Jan 17 03:11:04 PM PST 24
Finished Jan 17 03:14:29 PM PST 24
Peak memory 182928 kb
Host smart-3f07b6e2-8e45-48aa-a5ca-a961c267d50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886699690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.886699690
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.1302287224
Short name T274
Test name
Test status
Simulation time 1655861564073 ps
CPU time 607.44 seconds
Started Jan 17 03:11:06 PM PST 24
Finished Jan 17 03:21:15 PM PST 24
Peak memory 190856 kb
Host smart-481e1a4f-ec44-4729-a05a-abcc3e377a7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302287224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.1302287224
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3390342715
Short name T349
Test name
Test status
Simulation time 19902461947 ps
CPU time 34.84 seconds
Started Jan 17 03:11:13 PM PST 24
Finished Jan 17 03:11:50 PM PST 24
Peak memory 182636 kb
Host smart-9b9360f1-2e60-407e-93c8-e9cad62a4762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390342715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3390342715
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1556472776
Short name T117
Test name
Test status
Simulation time 314633097164 ps
CPU time 575.89 seconds
Started Jan 17 03:11:15 PM PST 24
Finished Jan 17 03:20:52 PM PST 24
Peak memory 191084 kb
Host smart-4d192201-37f6-4739-b14f-b98504eb38cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556472776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1556472776
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.1035768016
Short name T356
Test name
Test status
Simulation time 303747447431 ps
CPU time 349.99 seconds
Started Jan 17 03:11:12 PM PST 24
Finished Jan 17 03:17:06 PM PST 24
Peak memory 208292 kb
Host smart-88416b02-e2cd-4fb1-8e7a-1ed64c90233f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035768016 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.1035768016
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.2631928847
Short name T179
Test name
Test status
Simulation time 2900062573163 ps
CPU time 1007.95 seconds
Started Jan 17 03:11:15 PM PST 24
Finished Jan 17 03:28:04 PM PST 24
Peak memory 182956 kb
Host smart-5e886423-ff74-4e92-90c5-81aec013e533
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631928847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.2631928847
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.453589309
Short name T542
Test name
Test status
Simulation time 930662040079 ps
CPU time 129.93 seconds
Started Jan 17 03:11:17 PM PST 24
Finished Jan 17 03:13:27 PM PST 24
Peak memory 182844 kb
Host smart-616ed23d-0137-4fc3-a596-6a7891c1cd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453589309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.453589309
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.636303420
Short name T173
Test name
Test status
Simulation time 129707395727 ps
CPU time 352.99 seconds
Started Jan 17 03:11:14 PM PST 24
Finished Jan 17 03:17:09 PM PST 24
Peak memory 190752 kb
Host smart-65e22e68-4fdb-4ce2-83dc-6f2f7023b256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636303420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.636303420
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3718986346
Short name T237
Test name
Test status
Simulation time 53910378071 ps
CPU time 157.22 seconds
Started Jan 17 03:11:17 PM PST 24
Finished Jan 17 03:13:55 PM PST 24
Peak memory 183012 kb
Host smart-bfa861fd-69cf-41d0-876d-50694e5d9e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718986346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3718986346
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.201329421
Short name T525
Test name
Test status
Simulation time 187636655 ps
CPU time 0.65 seconds
Started Jan 17 03:11:18 PM PST 24
Finished Jan 17 03:11:19 PM PST 24
Peak memory 182744 kb
Host smart-e431c490-23d5-48dd-afe0-eb8730d08351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201329421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.
201329421
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.660648370
Short name T34
Test name
Test status
Simulation time 342431228756 ps
CPU time 212.22 seconds
Started Jan 17 03:11:15 PM PST 24
Finished Jan 17 03:14:48 PM PST 24
Peak memory 205820 kb
Host smart-b13e592a-9519-47a8-b212-005de1a2cf19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660648370 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.660648370
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.668534159
Short name T105
Test name
Test status
Simulation time 1433779318598 ps
CPU time 907.12 seconds
Started Jan 17 03:11:22 PM PST 24
Finished Jan 17 03:26:31 PM PST 24
Peak memory 182964 kb
Host smart-98dc9089-73ab-4cc4-aa62-3447b86ddbab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668534159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.rv_timer_cfg_update_on_fly.668534159
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.2754972155
Short name T498
Test name
Test status
Simulation time 26988505442 ps
CPU time 37.34 seconds
Started Jan 17 03:11:23 PM PST 24
Finished Jan 17 03:12:01 PM PST 24
Peak memory 182976 kb
Host smart-f3bba67c-62d2-4b2a-8677-4d2455d19153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754972155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.2754972155
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.805725850
Short name T245
Test name
Test status
Simulation time 69722659228 ps
CPU time 112.1 seconds
Started Jan 17 03:11:18 PM PST 24
Finished Jan 17 03:13:11 PM PST 24
Peak memory 191144 kb
Host smart-9ab5e34b-2be8-414b-b7a9-0bdfa18191dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805725850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.805725850
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.734233483
Short name T491
Test name
Test status
Simulation time 157387885 ps
CPU time 1 seconds
Started Jan 17 03:11:24 PM PST 24
Finished Jan 17 03:11:25 PM PST 24
Peak memory 191352 kb
Host smart-89ab0536-057e-4ca8-822a-282cd9127184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734233483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.734233483
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.3486282191
Short name T486
Test name
Test status
Simulation time 597391358086 ps
CPU time 294.5 seconds
Started Jan 17 03:11:21 PM PST 24
Finished Jan 17 03:16:17 PM PST 24
Peak memory 195388 kb
Host smart-6a1627e9-b13a-4308-a5a9-cac0ae1d0f5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486282191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.3486282191
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.444949623
Short name T592
Test name
Test status
Simulation time 60119035470 ps
CPU time 512.02 seconds
Started Jan 17 03:11:23 PM PST 24
Finished Jan 17 03:19:56 PM PST 24
Peak memory 205916 kb
Host smart-a67e08b5-6fb6-4890-94c2-0722fb636624
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444949623 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.444949623
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.2371871305
Short name T341
Test name
Test status
Simulation time 17601068798 ps
CPU time 16.4 seconds
Started Jan 17 03:07:40 PM PST 24
Finished Jan 17 03:07:57 PM PST 24
Peak memory 182952 kb
Host smart-2efd8117-5e6c-47d3-a0e3-5a20153116e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371871305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.2371871305
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.2860449148
Short name T569
Test name
Test status
Simulation time 125087157595 ps
CPU time 165.13 seconds
Started Jan 17 03:07:42 PM PST 24
Finished Jan 17 03:10:28 PM PST 24
Peak memory 182896 kb
Host smart-dfb34e84-2f1b-4e06-b31f-d7101c7cc96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860449148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2860449148
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.1258058833
Short name T510
Test name
Test status
Simulation time 1887020616 ps
CPU time 2.99 seconds
Started Jan 17 03:07:40 PM PST 24
Finished Jan 17 03:07:44 PM PST 24
Peak memory 194332 kb
Host smart-b24b081c-122d-49eb-ac59-e3bbd4427982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258058833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1258058833
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.3577883006
Short name T577
Test name
Test status
Simulation time 6754001653 ps
CPU time 50.72 seconds
Started Jan 17 03:07:40 PM PST 24
Finished Jan 17 03:08:31 PM PST 24
Peak memory 197636 kb
Host smart-32a3ef26-6b2b-42c1-bf7a-f356f4693e03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577883006 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.3577883006
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.2568011384
Short name T339
Test name
Test status
Simulation time 56122279554 ps
CPU time 91.04 seconds
Started Jan 17 03:11:24 PM PST 24
Finished Jan 17 03:12:55 PM PST 24
Peak memory 191136 kb
Host smart-3abe6af2-8f9b-4d0f-a71f-c489720d34fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568011384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2568011384
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.2810703562
Short name T616
Test name
Test status
Simulation time 45885322487 ps
CPU time 1448.78 seconds
Started Jan 17 03:11:28 PM PST 24
Finished Jan 17 03:35:38 PM PST 24
Peak memory 191200 kb
Host smart-875254d9-339f-4549-b91b-abb60c14b7e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810703562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2810703562
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1923566910
Short name T297
Test name
Test status
Simulation time 153607980357 ps
CPU time 241.2 seconds
Started Jan 17 03:11:29 PM PST 24
Finished Jan 17 03:15:31 PM PST 24
Peak memory 191156 kb
Host smart-20868c78-d541-4fb2-b442-b183525f58ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923566910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1923566910
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.1503127048
Short name T102
Test name
Test status
Simulation time 519708067654 ps
CPU time 886.11 seconds
Started Jan 17 03:11:28 PM PST 24
Finished Jan 17 03:26:15 PM PST 24
Peak memory 191188 kb
Host smart-ab3d215e-7e14-4cc0-8f17-818dae003dcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503127048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1503127048
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.272796146
Short name T99
Test name
Test status
Simulation time 79831809447 ps
CPU time 396.27 seconds
Started Jan 17 03:11:29 PM PST 24
Finished Jan 17 03:18:06 PM PST 24
Peak memory 191128 kb
Host smart-fb862b84-31f5-4ccd-ad6b-54c2541adebc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272796146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.272796146
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.303898908
Short name T144
Test name
Test status
Simulation time 63095679136 ps
CPU time 148.43 seconds
Started Jan 17 03:11:28 PM PST 24
Finished Jan 17 03:13:57 PM PST 24
Peak memory 191148 kb
Host smart-3c03f602-1006-412a-870a-fcb84b0bddef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303898908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.303898908
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1096766574
Short name T603
Test name
Test status
Simulation time 29140762731 ps
CPU time 137.65 seconds
Started Jan 17 03:11:30 PM PST 24
Finished Jan 17 03:13:48 PM PST 24
Peak memory 191260 kb
Host smart-4e923c11-77a6-4295-bb09-8872226ae286
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096766574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1096766574
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.4131108853
Short name T141
Test name
Test status
Simulation time 51261481906 ps
CPU time 71.18 seconds
Started Jan 17 03:11:32 PM PST 24
Finished Jan 17 03:12:44 PM PST 24
Peak memory 182852 kb
Host smart-33a5430c-feb4-41f1-bb4c-a24f1ce46b74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131108853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.4131108853
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2288617164
Short name T595
Test name
Test status
Simulation time 438467417297 ps
CPU time 253.18 seconds
Started Jan 17 03:11:32 PM PST 24
Finished Jan 17 03:15:46 PM PST 24
Peak memory 192160 kb
Host smart-e886a954-aabe-4a20-8374-fc0858307372
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288617164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2288617164
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1823359077
Short name T508
Test name
Test status
Simulation time 69115261105 ps
CPU time 120.46 seconds
Started Jan 17 03:07:51 PM PST 24
Finished Jan 17 03:09:52 PM PST 24
Peak memory 182940 kb
Host smart-225af130-9a89-44e7-94be-e1bfbcd11246
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823359077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1823359077
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.1637337768
Short name T497
Test name
Test status
Simulation time 154810066301 ps
CPU time 244.23 seconds
Started Jan 17 03:07:38 PM PST 24
Finished Jan 17 03:11:43 PM PST 24
Peak memory 183036 kb
Host smart-b613ea8e-5323-4b2b-ab65-a4ce29ba54cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637337768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1637337768
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.1885995580
Short name T316
Test name
Test status
Simulation time 349467399 ps
CPU time 1.7 seconds
Started Jan 17 03:07:39 PM PST 24
Finished Jan 17 03:07:41 PM PST 24
Peak memory 182876 kb
Host smart-35a2bc95-a8eb-4e2f-a7cf-6ab5e79cb4bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885995580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1885995580
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2645897999
Short name T488
Test name
Test status
Simulation time 26946434 ps
CPU time 0.55 seconds
Started Jan 17 03:07:52 PM PST 24
Finished Jan 17 03:07:53 PM PST 24
Peak memory 182368 kb
Host smart-658039f4-3c38-4636-b176-0e9c8b1d6b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645897999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2645897999
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.832191548
Short name T193
Test name
Test status
Simulation time 88882190807 ps
CPU time 130.48 seconds
Started Jan 17 03:07:51 PM PST 24
Finished Jan 17 03:10:03 PM PST 24
Peak memory 191212 kb
Host smart-1ce330f3-5c9e-4c12-ae0d-cdf816bb5de7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832191548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.832191548
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.160591475
Short name T311
Test name
Test status
Simulation time 131079283429 ps
CPU time 812.51 seconds
Started Jan 17 03:07:48 PM PST 24
Finished Jan 17 03:21:21 PM PST 24
Peak memory 208776 kb
Host smart-25d159b7-ec58-4697-a640-b2cd53b6398e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160591475 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.160591475
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.3015770897
Short name T88
Test name
Test status
Simulation time 399309145425 ps
CPU time 399.5 seconds
Started Jan 17 03:11:39 PM PST 24
Finished Jan 17 03:18:20 PM PST 24
Peak memory 191184 kb
Host smart-b0bc6745-62e4-4457-bb3c-afa57bca5dfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015770897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3015770897
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.388540128
Short name T221
Test name
Test status
Simulation time 26090660962 ps
CPU time 48.08 seconds
Started Jan 17 03:11:39 PM PST 24
Finished Jan 17 03:12:28 PM PST 24
Peak memory 191244 kb
Host smart-70486c71-b8fa-45c4-934e-4f6c49a8b5d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388540128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.388540128
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.543298310
Short name T594
Test name
Test status
Simulation time 30977721154 ps
CPU time 24.42 seconds
Started Jan 17 03:11:40 PM PST 24
Finished Jan 17 03:12:05 PM PST 24
Peak memory 183000 kb
Host smart-2b378b00-2911-4b44-a03e-37fbe8958759
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543298310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.543298310
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.2784397780
Short name T258
Test name
Test status
Simulation time 358342187849 ps
CPU time 242.11 seconds
Started Jan 17 03:11:38 PM PST 24
Finished Jan 17 03:15:41 PM PST 24
Peak memory 183004 kb
Host smart-62a8d444-5a7d-46a3-b5a5-7210217534f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784397780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2784397780
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.432975539
Short name T249
Test name
Test status
Simulation time 2989840764097 ps
CPU time 1220.27 seconds
Started Jan 17 03:11:41 PM PST 24
Finished Jan 17 03:32:02 PM PST 24
Peak memory 191156 kb
Host smart-8533381a-9438-43be-a404-4e65ec6a695b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432975539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.432975539
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.3990695402
Short name T325
Test name
Test status
Simulation time 78489000263 ps
CPU time 1604.54 seconds
Started Jan 17 03:11:41 PM PST 24
Finished Jan 17 03:38:26 PM PST 24
Peak memory 191156 kb
Host smart-b5b94f5b-08a4-46d9-ae9a-bd2cf5652f2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990695402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.3990695402
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1408978449
Short name T301
Test name
Test status
Simulation time 202501312187 ps
CPU time 98.27 seconds
Started Jan 17 03:11:43 PM PST 24
Finished Jan 17 03:13:21 PM PST 24
Peak memory 182880 kb
Host smart-3c793b97-96fe-4755-b86a-ad7093b937ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408978449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1408978449
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2598039525
Short name T191
Test name
Test status
Simulation time 376489491241 ps
CPU time 117.59 seconds
Started Jan 17 03:11:42 PM PST 24
Finished Jan 17 03:13:41 PM PST 24
Peak memory 191188 kb
Host smart-785b2c84-da9a-4a19-a3fb-04a4c5c27d2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598039525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2598039525
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3771486335
Short name T528
Test name
Test status
Simulation time 754356430606 ps
CPU time 213 seconds
Started Jan 17 03:07:51 PM PST 24
Finished Jan 17 03:11:25 PM PST 24
Peak memory 182916 kb
Host smart-3a9303f7-644e-4ab9-bf7e-879d670cce80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771486335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3771486335
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.532858053
Short name T151
Test name
Test status
Simulation time 197203630925 ps
CPU time 310.35 seconds
Started Jan 17 03:07:45 PM PST 24
Finished Jan 17 03:12:56 PM PST 24
Peak memory 191132 kb
Host smart-6fe47058-7b71-4f2d-9f41-ff05d1973c32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532858053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.532858053
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2333822035
Short name T490
Test name
Test status
Simulation time 32940862645 ps
CPU time 18.6 seconds
Started Jan 17 03:07:49 PM PST 24
Finished Jan 17 03:08:08 PM PST 24
Peak memory 194612 kb
Host smart-21a7fafd-fdf8-47b1-8829-50566b657533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333822035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2333822035
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.3092823517
Short name T300
Test name
Test status
Simulation time 462785871555 ps
CPU time 205.49 seconds
Started Jan 17 03:07:48 PM PST 24
Finished Jan 17 03:11:14 PM PST 24
Peak memory 191080 kb
Host smart-b05864e2-faa8-4bde-8031-c364705afc0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092823517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
3092823517
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.1875799525
Short name T260
Test name
Test status
Simulation time 262087443338 ps
CPU time 569.5 seconds
Started Jan 17 03:07:47 PM PST 24
Finished Jan 17 03:17:17 PM PST 24
Peak memory 212252 kb
Host smart-cac9dec8-d32c-49eb-8b5e-e143dc152668
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875799525 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.1875799525
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.1675990206
Short name T234
Test name
Test status
Simulation time 652995174101 ps
CPU time 344 seconds
Started Jan 17 03:11:45 PM PST 24
Finished Jan 17 03:17:29 PM PST 24
Peak memory 191192 kb
Host smart-96869215-371e-4a62-a079-6a1928b8ef87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675990206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.1675990206
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.214869324
Short name T125
Test name
Test status
Simulation time 104378275678 ps
CPU time 631.33 seconds
Started Jan 17 03:11:44 PM PST 24
Finished Jan 17 03:22:16 PM PST 24
Peak memory 191216 kb
Host smart-bba81c36-4380-4ccb-903c-2d262dd3c53e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214869324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.214869324
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.448019328
Short name T45
Test name
Test status
Simulation time 71399525805 ps
CPU time 226.1 seconds
Started Jan 17 03:11:43 PM PST 24
Finished Jan 17 03:15:29 PM PST 24
Peak memory 193740 kb
Host smart-df074a3e-c79d-4bda-912d-1b952614846f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448019328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.448019328
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3719785572
Short name T190
Test name
Test status
Simulation time 41875216741 ps
CPU time 208.57 seconds
Started Jan 17 03:11:47 PM PST 24
Finished Jan 17 03:15:16 PM PST 24
Peak memory 182984 kb
Host smart-384ddc6c-cf8f-4c04-9ba1-5779d7ccf5a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719785572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3719785572
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.978964802
Short name T284
Test name
Test status
Simulation time 97516008474 ps
CPU time 164.93 seconds
Started Jan 17 03:11:50 PM PST 24
Finished Jan 17 03:14:35 PM PST 24
Peak memory 194048 kb
Host smart-13b85141-d6af-4744-9766-2c19ed061113
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978964802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.978964802
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.799511776
Short name T126
Test name
Test status
Simulation time 60307325656 ps
CPU time 68.96 seconds
Started Jan 17 03:12:01 PM PST 24
Finished Jan 17 03:13:10 PM PST 24
Peak memory 191196 kb
Host smart-b704feb3-df14-4ae1-ab58-0a93c827d49b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799511776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.799511776
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.331337243
Short name T215
Test name
Test status
Simulation time 351319796380 ps
CPU time 181.36 seconds
Started Jan 17 03:12:02 PM PST 24
Finished Jan 17 03:15:03 PM PST 24
Peak memory 191180 kb
Host smart-07950141-f6ca-4496-bf86-2c7d7747fb33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331337243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.331337243
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.4031932502
Short name T122
Test name
Test status
Simulation time 416415536383 ps
CPU time 198.9 seconds
Started Jan 17 03:12:02 PM PST 24
Finished Jan 17 03:15:21 PM PST 24
Peak memory 191428 kb
Host smart-b3437688-1abb-4d42-b3ef-70e353450dff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031932502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.4031932502
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2058838326
Short name T353
Test name
Test status
Simulation time 88563259220 ps
CPU time 36.33 seconds
Started Jan 17 03:12:00 PM PST 24
Finished Jan 17 03:12:37 PM PST 24
Peak memory 183004 kb
Host smart-55550209-d33b-41c7-bd7d-6e80dd70f20a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058838326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2058838326
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3430186695
Short name T204
Test name
Test status
Simulation time 304099240887 ps
CPU time 318.54 seconds
Started Jan 17 03:07:47 PM PST 24
Finished Jan 17 03:13:06 PM PST 24
Peak memory 182904 kb
Host smart-db882e64-bac3-4439-9ad9-8a7bd92400d3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430186695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3430186695
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2420577866
Short name T481
Test name
Test status
Simulation time 182385914498 ps
CPU time 67.14 seconds
Started Jan 17 03:07:51 PM PST 24
Finished Jan 17 03:08:59 PM PST 24
Peak memory 182932 kb
Host smart-297b3cd9-07ba-4ebd-91e5-eb97be2fcbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420577866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2420577866
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.2829324660
Short name T532
Test name
Test status
Simulation time 118072927674 ps
CPU time 178.29 seconds
Started Jan 17 03:07:53 PM PST 24
Finished Jan 17 03:10:54 PM PST 24
Peak memory 191128 kb
Host smart-2420d6f9-1659-4782-b74d-de1d726277ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829324660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2829324660
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1398295057
Short name T589
Test name
Test status
Simulation time 632757455 ps
CPU time 1.11 seconds
Started Jan 17 03:07:49 PM PST 24
Finished Jan 17 03:07:51 PM PST 24
Peak memory 182740 kb
Host smart-8ca904f1-61db-450f-b9be-2ceb012ebb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398295057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1398295057
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.2844023901
Short name T495
Test name
Test status
Simulation time 74804535417 ps
CPU time 567.81 seconds
Started Jan 17 03:07:51 PM PST 24
Finished Jan 17 03:17:20 PM PST 24
Peak memory 205868 kb
Host smart-8372ca72-0d42-4216-b21c-78fb88c8baff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844023901 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.2844023901
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.3789475637
Short name T529
Test name
Test status
Simulation time 18301505359 ps
CPU time 27.29 seconds
Started Jan 17 03:12:02 PM PST 24
Finished Jan 17 03:12:30 PM PST 24
Peak memory 183036 kb
Host smart-7a9ea9ad-2596-413f-8ef2-3598e5a71acf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789475637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3789475637
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.2760939985
Short name T285
Test name
Test status
Simulation time 79933330041 ps
CPU time 157.24 seconds
Started Jan 17 03:11:59 PM PST 24
Finished Jan 17 03:14:37 PM PST 24
Peak memory 191136 kb
Host smart-43643001-6278-46bc-a1fa-1c2be526c1cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760939985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2760939985
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.3218600251
Short name T186
Test name
Test status
Simulation time 238949150990 ps
CPU time 258.6 seconds
Started Jan 17 03:12:01 PM PST 24
Finished Jan 17 03:16:20 PM PST 24
Peak memory 193940 kb
Host smart-d6ee0ad7-87a6-4ed1-8ce5-f62871d55e91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218600251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3218600251
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.2766733526
Short name T199
Test name
Test status
Simulation time 212612832966 ps
CPU time 44.13 seconds
Started Jan 17 03:12:01 PM PST 24
Finished Jan 17 03:12:46 PM PST 24
Peak memory 191052 kb
Host smart-82acd3a0-d1c6-461a-b1b9-259c96138b60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766733526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.2766733526
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.3958210704
Short name T333
Test name
Test status
Simulation time 34243122907 ps
CPU time 30.01 seconds
Started Jan 17 03:11:59 PM PST 24
Finished Jan 17 03:12:30 PM PST 24
Peak memory 182904 kb
Host smart-eaeea433-a8a7-4f9b-bfee-5509708ddb47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958210704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3958210704
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.4245163998
Short name T328
Test name
Test status
Simulation time 508089432922 ps
CPU time 627.34 seconds
Started Jan 17 03:11:59 PM PST 24
Finished Jan 17 03:22:27 PM PST 24
Peak memory 191188 kb
Host smart-11264fc5-0cda-4cfa-91ab-dc6de906a2bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245163998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.4245163998
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3824621446
Short name T332
Test name
Test status
Simulation time 143868757314 ps
CPU time 646.99 seconds
Started Jan 17 03:12:05 PM PST 24
Finished Jan 17 03:22:53 PM PST 24
Peak memory 191120 kb
Host smart-ca610254-cf95-49a7-90b3-7581c11292d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824621446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3824621446
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.3897414655
Short name T107
Test name
Test status
Simulation time 687452183917 ps
CPU time 496.15 seconds
Started Jan 17 03:12:14 PM PST 24
Finished Jan 17 03:20:31 PM PST 24
Peak memory 191076 kb
Host smart-a513550b-c7a7-4aeb-961f-748226c8834e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897414655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3897414655
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.2369201279
Short name T268
Test name
Test status
Simulation time 25679228684 ps
CPU time 36.62 seconds
Started Jan 17 03:12:13 PM PST 24
Finished Jan 17 03:12:50 PM PST 24
Peak memory 183016 kb
Host smart-c39b8ea3-b392-4b46-8519-65ecea92461e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369201279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2369201279
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.938158650
Short name T585
Test name
Test status
Simulation time 317730019940 ps
CPU time 173.37 seconds
Started Jan 17 03:07:48 PM PST 24
Finished Jan 17 03:10:42 PM PST 24
Peak memory 182976 kb
Host smart-9a71512a-8943-40b8-8919-ae85b16c7c57
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938158650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.rv_timer_cfg_update_on_fly.938158650
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.3900605087
Short name T6
Test name
Test status
Simulation time 435277753793 ps
CPU time 59.01 seconds
Started Jan 17 03:07:47 PM PST 24
Finished Jan 17 03:08:47 PM PST 24
Peak memory 182864 kb
Host smart-ce3ce59e-104d-4853-bb08-e098daa2543d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900605087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.3900605087
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1822639233
Short name T526
Test name
Test status
Simulation time 286830698998 ps
CPU time 634.67 seconds
Started Jan 17 03:07:51 PM PST 24
Finished Jan 17 03:18:27 PM PST 24
Peak memory 182948 kb
Host smart-32fae8b3-476e-4eb5-b7e8-4b615872ab9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822639233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1822639233
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3708264765
Short name T147
Test name
Test status
Simulation time 2152493443012 ps
CPU time 1047.52 seconds
Started Jan 17 03:07:48 PM PST 24
Finished Jan 17 03:25:17 PM PST 24
Peak memory 191056 kb
Host smart-cc00b46e-29f9-4171-b438-5e9bfbd0f7e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708264765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3708264765
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/91.rv_timer_random.2269920329
Short name T281
Test name
Test status
Simulation time 146268368971 ps
CPU time 130.64 seconds
Started Jan 17 03:12:11 PM PST 24
Finished Jan 17 03:14:24 PM PST 24
Peak memory 182940 kb
Host smart-96097cbf-5b15-4d2f-a727-03efe00121d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269920329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2269920329
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.549287987
Short name T225
Test name
Test status
Simulation time 312335786344 ps
CPU time 158.98 seconds
Started Jan 17 03:12:17 PM PST 24
Finished Jan 17 03:14:57 PM PST 24
Peak memory 191188 kb
Host smart-b6d5938a-8f6f-480f-988b-98218ef710c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549287987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.549287987
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.2224834365
Short name T322
Test name
Test status
Simulation time 297236579900 ps
CPU time 173.29 seconds
Started Jan 17 03:12:15 PM PST 24
Finished Jan 17 03:15:09 PM PST 24
Peak memory 191220 kb
Host smart-5f3eb5ef-71bb-4bc0-ba32-91b167a3f5ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224834365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2224834365
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2740948303
Short name T303
Test name
Test status
Simulation time 64860037385 ps
CPU time 124.48 seconds
Started Jan 17 03:12:15 PM PST 24
Finished Jan 17 03:14:20 PM PST 24
Peak memory 191040 kb
Host smart-393ebb7f-2f7a-4113-8ba5-ec6996d4e8d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740948303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2740948303
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3007614486
Short name T289
Test name
Test status
Simulation time 347661743838 ps
CPU time 269.95 seconds
Started Jan 17 03:12:24 PM PST 24
Finished Jan 17 03:16:57 PM PST 24
Peak memory 191192 kb
Host smart-366ec3a2-212f-4535-8c82-5a51bee402a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007614486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3007614486
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.94392508
Short name T183
Test name
Test status
Simulation time 241200095422 ps
CPU time 181.97 seconds
Started Jan 17 03:12:23 PM PST 24
Finished Jan 17 03:15:29 PM PST 24
Peak memory 191160 kb
Host smart-d758743c-665c-4eb7-9d5a-cd8ec2be348c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94392508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.94392508
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2124886112
Short name T212
Test name
Test status
Simulation time 248978939218 ps
CPU time 1775.9 seconds
Started Jan 17 03:12:22 PM PST 24
Finished Jan 17 03:42:03 PM PST 24
Peak memory 194680 kb
Host smart-17f99cf7-0e34-480e-aedf-471fa4d36fc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124886112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2124886112
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3278979143
Short name T220
Test name
Test status
Simulation time 611237205690 ps
CPU time 383.29 seconds
Started Jan 17 03:12:24 PM PST 24
Finished Jan 17 03:18:51 PM PST 24
Peak memory 195316 kb
Host smart-b76cdbab-77c2-4fea-8f38-6e46cd274495
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278979143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3278979143
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.152668581
Short name T323
Test name
Test status
Simulation time 124356481673 ps
CPU time 245.02 seconds
Started Jan 17 03:12:22 PM PST 24
Finished Jan 17 03:16:32 PM PST 24
Peak memory 194264 kb
Host smart-ae814461-b191-4969-8fe2-9cd29df87c10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152668581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.152668581
Directory /workspace/99.rv_timer_random/latest
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