Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.57 99.36 98.73 100.00 100.00 100.00 99.32


Total test records in report: 616
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T562 /workspace/coverage/default/117.rv_timer_random.2052368439 Jan 21 09:18:55 PM PST 24 Jan 21 09:19:10 PM PST 24 27765372226 ps
T205 /workspace/coverage/default/89.rv_timer_random.3580151138 Jan 21 09:18:17 PM PST 24 Jan 21 09:22:42 PM PST 24 120943487633 ps
T273 /workspace/coverage/default/142.rv_timer_random.1551718224 Jan 21 09:19:39 PM PST 24 Jan 21 09:23:36 PM PST 24 156315728535 ps
T303 /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3634280494 Jan 21 09:16:31 PM PST 24 Jan 21 09:17:06 PM PST 24 18102980029 ps
T563 /workspace/coverage/default/46.rv_timer_disabled.3069504970 Jan 21 09:16:55 PM PST 24 Jan 21 09:19:58 PM PST 24 431777377238 ps
T180 /workspace/coverage/default/193.rv_timer_random.1648697909 Jan 21 09:21:08 PM PST 24 Jan 21 09:25:32 PM PST 24 456726093777 ps
T225 /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.1903019471 Jan 21 09:27:00 PM PST 24 Jan 21 09:34:17 PM PST 24 70847614379 ps
T294 /workspace/coverage/default/114.rv_timer_random.503915861 Jan 21 09:18:48 PM PST 24 Jan 21 09:21:54 PM PST 24 412337365327 ps
T158 /workspace/coverage/default/153.rv_timer_random.2016780194 Jan 21 10:13:19 PM PST 24 Jan 21 10:14:54 PM PST 24 248797340586 ps
T195 /workspace/coverage/default/8.rv_timer_stress_all.740335460 Jan 21 09:12:20 PM PST 24 Jan 21 09:24:09 PM PST 24 1213392501752 ps
T314 /workspace/coverage/default/157.rv_timer_random.3587406602 Jan 21 09:19:57 PM PST 24 Jan 21 09:26:17 PM PST 24 387799684638 ps
T305 /workspace/coverage/default/24.rv_timer_random.1200143490 Jan 21 10:35:27 PM PST 24 Jan 21 10:40:09 PM PST 24 284679593933 ps
T564 /workspace/coverage/default/37.rv_timer_disabled.3529283857 Jan 21 09:15:29 PM PST 24 Jan 21 09:17:19 PM PST 24 68062917524 ps
T357 /workspace/coverage/default/37.rv_timer_stress_all.2494918295 Jan 21 09:15:39 PM PST 24 Jan 21 09:28:36 PM PST 24 162898200517 ps
T207 /workspace/coverage/default/30.rv_timer_stress_all.3139088988 Jan 21 09:14:25 PM PST 24 Jan 21 09:50:45 PM PST 24 625708963052 ps
T254 /workspace/coverage/default/90.rv_timer_random.1138470096 Jan 21 09:18:18 PM PST 24 Jan 21 09:21:22 PM PST 24 81341371017 ps
T326 /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.764433715 Jan 21 09:11:46 PM PST 24 Jan 21 09:27:16 PM PST 24 164827639728 ps
T350 /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3962604966 Jan 21 09:13:23 PM PST 24 Jan 21 09:25:41 PM PST 24 689923055366 ps
T565 /workspace/coverage/default/122.rv_timer_random.2586837762 Jan 21 09:18:58 PM PST 24 Jan 21 09:22:40 PM PST 24 339932527041 ps
T566 /workspace/coverage/default/20.rv_timer_random.518111810 Jan 21 09:12:57 PM PST 24 Jan 21 09:53:07 PM PST 24 314309912584 ps
T321 /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3991942467 Jan 21 09:47:33 PM PST 24 Jan 21 09:55:17 PM PST 24 446486945693 ps
T189 /workspace/coverage/default/46.rv_timer_random.1154990873 Jan 21 09:16:58 PM PST 24 Jan 21 09:24:19 PM PST 24 1809688579919 ps
T349 /workspace/coverage/default/163.rv_timer_random.1448761735 Jan 21 09:20:09 PM PST 24 Jan 21 09:22:04 PM PST 24 131276835040 ps
T164 /workspace/coverage/default/137.rv_timer_random.1424469465 Jan 21 09:19:26 PM PST 24 Jan 21 09:22:58 PM PST 24 1601690917585 ps
T344 /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3921784600 Jan 21 09:16:16 PM PST 24 Jan 21 09:25:25 PM PST 24 1521135520847 ps
T346 /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.4292312276 Jan 21 09:15:18 PM PST 24 Jan 21 09:17:58 PM PST 24 159888490345 ps
T197 /workspace/coverage/default/49.rv_timer_random.3371782560 Jan 21 09:17:16 PM PST 24 Jan 21 09:46:10 PM PST 24 366859950350 ps
T210 /workspace/coverage/default/134.rv_timer_random.783336578 Jan 21 09:19:29 PM PST 24 Jan 21 09:20:29 PM PST 24 29555725648 ps
T567 /workspace/coverage/default/28.rv_timer_stress_all.3029179793 Jan 21 09:14:04 PM PST 24 Jan 21 09:15:48 PM PST 24 102725066389 ps
T568 /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.2256843928 Jan 21 10:37:14 PM PST 24 Jan 21 10:37:39 PM PST 24 32577536977 ps
T219 /workspace/coverage/default/5.rv_timer_random_reset.4116148635 Jan 21 09:12:06 PM PST 24 Jan 21 09:14:17 PM PST 24 43628388094 ps
T569 /workspace/coverage/default/147.rv_timer_random.1441067592 Jan 21 09:19:44 PM PST 24 Jan 21 09:27:22 PM PST 24 92437740118 ps
T570 /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1075708940 Jan 21 09:15:47 PM PST 24 Jan 21 09:16:08 PM PST 24 10068107716 ps
T571 /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.1817927596 Jan 21 09:16:31 PM PST 24 Jan 21 09:23:30 PM PST 24 199538718786 ps
T309 /workspace/coverage/default/29.rv_timer_stress_all.3375039802 Jan 21 09:14:12 PM PST 24 Jan 21 09:29:33 PM PST 24 328241219409 ps
T572 /workspace/coverage/default/45.rv_timer_random_reset.495583265 Jan 21 09:16:55 PM PST 24 Jan 21 09:18:50 PM PST 24 48426550157 ps
T573 /workspace/coverage/default/27.rv_timer_stress_all.3416105889 Jan 21 09:13:57 PM PST 24 Jan 21 09:20:06 PM PST 24 879566175894 ps
T347 /workspace/coverage/default/59.rv_timer_random.1196192070 Jan 21 09:18:05 PM PST 24 Jan 21 09:18:11 PM PST 24 11088115273 ps
T341 /workspace/coverage/default/61.rv_timer_random.3913988421 Jan 21 09:17:52 PM PST 24 Jan 21 09:23:04 PM PST 24 201380588265 ps
T318 /workspace/coverage/default/146.rv_timer_random.1776599750 Jan 21 09:19:34 PM PST 24 Jan 21 09:26:01 PM PST 24 158283315426 ps
T574 /workspace/coverage/default/39.rv_timer_random_reset.3201796125 Jan 21 09:15:56 PM PST 24 Jan 21 09:17:15 PM PST 24 160245427718 ps
T176 /workspace/coverage/default/177.rv_timer_random.3514756062 Jan 21 09:20:45 PM PST 24 Jan 21 09:25:18 PM PST 24 447447481536 ps
T152 /workspace/coverage/default/68.rv_timer_random.125668021 Jan 21 09:45:35 PM PST 24 Jan 21 09:50:57 PM PST 24 451767379640 ps
T575 /workspace/coverage/default/12.rv_timer_random_reset.1088715026 Jan 21 09:45:41 PM PST 24 Jan 21 09:45:48 PM PST 24 2909036362 ps
T576 /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.2321963203 Jan 21 09:17:09 PM PST 24 Jan 21 09:54:42 PM PST 24 1104776225185 ps
T276 /workspace/coverage/default/40.rv_timer_random.1961800472 Jan 21 09:15:56 PM PST 24 Jan 21 09:25:44 PM PST 24 215970908330 ps
T577 /workspace/coverage/default/28.rv_timer_disabled.2001126679 Jan 21 09:14:04 PM PST 24 Jan 21 09:15:24 PM PST 24 48285079497 ps
T578 /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.38624193 Jan 21 09:15:07 PM PST 24 Jan 21 09:22:19 PM PST 24 131323664273 ps
T239 /workspace/coverage/default/162.rv_timer_random.2397686085 Jan 21 09:20:06 PM PST 24 Jan 21 09:21:35 PM PST 24 58343611779 ps
T223 /workspace/coverage/default/32.rv_timer_stress_all.34727429 Jan 21 09:15:12 PM PST 24 Jan 21 09:55:07 PM PST 24 1375318581513 ps
T77 /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.96877609 Jan 21 09:14:31 PM PST 24 Jan 21 09:20:30 PM PST 24 67208931962 ps
T315 /workspace/coverage/default/116.rv_timer_random.1743560816 Jan 21 09:18:56 PM PST 24 Jan 21 09:23:00 PM PST 24 463773067586 ps
T579 /workspace/coverage/default/21.rv_timer_disabled.2398507837 Jan 21 09:12:52 PM PST 24 Jan 21 09:17:01 PM PST 24 209632761482 ps
T283 /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.4062462857 Jan 21 09:13:08 PM PST 24 Jan 21 09:20:43 PM PST 24 165390798993 ps
T343 /workspace/coverage/default/65.rv_timer_random.2188125353 Jan 21 09:17:54 PM PST 24 Jan 21 09:18:14 PM PST 24 10182981613 ps
T580 /workspace/coverage/default/14.rv_timer_random.714361823 Jan 21 09:12:45 PM PST 24 Jan 21 09:19:09 PM PST 24 70330723520 ps
T581 /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.2863806333 Jan 21 09:12:44 PM PST 24 Jan 21 09:24:06 PM PST 24 63307983293 ps
T243 /workspace/coverage/default/166.rv_timer_random.2049577538 Jan 21 09:20:17 PM PST 24 Jan 21 09:23:09 PM PST 24 59863102090 ps
T582 /workspace/coverage/default/31.rv_timer_disabled.4210874212 Jan 21 09:14:30 PM PST 24 Jan 21 09:16:01 PM PST 24 53769182033 ps
T583 /workspace/coverage/default/39.rv_timer_random.1260245351 Jan 21 09:15:48 PM PST 24 Jan 21 09:38:32 PM PST 24 36605273415 ps
T584 /workspace/coverage/default/37.rv_timer_random_reset.2291042874 Jan 21 09:15:28 PM PST 24 Jan 21 09:16:47 PM PST 24 50684872204 ps
T173 /workspace/coverage/default/17.rv_timer_random_reset.4145122306 Jan 21 09:12:42 PM PST 24 Jan 21 09:14:45 PM PST 24 75600984935 ps
T585 /workspace/coverage/default/10.rv_timer_random_reset.4031884975 Jan 21 09:12:35 PM PST 24 Jan 21 09:12:43 PM PST 24 196254326 ps
T586 /workspace/coverage/default/2.rv_timer_stress_all.805706742 Jan 21 09:11:56 PM PST 24 Jan 21 09:14:57 PM PST 24 403907823849 ps
T165 /workspace/coverage/default/21.rv_timer_stress_all.1415598194 Jan 21 09:13:02 PM PST 24 Jan 21 09:53:34 PM PST 24 820489401209 ps
T216 /workspace/coverage/default/43.rv_timer_random.3034854259 Jan 21 09:16:17 PM PST 24 Jan 21 09:19:21 PM PST 24 148504816732 ps
T262 /workspace/coverage/default/83.rv_timer_random.3051305917 Jan 21 09:18:17 PM PST 24 Jan 21 09:31:29 PM PST 24 444023094231 ps
T587 /workspace/coverage/default/136.rv_timer_random.1126592635 Jan 21 09:19:24 PM PST 24 Jan 21 09:20:55 PM PST 24 85391655337 ps
T588 /workspace/coverage/default/12.rv_timer_disabled.325234556 Jan 21 09:12:32 PM PST 24 Jan 21 09:14:04 PM PST 24 52003331632 ps
T589 /workspace/coverage/default/2.rv_timer_random_reset.1540589321 Jan 21 09:12:07 PM PST 24 Jan 21 09:12:20 PM PST 24 4126653053 ps
T281 /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.4114531374 Jan 21 09:12:37 PM PST 24 Jan 21 09:13:14 PM PST 24 17429806404 ps
T298 /workspace/coverage/default/49.rv_timer_random_reset.2746828632 Jan 21 09:17:27 PM PST 24 Jan 21 09:18:39 PM PST 24 36514956709 ps
T590 /workspace/coverage/default/38.rv_timer_random_reset.1910587009 Jan 21 09:15:40 PM PST 24 Jan 21 09:16:56 PM PST 24 51136015499 ps
T591 /workspace/coverage/default/27.rv_timer_random.4293940005 Jan 21 09:13:49 PM PST 24 Jan 21 09:14:54 PM PST 24 69132761437 ps
T592 /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.4060083284 Jan 21 09:12:31 PM PST 24 Jan 21 09:27:51 PM PST 24 123619301496 ps
T247 /workspace/coverage/default/158.rv_timer_random.2433512788 Jan 21 09:19:56 PM PST 24 Jan 21 09:23:58 PM PST 24 127550631455 ps
T593 /workspace/coverage/default/34.rv_timer_random.2895641299 Jan 21 09:15:06 PM PST 24 Jan 21 09:16:29 PM PST 24 129026570083 ps
T594 /workspace/coverage/default/6.rv_timer_random.3432766635 Jan 21 09:12:19 PM PST 24 Jan 21 09:12:38 PM PST 24 5671146327 ps
T595 /workspace/coverage/default/11.rv_timer_random.881562721 Jan 21 09:12:36 PM PST 24 Jan 21 09:14:29 PM PST 24 70352141270 ps
T596 /workspace/coverage/default/34.rv_timer_disabled.566987591 Jan 21 10:06:16 PM PST 24 Jan 21 10:09:22 PM PST 24 416353877668 ps
T597 /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.786544579 Jan 21 09:17:09 PM PST 24 Jan 21 09:20:31 PM PST 24 502587687497 ps
T334 /workspace/coverage/default/45.rv_timer_random.669841942 Jan 21 09:16:46 PM PST 24 Jan 21 09:19:29 PM PST 24 76360648687 ps
T598 /workspace/coverage/default/47.rv_timer_random_reset.3116592744 Jan 21 09:17:08 PM PST 24 Jan 21 09:24:39 PM PST 24 159433790811 ps
T599 /workspace/coverage/default/33.rv_timer_random.1427621646 Jan 21 09:15:12 PM PST 24 Jan 21 09:15:32 PM PST 24 22353099773 ps
T600 /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.2281394878 Jan 21 09:12:51 PM PST 24 Jan 21 09:19:11 PM PST 24 49648927003 ps
T601 /workspace/coverage/default/16.rv_timer_disabled.2473313504 Jan 21 09:12:38 PM PST 24 Jan 21 09:17:35 PM PST 24 724523519433 ps
T602 /workspace/coverage/default/28.rv_timer_random_reset.1754762234 Jan 21 09:14:03 PM PST 24 Jan 21 09:14:23 PM PST 24 781842711 ps
T279 /workspace/coverage/default/60.rv_timer_random.689407165 Jan 21 09:17:53 PM PST 24 Jan 21 09:29:16 PM PST 24 148429466628 ps
T222 /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.3444002196 Jan 21 09:12:35 PM PST 24 Jan 21 09:13:38 PM PST 24 58529414877 ps
T265 /workspace/coverage/default/106.rv_timer_random.1302814653 Jan 21 09:57:53 PM PST 24 Jan 21 10:05:46 PM PST 24 130259119711 ps
T358 /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3921024621 Jan 21 09:12:34 PM PST 24 Jan 21 09:25:14 PM PST 24 2370733902181 ps
T352 /workspace/coverage/default/151.rv_timer_random.2288012909 Jan 21 09:43:18 PM PST 24 Jan 21 09:44:46 PM PST 24 51735767077 ps
T603 /workspace/coverage/default/3.rv_timer_random_reset.61127907 Jan 21 09:12:07 PM PST 24 Jan 21 09:14:29 PM PST 24 44154855078 ps
T128 /workspace/coverage/default/156.rv_timer_random.4278579249 Jan 21 09:19:56 PM PST 24 Jan 21 09:27:40 PM PST 24 600374784072 ps
T604 /workspace/coverage/default/40.rv_timer_random_reset.1937544617 Jan 21 09:15:50 PM PST 24 Jan 21 09:16:01 PM PST 24 13732024992 ps
T605 /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1303707914 Jan 21 09:12:48 PM PST 24 Jan 21 09:13:25 PM PST 24 21828270476 ps
T240 /workspace/coverage/default/43.rv_timer_random_reset.1911102025 Jan 21 09:16:20 PM PST 24 Jan 21 09:17:34 PM PST 24 45715879010 ps
T282 /workspace/coverage/default/87.rv_timer_random.1005652270 Jan 21 09:18:20 PM PST 24 Jan 21 09:20:44 PM PST 24 139968207017 ps
T606 /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.1660420571 Jan 21 09:15:22 PM PST 24 Jan 21 09:18:39 PM PST 24 48669484852 ps
T190 /workspace/coverage/default/10.rv_timer_random.1773758509 Jan 21 09:12:29 PM PST 24 Jan 21 09:14:06 PM PST 24 179183809433 ps
T607 /workspace/coverage/default/160.rv_timer_random.4092002587 Jan 21 09:19:58 PM PST 24 Jan 21 09:27:27 PM PST 24 804055211990 ps
T608 /workspace/coverage/default/45.rv_timer_stress_all.3412165431 Jan 21 09:16:53 PM PST 24 Jan 21 09:19:04 PM PST 24 171419940728 ps
T356 /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.1906136082 Jan 21 09:14:24 PM PST 24 Jan 21 09:34:35 PM PST 24 4027586862736 ps
T609 /workspace/coverage/default/66.rv_timer_random.2146261332 Jan 21 09:39:52 PM PST 24 Jan 21 09:41:34 PM PST 24 77664616289 ps
T340 /workspace/coverage/default/42.rv_timer_random.186457077 Jan 21 09:16:00 PM PST 24 Jan 21 09:28:12 PM PST 24 171674067748 ps
T129 /workspace/coverage/default/154.rv_timer_random.1261353754 Jan 21 09:19:45 PM PST 24 Jan 21 09:29:18 PM PST 24 237585423297 ps
T610 /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.412220356 Jan 21 10:30:10 PM PST 24 Jan 21 10:41:39 PM PST 24 1257237635209 ps
T259 /workspace/coverage/default/189.rv_timer_random.490974525 Jan 21 10:23:22 PM PST 24 Jan 21 10:27:43 PM PST 24 216726630919 ps
T354 /workspace/coverage/default/5.rv_timer_random.3156385459 Jan 21 09:12:07 PM PST 24 Jan 21 09:16:36 PM PST 24 152253808224 ps
T611 /workspace/coverage/default/64.rv_timer_random.115675574 Jan 21 09:17:55 PM PST 24 Jan 21 09:20:28 PM PST 24 93530375370 ps
T132 /workspace/coverage/default/125.rv_timer_random.1696672274 Jan 21 09:19:06 PM PST 24 Jan 21 09:21:51 PM PST 24 164337750275 ps
T612 /workspace/coverage/default/55.rv_timer_random.3281946852 Jan 21 09:17:41 PM PST 24 Jan 21 09:54:09 PM PST 24 597439292434 ps
T613 /workspace/coverage/default/35.rv_timer_stress_all.1704900122 Jan 21 09:15:19 PM PST 24 Jan 21 09:20:02 PM PST 24 464179559750 ps
T614 /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.557070402 Jan 21 09:49:09 PM PST 24 Jan 21 09:54:18 PM PST 24 36056849660 ps
T615 /workspace/coverage/default/33.rv_timer_disabled.741783870 Jan 21 09:15:08 PM PST 24 Jan 21 09:16:09 PM PST 24 59125371177 ps
T616 /workspace/coverage/default/84.rv_timer_random.608560030 Jan 21 09:18:18 PM PST 24 Jan 21 09:19:05 PM PST 24 70474980625 ps

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.3247789287
Short name T3
Test name
Test status
Simulation time 558868006814 ps
CPU time 825.29 seconds
Started Jan 21 09:40:44 PM PST 24
Finished Jan 21 09:54:33 PM PST 24
Peak memory 207284 kb
Host smart-f452f580-d482-44a3-a12b-6bcdf180d7e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247789287 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.3247789287
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.rv_timer_random.4181854917
Short name T12
Test name
Test status
Simulation time 1069727859206 ps
CPU time 308.63 seconds
Started Jan 21 09:17:25 PM PST 24
Finished Jan 21 09:22:42 PM PST 24
Peak memory 191740 kb
Host smart-2cdb99a1-5a24-423c-a233-a15c198314f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181854917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.4181854917
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.11058590
Short name T15
Test name
Test status
Simulation time 963023521 ps
CPU time 1.82 seconds
Started Jan 21 08:45:11 PM PST 24
Finished Jan 21 08:45:15 PM PST 24
Peak memory 183324 kb
Host smart-27ea2743-4f0e-4d87-82f5-7e72cc5320ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11058590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_int
g_err.11058590
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1424395985
Short name T137
Test name
Test status
Simulation time 1561944736741 ps
CPU time 2746.25 seconds
Started Jan 21 09:12:35 PM PST 24
Finished Jan 21 09:58:29 PM PST 24
Peak memory 191780 kb
Host smart-dcec3e77-9394-4ca8-b5c8-9898b6d4ba57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424395985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1424395985
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.989979061
Short name T90
Test name
Test status
Simulation time 3615208008499 ps
CPU time 3236.2 seconds
Started Jan 21 09:17:05 PM PST 24
Finished Jan 21 10:11:05 PM PST 24
Peak memory 191676 kb
Host smart-4b2eb74d-f76a-4faf-9f35-71d3d8c265ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989979061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
989979061
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.4147909348
Short name T35
Test name
Test status
Simulation time 384490586969 ps
CPU time 1585.84 seconds
Started Jan 21 09:14:02 PM PST 24
Finished Jan 21 09:40:46 PM PST 24
Peak memory 214728 kb
Host smart-61c055fa-1ebf-4853-a2c9-be98a4e5a024
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147909348 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.4147909348
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.4222558252
Short name T34
Test name
Test status
Simulation time 478399189987 ps
CPU time 824.96 seconds
Started Jan 21 09:12:08 PM PST 24
Finished Jan 21 09:25:56 PM PST 24
Peak memory 191724 kb
Host smart-7fc27d2f-a1a5-4156-bb76-ca2c75cecccb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222558252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
4222558252
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.3139088988
Short name T207
Test name
Test status
Simulation time 625708963052 ps
CPU time 2168.7 seconds
Started Jan 21 09:14:25 PM PST 24
Finished Jan 21 09:50:45 PM PST 24
Peak memory 191660 kb
Host smart-162eff3d-3ff3-499a-bd0a-1d0b2578e13f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139088988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.3139088988
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.514781822
Short name T105
Test name
Test status
Simulation time 8196601412424 ps
CPU time 1249.21 seconds
Started Jan 21 09:35:03 PM PST 24
Finished Jan 21 09:55:58 PM PST 24
Peak memory 191652 kb
Host smart-0189b408-e27f-41ae-88f3-c00c822c0ae6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514781822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.
514781822
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1250655622
Short name T193
Test name
Test status
Simulation time 1196550685439 ps
CPU time 2743.6 seconds
Started Jan 21 09:17:26 PM PST 24
Finished Jan 21 10:03:18 PM PST 24
Peak memory 191616 kb
Host smart-438811d1-3dd9-43d5-bfc4-7e560bba4b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250655622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1250655622
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1415598194
Short name T165
Test name
Test status
Simulation time 820489401209 ps
CPU time 2429.22 seconds
Started Jan 21 09:13:02 PM PST 24
Finished Jan 21 09:53:34 PM PST 24
Peak memory 191584 kb
Host smart-8d2cca69-bbbb-466e-a45e-15216fe5cc5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415598194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1415598194
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3232472079
Short name T218
Test name
Test status
Simulation time 621801488560 ps
CPU time 1274.19 seconds
Started Jan 21 09:12:06 PM PST 24
Finished Jan 21 09:33:24 PM PST 24
Peak memory 191716 kb
Host smart-cfb6e589-ac7f-45bc-b444-7a61087dece5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232472079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3232472079
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.2722226298
Short name T148
Test name
Test status
Simulation time 830027345516 ps
CPU time 1475.52 seconds
Started Jan 21 09:13:32 PM PST 24
Finished Jan 21 09:38:11 PM PST 24
Peak memory 191604 kb
Host smart-2f41b38f-7e27-4162-b4d3-eb1e3181682d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722226298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.2722226298
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_random.366708981
Short name T93
Test name
Test status
Simulation time 486732846612 ps
CPU time 736.05 seconds
Started Jan 21 09:12:43 PM PST 24
Finished Jan 21 09:25:03 PM PST 24
Peak memory 191624 kb
Host smart-261ab5c2-78bd-4be9-abb1-8cdf3a2d52f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366708981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.366708981
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2810576510
Short name T21
Test name
Test status
Simulation time 106716126 ps
CPU time 0.87 seconds
Started Jan 21 09:11:51 PM PST 24
Finished Jan 21 09:11:55 PM PST 24
Peak memory 213540 kb
Host smart-b335c04a-3d2d-41cf-9870-50abc3b13197
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810576510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2810576510
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.34727429
Short name T223
Test name
Test status
Simulation time 1375318581513 ps
CPU time 2393.95 seconds
Started Jan 21 09:15:12 PM PST 24
Finished Jan 21 09:55:07 PM PST 24
Peak memory 191588 kb
Host smart-a734bfa0-5a66-4fba-a52e-3f3fa786180f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34727429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.34727429
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.2868584468
Short name T100
Test name
Test status
Simulation time 1936351515853 ps
CPU time 1029.42 seconds
Started Jan 21 09:12:24 PM PST 24
Finished Jan 21 09:29:37 PM PST 24
Peak memory 191652 kb
Host smart-9f8105c9-3dc5-4b3e-8111-971e60dc73e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868584468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
2868584468
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2121288651
Short name T133
Test name
Test status
Simulation time 355068008334 ps
CPU time 665.93 seconds
Started Jan 21 09:11:53 PM PST 24
Finished Jan 21 09:23:05 PM PST 24
Peak memory 191596 kb
Host smart-88a88ac1-20f9-47fe-8310-1e9d1db0e6fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121288651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2121288651
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2231044794
Short name T26
Test name
Test status
Simulation time 778965822314 ps
CPU time 638.21 seconds
Started Jan 21 09:16:32 PM PST 24
Finished Jan 21 09:27:12 PM PST 24
Peak memory 191576 kb
Host smart-187acf94-d934-499f-b7bb-e9a842d80940
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231044794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2231044794
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.3214503333
Short name T150
Test name
Test status
Simulation time 2137421104723 ps
CPU time 1422.94 seconds
Started Jan 21 09:13:12 PM PST 24
Finished Jan 21 09:36:58 PM PST 24
Peak memory 191600 kb
Host smart-74eab5f9-b8f5-4795-904f-89b66abf79b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214503333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.3214503333
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/106.rv_timer_random.1302814653
Short name T265
Test name
Test status
Simulation time 130259119711 ps
CPU time 464.23 seconds
Started Jan 21 09:57:53 PM PST 24
Finished Jan 21 10:05:46 PM PST 24
Peak memory 191676 kb
Host smart-6ccb703c-09b0-4d86-98d7-0c3c6367dde1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302814653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1302814653
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.2354744919
Short name T203
Test name
Test status
Simulation time 170898249947 ps
CPU time 271.57 seconds
Started Jan 21 09:18:09 PM PST 24
Finished Jan 21 09:22:42 PM PST 24
Peak memory 191624 kb
Host smart-113ddcc0-bfaa-4fdc-94ce-428343b27b35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354744919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2354744919
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.3323643810
Short name T221
Test name
Test status
Simulation time 141157569700 ps
CPU time 198.01 seconds
Started Jan 21 09:18:45 PM PST 24
Finished Jan 21 09:22:05 PM PST 24
Peak memory 191612 kb
Host smart-a8193455-e40c-4e4b-8ee9-ffa19ed4de8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323643810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3323643810
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1252715017
Short name T4
Test name
Test status
Simulation time 1007478962125 ps
CPU time 597.01 seconds
Started Jan 21 09:12:11 PM PST 24
Finished Jan 21 09:22:11 PM PST 24
Peak memory 183692 kb
Host smart-d66979d1-f0f4-4c4e-af38-144dad9cbaff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252715017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1252715017
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/156.rv_timer_random.4278579249
Short name T128
Test name
Test status
Simulation time 600374784072 ps
CPU time 460.51 seconds
Started Jan 21 09:19:56 PM PST 24
Finished Jan 21 09:27:40 PM PST 24
Peak memory 191672 kb
Host smart-8608acdc-021c-4e2b-bfac-222015e944ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278579249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.4278579249
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.1569739321
Short name T139
Test name
Test status
Simulation time 569386948357 ps
CPU time 641.94 seconds
Started Jan 21 09:21:23 PM PST 24
Finished Jan 21 09:32:06 PM PST 24
Peak memory 191684 kb
Host smart-e41937cf-d80b-49b5-b47a-59500d385a2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569739321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.1569739321
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random.1154990873
Short name T189
Test name
Test status
Simulation time 1809688579919 ps
CPU time 438.53 seconds
Started Jan 21 09:16:58 PM PST 24
Finished Jan 21 09:24:19 PM PST 24
Peak memory 191688 kb
Host smart-dcf54af7-2dcd-4632-9382-6753b8b69751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154990873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1154990873
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.1454916055
Short name T301
Test name
Test status
Simulation time 113289555821 ps
CPU time 2475.13 seconds
Started Jan 21 09:20:07 PM PST 24
Finished Jan 21 10:01:25 PM PST 24
Peak memory 191620 kb
Host smart-67177e82-fad1-4a9c-897e-82dc6d165266
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454916055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1454916055
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.122739941
Short name T167
Test name
Test status
Simulation time 488350294199 ps
CPU time 1339.51 seconds
Started Jan 21 09:13:44 PM PST 24
Finished Jan 21 09:36:05 PM PST 24
Peak memory 191624 kb
Host smart-2af24709-2871-4004-9ddc-336ebd097d8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122739941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.
122739941
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.3142210873
Short name T248
Test name
Test status
Simulation time 2072823013843 ps
CPU time 1284.55 seconds
Started Jan 21 09:14:30 PM PST 24
Finished Jan 21 09:36:05 PM PST 24
Peak memory 191844 kb
Host smart-8d29e5b0-43bb-47ee-b703-9964002da607
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142210873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.3142210873
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1220719894
Short name T104
Test name
Test status
Simulation time 744534088548 ps
CPU time 280.22 seconds
Started Jan 21 09:16:17 PM PST 24
Finished Jan 21 09:20:59 PM PST 24
Peak memory 191640 kb
Host smart-98cb82ff-c71b-4635-bdd1-af321700ff8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220719894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1220719894
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1953546500
Short name T80
Test name
Test status
Simulation time 18300885 ps
CPU time 0.73 seconds
Started Jan 21 07:33:55 PM PST 24
Finished Jan 21 07:34:00 PM PST 24
Peak memory 193192 kb
Host smart-d12d5f4e-904d-4fed-912f-da4f02a940d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953546500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1953546500
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/18.rv_timer_random.2820229231
Short name T95
Test name
Test status
Simulation time 1074709452840 ps
CPU time 623.51 seconds
Started Jan 21 09:12:41 PM PST 24
Finished Jan 21 09:23:09 PM PST 24
Peak memory 194760 kb
Host smart-e89aea59-826b-4906-a04b-07873938b94b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820229231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2820229231
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.1648697909
Short name T180
Test name
Test status
Simulation time 456726093777 ps
CPU time 258.58 seconds
Started Jan 21 09:21:08 PM PST 24
Finished Jan 21 09:25:32 PM PST 24
Peak memory 194320 kb
Host smart-6b0c6275-86f3-4cfc-a5f0-d661ae396650
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648697909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1648697909
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3562678811
Short name T250
Test name
Test status
Simulation time 842813305370 ps
CPU time 840.31 seconds
Started Jan 21 09:13:23 PM PST 24
Finished Jan 21 09:27:25 PM PST 24
Peak memory 191584 kb
Host smart-ab4607cb-e71f-4998-98fd-93bba7a19e93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562678811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3562678811
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.740335460
Short name T195
Test name
Test status
Simulation time 1213392501752 ps
CPU time 704.69 seconds
Started Jan 21 09:12:20 PM PST 24
Finished Jan 21 09:24:09 PM PST 24
Peak memory 195452 kb
Host smart-cb548e76-0440-464c-9499-ceb597d74044
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740335460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.740335460
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/111.rv_timer_random.2234999218
Short name T154
Test name
Test status
Simulation time 166800175100 ps
CPU time 310.57 seconds
Started Jan 21 09:18:45 PM PST 24
Finished Jan 21 09:23:57 PM PST 24
Peak memory 191708 kb
Host smart-7d9f2b88-c456-42a1-95d6-30d76b374f85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234999218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2234999218
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.774143571
Short name T234
Test name
Test status
Simulation time 164891218466 ps
CPU time 1617.37 seconds
Started Jan 21 09:18:55 PM PST 24
Finished Jan 21 09:45:55 PM PST 24
Peak memory 191864 kb
Host smart-9da8b620-1be2-48e4-87da-ea83628aa96e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774143571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.774143571
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.3514756062
Short name T176
Test name
Test status
Simulation time 447447481536 ps
CPU time 270.39 seconds
Started Jan 21 09:20:45 PM PST 24
Finished Jan 21 09:25:18 PM PST 24
Peak memory 191672 kb
Host smart-d77ea52c-1ea2-4bfd-ba0a-6b9ea33f1aef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514756062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3514756062
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.3375039802
Short name T309
Test name
Test status
Simulation time 328241219409 ps
CPU time 905.57 seconds
Started Jan 21 09:14:12 PM PST 24
Finished Jan 21 09:29:33 PM PST 24
Peak memory 191580 kb
Host smart-4dcadaa8-3180-41cf-830c-26d27989f591
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375039802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.3375039802
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.1617769319
Short name T29
Test name
Test status
Simulation time 160092847518 ps
CPU time 125.69 seconds
Started Jan 21 09:17:10 PM PST 24
Finished Jan 21 09:19:19 PM PST 24
Peak memory 191604 kb
Host smart-9a85ee40-3f2d-4265-a3bc-d47462bf88a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617769319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1617769319
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.3897880505
Short name T53
Test name
Test status
Simulation time 108955090817 ps
CPU time 708.15 seconds
Started Jan 21 09:18:10 PM PST 24
Finished Jan 21 09:30:00 PM PST 24
Peak memory 191616 kb
Host smart-393eed0d-255b-45fe-918b-29eb41acebc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897880505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3897880505
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.4232343819
Short name T246
Test name
Test status
Simulation time 2954682724653 ps
CPU time 1451.73 seconds
Started Jan 21 09:11:51 PM PST 24
Finished Jan 21 09:36:08 PM PST 24
Peak memory 196104 kb
Host smart-025ed703-f693-422f-8f48-61219bd92f5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232343819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
4232343819
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/116.rv_timer_random.1743560816
Short name T315
Test name
Test status
Simulation time 463773067586 ps
CPU time 242.23 seconds
Started Jan 21 09:18:56 PM PST 24
Finished Jan 21 09:23:00 PM PST 24
Peak memory 191688 kb
Host smart-0d115849-8386-4752-858f-7d12b5797da4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743560816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1743560816
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.1696672274
Short name T132
Test name
Test status
Simulation time 164337750275 ps
CPU time 163.72 seconds
Started Jan 21 09:19:06 PM PST 24
Finished Jan 21 09:21:51 PM PST 24
Peak memory 191696 kb
Host smart-58e5c47c-8ffd-442c-bb17-4331a847cc3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696672274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1696672274
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2710444409
Short name T251
Test name
Test status
Simulation time 1024222322295 ps
CPU time 2053.01 seconds
Started Jan 21 09:36:38 PM PST 24
Finished Jan 21 10:11:01 PM PST 24
Peak memory 191656 kb
Host smart-2956a8a2-2d41-4c60-9357-1c971ea888a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710444409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2710444409
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1331624418
Short name T161
Test name
Test status
Simulation time 527774307753 ps
CPU time 275.48 seconds
Started Jan 21 09:31:43 PM PST 24
Finished Jan 21 09:36:45 PM PST 24
Peak memory 194508 kb
Host smart-eb1096ab-30a3-4830-a788-a77fd779889e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331624418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1331624418
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3963143301
Short name T338
Test name
Test status
Simulation time 201023054708 ps
CPU time 1546.84 seconds
Started Jan 21 09:12:48 PM PST 24
Finished Jan 21 09:38:37 PM PST 24
Peak memory 191672 kb
Host smart-5210ee2c-b22b-4c83-a564-effaa03cdfee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963143301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3963143301
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/195.rv_timer_random.4081533261
Short name T106
Test name
Test status
Simulation time 494614998248 ps
CPU time 374.84 seconds
Started Jan 21 10:07:32 PM PST 24
Finished Jan 21 10:13:50 PM PST 24
Peak memory 191616 kb
Host smart-314ecd85-3e5c-4147-9c1b-a91e27e765ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081533261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.4081533261
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1853999259
Short name T213
Test name
Test status
Simulation time 855832053482 ps
CPU time 491.59 seconds
Started Jan 21 09:11:56 PM PST 24
Finished Jan 21 09:20:14 PM PST 24
Peak memory 183424 kb
Host smart-64c621c6-e855-49bd-b297-a488daa12dc3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853999259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1853999259
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_random.2264422887
Short name T209
Test name
Test status
Simulation time 327725476961 ps
CPU time 439.33 seconds
Started Jan 21 09:15:39 PM PST 24
Finished Jan 21 09:23:04 PM PST 24
Peak memory 191712 kb
Host smart-91c81cbd-3438-482b-926f-09b8c0ac8b17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264422887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2264422887
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random.669841942
Short name T334
Test name
Test status
Simulation time 76360648687 ps
CPU time 162.09 seconds
Started Jan 21 09:16:46 PM PST 24
Finished Jan 21 09:19:29 PM PST 24
Peak memory 191700 kb
Host smart-5e3c8659-03d9-4469-bb6d-b8724a9d6bd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669841942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.669841942
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2114619609
Short name T64
Test name
Test status
Simulation time 38988155 ps
CPU time 1.47 seconds
Started Jan 21 07:33:09 PM PST 24
Finished Jan 21 07:33:14 PM PST 24
Peak memory 183180 kb
Host smart-0a6520e2-2972-4162-b056-26cbd85e666b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114619609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.2114619609
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.936197980
Short name T31
Test name
Test status
Simulation time 493001447 ps
CPU time 1.31 seconds
Started Jan 21 07:33:16 PM PST 24
Finished Jan 21 07:33:22 PM PST 24
Peak memory 183192 kb
Host smart-72290231-7023-44f4-9ce5-c40d15c7a902
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936197980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.936197980
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.3011385311
Short name T96
Test name
Test status
Simulation time 222783675436 ps
CPU time 760.97 seconds
Started Jan 21 09:43:57 PM PST 24
Finished Jan 21 09:56:39 PM PST 24
Peak memory 211392 kb
Host smart-cbc00887-41dc-41a9-a7bd-64d26f92f8c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011385311 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.3011385311
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/133.rv_timer_random.844781037
Short name T92
Test name
Test status
Simulation time 790072954044 ps
CPU time 417.4 seconds
Started Jan 21 09:19:28 PM PST 24
Finished Jan 21 09:26:39 PM PST 24
Peak memory 191652 kb
Host smart-db389089-bebd-4c15-8176-7b740f2978b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844781037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.844781037
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.578394256
Short name T230
Test name
Test status
Simulation time 223361487593 ps
CPU time 255.62 seconds
Started Jan 21 09:50:53 PM PST 24
Finished Jan 21 09:55:13 PM PST 24
Peak memory 194240 kb
Host smart-fd47b18a-150a-4f20-b7a7-cf99e4c49fed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578394256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.578394256
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.2016780194
Short name T158
Test name
Test status
Simulation time 248797340586 ps
CPU time 92.06 seconds
Started Jan 21 10:13:19 PM PST 24
Finished Jan 21 10:14:54 PM PST 24
Peak memory 191676 kb
Host smart-6f8251a4-6f0e-459d-8bfd-4449ffe2763c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016780194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2016780194
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.119631892
Short name T235
Test name
Test status
Simulation time 391112825339 ps
CPU time 1332.85 seconds
Started Jan 21 09:20:16 PM PST 24
Finished Jan 21 09:42:34 PM PST 24
Peak memory 193696 kb
Host smart-9d7f2dd7-0609-45e3-8e4d-ba28f049797b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119631892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.119631892
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.2718445709
Short name T109
Test name
Test status
Simulation time 243347637550 ps
CPU time 350.86 seconds
Started Jan 21 09:20:15 PM PST 24
Finished Jan 21 09:26:12 PM PST 24
Peak memory 191680 kb
Host smart-f40fea3d-c6f9-4fd9-a8ae-3f6c53f1008b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718445709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2718445709
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.2365776911
Short name T8
Test name
Test status
Simulation time 727708495546 ps
CPU time 935.19 seconds
Started Jan 21 09:32:03 PM PST 24
Finished Jan 21 09:48:01 PM PST 24
Peak memory 191696 kb
Host smart-43b54ff8-7228-45fe-96ef-c55111b66c3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365776911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2365776911
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.762238444
Short name T256
Test name
Test status
Simulation time 158382310748 ps
CPU time 769.83 seconds
Started Jan 21 09:20:34 PM PST 24
Finished Jan 21 09:33:25 PM PST 24
Peak memory 191664 kb
Host smart-c6aeb7f1-b805-43c4-9a50-80c758a2213b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762238444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.762238444
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.2403401714
Short name T144
Test name
Test status
Simulation time 198169383528 ps
CPU time 180.17 seconds
Started Jan 21 09:20:43 PM PST 24
Finished Jan 21 09:23:45 PM PST 24
Peak memory 191684 kb
Host smart-c5782522-3412-4896-887b-acdf01bb135c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403401714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.2403401714
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1703934416
Short name T224
Test name
Test status
Simulation time 750450430133 ps
CPU time 851.61 seconds
Started Jan 21 09:40:57 PM PST 24
Finished Jan 21 09:55:21 PM PST 24
Peak memory 191696 kb
Host smart-4fc4020a-4ff0-4a0b-92a3-93139ed17500
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703934416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1703934416
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.1094475091
Short name T191
Test name
Test status
Simulation time 542607215303 ps
CPU time 982.63 seconds
Started Jan 21 09:20:58 PM PST 24
Finished Jan 21 09:37:27 PM PST 24
Peak memory 191692 kb
Host smart-33d14cf7-c8d3-47ff-bb5d-6d2e28930e8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094475091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1094475091
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.3618520540
Short name T316
Test name
Test status
Simulation time 223723180050 ps
CPU time 397.15 seconds
Started Jan 21 09:12:49 PM PST 24
Finished Jan 21 09:19:28 PM PST 24
Peak memory 183448 kb
Host smart-0c5b6b7b-df39-4e90-82e2-1dd424530f4f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618520540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.3618520540
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3678655120
Short name T198
Test name
Test status
Simulation time 837727033330 ps
CPU time 330.04 seconds
Started Jan 21 09:15:07 PM PST 24
Finished Jan 21 09:20:39 PM PST 24
Peak memory 191728 kb
Host smart-ccb070a3-73de-48bc-b42b-27142905e050
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678655120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3678655120
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3116167137
Short name T143
Test name
Test status
Simulation time 2030103381221 ps
CPU time 777.94 seconds
Started Jan 21 09:16:48 PM PST 24
Finished Jan 21 09:29:48 PM PST 24
Peak memory 183452 kb
Host smart-619df261-d69e-41cb-bcba-835b3e649caa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116167137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3116167137
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/50.rv_timer_random.4049844644
Short name T48
Test name
Test status
Simulation time 120592903087 ps
CPU time 209.28 seconds
Started Jan 21 10:13:30 PM PST 24
Finished Jan 21 10:17:03 PM PST 24
Peak memory 191628 kb
Host smart-9ed0a768-11e1-4314-a465-0a3fcaf568be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049844644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.4049844644
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.174441322
Short name T149
Test name
Test status
Simulation time 933684280248 ps
CPU time 554.39 seconds
Started Jan 21 09:38:07 PM PST 24
Finished Jan 21 09:47:34 PM PST 24
Peak memory 191652 kb
Host smart-8acb343f-39d6-4d98-86a5-768492e64e07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174441322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.174441322
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.3244511896
Short name T175
Test name
Test status
Simulation time 147544394053 ps
CPU time 468.33 seconds
Started Jan 21 10:03:56 PM PST 24
Finished Jan 21 10:11:45 PM PST 24
Peak memory 191620 kb
Host smart-60e74bf0-0874-40b6-bb06-fea5938e1535
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244511896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3244511896
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random.4057877396
Short name T108
Test name
Test status
Simulation time 67082107160 ps
CPU time 368.53 seconds
Started Jan 21 09:11:48 PM PST 24
Finished Jan 21 09:18:00 PM PST 24
Peak memory 195048 kb
Host smart-cb5b0a68-ff17-4300-b3a8-2084e3cd3ab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057877396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.4057877396
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3921024621
Short name T358
Test name
Test status
Simulation time 2370733902181 ps
CPU time 752.44 seconds
Started Jan 21 09:12:34 PM PST 24
Finished Jan 21 09:25:14 PM PST 24
Peak memory 183488 kb
Host smart-8a7ec421-68c6-4d1b-8177-1a93e0312586
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921024621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3921024621
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/102.rv_timer_random.3862544084
Short name T258
Test name
Test status
Simulation time 51012048327 ps
CPU time 109.38 seconds
Started Jan 21 09:44:18 PM PST 24
Finished Jan 21 09:46:10 PM PST 24
Peak memory 183424 kb
Host smart-e38e8ed7-c48d-4241-87c8-acc111938950
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862544084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3862544084
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1953738292
Short name T51
Test name
Test status
Simulation time 81295259679 ps
CPU time 256.44 seconds
Started Jan 21 09:18:36 PM PST 24
Finished Jan 21 09:22:58 PM PST 24
Peak memory 191628 kb
Host smart-93fcfb72-b3f0-488f-a1dd-e5934c71004d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953738292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1953738292
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.608505344
Short name T232
Test name
Test status
Simulation time 402606071080 ps
CPU time 465.48 seconds
Started Jan 21 10:53:37 PM PST 24
Finished Jan 21 11:01:23 PM PST 24
Peak memory 195072 kb
Host smart-5df5481e-caf3-4f12-9929-bc0095cf58b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608505344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.608505344
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.503915861
Short name T294
Test name
Test status
Simulation time 412337365327 ps
CPU time 185.26 seconds
Started Jan 21 09:18:48 PM PST 24
Finished Jan 21 09:21:54 PM PST 24
Peak memory 191732 kb
Host smart-9f720fb2-3c4a-470a-b183-fdb72366d7f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503915861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.503915861
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3557496945
Short name T91
Test name
Test status
Simulation time 65894881690 ps
CPU time 106.05 seconds
Started Jan 21 09:18:45 PM PST 24
Finished Jan 21 09:20:33 PM PST 24
Peak memory 195252 kb
Host smart-06d2ca2d-9859-40cc-9c9d-de34b3410160
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557496945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3557496945
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.124649610
Short name T242
Test name
Test status
Simulation time 353110839399 ps
CPU time 210.18 seconds
Started Jan 21 09:18:57 PM PST 24
Finished Jan 21 09:22:29 PM PST 24
Peak memory 191592 kb
Host smart-c8a9b750-ea0a-4366-83e1-35a494becdc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124649610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.124649610
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.235898357
Short name T125
Test name
Test status
Simulation time 113463603601 ps
CPU time 918.76 seconds
Started Jan 21 09:19:18 PM PST 24
Finished Jan 21 09:34:47 PM PST 24
Peak memory 191692 kb
Host smart-a0965981-5be8-4779-96c3-cdcfa82e2774
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235898357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.235898357
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.3777756144
Short name T115
Test name
Test status
Simulation time 367227859520 ps
CPU time 1948.36 seconds
Started Jan 21 09:19:29 PM PST 24
Finished Jan 21 09:52:11 PM PST 24
Peak memory 191628 kb
Host smart-e53a9641-f290-47e3-a44d-693c7d3e9c32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777756144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3777756144
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.630478163
Short name T333
Test name
Test status
Simulation time 39049593057 ps
CPU time 67.86 seconds
Started Jan 21 09:19:35 PM PST 24
Finished Jan 21 09:20:54 PM PST 24
Peak memory 191696 kb
Host smart-7c80a3f0-90a4-4da0-b4f2-2ce69eb94a8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630478163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.630478163
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2674240299
Short name T194
Test name
Test status
Simulation time 520104415548 ps
CPU time 378.91 seconds
Started Jan 21 09:19:59 PM PST 24
Finished Jan 21 09:26:20 PM PST 24
Peak memory 191744 kb
Host smart-a6da9d16-ff26-43d0-b995-aeb50137d63a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674240299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2674240299
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.3744250877
Short name T275
Test name
Test status
Simulation time 53209338158 ps
CPU time 85.89 seconds
Started Jan 21 09:20:14 PM PST 24
Finished Jan 21 09:21:45 PM PST 24
Peak memory 191692 kb
Host smart-e943e5fd-64b0-4545-a8a9-f351310734a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744250877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3744250877
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3672458746
Short name T140
Test name
Test status
Simulation time 441575987030 ps
CPU time 287.93 seconds
Started Jan 21 09:58:07 PM PST 24
Finished Jan 21 10:02:57 PM PST 24
Peak memory 191696 kb
Host smart-1f5c3c50-d359-4883-a6b4-035cd2c8d99c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672458746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3672458746
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1799566857
Short name T52
Test name
Test status
Simulation time 157134884348 ps
CPU time 58.9 seconds
Started Jan 21 09:20:58 PM PST 24
Finished Jan 21 09:22:03 PM PST 24
Peak memory 192744 kb
Host smart-0eab4ed7-6281-48b3-9169-241052ed6eca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799566857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1799566857
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.4062462857
Short name T283
Test name
Test status
Simulation time 165390798993 ps
CPU time 452.26 seconds
Started Jan 21 09:13:08 PM PST 24
Finished Jan 21 09:20:43 PM PST 24
Peak memory 206200 kb
Host smart-7a15508c-8d84-4bb5-a6d8-b074afeb4510
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062462857 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.4062462857
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3661523714
Short name T121
Test name
Test status
Simulation time 70216580429 ps
CPU time 98.41 seconds
Started Jan 21 09:13:13 PM PST 24
Finished Jan 21 09:14:55 PM PST 24
Peak memory 183384 kb
Host smart-211e5ff2-0067-4fc9-b03d-e6673d7b2413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661523714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3661523714
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1320399311
Short name T134
Test name
Test status
Simulation time 498681655790 ps
CPU time 1037.63 seconds
Started Jan 21 09:13:47 PM PST 24
Finished Jan 21 09:31:06 PM PST 24
Peak memory 194316 kb
Host smart-b598cfc2-5da9-4146-bb31-9ebf62f8cfc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320399311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1320399311
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_random.1812002688
Short name T293
Test name
Test status
Simulation time 847574485809 ps
CPU time 396.48 seconds
Started Jan 21 09:12:03 PM PST 24
Finished Jan 21 09:18:44 PM PST 24
Peak memory 191680 kb
Host smart-955524ba-304d-4553-8ba6-83d479e0f1e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812002688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1812002688
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.4292312276
Short name T346
Test name
Test status
Simulation time 159888490345 ps
CPU time 158.02 seconds
Started Jan 21 09:15:18 PM PST 24
Finished Jan 21 09:17:58 PM PST 24
Peak memory 183488 kb
Host smart-ddf423bd-4543-4883-b10b-cbc3506e22e1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292312276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.4292312276
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.1911102025
Short name T240
Test name
Test status
Simulation time 45715879010 ps
CPU time 72.5 seconds
Started Jan 21 09:16:20 PM PST 24
Finished Jan 21 09:17:34 PM PST 24
Peak memory 191664 kb
Host smart-8dc73445-96c2-40c0-bd6b-f28184c21ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911102025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1911102025
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_random.3455434980
Short name T291
Test name
Test status
Simulation time 107765696124 ps
CPU time 53.21 seconds
Started Jan 21 09:16:30 PM PST 24
Finished Jan 21 09:17:25 PM PST 24
Peak memory 191676 kb
Host smart-0b445efd-ce9d-4b51-b541-92513ad0610f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455434980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3455434980
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.461317513
Short name T249
Test name
Test status
Simulation time 143792066587 ps
CPU time 540.33 seconds
Started Jan 21 09:16:46 PM PST 24
Finished Jan 21 09:25:47 PM PST 24
Peak memory 191520 kb
Host smart-e3239116-bfc9-49ec-9f08-6327108e744c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461317513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
461317513
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/56.rv_timer_random.3198020429
Short name T162
Test name
Test status
Simulation time 323399816742 ps
CPU time 293.97 seconds
Started Jan 21 09:17:39 PM PST 24
Finished Jan 21 09:22:36 PM PST 24
Peak memory 191696 kb
Host smart-775e59f1-48fe-49fe-be23-3b848ed85e6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198020429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3198020429
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3691482801
Short name T408
Test name
Test status
Simulation time 35129325 ps
CPU time 0.62 seconds
Started Jan 21 07:33:10 PM PST 24
Finished Jan 21 07:33:13 PM PST 24
Peak memory 182948 kb
Host smart-b3c3188e-7eb5-4ac4-9408-9c263987d04b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691482801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3691482801
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3529412747
Short name T396
Test name
Test status
Simulation time 70527034 ps
CPU time 0.58 seconds
Started Jan 21 07:33:09 PM PST 24
Finished Jan 21 07:33:13 PM PST 24
Peak memory 183084 kb
Host smart-969b8ced-5157-4e6a-aeaf-9ba5c74c9f34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529412747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.3529412747
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2679997592
Short name T477
Test name
Test status
Simulation time 57259454 ps
CPU time 0.69 seconds
Started Jan 21 07:33:11 PM PST 24
Finished Jan 21 07:33:15 PM PST 24
Peak memory 193588 kb
Host smart-9c514b8a-aaac-4162-b95b-f1c920805469
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679997592 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2679997592
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3884830596
Short name T435
Test name
Test status
Simulation time 29179262 ps
CPU time 0.54 seconds
Started Jan 21 07:33:07 PM PST 24
Finished Jan 21 07:33:10 PM PST 24
Peak memory 182508 kb
Host smart-865df751-8928-49a2-b748-4211380ae5f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884830596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3884830596
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.602308379
Short name T438
Test name
Test status
Simulation time 69813570 ps
CPU time 0.54 seconds
Started Jan 21 07:33:07 PM PST 24
Finished Jan 21 07:33:09 PM PST 24
Peak memory 181792 kb
Host smart-26931e9d-305b-4bb5-ab5a-d5fcc123a8af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602308379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.602308379
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3158486696
Short name T463
Test name
Test status
Simulation time 48504908 ps
CPU time 0.7 seconds
Started Jan 21 07:33:24 PM PST 24
Finished Jan 21 07:33:27 PM PST 24
Peak memory 191936 kb
Host smart-4fa866af-ea8b-4b1e-856d-3936f40c803e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158486696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.3158486696
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.938035182
Short name T378
Test name
Test status
Simulation time 24203234 ps
CPU time 1.27 seconds
Started Jan 21 07:33:12 PM PST 24
Finished Jan 21 07:33:16 PM PST 24
Peak memory 197688 kb
Host smart-21a9cb47-dae5-476a-b23a-38e3776368b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938035182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.938035182
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2048672640
Short name T88
Test name
Test status
Simulation time 48905615 ps
CPU time 0.83 seconds
Started Jan 21 07:33:09 PM PST 24
Finished Jan 21 07:33:13 PM PST 24
Peak memory 183152 kb
Host smart-646f5d7f-255a-44ec-ac93-c6d8bcf27a2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048672640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2048672640
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2264382272
Short name T43
Test name
Test status
Simulation time 37454257 ps
CPU time 0.87 seconds
Started Jan 21 07:33:23 PM PST 24
Finished Jan 21 07:33:27 PM PST 24
Peak memory 183032 kb
Host smart-87229b0e-3a40-49d3-af49-7296320dd7c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264382272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.2264382272
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2340020260
Short name T380
Test name
Test status
Simulation time 63972855 ps
CPU time 2.46 seconds
Started Jan 21 07:33:22 PM PST 24
Finished Jan 21 07:33:27 PM PST 24
Peak memory 192552 kb
Host smart-b761177c-f146-4e2d-ba6a-202cadc0b488
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340020260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2340020260
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.4226760437
Short name T65
Test name
Test status
Simulation time 26116963 ps
CPU time 0.54 seconds
Started Jan 21 07:33:17 PM PST 24
Finished Jan 21 07:33:21 PM PST 24
Peak memory 182328 kb
Host smart-329cf3e7-503e-45e8-b3a8-b93a792c8432
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226760437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.4226760437
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2104276529
Short name T424
Test name
Test status
Simulation time 174953843 ps
CPU time 0.74 seconds
Started Jan 21 07:33:21 PM PST 24
Finished Jan 21 07:33:24 PM PST 24
Peak memory 195376 kb
Host smart-bc44d414-e754-448e-83e1-2b5153e696f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104276529 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2104276529
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3864860883
Short name T474
Test name
Test status
Simulation time 20607228 ps
CPU time 0.55 seconds
Started Jan 21 07:33:15 PM PST 24
Finished Jan 21 07:33:20 PM PST 24
Peak memory 182496 kb
Host smart-1376fe89-fa36-4294-89a7-d154c8b317a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864860883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3864860883
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2517746458
Short name T433
Test name
Test status
Simulation time 18100460 ps
CPU time 0.55 seconds
Started Jan 21 08:49:45 PM PST 24
Finished Jan 21 08:50:04 PM PST 24
Peak memory 182292 kb
Host smart-9281a539-70ab-423a-b946-3ed4e7eb7ac1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517746458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2517746458
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3972688400
Short name T86
Test name
Test status
Simulation time 32816492 ps
CPU time 0.73 seconds
Started Jan 21 07:33:20 PM PST 24
Finished Jan 21 07:33:23 PM PST 24
Peak memory 193328 kb
Host smart-7ee761f7-bbe5-4e46-ae79-913803c0d899
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972688400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.3972688400
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.18517554
Short name T59
Test name
Test status
Simulation time 85072462 ps
CPU time 2.05 seconds
Started Jan 21 09:57:29 PM PST 24
Finished Jan 21 09:57:33 PM PST 24
Peak memory 197876 kb
Host smart-f6756349-6a2b-4832-a40f-2724289f946f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18517554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.18517554
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2450286715
Short name T415
Test name
Test status
Simulation time 28411135 ps
CPU time 0.84 seconds
Started Jan 21 07:33:44 PM PST 24
Finished Jan 21 07:33:50 PM PST 24
Peak memory 197136 kb
Host smart-e9791507-173b-49c4-9f2c-da028c5996b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450286715 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2450286715
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3083533490
Short name T68
Test name
Test status
Simulation time 19487202 ps
CPU time 0.61 seconds
Started Jan 21 07:33:46 PM PST 24
Finished Jan 21 07:33:52 PM PST 24
Peak memory 182844 kb
Host smart-2711e5cf-0646-4170-a793-4c982981f6da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083533490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3083533490
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2160402891
Short name T381
Test name
Test status
Simulation time 13519643 ps
CPU time 0.56 seconds
Started Jan 21 07:33:38 PM PST 24
Finished Jan 21 07:33:43 PM PST 24
Peak memory 182592 kb
Host smart-7fbb739a-9dd0-4c3b-8ea3-57d401876e4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160402891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2160402891
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2968189135
Short name T85
Test name
Test status
Simulation time 29114527 ps
CPU time 0.77 seconds
Started Jan 21 07:33:46 PM PST 24
Finished Jan 21 07:33:52 PM PST 24
Peak memory 191924 kb
Host smart-c1295068-f8af-4a20-ade8-43d2caebe2af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968189135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2968189135
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2674666586
Short name T476
Test name
Test status
Simulation time 81247428 ps
CPU time 2.88 seconds
Started Jan 21 07:33:43 PM PST 24
Finished Jan 21 07:33:51 PM PST 24
Peak memory 197820 kb
Host smart-ee3bed28-ed5b-44aa-871b-c3c7d87fb6c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674666586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.2674666586
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2103860296
Short name T482
Test name
Test status
Simulation time 271004481 ps
CPU time 1.11 seconds
Started Jan 21 07:33:36 PM PST 24
Finished Jan 21 07:33:42 PM PST 24
Peak memory 195164 kb
Host smart-8aab9a14-7bc9-42c1-9e5c-3cc71af4ef4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103860296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.2103860296
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2600749084
Short name T54
Test name
Test status
Simulation time 18445070 ps
CPU time 0.66 seconds
Started Jan 21 07:33:46 PM PST 24
Finished Jan 21 07:33:52 PM PST 24
Peak memory 193628 kb
Host smart-1e9f59d7-6b9a-4ad4-aa12-4468c9c1d57f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600749084 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2600749084
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3043554099
Short name T453
Test name
Test status
Simulation time 80296575 ps
CPU time 0.61 seconds
Started Jan 21 07:33:53 PM PST 24
Finished Jan 21 07:33:59 PM PST 24
Peak memory 183012 kb
Host smart-cd65a539-655c-4d38-bd58-1e4c247e69f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043554099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3043554099
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2494598999
Short name T413
Test name
Test status
Simulation time 37479583 ps
CPU time 0.6 seconds
Started Jan 21 07:33:51 PM PST 24
Finished Jan 21 07:33:55 PM PST 24
Peak memory 181812 kb
Host smart-8875f6bd-52b1-430d-b08f-a2d6f8ffb7a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494598999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2494598999
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1386616110
Short name T472
Test name
Test status
Simulation time 53358336 ps
CPU time 0.66 seconds
Started Jan 21 07:33:47 PM PST 24
Finished Jan 21 07:33:53 PM PST 24
Peak memory 192228 kb
Host smart-389b9a39-4ced-45c6-96ad-cac174460ccc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386616110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.1386616110
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2905769200
Short name T449
Test name
Test status
Simulation time 50632477 ps
CPU time 1.15 seconds
Started Jan 21 07:33:49 PM PST 24
Finished Jan 21 07:33:55 PM PST 24
Peak memory 197524 kb
Host smart-51cb796b-eb14-4c96-aaa7-9ee2fb904050
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905769200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2905769200
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2292134595
Short name T470
Test name
Test status
Simulation time 70852263 ps
CPU time 1.1 seconds
Started Jan 21 07:33:43 PM PST 24
Finished Jan 21 07:33:49 PM PST 24
Peak memory 195176 kb
Host smart-9a3dbf11-84b5-46bd-aa1e-3eb62c531190
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292134595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.2292134595
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3245434873
Short name T38
Test name
Test status
Simulation time 30488727 ps
CPU time 0.92 seconds
Started Jan 21 07:33:46 PM PST 24
Finished Jan 21 07:33:52 PM PST 24
Peak memory 196064 kb
Host smart-f09e38a0-fe43-48be-9c18-7a8aef5021f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245434873 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3245434873
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2391192536
Short name T439
Test name
Test status
Simulation time 37441773 ps
CPU time 0.55 seconds
Started Jan 21 07:33:48 PM PST 24
Finished Jan 21 07:33:53 PM PST 24
Peak memory 183036 kb
Host smart-bb52a182-9aa5-4bf9-9290-d857ff822286
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391192536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2391192536
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1354014662
Short name T364
Test name
Test status
Simulation time 11148683 ps
CPU time 0.54 seconds
Started Jan 21 07:33:44 PM PST 24
Finished Jan 21 07:33:50 PM PST 24
Peak memory 182240 kb
Host smart-734a9b80-2321-4d7f-8450-045344818164
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354014662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1354014662
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1842190891
Short name T446
Test name
Test status
Simulation time 18677940 ps
CPU time 0.62 seconds
Started Jan 21 07:33:46 PM PST 24
Finished Jan 21 07:33:51 PM PST 24
Peak memory 191696 kb
Host smart-6bcd0b10-6abe-44e2-8b2e-2b97f4e51ff8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842190891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1842190891
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.555576699
Short name T436
Test name
Test status
Simulation time 186084871 ps
CPU time 2.02 seconds
Started Jan 21 07:33:46 PM PST 24
Finished Jan 21 07:33:53 PM PST 24
Peak memory 197668 kb
Host smart-b7224801-b757-4a5f-a1f7-822699c7ac8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555576699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.555576699
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.516891095
Short name T386
Test name
Test status
Simulation time 49883367 ps
CPU time 0.86 seconds
Started Jan 21 07:33:56 PM PST 24
Finished Jan 21 07:34:01 PM PST 24
Peak memory 193780 kb
Host smart-97a0aa96-0336-40ff-aadb-a17c244a231b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516891095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_in
tg_err.516891095
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.4052954657
Short name T444
Test name
Test status
Simulation time 25734061 ps
CPU time 1.19 seconds
Started Jan 21 07:33:49 PM PST 24
Finished Jan 21 07:33:55 PM PST 24
Peak memory 198092 kb
Host smart-6d912e46-72ef-4140-a1d0-8c67e7d392c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052954657 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.4052954657
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1286937876
Short name T78
Test name
Test status
Simulation time 84769574 ps
CPU time 0.58 seconds
Started Jan 21 07:33:56 PM PST 24
Finished Jan 21 07:34:01 PM PST 24
Peak memory 183040 kb
Host smart-71d5a6c5-3f16-4883-9fa5-a58fa21705bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286937876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1286937876
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.842633249
Short name T387
Test name
Test status
Simulation time 14619705 ps
CPU time 0.57 seconds
Started Jan 21 07:33:52 PM PST 24
Finished Jan 21 07:33:57 PM PST 24
Peak memory 182568 kb
Host smart-6417ba1e-fc52-4a8b-8b87-afe027908c39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842633249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.842633249
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1668158874
Short name T483
Test name
Test status
Simulation time 47130612 ps
CPU time 0.75 seconds
Started Jan 21 07:33:48 PM PST 24
Finished Jan 21 07:33:54 PM PST 24
Peak memory 193360 kb
Host smart-a2b3c61f-c104-4a0b-9771-fdb1e7f50801
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668158874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1668158874
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.899006792
Short name T430
Test name
Test status
Simulation time 37797499 ps
CPU time 1.79 seconds
Started Jan 21 07:33:53 PM PST 24
Finished Jan 21 07:34:00 PM PST 24
Peak memory 197820 kb
Host smart-501fb82f-1258-4556-b797-2c92e235a349
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899006792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.899006792
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2195592433
Short name T465
Test name
Test status
Simulation time 148760122 ps
CPU time 1.14 seconds
Started Jan 21 07:33:46 PM PST 24
Finished Jan 21 07:33:52 PM PST 24
Peak memory 195284 kb
Host smart-ec66c828-6c6b-4a9c-bffe-4f913799387a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195592433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2195592433
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2193804257
Short name T372
Test name
Test status
Simulation time 21627536 ps
CPU time 0.83 seconds
Started Jan 21 07:33:54 PM PST 24
Finished Jan 21 07:33:59 PM PST 24
Peak memory 195280 kb
Host smart-b09a3c71-3a2c-45ff-9d50-aaae584cc69e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193804257 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2193804257
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3516437077
Short name T475
Test name
Test status
Simulation time 59870132 ps
CPU time 0.64 seconds
Started Jan 21 07:33:53 PM PST 24
Finished Jan 21 07:33:59 PM PST 24
Peak memory 183012 kb
Host smart-75897e8a-cfbb-48ed-bea8-6b7ca18334c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516437077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3516437077
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1603210365
Short name T425
Test name
Test status
Simulation time 50922405 ps
CPU time 0.57 seconds
Started Jan 21 07:33:56 PM PST 24
Finished Jan 21 07:34:01 PM PST 24
Peak memory 182624 kb
Host smart-f18358fc-e64c-4b9b-b271-ad526586cac2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603210365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1603210365
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3582037100
Short name T81
Test name
Test status
Simulation time 33093892 ps
CPU time 0.74 seconds
Started Jan 21 07:33:51 PM PST 24
Finished Jan 21 07:33:56 PM PST 24
Peak memory 193372 kb
Host smart-fe50675f-bc18-4827-917f-8895ef986183
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582037100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3582037100
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.933425728
Short name T478
Test name
Test status
Simulation time 208054075 ps
CPU time 2.8 seconds
Started Jan 21 07:33:48 PM PST 24
Finished Jan 21 07:33:56 PM PST 24
Peak memory 198084 kb
Host smart-2d6b2a02-c32f-4687-9835-3f2825588e75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933425728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.933425728
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.4139519413
Short name T462
Test name
Test status
Simulation time 488267987 ps
CPU time 1.18 seconds
Started Jan 21 07:33:49 PM PST 24
Finished Jan 21 07:33:55 PM PST 24
Peak memory 195348 kb
Host smart-996eaf5c-51ef-4f30-8ce3-1f3801feed58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139519413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.4139519413
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3638475880
Short name T479
Test name
Test status
Simulation time 32330601 ps
CPU time 0.86 seconds
Started Jan 21 07:33:55 PM PST 24
Finished Jan 21 07:34:00 PM PST 24
Peak memory 197164 kb
Host smart-c037b921-1228-4400-bedf-b1a66291c04b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638475880 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3638475880
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2082028215
Short name T382
Test name
Test status
Simulation time 32737081 ps
CPU time 0.59 seconds
Started Jan 21 07:34:03 PM PST 24
Finished Jan 21 07:34:07 PM PST 24
Peak memory 182536 kb
Host smart-fdb8b326-05f4-4104-84c8-4853e9c25f24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082028215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2082028215
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2039627211
Short name T427
Test name
Test status
Simulation time 12025386 ps
CPU time 0.56 seconds
Started Jan 21 08:12:18 PM PST 24
Finished Jan 21 08:12:23 PM PST 24
Peak memory 182720 kb
Host smart-8df6f9df-9d58-46f7-9848-13d36d36f5ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039627211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2039627211
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1643249289
Short name T45
Test name
Test status
Simulation time 612166521 ps
CPU time 0.85 seconds
Started Jan 21 07:34:03 PM PST 24
Finished Jan 21 07:34:08 PM PST 24
Peak memory 191968 kb
Host smart-1fed0b51-d0b5-4137-85e8-193e9bedb115
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643249289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.1643249289
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3739454637
Short name T375
Test name
Test status
Simulation time 164590859 ps
CPU time 2.28 seconds
Started Jan 21 07:33:54 PM PST 24
Finished Jan 21 07:34:01 PM PST 24
Peak memory 197732 kb
Host smart-4aa93d87-9f60-47d3-97ea-ce1d1fd85e40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739454637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3739454637
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2790227792
Short name T403
Test name
Test status
Simulation time 128592071 ps
CPU time 1.57 seconds
Started Jan 21 07:34:03 PM PST 24
Finished Jan 21 07:34:09 PM PST 24
Peak memory 183344 kb
Host smart-9d1c6b46-6c62-4468-8dd9-6e2dbbc76d0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790227792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2790227792
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2065423412
Short name T417
Test name
Test status
Simulation time 28698852 ps
CPU time 0.89 seconds
Started Jan 21 10:00:57 PM PST 24
Finished Jan 21 10:01:02 PM PST 24
Peak memory 196784 kb
Host smart-c3d9cf00-db5d-49cb-8906-e4ba03680ba8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065423412 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2065423412
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.4267928682
Short name T44
Test name
Test status
Simulation time 52993001 ps
CPU time 0.6 seconds
Started Jan 21 07:33:52 PM PST 24
Finished Jan 21 07:33:57 PM PST 24
Peak memory 183048 kb
Host smart-28c0cc80-15d7-43e3-83cd-f5392417475e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267928682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.4267928682
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2303745281
Short name T421
Test name
Test status
Simulation time 56653853 ps
CPU time 0.56 seconds
Started Jan 21 07:33:55 PM PST 24
Finished Jan 21 07:34:00 PM PST 24
Peak memory 182668 kb
Host smart-9baf99c4-a706-4a47-baa4-ba0382e11624
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303745281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2303745281
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3726408768
Short name T83
Test name
Test status
Simulation time 122987540 ps
CPU time 0.79 seconds
Started Jan 21 07:33:56 PM PST 24
Finished Jan 21 07:34:01 PM PST 24
Peak memory 193360 kb
Host smart-0ede00d4-ea42-4055-9370-c701170d6fd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726408768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.3726408768
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2716332773
Short name T369
Test name
Test status
Simulation time 69523345 ps
CPU time 1.59 seconds
Started Jan 21 07:55:02 PM PST 24
Finished Jan 21 07:55:04 PM PST 24
Peak memory 197884 kb
Host smart-223d759b-8521-45dc-a935-f7a8061d2cf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716332773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2716332773
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3706387037
Short name T406
Test name
Test status
Simulation time 171944182 ps
CPU time 1.24 seconds
Started Jan 21 07:33:56 PM PST 24
Finished Jan 21 07:34:02 PM PST 24
Peak memory 195272 kb
Host smart-87b8d1d9-41c6-4853-8c9b-b82693665847
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706387037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3706387037
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1012627680
Short name T401
Test name
Test status
Simulation time 62079220 ps
CPU time 0.74 seconds
Started Jan 21 08:10:26 PM PST 24
Finished Jan 21 08:10:29 PM PST 24
Peak memory 191432 kb
Host smart-4541dbb9-7906-4757-80ad-a38e7b6d5597
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012627680 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1012627680
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3983830481
Short name T70
Test name
Test status
Simulation time 12024937 ps
CPU time 0.6 seconds
Started Jan 21 08:12:19 PM PST 24
Finished Jan 21 08:12:24 PM PST 24
Peak memory 183068 kb
Host smart-15818ff4-a0cb-49d8-bb41-ce2104d63478
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983830481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.3983830481
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3666015170
Short name T56
Test name
Test status
Simulation time 13380599 ps
CPU time 0.56 seconds
Started Jan 21 07:33:55 PM PST 24
Finished Jan 21 07:34:01 PM PST 24
Peak memory 181716 kb
Host smart-05b0d68d-9eba-41f0-a601-cc3f43570fcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666015170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3666015170
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1345182673
Short name T63
Test name
Test status
Simulation time 61863151 ps
CPU time 0.72 seconds
Started Jan 21 07:33:46 PM PST 24
Finished Jan 21 07:33:52 PM PST 24
Peak memory 193320 kb
Host smart-5b9878a5-9af1-43c3-a491-74e8fad011f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345182673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.1345182673
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2793850287
Short name T390
Test name
Test status
Simulation time 24395472 ps
CPU time 1.33 seconds
Started Jan 21 07:33:56 PM PST 24
Finished Jan 21 07:34:02 PM PST 24
Peak memory 197876 kb
Host smart-7f9b63a3-6a95-45b2-8e52-d6efeaf12706
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793850287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2793850287
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.4009801826
Short name T410
Test name
Test status
Simulation time 36687960 ps
CPU time 1.02 seconds
Started Jan 21 07:33:59 PM PST 24
Finished Jan 21 07:34:06 PM PST 24
Peak memory 196964 kb
Host smart-577156bc-09a1-44b6-91e5-bc706712b5f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009801826 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.4009801826
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.4071068645
Short name T385
Test name
Test status
Simulation time 14288387 ps
CPU time 0.58 seconds
Started Jan 21 08:10:38 PM PST 24
Finished Jan 21 08:10:40 PM PST 24
Peak memory 183036 kb
Host smart-fdd294b8-6d5e-439f-90e7-349313f232b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071068645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.4071068645
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.4254164532
Short name T402
Test name
Test status
Simulation time 68048840 ps
CPU time 0.53 seconds
Started Jan 21 08:08:18 PM PST 24
Finished Jan 21 08:08:20 PM PST 24
Peak memory 182228 kb
Host smart-7ab8d251-6e97-4c11-aeb4-0ace278ced38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254164532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.4254164532
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.386878769
Short name T368
Test name
Test status
Simulation time 212931973 ps
CPU time 1.3 seconds
Started Jan 21 07:51:57 PM PST 24
Finished Jan 21 07:52:00 PM PST 24
Peak memory 197060 kb
Host smart-9147f8b1-a16e-4738-81e5-5692812805de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386878769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.386878769
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3474722300
Short name T32
Test name
Test status
Simulation time 121666064 ps
CPU time 1.39 seconds
Started Jan 21 09:52:15 PM PST 24
Finished Jan 21 09:52:17 PM PST 24
Peak memory 195420 kb
Host smart-15d7e276-4d9b-4aa5-80ff-513f411b6c53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474722300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.3474722300
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2712811603
Short name T14
Test name
Test status
Simulation time 88049062 ps
CPU time 0.86 seconds
Started Jan 21 07:33:57 PM PST 24
Finished Jan 21 07:34:03 PM PST 24
Peak memory 197648 kb
Host smart-978af3d6-1546-4f8d-a90b-d18d07333b4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712811603 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2712811603
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3177383264
Short name T457
Test name
Test status
Simulation time 22474676 ps
CPU time 0.62 seconds
Started Jan 21 07:33:57 PM PST 24
Finished Jan 21 07:34:01 PM PST 24
Peak memory 183084 kb
Host smart-864919c8-29e2-4353-88ad-4ea6b9019a0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177383264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.3177383264
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2914462735
Short name T471
Test name
Test status
Simulation time 52132112 ps
CPU time 0.63 seconds
Started Jan 21 07:33:59 PM PST 24
Finished Jan 21 07:34:06 PM PST 24
Peak memory 182672 kb
Host smart-cc27e24e-cf10-4f2a-895f-b356b4042f89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914462735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2914462735
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.378853341
Short name T84
Test name
Test status
Simulation time 162441058 ps
CPU time 0.85 seconds
Started Jan 21 07:33:57 PM PST 24
Finished Jan 21 07:34:02 PM PST 24
Peak memory 193424 kb
Host smart-13d9a7e1-4300-43e5-9517-ed0eea05d64a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378853341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_ti
mer_same_csr_outstanding.378853341
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.558786391
Short name T58
Test name
Test status
Simulation time 41615274 ps
CPU time 2.2 seconds
Started Jan 21 07:34:07 PM PST 24
Finished Jan 21 07:34:10 PM PST 24
Peak memory 197144 kb
Host smart-3dfd6ce7-4ebc-4d94-becb-098cc6cdee2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558786391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.558786391
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1703681946
Short name T423
Test name
Test status
Simulation time 50878785 ps
CPU time 0.89 seconds
Started Jan 21 07:34:07 PM PST 24
Finished Jan 21 07:34:09 PM PST 24
Peak memory 182620 kb
Host smart-899ff3ac-df3a-4713-b321-1f405520e26b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703681946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1703681946
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.12650589
Short name T458
Test name
Test status
Simulation time 423054882 ps
CPU time 0.7 seconds
Started Jan 21 07:33:15 PM PST 24
Finished Jan 21 07:33:21 PM PST 24
Peak memory 183012 kb
Host smart-f18a2f4f-ea71-4415-8199-0e0adf48118a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12650589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_aliasi
ng.12650589
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1349295543
Short name T428
Test name
Test status
Simulation time 161463791 ps
CPU time 2.47 seconds
Started Jan 21 07:33:24 PM PST 24
Finished Jan 21 07:33:29 PM PST 24
Peak memory 192452 kb
Host smart-a034fb5d-66c0-4693-84cb-7d15dc078d2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349295543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1349295543
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.4233642475
Short name T467
Test name
Test status
Simulation time 38024782 ps
CPU time 0.59 seconds
Started Jan 21 07:33:17 PM PST 24
Finished Jan 21 07:33:21 PM PST 24
Peak memory 182380 kb
Host smart-2c68218d-b367-4558-956d-a4829caa800b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233642475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.4233642475
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1859312974
Short name T448
Test name
Test status
Simulation time 27369180 ps
CPU time 0.95 seconds
Started Jan 21 07:33:24 PM PST 24
Finished Jan 21 07:33:27 PM PST 24
Peak memory 197616 kb
Host smart-8467a106-303d-4e76-a109-4f44cd757c2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859312974 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1859312974
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3382478702
Short name T16
Test name
Test status
Simulation time 23595264 ps
CPU time 0.57 seconds
Started Jan 21 07:33:20 PM PST 24
Finished Jan 21 07:33:23 PM PST 24
Peak memory 183040 kb
Host smart-eda97385-f0d9-4d48-9132-07ca4b54b7d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382478702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3382478702
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2383126757
Short name T371
Test name
Test status
Simulation time 144816477 ps
CPU time 0.57 seconds
Started Jan 21 07:33:20 PM PST 24
Finished Jan 21 07:33:23 PM PST 24
Peak memory 182692 kb
Host smart-c8a4c209-b513-4cb9-90c0-90ea2ca34326
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383126757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2383126757
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1515984259
Short name T469
Test name
Test status
Simulation time 28675066 ps
CPU time 0.82 seconds
Started Jan 21 07:33:19 PM PST 24
Finished Jan 21 07:33:23 PM PST 24
Peak memory 193380 kb
Host smart-62bbea20-98cf-4604-a18c-1b1ed4488ce0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515984259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.1515984259
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2766990924
Short name T473
Test name
Test status
Simulation time 110220509 ps
CPU time 1.58 seconds
Started Jan 21 07:33:20 PM PST 24
Finished Jan 21 07:33:24 PM PST 24
Peak memory 197480 kb
Host smart-7aacffcc-56e0-4839-9941-d79bc8361994
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766990924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2766990924
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2742189890
Short name T450
Test name
Test status
Simulation time 192124831 ps
CPU time 1.36 seconds
Started Jan 21 07:33:14 PM PST 24
Finished Jan 21 07:33:20 PM PST 24
Peak memory 183276 kb
Host smart-71576528-fcef-41b9-8128-a16334a9ee56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742189890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2742189890
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3861152221
Short name T374
Test name
Test status
Simulation time 45154509 ps
CPU time 0.58 seconds
Started Jan 21 07:33:55 PM PST 24
Finished Jan 21 07:34:01 PM PST 24
Peak memory 182600 kb
Host smart-8c1dffcc-f922-4dd7-9168-1768f2c814b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861152221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3861152221
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1654600642
Short name T452
Test name
Test status
Simulation time 44175703 ps
CPU time 0.55 seconds
Started Jan 21 07:33:57 PM PST 24
Finished Jan 21 07:34:03 PM PST 24
Peak memory 182624 kb
Host smart-c7aa652b-45c3-4216-8408-8161fa372bd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654600642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1654600642
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.949896178
Short name T365
Test name
Test status
Simulation time 16291302 ps
CPU time 0.62 seconds
Started Jan 21 07:33:56 PM PST 24
Finished Jan 21 07:34:01 PM PST 24
Peak memory 182776 kb
Host smart-88efe200-83c0-45f0-afa7-20f5d9e0e3fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949896178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.949896178
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.639118079
Short name T73
Test name
Test status
Simulation time 17142049 ps
CPU time 0.62 seconds
Started Jan 21 07:33:59 PM PST 24
Finished Jan 21 07:34:06 PM PST 24
Peak memory 182612 kb
Host smart-dee828cc-e462-4da6-9be2-22502348db00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639118079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.639118079
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.461124881
Short name T454
Test name
Test status
Simulation time 12883321 ps
CPU time 0.59 seconds
Started Jan 21 07:55:23 PM PST 24
Finished Jan 21 07:55:25 PM PST 24
Peak memory 182584 kb
Host smart-c04c72d3-d29d-4bfa-a473-4d3e74df3346
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461124881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.461124881
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.284737479
Short name T464
Test name
Test status
Simulation time 32737242 ps
CPU time 0.54 seconds
Started Jan 21 07:33:57 PM PST 24
Finished Jan 21 07:34:01 PM PST 24
Peak memory 181756 kb
Host smart-112e7d13-72e6-47a4-b4c6-43ac05d4ec5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284737479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.284737479
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.414745708
Short name T392
Test name
Test status
Simulation time 14741566 ps
CPU time 0.55 seconds
Started Jan 21 07:33:57 PM PST 24
Finished Jan 21 07:34:01 PM PST 24
Peak memory 182604 kb
Host smart-5772caa2-e49e-4730-9cc4-d2ab2ccdff2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414745708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.414745708
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3279811930
Short name T376
Test name
Test status
Simulation time 14629364 ps
CPU time 0.56 seconds
Started Jan 21 07:33:57 PM PST 24
Finished Jan 21 07:34:02 PM PST 24
Peak memory 182788 kb
Host smart-8c1ed3a9-6b4e-43dc-82d9-14c65aaa2a4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279811930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3279811930
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1664602819
Short name T373
Test name
Test status
Simulation time 55153180 ps
CPU time 0.56 seconds
Started Jan 21 08:03:04 PM PST 24
Finished Jan 21 08:03:26 PM PST 24
Peak memory 182728 kb
Host smart-f9db2763-9fd8-46df-ba2e-a741cbae9209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664602819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1664602819
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2679492557
Short name T72
Test name
Test status
Simulation time 15776923 ps
CPU time 0.61 seconds
Started Jan 21 08:25:09 PM PST 24
Finished Jan 21 08:25:11 PM PST 24
Peak memory 182632 kb
Host smart-f264ec45-e064-4ba0-a900-e9d0e99d0729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679492557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2679492557
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3881892920
Short name T69
Test name
Test status
Simulation time 33173834 ps
CPU time 0.81 seconds
Started Jan 21 09:25:09 PM PST 24
Finished Jan 21 09:25:16 PM PST 24
Peak memory 183020 kb
Host smart-2ed5ca53-6460-49d5-8580-357f3875d220
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881892920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3881892920
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2249352351
Short name T67
Test name
Test status
Simulation time 1469472023 ps
CPU time 3.81 seconds
Started Jan 21 07:33:24 PM PST 24
Finished Jan 21 07:33:30 PM PST 24
Peak memory 191412 kb
Host smart-b0c11740-c713-43ba-a73e-0cb4de25e69d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249352351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2249352351
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2331305260
Short name T422
Test name
Test status
Simulation time 37029120 ps
CPU time 0.54 seconds
Started Jan 21 07:33:19 PM PST 24
Finished Jan 21 07:33:23 PM PST 24
Peak memory 183028 kb
Host smart-6326304d-61c4-4fdb-9b77-4842d963b7c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331305260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.2331305260
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2365009170
Short name T389
Test name
Test status
Simulation time 152963903 ps
CPU time 1.53 seconds
Started Jan 21 08:12:10 PM PST 24
Finished Jan 21 08:12:14 PM PST 24
Peak memory 191604 kb
Host smart-bdbd884a-d48d-4b0a-bb02-020ec475f469
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365009170 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2365009170
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2947967778
Short name T399
Test name
Test status
Simulation time 28796887 ps
CPU time 0.53 seconds
Started Jan 21 07:33:29 PM PST 24
Finished Jan 21 07:33:34 PM PST 24
Peak memory 182456 kb
Host smart-a5dade6f-8e8e-46e3-801f-cf0701612c18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947967778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2947967778
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.4207466757
Short name T432
Test name
Test status
Simulation time 74817941 ps
CPU time 0.56 seconds
Started Jan 21 07:33:16 PM PST 24
Finished Jan 21 07:33:21 PM PST 24
Peak memory 182656 kb
Host smart-09142372-b7a5-43a8-a85e-97d05aab62f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207466757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.4207466757
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1486199843
Short name T445
Test name
Test status
Simulation time 150201557 ps
CPU time 0.72 seconds
Started Jan 21 07:33:20 PM PST 24
Finished Jan 21 07:33:24 PM PST 24
Peak memory 192228 kb
Host smart-8c8e786b-50f5-4f87-9adc-f666b7182571
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486199843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1486199843
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3984627732
Short name T414
Test name
Test status
Simulation time 136412010 ps
CPU time 1.12 seconds
Started Jan 21 07:33:20 PM PST 24
Finished Jan 21 07:33:24 PM PST 24
Peak memory 195948 kb
Host smart-3c0f6f57-d6a4-45fb-a964-8d0b8bdac920
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984627732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3984627732
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2823169707
Short name T409
Test name
Test status
Simulation time 44644235 ps
CPU time 0.87 seconds
Started Jan 21 07:33:16 PM PST 24
Finished Jan 21 07:33:21 PM PST 24
Peak memory 193416 kb
Host smart-ba7d255b-7e5a-4882-bf9d-4c857a89e506
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823169707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2823169707
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1360188279
Short name T418
Test name
Test status
Simulation time 11918591 ps
CPU time 0.55 seconds
Started Jan 21 08:53:40 PM PST 24
Finished Jan 21 08:53:58 PM PST 24
Peak memory 182760 kb
Host smart-8c56684b-14ed-4288-a0c2-ac18fd7cc915
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360188279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1360188279
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1657603052
Short name T440
Test name
Test status
Simulation time 21529721 ps
CPU time 0.57 seconds
Started Jan 21 07:34:07 PM PST 24
Finished Jan 21 07:34:09 PM PST 24
Peak memory 182300 kb
Host smart-babbc86c-1668-4ded-b074-fd0eebc76185
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657603052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1657603052
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.421815978
Short name T79
Test name
Test status
Simulation time 61160428 ps
CPU time 0.53 seconds
Started Jan 21 07:33:57 PM PST 24
Finished Jan 21 07:34:01 PM PST 24
Peak memory 181820 kb
Host smart-47736f97-0075-461c-a225-20f8dc8c5f5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421815978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.421815978
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3259567487
Short name T481
Test name
Test status
Simulation time 12328533 ps
CPU time 0.58 seconds
Started Jan 21 07:34:09 PM PST 24
Finished Jan 21 07:34:12 PM PST 24
Peak memory 182732 kb
Host smart-011569a0-57ec-4bf6-b696-c466ab8549ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259567487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3259567487
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.671001177
Short name T395
Test name
Test status
Simulation time 14501472 ps
CPU time 0.61 seconds
Started Jan 21 07:34:05 PM PST 24
Finished Jan 21 07:34:08 PM PST 24
Peak memory 182620 kb
Host smart-9e36fe80-fa62-49a0-acf0-3fa9ae392740
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671001177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.671001177
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2658615175
Short name T407
Test name
Test status
Simulation time 43701695 ps
CPU time 0.51 seconds
Started Jan 21 07:34:04 PM PST 24
Finished Jan 21 07:34:08 PM PST 24
Peak memory 182236 kb
Host smart-b4cfa06e-89a0-4fdb-812f-1dafe6dcc743
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658615175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2658615175
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.117929884
Short name T456
Test name
Test status
Simulation time 64587920 ps
CPU time 0.57 seconds
Started Jan 21 07:34:03 PM PST 24
Finished Jan 21 07:34:07 PM PST 24
Peak memory 182664 kb
Host smart-ea584cdb-a0a6-46b9-8ef0-da422dfec41e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117929884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.117929884
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.884952227
Short name T434
Test name
Test status
Simulation time 36174556 ps
CPU time 0.6 seconds
Started Jan 21 07:34:01 PM PST 24
Finished Jan 21 07:34:07 PM PST 24
Peak memory 182720 kb
Host smart-9546f983-41f7-4413-947a-50750a12cc3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884952227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.884952227
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.4118471916
Short name T366
Test name
Test status
Simulation time 23578617 ps
CPU time 0.57 seconds
Started Jan 21 07:34:09 PM PST 24
Finished Jan 21 07:34:12 PM PST 24
Peak memory 182640 kb
Host smart-9f9c914a-c062-429f-b096-26a84f2f8939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118471916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.4118471916
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3640335948
Short name T412
Test name
Test status
Simulation time 36265787 ps
CPU time 0.56 seconds
Started Jan 21 07:34:10 PM PST 24
Finished Jan 21 07:34:13 PM PST 24
Peak memory 182656 kb
Host smart-e9ba8303-f1c2-4642-a449-a761eda4c49b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640335948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3640335948
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3035035823
Short name T74
Test name
Test status
Simulation time 33987542 ps
CPU time 0.81 seconds
Started Jan 21 07:33:29 PM PST 24
Finished Jan 21 07:33:34 PM PST 24
Peak memory 192664 kb
Host smart-b32c3749-d7ee-4b5e-b14a-0e7513fb246d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035035823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3035035823
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.495081773
Short name T397
Test name
Test status
Simulation time 412917262 ps
CPU time 3.75 seconds
Started Jan 21 07:33:30 PM PST 24
Finished Jan 21 07:33:38 PM PST 24
Peak memory 183196 kb
Host smart-f953c8df-f7c3-430e-a74a-b261b44d120e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495081773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_b
ash.495081773
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1775094146
Short name T60
Test name
Test status
Simulation time 13131052 ps
CPU time 0.6 seconds
Started Jan 21 07:33:30 PM PST 24
Finished Jan 21 07:33:35 PM PST 24
Peak memory 182404 kb
Host smart-5ade0130-3f56-48c1-9e3a-a55a2e65359e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775094146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1775094146
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.4109214079
Short name T420
Test name
Test status
Simulation time 106628493 ps
CPU time 1.22 seconds
Started Jan 21 07:33:30 PM PST 24
Finished Jan 21 07:33:35 PM PST 24
Peak memory 197820 kb
Host smart-6f99236b-0cfe-442d-b49d-6adacc689b3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109214079 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.4109214079
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3460666000
Short name T391
Test name
Test status
Simulation time 102132772 ps
CPU time 0.56 seconds
Started Jan 21 07:33:28 PM PST 24
Finished Jan 21 07:33:33 PM PST 24
Peak memory 183012 kb
Host smart-0f71b65d-1818-4378-8df2-b80504c5c13a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460666000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3460666000
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1991093676
Short name T419
Test name
Test status
Simulation time 33235442 ps
CPU time 0.58 seconds
Started Jan 21 07:33:30 PM PST 24
Finished Jan 21 07:33:35 PM PST 24
Peak memory 182600 kb
Host smart-82631f2a-06cc-4025-b801-ba3333fe09a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991093676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1991093676
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3455561883
Short name T82
Test name
Test status
Simulation time 32735325 ps
CPU time 0.79 seconds
Started Jan 21 07:33:29 PM PST 24
Finished Jan 21 07:33:34 PM PST 24
Peak memory 193348 kb
Host smart-431cdaa8-05e3-4f59-a3a4-3605056dda6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455561883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.3455561883
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2757300331
Short name T451
Test name
Test status
Simulation time 257353702 ps
CPU time 3.19 seconds
Started Jan 21 07:33:24 PM PST 24
Finished Jan 21 07:33:29 PM PST 24
Peak memory 197832 kb
Host smart-c374480a-37b5-47bc-a52f-d9807feb8974
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757300331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2757300331
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2955996412
Short name T398
Test name
Test status
Simulation time 109280300 ps
CPU time 1.32 seconds
Started Jan 21 07:33:29 PM PST 24
Finished Jan 21 07:33:35 PM PST 24
Peak memory 183380 kb
Host smart-41b782cf-15b1-45fe-9fcb-7387c461424c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955996412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2955996412
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.51467303
Short name T388
Test name
Test status
Simulation time 34107260 ps
CPU time 0.56 seconds
Started Jan 21 07:34:01 PM PST 24
Finished Jan 21 07:34:07 PM PST 24
Peak memory 182628 kb
Host smart-efb82109-6dd2-4c51-a2c3-cdad32ad70b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51467303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.51467303
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3227778117
Short name T468
Test name
Test status
Simulation time 15008130 ps
CPU time 0.57 seconds
Started Jan 21 07:34:07 PM PST 24
Finished Jan 21 07:34:10 PM PST 24
Peak memory 182228 kb
Host smart-19df4f96-dbac-4d9e-8053-820724448e86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227778117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3227778117
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1953010135
Short name T383
Test name
Test status
Simulation time 61577100 ps
CPU time 0.58 seconds
Started Jan 21 07:34:08 PM PST 24
Finished Jan 21 07:34:12 PM PST 24
Peak memory 182788 kb
Host smart-cc5fbef8-9335-418d-bf69-8a3096057878
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953010135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1953010135
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2704179141
Short name T455
Test name
Test status
Simulation time 11063513 ps
CPU time 0.55 seconds
Started Jan 21 07:33:59 PM PST 24
Finished Jan 21 07:34:06 PM PST 24
Peak memory 182596 kb
Host smart-3c899288-bef7-4d93-b992-e06522e39e2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704179141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2704179141
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1930412694
Short name T55
Test name
Test status
Simulation time 29869174 ps
CPU time 0.58 seconds
Started Jan 21 07:34:07 PM PST 24
Finished Jan 21 07:34:10 PM PST 24
Peak memory 182652 kb
Host smart-94e92c8e-3574-499d-91ca-062c0305849f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930412694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1930412694
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1310347639
Short name T377
Test name
Test status
Simulation time 39946444 ps
CPU time 0.58 seconds
Started Jan 21 07:34:00 PM PST 24
Finished Jan 21 07:34:06 PM PST 24
Peak memory 182680 kb
Host smart-170db5c0-50a3-4f69-a074-d5ab8ac7fc8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310347639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1310347639
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2670285245
Short name T429
Test name
Test status
Simulation time 50433734 ps
CPU time 0.59 seconds
Started Jan 21 07:34:01 PM PST 24
Finished Jan 21 07:34:07 PM PST 24
Peak memory 182772 kb
Host smart-c6fed08b-498c-4c14-8585-4cb4d4985d25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670285245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2670285245
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1373778885
Short name T384
Test name
Test status
Simulation time 20390068 ps
CPU time 0.58 seconds
Started Jan 21 07:34:03 PM PST 24
Finished Jan 21 07:34:08 PM PST 24
Peak memory 182744 kb
Host smart-b61c3aa4-3d29-472c-b36f-ddeefa942a85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373778885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1373778885
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.4223704215
Short name T394
Test name
Test status
Simulation time 107166859 ps
CPU time 0.62 seconds
Started Jan 21 07:34:03 PM PST 24
Finished Jan 21 07:34:08 PM PST 24
Peak memory 182644 kb
Host smart-1ad78eb0-7321-4032-a4dc-3f8547ced882
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223704215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.4223704215
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1330147033
Short name T71
Test name
Test status
Simulation time 13295073 ps
CPU time 0.57 seconds
Started Jan 21 07:34:12 PM PST 24
Finished Jan 21 07:34:14 PM PST 24
Peak memory 182612 kb
Host smart-b08a73ff-0c31-4730-a856-432120ccfa4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330147033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1330147033
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1338796498
Short name T405
Test name
Test status
Simulation time 41002460 ps
CPU time 0.96 seconds
Started Jan 21 07:33:27 PM PST 24
Finished Jan 21 07:33:31 PM PST 24
Peak memory 195388 kb
Host smart-01dba4e6-e159-42a9-8df9-986ec20aa28b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338796498 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1338796498
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.213613537
Short name T42
Test name
Test status
Simulation time 13565825 ps
CPU time 0.57 seconds
Started Jan 21 07:33:27 PM PST 24
Finished Jan 21 07:33:32 PM PST 24
Peak memory 182960 kb
Host smart-584685f0-695e-4650-9835-300e25b1faf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213613537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.213613537
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1595957232
Short name T367
Test name
Test status
Simulation time 45435537 ps
CPU time 0.59 seconds
Started Jan 21 07:33:28 PM PST 24
Finished Jan 21 07:33:33 PM PST 24
Peak memory 182636 kb
Host smart-6fe001c4-8b1b-4494-a904-5dbd0558d9e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595957232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1595957232
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2254996271
Short name T442
Test name
Test status
Simulation time 42930342 ps
CPU time 0.82 seconds
Started Jan 21 07:33:31 PM PST 24
Finished Jan 21 07:33:36 PM PST 24
Peak memory 193460 kb
Host smart-f76df9ce-753f-4b4f-9ca6-9ce26dd3793b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254996271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2254996271
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2349573155
Short name T480
Test name
Test status
Simulation time 983675832 ps
CPU time 1.69 seconds
Started Jan 21 07:33:29 PM PST 24
Finished Jan 21 07:33:35 PM PST 24
Peak memory 197756 kb
Host smart-c29a4152-b062-430f-91b6-4741c88dd433
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349573155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2349573155
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.265388777
Short name T466
Test name
Test status
Simulation time 377693611 ps
CPU time 1.36 seconds
Started Jan 21 07:33:27 PM PST 24
Finished Jan 21 07:33:33 PM PST 24
Peak memory 183252 kb
Host smart-b0842bf0-7a3f-4cf6-bacb-9f8df77e9118
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265388777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int
g_err.265388777
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2995120927
Short name T33
Test name
Test status
Simulation time 329403305 ps
CPU time 0.95 seconds
Started Jan 21 07:33:31 PM PST 24
Finished Jan 21 07:33:37 PM PST 24
Peak memory 195148 kb
Host smart-d4d05353-c29d-40d0-aacf-7e7f0ac1b47a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995120927 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2995120927
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.119914594
Short name T62
Test name
Test status
Simulation time 11306580 ps
CPU time 0.58 seconds
Started Jan 21 07:33:35 PM PST 24
Finished Jan 21 07:33:39 PM PST 24
Peak memory 183012 kb
Host smart-f2460838-8c8e-45c5-a0f9-f858aeab1656
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119914594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.119914594
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3331460735
Short name T416
Test name
Test status
Simulation time 16480225 ps
CPU time 0.56 seconds
Started Jan 21 07:33:31 PM PST 24
Finished Jan 21 07:33:36 PM PST 24
Peak memory 181844 kb
Host smart-ee6d3181-e0aa-40bc-baf0-8b25583bb42f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331460735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3331460735
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3622068103
Short name T460
Test name
Test status
Simulation time 37106125 ps
CPU time 0.78 seconds
Started Jan 21 07:33:35 PM PST 24
Finished Jan 21 07:33:39 PM PST 24
Peak memory 191968 kb
Host smart-13aae057-2c3b-4c09-86d9-215fffa83757
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622068103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3622068103
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.63531296
Short name T411
Test name
Test status
Simulation time 225079152 ps
CPU time 3.46 seconds
Started Jan 21 07:33:30 PM PST 24
Finished Jan 21 07:33:38 PM PST 24
Peak memory 197836 kb
Host smart-04637ecf-e7f4-43cf-b662-01c12d3ea31d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63531296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.63531296
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3423237695
Short name T443
Test name
Test status
Simulation time 89881757 ps
CPU time 0.88 seconds
Started Jan 21 07:33:25 PM PST 24
Finished Jan 21 07:33:27 PM PST 24
Peak memory 193768 kb
Host smart-32e56e88-070b-46d4-931c-66373db696eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423237695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.3423237695
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.834781348
Short name T40
Test name
Test status
Simulation time 41234988 ps
CPU time 0.78 seconds
Started Jan 21 07:33:35 PM PST 24
Finished Jan 21 07:33:39 PM PST 24
Peak memory 193368 kb
Host smart-de85e3a3-602c-4c2f-95e2-d74820ffd19b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834781348 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.834781348
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3008456710
Short name T61
Test name
Test status
Simulation time 18849759 ps
CPU time 0.61 seconds
Started Jan 21 07:33:36 PM PST 24
Finished Jan 21 07:33:41 PM PST 24
Peak memory 183024 kb
Host smart-a763c9fe-77bf-479e-ab17-2faffbbc7bd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008456710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3008456710
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2041095431
Short name T370
Test name
Test status
Simulation time 27362909 ps
CPU time 0.55 seconds
Started Jan 21 07:33:31 PM PST 24
Finished Jan 21 07:33:36 PM PST 24
Peak memory 182636 kb
Host smart-fc680837-45f8-4845-a698-f7e06c2e3f0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041095431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2041095431
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1160205652
Short name T41
Test name
Test status
Simulation time 27201708 ps
CPU time 0.73 seconds
Started Jan 21 07:33:35 PM PST 24
Finished Jan 21 07:33:39 PM PST 24
Peak memory 192252 kb
Host smart-7bef7711-2753-4b8d-9f9f-46517699f11e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160205652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1160205652
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.343129979
Short name T57
Test name
Test status
Simulation time 797846471 ps
CPU time 2.22 seconds
Started Jan 21 07:33:32 PM PST 24
Finished Jan 21 07:33:39 PM PST 24
Peak memory 197844 kb
Host smart-c41d2dcd-87cd-47c9-a403-d7b7155d944a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343129979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.343129979
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1879437811
Short name T431
Test name
Test status
Simulation time 54826506 ps
CPU time 0.9 seconds
Started Jan 21 07:33:35 PM PST 24
Finished Jan 21 07:33:40 PM PST 24
Peak memory 183228 kb
Host smart-48622c5f-3189-469e-a3a2-167e0cf5d17d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879437811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1879437811
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.507582630
Short name T404
Test name
Test status
Simulation time 88440965 ps
CPU time 1.04 seconds
Started Jan 21 07:33:33 PM PST 24
Finished Jan 21 07:33:39 PM PST 24
Peak memory 197624 kb
Host smart-f9a7ba67-f896-4947-b7fb-3718b5b88cf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507582630 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.507582630
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.645748978
Short name T66
Test name
Test status
Simulation time 24783917 ps
CPU time 0.6 seconds
Started Jan 21 07:33:35 PM PST 24
Finished Jan 21 07:33:39 PM PST 24
Peak memory 183004 kb
Host smart-aaa5d7b0-b168-4f53-91b0-73971387088d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645748978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.645748978
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.926787685
Short name T426
Test name
Test status
Simulation time 11750875 ps
CPU time 0.6 seconds
Started Jan 21 07:33:35 PM PST 24
Finished Jan 21 07:33:39 PM PST 24
Peak memory 182664 kb
Host smart-01351acd-289f-4021-b200-c22a6314dd2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926787685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.926787685
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3944898770
Short name T437
Test name
Test status
Simulation time 73895052 ps
CPU time 0.71 seconds
Started Jan 21 07:33:35 PM PST 24
Finished Jan 21 07:33:40 PM PST 24
Peak memory 191844 kb
Host smart-c65e754d-6d46-4a54-b828-76b2ae46a4db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944898770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.3944898770
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1628538690
Short name T461
Test name
Test status
Simulation time 126476270 ps
CPU time 1.89 seconds
Started Jan 21 07:33:38 PM PST 24
Finished Jan 21 07:33:45 PM PST 24
Peak memory 197840 kb
Host smart-d0f83b5b-3e2f-4b96-b54f-67f3a29bb1bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628538690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1628538690
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1644930724
Short name T89
Test name
Test status
Simulation time 161032526 ps
CPU time 0.85 seconds
Started Jan 21 07:33:34 PM PST 24
Finished Jan 21 07:33:39 PM PST 24
Peak memory 183100 kb
Host smart-8f852212-29a5-43e0-b840-db5528803665
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644930724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1644930724
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1264156979
Short name T400
Test name
Test status
Simulation time 21774378 ps
CPU time 1.05 seconds
Started Jan 21 07:33:39 PM PST 24
Finished Jan 21 07:33:44 PM PST 24
Peak memory 197656 kb
Host smart-13d81a75-7673-467e-9259-17f98db2e935
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264156979 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1264156979
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2652276273
Short name T379
Test name
Test status
Simulation time 43418743 ps
CPU time 0.59 seconds
Started Jan 21 07:33:39 PM PST 24
Finished Jan 21 07:33:44 PM PST 24
Peak memory 183076 kb
Host smart-70e1b4bf-8f6f-4523-a18a-c831104fa96c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652276273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2652276273
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1831578877
Short name T393
Test name
Test status
Simulation time 19059277 ps
CPU time 0.56 seconds
Started Jan 21 07:33:43 PM PST 24
Finished Jan 21 07:33:49 PM PST 24
Peak memory 182728 kb
Host smart-e7e9a34f-3a7f-41e8-8262-ee8d6f2f31bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831578877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1831578877
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1265426109
Short name T459
Test name
Test status
Simulation time 22110427 ps
CPU time 0.71 seconds
Started Jan 21 07:33:39 PM PST 24
Finished Jan 21 07:33:44 PM PST 24
Peak memory 192224 kb
Host smart-24168d39-2d33-4f40-8893-59d87a4e0558
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265426109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1265426109
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2749791142
Short name T441
Test name
Test status
Simulation time 76463575 ps
CPU time 1.98 seconds
Started Jan 21 07:33:31 PM PST 24
Finished Jan 21 07:33:37 PM PST 24
Peak memory 197820 kb
Host smart-2ca1d934-e6a6-4cc0-8143-f1660b2bd4b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749791142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2749791142
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3193387966
Short name T447
Test name
Test status
Simulation time 512522522 ps
CPU time 1.35 seconds
Started Jan 21 07:33:41 PM PST 24
Finished Jan 21 07:33:46 PM PST 24
Peak memory 195188 kb
Host smart-8179456f-f0f8-4a3e-afbe-541e662b2ecf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193387966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3193387966
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1846924942
Short name T238
Test name
Test status
Simulation time 272939981920 ps
CPU time 407.91 seconds
Started Jan 21 09:11:52 PM PST 24
Finished Jan 21 09:18:46 PM PST 24
Peak memory 183496 kb
Host smart-fefa33a2-7e0e-4872-806b-ed395e8e1203
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846924942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1846924942
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.4155988686
Short name T509
Test name
Test status
Simulation time 47265504204 ps
CPU time 68.94 seconds
Started Jan 21 09:11:48 PM PST 24
Finished Jan 21 09:13:01 PM PST 24
Peak memory 183432 kb
Host smart-95cb8727-fd42-4e78-9c68-3124f4ca399b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155988686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.4155988686
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.3546842877
Short name T306
Test name
Test status
Simulation time 128002312474 ps
CPU time 752.95 seconds
Started Jan 21 09:11:48 PM PST 24
Finished Jan 21 09:24:25 PM PST 24
Peak memory 191680 kb
Host smart-6b7cba2a-fd54-4852-b344-63d3901e0819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546842877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3546842877
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.412296992
Short name T353
Test name
Test status
Simulation time 156951006426 ps
CPU time 1266.73 seconds
Started Jan 21 09:11:50 PM PST 24
Finished Jan 21 09:33:01 PM PST 24
Peak memory 195464 kb
Host smart-d781a0e8-1abd-420c-a92f-62e1b978facf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412296992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.412296992
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.764433715
Short name T326
Test name
Test status
Simulation time 164827639728 ps
CPU time 926.9 seconds
Started Jan 21 09:11:46 PM PST 24
Finished Jan 21 09:27:16 PM PST 24
Peak memory 214076 kb
Host smart-3af25493-5bc9-4c99-bbed-4808618f15f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764433715 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.764433715
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.3231931646
Short name T300
Test name
Test status
Simulation time 1828277954818 ps
CPU time 1048.16 seconds
Started Jan 21 09:11:47 PM PST 24
Finished Jan 21 09:29:19 PM PST 24
Peak memory 183400 kb
Host smart-afc866f3-7ebf-4d63-a71e-10c32cbc7e9e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231931646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.3231931646
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2042051358
Short name T532
Test name
Test status
Simulation time 200904306624 ps
CPU time 323.74 seconds
Started Jan 21 09:11:51 PM PST 24
Finished Jan 21 09:17:18 PM PST 24
Peak memory 183536 kb
Host smart-3400dbe8-9105-41e2-b4b0-3e8b31216f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042051358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2042051358
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3907410118
Short name T183
Test name
Test status
Simulation time 159570623236 ps
CPU time 375.6 seconds
Started Jan 21 10:00:14 PM PST 24
Finished Jan 21 10:06:40 PM PST 24
Peak memory 191716 kb
Host smart-04b61bbe-4731-4a2b-85a4-159a2230302f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907410118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3907410118
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.3763537493
Short name T17
Test name
Test status
Simulation time 56714158 ps
CPU time 0.87 seconds
Started Jan 21 09:12:03 PM PST 24
Finished Jan 21 09:12:08 PM PST 24
Peak memory 213528 kb
Host smart-560f612d-9146-40db-b212-b2dc664fc67b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763537493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3763537493
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.422228967
Short name T528
Test name
Test status
Simulation time 183923549298 ps
CPU time 134.98 seconds
Started Jan 21 09:11:59 PM PST 24
Finished Jan 21 09:14:19 PM PST 24
Peak memory 191576 kb
Host smart-544c3598-c5d0-4668-a827-2ac6585b9bc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422228967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.422228967
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.1067207301
Short name T520
Test name
Test status
Simulation time 378741277379 ps
CPU time 153.64 seconds
Started Jan 21 09:12:29 PM PST 24
Finished Jan 21 09:15:11 PM PST 24
Peak memory 183400 kb
Host smart-2448fab0-63a8-42dd-83a5-e482704b707e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067207301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1067207301
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.1773758509
Short name T190
Test name
Test status
Simulation time 179183809433 ps
CPU time 89.08 seconds
Started Jan 21 09:12:29 PM PST 24
Finished Jan 21 09:14:06 PM PST 24
Peak memory 183488 kb
Host smart-27a2c2c3-1224-442f-b1d6-226aa502f602
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773758509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1773758509
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.4031884975
Short name T585
Test name
Test status
Simulation time 196254326 ps
CPU time 0.88 seconds
Started Jan 21 09:12:35 PM PST 24
Finished Jan 21 09:12:43 PM PST 24
Peak memory 191440 kb
Host smart-330f6c67-951e-4e13-b040-c34872bf4759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031884975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.4031884975
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.4060083284
Short name T592
Test name
Test status
Simulation time 123619301496 ps
CPU time 914.01 seconds
Started Jan 21 09:12:31 PM PST 24
Finished Jan 21 09:27:51 PM PST 24
Peak memory 206256 kb
Host smart-8ec4900a-734a-4801-a4ff-091d6065414f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060083284 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.4060083284
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.402237107
Short name T153
Test name
Test status
Simulation time 57394382285 ps
CPU time 157.61 seconds
Started Jan 21 09:36:31 PM PST 24
Finished Jan 21 09:39:18 PM PST 24
Peak memory 182172 kb
Host smart-2069bf6c-4b58-41e6-8645-42d3ddca508b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402237107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.402237107
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.2031531181
Short name T523
Test name
Test status
Simulation time 10080583000 ps
CPU time 36.85 seconds
Started Jan 21 09:18:27 PM PST 24
Finished Jan 21 09:19:10 PM PST 24
Peak memory 183480 kb
Host smart-747f034f-0163-40c2-b34a-994e4c931664
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031531181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2031531181
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.61075283
Short name T541
Test name
Test status
Simulation time 83563056865 ps
CPU time 28.53 seconds
Started Jan 21 10:28:51 PM PST 24
Finished Jan 21 10:29:25 PM PST 24
Peak memory 183480 kb
Host smart-18adb9e1-c36d-4238-9598-7fafa98ec402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61075283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.61075283
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.1292960672
Short name T116
Test name
Test status
Simulation time 41305446967 ps
CPU time 62.2 seconds
Started Jan 21 09:18:39 PM PST 24
Finished Jan 21 09:19:46 PM PST 24
Peak memory 183272 kb
Host smart-ba9c744d-9200-433a-ac12-57f14a839fbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292960672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1292960672
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1912464303
Short name T559
Test name
Test status
Simulation time 121815348774 ps
CPU time 66.13 seconds
Started Jan 21 09:39:09 PM PST 24
Finished Jan 21 09:40:23 PM PST 24
Peak memory 183496 kb
Host smart-1e745634-dd22-4dde-b4d8-61e4ce95db9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912464303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1912464303
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.625796625
Short name T561
Test name
Test status
Simulation time 47705540552 ps
CPU time 1768.91 seconds
Started Jan 21 09:18:39 PM PST 24
Finished Jan 21 09:48:13 PM PST 24
Peak memory 183476 kb
Host smart-aab345b4-a44e-4b5d-941d-c7017452875b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625796625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.625796625
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2209561677
Short name T49
Test name
Test status
Simulation time 338836189247 ps
CPU time 182.25 seconds
Started Jan 21 09:12:31 PM PST 24
Finished Jan 21 09:15:39 PM PST 24
Peak memory 183424 kb
Host smart-34331cc0-52ae-4338-a798-26ada03f7631
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209561677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2209561677
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.4108847542
Short name T362
Test name
Test status
Simulation time 317732299960 ps
CPU time 54.26 seconds
Started Jan 21 09:12:36 PM PST 24
Finished Jan 21 09:13:38 PM PST 24
Peak memory 183520 kb
Host smart-c0a0fdab-65db-4656-b53b-84ac7eb0e745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108847542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.4108847542
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.881562721
Short name T595
Test name
Test status
Simulation time 70352141270 ps
CPU time 105.77 seconds
Started Jan 21 09:12:36 PM PST 24
Finished Jan 21 09:14:29 PM PST 24
Peak memory 191720 kb
Host smart-fc77d6fd-210a-47c5-bbca-f94d0a37c3ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881562721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.881562721
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2634379628
Short name T332
Test name
Test status
Simulation time 42259997019 ps
CPU time 68.75 seconds
Started Jan 21 09:12:30 PM PST 24
Finished Jan 21 09:13:46 PM PST 24
Peak memory 191632 kb
Host smart-ec9fab2e-7196-4034-9c23-9ab51cfb9419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634379628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2634379628
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.789639606
Short name T271
Test name
Test status
Simulation time 1283191563475 ps
CPU time 567.68 seconds
Started Jan 21 09:12:36 PM PST 24
Finished Jan 21 09:22:11 PM PST 24
Peak memory 191680 kb
Host smart-74c59283-338b-44aa-b80a-0725f4952f4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789639606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
789639606
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.3555330219
Short name T76
Test name
Test status
Simulation time 67855060239 ps
CPU time 408.07 seconds
Started Jan 21 09:12:35 PM PST 24
Finished Jan 21 09:19:31 PM PST 24
Peak memory 198100 kb
Host smart-cde0495c-c3ae-4f34-b78f-aee37e12c70d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555330219 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.3555330219
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.4102860514
Short name T159
Test name
Test status
Simulation time 153850636942 ps
CPU time 222.21 seconds
Started Jan 21 09:18:37 PM PST 24
Finished Jan 21 09:22:25 PM PST 24
Peak memory 191716 kb
Host smart-1337b98b-6039-42e2-b99a-85a83a8c4083
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102860514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.4102860514
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.1607760028
Short name T111
Test name
Test status
Simulation time 720619084907 ps
CPU time 623.53 seconds
Started Jan 21 09:18:46 PM PST 24
Finished Jan 21 09:29:11 PM PST 24
Peak memory 191708 kb
Host smart-ed6577ac-ae69-44a2-8558-a812b0fbe35c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607760028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1607760028
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.2052368439
Short name T562
Test name
Test status
Simulation time 27765372226 ps
CPU time 12.47 seconds
Started Jan 21 09:18:55 PM PST 24
Finished Jan 21 09:19:10 PM PST 24
Peak memory 183224 kb
Host smart-bea4b5e1-21db-48ba-aacb-ec91bc2affb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052368439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2052368439
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.2132739649
Short name T208
Test name
Test status
Simulation time 65963215955 ps
CPU time 47.6 seconds
Started Jan 21 09:18:57 PM PST 24
Finished Jan 21 09:19:46 PM PST 24
Peak memory 192660 kb
Host smart-61e2f10e-7b39-4872-893b-c03eaf4e7828
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132739649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2132739649
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.2958820300
Short name T5
Test name
Test status
Simulation time 308647285338 ps
CPU time 145.54 seconds
Started Jan 21 09:18:57 PM PST 24
Finished Jan 21 09:21:24 PM PST 24
Peak memory 191700 kb
Host smart-02bd32f4-7c77-4f33-8765-54c7e03397ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958820300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2958820300
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.2256843928
Short name T568
Test name
Test status
Simulation time 32577536977 ps
CPU time 17.95 seconds
Started Jan 21 10:37:14 PM PST 24
Finished Jan 21 10:37:39 PM PST 24
Peak memory 183492 kb
Host smart-10591063-7316-4772-8a2b-38c8832e0ce1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256843928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.2256843928
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.325234556
Short name T588
Test name
Test status
Simulation time 52003331632 ps
CPU time 86.32 seconds
Started Jan 21 09:12:32 PM PST 24
Finished Jan 21 09:14:04 PM PST 24
Peak memory 183416 kb
Host smart-dd8e27be-822a-4114-8e8d-2c5c3e908c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325234556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.325234556
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.2547382850
Short name T308
Test name
Test status
Simulation time 133781284712 ps
CPU time 100.85 seconds
Started Jan 21 10:05:47 PM PST 24
Finished Jan 21 10:07:35 PM PST 24
Peak memory 183488 kb
Host smart-ae6b1cae-52dc-4345-be94-3ab2188fbb66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547382850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2547382850
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1088715026
Short name T575
Test name
Test status
Simulation time 2909036362 ps
CPU time 1.8 seconds
Started Jan 21 09:45:41 PM PST 24
Finished Jan 21 09:45:48 PM PST 24
Peak memory 183344 kb
Host smart-c6278307-440f-4634-a282-3f18c2ae57fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088715026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1088715026
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.102746037
Short name T270
Test name
Test status
Simulation time 3085127703483 ps
CPU time 1983.98 seconds
Started Jan 21 09:12:44 PM PST 24
Finished Jan 21 09:45:51 PM PST 24
Peak memory 191640 kb
Host smart-366b5976-149c-47b5-8497-0b513d798d13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102746037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.
102746037
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.557070402
Short name T614
Test name
Test status
Simulation time 36056849660 ps
CPU time 306.07 seconds
Started Jan 21 09:49:09 PM PST 24
Finished Jan 21 09:54:18 PM PST 24
Peak memory 198148 kb
Host smart-563f4ca6-ec49-42cc-8522-2b7d99e56e25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557070402 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.557070402
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/122.rv_timer_random.2586837762
Short name T565
Test name
Test status
Simulation time 339932527041 ps
CPU time 219.97 seconds
Started Jan 21 09:18:58 PM PST 24
Finished Jan 21 09:22:40 PM PST 24
Peak memory 191716 kb
Host smart-63166715-4fcc-41f9-882d-ee200e564a64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586837762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2586837762
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.843085793
Short name T127
Test name
Test status
Simulation time 292678592002 ps
CPU time 409.61 seconds
Started Jan 21 09:19:05 PM PST 24
Finished Jan 21 09:25:56 PM PST 24
Peak memory 192700 kb
Host smart-f3c8b258-b481-43bb-8f7a-c6a9fb773d60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843085793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.843085793
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.968305698
Short name T339
Test name
Test status
Simulation time 156161897420 ps
CPU time 278.78 seconds
Started Jan 21 09:19:06 PM PST 24
Finished Jan 21 09:23:47 PM PST 24
Peak memory 191652 kb
Host smart-3001dc7b-0dc5-417b-9e86-35adbfde0b0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968305698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.968305698
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2150868523
Short name T231
Test name
Test status
Simulation time 151052212656 ps
CPU time 567.78 seconds
Started Jan 21 09:19:04 PM PST 24
Finished Jan 21 09:28:34 PM PST 24
Peak memory 191708 kb
Host smart-f26838d2-96f6-4549-a5bc-373291dd77bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150868523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2150868523
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.2366400699
Short name T236
Test name
Test status
Simulation time 337242108975 ps
CPU time 577.04 seconds
Started Jan 21 09:19:15 PM PST 24
Finished Jan 21 09:29:04 PM PST 24
Peak memory 194992 kb
Host smart-4ae0b599-2488-45f0-8885-f9fc0c6e4a5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366400699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2366400699
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.3115622231
Short name T342
Test name
Test status
Simulation time 383808453274 ps
CPU time 194.95 seconds
Started Jan 21 09:19:20 PM PST 24
Finished Jan 21 09:22:44 PM PST 24
Peak memory 191740 kb
Host smart-f17d00bd-0e44-4cf4-a2ea-115e51b285f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115622231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3115622231
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3283656755
Short name T233
Test name
Test status
Simulation time 902197694505 ps
CPU time 301.87 seconds
Started Jan 21 09:26:35 PM PST 24
Finished Jan 21 09:31:40 PM PST 24
Peak memory 183496 kb
Host smart-581de7ba-2a54-4d05-a573-1f6bdb3cc45a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283656755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.3283656755
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1747262631
Short name T496
Test name
Test status
Simulation time 525786474602 ps
CPU time 199.12 seconds
Started Jan 21 10:37:46 PM PST 24
Finished Jan 21 10:41:14 PM PST 24
Peak memory 183404 kb
Host smart-f6bc0e30-f633-4a0c-a106-91d2aae276bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747262631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1747262631
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.1503263904
Short name T540
Test name
Test status
Simulation time 89896776464 ps
CPU time 42.93 seconds
Started Jan 21 09:12:32 PM PST 24
Finished Jan 21 09:13:20 PM PST 24
Peak memory 183432 kb
Host smart-3c8c0870-d971-49bf-8ff4-ad6c10cd777c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503263904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.1503263904
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2004957840
Short name T522
Test name
Test status
Simulation time 116547659 ps
CPU time 0.66 seconds
Started Jan 21 10:14:09 PM PST 24
Finished Jan 21 10:14:14 PM PST 24
Peak memory 183136 kb
Host smart-298fcc25-668e-4952-b161-76be2c043904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004957840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2004957840
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.399053602
Short name T491
Test name
Test status
Simulation time 663219864662 ps
CPU time 239.66 seconds
Started Jan 21 09:54:37 PM PST 24
Finished Jan 21 09:58:48 PM PST 24
Peak memory 183424 kb
Host smart-5771cf6a-50c5-4fec-9eb6-ca655a47efbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399053602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.
399053602
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.3733173401
Short name T487
Test name
Test status
Simulation time 182761275561 ps
CPU time 321.75 seconds
Started Jan 21 09:12:45 PM PST 24
Finished Jan 21 09:18:10 PM PST 24
Peak memory 206252 kb
Host smart-474288f6-fa10-4327-a544-155c4d3353e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733173401 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.3733173401
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.979483568
Short name T263
Test name
Test status
Simulation time 99749749989 ps
CPU time 282.65 seconds
Started Jan 21 09:19:14 PM PST 24
Finished Jan 21 09:24:09 PM PST 24
Peak memory 191644 kb
Host smart-31c68096-c658-44ad-9def-386879878779
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979483568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.979483568
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.290577964
Short name T253
Test name
Test status
Simulation time 509219210820 ps
CPU time 622.98 seconds
Started Jan 21 09:19:15 PM PST 24
Finished Jan 21 09:29:50 PM PST 24
Peak memory 194700 kb
Host smart-a7f1bf41-1f9e-4c53-ad5f-40f51e09f844
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290577964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.290577964
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.2782078921
Short name T555
Test name
Test status
Simulation time 71230950188 ps
CPU time 218.16 seconds
Started Jan 21 09:19:16 PM PST 24
Finished Jan 21 09:23:05 PM PST 24
Peak memory 191716 kb
Host smart-cc382ae4-d321-452a-990f-87869dee1152
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782078921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2782078921
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.783336578
Short name T210
Test name
Test status
Simulation time 29555725648 ps
CPU time 45.88 seconds
Started Jan 21 09:19:29 PM PST 24
Finished Jan 21 09:20:29 PM PST 24
Peak memory 183408 kb
Host smart-f4226a84-ab2f-422d-ab91-905ce21e69e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783336578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.783336578
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.3056157164
Short name T312
Test name
Test status
Simulation time 563217374302 ps
CPU time 2069.87 seconds
Started Jan 21 09:19:25 PM PST 24
Finished Jan 21 09:54:10 PM PST 24
Peak memory 191680 kb
Host smart-a18a5db3-2ef4-440c-a131-dcafeb160521
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056157164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3056157164
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.1126592635
Short name T587
Test name
Test status
Simulation time 85391655337 ps
CPU time 76.93 seconds
Started Jan 21 09:19:24 PM PST 24
Finished Jan 21 09:20:55 PM PST 24
Peak memory 183472 kb
Host smart-4413cd93-4061-4809-93d8-f7d803a4698e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126592635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1126592635
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1424469465
Short name T164
Test name
Test status
Simulation time 1601690917585 ps
CPU time 197.56 seconds
Started Jan 21 09:19:26 PM PST 24
Finished Jan 21 09:22:58 PM PST 24
Peak memory 191684 kb
Host smart-c6a8b479-b2f4-48cf-95f9-868cfbe88048
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424469465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1424469465
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.3093227517
Short name T310
Test name
Test status
Simulation time 59901664860 ps
CPU time 1525.03 seconds
Started Jan 21 09:19:27 PM PST 24
Finished Jan 21 09:45:07 PM PST 24
Peak memory 191652 kb
Host smart-ac9708a1-2c71-4a8c-b61a-2ecffe8500db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093227517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3093227517
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2777265354
Short name T156
Test name
Test status
Simulation time 41040313346 ps
CPU time 80.22 seconds
Started Jan 21 09:55:11 PM PST 24
Finished Jan 21 09:56:40 PM PST 24
Peak memory 191672 kb
Host smart-1c8ef66c-129a-4ede-81ab-fdf472c070a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777265354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2777265354
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.412220356
Short name T610
Test name
Test status
Simulation time 1257237635209 ps
CPU time 685.64 seconds
Started Jan 21 10:30:10 PM PST 24
Finished Jan 21 10:41:39 PM PST 24
Peak memory 183484 kb
Host smart-b206e212-de95-44e1-acdd-2c781b296884
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412220356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.412220356
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.1311719316
Short name T2
Test name
Test status
Simulation time 338768892509 ps
CPU time 258.97 seconds
Started Jan 21 09:37:46 PM PST 24
Finished Jan 21 09:42:07 PM PST 24
Peak memory 183404 kb
Host smart-2810bf02-fa18-47dc-9756-f24f51dbe82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311719316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.1311719316
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.714361823
Short name T580
Test name
Test status
Simulation time 70330723520 ps
CPU time 380.78 seconds
Started Jan 21 09:12:45 PM PST 24
Finished Jan 21 09:19:09 PM PST 24
Peak memory 183440 kb
Host smart-cea77762-0661-4fd4-823f-a90d8941c00b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714361823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.714361823
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.1337869248
Short name T261
Test name
Test status
Simulation time 225677518972 ps
CPU time 324.25 seconds
Started Jan 21 09:12:36 PM PST 24
Finished Jan 21 09:18:08 PM PST 24
Peak memory 206248 kb
Host smart-7b247c3a-2238-455f-9c01-bdf427af43b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337869248 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.1337869248
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/142.rv_timer_random.1551718224
Short name T273
Test name
Test status
Simulation time 156315728535 ps
CPU time 228.79 seconds
Started Jan 21 09:19:39 PM PST 24
Finished Jan 21 09:23:36 PM PST 24
Peak memory 191740 kb
Host smart-4ebe631f-0f43-40c5-9dca-d0a3ca0dad17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551718224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1551718224
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1758966530
Short name T328
Test name
Test status
Simulation time 70388632018 ps
CPU time 116.84 seconds
Started Jan 21 09:19:38 PM PST 24
Finished Jan 21 09:21:44 PM PST 24
Peak memory 194268 kb
Host smart-9999dcce-f12e-4845-8507-ff79de7c0c37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758966530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1758966530
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.2358536811
Short name T117
Test name
Test status
Simulation time 456924670005 ps
CPU time 716.44 seconds
Started Jan 21 09:19:34 PM PST 24
Finished Jan 21 09:31:42 PM PST 24
Peak memory 191672 kb
Host smart-b23b036f-5061-463c-9f77-2751fd7fc75a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358536811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2358536811
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.71952061
Short name T264
Test name
Test status
Simulation time 92880755855 ps
CPU time 915.74 seconds
Started Jan 21 09:19:36 PM PST 24
Finished Jan 21 09:35:02 PM PST 24
Peak memory 195284 kb
Host smart-96a18e79-08f6-4451-a30a-ca5ba4893a7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71952061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.71952061
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.1776599750
Short name T318
Test name
Test status
Simulation time 158283315426 ps
CPU time 375 seconds
Started Jan 21 09:19:34 PM PST 24
Finished Jan 21 09:26:01 PM PST 24
Peak memory 191736 kb
Host smart-407602b2-ab68-45e5-a52f-f57b83065b82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776599750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1776599750
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.1441067592
Short name T569
Test name
Test status
Simulation time 92437740118 ps
CPU time 453.45 seconds
Started Jan 21 09:19:44 PM PST 24
Finished Jan 21 09:27:22 PM PST 24
Peak memory 191624 kb
Host smart-87df80fd-acbc-4b95-b2d8-eb95f109040c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441067592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1441067592
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3410191780
Short name T172
Test name
Test status
Simulation time 1644148800038 ps
CPU time 365.35 seconds
Started Jan 21 09:19:46 PM PST 24
Finished Jan 21 09:25:54 PM PST 24
Peak memory 191716 kb
Host smart-5ada765e-ef7e-425b-af58-aa4fdc069a0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410191780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3410191780
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.3444002196
Short name T222
Test name
Test status
Simulation time 58529414877 ps
CPU time 55.54 seconds
Started Jan 21 09:12:35 PM PST 24
Finished Jan 21 09:13:38 PM PST 24
Peak memory 183424 kb
Host smart-733098a7-2505-443f-827e-50d106aa844e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444002196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.3444002196
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.3664879582
Short name T547
Test name
Test status
Simulation time 73217580242 ps
CPU time 71.74 seconds
Started Jan 21 09:58:27 PM PST 24
Finished Jan 21 09:59:42 PM PST 24
Peak memory 183460 kb
Host smart-f00de588-8034-4abf-9610-08aacd920f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664879582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3664879582
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.1760462229
Short name T39
Test name
Test status
Simulation time 955196352889 ps
CPU time 342.71 seconds
Started Jan 21 09:12:36 PM PST 24
Finished Jan 21 09:18:26 PM PST 24
Peak memory 191652 kb
Host smart-cbcf4e76-48c3-4973-93c5-3709a177cccc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760462229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1760462229
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.4063035241
Short name T155
Test name
Test status
Simulation time 167935831881 ps
CPU time 64.27 seconds
Started Jan 21 09:20:00 PM PST 24
Finished Jan 21 09:21:07 PM PST 24
Peak memory 194964 kb
Host smart-0c426cfc-935a-4fef-ba22-2602e5061a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063035241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.4063035241
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1955085081
Short name T227
Test name
Test status
Simulation time 131170880259 ps
CPU time 86.71 seconds
Started Jan 21 09:12:37 PM PST 24
Finished Jan 21 09:14:11 PM PST 24
Peak memory 183512 kb
Host smart-81bafbb9-b3dd-4a36-9f32-75783ca83508
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955085081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1955085081
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.473522102
Short name T502
Test name
Test status
Simulation time 130457168322 ps
CPU time 835.81 seconds
Started Jan 21 09:12:37 PM PST 24
Finished Jan 21 09:26:40 PM PST 24
Peak memory 206348 kb
Host smart-dfacd67d-26b1-450a-a529-eb3a96baf8f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473522102 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.473522102
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.2288012909
Short name T352
Test name
Test status
Simulation time 51735767077 ps
CPU time 83.28 seconds
Started Jan 21 09:43:18 PM PST 24
Finished Jan 21 09:44:46 PM PST 24
Peak memory 191360 kb
Host smart-3b375f5b-156a-4162-ba00-ef20420caac2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288012909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2288012909
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.3249555623
Short name T302
Test name
Test status
Simulation time 36725242557 ps
CPU time 76.12 seconds
Started Jan 21 09:19:45 PM PST 24
Finished Jan 21 09:21:05 PM PST 24
Peak memory 183508 kb
Host smart-833919e2-96c8-4114-b38a-5ea84cea71f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249555623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3249555623
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1261353754
Short name T129
Test name
Test status
Simulation time 237585423297 ps
CPU time 569.72 seconds
Started Jan 21 09:19:45 PM PST 24
Finished Jan 21 09:29:18 PM PST 24
Peak memory 191716 kb
Host smart-fd261513-efd4-433a-98f1-86827d2ed953
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261353754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1261353754
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3587406602
Short name T314
Test name
Test status
Simulation time 387799684638 ps
CPU time 376.91 seconds
Started Jan 21 09:19:57 PM PST 24
Finished Jan 21 09:26:17 PM PST 24
Peak memory 191644 kb
Host smart-8a4801d4-9bed-4a99-9f3f-896917ad1f6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587406602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3587406602
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.2433512788
Short name T247
Test name
Test status
Simulation time 127550631455 ps
CPU time 238.33 seconds
Started Jan 21 09:19:56 PM PST 24
Finished Jan 21 09:23:58 PM PST 24
Peak memory 194836 kb
Host smart-111c7860-5ef9-404b-9c13-08d2bd7b19d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433512788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2433512788
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.1224731471
Short name T280
Test name
Test status
Simulation time 39624352525 ps
CPU time 491.96 seconds
Started Jan 21 09:19:56 PM PST 24
Finished Jan 21 09:28:12 PM PST 24
Peak memory 183524 kb
Host smart-69f1e7e6-bc63-4ee2-bb36-db636642c6de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224731471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1224731471
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.4114531374
Short name T281
Test name
Test status
Simulation time 17429806404 ps
CPU time 30.12 seconds
Started Jan 21 09:12:37 PM PST 24
Finished Jan 21 09:13:14 PM PST 24
Peak memory 183436 kb
Host smart-0806f9ed-75a4-4310-80e0-aea4b8458675
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114531374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.4114531374
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2473313504
Short name T601
Test name
Test status
Simulation time 724523519433 ps
CPU time 289.9 seconds
Started Jan 21 09:12:38 PM PST 24
Finished Jan 21 09:17:35 PM PST 24
Peak memory 183416 kb
Host smart-029b73fd-a93d-44c9-86dc-94927bd1d49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473313504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2473313504
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.2457949161
Short name T131
Test name
Test status
Simulation time 291240247789 ps
CPU time 272.19 seconds
Started Jan 21 10:05:33 PM PST 24
Finished Jan 21 10:10:13 PM PST 24
Peak memory 194604 kb
Host smart-7e5513c3-4a9c-434d-8c6a-8fbd909aead1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457949161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.2457949161
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1014691839
Short name T485
Test name
Test status
Simulation time 397539049 ps
CPU time 0.66 seconds
Started Jan 21 09:12:44 PM PST 24
Finished Jan 21 09:12:48 PM PST 24
Peak memory 183080 kb
Host smart-b58d9aab-e098-4be9-af7c-179ea6a6e219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014691839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1014691839
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3773226405
Short name T548
Test name
Test status
Simulation time 40326401 ps
CPU time 0.56 seconds
Started Jan 21 09:12:47 PM PST 24
Finished Jan 21 09:12:50 PM PST 24
Peak memory 183200 kb
Host smart-83814a40-ba1e-4489-86ed-fb237c0711a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773226405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3773226405
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.595451574
Short name T37
Test name
Test status
Simulation time 223803619894 ps
CPU time 717.63 seconds
Started Jan 21 09:12:44 PM PST 24
Finished Jan 21 09:24:45 PM PST 24
Peak memory 206732 kb
Host smart-01a0e170-4207-45b3-a977-64074b9f1b7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595451574 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.595451574
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.4092002587
Short name T607
Test name
Test status
Simulation time 804055211990 ps
CPU time 445.68 seconds
Started Jan 21 09:19:58 PM PST 24
Finished Jan 21 09:27:27 PM PST 24
Peak memory 191740 kb
Host smart-3e42dd9b-5838-4738-bfaa-c912b65fd50d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092002587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.4092002587
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2397686085
Short name T239
Test name
Test status
Simulation time 58343611779 ps
CPU time 86.52 seconds
Started Jan 21 09:20:06 PM PST 24
Finished Jan 21 09:21:35 PM PST 24
Peak memory 191648 kb
Host smart-4465aba2-86d7-40b3-b6cf-178c02588c08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397686085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2397686085
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.1448761735
Short name T349
Test name
Test status
Simulation time 131276835040 ps
CPU time 110.87 seconds
Started Jan 21 09:20:09 PM PST 24
Finished Jan 21 09:22:04 PM PST 24
Peak memory 191708 kb
Host smart-9bd4e11c-bafb-4bd6-be05-acd2d83ceba7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448761735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1448761735
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2049577538
Short name T243
Test name
Test status
Simulation time 59863102090 ps
CPU time 166.49 seconds
Started Jan 21 09:20:17 PM PST 24
Finished Jan 21 09:23:09 PM PST 24
Peak memory 191692 kb
Host smart-555c4bdd-3137-4e25-8d6b-b589a01e5a75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049577538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2049577538
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.283588567
Short name T47
Test name
Test status
Simulation time 644450627904 ps
CPU time 359.19 seconds
Started Jan 21 09:20:18 PM PST 24
Finished Jan 21 09:26:22 PM PST 24
Peak memory 191688 kb
Host smart-9a778a4a-dcec-4957-a35b-deff52c7fbc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283588567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.283588567
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1303707914
Short name T605
Test name
Test status
Simulation time 21828270476 ps
CPU time 34.83 seconds
Started Jan 21 09:12:48 PM PST 24
Finished Jan 21 09:13:25 PM PST 24
Peak memory 183448 kb
Host smart-4df2f0d0-e5e0-4926-a8d5-66f680cf5ac6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303707914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1303707914
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.2786779058
Short name T363
Test name
Test status
Simulation time 132317615717 ps
CPU time 198.4 seconds
Started Jan 21 09:12:47 PM PST 24
Finished Jan 21 09:16:08 PM PST 24
Peak memory 183624 kb
Host smart-a4a0ff2d-eb1b-42c7-936d-16ea155dae91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786779058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2786779058
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.530091754
Short name T141
Test name
Test status
Simulation time 172036629318 ps
CPU time 205.44 seconds
Started Jan 21 09:12:41 PM PST 24
Finished Jan 21 09:16:11 PM PST 24
Peak memory 191704 kb
Host smart-3c28b77a-3a11-451b-a9f7-fca71b02c4f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530091754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.530091754
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.4145122306
Short name T173
Test name
Test status
Simulation time 75600984935 ps
CPU time 118.71 seconds
Started Jan 21 09:12:42 PM PST 24
Finished Jan 21 09:14:45 PM PST 24
Peak memory 183428 kb
Host smart-47883c56-d5ad-4081-ae56-1c7bed2d1e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145122306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.4145122306
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.1535987362
Short name T30
Test name
Test status
Simulation time 7154221922135 ps
CPU time 1746.69 seconds
Started Jan 21 09:12:42 PM PST 24
Finished Jan 21 09:41:53 PM PST 24
Peak memory 191608 kb
Host smart-01b1eba3-f7fb-4f2f-a958-8473b1061be1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535987362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.1535987362
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.2863806333
Short name T581
Test name
Test status
Simulation time 63307983293 ps
CPU time 679.03 seconds
Started Jan 21 09:12:44 PM PST 24
Finished Jan 21 09:24:06 PM PST 24
Peak memory 206300 kb
Host smart-6fc2dd3a-82f0-416c-83c9-97c7a8eff5a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863806333 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.2863806333
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.2833826106
Short name T287
Test name
Test status
Simulation time 511419507626 ps
CPU time 302.67 seconds
Started Jan 21 09:20:26 PM PST 24
Finished Jan 21 09:25:30 PM PST 24
Peak memory 191672 kb
Host smart-d78222cb-843a-4dfb-a4da-7bd66744c709
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833826106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2833826106
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.4129801303
Short name T317
Test name
Test status
Simulation time 438260359383 ps
CPU time 988.91 seconds
Started Jan 21 10:35:10 PM PST 24
Finished Jan 21 10:51:41 PM PST 24
Peak memory 191684 kb
Host smart-e42dcb01-603e-4665-b7ab-625424399488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129801303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.4129801303
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.523103519
Short name T120
Test name
Test status
Simulation time 13078843690 ps
CPU time 11.38 seconds
Started Jan 21 09:20:25 PM PST 24
Finished Jan 21 09:20:38 PM PST 24
Peak memory 191900 kb
Host smart-d6b5aa54-c126-497b-8d28-b7b653d69c7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523103519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.523103519
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3997440464
Short name T297
Test name
Test status
Simulation time 166221324660 ps
CPU time 155.65 seconds
Started Jan 21 10:15:08 PM PST 24
Finished Jan 21 10:18:02 PM PST 24
Peak memory 192632 kb
Host smart-419f17bd-63c4-48f9-b64a-bcad482faa9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997440464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3997440464
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.356406292
Short name T168
Test name
Test status
Simulation time 132889593078 ps
CPU time 315.41 seconds
Started Jan 21 09:20:46 PM PST 24
Finished Jan 21 09:26:03 PM PST 24
Peak memory 191692 kb
Host smart-e22a9ce5-2ac7-4bdf-a527-4a3a85c745b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356406292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.356406292
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3602157376
Short name T260
Test name
Test status
Simulation time 100787496711 ps
CPU time 161.18 seconds
Started Jan 21 09:20:46 PM PST 24
Finished Jan 21 09:23:29 PM PST 24
Peak memory 191936 kb
Host smart-4170d24e-b705-434d-abd0-d04af1dc385e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602157376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3602157376
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.2138654048
Short name T311
Test name
Test status
Simulation time 82284158155 ps
CPU time 527.78 seconds
Started Jan 21 09:20:45 PM PST 24
Finished Jan 21 09:29:35 PM PST 24
Peak memory 191628 kb
Host smart-bca284d9-cd7d-4e0f-a342-95acba550eda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138654048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2138654048
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.1616805942
Short name T277
Test name
Test status
Simulation time 1208700657176 ps
CPU time 702.9 seconds
Started Jan 21 09:12:46 PM PST 24
Finished Jan 21 09:24:32 PM PST 24
Peak memory 183684 kb
Host smart-11a9d35f-b7b1-43d8-afb0-b4bb19cffcf9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616805942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.1616805942
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.3889059205
Short name T360
Test name
Test status
Simulation time 141229014367 ps
CPU time 91.56 seconds
Started Jan 21 09:12:43 PM PST 24
Finished Jan 21 09:14:18 PM PST 24
Peak memory 183500 kb
Host smart-043f70c0-cfcd-4c1b-8b77-1e7cbdd1f989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889059205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3889059205
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.2450716483
Short name T543
Test name
Test status
Simulation time 94903584997 ps
CPU time 133.56 seconds
Started Jan 21 09:12:46 PM PST 24
Finished Jan 21 09:15:02 PM PST 24
Peak memory 183688 kb
Host smart-c98d167d-283c-4ee9-bce5-6153bba3795e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450716483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2450716483
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1661140750
Short name T516
Test name
Test status
Simulation time 331924570032 ps
CPU time 486.62 seconds
Started Jan 21 09:12:41 PM PST 24
Finished Jan 21 09:20:52 PM PST 24
Peak memory 191652 kb
Host smart-c565f0a4-39d2-483c-a7e4-ca8af495bebe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661140750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1661140750
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.1909722347
Short name T521
Test name
Test status
Simulation time 119473409804 ps
CPU time 251.97 seconds
Started Jan 21 09:12:44 PM PST 24
Finished Jan 21 09:16:59 PM PST 24
Peak memory 206328 kb
Host smart-2c2645d1-83c1-4311-89be-fea312e28efb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909722347 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.1909722347
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.rv_timer_random.3668508962
Short name T199
Test name
Test status
Simulation time 945956527431 ps
CPU time 319.65 seconds
Started Jan 21 10:05:48 PM PST 24
Finished Jan 21 10:11:14 PM PST 24
Peak memory 191672 kb
Host smart-54401015-68cd-4b47-8ca0-49c5d14d1949
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668508962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3668508962
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.2096622663
Short name T304
Test name
Test status
Simulation time 38288258585 ps
CPU time 59.97 seconds
Started Jan 21 10:09:24 PM PST 24
Finished Jan 21 10:10:25 PM PST 24
Peak memory 183508 kb
Host smart-75760f3b-ab3a-41aa-9b89-dd8c1e2e4dde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096622663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.2096622663
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.2450811716
Short name T169
Test name
Test status
Simulation time 475082734408 ps
CPU time 248.49 seconds
Started Jan 21 09:20:49 PM PST 24
Finished Jan 21 09:25:00 PM PST 24
Peak memory 191936 kb
Host smart-9687fd46-b655-4821-bc15-d3bff4c04a6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450811716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2450811716
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3656703135
Short name T110
Test name
Test status
Simulation time 1034375283250 ps
CPU time 722.17 seconds
Started Jan 21 09:20:57 PM PST 24
Finished Jan 21 09:33:06 PM PST 24
Peak memory 191708 kb
Host smart-f4ba2421-0fb8-4bee-a122-ba7916667ff0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656703135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3656703135
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.490974525
Short name T259
Test name
Test status
Simulation time 216726630919 ps
CPU time 254.79 seconds
Started Jan 21 10:23:22 PM PST 24
Finished Jan 21 10:27:43 PM PST 24
Peak memory 191724 kb
Host smart-4b6791e4-4617-4f07-a78e-c5fd72b84283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490974525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.490974525
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.777309949
Short name T503
Test name
Test status
Simulation time 244660843839 ps
CPU time 105.43 seconds
Started Jan 21 09:28:59 PM PST 24
Finished Jan 21 09:30:57 PM PST 24
Peak memory 183472 kb
Host smart-24f191ec-39bd-402c-825f-52c8b8823e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777309949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.777309949
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3815560286
Short name T536
Test name
Test status
Simulation time 113592818 ps
CPU time 0.67 seconds
Started Jan 21 09:12:47 PM PST 24
Finished Jan 21 09:12:50 PM PST 24
Peak memory 182996 kb
Host smart-903ded9f-e08e-41f0-b0f2-2ec30105b7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815560286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3815560286
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.2281394878
Short name T600
Test name
Test status
Simulation time 49648927003 ps
CPU time 378.74 seconds
Started Jan 21 09:12:51 PM PST 24
Finished Jan 21 09:19:11 PM PST 24
Peak memory 206324 kb
Host smart-cbb63355-b3cd-46f1-abdd-6b62705552c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281394878 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.2281394878
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.2350322459
Short name T135
Test name
Test status
Simulation time 195508028997 ps
CPU time 89.47 seconds
Started Jan 21 09:21:10 PM PST 24
Finished Jan 21 09:22:45 PM PST 24
Peak memory 194988 kb
Host smart-9da1ed9b-44d6-43a9-b9fa-24916819e1ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350322459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2350322459
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.601177317
Short name T122
Test name
Test status
Simulation time 161100095148 ps
CPU time 718.89 seconds
Started Jan 21 09:21:05 PM PST 24
Finished Jan 21 09:33:08 PM PST 24
Peak memory 194464 kb
Host smart-0da8e741-2ad1-4a1e-a434-8160e011816b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601177317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.601177317
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.3005230729
Short name T206
Test name
Test status
Simulation time 59969657582 ps
CPU time 614.27 seconds
Started Jan 21 09:46:47 PM PST 24
Finished Jan 21 09:57:04 PM PST 24
Peak memory 194796 kb
Host smart-63963db0-136b-4227-8295-e03b39d93a92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005230729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3005230729
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.2650764995
Short name T285
Test name
Test status
Simulation time 112509955306 ps
CPU time 411.1 seconds
Started Jan 21 09:21:06 PM PST 24
Finished Jan 21 09:28:01 PM PST 24
Peak memory 191700 kb
Host smart-45116217-fe53-4bb5-9932-d92271b471a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650764995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2650764995
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.2064771853
Short name T185
Test name
Test status
Simulation time 114363575877 ps
CPU time 231.19 seconds
Started Jan 21 09:21:24 PM PST 24
Finished Jan 21 09:25:16 PM PST 24
Peak memory 191696 kb
Host smart-a83f1554-ec54-4b39-a320-d18e53732c33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064771853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2064771853
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.1568131886
Short name T24
Test name
Test status
Simulation time 405978523192 ps
CPU time 167.88 seconds
Started Jan 21 09:21:25 PM PST 24
Finished Jan 21 09:24:14 PM PST 24
Peak memory 194176 kb
Host smart-b1244142-bc77-48be-9d06-a06713656343
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568131886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1568131886
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2052812545
Short name T142
Test name
Test status
Simulation time 288550947363 ps
CPU time 524.17 seconds
Started Jan 21 09:21:23 PM PST 24
Finished Jan 21 09:30:08 PM PST 24
Peak memory 191628 kb
Host smart-0b55613c-48d8-469f-921d-9ac5a2d9323c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052812545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2052812545
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.3338826932
Short name T545
Test name
Test status
Simulation time 23752780796 ps
CPU time 31.06 seconds
Started Jan 21 09:11:56 PM PST 24
Finished Jan 21 09:12:33 PM PST 24
Peak memory 183500 kb
Host smart-420a49ef-7c63-4a37-b555-f44c1e875995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338826932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3338826932
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3563308201
Short name T124
Test name
Test status
Simulation time 550227695070 ps
CPU time 305.23 seconds
Started Jan 21 09:12:04 PM PST 24
Finished Jan 21 09:17:13 PM PST 24
Peak memory 194196 kb
Host smart-03f8fcb2-1e00-4a75-9477-cc91df0afbaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563308201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3563308201
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1540589321
Short name T589
Test name
Test status
Simulation time 4126653053 ps
CPU time 9.28 seconds
Started Jan 21 09:12:07 PM PST 24
Finished Jan 21 09:12:20 PM PST 24
Peak memory 183224 kb
Host smart-7759be66-8b9b-4f66-aff5-60788de17719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540589321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1540589321
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.1166677933
Short name T20
Test name
Test status
Simulation time 395202041 ps
CPU time 0.81 seconds
Started Jan 21 09:48:41 PM PST 24
Finished Jan 21 09:48:43 PM PST 24
Peak memory 213536 kb
Host smart-ef8eb56c-e7b5-44ab-a08a-889f67ce2ca5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166677933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1166677933
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.805706742
Short name T586
Test name
Test status
Simulation time 403907823849 ps
CPU time 175.64 seconds
Started Jan 21 09:11:56 PM PST 24
Finished Jan 21 09:14:57 PM PST 24
Peak memory 191588 kb
Host smart-6eadc651-7a4a-4439-93e7-1324e79bc124
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805706742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.805706742
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.3331714245
Short name T11
Test name
Test status
Simulation time 231798600274 ps
CPU time 624.8 seconds
Started Jan 21 09:12:03 PM PST 24
Finished Jan 21 09:22:32 PM PST 24
Peak memory 206320 kb
Host smart-03e87b5e-1e4e-4bf6-a50c-29a9e08eb490
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331714245 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.3331714245
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1503016825
Short name T182
Test name
Test status
Simulation time 214785786590 ps
CPU time 356.17 seconds
Started Jan 21 09:12:57 PM PST 24
Finished Jan 21 09:18:56 PM PST 24
Peak memory 183496 kb
Host smart-a7354ddb-dbd6-46cb-95c3-2cc45ebbc3d3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503016825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.1503016825
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.2206839148
Short name T25
Test name
Test status
Simulation time 2350530454 ps
CPU time 2.16 seconds
Started Jan 21 09:12:46 PM PST 24
Finished Jan 21 09:12:51 PM PST 24
Peak memory 183260 kb
Host smart-a24377e2-d80f-4522-b0c4-5405b6ff1eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206839148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.2206839148
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.518111810
Short name T566
Test name
Test status
Simulation time 314309912584 ps
CPU time 2407.71 seconds
Started Jan 21 09:12:57 PM PST 24
Finished Jan 21 09:53:07 PM PST 24
Peak memory 191676 kb
Host smart-5cc5f77e-4946-4ff4-862d-94a6a8522c5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518111810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.518111810
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.1742596061
Short name T361
Test name
Test status
Simulation time 42191094890 ps
CPU time 16.15 seconds
Started Jan 21 09:12:52 PM PST 24
Finished Jan 21 09:13:10 PM PST 24
Peak memory 192536 kb
Host smart-07c21a5e-839f-4f50-8731-fa30851d7889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742596061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.1742596061
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.833409826
Short name T512
Test name
Test status
Simulation time 244167836785 ps
CPU time 370.18 seconds
Started Jan 21 09:34:00 PM PST 24
Finished Jan 21 09:40:27 PM PST 24
Peak memory 191632 kb
Host smart-5f9e523f-039d-40bb-8f0b-628a6822b013
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833409826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.
833409826
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.3665186460
Short name T114
Test name
Test status
Simulation time 80771049701 ps
CPU time 351.41 seconds
Started Jan 21 09:45:39 PM PST 24
Finished Jan 21 09:51:35 PM PST 24
Peak memory 206328 kb
Host smart-629f20b3-66f5-4546-a031-34d94a9fe4fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665186460 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.3665186460
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.318598613
Short name T327
Test name
Test status
Simulation time 38791769162 ps
CPU time 20.46 seconds
Started Jan 21 09:13:02 PM PST 24
Finished Jan 21 09:13:25 PM PST 24
Peak memory 183340 kb
Host smart-e5139e65-0f0c-440a-a1ca-15776e687a6e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318598613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.rv_timer_cfg_update_on_fly.318598613
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.2398507837
Short name T579
Test name
Test status
Simulation time 209632761482 ps
CPU time 247.51 seconds
Started Jan 21 09:12:52 PM PST 24
Finished Jan 21 09:17:01 PM PST 24
Peak memory 183468 kb
Host smart-e8f8e50b-394d-4ff6-9d8c-3afadba0888c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398507837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2398507837
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.1640017628
Short name T319
Test name
Test status
Simulation time 945213538820 ps
CPU time 630.67 seconds
Started Jan 21 09:12:51 PM PST 24
Finished Jan 21 09:23:23 PM PST 24
Peak memory 191672 kb
Host smart-d8221f5e-5427-4568-987f-768bd056c95c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640017628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1640017628
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.2401498801
Short name T337
Test name
Test status
Simulation time 12044603658 ps
CPU time 97.85 seconds
Started Jan 21 09:13:00 PM PST 24
Finished Jan 21 09:14:40 PM PST 24
Peak memory 193688 kb
Host smart-88013932-49c7-424a-920a-8a38ca8f15c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401498801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2401498801
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.3612386398
Short name T514
Test name
Test status
Simulation time 37586808349 ps
CPU time 292.32 seconds
Started Jan 21 09:13:01 PM PST 24
Finished Jan 21 09:17:55 PM PST 24
Peak memory 206304 kb
Host smart-7d3101f2-9669-4433-b2d7-4f540411e2e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612386398 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.3612386398
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1024486227
Short name T202
Test name
Test status
Simulation time 271786661247 ps
CPU time 453.56 seconds
Started Jan 21 09:13:09 PM PST 24
Finished Jan 21 09:20:46 PM PST 24
Peak memory 183444 kb
Host smart-f7ffcecd-9e51-4515-aeba-742773ead2ed
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024486227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1024486227
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3298649173
Short name T505
Test name
Test status
Simulation time 16500014358 ps
CPU time 4.38 seconds
Started Jan 21 09:13:01 PM PST 24
Finished Jan 21 09:13:07 PM PST 24
Peak memory 183520 kb
Host smart-f37853b5-cc79-4236-ae84-013718bb84e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298649173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3298649173
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.3157269126
Short name T299
Test name
Test status
Simulation time 240044489553 ps
CPU time 219.63 seconds
Started Jan 21 09:13:03 PM PST 24
Finished Jan 21 09:16:45 PM PST 24
Peak memory 191676 kb
Host smart-928656cb-2827-493b-95c2-feeaf8486012
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157269126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3157269126
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2557419992
Short name T355
Test name
Test status
Simulation time 34348657174 ps
CPU time 54.5 seconds
Started Jan 21 09:13:10 PM PST 24
Finished Jan 21 09:14:08 PM PST 24
Peak memory 194896 kb
Host smart-106ddc6e-6b5c-4571-b664-437567709db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557419992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2557419992
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.3046161850
Short name T188
Test name
Test status
Simulation time 35927189400 ps
CPU time 35.85 seconds
Started Jan 21 09:13:13 PM PST 24
Finished Jan 21 09:13:52 PM PST 24
Peak memory 183408 kb
Host smart-6134270e-3b46-44f1-a866-e9954f19fab1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046161850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.3046161850
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.513864868
Short name T498
Test name
Test status
Simulation time 49007802676 ps
CPU time 40.8 seconds
Started Jan 21 09:13:08 PM PST 24
Finished Jan 21 09:13:52 PM PST 24
Peak memory 183492 kb
Host smart-8b5a47ed-475a-4d2b-aff0-29059f2327c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513864868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.513864868
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.2712685670
Short name T123
Test name
Test status
Simulation time 59306639005 ps
CPU time 29.77 seconds
Started Jan 21 09:13:09 PM PST 24
Finished Jan 21 09:13:42 PM PST 24
Peak memory 194000 kb
Host smart-b0c5230a-d767-4b2f-ab2d-97c2481b2a10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712685670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2712685670
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.1388133878
Short name T537
Test name
Test status
Simulation time 26306240848 ps
CPU time 293.12 seconds
Started Jan 21 09:13:13 PM PST 24
Finished Jan 21 09:18:09 PM PST 24
Peak memory 206308 kb
Host smart-910c8b28-9ed0-4b1d-b1ce-155b08aefcf7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388133878 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.1388133878
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3962604966
Short name T350
Test name
Test status
Simulation time 689923055366 ps
CPU time 736.35 seconds
Started Jan 21 09:13:23 PM PST 24
Finished Jan 21 09:25:41 PM PST 24
Peak memory 183484 kb
Host smart-f2075473-2eea-4cb2-b274-8373798d78bd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962604966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3962604966
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_random.1200143490
Short name T305
Test name
Test status
Simulation time 284679593933 ps
CPU time 281.14 seconds
Started Jan 21 10:35:27 PM PST 24
Finished Jan 21 10:40:09 PM PST 24
Peak memory 191680 kb
Host smart-d953c554-fd6e-433a-b966-47ce9416adb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200143490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.1200143490
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2354663122
Short name T267
Test name
Test status
Simulation time 84134569256 ps
CPU time 486.64 seconds
Started Jan 21 09:27:09 PM PST 24
Finished Jan 21 09:35:22 PM PST 24
Peak memory 183436 kb
Host smart-c5ebd6a5-db95-4053-98c7-188f2c07c91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354663122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2354663122
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.3087982284
Short name T551
Test name
Test status
Simulation time 83517211260 ps
CPU time 201.52 seconds
Started Jan 21 09:13:28 PM PST 24
Finished Jan 21 09:16:51 PM PST 24
Peak memory 206264 kb
Host smart-328255b5-226c-4606-b2f3-eb60f6e73e0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087982284 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.3087982284
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.3182703673
Short name T201
Test name
Test status
Simulation time 277760510111 ps
CPU time 133.77 seconds
Started Jan 21 09:13:26 PM PST 24
Finished Jan 21 09:15:43 PM PST 24
Peak memory 183468 kb
Host smart-aa118106-34d9-45b5-b176-96368f824cea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182703673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.3182703673
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.320227700
Short name T46
Test name
Test status
Simulation time 253575247059 ps
CPU time 203.75 seconds
Started Jan 21 09:13:29 PM PST 24
Finished Jan 21 09:16:55 PM PST 24
Peak memory 183484 kb
Host smart-4eef4b72-0002-451a-b0e5-cd396f45e0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320227700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.320227700
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.298038690
Short name T178
Test name
Test status
Simulation time 700429077590 ps
CPU time 290.09 seconds
Started Jan 21 09:13:31 PM PST 24
Finished Jan 21 09:18:24 PM PST 24
Peak memory 191628 kb
Host smart-f277a7c5-5778-4f12-a2eb-43d93d5eb241
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298038690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.298038690
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.3755488997
Short name T322
Test name
Test status
Simulation time 323323412450 ps
CPU time 107.88 seconds
Started Jan 21 09:13:44 PM PST 24
Finished Jan 21 09:15:33 PM PST 24
Peak memory 183396 kb
Host smart-8af9438e-f53c-4616-aa1a-c05a3b704ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755488997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3755488997
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.1541750972
Short name T539
Test name
Test status
Simulation time 41519815219 ps
CPU time 310.79 seconds
Started Jan 21 09:13:37 PM PST 24
Finished Jan 21 09:18:52 PM PST 24
Peak memory 198180 kb
Host smart-cb41aa25-1a76-4e9e-b119-65166ad756a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541750972 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.1541750972
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3458425408
Short name T147
Test name
Test status
Simulation time 36542233533 ps
CPU time 37.98 seconds
Started Jan 21 09:13:43 PM PST 24
Finished Jan 21 09:14:22 PM PST 24
Peak memory 183420 kb
Host smart-723c61f9-1332-43a8-a6ce-21e766a73033
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458425408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3458425408
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2141034347
Short name T506
Test name
Test status
Simulation time 27675552510 ps
CPU time 21.65 seconds
Started Jan 21 09:13:44 PM PST 24
Finished Jan 21 09:14:07 PM PST 24
Peak memory 183508 kb
Host smart-80e65269-8933-4ca3-82ff-049372f97672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141034347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2141034347
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.2132804336
Short name T204
Test name
Test status
Simulation time 77416843868 ps
CPU time 695.38 seconds
Started Jan 21 09:13:41 PM PST 24
Finished Jan 21 09:25:18 PM PST 24
Peak memory 195228 kb
Host smart-2e8e9e1d-e058-4539-b154-4a7e7b1f0c65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132804336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2132804336
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3156168119
Short name T28
Test name
Test status
Simulation time 60220612786 ps
CPU time 841.75 seconds
Started Jan 21 09:13:50 PM PST 24
Finished Jan 21 09:27:53 PM PST 24
Peak memory 183440 kb
Host smart-d18305a0-e7b9-4221-8e6e-3aff74b0bfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156168119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3156168119
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.1807185013
Short name T557
Test name
Test status
Simulation time 223927116603 ps
CPU time 769.16 seconds
Started Jan 21 09:13:46 PM PST 24
Finished Jan 21 09:26:36 PM PST 24
Peak memory 213896 kb
Host smart-1b39c42f-55be-4b26-b710-d245b9ae37cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807185013 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.1807185013
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3158702322
Short name T187
Test name
Test status
Simulation time 363863090859 ps
CPU time 672.82 seconds
Started Jan 21 09:13:56 PM PST 24
Finished Jan 21 09:25:15 PM PST 24
Peak memory 183504 kb
Host smart-2ba23aa5-a647-4f91-a2b5-b689290973a3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158702322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3158702322
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.563924478
Short name T527
Test name
Test status
Simulation time 832728541424 ps
CPU time 200.03 seconds
Started Jan 21 09:13:46 PM PST 24
Finished Jan 21 09:17:07 PM PST 24
Peak memory 183416 kb
Host smart-ffe425ce-7fe1-473e-a0a3-bd1309ac7982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563924478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.563924478
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.4293940005
Short name T591
Test name
Test status
Simulation time 69132761437 ps
CPU time 62.39 seconds
Started Jan 21 09:13:49 PM PST 24
Finished Jan 21 09:14:54 PM PST 24
Peak memory 183488 kb
Host smart-977d49a2-28e9-480a-8c02-f658c3874c47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293940005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.4293940005
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2724458307
Short name T119
Test name
Test status
Simulation time 23414196572 ps
CPU time 19.31 seconds
Started Jan 21 09:13:56 PM PST 24
Finished Jan 21 09:14:21 PM PST 24
Peak memory 183216 kb
Host smart-6f6f124b-15ec-4798-86a4-27831997092c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724458307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2724458307
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.3416105889
Short name T573
Test name
Test status
Simulation time 879566175894 ps
CPU time 358.24 seconds
Started Jan 21 09:13:57 PM PST 24
Finished Jan 21 09:20:06 PM PST 24
Peak memory 194744 kb
Host smart-f6d6dcc1-40e0-45d8-8634-6a20764057c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416105889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.3416105889
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.3554646051
Short name T36
Test name
Test status
Simulation time 321708911352 ps
CPU time 622.1 seconds
Started Jan 21 09:13:56 PM PST 24
Finished Jan 21 09:24:24 PM PST 24
Peak memory 206328 kb
Host smart-3dddb91e-f6dd-4205-afc1-d663cecff8da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554646051 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.3554646051
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2419623972
Short name T330
Test name
Test status
Simulation time 1713072608298 ps
CPU time 929.95 seconds
Started Jan 21 09:14:04 PM PST 24
Finished Jan 21 09:29:51 PM PST 24
Peak memory 183412 kb
Host smart-ef728d10-474e-4ae6-900d-80183b989148
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419623972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2419623972
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.2001126679
Short name T577
Test name
Test status
Simulation time 48285079497 ps
CPU time 62.99 seconds
Started Jan 21 09:14:04 PM PST 24
Finished Jan 21 09:15:24 PM PST 24
Peak memory 183472 kb
Host smart-532d48a3-2e50-4afb-9917-0bc284c3115c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001126679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2001126679
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.2099931518
Short name T220
Test name
Test status
Simulation time 140039176194 ps
CPU time 274.93 seconds
Started Jan 21 09:14:00 PM PST 24
Finished Jan 21 09:18:51 PM PST 24
Peak memory 191696 kb
Host smart-d22bc343-51fc-42de-a107-f12716bf32d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099931518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2099931518
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1754762234
Short name T602
Test name
Test status
Simulation time 781842711 ps
CPU time 1.45 seconds
Started Jan 21 09:14:03 PM PST 24
Finished Jan 21 09:14:23 PM PST 24
Peak memory 183092 kb
Host smart-57ab2137-5ed8-42e3-97c6-ccecdb1ee84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754762234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1754762234
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.3029179793
Short name T567
Test name
Test status
Simulation time 102725066389 ps
CPU time 86.73 seconds
Started Jan 21 09:14:04 PM PST 24
Finished Jan 21 09:15:48 PM PST 24
Peak memory 183504 kb
Host smart-d9f33185-4ec6-4854-9289-406ed81cfcc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029179793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.3029179793
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1921828875
Short name T526
Test name
Test status
Simulation time 693200032101 ps
CPU time 206.67 seconds
Started Jan 21 09:14:11 PM PST 24
Finished Jan 21 09:17:53 PM PST 24
Peak memory 183368 kb
Host smart-e769d9a4-2fcd-432b-9fbc-9f4db2d780fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921828875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1921828875
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.3759304615
Short name T542
Test name
Test status
Simulation time 18384181944 ps
CPU time 28.18 seconds
Started Jan 21 09:14:14 PM PST 24
Finished Jan 21 09:14:56 PM PST 24
Peak memory 183468 kb
Host smart-7dbdea9d-1b89-4cc0-ac26-a9aa66ee0ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759304615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.3759304615
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.3803775820
Short name T269
Test name
Test status
Simulation time 85637396984 ps
CPU time 159.69 seconds
Started Jan 21 09:47:35 PM PST 24
Finished Jan 21 09:50:16 PM PST 24
Peak memory 194872 kb
Host smart-d711ac6c-c246-45b0-8fbe-c758dc612db7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803775820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3803775820
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1141723198
Short name T489
Test name
Test status
Simulation time 1427883610 ps
CPU time 1.28 seconds
Started Jan 21 09:47:23 PM PST 24
Finished Jan 21 09:47:33 PM PST 24
Peak memory 193828 kb
Host smart-f644946f-924d-43a1-9780-1fb3d65cd0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141723198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1141723198
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.2224266906
Short name T531
Test name
Test status
Simulation time 55108915543 ps
CPU time 270.3 seconds
Started Jan 21 09:14:11 PM PST 24
Finished Jan 21 09:18:57 PM PST 24
Peak memory 206340 kb
Host smart-200c73eb-19ee-4e41-92f1-0eed8d79bd1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224266906 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.2224266906
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3807329889
Short name T286
Test name
Test status
Simulation time 2067953355202 ps
CPU time 1211.19 seconds
Started Jan 21 09:12:03 PM PST 24
Finished Jan 21 09:32:18 PM PST 24
Peak memory 183448 kb
Host smart-a670affb-68e3-4520-a50c-adbffcec41d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807329889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.3807329889
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.4130257367
Short name T23
Test name
Test status
Simulation time 72285586150 ps
CPU time 112.8 seconds
Started Jan 21 09:12:07 PM PST 24
Finished Jan 21 09:14:03 PM PST 24
Peak memory 183236 kb
Host smart-f264f19f-793e-42bd-b9c7-7e43f33b29e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130257367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.4130257367
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.61127907
Short name T603
Test name
Test status
Simulation time 44154855078 ps
CPU time 138.38 seconds
Started Jan 21 09:12:07 PM PST 24
Finished Jan 21 09:14:29 PM PST 24
Peak memory 183352 kb
Host smart-49c10a1f-72f5-4bbf-b0de-bc7bc12ee5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61127907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.61127907
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3229031480
Short name T18
Test name
Test status
Simulation time 78301258 ps
CPU time 0.87 seconds
Started Jan 21 09:12:07 PM PST 24
Finished Jan 21 09:12:11 PM PST 24
Peak memory 213484 kb
Host smart-9876e670-18bd-4b1e-b950-6ba7d7d59d2a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229031480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3229031480
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.2018488902
Short name T499
Test name
Test status
Simulation time 48418308069 ps
CPU time 213.84 seconds
Started Jan 21 09:11:59 PM PST 24
Finished Jan 21 09:15:38 PM PST 24
Peak memory 206348 kb
Host smart-90577fda-79e3-4c7d-a87e-e0903ee8f262
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018488902 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.2018488902
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.1906136082
Short name T356
Test name
Test status
Simulation time 4027586862736 ps
CPU time 1198.95 seconds
Started Jan 21 09:14:24 PM PST 24
Finished Jan 21 09:34:35 PM PST 24
Peak memory 183416 kb
Host smart-7294e12f-dade-4aaa-97d9-f3f784403a30
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906136082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.1906136082
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1615561903
Short name T525
Test name
Test status
Simulation time 61840202140 ps
CPU time 86.37 seconds
Started Jan 21 09:14:12 PM PST 24
Finished Jan 21 09:15:54 PM PST 24
Peak memory 183424 kb
Host smart-fcb65378-faa5-4c20-941e-06788eb08403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615561903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1615561903
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.3510151993
Short name T10
Test name
Test status
Simulation time 33095664554 ps
CPU time 45.3 seconds
Started Jan 21 09:14:13 PM PST 24
Finished Jan 21 09:15:13 PM PST 24
Peak memory 193604 kb
Host smart-21d67ac3-6def-45ec-b87b-d344f852b0ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510151993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3510151993
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1660773045
Short name T266
Test name
Test status
Simulation time 368424137479 ps
CPU time 66.95 seconds
Started Jan 21 09:14:23 PM PST 24
Finished Jan 21 09:15:42 PM PST 24
Peak memory 194056 kb
Host smart-2be1dc5a-c787-4249-afb0-812797eeac6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660773045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1660773045
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.2474097605
Short name T324
Test name
Test status
Simulation time 59595240069 ps
CPU time 501.29 seconds
Started Jan 21 09:14:25 PM PST 24
Finished Jan 21 09:22:58 PM PST 24
Peak memory 206300 kb
Host smart-b52ea818-a4de-4373-ac3d-05d4eb94d52f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474097605 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.2474097605
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2538142373
Short name T215
Test name
Test status
Simulation time 150948485099 ps
CPU time 79.6 seconds
Started Jan 21 09:14:30 PM PST 24
Finished Jan 21 09:15:59 PM PST 24
Peak memory 183452 kb
Host smart-7dfe8f29-5838-4df6-9400-4f0fe17a8323
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538142373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2538142373
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.4210874212
Short name T582
Test name
Test status
Simulation time 53769182033 ps
CPU time 81.58 seconds
Started Jan 21 09:14:30 PM PST 24
Finished Jan 21 09:16:01 PM PST 24
Peak memory 183500 kb
Host smart-5996b8e8-5f70-454a-9102-6f34c8cb1c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210874212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.4210874212
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2256576899
Short name T313
Test name
Test status
Simulation time 236684309632 ps
CPU time 214.14 seconds
Started Jan 21 09:14:34 PM PST 24
Finished Jan 21 09:18:17 PM PST 24
Peak memory 183448 kb
Host smart-86ab9a7b-60a3-4b7b-b97f-7e61d731dc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256576899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2256576899
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.96877609
Short name T77
Test name
Test status
Simulation time 67208931962 ps
CPU time 349.47 seconds
Started Jan 21 09:14:31 PM PST 24
Finished Jan 21 09:20:30 PM PST 24
Peak memory 198068 kb
Host smart-20f2f0fe-1556-4ac4-9fd3-f15fd6fa5f56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96877609 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.96877609
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3059567717
Short name T495
Test name
Test status
Simulation time 5522503817 ps
CPU time 9.6 seconds
Started Jan 21 10:12:11 PM PST 24
Finished Jan 21 10:12:23 PM PST 24
Peak memory 183508 kb
Host smart-7b216608-954f-4ae6-a68e-5249d21cf7bc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059567717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3059567717
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.152205915
Short name T513
Test name
Test status
Simulation time 16615565012 ps
CPU time 23.39 seconds
Started Jan 21 09:14:39 PM PST 24
Finished Jan 21 09:15:11 PM PST 24
Peak memory 183492 kb
Host smart-d6047cd3-2111-47df-9eca-646218bc70fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152205915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.152205915
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1278366030
Short name T170
Test name
Test status
Simulation time 1069572133359 ps
CPU time 1113.39 seconds
Started Jan 21 09:14:33 PM PST 24
Finished Jan 21 09:33:15 PM PST 24
Peak memory 191624 kb
Host smart-d55727a5-4711-4314-9754-abe51c1b1ee4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278366030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1278366030
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.304487132
Short name T101
Test name
Test status
Simulation time 157062721218 ps
CPU time 90.82 seconds
Started Jan 21 09:14:50 PM PST 24
Finished Jan 21 09:16:24 PM PST 24
Peak memory 183440 kb
Host smart-3817da3a-989e-48ff-aebf-61d447d21c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304487132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.304487132
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.38624193
Short name T578
Test name
Test status
Simulation time 131323664273 ps
CPU time 429.76 seconds
Started Jan 21 09:15:07 PM PST 24
Finished Jan 21 09:22:19 PM PST 24
Peak memory 206312 kb
Host smart-670f91af-cb39-4f80-99c5-cdddfafa1e7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38624193 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.38624193
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2743836413
Short name T200
Test name
Test status
Simulation time 18306516283 ps
CPU time 10.44 seconds
Started Jan 21 09:47:12 PM PST 24
Finished Jan 21 09:47:27 PM PST 24
Peak memory 183468 kb
Host smart-54cbb0ff-f8b8-4538-8bcc-352df28ba885
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743836413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2743836413
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.741783870
Short name T615
Test name
Test status
Simulation time 59125371177 ps
CPU time 59.61 seconds
Started Jan 21 09:15:08 PM PST 24
Finished Jan 21 09:16:09 PM PST 24
Peak memory 183416 kb
Host smart-aee6cd01-4bc6-4e4d-9303-cb6ebb4a9d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741783870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.741783870
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1427621646
Short name T599
Test name
Test status
Simulation time 22353099773 ps
CPU time 19.01 seconds
Started Jan 21 09:15:12 PM PST 24
Finished Jan 21 09:15:32 PM PST 24
Peak memory 183420 kb
Host smart-c52ef609-8746-46d3-9ce1-34719ed30c3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427621646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1427621646
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3087488041
Short name T508
Test name
Test status
Simulation time 25620570597 ps
CPU time 144.42 seconds
Started Jan 21 09:15:06 PM PST 24
Finished Jan 21 09:17:32 PM PST 24
Peak memory 191584 kb
Host smart-3cff7366-426f-4428-9ab1-3a39e4de1c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087488041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3087488041
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.2026904699
Short name T554
Test name
Test status
Simulation time 29793399744 ps
CPU time 562.02 seconds
Started Jan 21 09:15:07 PM PST 24
Finished Jan 21 09:24:30 PM PST 24
Peak memory 206324 kb
Host smart-0276b849-5ff4-4a4f-8e1e-72ee6260f9d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026904699 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.2026904699
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1751052571
Short name T130
Test name
Test status
Simulation time 416503016604 ps
CPU time 188.33 seconds
Started Jan 21 10:24:17 PM PST 24
Finished Jan 21 10:27:29 PM PST 24
Peak memory 183436 kb
Host smart-1aa7a73e-64f9-4bef-9a70-7feed56bc688
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751052571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.1751052571
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.566987591
Short name T596
Test name
Test status
Simulation time 416353877668 ps
CPU time 180.25 seconds
Started Jan 21 10:06:16 PM PST 24
Finished Jan 21 10:09:22 PM PST 24
Peak memory 183460 kb
Host smart-08fd539d-77cd-403f-9b7e-98d9ed5c80dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566987591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.566987591
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.2895641299
Short name T593
Test name
Test status
Simulation time 129026570083 ps
CPU time 81.65 seconds
Started Jan 21 09:15:06 PM PST 24
Finished Jan 21 09:16:29 PM PST 24
Peak memory 183432 kb
Host smart-55dc0d93-08f4-48e4-af51-bf12e3115dc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895641299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2895641299
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3460209391
Short name T331
Test name
Test status
Simulation time 44850732699 ps
CPU time 290.99 seconds
Started Jan 21 10:12:17 PM PST 24
Finished Jan 21 10:17:10 PM PST 24
Peak memory 194852 kb
Host smart-3aec5fda-53bc-4758-b2d9-2c02d0d22a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460209391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3460209391
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1333514753
Short name T27
Test name
Test status
Simulation time 1825015634905 ps
CPU time 374.39 seconds
Started Jan 21 09:15:18 PM PST 24
Finished Jan 21 09:21:34 PM PST 24
Peak memory 191672 kb
Host smart-6e1a969f-a785-41be-9e10-c6c691830868
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333514753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1333514753
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.2795328932
Short name T320
Test name
Test status
Simulation time 107173070955 ps
CPU time 2330.24 seconds
Started Jan 21 09:15:17 PM PST 24
Finished Jan 21 09:54:09 PM PST 24
Peak memory 214428 kb
Host smart-83421939-3bf0-47f0-9992-fbc585705f04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795328932 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.2795328932
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3991942467
Short name T321
Test name
Test status
Simulation time 446486945693 ps
CPU time 462 seconds
Started Jan 21 09:47:33 PM PST 24
Finished Jan 21 09:55:17 PM PST 24
Peak memory 183472 kb
Host smart-4599a4ff-04d2-471a-9e2c-143ba435a1ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991942467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3991942467
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.2303516147
Short name T556
Test name
Test status
Simulation time 363805437582 ps
CPU time 128.09 seconds
Started Jan 21 09:15:18 PM PST 24
Finished Jan 21 09:17:28 PM PST 24
Peak memory 183492 kb
Host smart-d380c0ea-4c39-4466-99a3-82954ffdce9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303516147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2303516147
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.3604251656
Short name T112
Test name
Test status
Simulation time 23006191103 ps
CPU time 44.03 seconds
Started Jan 21 11:10:12 PM PST 24
Finished Jan 21 11:10:57 PM PST 24
Peak memory 191820 kb
Host smart-d81ac508-adcc-4439-bab5-6e3a6d2bdab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604251656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3604251656
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.3147113224
Short name T257
Test name
Test status
Simulation time 46101558633 ps
CPU time 92.61 seconds
Started Jan 21 09:15:22 PM PST 24
Finished Jan 21 09:16:56 PM PST 24
Peak memory 191420 kb
Host smart-2d9a3945-7316-4de7-8ab3-83c57f5b4531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147113224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3147113224
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1704900122
Short name T613
Test name
Test status
Simulation time 464179559750 ps
CPU time 280.05 seconds
Started Jan 21 09:15:19 PM PST 24
Finished Jan 21 09:20:02 PM PST 24
Peak memory 191632 kb
Host smart-9718fa46-da61-4d84-a23e-1bfc354acd88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704900122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1704900122
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.1660420571
Short name T606
Test name
Test status
Simulation time 48669484852 ps
CPU time 195.08 seconds
Started Jan 21 09:15:22 PM PST 24
Finished Jan 21 09:18:39 PM PST 24
Peak memory 197880 kb
Host smart-dd32762c-6d6c-43ab-81ee-346d6599851b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660420571 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.1660420571
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.179475984
Short name T535
Test name
Test status
Simulation time 120754511560 ps
CPU time 182.6 seconds
Started Jan 21 09:15:19 PM PST 24
Finished Jan 21 09:18:24 PM PST 24
Peak memory 183516 kb
Host smart-a260c5ad-bfb8-437e-91c7-0d75b3e20f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179475984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.179475984
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.942304365
Short name T179
Test name
Test status
Simulation time 45209928679 ps
CPU time 658.95 seconds
Started Jan 21 09:15:20 PM PST 24
Finished Jan 21 09:26:21 PM PST 24
Peak memory 191648 kb
Host smart-4d20beec-bdb6-4ede-98b4-5b66e05fed0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942304365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.942304365
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3631718829
Short name T244
Test name
Test status
Simulation time 123393647309 ps
CPU time 147.09 seconds
Started Jan 21 09:15:19 PM PST 24
Finished Jan 21 09:17:48 PM PST 24
Peak memory 195028 kb
Host smart-957bd5a6-29c9-4b56-a52e-f045d39f8825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631718829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3631718829
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3277968487
Short name T500
Test name
Test status
Simulation time 51508207083 ps
CPU time 63.6 seconds
Started Jan 21 09:15:18 PM PST 24
Finished Jan 21 09:16:24 PM PST 24
Peak memory 183320 kb
Host smart-f8f8fce5-dd6b-477a-8ab2-8b060b2ee589
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277968487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3277968487
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.2451697440
Short name T560
Test name
Test status
Simulation time 230021092694 ps
CPU time 314.57 seconds
Started Jan 21 09:15:17 PM PST 24
Finished Jan 21 09:20:32 PM PST 24
Peak memory 206304 kb
Host smart-bf6042a0-2fe6-47db-8fef-bb6dc000070b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451697440 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.2451697440
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.2613075147
Short name T136
Test name
Test status
Simulation time 159521190665 ps
CPU time 89.33 seconds
Started Jan 21 09:15:29 PM PST 24
Finished Jan 21 09:17:01 PM PST 24
Peak memory 183480 kb
Host smart-3b90a70a-2cb7-41c0-8c8e-5c1c8826f9e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613075147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.2613075147
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.3529283857
Short name T564
Test name
Test status
Simulation time 68062917524 ps
CPU time 107.79 seconds
Started Jan 21 09:15:29 PM PST 24
Finished Jan 21 09:17:19 PM PST 24
Peak memory 183404 kb
Host smart-1d14606c-bb64-4cfc-8c94-3f32f40a380e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529283857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3529283857
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.707214434
Short name T212
Test name
Test status
Simulation time 102262052584 ps
CPU time 186.59 seconds
Started Jan 21 09:15:29 PM PST 24
Finished Jan 21 09:18:38 PM PST 24
Peak memory 191736 kb
Host smart-daadf2b4-f23b-4eb1-b97e-8328d37ae998
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707214434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.707214434
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2291042874
Short name T584
Test name
Test status
Simulation time 50684872204 ps
CPU time 77.33 seconds
Started Jan 21 09:15:28 PM PST 24
Finished Jan 21 09:16:47 PM PST 24
Peak memory 195092 kb
Host smart-0258e314-bf64-48d6-8b67-9083c11407af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291042874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2291042874
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2494918295
Short name T357
Test name
Test status
Simulation time 162898200517 ps
CPU time 772.05 seconds
Started Jan 21 09:15:39 PM PST 24
Finished Jan 21 09:28:36 PM PST 24
Peak memory 191728 kb
Host smart-9b4aaa09-3012-48f2-84d3-2d7273a1953a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494918295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2494918295
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.786240426
Short name T534
Test name
Test status
Simulation time 431090698042 ps
CPU time 479.18 seconds
Started Jan 21 09:15:31 PM PST 24
Finished Jan 21 09:23:33 PM PST 24
Peak memory 206292 kb
Host smart-34c5245a-c4ed-41d3-a5fc-a1d747fb1abf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786240426 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.786240426
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.2497021523
Short name T113
Test name
Test status
Simulation time 273661440016 ps
CPU time 151.18 seconds
Started Jan 21 09:15:41 PM PST 24
Finished Jan 21 09:18:19 PM PST 24
Peak memory 183424 kb
Host smart-9c1ef443-5bf5-464f-b994-3909432b290f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497021523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.2497021523
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3710861163
Short name T538
Test name
Test status
Simulation time 149912105682 ps
CPU time 189.79 seconds
Started Jan 21 09:15:39 PM PST 24
Finished Jan 21 09:18:54 PM PST 24
Peak memory 183500 kb
Host smart-01c58a7f-9691-4852-9163-8c4cbe5b92a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710861163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3710861163
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1910587009
Short name T590
Test name
Test status
Simulation time 51136015499 ps
CPU time 71.37 seconds
Started Jan 21 09:15:40 PM PST 24
Finished Jan 21 09:16:56 PM PST 24
Peak memory 191988 kb
Host smart-6ad3bf6b-1c28-430b-8d32-a9d44381b987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910587009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1910587009
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.4034302165
Short name T515
Test name
Test status
Simulation time 156729645141 ps
CPU time 62.88 seconds
Started Jan 21 09:15:56 PM PST 24
Finished Jan 21 09:17:01 PM PST 24
Peak memory 183432 kb
Host smart-cf345152-96ca-4deb-9c8c-37cc34d7daa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034302165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.4034302165
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.214898227
Short name T255
Test name
Test status
Simulation time 68101940476 ps
CPU time 17.89 seconds
Started Jan 21 09:15:47 PM PST 24
Finished Jan 21 09:16:10 PM PST 24
Peak memory 183680 kb
Host smart-1124b8f4-57e0-46b1-bf08-e35fbcc041a1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214898227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.rv_timer_cfg_update_on_fly.214898227
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.4124368897
Short name T552
Test name
Test status
Simulation time 242497844549 ps
CPU time 92.24 seconds
Started Jan 21 09:15:50 PM PST 24
Finished Jan 21 09:17:26 PM PST 24
Peak memory 183460 kb
Host smart-609f457e-caab-4c4b-83ca-fa521c066c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124368897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.4124368897
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.1260245351
Short name T583
Test name
Test status
Simulation time 36605273415 ps
CPU time 1358.48 seconds
Started Jan 21 09:15:48 PM PST 24
Finished Jan 21 09:38:32 PM PST 24
Peak memory 183488 kb
Host smart-c7557abf-168e-4291-80e9-6a6fb5ef95a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260245351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1260245351
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3201796125
Short name T574
Test name
Test status
Simulation time 160245427718 ps
CPU time 77.49 seconds
Started Jan 21 09:15:56 PM PST 24
Finished Jan 21 09:17:15 PM PST 24
Peak memory 194768 kb
Host smart-8e5e76d7-e586-483d-a3ac-f0890b6177e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201796125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3201796125
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3207134167
Short name T138
Test name
Test status
Simulation time 224046628955 ps
CPU time 538.93 seconds
Started Jan 21 09:15:48 PM PST 24
Finished Jan 21 09:24:52 PM PST 24
Peak memory 191648 kb
Host smart-599fe7dd-879f-4cb1-a377-2ffec7a8b83c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207134167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3207134167
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.2818560795
Short name T546
Test name
Test status
Simulation time 162151676430 ps
CPU time 370.48 seconds
Started Jan 21 10:15:49 PM PST 24
Finished Jan 21 10:22:06 PM PST 24
Peak memory 198124 kb
Host smart-580de296-1c0c-42e3-ad10-391b77a9f4f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818560795 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.2818560795
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2134089184
Short name T504
Test name
Test status
Simulation time 199755805595 ps
CPU time 312.35 seconds
Started Jan 21 09:11:58 PM PST 24
Finished Jan 21 09:17:16 PM PST 24
Peak memory 183388 kb
Host smart-5bcd0ddb-8050-4d6f-83aa-e6cfedce5d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134089184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2134089184
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.1573560862
Short name T288
Test name
Test status
Simulation time 117260768900 ps
CPU time 144.79 seconds
Started Jan 21 09:12:03 PM PST 24
Finished Jan 21 09:14:32 PM PST 24
Peak memory 183524 kb
Host smart-f24a25ad-5f15-436c-901b-2566b9e8e06a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573560862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.1573560862
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2969859839
Short name T488
Test name
Test status
Simulation time 967560454 ps
CPU time 1.75 seconds
Started Jan 21 10:14:58 PM PST 24
Finished Jan 21 10:15:22 PM PST 24
Peak memory 183320 kb
Host smart-e6e960df-922f-4fa2-9d61-79052146608e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969859839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2969859839
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.1079044501
Short name T19
Test name
Test status
Simulation time 139156701 ps
CPU time 0.86 seconds
Started Jan 21 09:12:08 PM PST 24
Finished Jan 21 09:12:12 PM PST 24
Peak memory 213572 kb
Host smart-276b827b-92d4-409b-9e1d-b528a081efeb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079044501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1079044501
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.2350762771
Short name T494
Test name
Test status
Simulation time 38157236124 ps
CPU time 673.04 seconds
Started Jan 21 09:12:05 PM PST 24
Finished Jan 21 09:23:22 PM PST 24
Peak memory 206280 kb
Host smart-cb45a654-ab6c-447c-9b43-03f69758ad4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350762771 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.2350762771
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1075708940
Short name T570
Test name
Test status
Simulation time 10068107716 ps
CPU time 16.18 seconds
Started Jan 21 09:15:47 PM PST 24
Finished Jan 21 09:16:08 PM PST 24
Peak memory 183496 kb
Host smart-24890aca-f631-4190-88f2-ea7c66445204
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075708940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1075708940
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2814606480
Short name T517
Test name
Test status
Simulation time 105419281141 ps
CPU time 46.86 seconds
Started Jan 21 09:15:49 PM PST 24
Finished Jan 21 09:16:40 PM PST 24
Peak memory 183412 kb
Host smart-4a28dc60-b124-4b30-b02a-6fcaebad8e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814606480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2814606480
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.1961800472
Short name T276
Test name
Test status
Simulation time 215970908330 ps
CPU time 586.18 seconds
Started Jan 21 09:15:56 PM PST 24
Finished Jan 21 09:25:44 PM PST 24
Peak memory 191688 kb
Host smart-b64cea67-c0d6-4d68-adfa-19d4c1e5842d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961800472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1961800472
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1937544617
Short name T604
Test name
Test status
Simulation time 13732024992 ps
CPU time 6.66 seconds
Started Jan 21 09:15:50 PM PST 24
Finished Jan 21 09:16:01 PM PST 24
Peak memory 183460 kb
Host smart-8e05153f-ea99-4641-b53c-47b5c5c1e5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937544617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1937544617
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1109375343
Short name T163
Test name
Test status
Simulation time 608461963163 ps
CPU time 1262.52 seconds
Started Jan 21 09:15:58 PM PST 24
Finished Jan 21 09:37:02 PM PST 24
Peak memory 191620 kb
Host smart-7b53ffad-c03b-4fe8-833c-7f69d70bfa8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109375343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1109375343
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.1407852979
Short name T228
Test name
Test status
Simulation time 268548900996 ps
CPU time 541.8 seconds
Started Jan 21 09:15:59 PM PST 24
Finished Jan 21 09:25:02 PM PST 24
Peak memory 207776 kb
Host smart-7d7823af-bc36-4542-b279-cc9fbf4d43d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407852979 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.1407852979
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1797823574
Short name T211
Test name
Test status
Simulation time 762399746458 ps
CPU time 377.51 seconds
Started Jan 21 09:16:06 PM PST 24
Finished Jan 21 09:22:25 PM PST 24
Peak memory 183492 kb
Host smart-5be23b26-1a10-4dd4-ba24-ce3018c1ab84
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797823574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1797823574
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.1263685814
Short name T507
Test name
Test status
Simulation time 159419531789 ps
CPU time 202.42 seconds
Started Jan 21 09:16:01 PM PST 24
Finished Jan 21 09:19:25 PM PST 24
Peak memory 183500 kb
Host smart-439bd482-3000-42b6-94f8-a76ff1d60cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263685814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1263685814
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.2420982588
Short name T118
Test name
Test status
Simulation time 619847401937 ps
CPU time 588.76 seconds
Started Jan 21 09:15:57 PM PST 24
Finished Jan 21 09:25:47 PM PST 24
Peak memory 191656 kb
Host smart-75f5fe18-2b2c-417f-ba81-ee0f85864c1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420982588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2420982588
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.304664051
Short name T174
Test name
Test status
Simulation time 134273254218 ps
CPU time 63.53 seconds
Started Jan 21 09:15:59 PM PST 24
Finished Jan 21 09:17:03 PM PST 24
Peak memory 191648 kb
Host smart-27590419-146c-4607-9e60-7048a14dba00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304664051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.304664051
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.842278882
Short name T166
Test name
Test status
Simulation time 499451811006 ps
CPU time 346.37 seconds
Started Jan 21 09:16:00 PM PST 24
Finished Jan 21 09:21:48 PM PST 24
Peak memory 191752 kb
Host smart-0153bc27-c72b-4079-b8c1-eb9e6333ecaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842278882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.
842278882
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.1201096471
Short name T284
Test name
Test status
Simulation time 242477829521 ps
CPU time 969 seconds
Started Jan 21 09:15:59 PM PST 24
Finished Jan 21 09:32:09 PM PST 24
Peak memory 213508 kb
Host smart-3538bdb9-cdee-467a-b236-6b83df9e41b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201096471 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.1201096471
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3921784600
Short name T344
Test name
Test status
Simulation time 1521135520847 ps
CPU time 547.85 seconds
Started Jan 21 09:16:16 PM PST 24
Finished Jan 21 09:25:25 PM PST 24
Peak memory 183436 kb
Host smart-12743281-83b2-4fb4-a7b9-a61a79c45866
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921784600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.3921784600
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2152963187
Short name T501
Test name
Test status
Simulation time 67746571749 ps
CPU time 70.46 seconds
Started Jan 21 09:15:57 PM PST 24
Finished Jan 21 09:17:09 PM PST 24
Peak memory 183520 kb
Host smart-35b281f2-2c72-4bc8-927b-da0a363cea23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152963187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2152963187
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.186457077
Short name T340
Test name
Test status
Simulation time 171674067748 ps
CPU time 730.89 seconds
Started Jan 21 09:16:00 PM PST 24
Finished Jan 21 09:28:12 PM PST 24
Peak memory 191624 kb
Host smart-1b60a89d-5b53-4d74-a109-5c2f49f800de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186457077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.186457077
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1202977042
Short name T329
Test name
Test status
Simulation time 28978509269 ps
CPU time 40.9 seconds
Started Jan 21 09:16:10 PM PST 24
Finished Jan 21 09:16:53 PM PST 24
Peak memory 183388 kb
Host smart-957ea572-cfee-410d-947b-5acfa9ad6ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202977042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1202977042
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.2508821768
Short name T13
Test name
Test status
Simulation time 46252533627 ps
CPU time 504.04 seconds
Started Jan 21 09:16:17 PM PST 24
Finished Jan 21 09:24:42 PM PST 24
Peak memory 210148 kb
Host smart-f014b335-1339-436c-b9c2-366952a85e88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508821768 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.2508821768
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3211228993
Short name T214
Test name
Test status
Simulation time 691544757 ps
CPU time 1.76 seconds
Started Jan 21 09:16:17 PM PST 24
Finished Jan 21 09:16:21 PM PST 24
Peak memory 183068 kb
Host smart-bb7deaa8-71ed-44cd-94b6-52633dfeb5a7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211228993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3211228993
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.2487283186
Short name T524
Test name
Test status
Simulation time 8851383926 ps
CPU time 13.57 seconds
Started Jan 21 09:16:18 PM PST 24
Finished Jan 21 09:16:33 PM PST 24
Peak memory 183400 kb
Host smart-9fc42948-5854-4688-8532-87a9db042db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487283186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2487283186
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.3034854259
Short name T216
Test name
Test status
Simulation time 148504816732 ps
CPU time 181.97 seconds
Started Jan 21 09:16:17 PM PST 24
Finished Jan 21 09:19:21 PM PST 24
Peak memory 191620 kb
Host smart-e1ed40cb-a3f9-4f28-939d-f61f97fd197c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034854259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3034854259
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.1817927596
Short name T571
Test name
Test status
Simulation time 199538718786 ps
CPU time 416.26 seconds
Started Jan 21 09:16:31 PM PST 24
Finished Jan 21 09:23:30 PM PST 24
Peak memory 209820 kb
Host smart-18f750f9-58f9-4ead-afdf-08dd14522daf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817927596 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.1817927596
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3634280494
Short name T303
Test name
Test status
Simulation time 18102980029 ps
CPU time 33.31 seconds
Started Jan 21 09:16:31 PM PST 24
Finished Jan 21 09:17:06 PM PST 24
Peak memory 183444 kb
Host smart-41ccf678-be2a-4d4d-9823-0480c7449580
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634280494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3634280494
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.974345802
Short name T530
Test name
Test status
Simulation time 703393255447 ps
CPU time 196.05 seconds
Started Jan 21 09:16:32 PM PST 24
Finished Jan 21 09:19:50 PM PST 24
Peak memory 183460 kb
Host smart-412c7b64-a00b-4097-b174-2cdee02bdc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974345802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.974345802
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1597937873
Short name T145
Test name
Test status
Simulation time 50450479204 ps
CPU time 44.01 seconds
Started Jan 21 09:16:30 PM PST 24
Finished Jan 21 09:17:16 PM PST 24
Peak memory 193820 kb
Host smart-eb45154c-985f-4c6e-aefa-3655ea73bf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597937873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1597937873
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.1466900771
Short name T75
Test name
Test status
Simulation time 361724582247 ps
CPU time 633.68 seconds
Started Jan 21 09:16:31 PM PST 24
Finished Jan 21 09:27:07 PM PST 24
Peak memory 206376 kb
Host smart-6e4fcff8-0278-44ae-9b4e-19c04c248daa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466900771 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.1466900771
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.3720647704
Short name T497
Test name
Test status
Simulation time 26447152393 ps
CPU time 19.13 seconds
Started Jan 21 09:16:56 PM PST 24
Finished Jan 21 09:17:17 PM PST 24
Peak memory 183416 kb
Host smart-9a91cd85-5e25-42da-a061-85f49855f0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720647704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3720647704
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.495583265
Short name T572
Test name
Test status
Simulation time 48426550157 ps
CPU time 112.66 seconds
Started Jan 21 09:16:55 PM PST 24
Finished Jan 21 09:18:50 PM PST 24
Peak memory 183432 kb
Host smart-b607a45a-ac57-4f72-953d-651fc30ebcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495583265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.495583265
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3412165431
Short name T608
Test name
Test status
Simulation time 171419940728 ps
CPU time 128.53 seconds
Started Jan 21 09:16:53 PM PST 24
Finished Jan 21 09:19:04 PM PST 24
Peak memory 183452 kb
Host smart-c388e1d5-92a2-401e-bf1c-ca4ff3f161b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412165431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3412165431
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.4218284013
Short name T529
Test name
Test status
Simulation time 77436533535 ps
CPU time 954.46 seconds
Started Jan 21 09:16:56 PM PST 24
Finished Jan 21 09:32:53 PM PST 24
Peak memory 198112 kb
Host smart-311262d1-8915-4f2e-b4a6-b5c66e6dcbde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218284013 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.4218284013
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3569068769
Short name T126
Test name
Test status
Simulation time 27978406523 ps
CPU time 51.54 seconds
Started Jan 21 09:16:58 PM PST 24
Finished Jan 21 09:17:52 PM PST 24
Peak memory 183504 kb
Host smart-19b761ed-8058-4ef1-808e-eaf863fffc18
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569068769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3569068769
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3069504970
Short name T563
Test name
Test status
Simulation time 431777377238 ps
CPU time 180.82 seconds
Started Jan 21 09:16:55 PM PST 24
Finished Jan 21 09:19:58 PM PST 24
Peak memory 183704 kb
Host smart-5c254888-841d-4f62-adaf-30d22d801a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069504970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3069504970
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.748567417
Short name T533
Test name
Test status
Simulation time 2697644533 ps
CPU time 4.04 seconds
Started Jan 21 09:16:54 PM PST 24
Finished Jan 21 09:17:00 PM PST 24
Peak memory 183064 kb
Host smart-8843e7ec-2427-46d0-8c12-081fef39e6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748567417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.748567417
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3566810654
Short name T146
Test name
Test status
Simulation time 248170433045 ps
CPU time 194.37 seconds
Started Jan 21 09:16:58 PM PST 24
Finished Jan 21 09:20:15 PM PST 24
Peak memory 191640 kb
Host smart-f2889def-6ff6-44a2-b7d8-f5ecdcdea6fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566810654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3566810654
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.2188683150
Short name T484
Test name
Test status
Simulation time 21060613838 ps
CPU time 169.55 seconds
Started Jan 21 09:16:56 PM PST 24
Finished Jan 21 09:19:48 PM PST 24
Peak memory 198328 kb
Host smart-acd63578-bca8-407e-9f1d-2d83790ce754
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188683150 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.2188683150
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2772899807
Short name T289
Test name
Test status
Simulation time 50277242420 ps
CPU time 81.02 seconds
Started Jan 21 09:16:59 PM PST 24
Finished Jan 21 09:18:24 PM PST 24
Peak memory 183444 kb
Host smart-0f289b7e-889f-4e50-bf92-d7d73b6789d5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772899807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2772899807
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.405924802
Short name T490
Test name
Test status
Simulation time 338028387272 ps
CPU time 146.58 seconds
Started Jan 21 09:16:56 PM PST 24
Finished Jan 21 09:19:24 PM PST 24
Peak memory 183468 kb
Host smart-966704eb-47f2-43ae-9556-b595f763ad40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405924802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.405924802
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.3272425628
Short name T226
Test name
Test status
Simulation time 504197353226 ps
CPU time 358.92 seconds
Started Jan 21 09:16:53 PM PST 24
Finished Jan 21 09:22:54 PM PST 24
Peak memory 194796 kb
Host smart-a4d54f34-5538-4ad9-9ddf-e9e45a339c6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272425628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3272425628
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3116592744
Short name T598
Test name
Test status
Simulation time 159433790811 ps
CPU time 448.5 seconds
Started Jan 21 09:17:08 PM PST 24
Finished Jan 21 09:24:39 PM PST 24
Peak memory 191704 kb
Host smart-320de229-65f0-4a12-ba5c-ea8483a446a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116592744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3116592744
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.2321963203
Short name T576
Test name
Test status
Simulation time 1104776225185 ps
CPU time 2250.33 seconds
Started Jan 21 09:17:09 PM PST 24
Finished Jan 21 09:54:42 PM PST 24
Peak memory 222664 kb
Host smart-23e28a21-1fcd-4a91-985a-22838fb03843
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321963203 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.2321963203
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.786544579
Short name T597
Test name
Test status
Simulation time 502587687497 ps
CPU time 198.77 seconds
Started Jan 21 09:17:09 PM PST 24
Finished Jan 21 09:20:31 PM PST 24
Peak memory 183432 kb
Host smart-7c710a5b-0de4-4a5d-83c8-91f12e1e69ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786544579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.786544579
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1156781134
Short name T486
Test name
Test status
Simulation time 333807218475 ps
CPU time 238.13 seconds
Started Jan 21 09:17:06 PM PST 24
Finished Jan 21 09:21:07 PM PST 24
Peak memory 183344 kb
Host smart-3240c57a-5f99-42a3-bfd0-25a66f9f120c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156781134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1156781134
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.684541434
Short name T272
Test name
Test status
Simulation time 141090105719 ps
CPU time 585.47 seconds
Started Jan 21 09:27:30 PM PST 24
Finished Jan 21 09:37:18 PM PST 24
Peak memory 191688 kb
Host smart-6711ddbd-ae9b-4369-97f5-3ef1af4990a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684541434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.684541434
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.1903019471
Short name T225
Test name
Test status
Simulation time 70847614379 ps
CPU time 425.83 seconds
Started Jan 21 09:27:00 PM PST 24
Finished Jan 21 09:34:17 PM PST 24
Peak memory 198136 kb
Host smart-3ebda55e-3d3f-4b6b-8c6a-7db070e77324
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903019471 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.1903019471
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.883568279
Short name T268
Test name
Test status
Simulation time 71628317747 ps
CPU time 123.61 seconds
Started Jan 21 10:05:32 PM PST 24
Finished Jan 21 10:07:44 PM PST 24
Peak memory 183496 kb
Host smart-62c655d2-f18b-49d5-8d8e-fc9d5ca99845
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883568279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.rv_timer_cfg_update_on_fly.883568279
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.2340058220
Short name T510
Test name
Test status
Simulation time 53485600662 ps
CPU time 78.08 seconds
Started Jan 21 09:17:17 PM PST 24
Finished Jan 21 09:18:41 PM PST 24
Peak memory 183460 kb
Host smart-951cea0f-76ee-47fb-a55e-fa70f572ad8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340058220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.2340058220
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.3371782560
Short name T197
Test name
Test status
Simulation time 366859950350 ps
CPU time 1728.43 seconds
Started Jan 21 09:17:16 PM PST 24
Finished Jan 21 09:46:10 PM PST 24
Peak memory 191588 kb
Host smart-13c2cfdc-807a-48de-806f-ed36889dfa64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371782560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3371782560
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.2746828632
Short name T298
Test name
Test status
Simulation time 36514956709 ps
CPU time 63.34 seconds
Started Jan 21 09:17:27 PM PST 24
Finished Jan 21 09:18:39 PM PST 24
Peak memory 183440 kb
Host smart-011f7fda-d247-48d3-8214-69eef2c58738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746828632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2746828632
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.3196335952
Short name T511
Test name
Test status
Simulation time 452393999901 ps
CPU time 1001.41 seconds
Started Jan 21 09:17:28 PM PST 24
Finished Jan 21 09:34:17 PM PST 24
Peak memory 207356 kb
Host smart-3a712d61-8c64-4fd9-aac1-f4e3def2ba8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196335952 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.3196335952
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.4052554538
Short name T345
Test name
Test status
Simulation time 1536966046187 ps
CPU time 808.85 seconds
Started Jan 21 09:12:19 PM PST 24
Finished Jan 21 09:25:53 PM PST 24
Peak memory 183368 kb
Host smart-4c9188d7-be1d-429b-818f-c0f7147ddc95
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052554538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.4052554538
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.2982544738
Short name T518
Test name
Test status
Simulation time 144601569161 ps
CPU time 193.75 seconds
Started Jan 21 09:12:19 PM PST 24
Finished Jan 21 09:15:38 PM PST 24
Peak memory 183380 kb
Host smart-7d2ca9ad-420c-4cfe-b3e4-118d3c28463a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982544738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2982544738
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.3156385459
Short name T354
Test name
Test status
Simulation time 152253808224 ps
CPU time 265.65 seconds
Started Jan 21 09:12:07 PM PST 24
Finished Jan 21 09:16:36 PM PST 24
Peak memory 191660 kb
Host smart-34d515a1-20bb-4360-8e5a-28288cf6335b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156385459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3156385459
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.4116148635
Short name T219
Test name
Test status
Simulation time 43628388094 ps
CPU time 127.37 seconds
Started Jan 21 09:12:06 PM PST 24
Finished Jan 21 09:14:17 PM PST 24
Peak memory 191652 kb
Host smart-41b15678-443e-4686-ab03-869f3da9d9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116148635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.4116148635
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.3428296988
Short name T99
Test name
Test status
Simulation time 529804029899 ps
CPU time 1109.03 seconds
Started Jan 21 09:12:07 PM PST 24
Finished Jan 21 09:30:40 PM PST 24
Peak memory 210632 kb
Host smart-abd610b9-ab7f-4884-bef6-f0efcc5fd3f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428296988 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.3428296988
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.rv_timer_random.65148335
Short name T171
Test name
Test status
Simulation time 314041756542 ps
CPU time 238.77 seconds
Started Jan 21 10:26:41 PM PST 24
Finished Jan 21 10:30:57 PM PST 24
Peak memory 194724 kb
Host smart-69fb6151-8c0e-4042-8839-caf1a6629b4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65148335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.65148335
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.2500730927
Short name T107
Test name
Test status
Simulation time 729547240814 ps
CPU time 307.85 seconds
Started Jan 21 09:17:40 PM PST 24
Finished Jan 21 09:22:51 PM PST 24
Peak memory 195088 kb
Host smart-2ccb980f-ad5f-4f2c-baaa-21a976564d5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500730927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2500730927
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.3281946852
Short name T612
Test name
Test status
Simulation time 597439292434 ps
CPU time 2184.91 seconds
Started Jan 21 09:17:41 PM PST 24
Finished Jan 21 09:54:09 PM PST 24
Peak memory 191664 kb
Host smart-68a779d8-b0af-40a4-a979-bf88f6ac7bf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281946852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.3281946852
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1690391794
Short name T98
Test name
Test status
Simulation time 190646503220 ps
CPU time 307.74 seconds
Started Jan 21 09:17:54 PM PST 24
Finished Jan 21 09:23:02 PM PST 24
Peak memory 194760 kb
Host smart-672a72c3-da0e-4e79-8746-956acc36d085
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690391794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1690391794
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3976432283
Short name T335
Test name
Test status
Simulation time 96004968973 ps
CPU time 109.73 seconds
Started Jan 21 09:28:27 PM PST 24
Finished Jan 21 09:30:23 PM PST 24
Peak memory 191692 kb
Host smart-7de6eec8-f787-4103-8d4f-02b8235d7e63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976432283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3976432283
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1196192070
Short name T347
Test name
Test status
Simulation time 11088115273 ps
CPU time 5.85 seconds
Started Jan 21 09:18:05 PM PST 24
Finished Jan 21 09:18:11 PM PST 24
Peak memory 183492 kb
Host smart-1c9cd69e-4241-43ea-8ced-81da8837434f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196192070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1196192070
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1592312779
Short name T87
Test name
Test status
Simulation time 2152289635102 ps
CPU time 722.67 seconds
Started Jan 21 09:12:03 PM PST 24
Finished Jan 21 09:24:10 PM PST 24
Peak memory 183452 kb
Host smart-c397bbb1-a209-4427-873a-5e03da9c9b09
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592312779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1592312779
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.3047206724
Short name T544
Test name
Test status
Simulation time 111344992796 ps
CPU time 91.68 seconds
Started Jan 21 09:46:42 PM PST 24
Finished Jan 21 09:48:18 PM PST 24
Peak memory 183500 kb
Host smart-62260d40-cddf-4c6f-a67d-7e64b025482e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047206724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3047206724
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.3432766635
Short name T594
Test name
Test status
Simulation time 5671146327 ps
CPU time 13.86 seconds
Started Jan 21 09:12:19 PM PST 24
Finished Jan 21 09:12:38 PM PST 24
Peak memory 183484 kb
Host smart-9ea7c34a-b191-40d5-ace4-97aeb7d7a5a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432766635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3432766635
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.60367141
Short name T307
Test name
Test status
Simulation time 36361032506 ps
CPU time 16.76 seconds
Started Jan 21 09:12:19 PM PST 24
Finished Jan 21 09:12:41 PM PST 24
Peak memory 183440 kb
Host smart-3dd9ff59-b5c7-4b65-becc-a00c666e8f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60367141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.60367141
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.4273087848
Short name T519
Test name
Test status
Simulation time 332777676514 ps
CPU time 543.99 seconds
Started Jan 21 09:12:05 PM PST 24
Finished Jan 21 09:21:13 PM PST 24
Peak memory 191728 kb
Host smart-416792e8-3ce0-484b-a862-fa138321fe54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273087848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
4273087848
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.2775408783
Short name T22
Test name
Test status
Simulation time 103284469357 ps
CPU time 841.5 seconds
Started Jan 21 09:12:19 PM PST 24
Finished Jan 21 09:26:25 PM PST 24
Peak memory 210060 kb
Host smart-37ffeab4-1133-4dfb-8f18-b2bd8d5bd840
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775408783 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.2775408783
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.689407165
Short name T279
Test name
Test status
Simulation time 148429466628 ps
CPU time 682.14 seconds
Started Jan 21 09:17:53 PM PST 24
Finished Jan 21 09:29:16 PM PST 24
Peak memory 191664 kb
Host smart-23756ada-b2a4-45d7-9610-bbe6481573ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689407165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.689407165
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.3913988421
Short name T341
Test name
Test status
Simulation time 201380588265 ps
CPU time 310.08 seconds
Started Jan 21 09:17:52 PM PST 24
Finished Jan 21 09:23:04 PM PST 24
Peak memory 191724 kb
Host smart-d5c80948-7c2a-4515-8428-1ec4b7c1ab7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913988421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3913988421
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.3877696717
Short name T229
Test name
Test status
Simulation time 191886158205 ps
CPU time 1460.86 seconds
Started Jan 21 09:17:52 PM PST 24
Finished Jan 21 09:42:15 PM PST 24
Peak memory 191632 kb
Host smart-d90de779-cdee-45af-a9ad-c5a4cf1bc998
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877696717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3877696717
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.258461922
Short name T252
Test name
Test status
Simulation time 516093146983 ps
CPU time 733.31 seconds
Started Jan 21 10:24:14 PM PST 24
Finished Jan 21 10:36:31 PM PST 24
Peak memory 191664 kb
Host smart-c99b4422-96ec-4870-bdb4-2052c27545c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258461922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.258461922
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.115675574
Short name T611
Test name
Test status
Simulation time 93530375370 ps
CPU time 150.6 seconds
Started Jan 21 09:17:55 PM PST 24
Finished Jan 21 09:20:28 PM PST 24
Peak memory 194332 kb
Host smart-c1d04e55-6537-4524-ae5a-93f790d4cd33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115675574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.115675574
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.2188125353
Short name T343
Test name
Test status
Simulation time 10182981613 ps
CPU time 19.78 seconds
Started Jan 21 09:17:54 PM PST 24
Finished Jan 21 09:18:14 PM PST 24
Peak memory 183420 kb
Host smart-2d55ca84-40e2-4e5c-8b87-367d217f47c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188125353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2188125353
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.2146261332
Short name T609
Test name
Test status
Simulation time 77664616289 ps
CPU time 100.61 seconds
Started Jan 21 09:39:52 PM PST 24
Finished Jan 21 09:41:34 PM PST 24
Peak memory 191988 kb
Host smart-3c7ca95b-2052-421f-95af-33913dd485e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146261332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2146261332
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1362463825
Short name T50
Test name
Test status
Simulation time 128873189417 ps
CPU time 73.61 seconds
Started Jan 21 09:17:55 PM PST 24
Finished Jan 21 09:19:10 PM PST 24
Peak memory 191668 kb
Host smart-2bf99e1e-7d0b-4bea-8377-3ac4fedc75e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362463825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1362463825
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.125668021
Short name T152
Test name
Test status
Simulation time 451767379640 ps
CPU time 318.97 seconds
Started Jan 21 09:45:35 PM PST 24
Finished Jan 21 09:50:57 PM PST 24
Peak memory 191708 kb
Host smart-a52fd085-74ed-43f6-9afe-1bc282d29217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125668021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.125668021
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.2950867943
Short name T196
Test name
Test status
Simulation time 160385497971 ps
CPU time 109.55 seconds
Started Jan 21 10:10:49 PM PST 24
Finished Jan 21 10:12:40 PM PST 24
Peak memory 183536 kb
Host smart-07f47b5f-7e4c-4a25-8efb-624e40132d50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950867943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2950867943
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1203298703
Short name T241
Test name
Test status
Simulation time 765308156009 ps
CPU time 667.48 seconds
Started Jan 21 09:12:25 PM PST 24
Finished Jan 21 09:23:40 PM PST 24
Peak memory 183484 kb
Host smart-bc45a8b4-1c92-41b2-b7ff-af06146b3d3d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203298703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1203298703
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.2880072556
Short name T492
Test name
Test status
Simulation time 65392245537 ps
CPU time 99.15 seconds
Started Jan 21 09:12:22 PM PST 24
Finished Jan 21 09:14:06 PM PST 24
Peak memory 183416 kb
Host smart-7403b554-b609-498e-95b3-842e97f2fd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880072556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.2880072556
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.1865795124
Short name T184
Test name
Test status
Simulation time 415470340519 ps
CPU time 1556.66 seconds
Started Jan 21 09:12:04 PM PST 24
Finished Jan 21 09:38:05 PM PST 24
Peak memory 194124 kb
Host smart-72a4b713-aff7-4a5f-9842-58796c735c8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865795124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1865795124
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.4083916649
Short name T296
Test name
Test status
Simulation time 182298174267 ps
CPU time 227 seconds
Started Jan 21 09:12:23 PM PST 24
Finished Jan 21 09:16:15 PM PST 24
Peak memory 195360 kb
Host smart-73d3105a-3abd-4083-b97a-904273516e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083916649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.4083916649
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.745734163
Short name T553
Test name
Test status
Simulation time 44648307236 ps
CPU time 459.16 seconds
Started Jan 21 09:12:21 PM PST 24
Finished Jan 21 09:20:06 PM PST 24
Peak memory 198120 kb
Host smart-8d60acae-023d-4978-98c1-3e004ae64630
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745734163 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.745734163
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.3545289839
Short name T160
Test name
Test status
Simulation time 24507024508 ps
CPU time 12.48 seconds
Started Jan 21 09:17:53 PM PST 24
Finished Jan 21 09:18:07 PM PST 24
Peak memory 183496 kb
Host smart-9097aacd-ab3f-4f11-9618-5a3b479000c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545289839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3545289839
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3891716892
Short name T177
Test name
Test status
Simulation time 247696477732 ps
CPU time 243.04 seconds
Started Jan 21 09:18:14 PM PST 24
Finished Jan 21 09:22:25 PM PST 24
Peak memory 191296 kb
Host smart-1733ddd9-8bd2-46dd-b01a-b295709220e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891716892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3891716892
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2856723510
Short name T157
Test name
Test status
Simulation time 630175485643 ps
CPU time 370.76 seconds
Started Jan 21 09:18:09 PM PST 24
Finished Jan 21 09:24:21 PM PST 24
Peak memory 194700 kb
Host smart-ca3bf0da-e64a-4cca-98d0-70341fe49414
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856723510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2856723510
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.919487281
Short name T325
Test name
Test status
Simulation time 350255558710 ps
CPU time 607.2 seconds
Started Jan 21 09:18:14 PM PST 24
Finished Jan 21 09:28:29 PM PST 24
Peak memory 191356 kb
Host smart-5edf5b73-c3b4-45ed-b31c-16cab5c49e4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919487281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.919487281
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.1862967622
Short name T359
Test name
Test status
Simulation time 172433951267 ps
CPU time 142.84 seconds
Started Jan 21 09:18:14 PM PST 24
Finished Jan 21 09:20:45 PM PST 24
Peak memory 191716 kb
Host smart-aa6c547a-2abe-4528-ad86-d1a854e4ee15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862967622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1862967622
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.4159750804
Short name T217
Test name
Test status
Simulation time 121800282912 ps
CPU time 203.52 seconds
Started Jan 21 09:18:10 PM PST 24
Finished Jan 21 09:21:36 PM PST 24
Peak memory 191592 kb
Host smart-e84bbdff-0470-4d61-bac9-e63d527dad0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159750804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.4159750804
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3784940551
Short name T558
Test name
Test status
Simulation time 92694043562 ps
CPU time 956.64 seconds
Started Jan 21 09:18:10 PM PST 24
Finished Jan 21 09:34:09 PM PST 24
Peak memory 183452 kb
Host smart-7b4f6d28-9c32-422b-91b0-70cd2e831c1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784940551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3784940551
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.1514086757
Short name T192
Test name
Test status
Simulation time 123556591813 ps
CPU time 1349.55 seconds
Started Jan 21 09:18:09 PM PST 24
Finished Jan 21 09:40:40 PM PST 24
Peak memory 194168 kb
Host smart-174657d8-f05c-412d-9ba5-3def33d031ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514086757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1514086757
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1257288707
Short name T295
Test name
Test status
Simulation time 4845208212893 ps
CPU time 1109.56 seconds
Started Jan 21 09:12:25 PM PST 24
Finished Jan 21 09:31:03 PM PST 24
Peak memory 183404 kb
Host smart-f159cb57-0d58-4d03-b93f-2b471b99ea9e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257288707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1257288707
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.385505722
Short name T493
Test name
Test status
Simulation time 221398553504 ps
CPU time 97.27 seconds
Started Jan 21 09:12:25 PM PST 24
Finished Jan 21 09:14:10 PM PST 24
Peak memory 183452 kb
Host smart-0271a371-39e1-4378-85e8-b9b3719f4f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385505722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.385505722
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3972205182
Short name T9
Test name
Test status
Simulation time 135411598447 ps
CPU time 501.82 seconds
Started Jan 21 09:12:21 PM PST 24
Finished Jan 21 09:20:48 PM PST 24
Peak memory 191696 kb
Host smart-19d79f17-ef02-4bea-a438-dfe44fd85cb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972205182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3972205182
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.2661537266
Short name T7
Test name
Test status
Simulation time 165290898211 ps
CPU time 131.17 seconds
Started Jan 21 09:12:24 PM PST 24
Finished Jan 21 09:14:43 PM PST 24
Peak memory 183408 kb
Host smart-38d85e28-258f-437f-9aa2-88e43231806b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661537266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2661537266
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.1767039975
Short name T274
Test name
Test status
Simulation time 48369225993 ps
CPU time 359.88 seconds
Started Jan 21 09:12:25 PM PST 24
Finished Jan 21 09:18:32 PM PST 24
Peak memory 206320 kb
Host smart-bbfdcd21-2520-4c9b-9738-cb461cece7d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767039975 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.1767039975
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.rv_timer_random.1856966311
Short name T237
Test name
Test status
Simulation time 565236706866 ps
CPU time 180.51 seconds
Started Jan 21 09:18:11 PM PST 24
Finished Jan 21 09:21:13 PM PST 24
Peak memory 191652 kb
Host smart-b99e2827-9d8c-4000-8fe2-93738037a8e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856966311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1856966311
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.407696581
Short name T181
Test name
Test status
Simulation time 874206744748 ps
CPU time 1888.24 seconds
Started Jan 21 09:49:37 PM PST 24
Finished Jan 21 10:21:07 PM PST 24
Peak memory 191692 kb
Host smart-35cf1a4e-5ba0-48c1-8dd6-e19e170aef96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407696581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.407696581
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3051305917
Short name T262
Test name
Test status
Simulation time 444023094231 ps
CPU time 785.2 seconds
Started Jan 21 09:18:17 PM PST 24
Finished Jan 21 09:31:29 PM PST 24
Peak memory 191692 kb
Host smart-5bd46e96-49b0-4b5e-83a1-297a100bef75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051305917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3051305917
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.608560030
Short name T616
Test name
Test status
Simulation time 70474980625 ps
CPU time 40.63 seconds
Started Jan 21 09:18:18 PM PST 24
Finished Jan 21 09:19:05 PM PST 24
Peak memory 191736 kb
Host smart-6777a563-73dc-43a0-a468-c692ce9ebbcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608560030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.608560030
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.4135541770
Short name T102
Test name
Test status
Simulation time 554944426842 ps
CPU time 226.38 seconds
Started Jan 21 09:18:17 PM PST 24
Finished Jan 21 09:22:10 PM PST 24
Peak memory 191620 kb
Host smart-495ddac7-88aa-4e10-87f2-c4a4ea032ce5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135541770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.4135541770
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3504916320
Short name T336
Test name
Test status
Simulation time 184946999240 ps
CPU time 440.2 seconds
Started Jan 21 09:18:17 PM PST 24
Finished Jan 21 09:25:44 PM PST 24
Peak memory 191680 kb
Host smart-312c96f7-1ee7-448d-a675-174fa4c68dbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504916320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3504916320
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.1005652270
Short name T282
Test name
Test status
Simulation time 139968207017 ps
CPU time 139.17 seconds
Started Jan 21 09:18:20 PM PST 24
Finished Jan 21 09:20:44 PM PST 24
Peak memory 191676 kb
Host smart-85fecc32-5987-4a08-bb0c-608b185acc3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005652270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1005652270
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.763942747
Short name T292
Test name
Test status
Simulation time 84770406878 ps
CPU time 30.46 seconds
Started Jan 21 09:18:17 PM PST 24
Finished Jan 21 09:18:55 PM PST 24
Peak memory 183276 kb
Host smart-fb68035c-97d2-4174-9a3a-6c97ba8e37b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763942747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.763942747
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.3580151138
Short name T205
Test name
Test status
Simulation time 120943487633 ps
CPU time 257.7 seconds
Started Jan 21 09:18:17 PM PST 24
Finished Jan 21 09:22:42 PM PST 24
Peak memory 191604 kb
Host smart-4889dafa-e246-41ad-83f7-bedee29e3509
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580151138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3580151138
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.1268975853
Short name T245
Test name
Test status
Simulation time 82519697975 ps
CPU time 144.34 seconds
Started Jan 21 09:12:32 PM PST 24
Finished Jan 21 09:15:02 PM PST 24
Peak memory 183448 kb
Host smart-fab9edb2-f76e-4bfe-bec5-ef207b1de012
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268975853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.1268975853
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.4090247931
Short name T550
Test name
Test status
Simulation time 372552857897 ps
CPU time 151.73 seconds
Started Jan 21 09:12:30 PM PST 24
Finished Jan 21 09:15:09 PM PST 24
Peak memory 183448 kb
Host smart-5cd913bd-254e-4915-87ff-7c85407fc7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090247931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.4090247931
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.3755398982
Short name T103
Test name
Test status
Simulation time 704928771996 ps
CPU time 522.37 seconds
Started Jan 21 09:12:30 PM PST 24
Finished Jan 21 09:21:19 PM PST 24
Peak memory 191656 kb
Host smart-299c3d1c-ddba-419c-ba94-56d2ee6fe7cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755398982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3755398982
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.318761876
Short name T323
Test name
Test status
Simulation time 179992852743 ps
CPU time 80.48 seconds
Started Jan 21 09:12:28 PM PST 24
Finished Jan 21 09:13:57 PM PST 24
Peak memory 194092 kb
Host smart-846a3a06-1f95-4fb4-8e28-2e85da9da2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318761876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.318761876
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.2977907004
Short name T97
Test name
Test status
Simulation time 1347420721523 ps
CPU time 787.58 seconds
Started Jan 21 09:12:29 PM PST 24
Finished Jan 21 09:25:45 PM PST 24
Peak memory 191788 kb
Host smart-d9d4c38b-deaa-4c8f-9b36-e8b704e1b30f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977907004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
2977907004
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.4112207878
Short name T278
Test name
Test status
Simulation time 375553669413 ps
CPU time 1020.43 seconds
Started Jan 21 09:12:36 PM PST 24
Finished Jan 21 09:29:45 PM PST 24
Peak memory 212604 kb
Host smart-96ed7622-5186-4172-bb80-23326b458a2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112207878 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.4112207878
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.1138470096
Short name T254
Test name
Test status
Simulation time 81341371017 ps
CPU time 178.22 seconds
Started Jan 21 09:18:18 PM PST 24
Finished Jan 21 09:21:22 PM PST 24
Peak memory 191696 kb
Host smart-7f7e665e-a34a-47a2-9f03-32a14fd65588
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138470096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1138470096
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.2812066123
Short name T151
Test name
Test status
Simulation time 69034550481 ps
CPU time 467.62 seconds
Started Jan 21 09:18:17 PM PST 24
Finished Jan 21 09:26:12 PM PST 24
Peak memory 194580 kb
Host smart-85a43158-8619-404d-9bb4-591dd5378dde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812066123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2812066123
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.4056399233
Short name T186
Test name
Test status
Simulation time 133429149361 ps
CPU time 38.6 seconds
Started Jan 21 10:14:35 PM PST 24
Finished Jan 21 10:15:15 PM PST 24
Peak memory 195200 kb
Host smart-1c376a0c-63dd-42de-b40c-d44c684fb3d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056399233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.4056399233
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.1570676675
Short name T94
Test name
Test status
Simulation time 131866877297 ps
CPU time 339.1 seconds
Started Jan 21 10:09:34 PM PST 24
Finished Jan 21 10:15:14 PM PST 24
Peak memory 191652 kb
Host smart-de95a241-e821-4f7b-9d65-a4aa90e88afd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570676675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1570676675
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1065446207
Short name T351
Test name
Test status
Simulation time 29890039152 ps
CPU time 47.15 seconds
Started Jan 21 09:18:26 PM PST 24
Finished Jan 21 09:19:20 PM PST 24
Peak memory 183496 kb
Host smart-8894ac51-3db6-4adf-adca-ba804a5cb98f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065446207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1065446207
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.2859789135
Short name T290
Test name
Test status
Simulation time 172402907671 ps
CPU time 157.27 seconds
Started Jan 21 09:18:27 PM PST 24
Finished Jan 21 09:21:11 PM PST 24
Peak memory 191708 kb
Host smart-f370a4ef-c1b9-47cc-afe8-b4919e86e9f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859789135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.2859789135
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3805096284
Short name T1
Test name
Test status
Simulation time 349723448789 ps
CPU time 180.94 seconds
Started Jan 21 09:55:11 PM PST 24
Finished Jan 21 09:58:20 PM PST 24
Peak memory 191708 kb
Host smart-37860864-e7d0-42b0-9384-4b7b78ebfe2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805096284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3805096284
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2662007327
Short name T348
Test name
Test status
Simulation time 118577157460 ps
CPU time 220.04 seconds
Started Jan 21 09:18:27 PM PST 24
Finished Jan 21 09:22:14 PM PST 24
Peak memory 191668 kb
Host smart-61c7e701-a50d-4cd7-b7ff-53ac3a81fa88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662007327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2662007327
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1164695738
Short name T6
Test name
Test status
Simulation time 667343977987 ps
CPU time 309.1 seconds
Started Jan 21 09:18:28 PM PST 24
Finished Jan 21 09:23:43 PM PST 24
Peak memory 195116 kb
Host smart-a849d7cf-720a-4731-a273-9ac6e44036bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164695738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1164695738
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.665834460
Short name T549
Test name
Test status
Simulation time 50573427879 ps
CPU time 30.14 seconds
Started Jan 21 09:50:39 PM PST 24
Finished Jan 21 09:51:14 PM PST 24
Peak memory 183444 kb
Host smart-3269471b-19ce-4e4c-8be1-72c1a066c1e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665834460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.665834460
Directory /workspace/99.rv_timer_random/latest
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