Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.36 98.73 100.00 100.00 100.00 99.77


Total test records in report: 615
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T555 /workspace/coverage/default/25.rv_timer_random_reset.2710574194 Jan 25 04:02:28 AM PST 24 Jan 25 04:02:35 AM PST 24 3357342004 ps
T556 /workspace/coverage/default/27.rv_timer_disabled.2476290494 Jan 25 04:02:50 AM PST 24 Jan 25 04:03:29 AM PST 24 72106266010 ps
T557 /workspace/coverage/default/1.rv_timer_random.2480734859 Jan 25 03:55:24 AM PST 24 Jan 25 03:55:33 AM PST 24 592625304 ps
T558 /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3311731339 Jan 25 03:59:01 AM PST 24 Jan 25 04:03:03 AM PST 24 135579544754 ps
T559 /workspace/coverage/default/6.rv_timer_disabled.1391435198 Jan 25 03:56:32 AM PST 24 Jan 25 04:00:36 AM PST 24 584957110813 ps
T560 /workspace/coverage/default/35.rv_timer_disabled.3340709323 Jan 25 04:04:23 AM PST 24 Jan 25 04:05:06 AM PST 24 112157019567 ps
T561 /workspace/coverage/default/37.rv_timer_random_reset.3851944150 Jan 25 04:05:19 AM PST 24 Jan 25 04:05:24 AM PST 24 1366219763 ps
T279 /workspace/coverage/default/18.rv_timer_random.453314483 Jan 25 03:59:34 AM PST 24 Jan 25 04:20:26 AM PST 24 146022672138 ps
T303 /workspace/coverage/default/197.rv_timer_random.4160036076 Jan 25 04:14:41 AM PST 24 Jan 25 04:18:11 AM PST 24 377966081214 ps
T366 /workspace/coverage/default/199.rv_timer_random.1334253910 Jan 25 04:14:40 AM PST 24 Jan 25 04:18:27 AM PST 24 107983503790 ps
T562 /workspace/coverage/default/129.rv_timer_random.1385889261 Jan 25 04:12:10 AM PST 24 Jan 25 04:12:41 AM PST 24 47070686101 ps
T333 /workspace/coverage/default/51.rv_timer_random.1301297817 Jan 25 04:29:12 AM PST 24 Jan 25 04:36:47 AM PST 24 188581358103 ps
T324 /workspace/coverage/default/15.rv_timer_random_reset.3249697663 Jan 25 05:18:51 AM PST 24 Jan 25 05:25:04 AM PST 24 103342142237 ps
T563 /workspace/coverage/default/32.rv_timer_disabled.2220996328 Jan 25 04:03:47 AM PST 24 Jan 25 04:05:59 AM PST 24 92364268179 ps
T272 /workspace/coverage/default/39.rv_timer_stress_all.4143197849 Jan 25 04:06:02 AM PST 24 Jan 25 04:35:50 AM PST 24 2703908646548 ps
T343 /workspace/coverage/default/4.rv_timer_random_reset.1875328727 Jan 25 03:56:29 AM PST 24 Jan 25 03:58:21 AM PST 24 121274564631 ps
T228 /workspace/coverage/default/49.rv_timer_stress_all.1097456262 Jan 25 07:39:47 AM PST 24 Jan 25 07:51:07 AM PST 24 844984675991 ps
T229 /workspace/coverage/default/130.rv_timer_random.3668996822 Jan 25 04:12:11 AM PST 24 Jan 25 04:22:34 AM PST 24 107327700823 ps
T564 /workspace/coverage/default/21.rv_timer_disabled.1397477785 Jan 25 04:00:55 AM PST 24 Jan 25 04:03:48 AM PST 24 471642809659 ps
T565 /workspace/coverage/default/2.rv_timer_random_reset.607134765 Jan 25 03:55:51 AM PST 24 Jan 25 03:55:54 AM PST 24 316580562 ps
T348 /workspace/coverage/default/109.rv_timer_random.1547724204 Jan 25 04:10:59 AM PST 24 Jan 25 04:15:59 AM PST 24 297742446279 ps
T273 /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.264847869 Jan 25 04:00:56 AM PST 24 Jan 25 04:02:54 AM PST 24 199408060093 ps
T219 /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.1712423263 Jan 25 03:58:53 AM PST 24 Jan 25 04:05:38 AM PST 24 416611610299 ps
T157 /workspace/coverage/default/104.rv_timer_random.2438941620 Jan 25 04:10:59 AM PST 24 Jan 25 04:49:11 AM PST 24 166717110335 ps
T566 /workspace/coverage/default/9.rv_timer_disabled.3115289253 Jan 25 03:58:49 AM PST 24 Jan 25 04:01:47 AM PST 24 121118031315 ps
T567 /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.2390989500 Jan 25 03:56:36 AM PST 24 Jan 25 04:12:02 AM PST 24 243805757048 ps
T568 /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.607085188 Jan 25 03:59:18 AM PST 24 Jan 25 04:19:20 AM PST 24 2180879444550 ps
T569 /workspace/coverage/default/127.rv_timer_random.4007898823 Jan 25 04:11:52 AM PST 24 Jan 25 04:21:49 AM PST 24 409380746012 ps
T361 /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1317932804 Jan 25 04:03:28 AM PST 24 Jan 25 04:12:02 AM PST 24 1270590520156 ps
T354 /workspace/coverage/default/186.rv_timer_random.878628778 Jan 25 04:14:23 AM PST 24 Jan 25 04:15:55 AM PST 24 52963557261 ps
T570 /workspace/coverage/default/27.rv_timer_random_reset.1120034901 Jan 25 04:02:50 AM PST 24 Jan 25 04:02:54 AM PST 24 112837930 ps
T220 /workspace/coverage/default/121.rv_timer_random.2871466323 Jan 25 04:26:26 AM PST 24 Jan 25 04:30:35 AM PST 24 259539055091 ps
T277 /workspace/coverage/default/58.rv_timer_random.2182157969 Jan 25 05:28:06 AM PST 24 Jan 25 05:31:59 AM PST 24 128879035195 ps
T571 /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.4057778069 Jan 25 04:03:27 AM PST 24 Jan 25 04:08:21 AM PST 24 37992234907 ps
T164 /workspace/coverage/default/10.rv_timer_stress_all.1412761416 Jan 25 06:19:04 AM PST 24 Jan 25 06:19:35 AM PST 24 20273328632 ps
T572 /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.777905407 Jan 25 04:06:23 AM PST 24 Jan 25 04:09:35 AM PST 24 102848222618 ps
T573 /workspace/coverage/default/72.rv_timer_random.3201807714 Jan 25 06:55:13 AM PST 24 Jan 25 06:55:22 AM PST 24 23279586284 ps
T574 /workspace/coverage/default/63.rv_timer_random.4244220458 Jan 25 04:09:38 AM PST 24 Jan 25 04:10:00 AM PST 24 13878332450 ps
T290 /workspace/coverage/default/0.rv_timer_random.235492339 Jan 25 03:55:21 AM PST 24 Jan 25 03:57:15 AM PST 24 216585773782 ps
T347 /workspace/coverage/default/36.rv_timer_random.3261295249 Jan 25 04:04:50 AM PST 24 Jan 25 04:05:29 AM PST 24 16905900473 ps
T575 /workspace/coverage/default/74.rv_timer_random.876087912 Jan 25 04:09:57 AM PST 24 Jan 25 04:12:13 AM PST 24 118783457641 ps
T86 /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.3257579830 Jan 25 04:06:06 AM PST 24 Jan 25 04:30:08 AM PST 24 1426586017902 ps
T175 /workspace/coverage/default/159.rv_timer_random.1464047178 Jan 25 04:13:25 AM PST 24 Jan 25 04:14:39 AM PST 24 41242900062 ps
T576 /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.4222575893 Jan 25 04:02:27 AM PST 24 Jan 25 04:13:10 AM PST 24 825212774391 ps
T236 /workspace/coverage/default/105.rv_timer_random.4212539511 Jan 25 04:11:01 AM PST 24 Jan 25 04:16:44 AM PST 24 503044971256 ps
T577 /workspace/coverage/default/131.rv_timer_random.668476248 Jan 25 04:12:14 AM PST 24 Jan 25 04:18:36 AM PST 24 60679332787 ps
T578 /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1075914270 Jan 25 04:05:18 AM PST 24 Jan 25 04:13:04 AM PST 24 287558713870 ps
T579 /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.2137682042 Jan 25 05:18:54 AM PST 24 Jan 25 05:41:37 AM PST 24 580596407888 ps
T223 /workspace/coverage/default/152.rv_timer_random.1263787929 Jan 25 04:12:38 AM PST 24 Jan 25 04:27:25 AM PST 24 231378836620 ps
T580 /workspace/coverage/default/19.rv_timer_disabled.2699725248 Jan 25 03:59:40 AM PST 24 Jan 25 04:00:21 AM PST 24 23620915923 ps
T182 /workspace/coverage/default/141.rv_timer_random.1713727908 Jan 25 04:12:25 AM PST 24 Jan 25 04:15:47 AM PST 24 349610498245 ps
T581 /workspace/coverage/default/98.rv_timer_random.1870246608 Jan 25 04:10:34 AM PST 24 Jan 25 04:11:56 AM PST 24 46125131884 ps
T350 /workspace/coverage/default/73.rv_timer_random.4130494247 Jan 25 05:31:30 AM PST 24 Jan 25 05:51:14 AM PST 24 362682910355 ps
T582 /workspace/coverage/default/103.rv_timer_random.2260882471 Jan 25 04:48:29 AM PST 24 Jan 25 04:49:09 AM PST 24 21970917282 ps
T250 /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2582922269 Jan 25 04:04:48 AM PST 24 Jan 25 04:12:37 AM PST 24 825225501353 ps
T583 /workspace/coverage/default/95.rv_timer_random.1752681404 Jan 25 04:10:29 AM PST 24 Jan 25 04:13:56 AM PST 24 273718823585 ps
T284 /workspace/coverage/default/9.rv_timer_stress_all.1082418875 Jan 25 03:58:46 AM PST 24 Jan 25 04:14:36 AM PST 24 1458308683925 ps
T584 /workspace/coverage/default/146.rv_timer_random.3975107571 Jan 25 04:12:22 AM PST 24 Jan 25 04:12:45 AM PST 24 41503524818 ps
T224 /workspace/coverage/default/108.rv_timer_random.1127504840 Jan 25 04:11:01 AM PST 24 Jan 25 04:20:19 AM PST 24 824033654417 ps
T374 /workspace/coverage/default/99.rv_timer_random.881879073 Jan 25 04:10:42 AM PST 24 Jan 25 04:13:30 AM PST 24 575422341536 ps
T585 /workspace/coverage/default/18.rv_timer_disabled.3907346945 Jan 25 03:59:35 AM PST 24 Jan 25 04:03:01 AM PST 24 485648986015 ps
T586 /workspace/coverage/default/5.rv_timer_disabled.1614080922 Jan 25 03:56:24 AM PST 24 Jan 25 04:00:19 AM PST 24 284912540123 ps
T171 /workspace/coverage/default/39.rv_timer_random.631256114 Jan 25 04:06:04 AM PST 24 Jan 25 04:08:02 AM PST 24 150243449382 ps
T587 /workspace/coverage/default/139.rv_timer_random.460831763 Jan 25 04:12:20 AM PST 24 Jan 25 04:40:58 AM PST 24 353073256996 ps
T588 /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.252604536 Jan 25 04:01:45 AM PST 24 Jan 25 04:06:25 AM PST 24 146676732199 ps
T589 /workspace/coverage/default/49.rv_timer_random_reset.459955041 Jan 25 04:08:16 AM PST 24 Jan 25 04:08:29 AM PST 24 103472245 ps
T590 /workspace/coverage/default/27.rv_timer_stress_all.1652505521 Jan 25 04:02:52 AM PST 24 Jan 25 04:16:20 AM PST 24 522637403613 ps
T375 /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3413014676 Jan 25 04:08:13 AM PST 24 Jan 25 04:14:23 AM PST 24 220179712527 ps
T221 /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1995549361 Jan 25 03:59:29 AM PST 24 Jan 25 04:06:12 AM PST 24 243363709323 ps
T263 /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2745058941 Jan 25 03:58:47 AM PST 24 Jan 25 04:03:36 AM PST 24 447772447842 ps
T591 /workspace/coverage/default/0.rv_timer_random_reset.562066939 Jan 25 03:55:21 AM PST 24 Jan 25 03:57:06 AM PST 24 214360597378 ps
T592 /workspace/coverage/default/6.rv_timer_random_reset.4238575172 Jan 25 03:56:33 AM PST 24 Jan 25 03:56:37 AM PST 24 1513568413 ps
T160 /workspace/coverage/default/11.rv_timer_stress_all.1429464103 Jan 25 03:59:00 AM PST 24 Jan 25 04:10:39 AM PST 24 291647887616 ps
T593 /workspace/coverage/default/36.rv_timer_random_reset.3833727194 Jan 25 04:04:49 AM PST 24 Jan 25 04:04:57 AM PST 24 74816088 ps
T19 /workspace/coverage/default/3.rv_timer_sec_cm.2441626300 Jan 25 03:55:50 AM PST 24 Jan 25 03:55:52 AM PST 24 109240105 ps
T146 /workspace/coverage/default/138.rv_timer_random.4089074674 Jan 25 04:12:24 AM PST 24 Jan 25 04:23:04 AM PST 24 161670319481 ps
T594 /workspace/coverage/default/14.rv_timer_disabled.4143358548 Jan 25 03:59:18 AM PST 24 Jan 25 04:02:28 AM PST 24 207323956696 ps
T275 /workspace/coverage/default/172.rv_timer_random.328381005 Jan 25 04:13:37 AM PST 24 Jan 25 04:30:18 AM PST 24 457878548336 ps
T268 /workspace/coverage/default/82.rv_timer_random.2711706135 Jan 25 04:10:13 AM PST 24 Jan 25 04:15:09 AM PST 24 257554454565 ps
T595 /workspace/coverage/default/10.rv_timer_disabled.3917292024 Jan 25 03:58:50 AM PST 24 Jan 25 04:00:17 AM PST 24 56131091472 ps
T596 /workspace/coverage/default/113.rv_timer_random.1036040166 Jan 25 04:11:10 AM PST 24 Jan 25 04:12:16 AM PST 24 20803302358 ps
T356 /workspace/coverage/default/44.rv_timer_random_reset.3737935864 Jan 25 04:07:11 AM PST 24 Jan 25 04:09:01 AM PST 24 192986843667 ps
T597 /workspace/coverage/default/28.rv_timer_random_reset.2544583429 Jan 25 04:02:51 AM PST 24 Jan 25 04:06:36 AM PST 24 127030083535 ps
T598 /workspace/coverage/default/9.rv_timer_random_reset.2911504014 Jan 25 03:58:53 AM PST 24 Jan 25 04:00:18 AM PST 24 189267567719 ps
T599 /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.2627072635 Jan 25 03:56:32 AM PST 24 Jan 25 04:09:17 AM PST 24 427592903136 ps
T297 /workspace/coverage/default/67.rv_timer_random.3790167204 Jan 25 05:41:28 AM PST 24 Jan 25 05:52:11 AM PST 24 1246418057587 ps
T285 /workspace/coverage/default/27.rv_timer_random.1128044929 Jan 25 04:02:53 AM PST 24 Jan 25 04:04:05 AM PST 24 40997769047 ps
T600 /workspace/coverage/default/36.rv_timer_disabled.1459747595 Jan 25 04:04:53 AM PST 24 Jan 25 04:06:36 AM PST 24 68836668998 ps
T161 /workspace/coverage/default/17.rv_timer_stress_all.2470213426 Jan 25 03:59:32 AM PST 24 Jan 25 04:31:34 AM PST 24 446952909759 ps
T262 /workspace/coverage/default/122.rv_timer_random.1717837582 Jan 25 04:11:59 AM PST 24 Jan 25 04:21:10 AM PST 24 313753912025 ps
T601 /workspace/coverage/default/89.rv_timer_random.236396777 Jan 25 04:10:11 AM PST 24 Jan 25 04:24:26 AM PST 24 129550631707 ps
T300 /workspace/coverage/default/160.rv_timer_random.1747336344 Jan 25 04:13:26 AM PST 24 Jan 25 04:17:57 AM PST 24 283607246385 ps
T602 /workspace/coverage/default/41.rv_timer_disabled.2087780616 Jan 25 04:49:05 AM PST 24 Jan 25 04:52:24 AM PST 24 245112461910 ps
T339 /workspace/coverage/default/5.rv_timer_stress_all.3468491432 Jan 25 03:56:23 AM PST 24 Jan 25 04:10:19 AM PST 24 1823238994747 ps
T603 /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.681677235 Jan 25 03:59:13 AM PST 24 Jan 25 04:16:43 AM PST 24 108938116228 ps
T604 /workspace/coverage/default/4.rv_timer_disabled.413900629 Jan 25 03:56:12 AM PST 24 Jan 25 04:00:27 AM PST 24 161805769633 ps
T605 /workspace/coverage/default/116.rv_timer_random.665868250 Jan 25 04:11:31 AM PST 24 Jan 25 04:12:08 AM PST 24 38890567336 ps
T606 /workspace/coverage/default/76.rv_timer_random.1867678604 Jan 25 06:03:31 AM PST 24 Jan 25 06:05:43 AM PST 24 133872945473 ps
T607 /workspace/coverage/default/25.rv_timer_disabled.3917861317 Jan 25 04:01:54 AM PST 24 Jan 25 04:02:01 AM PST 24 672384430 ps
T255 /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.3039197106 Jan 25 03:59:32 AM PST 24 Jan 25 04:13:58 AM PST 24 181697648202 ps
T308 /workspace/coverage/default/161.rv_timer_random.4263445959 Jan 25 04:13:27 AM PST 24 Jan 25 04:17:18 AM PST 24 390263185342 ps
T608 /workspace/coverage/default/102.rv_timer_random.3956084032 Jan 25 04:10:59 AM PST 24 Jan 25 04:11:20 AM PST 24 22955610792 ps
T316 /workspace/coverage/default/194.rv_timer_random.2820043229 Jan 25 05:08:30 AM PST 24 Jan 25 05:15:15 AM PST 24 442975743573 ps
T326 /workspace/coverage/default/93.rv_timer_random.267179275 Jan 25 04:18:01 AM PST 24 Jan 25 04:20:40 AM PST 24 589123446449 ps
T609 /workspace/coverage/default/1.rv_timer_disabled.3294855399 Jan 25 03:55:22 AM PST 24 Jan 25 03:56:25 AM PST 24 126551838783 ps
T20 /workspace/coverage/default/2.rv_timer_sec_cm.184643551 Jan 25 03:55:52 AM PST 24 Jan 25 03:55:53 AM PST 24 36620368 ps
T610 /workspace/coverage/default/0.rv_timer_stress_all.44630784 Jan 25 03:55:18 AM PST 24 Jan 25 03:55:28 AM PST 24 199060931 ps
T611 /workspace/coverage/default/7.rv_timer_random.907162744 Jan 25 03:56:35 AM PST 24 Jan 25 03:58:04 AM PST 24 178479577804 ps
T612 /workspace/coverage/default/43.rv_timer_disabled.2035580575 Jan 25 04:06:40 AM PST 24 Jan 25 04:09:07 AM PST 24 90459867846 ps
T376 /workspace/coverage/default/100.rv_timer_random.132475168 Jan 25 04:10:44 AM PST 24 Jan 25 04:38:57 AM PST 24 215762203136 ps
T156 /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.594736654 Jan 25 06:36:26 AM PST 24 Jan 25 06:52:36 AM PST 24 221337355759 ps
T613 /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.4264560648 Jan 25 04:05:17 AM PST 24 Jan 25 04:11:12 AM PST 24 38264569579 ps
T614 /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1330807976 Jan 25 04:03:00 AM PST 24 Jan 25 04:17:29 AM PST 24 2677068748891 ps
T615 /workspace/coverage/default/45.rv_timer_disabled.1650641990 Jan 25 04:07:11 AM PST 24 Jan 25 04:09:05 AM PST 24 499603592908 ps
T147 /workspace/coverage/default/112.rv_timer_random.801255075 Jan 25 04:11:09 AM PST 24 Jan 25 04:17:39 AM PST 24 1153219817798 ps

Test location /workspace/coverage/default/31.rv_timer_random.3163187097
Short name T9
Test name
Test status
Simulation time 190492796352 ps
CPU time 172.95 seconds
Started Jan 25 04:31:11 AM PST 24
Finished Jan 25 04:34:14 AM PST 24
Peak memory 191740 kb
Host smart-316bf5f5-5b57-4099-8703-bae7d0d05ac8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163187097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3163187097
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.2739944564
Short name T13
Test name
Test status
Simulation time 61355415879 ps
CPU time 128.08 seconds
Started Jan 25 04:03:45 AM PST 24
Finished Jan 25 04:05:56 AM PST 24
Peak memory 206360 kb
Host smart-530b27df-b77d-4474-9669-8e47510f680c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739944564 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.2739944564
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2391376856
Short name T56
Test name
Test status
Simulation time 1045005288916 ps
CPU time 4565.99 seconds
Started Jan 25 04:04:01 AM PST 24
Finished Jan 25 05:20:09 AM PST 24
Peak memory 191712 kb
Host smart-8a503560-8e10-4b76-b178-04d3b85260d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391376856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2391376856
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.493069353
Short name T29
Test name
Test status
Simulation time 76061728 ps
CPU time 1.12 seconds
Started Jan 24 11:10:32 PM PST 24
Finished Jan 24 11:10:34 PM PST 24
Peak memory 195224 kb
Host smart-a47c53e6-67e9-41a2-af36-7c875e3bb00f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493069353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in
tg_err.493069353
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3443826539
Short name T131
Test name
Test status
Simulation time 2868846842305 ps
CPU time 2796.77 seconds
Started Jan 25 04:05:16 AM PST 24
Finished Jan 25 04:51:59 AM PST 24
Peak memory 191704 kb
Host smart-d3fa7ad5-aa28-41f1-9c88-b65da6a4851b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443826539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3443826539
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2571750839
Short name T49
Test name
Test status
Simulation time 436954512623 ps
CPU time 1494.77 seconds
Started Jan 25 04:00:54 AM PST 24
Finished Jan 25 04:25:49 AM PST 24
Peak memory 191660 kb
Host smart-e7d7a839-8279-4fc1-b044-579830a7627e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571750839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2571750839
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.592803748
Short name T185
Test name
Test status
Simulation time 2099126632139 ps
CPU time 2486.61 seconds
Started Jan 25 04:00:42 AM PST 24
Finished Jan 25 04:42:10 AM PST 24
Peak memory 191676 kb
Host smart-d52c3c49-1711-4f6a-abae-72917c7951d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592803748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.
592803748
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1769614258
Short name T7
Test name
Test status
Simulation time 337537331540 ps
CPU time 609.13 seconds
Started Jan 25 04:02:48 AM PST 24
Finished Jan 25 04:13:01 AM PST 24
Peak memory 191660 kb
Host smart-ea7830ed-1b76-401d-ad30-dc92d8811322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769614258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1769614258
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.391743064
Short name T121
Test name
Test status
Simulation time 1451986101658 ps
CPU time 1711.43 seconds
Started Jan 25 06:04:18 AM PST 24
Finished Jan 25 06:32:51 AM PST 24
Peak memory 191880 kb
Host smart-62a27ddf-9bdf-4d4a-8dd4-284d81733ca6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391743064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.
391743064
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.1429464103
Short name T160
Test name
Test status
Simulation time 291647887616 ps
CPU time 695.96 seconds
Started Jan 25 03:59:00 AM PST 24
Finished Jan 25 04:10:39 AM PST 24
Peak memory 195708 kb
Host smart-5ff678c1-c259-4ea4-a755-dbf3cde9b630
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429464103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1429464103
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.3171530085
Short name T34
Test name
Test status
Simulation time 207987799968 ps
CPU time 570.54 seconds
Started Jan 25 05:05:13 AM PST 24
Finished Jan 25 05:14:45 AM PST 24
Peak memory 206372 kb
Host smart-aab57a69-d41c-43bc-933b-6cb81ab37c46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171530085 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.3171530085
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.3648660928
Short name T122
Test name
Test status
Simulation time 445300820114 ps
CPU time 768.18 seconds
Started Jan 25 03:59:18 AM PST 24
Finished Jan 25 04:12:09 AM PST 24
Peak memory 191704 kb
Host smart-e27e47c6-c91f-47b3-9f71-fb80ccd077b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648660928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.3648660928
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1876274467
Short name T233
Test name
Test status
Simulation time 3121398271885 ps
CPU time 1065.06 seconds
Started Jan 25 04:06:07 AM PST 24
Finished Jan 25 04:23:53 AM PST 24
Peak memory 191688 kb
Host smart-3517cf8e-b2dd-452b-9206-fe1f50d86974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876274467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1876274467
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.4008557653
Short name T257
Test name
Test status
Simulation time 420710965156 ps
CPU time 804.45 seconds
Started Jan 25 04:01:16 AM PST 24
Finished Jan 25 04:14:41 AM PST 24
Peak memory 191672 kb
Host smart-a23ebb06-5197-48a0-9d17-8b0b2472eb0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008557653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.4008557653
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.374058076
Short name T166
Test name
Test status
Simulation time 706212615390 ps
CPU time 1617.57 seconds
Started Jan 25 04:03:42 AM PST 24
Finished Jan 25 04:30:41 AM PST 24
Peak memory 191732 kb
Host smart-c5a8ba44-476f-434d-b2d2-3c41e08ba0a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374058076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.
374058076
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.3086167934
Short name T18
Test name
Test status
Simulation time 531566474 ps
CPU time 0.78 seconds
Started Jan 25 03:55:23 AM PST 24
Finished Jan 25 03:55:29 AM PST 24
Peak memory 213548 kb
Host smart-8d295a61-17e6-4650-aa55-cbc20f48b89c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086167934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.3086167934
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3468491432
Short name T339
Test name
Test status
Simulation time 1823238994747 ps
CPU time 829.69 seconds
Started Jan 25 03:56:23 AM PST 24
Finished Jan 25 04:10:19 AM PST 24
Peak memory 191652 kb
Host smart-e0751359-2c9a-4dfe-acce-9deb10895a02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468491432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3468491432
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/132.rv_timer_random.4150816477
Short name T118
Test name
Test status
Simulation time 270237269167 ps
CPU time 215.19 seconds
Started Jan 25 04:12:14 AM PST 24
Finished Jan 25 04:15:58 AM PST 24
Peak memory 194980 kb
Host smart-3d70cf2b-8f6d-4ac7-9413-2d240708884d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150816477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.4150816477
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.328381005
Short name T275
Test name
Test status
Simulation time 457878548336 ps
CPU time 997.52 seconds
Started Jan 25 04:13:37 AM PST 24
Finished Jan 25 04:30:18 AM PST 24
Peak memory 191696 kb
Host smart-28cd3860-1963-4bcc-88b6-410573114f11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328381005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.328381005
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.4081798727
Short name T222
Test name
Test status
Simulation time 1331601915950 ps
CPU time 1283.96 seconds
Started Jan 25 03:56:45 AM PST 24
Finished Jan 25 04:18:10 AM PST 24
Peak memory 196012 kb
Host smart-fae77741-b95a-4989-affa-11902b851322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081798727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
4081798727
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/179.rv_timer_random.3046091557
Short name T111
Test name
Test status
Simulation time 159508430918 ps
CPU time 765.05 seconds
Started Jan 25 04:36:31 AM PST 24
Finished Jan 25 04:49:46 AM PST 24
Peak memory 195088 kb
Host smart-6fa09f87-6e21-4382-bbc9-89451e990ef1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046091557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3046091557
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random.3803505126
Short name T104
Test name
Test status
Simulation time 205972539961 ps
CPU time 398.2 seconds
Started Jan 25 05:10:47 AM PST 24
Finished Jan 25 05:17:33 AM PST 24
Peak memory 191808 kb
Host smart-702e9e0d-a1c2-4696-9b6e-cdb2c8106a3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803505126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3803505126
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.4143197849
Short name T272
Test name
Test status
Simulation time 2703908646548 ps
CPU time 1787.52 seconds
Started Jan 25 04:06:02 AM PST 24
Finished Jan 25 04:35:50 AM PST 24
Peak memory 191660 kb
Host smart-b5d43c98-8fb5-47ab-af77-de0f88410833
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143197849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.4143197849
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2470213426
Short name T161
Test name
Test status
Simulation time 446952909759 ps
CPU time 1916.03 seconds
Started Jan 25 03:59:32 AM PST 24
Finished Jan 25 04:31:34 AM PST 24
Peak memory 191668 kb
Host smart-3799679b-a967-49bc-835d-a085f6ad5ee0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470213426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2470213426
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_random.2062234864
Short name T102
Test name
Test status
Simulation time 1442590666715 ps
CPU time 1260.88 seconds
Started Jan 25 04:06:24 AM PST 24
Finished Jan 25 04:27:26 AM PST 24
Peak memory 191724 kb
Host smart-528cabdb-4daa-43cc-9337-9373e9d12969
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062234864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2062234864
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random.357333818
Short name T190
Test name
Test status
Simulation time 123597033807 ps
CPU time 205.1 seconds
Started Jan 25 05:27:58 AM PST 24
Finished Jan 25 05:31:24 AM PST 24
Peak memory 191808 kb
Host smart-dd885db9-b007-4c64-95ae-ee55907cbce8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357333818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.357333818
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3889441311
Short name T149
Test name
Test status
Simulation time 136850201417 ps
CPU time 384.03 seconds
Started Jan 25 04:46:07 AM PST 24
Finished Jan 25 04:52:33 AM PST 24
Peak memory 191684 kb
Host smart-da21a667-d658-459f-8e54-461fa51d7171
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889441311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3889441311
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/122.rv_timer_random.1717837582
Short name T262
Test name
Test status
Simulation time 313753912025 ps
CPU time 548.61 seconds
Started Jan 25 04:11:59 AM PST 24
Finished Jan 25 04:21:10 AM PST 24
Peak memory 191748 kb
Host smart-cdbc188f-a239-44c8-b7a7-cc90873dccb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717837582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.1717837582
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.88988745
Short name T211
Test name
Test status
Simulation time 632091838024 ps
CPU time 986.42 seconds
Started Jan 25 04:13:01 AM PST 24
Finished Jan 25 04:29:28 AM PST 24
Peak memory 191680 kb
Host smart-1ea7c6a3-988b-4444-8def-f842ff4e533f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88988745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.88988745
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.1334253910
Short name T366
Test name
Test status
Simulation time 107983503790 ps
CPU time 222.4 seconds
Started Jan 25 04:14:40 AM PST 24
Finished Jan 25 04:18:27 AM PST 24
Peak memory 193800 kb
Host smart-cf9a8905-b003-4a43-9504-58fdd5d892f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334253910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.1334253910
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random.131903594
Short name T163
Test name
Test status
Simulation time 444177787366 ps
CPU time 1292.8 seconds
Started Jan 25 04:03:00 AM PST 24
Finished Jan 25 04:24:34 AM PST 24
Peak memory 191748 kb
Host smart-bd7d6d9c-8905-404b-9833-56e9c3b46f58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131903594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.131903594
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random.127201616
Short name T281
Test name
Test status
Simulation time 184115618942 ps
CPU time 285.38 seconds
Started Jan 25 04:06:04 AM PST 24
Finished Jan 25 04:10:50 AM PST 24
Peak memory 191696 kb
Host smart-11f72eca-50af-458a-b08a-47dad64467c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127201616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.127201616
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3565842697
Short name T116
Test name
Test status
Simulation time 451192853700 ps
CPU time 1340.26 seconds
Started Jan 25 04:07:11 AM PST 24
Finished Jan 25 04:29:35 AM PST 24
Peak memory 191668 kb
Host smart-c8ef858d-c625-4d67-9860-71ae14d04f9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565842697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3565842697
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/56.rv_timer_random.2332575180
Short name T112
Test name
Test status
Simulation time 134303836617 ps
CPU time 736.64 seconds
Started Jan 25 05:25:53 AM PST 24
Finished Jan 25 05:38:11 AM PST 24
Peak memory 191808 kb
Host smart-fb0a19ba-8e65-4a5f-8171-a8c097eb87db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332575180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2332575180
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.968434774
Short name T62
Test name
Test status
Simulation time 16103444 ps
CPU time 0.59 seconds
Started Jan 24 11:10:54 PM PST 24
Finished Jan 24 11:10:56 PM PST 24
Peak memory 183112 kb
Host smart-07f99774-74c0-493c-82e6-4f66aceb74d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968434774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.968434774
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/162.rv_timer_random.3577274305
Short name T24
Test name
Test status
Simulation time 164174643642 ps
CPU time 1831.32 seconds
Started Jan 25 04:13:25 AM PST 24
Finished Jan 25 04:43:57 AM PST 24
Peak memory 191660 kb
Host smart-28bf9b7e-02be-473e-b9a7-fbf4c763592e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577274305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3577274305
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random.89285170
Short name T142
Test name
Test status
Simulation time 514223920683 ps
CPU time 1752.07 seconds
Started Jan 25 04:01:41 AM PST 24
Finished Jan 25 04:30:55 AM PST 24
Peak memory 191708 kb
Host smart-8ff26afb-529b-4257-8220-879af7815546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89285170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.89285170
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random.2888941099
Short name T100
Test name
Test status
Simulation time 480585379882 ps
CPU time 1246.66 seconds
Started Jan 25 04:02:27 AM PST 24
Finished Jan 25 04:23:14 AM PST 24
Peak memory 194784 kb
Host smart-10fdb159-1ab2-4043-aab3-7fab64551a54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888941099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2888941099
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random.3143801719
Short name T292
Test name
Test status
Simulation time 167393865513 ps
CPU time 669.17 seconds
Started Jan 25 04:04:25 AM PST 24
Finished Jan 25 04:15:35 AM PST 24
Peak memory 191772 kb
Host smart-c1c968f8-d3d3-46bb-8321-fadedf366ba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143801719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3143801719
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1182554717
Short name T148
Test name
Test status
Simulation time 1448456095471 ps
CPU time 400.62 seconds
Started Jan 25 04:10:13 AM PST 24
Finished Jan 25 04:16:59 AM PST 24
Peak memory 195088 kb
Host smart-ec0844aa-1d3b-4e99-ba0b-bfe6cc43703f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182554717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1182554717
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/90.rv_timer_random.998355438
Short name T207
Test name
Test status
Simulation time 1012116486446 ps
CPU time 994.75 seconds
Started Jan 25 04:10:18 AM PST 24
Finished Jan 25 04:27:03 AM PST 24
Peak memory 191688 kb
Host smart-2d700e9f-c2b8-420e-8131-6798a83157b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998355438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.998355438
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.1882615744
Short name T114
Test name
Test status
Simulation time 785253539584 ps
CPU time 1636.95 seconds
Started Jan 25 04:11:51 AM PST 24
Finished Jan 25 04:39:10 AM PST 24
Peak memory 191688 kb
Host smart-d25fff94-d63d-4ad6-b999-83991c8db024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882615744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1882615744
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.4089074674
Short name T146
Test name
Test status
Simulation time 161670319481 ps
CPU time 636.29 seconds
Started Jan 25 04:12:24 AM PST 24
Finished Jan 25 04:23:04 AM PST 24
Peak memory 191740 kb
Host smart-030ea5e0-15e7-4e91-8495-c5a3f7390435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089074674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.4089074674
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random.4027560762
Short name T179
Test name
Test status
Simulation time 698517771154 ps
CPU time 577.25 seconds
Started Jan 25 03:55:37 AM PST 24
Finished Jan 25 04:05:20 AM PST 24
Peak memory 194540 kb
Host smart-849fc796-1f3b-4376-abbb-45d1def1367c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027560762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.4027560762
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.3961469552
Short name T151
Test name
Test status
Simulation time 200900401878 ps
CPU time 746.11 seconds
Started Jan 25 04:01:58 AM PST 24
Finished Jan 25 04:14:26 AM PST 24
Peak memory 195068 kb
Host smart-5efa6319-04ba-49db-8d32-160d3d14ab39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961469552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.3961469552
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2282045730
Short name T248
Test name
Test status
Simulation time 486336955064 ps
CPU time 391.09 seconds
Started Jan 25 04:03:30 AM PST 24
Finished Jan 25 04:10:01 AM PST 24
Peak memory 183500 kb
Host smart-9d71785c-dec9-410e-89eb-646f228df0f5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282045730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2282045730
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/64.rv_timer_random.723544412
Short name T4
Test name
Test status
Simulation time 200481133913 ps
CPU time 231.49 seconds
Started Jan 25 04:09:36 AM PST 24
Finished Jan 25 04:13:28 AM PST 24
Peak memory 191660 kb
Host smart-733f4687-96f8-4e96-a918-7bcf0cdee018
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723544412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.723544412
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.2711706135
Short name T268
Test name
Test status
Simulation time 257554454565 ps
CPU time 286.76 seconds
Started Jan 25 04:10:13 AM PST 24
Finished Jan 25 04:15:09 AM PST 24
Peak memory 191684 kb
Host smart-66b14cad-94ff-428d-84c4-6191f295694a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711706135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2711706135
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.926478591
Short name T299
Test name
Test status
Simulation time 287288156911 ps
CPU time 558.77 seconds
Started Jan 25 03:55:23 AM PST 24
Finished Jan 25 04:04:47 AM PST 24
Peak memory 183476 kb
Host smart-12e0837e-9f48-470e-89f4-8b59a7646d5e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926478591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rv_timer_cfg_update_on_fly.926478591
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/105.rv_timer_random.4212539511
Short name T236
Test name
Test status
Simulation time 503044971256 ps
CPU time 341.44 seconds
Started Jan 25 04:11:01 AM PST 24
Finished Jan 25 04:16:44 AM PST 24
Peak memory 191672 kb
Host smart-050ce6aa-a397-4190-8168-9011aec82387
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212539511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.4212539511
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3433479961
Short name T288
Test name
Test status
Simulation time 103891325110 ps
CPU time 171.12 seconds
Started Jan 25 04:12:40 AM PST 24
Finished Jan 25 04:15:33 AM PST 24
Peak memory 191740 kb
Host smart-b68a5005-58a4-484e-97c6-df71115d1a4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433479961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3433479961
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.358217355
Short name T107
Test name
Test status
Simulation time 1134047450872 ps
CPU time 1238.64 seconds
Started Jan 25 04:13:39 AM PST 24
Finished Jan 25 04:34:21 AM PST 24
Peak memory 195044 kb
Host smart-dadd2c3c-0efe-4eae-b8b1-785f4b1ada34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358217355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.358217355
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3329511477
Short name T42
Test name
Test status
Simulation time 153951896786 ps
CPU time 234.61 seconds
Started Jan 25 03:59:41 AM PST 24
Finished Jan 25 04:03:40 AM PST 24
Peak memory 183472 kb
Host smart-57cab775-3b38-4e5f-807b-e18e0824cce7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329511477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3329511477
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/189.rv_timer_random.1374653437
Short name T159
Test name
Test status
Simulation time 180395524071 ps
CPU time 852.99 seconds
Started Jan 25 04:45:10 AM PST 24
Finished Jan 25 04:59:27 AM PST 24
Peak memory 191812 kb
Host smart-3b123c48-ceab-4f97-a874-030346979e0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374653437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1374653437
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.3115470341
Short name T188
Test name
Test status
Simulation time 843290888068 ps
CPU time 590.7 seconds
Started Jan 25 05:28:09 AM PST 24
Finished Jan 25 05:38:01 AM PST 24
Peak memory 191840 kb
Host smart-27c61de4-6a47-4605-899f-90c0f0ce34ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115470341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
3115470341
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.264847869
Short name T273
Test name
Test status
Simulation time 199408060093 ps
CPU time 116.47 seconds
Started Jan 25 04:00:56 AM PST 24
Finished Jan 25 04:02:54 AM PST 24
Peak memory 183500 kb
Host smart-e32a9fe8-fd43-4c35-8cb2-af1dcf10d9cf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264847869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.rv_timer_cfg_update_on_fly.264847869
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2582922269
Short name T250
Test name
Test status
Simulation time 825225501353 ps
CPU time 466.46 seconds
Started Jan 25 04:04:48 AM PST 24
Finished Jan 25 04:12:37 AM PST 24
Peak memory 183448 kb
Host smart-138e3b05-8af4-455f-9786-4002ad5f35a6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582922269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2582922269
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/58.rv_timer_random.2182157969
Short name T277
Test name
Test status
Simulation time 128879035195 ps
CPU time 230.73 seconds
Started Jan 25 05:28:06 AM PST 24
Finished Jan 25 05:31:59 AM PST 24
Peak memory 191764 kb
Host smart-88ef2741-a890-401b-b61d-df08e7732093
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182157969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.2182157969
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2895254875
Short name T97
Test name
Test status
Simulation time 80495889 ps
CPU time 0.6 seconds
Started Jan 24 11:09:27 PM PST 24
Finished Jan 24 11:09:28 PM PST 24
Peak memory 191476 kb
Host smart-efcdc655-5174-46d2-8cc3-8ca52f3c5e37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895254875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2895254875
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2169960234
Short name T89
Test name
Test status
Simulation time 458874272 ps
CPU time 1.47 seconds
Started Jan 24 11:06:52 PM PST 24
Finished Jan 24 11:06:57 PM PST 24
Peak memory 183236 kb
Host smart-dd3a8d0e-3469-41cc-950e-f7d2fb6f2153
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169960234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2169960234
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/100.rv_timer_random.132475168
Short name T376
Test name
Test status
Simulation time 215762203136 ps
CPU time 1691.37 seconds
Started Jan 25 04:10:44 AM PST 24
Finished Jan 25 04:38:57 AM PST 24
Peak memory 191708 kb
Host smart-dbc5a733-4cc3-4d42-a4e6-e1befb871fcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132475168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.132475168
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.936626403
Short name T152
Test name
Test status
Simulation time 153912119326 ps
CPU time 134.05 seconds
Started Jan 25 04:10:56 AM PST 24
Finished Jan 25 04:13:11 AM PST 24
Peak memory 191744 kb
Host smart-625aaafc-0c8e-4d67-a48d-aed871f33385
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936626403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.936626403
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.2074010947
Short name T167
Test name
Test status
Simulation time 164506515152 ps
CPU time 275.99 seconds
Started Jan 25 04:10:58 AM PST 24
Finished Jan 25 04:15:35 AM PST 24
Peak memory 191752 kb
Host smart-54a2d059-920b-472a-a081-4b5aa310d316
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074010947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2074010947
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/130.rv_timer_random.3668996822
Short name T229
Test name
Test status
Simulation time 107327700823 ps
CPU time 618.38 seconds
Started Jan 25 04:12:11 AM PST 24
Finished Jan 25 04:22:34 AM PST 24
Peak memory 194544 kb
Host smart-9bda7da7-9c6c-4a90-85ab-7397c39ee7cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668996822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3668996822
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3854952969
Short name T169
Test name
Test status
Simulation time 410841619298 ps
CPU time 413.84 seconds
Started Jan 25 04:33:45 AM PST 24
Finished Jan 25 04:40:45 AM PST 24
Peak memory 191668 kb
Host smart-3933c2f7-9421-404d-b3f6-f10e2ac97a93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854952969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3854952969
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.2798870658
Short name T198
Test name
Test status
Simulation time 21461436101 ps
CPU time 97.04 seconds
Started Jan 25 03:59:24 AM PST 24
Finished Jan 25 04:01:02 AM PST 24
Peak memory 183552 kb
Host smart-3698fcb3-7deb-4575-8ac9-587a1011caed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798870658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2798870658
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.135074353
Short name T141
Test name
Test status
Simulation time 494316927002 ps
CPU time 793.37 seconds
Started Jan 25 05:26:15 AM PST 24
Finished Jan 25 05:39:31 AM PST 24
Peak memory 191808 kb
Host smart-c09bf48c-9033-484b-b787-8abee367c6d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135074353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.135074353
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3610961121
Short name T216
Test name
Test status
Simulation time 2433524213840 ps
CPU time 450.21 seconds
Started Jan 25 04:13:01 AM PST 24
Finished Jan 25 04:20:33 AM PST 24
Peak memory 194612 kb
Host smart-b3d8ee5a-22c5-425b-8efa-8afa5356c1bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610961121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3610961121
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2363019784
Short name T177
Test name
Test status
Simulation time 139458531644 ps
CPU time 581.92 seconds
Started Jan 25 04:13:59 AM PST 24
Finished Jan 25 04:23:44 AM PST 24
Peak memory 191732 kb
Host smart-d913af8e-f216-4190-8835-705603059c4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363019784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2363019784
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.4196244544
Short name T206
Test name
Test status
Simulation time 724831088708 ps
CPU time 1037.31 seconds
Started Jan 25 06:19:05 AM PST 24
Finished Jan 25 06:36:24 AM PST 24
Peak memory 191812 kb
Host smart-d883ae71-75ca-49c8-90a2-a69778112dd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196244544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.4196244544
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.4160036076
Short name T303
Test name
Test status
Simulation time 377966081214 ps
CPU time 206.81 seconds
Started Jan 25 04:14:41 AM PST 24
Finished Jan 25 04:18:11 AM PST 24
Peak memory 194592 kb
Host smart-88423d46-9c06-4203-bb3a-525c1d8fa464
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160036076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.4160036076
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.3524855299
Short name T178
Test name
Test status
Simulation time 196184188919 ps
CPU time 380.95 seconds
Started Jan 25 04:28:34 AM PST 24
Finished Jan 25 04:34:56 AM PST 24
Peak memory 191728 kb
Host smart-d106feda-47b3-4362-a937-145e0dd4eaa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524855299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3524855299
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random.2350960408
Short name T153
Test name
Test status
Simulation time 329537475231 ps
CPU time 348.83 seconds
Started Jan 25 04:02:48 AM PST 24
Finished Jan 25 04:08:41 AM PST 24
Peak memory 191660 kb
Host smart-ccf7bb0c-823e-424d-b8a0-3cb6c85cc721
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350960408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2350960408
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1317932804
Short name T361
Test name
Test status
Simulation time 1270590520156 ps
CPU time 513.37 seconds
Started Jan 25 04:03:28 AM PST 24
Finished Jan 25 04:12:02 AM PST 24
Peak memory 183452 kb
Host smart-c905adc1-cb09-4831-a66b-2ef9873e8047
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317932804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1317932804
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.1379157756
Short name T289
Test name
Test status
Simulation time 97308711366 ps
CPU time 262.28 seconds
Started Jan 25 04:03:45 AM PST 24
Finished Jan 25 04:08:08 AM PST 24
Peak memory 191748 kb
Host smart-40bcd4f7-7876-4ca7-abbb-6c611a1a837b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379157756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1379157756
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.546575596
Short name T226
Test name
Test status
Simulation time 291238754191 ps
CPU time 523.65 seconds
Started Jan 25 04:04:06 AM PST 24
Finished Jan 25 04:12:52 AM PST 24
Peak memory 183524 kb
Host smart-9f16ed8e-308e-4a3b-be2b-c274940d9c6a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546575596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.546575596
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_random.631256114
Short name T171
Test name
Test status
Simulation time 150243449382 ps
CPU time 117.47 seconds
Started Jan 25 04:06:04 AM PST 24
Finished Jan 25 04:08:02 AM PST 24
Peak memory 191716 kb
Host smart-85215288-a699-4e14-8627-b8f50ae3a5af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631256114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.631256114
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.594736654
Short name T156
Test name
Test status
Simulation time 221337355759 ps
CPU time 968.42 seconds
Started Jan 25 06:36:26 AM PST 24
Finished Jan 25 06:52:36 AM PST 24
Peak memory 201884 kb
Host smart-f6a5e749-79ee-4cde-ae50-7336a9f38444
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594736654 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.594736654
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.678705964
Short name T265
Test name
Test status
Simulation time 733603686030 ps
CPU time 599.1 seconds
Started Jan 25 04:06:41 AM PST 24
Finished Jan 25 04:16:43 AM PST 24
Peak memory 191720 kb
Host smart-dd59ffd3-9bbb-421a-95bb-9084a3feb50a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678705964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
678705964
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.3280970677
Short name T181
Test name
Test status
Simulation time 636609940380 ps
CPU time 689.76 seconds
Started Jan 25 04:08:32 AM PST 24
Finished Jan 25 04:20:04 AM PST 24
Peak memory 191732 kb
Host smart-dc129875-506c-4228-9e77-313bd11fb36d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280970677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3280970677
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.3790167204
Short name T297
Test name
Test status
Simulation time 1246418057587 ps
CPU time 641.92 seconds
Started Jan 25 05:41:28 AM PST 24
Finished Jan 25 05:52:11 AM PST 24
Peak memory 194752 kb
Host smart-b307c8f1-c055-4509-9816-381ed101ea19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790167204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3790167204
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random.1004089741
Short name T282
Test name
Test status
Simulation time 972386729731 ps
CPU time 742.57 seconds
Started Jan 25 04:50:33 AM PST 24
Finished Jan 25 05:02:59 AM PST 24
Peak memory 193984 kb
Host smart-41c40579-b758-4a36-845c-d3f2ef66cad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004089741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1004089741
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.539072303
Short name T306
Test name
Test status
Simulation time 259372003928 ps
CPU time 321.71 seconds
Started Jan 25 05:21:46 AM PST 24
Finished Jan 25 05:27:14 AM PST 24
Peak memory 191856 kb
Host smart-57d82194-0b40-40aa-9f53-be90aff84bc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539072303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.539072303
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.902989458
Short name T244
Test name
Test status
Simulation time 536758016335 ps
CPU time 508.49 seconds
Started Jan 25 03:59:02 AM PST 24
Finished Jan 25 04:07:32 AM PST 24
Peak memory 183508 kb
Host smart-f97689cf-37c0-447d-ae39-f2a6827e0c98
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902989458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.rv_timer_cfg_update_on_fly.902989458
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_random.280221559
Short name T184
Test name
Test status
Simulation time 81139568992 ps
CPU time 71.04 seconds
Started Jan 25 03:59:02 AM PST 24
Finished Jan 25 04:00:14 AM PST 24
Peak memory 191708 kb
Host smart-344bdaf6-2118-4a48-94e0-891fef299a8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280221559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.280221559
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.2183467438
Short name T101
Test name
Test status
Simulation time 348015312130 ps
CPU time 423.59 seconds
Started Jan 25 04:11:35 AM PST 24
Finished Jan 25 04:18:40 AM PST 24
Peak memory 194384 kb
Host smart-46294d8e-737a-4990-a170-f74606d7d8dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183467438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2183467438
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.843376978
Short name T238
Test name
Test status
Simulation time 107670341103 ps
CPU time 748.68 seconds
Started Jan 25 04:11:54 AM PST 24
Finished Jan 25 04:24:25 AM PST 24
Peak memory 191696 kb
Host smart-954259b6-a97e-431a-b207-ddc06c5a188a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843376978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.843376978
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2596801460
Short name T46
Test name
Test status
Simulation time 78323318929 ps
CPU time 148.85 seconds
Started Jan 25 05:33:59 AM PST 24
Finished Jan 25 05:36:29 AM PST 24
Peak memory 191872 kb
Host smart-0e864623-a32a-4609-b480-a5f0bd4944e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596801460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2596801460
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1273421803
Short name T202
Test name
Test status
Simulation time 196140923537 ps
CPU time 1118.75 seconds
Started Jan 25 04:13:05 AM PST 24
Finished Jan 25 04:31:45 AM PST 24
Peak memory 191704 kb
Host smart-a3ca2b3e-4740-4cbb-b1a1-6570f0b0cdd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273421803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1273421803
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.4007448603
Short name T201
Test name
Test status
Simulation time 576710835563 ps
CPU time 203.84 seconds
Started Jan 25 04:13:00 AM PST 24
Finished Jan 25 04:16:25 AM PST 24
Peak memory 191724 kb
Host smart-ec86b22e-ca7a-45c4-bab2-b46367ec0898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007448603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.4007448603
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.1464047178
Short name T175
Test name
Test status
Simulation time 41242900062 ps
CPU time 72.98 seconds
Started Jan 25 04:13:25 AM PST 24
Finished Jan 25 04:14:39 AM PST 24
Peak memory 191708 kb
Host smart-e064f83d-3e69-41b6-916d-591e8dce782c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464047178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1464047178
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.4046163702
Short name T270
Test name
Test status
Simulation time 32572778364 ps
CPU time 55.25 seconds
Started Jan 25 04:13:23 AM PST 24
Finished Jan 25 04:14:19 AM PST 24
Peak memory 183488 kb
Host smart-c911be06-0349-4db5-980f-1db5e6eedd7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046163702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.4046163702
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.878628778
Short name T354
Test name
Test status
Simulation time 52963557261 ps
CPU time 90.81 seconds
Started Jan 25 04:14:23 AM PST 24
Finished Jan 25 04:15:55 AM PST 24
Peak memory 194924 kb
Host smart-d209fc2a-abb9-4851-b65b-65c647c55876
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878628778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.878628778
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.2669022029
Short name T195
Test name
Test status
Simulation time 606358790399 ps
CPU time 882.08 seconds
Started Jan 25 04:14:25 AM PST 24
Finished Jan 25 04:29:09 AM PST 24
Peak memory 191704 kb
Host smart-2b718af0-78eb-4978-9619-5c259a4fc487
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669022029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2669022029
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1583563510
Short name T137
Test name
Test status
Simulation time 49464290105 ps
CPU time 355.45 seconds
Started Jan 25 04:14:42 AM PST 24
Finished Jan 25 04:20:40 AM PST 24
Peak memory 191732 kb
Host smart-45714640-a17b-415b-b338-afca10693ec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583563510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1583563510
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3487813280
Short name T310
Test name
Test status
Simulation time 234951475931 ps
CPU time 383.72 seconds
Started Jan 25 04:01:15 AM PST 24
Finished Jan 25 04:07:39 AM PST 24
Peak memory 183484 kb
Host smart-e5440bf5-ce37-4359-a290-56b6356e54ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487813280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.3487813280
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.322601588
Short name T154
Test name
Test status
Simulation time 822651750399 ps
CPU time 1031.36 seconds
Started Jan 25 04:03:10 AM PST 24
Finished Jan 25 04:20:26 AM PST 24
Peak memory 191740 kb
Host smart-3e136d0c-93b2-4cd6-92fa-aa2178a01906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322601588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.
322601588
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3216077603
Short name T337
Test name
Test status
Simulation time 219715623253 ps
CPU time 181.49 seconds
Started Jan 25 04:04:04 AM PST 24
Finished Jan 25 04:07:07 AM PST 24
Peak memory 191684 kb
Host smart-5c3becbb-45c4-4fb2-a0b0-921c419eed1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216077603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3216077603
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1159631834
Short name T293
Test name
Test status
Simulation time 743730914598 ps
CPU time 700.44 seconds
Started Jan 25 04:04:49 AM PST 24
Finished Jan 25 04:16:37 AM PST 24
Peak memory 183476 kb
Host smart-987b517c-0978-40e8-8759-2911f9b39856
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159631834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1159631834
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1875328727
Short name T343
Test name
Test status
Simulation time 121274564631 ps
CPU time 108.38 seconds
Started Jan 25 03:56:29 AM PST 24
Finished Jan 25 03:58:21 AM PST 24
Peak memory 191336 kb
Host smart-4ae54baa-2451-4e73-8a7a-3a0737793028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875328727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1875328727
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.188131965
Short name T301
Test name
Test status
Simulation time 379860758956 ps
CPU time 702.25 seconds
Started Jan 25 04:06:02 AM PST 24
Finished Jan 25 04:17:46 AM PST 24
Peak memory 183468 kb
Host smart-dcfa87b5-f086-49f6-adb1-082ad5294b13
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188131965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.rv_timer_cfg_update_on_fly.188131965
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/65.rv_timer_random.2139012593
Short name T341
Test name
Test status
Simulation time 63022092194 ps
CPU time 94.09 seconds
Started Jan 25 04:09:35 AM PST 24
Finished Jan 25 04:11:10 AM PST 24
Peak memory 191732 kb
Host smart-5a36d08c-4d89-4a09-a623-0326d614399f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139012593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2139012593
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.267179275
Short name T326
Test name
Test status
Simulation time 589123446449 ps
CPU time 152.65 seconds
Started Jan 25 04:18:01 AM PST 24
Finished Jan 25 04:20:40 AM PST 24
Peak memory 191744 kb
Host smart-393f0f97-3599-4de4-bbda-5e7c6d4ecfc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267179275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.267179275
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1537205071
Short name T83
Test name
Test status
Simulation time 18565881 ps
CPU time 0.81 seconds
Started Jan 24 11:06:51 PM PST 24
Finished Jan 24 11:06:54 PM PST 24
Peak memory 183076 kb
Host smart-1e5f2342-bb6e-45aa-b231-952482e9568a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537205071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.1537205071
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3185263466
Short name T51
Test name
Test status
Simulation time 200585320 ps
CPU time 2.41 seconds
Started Jan 24 11:06:52 PM PST 24
Finished Jan 24 11:06:57 PM PST 24
Peak memory 191416 kb
Host smart-3451e982-04e5-40f7-9c47-8279732ff299
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185263466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3185263466
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3820643431
Short name T53
Test name
Test status
Simulation time 16128909 ps
CPU time 0.56 seconds
Started Jan 24 11:06:49 PM PST 24
Finished Jan 24 11:06:51 PM PST 24
Peak memory 183068 kb
Host smart-3ad734dc-fd87-4465-ae8f-30924da1c20d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820643431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.3820643431
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1330582239
Short name T428
Test name
Test status
Simulation time 67193938 ps
CPU time 0.74 seconds
Started Jan 24 11:06:52 PM PST 24
Finished Jan 24 11:06:55 PM PST 24
Peak memory 195060 kb
Host smart-c88283a8-5885-464d-a8f6-0a3a8a57216c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330582239 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.1330582239
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1334775628
Short name T61
Test name
Test status
Simulation time 13868726 ps
CPU time 0.62 seconds
Started Jan 24 11:06:51 PM PST 24
Finished Jan 24 11:06:54 PM PST 24
Peak memory 183072 kb
Host smart-58dc12f7-5296-44ef-8945-f10f0d1d3928
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334775628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1334775628
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2251578375
Short name T68
Test name
Test status
Simulation time 133975448 ps
CPU time 0.56 seconds
Started Jan 24 11:06:49 PM PST 24
Finished Jan 24 11:06:51 PM PST 24
Peak memory 182680 kb
Host smart-56e13477-5de4-4934-8ab5-ccf892f7bb52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251578375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2251578375
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1721304290
Short name T446
Test name
Test status
Simulation time 66066119 ps
CPU time 0.68 seconds
Started Jan 24 11:06:51 PM PST 24
Finished Jan 24 11:06:54 PM PST 24
Peak memory 191412 kb
Host smart-a177be75-7167-478e-95cd-be874978e623
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721304290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1721304290
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3281994652
Short name T458
Test name
Test status
Simulation time 283458040 ps
CPU time 1.71 seconds
Started Jan 24 11:06:52 PM PST 24
Finished Jan 24 11:06:56 PM PST 24
Peak memory 197832 kb
Host smart-577e8831-3686-4b8c-9062-45197f85030d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281994652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3281994652
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1153495789
Short name T74
Test name
Test status
Simulation time 170713913 ps
CPU time 0.84 seconds
Started Jan 24 11:07:05 PM PST 24
Finished Jan 24 11:07:07 PM PST 24
Peak memory 192724 kb
Host smart-e1284e8a-8889-4d5f-9418-a1bea1b9b2f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153495789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1153495789
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3331174600
Short name T72
Test name
Test status
Simulation time 415231566 ps
CPU time 3.75 seconds
Started Jan 24 11:07:04 PM PST 24
Finished Jan 24 11:07:09 PM PST 24
Peak memory 191364 kb
Host smart-4a5c8b8c-ae07-4550-9623-e8bb6d4d0339
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331174600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.3331174600
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.656884520
Short name T407
Test name
Test status
Simulation time 30878899 ps
CPU time 0.58 seconds
Started Jan 24 11:07:02 PM PST 24
Finished Jan 24 11:07:04 PM PST 24
Peak memory 183040 kb
Host smart-97d53a87-df67-4003-b7bb-95a5aa41ee0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656884520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re
set.656884520
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.787651153
Short name T394
Test name
Test status
Simulation time 101934376 ps
CPU time 1.43 seconds
Started Jan 24 11:07:05 PM PST 24
Finished Jan 24 11:07:08 PM PST 24
Peak memory 197896 kb
Host smart-a84fb34d-8260-413d-bc5c-81ccb5ec2d3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787651153 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.787651153
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.575675098
Short name T477
Test name
Test status
Simulation time 65713333 ps
CPU time 0.55 seconds
Started Jan 24 11:07:04 PM PST 24
Finished Jan 24 11:07:06 PM PST 24
Peak memory 183060 kb
Host smart-4cfd469f-9d89-4672-8cee-29201681a350
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575675098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.575675098
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2432826979
Short name T79
Test name
Test status
Simulation time 27247683 ps
CPU time 0.58 seconds
Started Jan 24 11:07:04 PM PST 24
Finished Jan 24 11:07:06 PM PST 24
Peak memory 182612 kb
Host smart-d41ba5b6-a68a-492e-91e0-d71863bd1ee9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432826979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2432826979
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3438833780
Short name T67
Test name
Test status
Simulation time 28472352 ps
CPU time 0.69 seconds
Started Jan 24 11:07:02 PM PST 24
Finished Jan 24 11:07:04 PM PST 24
Peak memory 191436 kb
Host smart-1a046618-a721-4a25-aa67-702d453d838b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438833780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.3438833780
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2505069510
Short name T442
Test name
Test status
Simulation time 318921719 ps
CPU time 2.66 seconds
Started Jan 24 11:06:52 PM PST 24
Finished Jan 24 11:06:57 PM PST 24
Peak memory 197676 kb
Host smart-20359215-564d-4bc1-8e19-5b246f4816dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505069510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2505069510
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2643064653
Short name T387
Test name
Test status
Simulation time 740404926 ps
CPU time 1.19 seconds
Started Jan 24 11:07:03 PM PST 24
Finished Jan 24 11:07:06 PM PST 24
Peak memory 183404 kb
Host smart-087ec801-5e57-4a20-a788-06043bfb04fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643064653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.2643064653
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.139630288
Short name T480
Test name
Test status
Simulation time 20606132 ps
CPU time 1.05 seconds
Started Jan 24 11:09:25 PM PST 24
Finished Jan 24 11:09:27 PM PST 24
Peak memory 197812 kb
Host smart-f53c3fe5-9205-4a98-a368-d3d97879d876
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139630288 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.139630288
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2487704020
Short name T59
Test name
Test status
Simulation time 24980002 ps
CPU time 0.6 seconds
Started Jan 24 11:09:25 PM PST 24
Finished Jan 24 11:09:26 PM PST 24
Peak memory 183076 kb
Host smart-49e77c26-f730-4e4b-ac2c-a358e7dc1286
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487704020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2487704020
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.625670493
Short name T433
Test name
Test status
Simulation time 15452896 ps
CPU time 0.61 seconds
Started Jan 24 11:09:25 PM PST 24
Finished Jan 24 11:09:27 PM PST 24
Peak memory 181860 kb
Host smart-42a76449-6544-4ac6-8136-8b5a500f20b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625670493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.625670493
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2086044075
Short name T481
Test name
Test status
Simulation time 19794761 ps
CPU time 0.62 seconds
Started Jan 25 12:56:22 AM PST 24
Finished Jan 25 12:56:24 AM PST 24
Peak memory 191392 kb
Host smart-cbd176dc-5f3b-4e0d-9d5a-eefc3e2b580e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086044075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2086044075
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.815930553
Short name T459
Test name
Test status
Simulation time 342084493 ps
CPU time 2.52 seconds
Started Jan 24 11:09:08 PM PST 24
Finished Jan 24 11:09:12 PM PST 24
Peak memory 197876 kb
Host smart-d8d05e50-bd47-4dde-8ba8-8fe0e0afe1fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815930553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.815930553
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.4151714964
Short name T473
Test name
Test status
Simulation time 873213138 ps
CPU time 1.15 seconds
Started Jan 24 11:09:06 PM PST 24
Finished Jan 24 11:09:09 PM PST 24
Peak memory 183228 kb
Host smart-16d98543-b230-4f47-9903-3d780113bd77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151714964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.4151714964
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1985965952
Short name T475
Test name
Test status
Simulation time 37469907 ps
CPU time 1.16 seconds
Started Jan 24 11:09:52 PM PST 24
Finished Jan 24 11:09:55 PM PST 24
Peak memory 197896 kb
Host smart-661d62a8-101d-4e6f-8f6c-ce12bb00e17f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985965952 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1985965952
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1676879725
Short name T451
Test name
Test status
Simulation time 14916805 ps
CPU time 0.55 seconds
Started Jan 24 11:09:25 PM PST 24
Finished Jan 24 11:09:26 PM PST 24
Peak memory 182592 kb
Host smart-45f2e829-d963-4b98-84d1-13fd538f3961
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676879725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1676879725
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3600550793
Short name T385
Test name
Test status
Simulation time 40393454 ps
CPU time 0.54 seconds
Started Jan 24 11:09:26 PM PST 24
Finished Jan 24 11:09:27 PM PST 24
Peak memory 181840 kb
Host smart-09aeb238-7bba-43ed-a153-09903607b60f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600550793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3600550793
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3150935142
Short name T444
Test name
Test status
Simulation time 48539359 ps
CPU time 2.22 seconds
Started Jan 24 11:09:26 PM PST 24
Finished Jan 24 11:09:29 PM PST 24
Peak memory 197872 kb
Host smart-157cd107-8e25-45ff-87eb-0b3f3d5a84c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150935142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3150935142
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.488082737
Short name T40
Test name
Test status
Simulation time 300772468 ps
CPU time 0.85 seconds
Started Jan 24 11:09:26 PM PST 24
Finished Jan 24 11:09:28 PM PST 24
Peak memory 183248 kb
Host smart-6f032b81-5af2-47a2-b470-91b002d3901b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488082737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.488082737
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.693810077
Short name T392
Test name
Test status
Simulation time 68673110 ps
CPU time 0.9 seconds
Started Jan 24 11:09:47 PM PST 24
Finished Jan 24 11:09:51 PM PST 24
Peak memory 197528 kb
Host smart-208dc9a1-962d-4c24-954d-e6b272679de1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693810077 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.693810077
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.3228266403
Short name T71
Test name
Test status
Simulation time 44753731 ps
CPU time 0.58 seconds
Started Jan 25 03:51:29 AM PST 24
Finished Jan 25 03:51:31 AM PST 24
Peak memory 183068 kb
Host smart-21ff42a4-9b73-452e-9e85-3605b4691fee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228266403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.3228266403
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2003825648
Short name T397
Test name
Test status
Simulation time 21035058 ps
CPU time 0.54 seconds
Started Jan 24 11:23:48 PM PST 24
Finished Jan 24 11:23:51 PM PST 24
Peak memory 181852 kb
Host smart-a59519ba-aab4-4be9-989a-f3a2b2c74b03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003825648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2003825648
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1060415328
Short name T55
Test name
Test status
Simulation time 35039343 ps
CPU time 0.85 seconds
Started Jan 24 11:09:52 PM PST 24
Finished Jan 24 11:09:54 PM PST 24
Peak memory 191996 kb
Host smart-e66c831f-bb83-44aa-92ae-701f84763485
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060415328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1060415328
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.851847750
Short name T405
Test name
Test status
Simulation time 240788913 ps
CPU time 2.76 seconds
Started Jan 24 11:09:48 PM PST 24
Finished Jan 24 11:09:54 PM PST 24
Peak memory 197884 kb
Host smart-4409f546-d3b1-4af6-b23f-e74a8e12a900
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851847750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.851847750
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.4165989130
Short name T457
Test name
Test status
Simulation time 114487832 ps
CPU time 1.53 seconds
Started Jan 24 11:09:48 PM PST 24
Finished Jan 24 11:09:52 PM PST 24
Peak memory 195312 kb
Host smart-5a8eda5d-e1cb-440a-8dcd-da0364c8e944
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165989130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.4165989130
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2549057238
Short name T422
Test name
Test status
Simulation time 56571957 ps
CPU time 1.42 seconds
Started Jan 24 11:10:08 PM PST 24
Finished Jan 24 11:10:11 PM PST 24
Peak memory 191676 kb
Host smart-ece1935b-91d1-4893-bfd3-2851ca68003f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549057238 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2549057238
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1290529326
Short name T85
Test name
Test status
Simulation time 15723396 ps
CPU time 0.6 seconds
Started Jan 24 11:09:45 PM PST 24
Finished Jan 24 11:09:49 PM PST 24
Peak memory 183020 kb
Host smart-753acb88-1ff1-43b5-8b80-d5b6f1a4a49e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290529326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1290529326
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2950615563
Short name T404
Test name
Test status
Simulation time 15155961 ps
CPU time 0.55 seconds
Started Jan 24 11:24:56 PM PST 24
Finished Jan 24 11:24:59 PM PST 24
Peak memory 181864 kb
Host smart-8f785153-5492-49ae-a0b7-24cf81bd5680
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950615563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2950615563
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2897618718
Short name T418
Test name
Test status
Simulation time 109431373 ps
CPU time 0.82 seconds
Started Jan 25 02:39:30 AM PST 24
Finished Jan 25 02:39:43 AM PST 24
Peak memory 193456 kb
Host smart-62c5a6ff-a00a-42c1-8edc-9b925123b93b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897618718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2897618718
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1847836164
Short name T412
Test name
Test status
Simulation time 184249444 ps
CPU time 2.51 seconds
Started Jan 24 11:09:52 PM PST 24
Finished Jan 24 11:09:56 PM PST 24
Peak memory 197872 kb
Host smart-028aa92e-b9f5-4772-ad39-a7b67065dfd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847836164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1847836164
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2691464235
Short name T409
Test name
Test status
Simulation time 235403546 ps
CPU time 1.42 seconds
Started Jan 24 11:18:48 PM PST 24
Finished Jan 24 11:18:55 PM PST 24
Peak memory 195640 kb
Host smart-3b2aa483-ac09-47be-bb30-d2300f6b15fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691464235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2691464235
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2946257137
Short name T383
Test name
Test status
Simulation time 51148632 ps
CPU time 0.83 seconds
Started Jan 24 11:10:09 PM PST 24
Finished Jan 24 11:10:12 PM PST 24
Peak memory 196652 kb
Host smart-40140f65-bc84-444a-b936-6a40884b7c04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946257137 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2946257137
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.276046296
Short name T479
Test name
Test status
Simulation time 13316884 ps
CPU time 0.56 seconds
Started Jan 24 11:10:07 PM PST 24
Finished Jan 24 11:10:08 PM PST 24
Peak memory 182484 kb
Host smart-a7f37aad-8242-4b1a-9877-8dc250f9250b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276046296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.276046296
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.142876390
Short name T425
Test name
Test status
Simulation time 146786161 ps
CPU time 0.54 seconds
Started Jan 24 11:10:08 PM PST 24
Finished Jan 24 11:10:09 PM PST 24
Peak memory 181888 kb
Host smart-b9345b62-7bc2-407f-bc79-a2829e872386
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142876390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.142876390
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3844873115
Short name T421
Test name
Test status
Simulation time 56026682 ps
CPU time 0.8 seconds
Started Jan 25 02:06:28 AM PST 24
Finished Jan 25 02:06:31 AM PST 24
Peak memory 191892 kb
Host smart-8a860a85-0d61-4994-94ed-c0d04b97361f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844873115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3844873115
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2048296231
Short name T384
Test name
Test status
Simulation time 165668118 ps
CPU time 2.54 seconds
Started Jan 24 11:10:07 PM PST 24
Finished Jan 24 11:10:11 PM PST 24
Peak memory 197916 kb
Host smart-ee603d6a-5f7c-42d7-a34c-426bfd3bb1d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048296231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2048296231
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1854223312
Short name T432
Test name
Test status
Simulation time 2077790828 ps
CPU time 1.52 seconds
Started Jan 24 11:10:08 PM PST 24
Finished Jan 24 11:10:12 PM PST 24
Peak memory 195424 kb
Host smart-392746d1-4b59-4439-a1a2-eb47626bf5df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854223312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1854223312
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.269635881
Short name T401
Test name
Test status
Simulation time 95798800 ps
CPU time 0.84 seconds
Started Jan 24 11:10:32 PM PST 24
Finished Jan 24 11:10:34 PM PST 24
Peak memory 196676 kb
Host smart-ea33620c-df1e-4edf-8751-c0f2ad10fa63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269635881 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.269635881
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3448687046
Short name T482
Test name
Test status
Simulation time 32230467 ps
CPU time 0.65 seconds
Started Jan 25 02:35:37 AM PST 24
Finished Jan 25 02:35:45 AM PST 24
Peak memory 183016 kb
Host smart-a51f6d1a-3de5-4ec2-b142-8c855c53a5ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448687046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3448687046
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1307264120
Short name T488
Test name
Test status
Simulation time 85823016 ps
CPU time 0.57 seconds
Started Jan 24 11:10:09 PM PST 24
Finished Jan 24 11:10:12 PM PST 24
Peak memory 182668 kb
Host smart-7a243655-e1cc-4e34-92f5-fe18049a5e6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307264120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1307264120
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1506907591
Short name T449
Test name
Test status
Simulation time 22150759 ps
CPU time 0.67 seconds
Started Jan 24 11:10:08 PM PST 24
Finished Jan 24 11:10:10 PM PST 24
Peak memory 191460 kb
Host smart-c4cb156a-6db1-4245-b223-7db4e405b3de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506907591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.1506907591
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1158877162
Short name T382
Test name
Test status
Simulation time 149129886 ps
CPU time 3.14 seconds
Started Jan 25 12:01:41 AM PST 24
Finished Jan 25 12:01:45 AM PST 24
Peak memory 197880 kb
Host smart-3f634f65-4d73-422a-8e0b-50f1cea1cc00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158877162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1158877162
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1427978591
Short name T16
Test name
Test status
Simulation time 120062096 ps
CPU time 0.92 seconds
Started Jan 24 11:10:08 PM PST 24
Finished Jan 24 11:10:11 PM PST 24
Peak memory 193724 kb
Host smart-72d8612d-20fc-49ce-8034-9b6a90d40067
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427978591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1427978591
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3716752881
Short name T463
Test name
Test status
Simulation time 133296395 ps
CPU time 1.6 seconds
Started Jan 24 11:10:32 PM PST 24
Finished Jan 24 11:10:35 PM PST 24
Peak memory 197924 kb
Host smart-0d526511-5482-4625-aab4-65cab1c5e487
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716752881 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3716752881
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3852458756
Short name T396
Test name
Test status
Simulation time 37753836 ps
CPU time 0.62 seconds
Started Jan 24 11:10:32 PM PST 24
Finished Jan 24 11:10:34 PM PST 24
Peak memory 183060 kb
Host smart-9b12c3e3-c6e3-4e2e-88ac-a765823c8349
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852458756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3852458756
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3393841685
Short name T381
Test name
Test status
Simulation time 45474272 ps
CPU time 0.55 seconds
Started Jan 24 11:10:33 PM PST 24
Finished Jan 24 11:10:36 PM PST 24
Peak memory 182328 kb
Host smart-742e7488-78c5-4c4f-b43b-e04af5c18c3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393841685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3393841685
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.207129018
Short name T435
Test name
Test status
Simulation time 26141006 ps
CPU time 0.68 seconds
Started Jan 24 11:10:32 PM PST 24
Finished Jan 24 11:10:34 PM PST 24
Peak memory 191776 kb
Host smart-c55f7150-177d-45d8-a845-5d8d99988ef3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207129018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_ti
mer_same_csr_outstanding.207129018
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.4071876746
Short name T461
Test name
Test status
Simulation time 214241332 ps
CPU time 0.92 seconds
Started Jan 24 11:10:29 PM PST 24
Finished Jan 24 11:10:32 PM PST 24
Peak memory 195928 kb
Host smart-9a92de55-c9b1-4914-8682-940aeeab7194
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071876746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.4071876746
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2279479093
Short name T485
Test name
Test status
Simulation time 248690482 ps
CPU time 1.39 seconds
Started Jan 24 11:10:33 PM PST 24
Finished Jan 24 11:10:37 PM PST 24
Peak memory 183300 kb
Host smart-c972f97c-348e-4ef4-bacf-4c4abdc6074f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279479093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2279479093
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2673532561
Short name T487
Test name
Test status
Simulation time 31510714 ps
CPU time 1.51 seconds
Started Jan 24 11:10:30 PM PST 24
Finished Jan 24 11:10:33 PM PST 24
Peak memory 197924 kb
Host smart-0fee3989-b6b6-445d-a1f5-0516eb071cdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673532561 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2673532561
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.447479934
Short name T54
Test name
Test status
Simulation time 15491075 ps
CPU time 0.62 seconds
Started Jan 24 11:10:29 PM PST 24
Finished Jan 24 11:10:31 PM PST 24
Peak memory 183020 kb
Host smart-d4da3219-433a-4290-861f-b9b175346f1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447479934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.447479934
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1899564009
Short name T450
Test name
Test status
Simulation time 12107253 ps
CPU time 0.55 seconds
Started Jan 24 11:10:33 PM PST 24
Finished Jan 24 11:10:36 PM PST 24
Peak memory 181844 kb
Host smart-4b2559ad-505f-4129-b13f-43bbbbdb5c4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899564009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1899564009
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.4144584178
Short name T87
Test name
Test status
Simulation time 29854735 ps
CPU time 0.69 seconds
Started Jan 24 11:10:34 PM PST 24
Finished Jan 24 11:10:37 PM PST 24
Peak memory 191708 kb
Host smart-9e6305cf-7f02-4d92-8b66-f488845d8ccb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144584178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.4144584178
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1898042224
Short name T36
Test name
Test status
Simulation time 1741649620 ps
CPU time 2.92 seconds
Started Jan 24 11:10:32 PM PST 24
Finished Jan 24 11:10:37 PM PST 24
Peak memory 197840 kb
Host smart-52cb3862-3649-45d4-b8f4-fbe81abaeae9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898042224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1898042224
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3449621234
Short name T456
Test name
Test status
Simulation time 51453433 ps
CPU time 0.79 seconds
Started Jan 24 11:10:52 PM PST 24
Finished Jan 24 11:10:54 PM PST 24
Peak memory 191484 kb
Host smart-7f7b61b0-c4b0-47f7-b269-a0635838f984
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449621234 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3449621234
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.557436081
Short name T448
Test name
Test status
Simulation time 26880480 ps
CPU time 0.6 seconds
Started Jan 24 11:10:47 PM PST 24
Finished Jan 24 11:10:50 PM PST 24
Peak memory 182744 kb
Host smart-aa1b4983-d732-4dcb-9e6f-63971e325209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557436081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.557436081
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2297067506
Short name T94
Test name
Test status
Simulation time 17713019 ps
CPU time 0.75 seconds
Started Jan 24 11:10:53 PM PST 24
Finished Jan 24 11:10:55 PM PST 24
Peak memory 191884 kb
Host smart-0b1bbadf-16da-42ae-9c03-507866909609
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297067506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.2297067506
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2372484069
Short name T37
Test name
Test status
Simulation time 238425177 ps
CPU time 2.13 seconds
Started Jan 24 11:10:32 PM PST 24
Finished Jan 24 11:10:35 PM PST 24
Peak memory 197888 kb
Host smart-0802a9c2-a721-4044-a6e0-30df08552d57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372484069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2372484069
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.22231051
Short name T455
Test name
Test status
Simulation time 130995311 ps
CPU time 1.45 seconds
Started Jan 24 11:10:52 PM PST 24
Finished Jan 24 11:10:55 PM PST 24
Peak memory 195532 kb
Host smart-e0654abe-8314-4df0-b956-b40aa42abb9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22231051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_int
g_err.22231051
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1245121670
Short name T80
Test name
Test status
Simulation time 116377416 ps
CPU time 0.92 seconds
Started Jan 24 11:11:00 PM PST 24
Finished Jan 24 11:11:02 PM PST 24
Peak memory 194988 kb
Host smart-fcb140ae-1fe4-4efc-b008-3da15a010d1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245121670 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1245121670
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2952733428
Short name T478
Test name
Test status
Simulation time 203555610 ps
CPU time 0.6 seconds
Started Jan 24 11:11:00 PM PST 24
Finished Jan 24 11:11:02 PM PST 24
Peak memory 183012 kb
Host smart-cad76686-a3d7-4642-ab5e-e6ea403c0955
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952733428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2952733428
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3121104434
Short name T391
Test name
Test status
Simulation time 15767555 ps
CPU time 0.59 seconds
Started Jan 24 11:11:03 PM PST 24
Finished Jan 24 11:11:05 PM PST 24
Peak memory 182324 kb
Host smart-46628740-e796-479d-abf7-2f2672aa1e85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121104434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3121104434
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2218887937
Short name T96
Test name
Test status
Simulation time 52577407 ps
CPU time 0.71 seconds
Started Jan 24 11:11:00 PM PST 24
Finished Jan 24 11:11:02 PM PST 24
Peak memory 191728 kb
Host smart-73443403-486c-4220-8b71-6454c6e4d1a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218887937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2218887937
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3160883153
Short name T441
Test name
Test status
Simulation time 139905759 ps
CPU time 1.13 seconds
Started Jan 24 11:10:50 PM PST 24
Finished Jan 24 11:10:53 PM PST 24
Peak memory 197684 kb
Host smart-ffbdc936-2d38-4dd1-9111-3db6ff5e5790
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160883153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3160883153
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2656969510
Short name T98
Test name
Test status
Simulation time 109525373 ps
CPU time 1.14 seconds
Started Jan 24 11:10:55 PM PST 24
Finished Jan 24 11:10:57 PM PST 24
Peak memory 183348 kb
Host smart-bc7d67bc-4627-4c60-906d-591f1bae4ad7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656969510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2656969510
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1562189381
Short name T388
Test name
Test status
Simulation time 149956668 ps
CPU time 0.61 seconds
Started Jan 24 11:07:23 PM PST 24
Finished Jan 24 11:07:24 PM PST 24
Peak memory 183028 kb
Host smart-63ed176f-8b39-4559-a167-ea65a43c0d8f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562189381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1562189381
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2100923065
Short name T73
Test name
Test status
Simulation time 310264354 ps
CPU time 3.25 seconds
Started Jan 24 11:07:21 PM PST 24
Finished Jan 24 11:07:25 PM PST 24
Peak memory 192572 kb
Host smart-a8b3baf5-842b-4bdb-b249-7abecdf3b64d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100923065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.2100923065
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1099156415
Short name T38
Test name
Test status
Simulation time 27638431 ps
CPU time 0.57 seconds
Started Jan 24 11:07:24 PM PST 24
Finished Jan 24 11:07:25 PM PST 24
Peak memory 183060 kb
Host smart-0ed11b44-28a8-4690-b0ff-7451648a488a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099156415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.1099156415
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3871685541
Short name T470
Test name
Test status
Simulation time 38284218 ps
CPU time 0.78 seconds
Started Jan 24 11:07:38 PM PST 24
Finished Jan 24 11:07:40 PM PST 24
Peak memory 195280 kb
Host smart-064b5e91-293a-4c16-b302-ac8f09225e29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871685541 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3871685541
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2578328052
Short name T60
Test name
Test status
Simulation time 31156052 ps
CPU time 0.58 seconds
Started Jan 24 11:07:24 PM PST 24
Finished Jan 24 11:07:25 PM PST 24
Peak memory 183064 kb
Host smart-b0e456d6-7678-48c3-a3d3-6280ffc812cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578328052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2578328052
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.559338545
Short name T429
Test name
Test status
Simulation time 71956393 ps
CPU time 0.55 seconds
Started Jan 24 11:07:21 PM PST 24
Finished Jan 24 11:07:23 PM PST 24
Peak memory 182692 kb
Host smart-93927e2b-118f-4d63-abcd-aaf7ca9827ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559338545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.559338545
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3928325920
Short name T52
Test name
Test status
Simulation time 46449324 ps
CPU time 0.72 seconds
Started Jan 24 11:07:39 PM PST 24
Finished Jan 24 11:07:41 PM PST 24
Peak memory 192432 kb
Host smart-85944a29-1496-4293-9aec-96286553b497
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928325920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3928325920
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1208431308
Short name T436
Test name
Test status
Simulation time 95670654 ps
CPU time 1.24 seconds
Started Jan 24 11:07:03 PM PST 24
Finished Jan 24 11:07:06 PM PST 24
Peak memory 196752 kb
Host smart-13d76d03-f4c4-40e0-be1f-4e60240b0e71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208431308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1208431308
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3999482256
Short name T467
Test name
Test status
Simulation time 89257896 ps
CPU time 1.11 seconds
Started Jan 24 11:07:21 PM PST 24
Finished Jan 24 11:07:24 PM PST 24
Peak memory 195272 kb
Host smart-37295d32-4c25-4e19-90dd-3a4c73da552d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999482256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.3999482256
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3809636264
Short name T474
Test name
Test status
Simulation time 13552340 ps
CPU time 0.57 seconds
Started Jan 24 11:10:59 PM PST 24
Finished Jan 24 11:11:01 PM PST 24
Peak memory 182724 kb
Host smart-787e1a8c-77a3-4b24-b74e-e538cbcce75b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809636264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3809636264
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.916495105
Short name T469
Test name
Test status
Simulation time 10411666 ps
CPU time 0.55 seconds
Started Jan 24 11:11:03 PM PST 24
Finished Jan 24 11:11:05 PM PST 24
Peak memory 182336 kb
Host smart-ef7cc21a-e240-4a47-8012-b9d923d1b4ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916495105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.916495105
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2466979000
Short name T460
Test name
Test status
Simulation time 29602295 ps
CPU time 0.57 seconds
Started Jan 24 11:11:20 PM PST 24
Finished Jan 24 11:11:24 PM PST 24
Peak memory 182748 kb
Host smart-0c4cc492-d0b5-42d4-b772-5fef594ea0c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466979000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2466979000
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3945430077
Short name T399
Test name
Test status
Simulation time 14252023 ps
CPU time 0.56 seconds
Started Jan 25 03:05:12 AM PST 24
Finished Jan 25 03:05:14 AM PST 24
Peak memory 182652 kb
Host smart-40f4c584-e6e3-4dac-8838-8d341e64ae51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945430077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3945430077
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.108801400
Short name T431
Test name
Test status
Simulation time 26962967 ps
CPU time 0.54 seconds
Started Jan 24 11:11:17 PM PST 24
Finished Jan 24 11:11:19 PM PST 24
Peak memory 181908 kb
Host smart-5d034c29-6d4d-468b-aca2-b0e7b1620ae2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108801400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.108801400
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3823576492
Short name T440
Test name
Test status
Simulation time 33904402 ps
CPU time 0.57 seconds
Started Jan 24 11:11:18 PM PST 24
Finished Jan 24 11:11:19 PM PST 24
Peak memory 182736 kb
Host smart-e3b84b34-8f22-401b-b585-01899b7fc54f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823576492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3823576492
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1088199118
Short name T92
Test name
Test status
Simulation time 23916115 ps
CPU time 0.55 seconds
Started Jan 24 11:11:21 PM PST 24
Finished Jan 24 11:11:24 PM PST 24
Peak memory 181920 kb
Host smart-791490f5-553c-4eaa-9b66-42d5977d81a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088199118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1088199118
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2415416673
Short name T476
Test name
Test status
Simulation time 51061984 ps
CPU time 0.61 seconds
Started Jan 24 11:11:18 PM PST 24
Finished Jan 24 11:11:22 PM PST 24
Peak memory 182788 kb
Host smart-07a83645-309b-4c2a-bc1c-756a020ca864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415416673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2415416673
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3274298383
Short name T454
Test name
Test status
Simulation time 16207082 ps
CPU time 0.6 seconds
Started Jan 25 12:11:44 AM PST 24
Finished Jan 25 12:11:46 AM PST 24
Peak memory 182664 kb
Host smart-d2a80064-9ac7-4409-ba5e-d790411eff19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274298383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3274298383
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2967201594
Short name T90
Test name
Test status
Simulation time 14238498 ps
CPU time 0.53 seconds
Started Jan 24 11:11:19 PM PST 24
Finished Jan 24 11:11:24 PM PST 24
Peak memory 181852 kb
Host smart-d2abbbba-c94b-4193-8fe3-bbf5f0db8cd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967201594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2967201594
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1529399649
Short name T91
Test name
Test status
Simulation time 52736175 ps
CPU time 0.8 seconds
Started Jan 24 11:07:40 PM PST 24
Finished Jan 24 11:07:41 PM PST 24
Peak memory 183048 kb
Host smart-5a19d49a-8b39-41d2-803a-dd5a59f47265
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529399649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.1529399649
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2265918027
Short name T39
Test name
Test status
Simulation time 408702508 ps
CPU time 3.81 seconds
Started Jan 24 11:07:37 PM PST 24
Finished Jan 24 11:07:42 PM PST 24
Peak memory 183360 kb
Host smart-706cec0c-c782-4f56-bf75-e3c289a835bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265918027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2265918027
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2821449745
Short name T398
Test name
Test status
Simulation time 65764527 ps
CPU time 0.56 seconds
Started Jan 24 11:07:40 PM PST 24
Finished Jan 24 11:07:41 PM PST 24
Peak memory 183072 kb
Host smart-61ee6cc6-bca7-4594-9fa8-d72a741f9db8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821449745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.2821449745
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1590584954
Short name T41
Test name
Test status
Simulation time 83738139 ps
CPU time 0.89 seconds
Started Jan 25 01:45:08 AM PST 24
Finished Jan 25 01:45:10 AM PST 24
Peak memory 195564 kb
Host smart-9f305fbe-e648-4d46-88d8-66d31a2b3edf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590584954 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1590584954
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1888965369
Short name T430
Test name
Test status
Simulation time 134051166 ps
CPU time 0.54 seconds
Started Jan 24 11:07:37 PM PST 24
Finished Jan 24 11:07:39 PM PST 24
Peak memory 183012 kb
Host smart-7c52eefe-4561-4ad9-9399-156c2624db83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888965369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1888965369
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3497476333
Short name T443
Test name
Test status
Simulation time 18572654 ps
CPU time 0.59 seconds
Started Jan 24 11:07:40 PM PST 24
Finished Jan 24 11:07:42 PM PST 24
Peak memory 182660 kb
Host smart-9e3a8e65-2b91-404a-b883-9b182a022304
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497476333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3497476333
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2883383311
Short name T465
Test name
Test status
Simulation time 18767831 ps
CPU time 0.77 seconds
Started Jan 24 11:57:04 PM PST 24
Finished Jan 24 11:57:06 PM PST 24
Peak memory 191856 kb
Host smart-376d2203-912a-4366-a520-743128afda18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883383311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.2883383311
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1644060884
Short name T403
Test name
Test status
Simulation time 185169971 ps
CPU time 2.85 seconds
Started Jan 24 11:07:38 PM PST 24
Finished Jan 24 11:07:42 PM PST 24
Peak memory 197884 kb
Host smart-ab9f7d38-b8e7-4879-9646-860f4b8f271f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644060884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1644060884
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3242386713
Short name T390
Test name
Test status
Simulation time 83855206 ps
CPU time 0.81 seconds
Started Jan 24 11:07:38 PM PST 24
Finished Jan 24 11:07:40 PM PST 24
Peak memory 193544 kb
Host smart-da47a518-5ce6-4753-ac51-783402a992ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242386713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3242386713
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2399344566
Short name T419
Test name
Test status
Simulation time 267310356 ps
CPU time 0.56 seconds
Started Jan 24 11:11:18 PM PST 24
Finished Jan 24 11:11:19 PM PST 24
Peak memory 182736 kb
Host smart-dc997fd2-e85a-4468-b178-d8b7fbbf453c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399344566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2399344566
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.382158305
Short name T82
Test name
Test status
Simulation time 14207828 ps
CPU time 0.57 seconds
Started Jan 24 11:11:19 PM PST 24
Finished Jan 24 11:11:24 PM PST 24
Peak memory 182680 kb
Host smart-08fb02e1-d798-46c2-b8ac-0491dbd1dc39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382158305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.382158305
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3310577990
Short name T427
Test name
Test status
Simulation time 121672883 ps
CPU time 0.61 seconds
Started Jan 24 11:11:21 PM PST 24
Finished Jan 24 11:11:24 PM PST 24
Peak memory 182812 kb
Host smart-3884cb21-33fe-4228-ae53-b6c2699f097c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310577990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.3310577990
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.4040309000
Short name T75
Test name
Test status
Simulation time 42339316 ps
CPU time 0.56 seconds
Started Jan 24 11:11:15 PM PST 24
Finished Jan 24 11:11:17 PM PST 24
Peak memory 181812 kb
Host smart-cce0d06a-81c3-4b21-930c-2aee98b801ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040309000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.4040309000
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.4096045063
Short name T408
Test name
Test status
Simulation time 32621137 ps
CPU time 0.57 seconds
Started Jan 24 11:11:19 PM PST 24
Finished Jan 24 11:11:22 PM PST 24
Peak memory 182316 kb
Host smart-07099a2a-fee5-4841-a089-c21d2a263475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096045063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.4096045063
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2937351741
Short name T439
Test name
Test status
Simulation time 11220130 ps
CPU time 0.56 seconds
Started Jan 25 06:51:04 AM PST 24
Finished Jan 25 06:51:12 AM PST 24
Peak memory 182800 kb
Host smart-96f3c5a6-e02b-4673-9678-6292c8bc360d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937351741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2937351741
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2667472925
Short name T413
Test name
Test status
Simulation time 24146066 ps
CPU time 0.55 seconds
Started Jan 24 11:11:39 PM PST 24
Finished Jan 24 11:11:43 PM PST 24
Peak memory 181840 kb
Host smart-bdd7ce64-eb2b-4f37-81f0-8b7f6edd49bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667472925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2667472925
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1686832955
Short name T472
Test name
Test status
Simulation time 14948541 ps
CPU time 0.56 seconds
Started Jan 24 11:11:37 PM PST 24
Finished Jan 24 11:11:40 PM PST 24
Peak memory 181916 kb
Host smart-799ac2b5-1213-4a68-b1a8-1077b1b85a0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686832955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1686832955
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.485608187
Short name T386
Test name
Test status
Simulation time 13736000 ps
CPU time 0.57 seconds
Started Jan 24 11:11:36 PM PST 24
Finished Jan 24 11:11:40 PM PST 24
Peak memory 182740 kb
Host smart-b68ca1de-f965-4566-b46b-c2b363d913a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485608187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.485608187
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.4170354472
Short name T69
Test name
Test status
Simulation time 22491168 ps
CPU time 0.53 seconds
Started Jan 24 11:11:40 PM PST 24
Finished Jan 24 11:11:44 PM PST 24
Peak memory 181908 kb
Host smart-9a8dbcfb-7d8e-4819-9399-83f7865e9edc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170354472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.4170354472
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3608328220
Short name T417
Test name
Test status
Simulation time 22368820 ps
CPU time 0.7 seconds
Started Jan 24 11:08:00 PM PST 24
Finished Jan 24 11:08:04 PM PST 24
Peak memory 192316 kb
Host smart-d82cdae7-3083-4c78-8882-0d234d84f3c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608328220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3608328220
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2058698551
Short name T50
Test name
Test status
Simulation time 501039953 ps
CPU time 1.67 seconds
Started Jan 25 01:21:14 AM PST 24
Finished Jan 25 01:21:16 AM PST 24
Peak memory 192464 kb
Host smart-b7b0c5fd-cf8f-4310-b725-831435ca851e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058698551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2058698551
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3253745614
Short name T70
Test name
Test status
Simulation time 58695354 ps
CPU time 0.58 seconds
Started Jan 25 12:30:16 AM PST 24
Finished Jan 25 12:30:18 AM PST 24
Peak memory 183096 kb
Host smart-999e1d30-9c63-49c6-b1eb-098a2e03809e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253745614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3253745614
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1484289858
Short name T452
Test name
Test status
Simulation time 410044750 ps
CPU time 0.86 seconds
Started Jan 24 11:08:21 PM PST 24
Finished Jan 24 11:08:24 PM PST 24
Peak memory 195640 kb
Host smart-439235bd-1262-4898-a110-68f25ee57fe3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484289858 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1484289858
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3781709035
Short name T453
Test name
Test status
Simulation time 16973532 ps
CPU time 0.59 seconds
Started Jan 24 11:08:01 PM PST 24
Finished Jan 24 11:08:05 PM PST 24
Peak memory 183004 kb
Host smart-b6bacc5b-e20d-43c5-a21d-e264e1103980
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781709035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3781709035
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3406414917
Short name T468
Test name
Test status
Simulation time 28066063 ps
CPU time 0.56 seconds
Started Jan 24 11:08:00 PM PST 24
Finished Jan 24 11:08:02 PM PST 24
Peak memory 181908 kb
Host smart-34ea9408-2b37-4d94-bc44-37d7c1c20b1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406414917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3406414917
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3507773142
Short name T95
Test name
Test status
Simulation time 52774337 ps
CPU time 0.7 seconds
Started Jan 24 11:07:59 PM PST 24
Finished Jan 24 11:08:01 PM PST 24
Peak memory 192268 kb
Host smart-d5346ab8-85a6-401b-a77c-97bb04846e58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507773142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.3507773142
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3212444979
Short name T395
Test name
Test status
Simulation time 53857800 ps
CPU time 1.12 seconds
Started Jan 24 11:08:01 PM PST 24
Finished Jan 24 11:08:05 PM PST 24
Peak memory 197132 kb
Host smart-4ea33257-8e90-4091-aba9-5df49c7ee7dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212444979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3212444979
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1794175335
Short name T389
Test name
Test status
Simulation time 784216366 ps
CPU time 1.06 seconds
Started Jan 25 12:02:43 AM PST 24
Finished Jan 25 12:02:46 AM PST 24
Peak memory 183328 kb
Host smart-d10c68b4-ac28-438a-930f-a021bba81736
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794175335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1794175335
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.4049172791
Short name T483
Test name
Test status
Simulation time 14163110 ps
CPU time 0.56 seconds
Started Jan 24 11:11:37 PM PST 24
Finished Jan 24 11:11:41 PM PST 24
Peak memory 182640 kb
Host smart-ff4e6e45-0ffc-4974-a78c-15990fcd3781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049172791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.4049172791
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1822318792
Short name T411
Test name
Test status
Simulation time 14280273 ps
CPU time 0.55 seconds
Started Jan 24 11:11:39 PM PST 24
Finished Jan 24 11:11:43 PM PST 24
Peak memory 182664 kb
Host smart-7b32ba8e-47dc-488f-b433-0c88e9d1d3f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822318792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1822318792
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2254874198
Short name T438
Test name
Test status
Simulation time 53250282 ps
CPU time 0.54 seconds
Started Jan 24 11:11:36 PM PST 24
Finished Jan 24 11:11:40 PM PST 24
Peak memory 182688 kb
Host smart-8c2db4f4-3abf-46f4-b107-0223e6ca2762
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254874198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2254874198
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2468491783
Short name T64
Test name
Test status
Simulation time 26044337 ps
CPU time 0.58 seconds
Started Jan 25 03:17:12 AM PST 24
Finished Jan 25 03:17:13 AM PST 24
Peak memory 182792 kb
Host smart-5f4f2778-43b2-45c0-94be-1cf611f0bca5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468491783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2468491783
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1791437070
Short name T410
Test name
Test status
Simulation time 55725977 ps
CPU time 0.54 seconds
Started Jan 24 11:11:36 PM PST 24
Finished Jan 24 11:11:40 PM PST 24
Peak memory 182676 kb
Host smart-f7fdbb45-4944-47f8-80bc-126f2ab4349d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791437070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1791437070
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.4003298433
Short name T464
Test name
Test status
Simulation time 26382526 ps
CPU time 0.56 seconds
Started Jan 24 11:36:07 PM PST 24
Finished Jan 24 11:36:14 PM PST 24
Peak memory 182756 kb
Host smart-a6770ef9-24ab-48b8-8c58-f468bac8a9c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003298433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.4003298433
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2172927675
Short name T471
Test name
Test status
Simulation time 61307737 ps
CPU time 0.55 seconds
Started Jan 24 11:11:40 PM PST 24
Finished Jan 24 11:11:44 PM PST 24
Peak memory 182652 kb
Host smart-a42fd9d6-8b80-45ff-9b7f-20490e711b7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172927675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2172927675
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2753016
Short name T414
Test name
Test status
Simulation time 13459938 ps
CPU time 0.59 seconds
Started Jan 24 11:11:34 PM PST 24
Finished Jan 24 11:11:39 PM PST 24
Peak memory 182628 kb
Host smart-a6790a51-a528-4d4f-9888-1eb8f68b6f1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2753016
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1217387359
Short name T415
Test name
Test status
Simulation time 27886341 ps
CPU time 0.55 seconds
Started Jan 24 11:11:38 PM PST 24
Finished Jan 24 11:11:42 PM PST 24
Peak memory 182696 kb
Host smart-6ba09d99-c1c1-400b-9f1f-ce001149a735
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217387359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1217387359
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2793208957
Short name T445
Test name
Test status
Simulation time 12610847 ps
CPU time 0.54 seconds
Started Jan 24 11:11:38 PM PST 24
Finished Jan 24 11:11:42 PM PST 24
Peak memory 181836 kb
Host smart-94d32953-e184-401b-a253-46289d152ea5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793208957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2793208957
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3733501645
Short name T93
Test name
Test status
Simulation time 38727751 ps
CPU time 0.9 seconds
Started Jan 24 11:08:26 PM PST 24
Finished Jan 24 11:08:28 PM PST 24
Peak memory 196496 kb
Host smart-57bf5fa0-4de4-4721-8216-c0359c9bac7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733501645 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.3733501645
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2631159388
Short name T63
Test name
Test status
Simulation time 37315054 ps
CPU time 0.56 seconds
Started Jan 24 11:08:47 PM PST 24
Finished Jan 24 11:08:49 PM PST 24
Peak memory 182412 kb
Host smart-09781d2e-4a37-432d-9ba4-bb489d0122f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631159388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2631159388
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2694045828
Short name T466
Test name
Test status
Simulation time 40750240 ps
CPU time 0.53 seconds
Started Jan 24 11:08:24 PM PST 24
Finished Jan 24 11:08:25 PM PST 24
Peak memory 181908 kb
Host smart-c7bcf708-a639-4fb1-9ace-e4794e733e88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694045828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2694045828
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3007817034
Short name T65
Test name
Test status
Simulation time 92752131 ps
CPU time 0.71 seconds
Started Jan 24 11:08:21 PM PST 24
Finished Jan 24 11:08:24 PM PST 24
Peak memory 191820 kb
Host smart-fde9ebe4-ed94-446d-8500-78c1d9b451cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007817034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3007817034
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1513276233
Short name T406
Test name
Test status
Simulation time 310447960 ps
CPU time 2.87 seconds
Started Jan 24 11:08:21 PM PST 24
Finished Jan 24 11:08:26 PM PST 24
Peak memory 197900 kb
Host smart-a7c7a64a-3394-401c-abed-22782c56a670
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513276233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1513276233
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3740799541
Short name T88
Test name
Test status
Simulation time 97048964 ps
CPU time 1.15 seconds
Started Jan 24 11:08:29 PM PST 24
Finished Jan 24 11:08:32 PM PST 24
Peak memory 195340 kb
Host smart-6f64cc59-a36b-47aa-b467-22b1229d2d04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740799541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3740799541
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3835577544
Short name T420
Test name
Test status
Simulation time 25804310 ps
CPU time 0.83 seconds
Started Jan 24 11:08:46 PM PST 24
Finished Jan 24 11:08:49 PM PST 24
Peak memory 195904 kb
Host smart-8e8d6eb9-2556-4f13-afc8-f35b0dddf37f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835577544 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3835577544
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.455623162
Short name T84
Test name
Test status
Simulation time 11453341 ps
CPU time 0.57 seconds
Started Jan 24 11:08:24 PM PST 24
Finished Jan 24 11:08:25 PM PST 24
Peak memory 183060 kb
Host smart-c51883d3-5c37-4520-8456-ad2bfedbfa3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455623162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.455623162
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1460245644
Short name T66
Test name
Test status
Simulation time 19426866 ps
CPU time 0.54 seconds
Started Jan 24 11:08:22 PM PST 24
Finished Jan 24 11:08:24 PM PST 24
Peak memory 181888 kb
Host smart-e3f69348-90e0-4522-b9c4-6d760f14154c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460245644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1460245644
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2597887416
Short name T447
Test name
Test status
Simulation time 34678215 ps
CPU time 0.86 seconds
Started Jan 24 11:08:47 PM PST 24
Finished Jan 24 11:08:49 PM PST 24
Peak memory 193368 kb
Host smart-7525d548-ecf4-430a-924e-f454f183f961
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597887416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.2597887416
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.4269047981
Short name T424
Test name
Test status
Simulation time 311332774 ps
CPU time 1.18 seconds
Started Jan 24 11:08:24 PM PST 24
Finished Jan 24 11:08:26 PM PST 24
Peak memory 196768 kb
Host smart-5ccb06c0-f5fd-4dc7-8877-0be0f017afd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269047981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.4269047981
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.561123051
Short name T99
Test name
Test status
Simulation time 357321730 ps
CPU time 0.85 seconds
Started Jan 24 11:08:22 PM PST 24
Finished Jan 24 11:08:24 PM PST 24
Peak memory 183180 kb
Host smart-914c00a0-6a6c-4e39-955e-ed7a50c04e61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561123051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.561123051
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.530801649
Short name T402
Test name
Test status
Simulation time 24260378 ps
CPU time 1.23 seconds
Started Jan 24 11:08:49 PM PST 24
Finished Jan 24 11:08:53 PM PST 24
Peak memory 197888 kb
Host smart-8ff4d170-b06a-48f1-9638-8659c2eb2a6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530801649 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.530801649
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3685679527
Short name T423
Test name
Test status
Simulation time 14385315 ps
CPU time 0.64 seconds
Started Jan 25 12:14:33 AM PST 24
Finished Jan 25 12:14:37 AM PST 24
Peak memory 183084 kb
Host smart-7d52c340-2901-4608-ae45-0b67213cb407
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685679527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3685679527
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.4009432339
Short name T462
Test name
Test status
Simulation time 29903934 ps
CPU time 0.58 seconds
Started Jan 24 11:08:49 PM PST 24
Finished Jan 24 11:08:52 PM PST 24
Peak memory 182668 kb
Host smart-336b0e04-a0a9-48ff-a90d-68c68735b0a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009432339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.4009432339
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.882663572
Short name T15
Test name
Test status
Simulation time 18284448 ps
CPU time 0.71 seconds
Started Jan 24 11:08:48 PM PST 24
Finished Jan 24 11:08:52 PM PST 24
Peak memory 193308 kb
Host smart-b36e1417-d2f1-4989-9044-781b28dee5b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882663572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_tim
er_same_csr_outstanding.882663572
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3458046400
Short name T484
Test name
Test status
Simulation time 210744497 ps
CPU time 2.8 seconds
Started Jan 24 11:08:49 PM PST 24
Finished Jan 24 11:08:54 PM PST 24
Peak memory 197892 kb
Host smart-bce93e10-32a4-4971-8e20-8f1dd49be9ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458046400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3458046400
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1725523497
Short name T78
Test name
Test status
Simulation time 92516502 ps
CPU time 1.14 seconds
Started Jan 24 11:08:48 PM PST 24
Finished Jan 24 11:08:51 PM PST 24
Peak memory 195124 kb
Host smart-ed9ec44d-690d-4fe5-8b77-8a30ef3a6e7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725523497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1725523497
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2947082355
Short name T393
Test name
Test status
Simulation time 319423168 ps
CPU time 0.66 seconds
Started Jan 24 11:08:47 PM PST 24
Finished Jan 24 11:08:50 PM PST 24
Peak memory 192796 kb
Host smart-42282fad-5d6a-43d3-b623-78c91611f2a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947082355 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2947082355
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3755625776
Short name T58
Test name
Test status
Simulation time 37668525 ps
CPU time 0.6 seconds
Started Jan 24 11:08:46 PM PST 24
Finished Jan 24 11:08:48 PM PST 24
Peak memory 183016 kb
Host smart-9801afc7-2b3f-4123-84c6-89b388496dac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755625776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3755625776
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3275961567
Short name T486
Test name
Test status
Simulation time 16123958 ps
CPU time 0.61 seconds
Started Jan 25 12:04:27 AM PST 24
Finished Jan 25 12:04:31 AM PST 24
Peak memory 182816 kb
Host smart-201bf257-5b7c-4fec-8989-5b73eb835986
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275961567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3275961567
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.718753115
Short name T416
Test name
Test status
Simulation time 104073167 ps
CPU time 0.75 seconds
Started Jan 24 11:13:06 PM PST 24
Finished Jan 24 11:13:08 PM PST 24
Peak memory 193384 kb
Host smart-aadc18ee-a111-4e4d-90c0-ea3ce43ba4a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718753115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim
er_same_csr_outstanding.718753115
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3727070315
Short name T77
Test name
Test status
Simulation time 100141486 ps
CPU time 2.06 seconds
Started Jan 24 11:08:45 PM PST 24
Finished Jan 24 11:08:48 PM PST 24
Peak memory 197872 kb
Host smart-926891f3-67e5-4fa9-9099-1c443dec6b41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727070315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3727070315
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1115027662
Short name T434
Test name
Test status
Simulation time 121782447 ps
CPU time 1.59 seconds
Started Jan 25 01:15:22 AM PST 24
Finished Jan 25 01:15:25 AM PST 24
Peak memory 183256 kb
Host smart-feff5566-2bbf-4ced-9e42-3080a4b33d85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115027662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1115027662
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3805737635
Short name T426
Test name
Test status
Simulation time 21732324 ps
CPU time 0.76 seconds
Started Jan 25 12:26:46 AM PST 24
Finished Jan 25 12:26:47 AM PST 24
Peak memory 195332 kb
Host smart-a7aa1c11-d07f-43ce-b26a-037c08a25697
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805737635 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3805737635
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3374036563
Short name T400
Test name
Test status
Simulation time 34331152 ps
CPU time 0.55 seconds
Started Jan 24 11:09:07 PM PST 24
Finished Jan 24 11:09:09 PM PST 24
Peak memory 182540 kb
Host smart-504a1551-8c39-4f66-8216-2911efb76117
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374036563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3374036563
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.851659401
Short name T437
Test name
Test status
Simulation time 14977438 ps
CPU time 0.56 seconds
Started Jan 25 05:07:02 AM PST 24
Finished Jan 25 05:07:11 AM PST 24
Peak memory 181920 kb
Host smart-dc8c9b33-65e7-441b-b1b6-fdd32eefe3fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851659401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.851659401
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2273601970
Short name T76
Test name
Test status
Simulation time 35463446 ps
CPU time 0.66 seconds
Started Jan 24 11:33:40 PM PST 24
Finished Jan 24 11:33:43 PM PST 24
Peak memory 192272 kb
Host smart-9616486b-5f54-4dbd-92ae-d3bf95d76bf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273601970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2273601970
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1860584057
Short name T81
Test name
Test status
Simulation time 88103946 ps
CPU time 1.26 seconds
Started Jan 24 11:08:46 PM PST 24
Finished Jan 24 11:08:50 PM PST 24
Peak memory 197588 kb
Host smart-4eb95471-3f8f-4408-85e9-281f120b609e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860584057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1860584057
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2805437147
Short name T30
Test name
Test status
Simulation time 49356690 ps
CPU time 0.87 seconds
Started Jan 24 11:08:47 PM PST 24
Finished Jan 24 11:08:50 PM PST 24
Peak memory 193784 kb
Host smart-938d06b5-2d7a-4f88-bdfe-28888969cde6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805437147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.2805437147
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2662363780
Short name T227
Test name
Test status
Simulation time 75624279484 ps
CPU time 44.59 seconds
Started Jan 25 03:55:21 AM PST 24
Finished Jan 25 03:56:12 AM PST 24
Peak memory 183492 kb
Host smart-06e83bb4-d060-4fc2-b3a6-4f466b4daf46
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662363780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2662363780
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3783785381
Short name T528
Test name
Test status
Simulation time 131800260612 ps
CPU time 53.52 seconds
Started Jan 25 03:55:21 AM PST 24
Finished Jan 25 03:56:21 AM PST 24
Peak memory 183496 kb
Host smart-223aa1b3-eed0-449e-a18a-b6b8094f1440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783785381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3783785381
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.235492339
Short name T290
Test name
Test status
Simulation time 216585773782 ps
CPU time 107.78 seconds
Started Jan 25 03:55:21 AM PST 24
Finished Jan 25 03:57:15 AM PST 24
Peak memory 191688 kb
Host smart-8b1ae0af-2d08-45ca-9e75-b4685a13c262
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235492339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.235492339
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.562066939
Short name T591
Test name
Test status
Simulation time 214360597378 ps
CPU time 98.25 seconds
Started Jan 25 03:55:21 AM PST 24
Finished Jan 25 03:57:06 AM PST 24
Peak memory 191732 kb
Host smart-686c8f41-b281-49f4-8ebb-b918132aabef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562066939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.562066939
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.44630784
Short name T610
Test name
Test status
Simulation time 199060931 ps
CPU time 0.68 seconds
Started Jan 25 03:55:18 AM PST 24
Finished Jan 25 03:55:28 AM PST 24
Peak memory 182992 kb
Host smart-1833a861-b31e-4073-8748-715b0a262255
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44630784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.44630784
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.3884060674
Short name T533
Test name
Test status
Simulation time 12944946763 ps
CPU time 135.36 seconds
Started Jan 25 03:55:23 AM PST 24
Finished Jan 25 03:57:44 AM PST 24
Peak memory 198112 kb
Host smart-7e12fb6d-68b8-40ee-bd55-b9111f1fdb76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884060674 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.3884060674
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3294855399
Short name T609
Test name
Test status
Simulation time 126551838783 ps
CPU time 56.49 seconds
Started Jan 25 03:55:22 AM PST 24
Finished Jan 25 03:56:25 AM PST 24
Peak memory 183496 kb
Host smart-5bf82400-23ac-4b8f-9b44-b339735ece85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294855399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3294855399
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.2480734859
Short name T557
Test name
Test status
Simulation time 592625304 ps
CPU time 1.77 seconds
Started Jan 25 03:55:24 AM PST 24
Finished Jan 25 03:55:33 AM PST 24
Peak memory 183180 kb
Host smart-ff2d2de1-984d-45f5-86c3-fa9dc33ea55b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480734859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2480734859
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3863633254
Short name T549
Test name
Test status
Simulation time 739206398 ps
CPU time 3 seconds
Started Jan 25 03:55:45 AM PST 24
Finished Jan 25 03:55:49 AM PST 24
Peak memory 192572 kb
Host smart-73202650-2a62-4762-bb88-29d0967c5f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863633254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3863633254
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1126175126
Short name T17
Test name
Test status
Simulation time 35423002 ps
CPU time 0.75 seconds
Started Jan 25 03:55:37 AM PST 24
Finished Jan 25 03:55:43 AM PST 24
Peak memory 213488 kb
Host smart-99520edd-4676-446c-9a3b-1623362147a8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126175126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1126175126
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3895397185
Short name T108
Test name
Test status
Simulation time 868276422150 ps
CPU time 385.13 seconds
Started Jan 25 03:55:41 AM PST 24
Finished Jan 25 04:02:11 AM PST 24
Peak memory 183448 kb
Host smart-325b46db-800c-40a1-8f68-b51014481955
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895397185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3895397185
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.4149993664
Short name T35
Test name
Test status
Simulation time 212565193448 ps
CPU time 450.99 seconds
Started Jan 25 03:55:34 AM PST 24
Finished Jan 25 04:03:12 AM PST 24
Peak memory 206320 kb
Host smart-478abf1d-4c37-4566-9161-24395591d3c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149993664 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.4149993664
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.1712423263
Short name T219
Test name
Test status
Simulation time 416611610299 ps
CPU time 403.79 seconds
Started Jan 25 03:58:53 AM PST 24
Finished Jan 25 04:05:38 AM PST 24
Peak memory 183448 kb
Host smart-aa657747-f9b4-42d1-a306-e9e7c8a5bdf6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712423263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.1712423263
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3917292024
Short name T595
Test name
Test status
Simulation time 56131091472 ps
CPU time 86.04 seconds
Started Jan 25 03:58:50 AM PST 24
Finished Jan 25 04:00:17 AM PST 24
Peak memory 183516 kb
Host smart-970f661c-93c1-47cb-a322-b97e32a19343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917292024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3917292024
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.524560807
Short name T298
Test name
Test status
Simulation time 18973947974 ps
CPU time 264.54 seconds
Started Jan 25 03:59:00 AM PST 24
Finished Jan 25 04:03:27 AM PST 24
Peak memory 183484 kb
Host smart-ca8b9645-6a85-49cc-a8db-d1632f7b1c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524560807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.524560807
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1412761416
Short name T164
Test name
Test status
Simulation time 20273328632 ps
CPU time 30.54 seconds
Started Jan 25 06:19:04 AM PST 24
Finished Jan 25 06:19:35 AM PST 24
Peak memory 183688 kb
Host smart-98e0021e-9afb-4d46-ac30-7ed381d9f1c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412761416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1412761416
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.4208783249
Short name T554
Test name
Test status
Simulation time 76259367464 ps
CPU time 769.32 seconds
Started Jan 25 03:58:58 AM PST 24
Finished Jan 25 04:11:51 AM PST 24
Peak memory 198252 kb
Host smart-dff6bd38-18ae-4965-a34d-59f5746c9b5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208783249 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.4208783249
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/102.rv_timer_random.3956084032
Short name T608
Test name
Test status
Simulation time 22955610792 ps
CPU time 20 seconds
Started Jan 25 04:10:59 AM PST 24
Finished Jan 25 04:11:20 AM PST 24
Peak memory 183576 kb
Host smart-bffe9e41-8a47-4d5e-8d43-5138d72ffa79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956084032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3956084032
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.2260882471
Short name T582
Test name
Test status
Simulation time 21970917282 ps
CPU time 33.93 seconds
Started Jan 25 04:48:29 AM PST 24
Finished Jan 25 04:49:09 AM PST 24
Peak memory 183504 kb
Host smart-3c51b128-8bc5-4a58-b98f-182b5301a641
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260882471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2260882471
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.2438941620
Short name T157
Test name
Test status
Simulation time 166717110335 ps
CPU time 2290.39 seconds
Started Jan 25 04:10:59 AM PST 24
Finished Jan 25 04:49:11 AM PST 24
Peak memory 194776 kb
Host smart-48f41967-2bbb-41c5-98d1-05849b81a0c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438941620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2438941620
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.3741457176
Short name T538
Test name
Test status
Simulation time 224441654683 ps
CPU time 98.1 seconds
Started Jan 25 04:10:59 AM PST 24
Finished Jan 25 04:12:38 AM PST 24
Peak memory 183548 kb
Host smart-7132c462-42a7-4f30-8f1f-4cd1697b7928
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741457176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3741457176
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.1127504840
Short name T224
Test name
Test status
Simulation time 824033654417 ps
CPU time 556.89 seconds
Started Jan 25 04:11:01 AM PST 24
Finished Jan 25 04:20:19 AM PST 24
Peak memory 191672 kb
Host smart-4822790e-b361-498a-b19a-3ae27b1ccaa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127504840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1127504840
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.1547724204
Short name T348
Test name
Test status
Simulation time 297742446279 ps
CPU time 298.22 seconds
Started Jan 25 04:10:59 AM PST 24
Finished Jan 25 04:15:59 AM PST 24
Peak memory 191728 kb
Host smart-7a8ba6de-6832-455b-a133-e4c97fe46b50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547724204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1547724204
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2825968942
Short name T495
Test name
Test status
Simulation time 131750673240 ps
CPU time 189.36 seconds
Started Jan 25 03:59:00 AM PST 24
Finished Jan 25 04:02:12 AM PST 24
Peak memory 183448 kb
Host smart-b8199b29-463e-4e03-87fc-ffa007a8cfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825968942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2825968942
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.3920279961
Short name T355
Test name
Test status
Simulation time 149492847660 ps
CPU time 927.73 seconds
Started Jan 25 03:59:01 AM PST 24
Finished Jan 25 04:14:30 AM PST 24
Peak memory 191704 kb
Host smart-1664aba3-c7e6-41de-ad32-aa3a7d2c4a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920279961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.3920279961
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.2046783228
Short name T368
Test name
Test status
Simulation time 73458669970 ps
CPU time 961.72 seconds
Started Jan 25 04:20:16 AM PST 24
Finished Jan 25 04:36:18 AM PST 24
Peak memory 211192 kb
Host smart-37eaec3b-dcef-48af-a094-e53d07cba512
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046783228 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.2046783228
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.rv_timer_random.566536877
Short name T204
Test name
Test status
Simulation time 139032351826 ps
CPU time 62.04 seconds
Started Jan 25 04:11:14 AM PST 24
Finished Jan 25 04:12:24 AM PST 24
Peak memory 183552 kb
Host smart-763150cc-56b5-4eaa-b7b4-b17beee3b226
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566536877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.566536877
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.801255075
Short name T147
Test name
Test status
Simulation time 1153219817798 ps
CPU time 377.03 seconds
Started Jan 25 04:11:09 AM PST 24
Finished Jan 25 04:17:39 AM PST 24
Peak memory 193048 kb
Host smart-2266ba75-aefc-4efb-b2c7-b62f11123ca3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801255075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.801255075
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.1036040166
Short name T596
Test name
Test status
Simulation time 20803302358 ps
CPU time 54.31 seconds
Started Jan 25 04:11:10 AM PST 24
Finished Jan 25 04:12:16 AM PST 24
Peak memory 183524 kb
Host smart-4fa9ba0d-746b-4ce2-bdcf-eaca8860e958
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036040166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1036040166
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.154565950
Short name T283
Test name
Test status
Simulation time 240471185950 ps
CPU time 302.67 seconds
Started Jan 25 04:11:35 AM PST 24
Finished Jan 25 04:16:39 AM PST 24
Peak memory 191748 kb
Host smart-b1108492-42ac-4468-a3be-43139e4aa378
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154565950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.154565950
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.665868250
Short name T605
Test name
Test status
Simulation time 38890567336 ps
CPU time 33.61 seconds
Started Jan 25 04:11:31 AM PST 24
Finished Jan 25 04:12:08 AM PST 24
Peak memory 183488 kb
Host smart-40e0db87-b2ce-4112-ad6a-67b9fb0587ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665868250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.665868250
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.2689121655
Short name T140
Test name
Test status
Simulation time 58206540788 ps
CPU time 93.16 seconds
Started Jan 25 04:11:35 AM PST 24
Finished Jan 25 04:13:10 AM PST 24
Peak memory 191704 kb
Host smart-9c138291-266c-4de0-8a63-5a08601ff191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689121655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2689121655
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.2484646227
Short name T126
Test name
Test status
Simulation time 683929780422 ps
CPU time 313.95 seconds
Started Jan 25 04:11:32 AM PST 24
Finished Jan 25 04:16:48 AM PST 24
Peak memory 191748 kb
Host smart-85895c02-f8a3-4b55-b833-cf6eb146f8a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484646227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2484646227
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3311731339
Short name T558
Test name
Test status
Simulation time 135579544754 ps
CPU time 240.21 seconds
Started Jan 25 03:59:01 AM PST 24
Finished Jan 25 04:03:03 AM PST 24
Peak memory 183484 kb
Host smart-3a474ee9-8f3d-4dfe-b888-9e296350e78c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311731339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3311731339
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1832134168
Short name T3
Test name
Test status
Simulation time 168158247056 ps
CPU time 144.09 seconds
Started Jan 25 03:59:00 AM PST 24
Finished Jan 25 04:01:26 AM PST 24
Peak memory 183452 kb
Host smart-88eda81d-8a6b-404f-917c-ec92e5cf69a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832134168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1832134168
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.38420809
Short name T295
Test name
Test status
Simulation time 203368627946 ps
CPU time 440.5 seconds
Started Jan 25 03:58:59 AM PST 24
Finished Jan 25 04:06:22 AM PST 24
Peak memory 191660 kb
Host smart-91b2187a-bc75-4fd0-84c1-39cf0177df42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38420809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.38420809
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1317233928
Short name T165
Test name
Test status
Simulation time 66583268201 ps
CPU time 124.64 seconds
Started Jan 25 04:57:36 AM PST 24
Finished Jan 25 04:59:43 AM PST 24
Peak memory 191708 kb
Host smart-cbe28b5c-32ce-4cfd-b719-8a52743e98f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317233928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1317233928
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.681677235
Short name T603
Test name
Test status
Simulation time 108938116228 ps
CPU time 1049.13 seconds
Started Jan 25 03:59:13 AM PST 24
Finished Jan 25 04:16:43 AM PST 24
Peak memory 209888 kb
Host smart-a4d31fe8-277e-4fa1-bf47-cd6a36e998a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681677235 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.681677235
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/121.rv_timer_random.2871466323
Short name T220
Test name
Test status
Simulation time 259539055091 ps
CPU time 232.12 seconds
Started Jan 25 04:26:26 AM PST 24
Finished Jan 25 04:30:35 AM PST 24
Peak memory 194764 kb
Host smart-e9f2dd51-0e68-40b7-9c93-64fbd90192d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871466323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2871466323
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2746947077
Short name T237
Test name
Test status
Simulation time 84039402267 ps
CPU time 132.17 seconds
Started Jan 25 04:11:57 AM PST 24
Finished Jan 25 04:14:11 AM PST 24
Peak memory 194632 kb
Host smart-c21fd49a-2059-4a47-8adb-773711fa45de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746947077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2746947077
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3941774657
Short name T134
Test name
Test status
Simulation time 134688289727 ps
CPU time 988.92 seconds
Started Jan 25 04:11:51 AM PST 24
Finished Jan 25 04:28:21 AM PST 24
Peak memory 194384 kb
Host smart-23bf925e-4e4d-4f2e-a9de-ffe02cc7658b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941774657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3941774657
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.4234100891
Short name T352
Test name
Test status
Simulation time 109795397307 ps
CPU time 901.85 seconds
Started Jan 25 04:11:52 AM PST 24
Finished Jan 25 04:26:56 AM PST 24
Peak memory 194908 kb
Host smart-a586bd32-ddd3-4ea9-9036-323e0e4af835
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234100891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.4234100891
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.4007898823
Short name T569
Test name
Test status
Simulation time 409380746012 ps
CPU time 595.09 seconds
Started Jan 25 04:11:52 AM PST 24
Finished Jan 25 04:21:49 AM PST 24
Peak memory 191724 kb
Host smart-32deec17-8d41-44e9-99d1-ef6a0db3c1fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007898823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.4007898823
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1428633193
Short name T197
Test name
Test status
Simulation time 68206849614 ps
CPU time 468.9 seconds
Started Jan 25 04:11:54 AM PST 24
Finished Jan 25 04:19:45 AM PST 24
Peak memory 193784 kb
Host smart-9d8b750a-13fb-4748-9b48-5a1202c26233
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428633193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1428633193
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.1385889261
Short name T562
Test name
Test status
Simulation time 47070686101 ps
CPU time 28.61 seconds
Started Jan 25 04:12:10 AM PST 24
Finished Jan 25 04:12:41 AM PST 24
Peak memory 183508 kb
Host smart-99d33020-d252-41c6-8af1-374efaea0c57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385889261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1385889261
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1959158949
Short name T544
Test name
Test status
Simulation time 10343549538 ps
CPU time 18.41 seconds
Started Jan 25 03:59:10 AM PST 24
Finished Jan 25 03:59:30 AM PST 24
Peak memory 183524 kb
Host smart-c1c4bd4b-731e-46b0-85bc-ca0f8a7d99a0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959158949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1959158949
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1371849550
Short name T57
Test name
Test status
Simulation time 32607342481 ps
CPU time 49.9 seconds
Started Jan 25 03:59:15 AM PST 24
Finished Jan 25 04:00:06 AM PST 24
Peak memory 183496 kb
Host smart-6d7ef409-c973-4ca5-b2f2-9ef39a4a3f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371849550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1371849550
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.992884633
Short name T317
Test name
Test status
Simulation time 481881717942 ps
CPU time 466.63 seconds
Started Jan 25 03:59:11 AM PST 24
Finished Jan 25 04:06:58 AM PST 24
Peak memory 191724 kb
Host smart-4c768c73-50cb-4f2b-a6cb-85e34f796316
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992884633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.992884633
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2286555198
Short name T494
Test name
Test status
Simulation time 1015169136 ps
CPU time 1.09 seconds
Started Jan 25 03:59:09 AM PST 24
Finished Jan 25 03:59:12 AM PST 24
Peak memory 183428 kb
Host smart-587025cd-35be-4559-9569-b5934593343f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286555198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2286555198
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.720621384
Short name T524
Test name
Test status
Simulation time 26888088902 ps
CPU time 35.1 seconds
Started Jan 25 03:59:14 AM PST 24
Finished Jan 25 03:59:50 AM PST 24
Peak memory 183500 kb
Host smart-adc13c3e-fd07-4ee8-bb16-8c1fc71d74e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720621384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.
720621384
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/131.rv_timer_random.668476248
Short name T577
Test name
Test status
Simulation time 60679332787 ps
CPU time 373.52 seconds
Started Jan 25 04:12:14 AM PST 24
Finished Jan 25 04:18:36 AM PST 24
Peak memory 191696 kb
Host smart-696b6e5c-0682-4883-b5c8-b43dd7c93c88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668476248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.668476248
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.2838431067
Short name T242
Test name
Test status
Simulation time 231556301071 ps
CPU time 459.97 seconds
Started Jan 25 04:12:22 AM PST 24
Finished Jan 25 04:20:07 AM PST 24
Peak memory 191660 kb
Host smart-7a77e6ab-43d2-4f49-b7c8-e78b274a21ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838431067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2838431067
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2272725957
Short name T162
Test name
Test status
Simulation time 46913808100 ps
CPU time 41.33 seconds
Started Jan 25 04:12:22 AM PST 24
Finished Jan 25 04:13:09 AM PST 24
Peak memory 183420 kb
Host smart-703e9753-0d01-46e5-b69b-a545806d697a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272725957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2272725957
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.4223023601
Short name T312
Test name
Test status
Simulation time 170384570288 ps
CPU time 1143.46 seconds
Started Jan 25 04:12:21 AM PST 24
Finished Jan 25 04:31:31 AM PST 24
Peak memory 193732 kb
Host smart-a35c3a29-794a-42dd-b5aa-f7895e46225b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223023601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.4223023601
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.2169294990
Short name T552
Test name
Test status
Simulation time 20566333457 ps
CPU time 236.56 seconds
Started Jan 25 04:12:22 AM PST 24
Finished Jan 25 04:16:24 AM PST 24
Peak memory 183524 kb
Host smart-e4d3abbf-4e34-4aea-97f5-b9fe498c3a62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169294990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2169294990
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3448869307
Short name T231
Test name
Test status
Simulation time 144387969753 ps
CPU time 245.87 seconds
Started Jan 25 04:12:20 AM PST 24
Finished Jan 25 04:16:33 AM PST 24
Peak memory 191740 kb
Host smart-58d1243a-12f9-4a91-b63b-c8929a5ce1bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448869307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3448869307
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.460831763
Short name T587
Test name
Test status
Simulation time 353073256996 ps
CPU time 1710.38 seconds
Started Jan 25 04:12:20 AM PST 24
Finished Jan 25 04:40:58 AM PST 24
Peak memory 183508 kb
Host smart-ce71a8b0-86e3-45be-bd48-ea7065163b92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460831763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.460831763
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.469894682
Short name T119
Test name
Test status
Simulation time 81274186830 ps
CPU time 79.36 seconds
Started Jan 25 03:59:12 AM PST 24
Finished Jan 25 04:00:32 AM PST 24
Peak memory 183476 kb
Host smart-9050fda5-c341-4c07-ad85-d2c613361025
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469894682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.469894682
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.4143358548
Short name T594
Test name
Test status
Simulation time 207323956696 ps
CPU time 187.42 seconds
Started Jan 25 03:59:18 AM PST 24
Finished Jan 25 04:02:28 AM PST 24
Peak memory 183364 kb
Host smart-c0c3f98e-6daa-4b88-b88f-128184a08ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143358548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.4143358548
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.3178229737
Short name T247
Test name
Test status
Simulation time 81220142957 ps
CPU time 415.48 seconds
Started Jan 25 03:59:16 AM PST 24
Finished Jan 25 04:06:12 AM PST 24
Peak memory 191696 kb
Host smart-c5e3122a-6e4d-4c65-88ad-6b25ef201d9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178229737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3178229737
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3770677246
Short name T200
Test name
Test status
Simulation time 83540545641 ps
CPU time 156.32 seconds
Started Jan 25 03:59:18 AM PST 24
Finished Jan 25 04:01:57 AM PST 24
Peak memory 191704 kb
Host smart-b536ce1d-8fa9-4e9f-ab07-6dca6976ba6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770677246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3770677246
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.607085188
Short name T568
Test name
Test status
Simulation time 2180879444550 ps
CPU time 1199.61 seconds
Started Jan 25 03:59:18 AM PST 24
Finished Jan 25 04:19:20 AM PST 24
Peak memory 213000 kb
Host smart-8a38305e-1b00-4b23-9609-503b9194c00a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607085188 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.607085188
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.1960449819
Short name T280
Test name
Test status
Simulation time 10426018252 ps
CPU time 89.13 seconds
Started Jan 25 04:12:21 AM PST 24
Finished Jan 25 04:13:57 AM PST 24
Peak memory 183484 kb
Host smart-6bb75ff6-c14d-4f30-9c1e-136b6b4d3082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960449819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1960449819
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.1713727908
Short name T182
Test name
Test status
Simulation time 349610498245 ps
CPU time 199.2 seconds
Started Jan 25 04:12:25 AM PST 24
Finished Jan 25 04:15:47 AM PST 24
Peak memory 195396 kb
Host smart-a897292e-01b7-471d-82e5-de4777635162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713727908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1713727908
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.3846978469
Short name T6
Test name
Test status
Simulation time 106102445550 ps
CPU time 67.02 seconds
Started Jan 25 04:12:25 AM PST 24
Finished Jan 25 04:13:36 AM PST 24
Peak memory 183312 kb
Host smart-0e6beea4-1d52-4496-b81e-e82e473b9db0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846978469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3846978469
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3259760785
Short name T44
Test name
Test status
Simulation time 48552658500 ps
CPU time 234.68 seconds
Started Jan 25 04:12:24 AM PST 24
Finished Jan 25 04:16:23 AM PST 24
Peak memory 191696 kb
Host smart-673c6247-9f42-4af4-aa56-185a45ffa269
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259760785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3259760785
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1299934113
Short name T209
Test name
Test status
Simulation time 206053475876 ps
CPU time 442.27 seconds
Started Jan 25 04:12:24 AM PST 24
Finished Jan 25 04:19:50 AM PST 24
Peak memory 194384 kb
Host smart-df05e48b-3be7-42bd-b5f5-ec7477d4e7e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299934113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1299934113
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3768387887
Short name T113
Test name
Test status
Simulation time 57065257207 ps
CPU time 210.28 seconds
Started Jan 25 04:12:23 AM PST 24
Finished Jan 25 04:15:58 AM PST 24
Peak memory 191668 kb
Host smart-1ab2172b-5fbd-4635-b914-413f058c58b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768387887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3768387887
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3975107571
Short name T584
Test name
Test status
Simulation time 41503524818 ps
CPU time 17.14 seconds
Started Jan 25 04:12:22 AM PST 24
Finished Jan 25 04:12:45 AM PST 24
Peak memory 183548 kb
Host smart-74b8f4e5-dd52-474a-9d91-53e039c2c75a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975107571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3975107571
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.4195874185
Short name T331
Test name
Test status
Simulation time 915488914051 ps
CPU time 701.98 seconds
Started Jan 25 03:59:16 AM PST 24
Finished Jan 25 04:10:59 AM PST 24
Peak memory 183476 kb
Host smart-dc853b5a-f9aa-4a06-b75d-6466fc338e45
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195874185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.4195874185
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.3268921590
Short name T508
Test name
Test status
Simulation time 26614587751 ps
CPU time 21.73 seconds
Started Jan 25 03:59:19 AM PST 24
Finished Jan 25 03:59:43 AM PST 24
Peak memory 183536 kb
Host smart-7c6a6ec9-7851-43a0-953e-67c41d7a7674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268921590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3268921590
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3249697663
Short name T324
Test name
Test status
Simulation time 103342142237 ps
CPU time 366.85 seconds
Started Jan 25 05:18:51 AM PST 24
Finished Jan 25 05:25:04 AM PST 24
Peak memory 191844 kb
Host smart-aebc5eeb-6208-45b3-ac7e-a9e081e826da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249697663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3249697663
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1242091786
Short name T246
Test name
Test status
Simulation time 266590310858 ps
CPU time 320.84 seconds
Started Jan 25 03:59:30 AM PST 24
Finished Jan 25 04:04:57 AM PST 24
Peak memory 191704 kb
Host smart-9aaefebe-e296-4020-8610-c77c15d17e50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242091786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1242091786
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.2025036866
Short name T536
Test name
Test status
Simulation time 9069632164 ps
CPU time 108.28 seconds
Started Jan 25 03:59:30 AM PST 24
Finished Jan 25 04:01:19 AM PST 24
Peak memory 198160 kb
Host smart-07311c81-2f0e-42c8-af59-d7c4f8b97d34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025036866 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.2025036866
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.2581765687
Short name T173
Test name
Test status
Simulation time 176016186861 ps
CPU time 190.92 seconds
Started Jan 25 04:12:38 AM PST 24
Finished Jan 25 04:15:50 AM PST 24
Peak memory 191628 kb
Host smart-7ac0a337-1ffd-4a3b-a080-966a0e7fa5f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581765687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.2581765687
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.1263787929
Short name T223
Test name
Test status
Simulation time 231378836620 ps
CPU time 885.2 seconds
Started Jan 25 04:12:38 AM PST 24
Finished Jan 25 04:27:25 AM PST 24
Peak memory 194840 kb
Host smart-69141e84-b7c1-46b5-b2f4-7024fa540266
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263787929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1263787929
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3173192229
Short name T346
Test name
Test status
Simulation time 510227905380 ps
CPU time 242.1 seconds
Started Jan 25 04:13:03 AM PST 24
Finished Jan 25 04:17:06 AM PST 24
Peak memory 191752 kb
Host smart-2f0702b5-37fb-4025-8d52-99f869208b65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173192229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3173192229
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2067630863
Short name T133
Test name
Test status
Simulation time 101581362329 ps
CPU time 1409.58 seconds
Started Jan 25 04:13:04 AM PST 24
Finished Jan 25 04:36:35 AM PST 24
Peak memory 194932 kb
Host smart-b116c2a5-57b7-466f-8d09-7f0a62ac626e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067630863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2067630863
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1995549361
Short name T221
Test name
Test status
Simulation time 243363709323 ps
CPU time 401.45 seconds
Started Jan 25 03:59:29 AM PST 24
Finished Jan 25 04:06:12 AM PST 24
Peak memory 183544 kb
Host smart-542a8599-3345-46be-a8e9-36aa3c093f99
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995549361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1995549361
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.373645599
Short name T500
Test name
Test status
Simulation time 189391752075 ps
CPU time 271.56 seconds
Started Jan 25 03:59:31 AM PST 24
Finished Jan 25 04:04:09 AM PST 24
Peak memory 183516 kb
Host smart-88e32e75-a146-4b96-99f9-dd3f544d140e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373645599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.373645599
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.3485234566
Short name T176
Test name
Test status
Simulation time 254180275855 ps
CPU time 123.94 seconds
Started Jan 25 03:59:32 AM PST 24
Finished Jan 25 04:01:42 AM PST 24
Peak memory 191760 kb
Host smart-250e0620-102f-4058-9b21-db63a3bcf710
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485234566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3485234566
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.3406319768
Short name T540
Test name
Test status
Simulation time 32023526203 ps
CPU time 22.15 seconds
Started Jan 25 03:59:31 AM PST 24
Finished Jan 25 04:00:00 AM PST 24
Peak memory 194160 kb
Host smart-bf36c1b2-87d7-494b-a5be-f8d691c15698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406319768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.3406319768
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2729467203
Short name T371
Test name
Test status
Simulation time 612827209958 ps
CPU time 425.7 seconds
Started Jan 25 03:59:31 AM PST 24
Finished Jan 25 04:06:44 AM PST 24
Peak memory 191708 kb
Host smart-7470c055-c5af-4cb0-b8a7-4e80d9101194
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729467203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2729467203
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.2728728214
Short name T11
Test name
Test status
Simulation time 114552360028 ps
CPU time 258.6 seconds
Started Jan 25 03:59:32 AM PST 24
Finished Jan 25 04:03:57 AM PST 24
Peak memory 198124 kb
Host smart-06b83258-ffe0-405d-a03e-10dbea06cf31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728728214 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.2728728214
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.1747336344
Short name T300
Test name
Test status
Simulation time 283607246385 ps
CPU time 269.67 seconds
Started Jan 25 04:13:26 AM PST 24
Finished Jan 25 04:17:57 AM PST 24
Peak memory 194984 kb
Host smart-f0a55922-b426-474b-8095-5ef126081d79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747336344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1747336344
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.4263445959
Short name T308
Test name
Test status
Simulation time 390263185342 ps
CPU time 230.74 seconds
Started Jan 25 04:13:27 AM PST 24
Finished Jan 25 04:17:18 AM PST 24
Peak memory 194804 kb
Host smart-95c0a7d9-50f7-4814-99d0-dbcb5202d674
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263445959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.4263445959
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.1573162915
Short name T183
Test name
Test status
Simulation time 278195721612 ps
CPU time 256.06 seconds
Started Jan 25 04:13:24 AM PST 24
Finished Jan 25 04:17:41 AM PST 24
Peak memory 191748 kb
Host smart-1e86a297-81ea-4245-9e02-4af207ec1c8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573162915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1573162915
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2427273924
Short name T335
Test name
Test status
Simulation time 147278147881 ps
CPU time 86.29 seconds
Started Jan 25 04:13:24 AM PST 24
Finished Jan 25 04:14:51 AM PST 24
Peak memory 191704 kb
Host smart-4b711e86-6527-4035-bd1d-c1129970ce4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427273924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2427273924
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.127396972
Short name T364
Test name
Test status
Simulation time 146236133721 ps
CPU time 101.32 seconds
Started Jan 25 04:13:22 AM PST 24
Finished Jan 25 04:15:04 AM PST 24
Peak memory 183508 kb
Host smart-292324ba-a5dc-4bce-9cbb-d2739b97fd62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127396972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.127396972
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.453932401
Short name T155
Test name
Test status
Simulation time 171460942307 ps
CPU time 424.47 seconds
Started Jan 25 04:13:25 AM PST 24
Finished Jan 25 04:20:30 AM PST 24
Peak memory 183508 kb
Host smart-19774684-e0f5-4181-bcc5-3ceac33289b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453932401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.453932401
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.2189718422
Short name T527
Test name
Test status
Simulation time 6691659214 ps
CPU time 126.97 seconds
Started Jan 25 04:13:27 AM PST 24
Finished Jan 25 04:15:34 AM PST 24
Peak memory 183484 kb
Host smart-c6051073-d29a-429f-bf96-1bad1c32bad2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189718422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2189718422
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.389698403
Short name T192
Test name
Test status
Simulation time 240667362355 ps
CPU time 230.24 seconds
Started Jan 25 04:13:24 AM PST 24
Finished Jan 25 04:17:15 AM PST 24
Peak memory 194448 kb
Host smart-c1092003-b3ef-4926-9049-1f3c31dfc5d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389698403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.389698403
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.54294958
Short name T351
Test name
Test status
Simulation time 8122626588 ps
CPU time 15.96 seconds
Started Jan 25 03:59:31 AM PST 24
Finished Jan 25 03:59:53 AM PST 24
Peak memory 183508 kb
Host smart-d2c971b1-2382-4cad-a80c-d8d2126be42c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54294958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.rv_timer_cfg_update_on_fly.54294958
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.2575393490
Short name T521
Test name
Test status
Simulation time 216621273938 ps
CPU time 80.12 seconds
Started Jan 25 03:59:40 AM PST 24
Finished Jan 25 04:01:05 AM PST 24
Peak memory 183536 kb
Host smart-b13ae340-cfb8-4182-bb70-998be75cdafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575393490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2575393490
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.1104625574
Short name T189
Test name
Test status
Simulation time 428133440997 ps
CPU time 545.9 seconds
Started Jan 25 03:59:38 AM PST 24
Finished Jan 25 04:08:49 AM PST 24
Peak memory 194072 kb
Host smart-ef4eb531-a0cf-44e7-9299-a895bda77ec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104625574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1104625574
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.2139057944
Short name T323
Test name
Test status
Simulation time 271879498873 ps
CPU time 218.29 seconds
Started Jan 25 03:59:31 AM PST 24
Finished Jan 25 04:03:16 AM PST 24
Peak memory 191728 kb
Host smart-5e56a0aa-76d4-45e1-9e38-39f6b1688cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139057944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2139057944
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.2174144805
Short name T193
Test name
Test status
Simulation time 397082512280 ps
CPU time 907.32 seconds
Started Jan 25 03:59:32 AM PST 24
Finished Jan 25 04:14:46 AM PST 24
Peak memory 209912 kb
Host smart-a1732507-975a-4cb5-a28e-ac23915c3df4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174144805 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.2174144805
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.2971555273
Short name T518
Test name
Test status
Simulation time 50531182404 ps
CPU time 247.54 seconds
Started Jan 25 04:13:37 AM PST 24
Finished Jan 25 04:17:48 AM PST 24
Peak memory 191628 kb
Host smart-1490f70a-25f1-4b5d-8f5c-5b69c842ecba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971555273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2971555273
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.242958707
Short name T249
Test name
Test status
Simulation time 27830776862 ps
CPU time 27.11 seconds
Started Jan 25 04:13:40 AM PST 24
Finished Jan 25 04:14:10 AM PST 24
Peak memory 183488 kb
Host smart-fe46f273-7431-49b0-8d31-66547230a694
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242958707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.242958707
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.257979417
Short name T109
Test name
Test status
Simulation time 107394766465 ps
CPU time 563.81 seconds
Started Jan 25 04:13:36 AM PST 24
Finished Jan 25 04:23:01 AM PST 24
Peak memory 191700 kb
Host smart-0349ed74-fc17-4410-8506-186680815b4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257979417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.257979417
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2637488039
Short name T274
Test name
Test status
Simulation time 2521640492677 ps
CPU time 600.06 seconds
Started Jan 25 04:13:38 AM PST 24
Finished Jan 25 04:23:41 AM PST 24
Peak memory 194612 kb
Host smart-aa784c4a-495b-4d47-8825-2df1e6f38b2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637488039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2637488039
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.1684948240
Short name T252
Test name
Test status
Simulation time 5020256772 ps
CPU time 8.76 seconds
Started Jan 25 04:13:40 AM PST 24
Finished Jan 25 04:13:51 AM PST 24
Peak memory 183548 kb
Host smart-7015a30d-a53b-4032-80d2-af373acf735b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684948240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1684948240
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2373296770
Short name T10
Test name
Test status
Simulation time 88176108587 ps
CPU time 50.98 seconds
Started Jan 25 04:13:41 AM PST 24
Finished Jan 25 04:14:35 AM PST 24
Peak memory 183508 kb
Host smart-c41d8325-9dea-4f98-821a-33f49caaa47c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373296770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2373296770
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3733368202
Short name T130
Test name
Test status
Simulation time 167427093239 ps
CPU time 267.15 seconds
Started Jan 25 03:59:34 AM PST 24
Finished Jan 25 04:04:06 AM PST 24
Peak memory 183472 kb
Host smart-47bbcb8c-9128-4bd0-9fa2-fc016956a504
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733368202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3733368202
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.3907346945
Short name T585
Test name
Test status
Simulation time 485648986015 ps
CPU time 202.25 seconds
Started Jan 25 03:59:35 AM PST 24
Finished Jan 25 04:03:01 AM PST 24
Peak memory 183448 kb
Host smart-1a1b992b-da23-4329-b526-3c6fcd9bdc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907346945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3907346945
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.453314483
Short name T279
Test name
Test status
Simulation time 146022672138 ps
CPU time 1247.21 seconds
Started Jan 25 03:59:34 AM PST 24
Finished Jan 25 04:20:26 AM PST 24
Peak memory 191684 kb
Host smart-041ff6e1-fb8b-4490-8a91-07862c7a376d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453314483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.453314483
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1598704769
Short name T235
Test name
Test status
Simulation time 93528643572 ps
CPU time 105.59 seconds
Started Jan 25 03:59:33 AM PST 24
Finished Jan 25 04:01:24 AM PST 24
Peak memory 183480 kb
Host smart-d0151ef1-6f20-43eb-ac82-c546dda65523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598704769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1598704769
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.3039197106
Short name T255
Test name
Test status
Simulation time 181697648202 ps
CPU time 859.38 seconds
Started Jan 25 03:59:32 AM PST 24
Finished Jan 25 04:13:58 AM PST 24
Peak memory 206352 kb
Host smart-105223f6-58bf-471e-ac9d-ff8a9a527ed5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039197106 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.3039197106
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.3375694256
Short name T359
Test name
Test status
Simulation time 87381687522 ps
CPU time 162.77 seconds
Started Jan 25 04:14:00 AM PST 24
Finished Jan 25 04:16:46 AM PST 24
Peak memory 191732 kb
Host smart-a3371c56-49be-4c3d-b7c4-4173524d4e43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375694256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3375694256
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.4025529525
Short name T205
Test name
Test status
Simulation time 44431894441 ps
CPU time 276.92 seconds
Started Jan 25 04:25:57 AM PST 24
Finished Jan 25 04:30:39 AM PST 24
Peak memory 194296 kb
Host smart-44b41ed0-c5ce-439c-aec6-a23bc8aef7d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025529525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.4025529525
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.3495246452
Short name T115
Test name
Test status
Simulation time 147104731538 ps
CPU time 251.59 seconds
Started Jan 25 04:13:55 AM PST 24
Finished Jan 25 04:18:13 AM PST 24
Peak memory 194340 kb
Host smart-06888277-3ed2-415e-913b-625a34756d87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495246452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3495246452
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3199745012
Short name T150
Test name
Test status
Simulation time 233261307619 ps
CPU time 65.41 seconds
Started Jan 25 04:13:55 AM PST 24
Finished Jan 25 04:15:07 AM PST 24
Peak memory 183528 kb
Host smart-05920204-469a-45f1-b326-6058fb638978
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199745012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3199745012
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.390416580
Short name T136
Test name
Test status
Simulation time 97436453141 ps
CPU time 198.03 seconds
Started Jan 25 04:13:56 AM PST 24
Finished Jan 25 04:17:20 AM PST 24
Peak memory 191748 kb
Host smart-3be15341-cb13-4efd-bcca-afc9c2270279
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390416580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.390416580
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1227130893
Short name T321
Test name
Test status
Simulation time 93937700679 ps
CPU time 131.92 seconds
Started Jan 25 04:13:56 AM PST 24
Finished Jan 25 04:16:14 AM PST 24
Peak memory 191744 kb
Host smart-8729b298-4ef4-4989-9f4a-dfb19aa62ae9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227130893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1227130893
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2720792292
Short name T26
Test name
Test status
Simulation time 1134105340413 ps
CPU time 628.83 seconds
Started Jan 25 04:14:25 AM PST 24
Finished Jan 25 04:24:55 AM PST 24
Peak memory 191708 kb
Host smart-787069d7-6159-4fc6-be43-13c6a4d55783
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720792292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2720792292
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2522914820
Short name T258
Test name
Test status
Simulation time 317406741781 ps
CPU time 189.51 seconds
Started Jan 25 03:59:41 AM PST 24
Finished Jan 25 04:02:55 AM PST 24
Peak memory 183452 kb
Host smart-f13fa615-c9f3-421c-83d7-a38b5dc4d43d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522914820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2522914820
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.2699725248
Short name T580
Test name
Test status
Simulation time 23620915923 ps
CPU time 35.51 seconds
Started Jan 25 03:59:40 AM PST 24
Finished Jan 25 04:00:21 AM PST 24
Peak memory 183488 kb
Host smart-9ecb88ca-90e4-4c6a-aa7f-07631444b765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699725248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2699725248
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.3020634649
Short name T338
Test name
Test status
Simulation time 212378581037 ps
CPU time 401.88 seconds
Started Jan 25 03:59:42 AM PST 24
Finished Jan 25 04:06:28 AM PST 24
Peak memory 191744 kb
Host smart-fda552b6-af2b-47c1-b7a8-525f7935cb51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020634649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3020634649
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.319696915
Short name T47
Test name
Test status
Simulation time 367482452 ps
CPU time 0.85 seconds
Started Jan 25 04:00:42 AM PST 24
Finished Jan 25 04:00:43 AM PST 24
Peak memory 183080 kb
Host smart-47ff63b3-8c5a-4f57-b9d8-d7ccbfcced86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319696915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.319696915
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.3096214577
Short name T506
Test name
Test status
Simulation time 208847425747 ps
CPU time 869.99 seconds
Started Jan 25 04:00:42 AM PST 24
Finished Jan 25 04:15:13 AM PST 24
Peak memory 206276 kb
Host smart-91fb5fed-fcb2-476a-a3dc-907ef3edf0d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096214577 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.3096214577
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.1724633947
Short name T327
Test name
Test status
Simulation time 429949745869 ps
CPU time 192.95 seconds
Started Jan 25 05:26:14 AM PST 24
Finished Jan 25 05:29:31 AM PST 24
Peak memory 183608 kb
Host smart-766546ab-d676-4a33-a969-73730507485b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724633947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1724633947
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.1983254350
Short name T267
Test name
Test status
Simulation time 3384540932 ps
CPU time 4.22 seconds
Started Jan 25 04:14:25 AM PST 24
Finished Jan 25 04:14:31 AM PST 24
Peak memory 191708 kb
Host smart-812e0a7f-0ad7-4140-81c5-5a72a8de6b5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983254350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1983254350
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.1785128220
Short name T217
Test name
Test status
Simulation time 50926033245 ps
CPU time 76.22 seconds
Started Jan 25 04:59:47 AM PST 24
Finished Jan 25 05:01:15 AM PST 24
Peak memory 191756 kb
Host smart-8a2940b8-f45a-4531-831a-f8e94e6aa016
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785128220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1785128220
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.2820043229
Short name T316
Test name
Test status
Simulation time 442975743573 ps
CPU time 399.77 seconds
Started Jan 25 05:08:30 AM PST 24
Finished Jan 25 05:15:15 AM PST 24
Peak memory 194716 kb
Host smart-18964171-f333-4064-978c-f7e69606a10b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820043229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2820043229
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.598837261
Short name T117
Test name
Test status
Simulation time 133211439901 ps
CPU time 479.95 seconds
Started Jan 25 05:26:26 AM PST 24
Finished Jan 25 05:34:29 AM PST 24
Peak memory 191808 kb
Host smart-5acdd38a-78fa-4bf1-9d93-32af8ad2232c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598837261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.598837261
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.401475278
Short name T334
Test name
Test status
Simulation time 133619473629 ps
CPU time 219.87 seconds
Started Jan 25 03:55:38 AM PST 24
Finished Jan 25 03:59:23 AM PST 24
Peak memory 183532 kb
Host smart-6431a062-bb8f-441a-9716-ce3e4c4552ea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401475278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.rv_timer_cfg_update_on_fly.401475278
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.4113680900
Short name T512
Test name
Test status
Simulation time 400322231818 ps
CPU time 174.57 seconds
Started Jan 25 03:55:39 AM PST 24
Finished Jan 25 03:58:37 AM PST 24
Peak memory 183492 kb
Host smart-2cf127a4-4ba0-4465-98f6-ce3db13de203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113680900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.4113680900
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.607134765
Short name T565
Test name
Test status
Simulation time 316580562 ps
CPU time 2.15 seconds
Started Jan 25 03:55:51 AM PST 24
Finished Jan 25 03:55:54 AM PST 24
Peak memory 183288 kb
Host smart-9328b4df-3b45-4801-ae06-7b008926aebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607134765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.607134765
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.184643551
Short name T20
Test name
Test status
Simulation time 36620368 ps
CPU time 0.79 seconds
Started Jan 25 03:55:52 AM PST 24
Finished Jan 25 03:55:53 AM PST 24
Peak memory 213500 kb
Host smart-b9f6cfb1-2ae1-4754-b81a-46d29f8bf340
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184643551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.184643551
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.2409487515
Short name T12
Test name
Test status
Simulation time 345511327749 ps
CPU time 968.34 seconds
Started Jan 25 05:04:11 AM PST 24
Finished Jan 25 05:20:24 AM PST 24
Peak memory 213852 kb
Host smart-26f92f12-87e6-4399-92d0-9918df99f284
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409487515 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.2409487515
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1854621262
Short name T502
Test name
Test status
Simulation time 143314712687 ps
CPU time 198.29 seconds
Started Jan 25 04:00:43 AM PST 24
Finished Jan 25 04:04:02 AM PST 24
Peak memory 183544 kb
Host smart-2ec4d49a-06f6-4b70-935f-30fa795d6c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854621262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1854621262
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.2777561895
Short name T132
Test name
Test status
Simulation time 137850529643 ps
CPU time 393.16 seconds
Started Jan 25 04:00:42 AM PST 24
Finished Jan 25 04:07:16 AM PST 24
Peak memory 191696 kb
Host smart-1c329731-e624-46a9-9cc8-5b751f30f1ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777561895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2777561895
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.4220680697
Short name T514
Test name
Test status
Simulation time 34715985 ps
CPU time 0.56 seconds
Started Jan 25 04:00:55 AM PST 24
Finished Jan 25 04:00:57 AM PST 24
Peak memory 182804 kb
Host smart-3b5a16d6-c9db-41d5-b20a-0310806cfebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220680697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.4220680697
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.3255186815
Short name T507
Test name
Test status
Simulation time 466744484455 ps
CPU time 622.13 seconds
Started Jan 25 04:00:56 AM PST 24
Finished Jan 25 04:11:19 AM PST 24
Peak memory 206920 kb
Host smart-8f63b178-9168-4258-9023-f2d4f04d7ebf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255186815 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.3255186815
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1397477785
Short name T564
Test name
Test status
Simulation time 471642809659 ps
CPU time 171.86 seconds
Started Jan 25 04:00:55 AM PST 24
Finished Jan 25 04:03:48 AM PST 24
Peak memory 183532 kb
Host smart-4e319282-b0d5-433e-acfb-b079b088893e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397477785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1397477785
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.2631564909
Short name T349
Test name
Test status
Simulation time 82728893550 ps
CPU time 15.98 seconds
Started Jan 25 04:01:15 AM PST 24
Finished Jan 25 04:01:32 AM PST 24
Peak memory 183284 kb
Host smart-97561006-095e-47c6-b786-4e542cbeb679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631564909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2631564909
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.4209040846
Short name T31
Test name
Test status
Simulation time 169231283516 ps
CPU time 1984.1 seconds
Started Jan 25 04:01:14 AM PST 24
Finished Jan 25 04:34:19 AM PST 24
Peak memory 210960 kb
Host smart-b239b9c6-16f8-4182-a936-56e32059cb83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209040846 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.4209040846
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1552721987
Short name T259
Test name
Test status
Simulation time 27808202224 ps
CPU time 52.61 seconds
Started Jan 25 04:01:48 AM PST 24
Finished Jan 25 04:02:42 AM PST 24
Peak memory 183520 kb
Host smart-8c5c783c-e991-4e1f-b522-a355439a0855
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552721987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1552721987
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.1846972323
Short name T529
Test name
Test status
Simulation time 92144750317 ps
CPU time 129.44 seconds
Started Jan 25 04:01:37 AM PST 24
Finished Jan 25 04:03:52 AM PST 24
Peak memory 183480 kb
Host smart-1f5974d1-02c1-4a1a-bde2-7a8ab3636867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846972323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1846972323
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.2010130792
Short name T251
Test name
Test status
Simulation time 269839140657 ps
CPU time 602.29 seconds
Started Jan 25 04:01:39 AM PST 24
Finished Jan 25 04:11:45 AM PST 24
Peak memory 194312 kb
Host smart-d5435926-3867-4efc-8334-7f83d742dabe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010130792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2010130792
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2133319293
Short name T532
Test name
Test status
Simulation time 74089309 ps
CPU time 0.63 seconds
Started Jan 25 04:01:43 AM PST 24
Finished Jan 25 04:01:47 AM PST 24
Peak memory 182900 kb
Host smart-145af95c-1fbe-436c-b792-a0dda23f4c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133319293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2133319293
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.3275037335
Short name T170
Test name
Test status
Simulation time 292980831697 ps
CPU time 145.86 seconds
Started Jan 25 04:01:46 AM PST 24
Finished Jan 25 04:04:13 AM PST 24
Peak memory 191696 kb
Host smart-f3393480-2760-464d-a24f-03f6cdf97ba2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275037335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.3275037335
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.252604536
Short name T588
Test name
Test status
Simulation time 146676732199 ps
CPU time 277.06 seconds
Started Jan 25 04:01:45 AM PST 24
Finished Jan 25 04:06:25 AM PST 24
Peak memory 209356 kb
Host smart-c11df63b-9f02-4103-8ea6-7bbd2581d5ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252604536 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.252604536
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.290407133
Short name T322
Test name
Test status
Simulation time 1538152718551 ps
CPU time 692.23 seconds
Started Jan 25 04:01:40 AM PST 24
Finished Jan 25 04:13:15 AM PST 24
Peak memory 183480 kb
Host smart-8b86f894-6c71-4098-85cb-8398c4d400f3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290407133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.290407133
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2957176035
Short name T505
Test name
Test status
Simulation time 8393852781 ps
CPU time 14.58 seconds
Started Jan 25 04:01:46 AM PST 24
Finished Jan 25 04:02:02 AM PST 24
Peak memory 183496 kb
Host smart-279462d4-6e83-4a7a-808f-59bd1c279535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957176035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2957176035
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1523988412
Short name T296
Test name
Test status
Simulation time 137509141015 ps
CPU time 488.23 seconds
Started Jan 25 04:01:49 AM PST 24
Finished Jan 25 04:09:58 AM PST 24
Peak memory 194556 kb
Host smart-71b403a4-16d8-407b-9f46-ff0d8cb025c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523988412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1523988412
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.171477179
Short name T367
Test name
Test status
Simulation time 52682187987 ps
CPU time 94.65 seconds
Started Jan 25 04:01:43 AM PST 24
Finished Jan 25 04:03:22 AM PST 24
Peak memory 183364 kb
Host smart-34b97b2e-9a76-4219-94dc-e57c68a1bf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171477179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.171477179
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3107288491
Short name T28
Test name
Test status
Simulation time 2248160996242 ps
CPU time 2155.85 seconds
Started Jan 25 04:01:45 AM PST 24
Finished Jan 25 04:37:44 AM PST 24
Peak memory 191628 kb
Host smart-18ed9260-e601-4a0c-b033-cdcec7bf7d30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107288491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3107288491
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.3390230459
Short name T232
Test name
Test status
Simulation time 216695719813 ps
CPU time 573.3 seconds
Started Jan 25 04:01:45 AM PST 24
Finished Jan 25 04:11:21 AM PST 24
Peak memory 206364 kb
Host smart-22e36e38-0c1d-43b7-8ce4-21c3389522ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390230459 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.3390230459
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3597363641
Short name T27
Test name
Test status
Simulation time 900815934229 ps
CPU time 828.12 seconds
Started Jan 25 04:01:39 AM PST 24
Finished Jan 25 04:15:31 AM PST 24
Peak memory 183528 kb
Host smart-2b0089ca-845a-43a3-856b-7c7761e5ef18
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597363641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3597363641
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.4083040067
Short name T5
Test name
Test status
Simulation time 102815841005 ps
CPU time 160.61 seconds
Started Jan 25 04:01:38 AM PST 24
Finished Jan 25 04:04:23 AM PST 24
Peak memory 183480 kb
Host smart-bae0c109-6d88-4c2d-b28e-d03c5ffe8297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083040067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.4083040067
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2079245081
Short name T511
Test name
Test status
Simulation time 188862779 ps
CPU time 0.87 seconds
Started Jan 25 04:01:39 AM PST 24
Finished Jan 25 04:01:44 AM PST 24
Peak memory 183184 kb
Host smart-f56dd9c7-c060-4497-9ea0-be16ac25d1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079245081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2079245081
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.2209661806
Short name T516
Test name
Test status
Simulation time 1497173351313 ps
CPU time 745.66 seconds
Started Jan 25 04:01:57 AM PST 24
Finished Jan 25 04:14:26 AM PST 24
Peak memory 208352 kb
Host smart-6779515d-b144-4138-baa1-5c490c54eb1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209661806 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.2209661806
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2289367508
Short name T144
Test name
Test status
Simulation time 844721663571 ps
CPU time 501.82 seconds
Started Jan 25 04:02:27 AM PST 24
Finished Jan 25 04:10:49 AM PST 24
Peak memory 183512 kb
Host smart-d36b28ae-0a76-4faa-95a6-c79741cb78d8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289367508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2289367508
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.3917861317
Short name T607
Test name
Test status
Simulation time 672384430 ps
CPU time 1.07 seconds
Started Jan 25 04:01:54 AM PST 24
Finished Jan 25 04:02:01 AM PST 24
Peak memory 183152 kb
Host smart-066f3760-09f5-47b8-a555-df3523da7da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917861317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3917861317
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.735460957
Short name T539
Test name
Test status
Simulation time 510475210182 ps
CPU time 404.13 seconds
Started Jan 25 04:02:00 AM PST 24
Finished Jan 25 04:08:45 AM PST 24
Peak memory 191752 kb
Host smart-265415f8-d0df-4356-b04d-e943d94776a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735460957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.735460957
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.2710574194
Short name T555
Test name
Test status
Simulation time 3357342004 ps
CPU time 5.82 seconds
Started Jan 25 04:02:28 AM PST 24
Finished Jan 25 04:02:35 AM PST 24
Peak memory 183524 kb
Host smart-17ccb5ef-a8f9-4ab8-adfa-e0ac47dff7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710574194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2710574194
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2227498696
Short name T212
Test name
Test status
Simulation time 417872527705 ps
CPU time 639.77 seconds
Started Jan 25 04:02:31 AM PST 24
Finished Jan 25 04:13:12 AM PST 24
Peak memory 191728 kb
Host smart-3a9f6c7a-3ef5-4e2f-a6c6-cbd56b399b94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227498696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2227498696
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.4222575893
Short name T576
Test name
Test status
Simulation time 825212774391 ps
CPU time 641.86 seconds
Started Jan 25 04:02:27 AM PST 24
Finished Jan 25 04:13:10 AM PST 24
Peak memory 209240 kb
Host smart-5ca233f3-b097-42c7-96bc-4452c742c600
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222575893 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.4222575893
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.4237038152
Short name T332
Test name
Test status
Simulation time 13004465653 ps
CPU time 13.9 seconds
Started Jan 25 04:02:27 AM PST 24
Finished Jan 25 04:02:42 AM PST 24
Peak memory 183468 kb
Host smart-f49c2d74-0024-466e-803e-6f458a2796eb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237038152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.4237038152
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.1081954190
Short name T535
Test name
Test status
Simulation time 600006963499 ps
CPU time 251.2 seconds
Started Jan 25 04:02:36 AM PST 24
Finished Jan 25 04:06:48 AM PST 24
Peak memory 183496 kb
Host smart-c53b446e-3fae-48a8-a04b-824512fea603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081954190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1081954190
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3641578814
Short name T291
Test name
Test status
Simulation time 611135645921 ps
CPU time 84.38 seconds
Started Jan 25 04:02:28 AM PST 24
Finished Jan 25 04:03:54 AM PST 24
Peak memory 195532 kb
Host smart-d856fe0c-0804-47bd-9855-3ecb7cdefe52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641578814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3641578814
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.4065342044
Short name T530
Test name
Test status
Simulation time 70183797714 ps
CPU time 326.6 seconds
Started Jan 25 04:03:00 AM PST 24
Finished Jan 25 04:08:27 AM PST 24
Peak memory 198160 kb
Host smart-7c517bb8-e705-4b75-838b-509ba38be1c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065342044 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.4065342044
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.4134089474
Short name T123
Test name
Test status
Simulation time 551155931246 ps
CPU time 899.38 seconds
Started Jan 25 04:02:53 AM PST 24
Finished Jan 25 04:17:57 AM PST 24
Peak memory 183452 kb
Host smart-2cb01bf0-a81e-4616-9d1a-0002fa3115aa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134089474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.4134089474
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2476290494
Short name T556
Test name
Test status
Simulation time 72106266010 ps
CPU time 32.6 seconds
Started Jan 25 04:02:50 AM PST 24
Finished Jan 25 04:03:29 AM PST 24
Peak memory 183516 kb
Host smart-b852e098-86ed-4374-9d5d-ea16e09b4b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476290494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2476290494
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.1128044929
Short name T285
Test name
Test status
Simulation time 40997769047 ps
CPU time 67.3 seconds
Started Jan 25 04:02:53 AM PST 24
Finished Jan 25 04:04:05 AM PST 24
Peak memory 193728 kb
Host smart-e41ed8ad-ae48-4f6c-a8ca-0617cabf3075
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128044929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1128044929
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.1120034901
Short name T570
Test name
Test status
Simulation time 112837930 ps
CPU time 0.75 seconds
Started Jan 25 04:02:50 AM PST 24
Finished Jan 25 04:02:54 AM PST 24
Peak memory 183184 kb
Host smart-9453c0d9-3e02-4157-9b66-3cf670fc5ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120034901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1120034901
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.1652505521
Short name T590
Test name
Test status
Simulation time 522637403613 ps
CPU time 803.17 seconds
Started Jan 25 04:02:52 AM PST 24
Finished Jan 25 04:16:20 AM PST 24
Peak memory 191720 kb
Host smart-53e45f9e-5140-4c32-a87c-7ef42b68f81d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652505521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.1652505521
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.2038974317
Short name T138
Test name
Test status
Simulation time 210557457429 ps
CPU time 1048.09 seconds
Started Jan 25 04:02:53 AM PST 24
Finished Jan 25 04:20:26 AM PST 24
Peak memory 213888 kb
Host smart-a6576e8a-27a5-450d-8d35-bc88445e4ba6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038974317 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.2038974317
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1330807976
Short name T614
Test name
Test status
Simulation time 2677068748891 ps
CPU time 868.34 seconds
Started Jan 25 04:03:00 AM PST 24
Finished Jan 25 04:17:29 AM PST 24
Peak memory 183496 kb
Host smart-42096a85-0262-4903-8dee-64b0f6a746e8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330807976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1330807976
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.314283181
Short name T513
Test name
Test status
Simulation time 248638531983 ps
CPU time 182.71 seconds
Started Jan 25 04:02:51 AM PST 24
Finished Jan 25 04:05:59 AM PST 24
Peak memory 183544 kb
Host smart-63277bb4-4368-46c3-acf0-f5f8c53e0ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314283181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.314283181
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2544583429
Short name T597
Test name
Test status
Simulation time 127030083535 ps
CPU time 219 seconds
Started Jan 25 04:02:51 AM PST 24
Finished Jan 25 04:06:36 AM PST 24
Peak memory 191600 kb
Host smart-9f599479-b73f-459d-aa17-df36a2358df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544583429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2544583429
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.33938846
Short name T196
Test name
Test status
Simulation time 366200971706 ps
CPU time 629.05 seconds
Started Jan 25 04:02:50 AM PST 24
Finished Jan 25 04:13:22 AM PST 24
Peak memory 191716 kb
Host smart-7e0f3359-9ecd-4f5e-bf4d-a67018228760
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33938846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.33938846
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.2516488025
Short name T509
Test name
Test status
Simulation time 361667473787 ps
CPU time 1020.78 seconds
Started Jan 25 04:02:53 AM PST 24
Finished Jan 25 04:19:59 AM PST 24
Peak memory 214536 kb
Host smart-1fa33e8d-b912-497a-a3c6-519d1298b513
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516488025 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.2516488025
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.84400298
Short name T103
Test name
Test status
Simulation time 286994940116 ps
CPU time 464.41 seconds
Started Jan 25 04:03:13 AM PST 24
Finished Jan 25 04:11:03 AM PST 24
Peak memory 183516 kb
Host smart-e354a58b-ce8a-416d-8a8e-35b13e2bfc2d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84400298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.rv_timer_cfg_update_on_fly.84400298
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.3609740948
Short name T379
Test name
Test status
Simulation time 67768276480 ps
CPU time 55.89 seconds
Started Jan 25 04:03:11 AM PST 24
Finished Jan 25 04:04:11 AM PST 24
Peak memory 183452 kb
Host smart-c9e6c04d-5a37-46ad-8e35-2bfbebfdfafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609740948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.3609740948
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.1057486478
Short name T353
Test name
Test status
Simulation time 43010379327 ps
CPU time 79.39 seconds
Started Jan 25 04:03:12 AM PST 24
Finished Jan 25 04:04:34 AM PST 24
Peak memory 191712 kb
Host smart-90f26804-c100-43a3-ade8-18d387778e53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057486478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1057486478
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.3672883432
Short name T240
Test name
Test status
Simulation time 195231776359 ps
CPU time 168.65 seconds
Started Jan 25 04:03:11 AM PST 24
Finished Jan 25 04:06:04 AM PST 24
Peak memory 194120 kb
Host smart-d6538a54-3e59-45e0-9e98-d71b02c6d4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672883432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3672883432
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.2893636043
Short name T501
Test name
Test status
Simulation time 444779177537 ps
CPU time 422.68 seconds
Started Jan 25 04:03:08 AM PST 24
Finished Jan 25 04:10:16 AM PST 24
Peak memory 206320 kb
Host smart-db4b2d1f-260e-4f53-b291-4f288b57755e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893636043 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.2893636043
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.859367853
Short name T48
Test name
Test status
Simulation time 467502351615 ps
CPU time 767.65 seconds
Started Jan 25 04:26:27 AM PST 24
Finished Jan 25 04:39:30 AM PST 24
Peak memory 183520 kb
Host smart-92a74369-23ff-48fa-a7b1-a0d7117dc44e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859367853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.859367853
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.814225574
Short name T548
Test name
Test status
Simulation time 270624167029 ps
CPU time 180.49 seconds
Started Jan 25 03:55:50 AM PST 24
Finished Jan 25 03:58:52 AM PST 24
Peak memory 183504 kb
Host smart-59c1ee74-100d-4bc4-b1e9-b1a0b3202311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814225574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.814225574
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.4222753061
Short name T135
Test name
Test status
Simulation time 173631200764 ps
CPU time 346.57 seconds
Started Jan 25 03:55:51 AM PST 24
Finished Jan 25 04:01:38 AM PST 24
Peak memory 195312 kb
Host smart-1af2e3c2-0c0c-4e20-9e63-0703e1fa1325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222753061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.4222753061
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2441626300
Short name T19
Test name
Test status
Simulation time 109240105 ps
CPU time 0.8 seconds
Started Jan 25 03:55:50 AM PST 24
Finished Jan 25 03:55:52 AM PST 24
Peak memory 213452 kb
Host smart-c9eedd06-de3f-4e40-b93f-59a7f9c9cba6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441626300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2441626300
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.560801210
Short name T320
Test name
Test status
Simulation time 690149256131 ps
CPU time 1589.57 seconds
Started Jan 25 05:28:09 AM PST 24
Finished Jan 25 05:54:41 AM PST 24
Peak memory 191828 kb
Host smart-05239805-6c51-410e-8767-b94ad8989096
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560801210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.560801210
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.1161425848
Short name T194
Test name
Test status
Simulation time 58537428553 ps
CPU time 662.42 seconds
Started Jan 25 03:55:49 AM PST 24
Finished Jan 25 04:06:53 AM PST 24
Peak memory 206368 kb
Host smart-8d0fb138-706a-4f7f-b53b-e7758496a31e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161425848 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.1161425848
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2418803055
Short name T523
Test name
Test status
Simulation time 321150580530 ps
CPU time 147.74 seconds
Started Jan 25 04:03:10 AM PST 24
Finished Jan 25 04:05:42 AM PST 24
Peak memory 183448 kb
Host smart-0679d95e-2756-4c07-ae36-0fe37796b842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418803055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2418803055
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2380455911
Short name T110
Test name
Test status
Simulation time 12174720555 ps
CPU time 21.11 seconds
Started Jan 25 04:03:11 AM PST 24
Finished Jan 25 04:03:36 AM PST 24
Peak memory 183548 kb
Host smart-a78a9e76-e2b1-48c5-bf72-48fb392fb766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380455911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2380455911
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2468301669
Short name T492
Test name
Test status
Simulation time 8454587454 ps
CPU time 16.07 seconds
Started Jan 25 04:03:28 AM PST 24
Finished Jan 25 04:03:45 AM PST 24
Peak memory 183420 kb
Host smart-94862f97-d34a-41c0-b602-c3a5ab839a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468301669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2468301669
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.3667093014
Short name T340
Test name
Test status
Simulation time 581845505415 ps
CPU time 802.67 seconds
Started Jan 25 04:58:44 AM PST 24
Finished Jan 25 05:12:08 AM PST 24
Peak memory 191760 kb
Host smart-d2dabc88-2d28-4e7d-aac3-dda775c673df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667093014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.3667093014
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.4057778069
Short name T571
Test name
Test status
Simulation time 37992234907 ps
CPU time 291.68 seconds
Started Jan 25 04:03:27 AM PST 24
Finished Jan 25 04:08:21 AM PST 24
Peak memory 206308 kb
Host smart-d53b73fb-80f3-4ede-ac18-42c51302890d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057778069 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.4057778069
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3190544681
Short name T493
Test name
Test status
Simulation time 565124434876 ps
CPU time 177.62 seconds
Started Jan 25 04:25:28 AM PST 24
Finished Jan 25 04:28:28 AM PST 24
Peak memory 183504 kb
Host smart-0e351462-a764-4ee4-ab7c-9cecd664f5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190544681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3190544681
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.4021208388
Short name T294
Test name
Test status
Simulation time 895571431196 ps
CPU time 778.67 seconds
Started Jan 25 04:03:45 AM PST 24
Finished Jan 25 04:16:45 AM PST 24
Peak memory 183420 kb
Host smart-da3163ff-416c-4abc-a019-1ba6bccedb3c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021208388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.4021208388
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2220996328
Short name T563
Test name
Test status
Simulation time 92364268179 ps
CPU time 130.29 seconds
Started Jan 25 04:03:47 AM PST 24
Finished Jan 25 04:05:59 AM PST 24
Peak memory 183416 kb
Host smart-0d43a139-5dea-4b30-a2f6-94fe1d4b6a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220996328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2220996328
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.4090127074
Short name T328
Test name
Test status
Simulation time 318636387652 ps
CPU time 109.01 seconds
Started Jan 25 04:03:44 AM PST 24
Finished Jan 25 04:05:33 AM PST 24
Peak memory 191684 kb
Host smart-5b82468a-5ff5-409a-9a44-3fe2dd89bc34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090127074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.4090127074
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.429399069
Short name T545
Test name
Test status
Simulation time 386534763 ps
CPU time 0.67 seconds
Started Jan 25 04:04:04 AM PST 24
Finished Jan 25 04:04:06 AM PST 24
Peak memory 183156 kb
Host smart-ed2381c8-4a21-4b69-8250-a6bf5699ef57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429399069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.429399069
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.989127585
Short name T370
Test name
Test status
Simulation time 120280035423 ps
CPU time 749.48 seconds
Started Jan 25 04:04:04 AM PST 24
Finished Jan 25 04:16:34 AM PST 24
Peak memory 208924 kb
Host smart-a70b8a8b-0635-4f60-a768-f757616ddfab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989127585 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.989127585
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.31257524
Short name T489
Test name
Test status
Simulation time 190835075697 ps
CPU time 81.19 seconds
Started Jan 25 04:04:01 AM PST 24
Finished Jan 25 04:05:24 AM PST 24
Peak memory 183452 kb
Host smart-e7882b9a-c309-49c7-9ce7-6461e77c3589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31257524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.31257524
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.2766218427
Short name T377
Test name
Test status
Simulation time 9081389059 ps
CPU time 15.81 seconds
Started Jan 25 05:20:16 AM PST 24
Finished Jan 25 05:20:33 AM PST 24
Peak memory 191812 kb
Host smart-85aaf68e-20ca-4d0f-b12e-d540723246c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766218427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2766218427
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2865562414
Short name T269
Test name
Test status
Simulation time 236541942129 ps
CPU time 94.41 seconds
Started Jan 25 04:04:03 AM PST 24
Finished Jan 25 04:05:38 AM PST 24
Peak memory 194172 kb
Host smart-143e6400-9cb0-4347-9235-4808ac44710b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865562414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2865562414
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.1151689649
Short name T369
Test name
Test status
Simulation time 119579796781 ps
CPU time 676.17 seconds
Started Jan 25 04:04:06 AM PST 24
Finished Jan 25 04:15:24 AM PST 24
Peak memory 206404 kb
Host smart-0e722b0b-993a-4518-8133-a503706494ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151689649 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.1151689649
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2568894658
Short name T336
Test name
Test status
Simulation time 503329398853 ps
CPU time 287.23 seconds
Started Jan 25 04:04:22 AM PST 24
Finished Jan 25 04:09:10 AM PST 24
Peak memory 183508 kb
Host smart-da8eb035-ee31-4a25-9ef5-133f2ed1270a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568894658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2568894658
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_random.2447128962
Short name T241
Test name
Test status
Simulation time 89137599511 ps
CPU time 320.11 seconds
Started Jan 25 04:04:03 AM PST 24
Finished Jan 25 04:09:24 AM PST 24
Peak memory 191732 kb
Host smart-33634da5-6688-4f00-9660-d010141d23e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447128962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2447128962
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2602754392
Short name T45
Test name
Test status
Simulation time 31993291119 ps
CPU time 16.56 seconds
Started Jan 25 04:04:22 AM PST 24
Finished Jan 25 04:04:40 AM PST 24
Peak memory 194940 kb
Host smart-5f81a4ef-e50d-4c16-ac88-a27181ea82d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602754392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2602754392
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1765538528
Short name T260
Test name
Test status
Simulation time 505653835925 ps
CPU time 240.26 seconds
Started Jan 25 04:04:24 AM PST 24
Finished Jan 25 04:08:25 AM PST 24
Peak memory 191660 kb
Host smart-9a9b44e5-b9a4-4804-8ee3-e250bea730fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765538528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1765538528
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.510768290
Short name T531
Test name
Test status
Simulation time 121959780365 ps
CPU time 543.71 seconds
Started Jan 25 04:04:23 AM PST 24
Finished Jan 25 04:13:28 AM PST 24
Peak memory 208028 kb
Host smart-da440f83-34b2-4cdb-a9b9-63bc90b0143a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510768290 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.510768290
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3340709323
Short name T560
Test name
Test status
Simulation time 112157019567 ps
CPU time 41.72 seconds
Started Jan 25 04:04:23 AM PST 24
Finished Jan 25 04:05:06 AM PST 24
Peak memory 183472 kb
Host smart-9713be3b-efe4-431b-b5b7-c5a62a9ce02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340709323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3340709323
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.862245804
Short name T243
Test name
Test status
Simulation time 250286086978 ps
CPU time 278.03 seconds
Started Jan 25 04:04:48 AM PST 24
Finished Jan 25 04:09:29 AM PST 24
Peak memory 191748 kb
Host smart-caa41304-d5a2-4a0c-9d2e-a88baabbbbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862245804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.862245804
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2703138283
Short name T210
Test name
Test status
Simulation time 212778343948 ps
CPU time 157.88 seconds
Started Jan 25 04:04:52 AM PST 24
Finished Jan 25 04:07:38 AM PST 24
Peak memory 183400 kb
Host smart-665542ec-d5e2-4791-a4ff-b58014d1f9e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703138283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2703138283
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.1940644227
Short name T550
Test name
Test status
Simulation time 263539627059 ps
CPU time 619.07 seconds
Started Jan 25 04:04:49 AM PST 24
Finished Jan 25 04:15:16 AM PST 24
Peak memory 214456 kb
Host smart-6b643a1f-13c0-4da4-b9c2-fd6a476a09a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940644227 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.1940644227
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1459747595
Short name T600
Test name
Test status
Simulation time 68836668998 ps
CPU time 95.75 seconds
Started Jan 25 04:04:53 AM PST 24
Finished Jan 25 04:06:36 AM PST 24
Peak memory 183444 kb
Host smart-72af9432-d3e4-4f85-a5d4-e29d6727ffa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459747595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1459747595
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.3261295249
Short name T347
Test name
Test status
Simulation time 16905900473 ps
CPU time 31.65 seconds
Started Jan 25 04:04:50 AM PST 24
Finished Jan 25 04:05:29 AM PST 24
Peak memory 183480 kb
Host smart-be9ae6f4-580f-49d4-87ac-9eacb872d9b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261295249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3261295249
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3833727194
Short name T593
Test name
Test status
Simulation time 74816088 ps
CPU time 0.84 seconds
Started Jan 25 04:04:49 AM PST 24
Finished Jan 25 04:04:57 AM PST 24
Peak memory 191716 kb
Host smart-0fa55cc1-36dd-440a-b6ca-378e312fb6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833727194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3833727194
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.3022046038
Short name T490
Test name
Test status
Simulation time 330687786821 ps
CPU time 875.08 seconds
Started Jan 25 05:42:34 AM PST 24
Finished Jan 25 05:57:10 AM PST 24
Peak memory 212372 kb
Host smart-a48fc972-d3b1-4ac3-991e-62e25f2ef943
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022046038 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.3022046038
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1075914270
Short name T578
Test name
Test status
Simulation time 287558713870 ps
CPU time 461.91 seconds
Started Jan 25 04:05:18 AM PST 24
Finished Jan 25 04:13:04 AM PST 24
Peak memory 183452 kb
Host smart-8711d34f-928b-4cf7-b147-13070280d549
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075914270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1075914270
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.3737574005
Short name T546
Test name
Test status
Simulation time 49404368648 ps
CPU time 37.94 seconds
Started Jan 25 04:43:37 AM PST 24
Finished Jan 25 04:44:49 AM PST 24
Peak memory 183504 kb
Host smart-25fb3d06-ffaf-4b27-bcbb-b4ce64b4b89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737574005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3737574005
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.339095160
Short name T139
Test name
Test status
Simulation time 238763036609 ps
CPU time 406.49 seconds
Started Jan 25 04:05:19 AM PST 24
Finished Jan 25 04:12:09 AM PST 24
Peak memory 191660 kb
Host smart-8feb8683-8357-403d-94c7-1d4e17a31b1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339095160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.339095160
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3851944150
Short name T561
Test name
Test status
Simulation time 1366219763 ps
CPU time 1.43 seconds
Started Jan 25 04:05:19 AM PST 24
Finished Jan 25 04:05:24 AM PST 24
Peak memory 183400 kb
Host smart-1abd7dab-819f-48eb-b294-63a022bb22e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851944150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3851944150
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.4264560648
Short name T613
Test name
Test status
Simulation time 38264569579 ps
CPU time 350.08 seconds
Started Jan 25 04:05:17 AM PST 24
Finished Jan 25 04:11:12 AM PST 24
Peak memory 206364 kb
Host smart-c160a437-d363-4a8a-810e-a260aa4f3bfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264560648 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.4264560648
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1759382083
Short name T542
Test name
Test status
Simulation time 193765976821 ps
CPU time 365.58 seconds
Started Jan 25 04:05:18 AM PST 24
Finished Jan 25 04:11:28 AM PST 24
Peak memory 183344 kb
Host smart-623768ea-ea2b-452c-9fb6-d793e1485a83
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759382083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1759382083
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.37400595
Short name T497
Test name
Test status
Simulation time 91086773394 ps
CPU time 130.59 seconds
Started Jan 25 04:05:18 AM PST 24
Finished Jan 25 04:07:33 AM PST 24
Peak memory 183220 kb
Host smart-c24d534f-d2c0-492d-8906-8dc6a7ec3f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37400595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.37400595
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.243057288
Short name T372
Test name
Test status
Simulation time 89363358494 ps
CPU time 94.88 seconds
Started Jan 25 04:05:17 AM PST 24
Finished Jan 25 04:06:57 AM PST 24
Peak memory 191732 kb
Host smart-b235b103-ca5c-4e80-b248-98169b3157d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243057288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.243057288
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.4112703342
Short name T522
Test name
Test status
Simulation time 26084078 ps
CPU time 0.6 seconds
Started Jan 25 04:05:18 AM PST 24
Finished Jan 25 04:05:23 AM PST 24
Peak memory 182828 kb
Host smart-cea5b973-0961-429e-aaea-15bc0351a98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112703342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.4112703342
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.2463175356
Short name T234
Test name
Test status
Simulation time 340828530261 ps
CPU time 891.34 seconds
Started Jan 25 07:17:47 AM PST 24
Finished Jan 25 07:32:44 AM PST 24
Peak memory 195960 kb
Host smart-e61e46ef-1b06-4fd1-856d-f2a8f1ab1dec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463175356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.2463175356
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.4285749468
Short name T525
Test name
Test status
Simulation time 464230020208 ps
CPU time 401.14 seconds
Started Jan 25 04:05:18 AM PST 24
Finished Jan 25 04:12:03 AM PST 24
Peak memory 206308 kb
Host smart-c63b6c46-9ba2-4ddb-a76a-1fa667326740
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285749468 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.4285749468
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.1393670301
Short name T2
Test name
Test status
Simulation time 35338351252 ps
CPU time 20.5 seconds
Started Jan 25 04:06:04 AM PST 24
Finished Jan 25 04:06:26 AM PST 24
Peak memory 183468 kb
Host smart-0c602e95-f5e9-467f-a7f8-1491abab87a8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393670301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.1393670301
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3955726127
Short name T498
Test name
Test status
Simulation time 72489810943 ps
CPU time 105.72 seconds
Started Jan 25 04:06:02 AM PST 24
Finished Jan 25 04:07:48 AM PST 24
Peak memory 183464 kb
Host smart-93433e8f-a203-4b4e-8815-82351c3b3dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955726127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3955726127
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3945309029
Short name T519
Test name
Test status
Simulation time 387054533 ps
CPU time 0.77 seconds
Started Jan 25 04:06:04 AM PST 24
Finished Jan 25 04:06:05 AM PST 24
Peak memory 191456 kb
Host smart-f2485d08-4416-4353-965d-bd5001f38d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945309029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3945309029
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.3152485999
Short name T510
Test name
Test status
Simulation time 295352132678 ps
CPU time 1091.1 seconds
Started Jan 25 04:06:03 AM PST 24
Finished Jan 25 04:24:16 AM PST 24
Peak memory 207908 kb
Host smart-a6563df2-f978-4964-9b47-4b73775befbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152485999 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.3152485999
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.951190430
Short name T330
Test name
Test status
Simulation time 1011134110644 ps
CPU time 868.2 seconds
Started Jan 25 03:56:06 AM PST 24
Finished Jan 25 04:10:46 AM PST 24
Peak memory 183480 kb
Host smart-90122c84-b73b-4cf3-be04-bdd74037ad8f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951190430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.rv_timer_cfg_update_on_fly.951190430
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.413900629
Short name T604
Test name
Test status
Simulation time 161805769633 ps
CPU time 248.35 seconds
Started Jan 25 03:56:12 AM PST 24
Finished Jan 25 04:00:27 AM PST 24
Peak memory 183452 kb
Host smart-2fbc2702-909f-46f4-bf6b-27ab94b4009c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413900629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.413900629
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.947655740
Short name T158
Test name
Test status
Simulation time 85137604136 ps
CPU time 170.7 seconds
Started Jan 25 03:55:49 AM PST 24
Finished Jan 25 03:58:41 AM PST 24
Peak memory 194304 kb
Host smart-6d718a1b-61b6-4b10-b7da-33aa8a983228
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947655740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.947655740
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.1139033391
Short name T14
Test name
Test status
Simulation time 131732620 ps
CPU time 0.74 seconds
Started Jan 25 03:56:20 AM PST 24
Finished Jan 25 03:56:29 AM PST 24
Peak memory 213488 kb
Host smart-244e9870-ee8e-4595-be0b-0f00afc1c74f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139033391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1139033391
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3104318726
Short name T105
Test name
Test status
Simulation time 2686174165396 ps
CPU time 1403.38 seconds
Started Jan 25 03:56:21 AM PST 24
Finished Jan 25 04:19:52 AM PST 24
Peak memory 191700 kb
Host smart-a7193db4-0481-43ec-9292-87cbbf4a0d6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104318726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3104318726
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.2022823551
Short name T515
Test name
Test status
Simulation time 453162323441 ps
CPU time 1135.43 seconds
Started Jan 25 03:56:29 AM PST 24
Finished Jan 25 04:15:28 AM PST 24
Peak memory 213584 kb
Host smart-03f46ef2-9809-4643-b385-f204095f3e9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022823551 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.2022823551
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.3145929989
Short name T378
Test name
Test status
Simulation time 246497274470 ps
CPU time 96.13 seconds
Started Jan 25 04:06:06 AM PST 24
Finished Jan 25 04:07:43 AM PST 24
Peak memory 183540 kb
Host smart-85389b1c-5262-4fc9-a5a4-0eaa5d862dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145929989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.3145929989
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3133603148
Short name T1
Test name
Test status
Simulation time 399304217287 ps
CPU time 271.54 seconds
Started Jan 25 04:06:03 AM PST 24
Finished Jan 25 04:10:36 AM PST 24
Peak memory 191772 kb
Host smart-3b8939bc-ad44-4abb-a53f-6c7dc70204e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133603148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3133603148
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.526734914
Short name T304
Test name
Test status
Simulation time 109956535952 ps
CPU time 1945.25 seconds
Started Jan 25 04:06:04 AM PST 24
Finished Jan 25 04:38:31 AM PST 24
Peak memory 194792 kb
Host smart-ef54e26a-75d5-4e4c-88a6-38453ce0b445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526734914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.526734914
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.3257579830
Short name T86
Test name
Test status
Simulation time 1426586017902 ps
CPU time 1441.18 seconds
Started Jan 25 04:06:06 AM PST 24
Finished Jan 25 04:30:08 AM PST 24
Peak memory 214568 kb
Host smart-2dcaa639-4ca3-4edc-9282-d2f99e548f91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257579830 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.3257579830
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3422446924
Short name T360
Test name
Test status
Simulation time 253966248230 ps
CPU time 248.07 seconds
Started Jan 25 04:06:22 AM PST 24
Finished Jan 25 04:10:31 AM PST 24
Peak memory 183496 kb
Host smart-d30503c7-56ce-4888-a64c-e503a959ab6c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422446924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3422446924
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2087780616
Short name T602
Test name
Test status
Simulation time 245112461910 ps
CPU time 181.59 seconds
Started Jan 25 04:49:05 AM PST 24
Finished Jan 25 04:52:24 AM PST 24
Peak memory 183548 kb
Host smart-0c3e5eea-666c-4371-885c-3db8c1b00b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087780616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2087780616
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.1465779895
Short name T286
Test name
Test status
Simulation time 31827057585 ps
CPU time 46.97 seconds
Started Jan 25 04:06:25 AM PST 24
Finished Jan 25 04:07:13 AM PST 24
Peak memory 191752 kb
Host smart-1801f737-e91a-4b83-a400-019f3bb30d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465779895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1465779895
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3048895442
Short name T357
Test name
Test status
Simulation time 1104725526260 ps
CPU time 598.19 seconds
Started Jan 25 04:06:23 AM PST 24
Finished Jan 25 04:16:22 AM PST 24
Peak memory 191776 kb
Host smart-40e99678-c4f2-42e9-888e-57b3d2786a8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048895442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3048895442
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.777905407
Short name T572
Test name
Test status
Simulation time 102848222618 ps
CPU time 191.41 seconds
Started Jan 25 04:06:23 AM PST 24
Finished Jan 25 04:09:35 AM PST 24
Peak memory 183400 kb
Host smart-4c4d0b74-a8ce-4b33-81aa-5af9638d7292
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777905407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.777905407
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2760187023
Short name T302
Test name
Test status
Simulation time 261282696082 ps
CPU time 143.93 seconds
Started Jan 25 04:06:41 AM PST 24
Finished Jan 25 04:09:07 AM PST 24
Peak memory 194636 kb
Host smart-9e6aee39-fff8-47c6-b854-a12e8ca8dc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760187023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2760187023
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.776562878
Short name T174
Test name
Test status
Simulation time 129204295822 ps
CPU time 1352.55 seconds
Started Jan 25 04:06:44 AM PST 24
Finished Jan 25 04:29:18 AM PST 24
Peak memory 214440 kb
Host smart-f776d0c8-948a-43b6-9caf-631696af3b3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776562878 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.776562878
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2715166787
Short name T172
Test name
Test status
Simulation time 161220430410 ps
CPU time 149.4 seconds
Started Jan 25 05:42:15 AM PST 24
Finished Jan 25 05:44:48 AM PST 24
Peak memory 183556 kb
Host smart-53f056b0-3c2d-49b0-94e8-2ecca6c9ba4a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715166787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2715166787
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.2035580575
Short name T612
Test name
Test status
Simulation time 90459867846 ps
CPU time 144.64 seconds
Started Jan 25 04:06:40 AM PST 24
Finished Jan 25 04:09:07 AM PST 24
Peak memory 183476 kb
Host smart-4ec0a0c2-c8cc-4cae-843a-637246db04d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035580575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2035580575
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.1764985394
Short name T318
Test name
Test status
Simulation time 13330709190 ps
CPU time 96.78 seconds
Started Jan 25 04:06:43 AM PST 24
Finished Jan 25 04:08:22 AM PST 24
Peak memory 191732 kb
Host smart-73cd4964-d764-4876-b0a9-b52099484432
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764985394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.1764985394
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.3157683480
Short name T363
Test name
Test status
Simulation time 7742499005 ps
CPU time 12.55 seconds
Started Jan 25 04:06:40 AM PST 24
Finished Jan 25 04:06:54 AM PST 24
Peak memory 183444 kb
Host smart-a91b717b-88a2-4ed5-8dab-3830ffe42b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157683480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3157683480
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2607097831
Short name T380
Test name
Test status
Simulation time 51926495198 ps
CPU time 69.96 seconds
Started Jan 25 04:06:44 AM PST 24
Finished Jan 25 04:07:55 AM PST 24
Peak memory 183428 kb
Host smart-dfbbf167-b1e9-4980-acc5-276a5a75b222
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607097831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2607097831
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.3967044141
Short name T33
Test name
Test status
Simulation time 342925027995 ps
CPU time 660.98 seconds
Started Jan 25 04:06:41 AM PST 24
Finished Jan 25 04:17:44 AM PST 24
Peak memory 207624 kb
Host smart-356a308f-89e5-4f69-9a0c-f408e22e48c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967044141 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.3967044141
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3924740435
Short name T254
Test name
Test status
Simulation time 375242628107 ps
CPU time 575.3 seconds
Started Jan 25 04:06:43 AM PST 24
Finished Jan 25 04:16:20 AM PST 24
Peak memory 183476 kb
Host smart-df61cec4-b8f7-4b5e-8167-1222ce42d372
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924740435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3924740435
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2572421507
Short name T553
Test name
Test status
Simulation time 390496318403 ps
CPU time 159 seconds
Started Jan 25 04:06:41 AM PST 24
Finished Jan 25 04:09:22 AM PST 24
Peak memory 183488 kb
Host smart-9d75d0da-eeb5-4908-b747-d36925ae177e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572421507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2572421507
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.312530715
Short name T145
Test name
Test status
Simulation time 455711011579 ps
CPU time 163.36 seconds
Started Jan 25 06:11:51 AM PST 24
Finished Jan 25 06:14:38 AM PST 24
Peak memory 191856 kb
Host smart-3c6889b6-95b6-4014-88cd-0b4224f21735
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312530715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.312530715
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3737935864
Short name T356
Test name
Test status
Simulation time 192986843667 ps
CPU time 107.24 seconds
Started Jan 25 04:07:11 AM PST 24
Finished Jan 25 04:09:01 AM PST 24
Peak memory 183456 kb
Host smart-1f8be9b6-cd42-4fb5-bc44-20cb83fa75ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737935864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3737935864
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.2137682042
Short name T579
Test name
Test status
Simulation time 580596407888 ps
CPU time 1359 seconds
Started Jan 25 05:18:54 AM PST 24
Finished Jan 25 05:41:37 AM PST 24
Peak memory 207936 kb
Host smart-453f4a37-2c08-4248-8ded-25e15669ebc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137682042 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.2137682042
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3267358057
Short name T373
Test name
Test status
Simulation time 328176450981 ps
CPU time 319.06 seconds
Started Jan 25 04:45:32 AM PST 24
Finished Jan 25 04:50:55 AM PST 24
Peak memory 183532 kb
Host smart-35ebcfd5-a449-4f61-9b1e-743e5bf97938
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267358057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3267358057
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1650641990
Short name T615
Test name
Test status
Simulation time 499603592908 ps
CPU time 110.72 seconds
Started Jan 25 04:07:11 AM PST 24
Finished Jan 25 04:09:05 AM PST 24
Peak memory 183480 kb
Host smart-6de2f051-f82c-46ce-8a35-81185160c022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650641990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1650641990
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.1728457004
Short name T503
Test name
Test status
Simulation time 121486534 ps
CPU time 0.79 seconds
Started Jan 25 05:34:37 AM PST 24
Finished Jan 25 05:34:38 AM PST 24
Peak memory 183280 kb
Host smart-076a5e11-5025-45ab-b9ac-69de22b93744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728457004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1728457004
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.4045828999
Short name T271
Test name
Test status
Simulation time 141251116188 ps
CPU time 137.24 seconds
Started Jan 25 04:07:35 AM PST 24
Finished Jan 25 04:09:55 AM PST 24
Peak memory 183380 kb
Host smart-bf28c4ae-b04a-4dee-aa24-c651cae67ab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045828999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.4045828999
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.326528794
Short name T551
Test name
Test status
Simulation time 1339228259706 ps
CPU time 1154.27 seconds
Started Jan 25 04:07:33 AM PST 24
Finished Jan 25 04:26:50 AM PST 24
Peak memory 212400 kb
Host smart-22943908-e988-494b-ad2f-d980f222022b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326528794 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.326528794
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2124480860
Short name T187
Test name
Test status
Simulation time 153229321043 ps
CPU time 329.72 seconds
Started Jan 25 06:26:39 AM PST 24
Finished Jan 25 06:32:22 AM PST 24
Peak memory 183600 kb
Host smart-e3d47bdb-1931-4b49-b2b8-b5e4f0e04667
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124480860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.2124480860
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3166485321
Short name T520
Test name
Test status
Simulation time 118553992061 ps
CPU time 189.48 seconds
Started Jan 25 04:07:47 AM PST 24
Finished Jan 25 04:11:16 AM PST 24
Peak memory 183456 kb
Host smart-16590090-8965-4ef1-a8d6-9f00f250dd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166485321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3166485321
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.1952582086
Short name T342
Test name
Test status
Simulation time 74796328849 ps
CPU time 90.77 seconds
Started Jan 25 04:07:36 AM PST 24
Finished Jan 25 04:09:09 AM PST 24
Peak memory 191704 kb
Host smart-4048b59d-80fd-4f3d-bdfd-171d9f431dfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952582086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1952582086
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2294173668
Short name T311
Test name
Test status
Simulation time 115168224125 ps
CPU time 97.72 seconds
Started Jan 25 04:22:25 AM PST 24
Finished Jan 25 04:24:04 AM PST 24
Peak memory 195100 kb
Host smart-1c2c8add-3723-46d3-a6a6-590f719524a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294173668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2294173668
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2213826744
Short name T287
Test name
Test status
Simulation time 196526023374 ps
CPU time 480.2 seconds
Started Jan 25 08:54:17 AM PST 24
Finished Jan 25 09:02:19 AM PST 24
Peak memory 191828 kb
Host smart-23850119-1a94-4322-9078-a4a9bff77be6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213826744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2213826744
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.3003259742
Short name T314
Test name
Test status
Simulation time 111751396877 ps
CPU time 944.15 seconds
Started Jan 25 05:39:09 AM PST 24
Finished Jan 25 05:54:54 AM PST 24
Peak memory 213740 kb
Host smart-196b88a1-c23b-4e2c-a792-93cbcbd5c798
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003259742 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.3003259742
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1329258524
Short name T541
Test name
Test status
Simulation time 412518558150 ps
CPU time 374.7 seconds
Started Jan 25 04:07:50 AM PST 24
Finished Jan 25 04:14:22 AM PST 24
Peak memory 183516 kb
Host smart-b5c4aa45-a31d-4343-9a3d-c997095ec2a8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329258524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1329258524
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2031687068
Short name T543
Test name
Test status
Simulation time 221716875806 ps
CPU time 167.72 seconds
Started Jan 25 04:07:53 AM PST 24
Finished Jan 25 04:10:55 AM PST 24
Peak memory 183536 kb
Host smart-b372e319-a46a-4173-9619-63e8882b032c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031687068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2031687068
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.4251449762
Short name T21
Test name
Test status
Simulation time 980194412520 ps
CPU time 296.69 seconds
Started Jan 25 04:18:59 AM PST 24
Finished Jan 25 04:24:01 AM PST 24
Peak memory 191740 kb
Host smart-d7ffbb11-a83c-470c-8a8c-fd1c1c6c07c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251449762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.4251449762
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.1240003027
Short name T547
Test name
Test status
Simulation time 61513093 ps
CPU time 0.63 seconds
Started Jan 25 04:07:52 AM PST 24
Finished Jan 25 04:08:07 AM PST 24
Peak memory 182900 kb
Host smart-65a03952-e67c-4273-9aaf-f829defa013f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240003027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1240003027
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3375047663
Short name T215
Test name
Test status
Simulation time 1925004372519 ps
CPU time 739.45 seconds
Started Jan 25 04:07:51 AM PST 24
Finished Jan 25 04:20:26 AM PST 24
Peak memory 191660 kb
Host smart-34a901b4-2947-4c9a-a415-f99a5095b756
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375047663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3375047663
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.4176496107
Short name T496
Test name
Test status
Simulation time 308571343848 ps
CPU time 731.8 seconds
Started Jan 25 04:07:51 AM PST 24
Finished Jan 25 04:20:18 AM PST 24
Peak memory 207348 kb
Host smart-c6827cbe-8cea-4a45-9f97-263785d674a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176496107 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.4176496107
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3413014676
Short name T375
Test name
Test status
Simulation time 220179712527 ps
CPU time 355.63 seconds
Started Jan 25 04:08:13 AM PST 24
Finished Jan 25 04:14:23 AM PST 24
Peak memory 183480 kb
Host smart-2125feee-ee1a-40fd-aa7c-f93e079fdf91
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413014676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3413014676
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_random.324677915
Short name T305
Test name
Test status
Simulation time 369678533597 ps
CPU time 361.3 seconds
Started Jan 25 04:07:52 AM PST 24
Finished Jan 25 04:14:08 AM PST 24
Peak memory 191672 kb
Host smart-c766a708-a7b8-4345-9694-0cb89ae52d70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324677915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.324677915
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3989866823
Short name T276
Test name
Test status
Simulation time 457683608605 ps
CPU time 469.01 seconds
Started Jan 25 04:08:14 AM PST 24
Finished Jan 25 04:16:16 AM PST 24
Peak memory 191744 kb
Host smart-cae0fae2-369b-44bb-9c12-8636cbb941a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989866823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3989866823
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1384667773
Short name T329
Test name
Test status
Simulation time 2870228743796 ps
CPU time 1246.03 seconds
Started Jan 25 04:25:54 AM PST 24
Finished Jan 25 04:46:47 AM PST 24
Peak memory 191704 kb
Host smart-5f41d814-f8ad-4fe0-ac8a-f2e15118211a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384667773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1384667773
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.1663653880
Short name T499
Test name
Test status
Simulation time 52587531892 ps
CPU time 446.7 seconds
Started Jan 25 04:45:52 AM PST 24
Finished Jan 25 04:53:22 AM PST 24
Peak memory 206328 kb
Host smart-c744bcb4-dfda-4c33-b0ab-542e3377edc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663653880 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.1663653880
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1875521907
Short name T319
Test name
Test status
Simulation time 33118294905 ps
CPU time 25.85 seconds
Started Jan 25 04:08:16 AM PST 24
Finished Jan 25 04:08:54 AM PST 24
Peak memory 183484 kb
Host smart-e7ab2c9d-dc1f-4468-a72f-c4c54f8b61ef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875521907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.1875521907
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_random.724853818
Short name T253
Test name
Test status
Simulation time 230204526896 ps
CPU time 137.99 seconds
Started Jan 25 04:08:13 AM PST 24
Finished Jan 25 04:10:45 AM PST 24
Peak memory 191704 kb
Host smart-5594a82d-3562-4445-b3e1-b8a0d535b875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724853818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.724853818
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.459955041
Short name T589
Test name
Test status
Simulation time 103472245 ps
CPU time 0.75 seconds
Started Jan 25 04:08:16 AM PST 24
Finished Jan 25 04:08:29 AM PST 24
Peak memory 191436 kb
Host smart-8647132d-bb1b-47a8-aeee-66647b6db4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459955041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.459955041
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1097456262
Short name T228
Test name
Test status
Simulation time 844984675991 ps
CPU time 678.36 seconds
Started Jan 25 07:39:47 AM PST 24
Finished Jan 25 07:51:07 AM PST 24
Peak memory 191884 kb
Host smart-716a8bce-dca3-413a-934b-b6bd1591c20a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097456262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1097456262
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.2732846901
Short name T307
Test name
Test status
Simulation time 156164589115 ps
CPU time 201.49 seconds
Started Jan 25 06:01:54 AM PST 24
Finished Jan 25 06:05:18 AM PST 24
Peak memory 198268 kb
Host smart-0e621f34-c2d0-4869-a7ce-817ec21cdba9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732846901 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.2732846901
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.4292093231
Short name T534
Test name
Test status
Simulation time 268287277162 ps
CPU time 145.1 seconds
Started Jan 25 03:56:22 AM PST 24
Finished Jan 25 03:58:53 AM PST 24
Peak memory 183488 kb
Host smart-3ec2a8e9-609f-4a2f-aadf-2a6b66728851
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292093231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.4292093231
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1614080922
Short name T586
Test name
Test status
Simulation time 284912540123 ps
CPU time 229.98 seconds
Started Jan 25 03:56:24 AM PST 24
Finished Jan 25 04:00:19 AM PST 24
Peak memory 183480 kb
Host smart-2c894d7e-817a-4b9d-9be4-057caa8cd0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614080922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1614080922
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.965602508
Short name T261
Test name
Test status
Simulation time 319608536665 ps
CPU time 687.7 seconds
Started Jan 25 03:56:24 AM PST 24
Finished Jan 25 04:07:57 AM PST 24
Peak memory 191688 kb
Host smart-31418516-fc02-488a-946d-77f71e158ffc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965602508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.965602508
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2197916196
Short name T25
Test name
Test status
Simulation time 48272134112 ps
CPU time 88.76 seconds
Started Jan 25 03:56:29 AM PST 24
Finished Jan 25 03:58:02 AM PST 24
Peak memory 191704 kb
Host smart-2a38159d-dd07-4189-8595-061cb04d8cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197916196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2197916196
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.2052922890
Short name T143
Test name
Test status
Simulation time 149818607804 ps
CPU time 2525.74 seconds
Started Jan 25 03:56:20 AM PST 24
Finished Jan 25 04:38:34 AM PST 24
Peak memory 214476 kb
Host smart-d6983f66-913f-485a-bf5c-200fbf14bbb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052922890 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.2052922890
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.rv_timer_random.1301297817
Short name T333
Test name
Test status
Simulation time 188581358103 ps
CPU time 444.91 seconds
Started Jan 25 04:29:12 AM PST 24
Finished Jan 25 04:36:47 AM PST 24
Peak memory 191696 kb
Host smart-e152a795-f15e-450e-ad44-111c68e196e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301297817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1301297817
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.3554264166
Short name T256
Test name
Test status
Simulation time 70428467517 ps
CPU time 62.77 seconds
Started Jan 25 04:19:07 AM PST 24
Finished Jan 25 04:20:12 AM PST 24
Peak memory 183528 kb
Host smart-f9d7c3b6-4a2c-4ccd-bdd6-fdfe854b432e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554264166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3554264166
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.234297509
Short name T120
Test name
Test status
Simulation time 53584758155 ps
CPU time 207.51 seconds
Started Jan 25 04:08:48 AM PST 24
Finished Jan 25 04:12:16 AM PST 24
Peak memory 195156 kb
Host smart-c63cd20b-ea16-494d-9d2e-84bb92193e06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234297509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.234297509
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.4119503766
Short name T266
Test name
Test status
Simulation time 307875601535 ps
CPU time 426.92 seconds
Started Jan 25 04:08:51 AM PST 24
Finished Jan 25 04:16:01 AM PST 24
Peak memory 191760 kb
Host smart-2c85b1b4-f5c6-425c-96f5-83acb0afef4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119503766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.4119503766
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.4160833756
Short name T362
Test name
Test status
Simulation time 10506746297 ps
CPU time 6.43 seconds
Started Jan 25 04:09:08 AM PST 24
Finished Jan 25 04:09:29 AM PST 24
Peak memory 183000 kb
Host smart-4e113076-f75e-4cf1-b1cc-1ae5d105fc7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160833756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.4160833756
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.3953691613
Short name T239
Test name
Test status
Simulation time 66067864234 ps
CPU time 125.03 seconds
Started Jan 25 04:09:09 AM PST 24
Finished Jan 25 04:11:28 AM PST 24
Peak memory 191760 kb
Host smart-d966dc2d-ac64-4a20-8140-03524bdc8acc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953691613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3953691613
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2587859802
Short name T168
Test name
Test status
Simulation time 243924865456 ps
CPU time 116.07 seconds
Started Jan 25 04:09:05 AM PST 24
Finished Jan 25 04:11:19 AM PST 24
Peak memory 191696 kb
Host smart-9bfa1e8b-47d2-43ef-86f3-fbeb3cdc9ad6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587859802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2587859802
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.360283891
Short name T106
Test name
Test status
Simulation time 608218813850 ps
CPU time 577.04 seconds
Started Jan 25 03:56:34 AM PST 24
Finished Jan 25 04:06:13 AM PST 24
Peak memory 183504 kb
Host smart-93e22323-bad7-44d0-a51d-3d426b5ed9a7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360283891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.360283891
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.1391435198
Short name T559
Test name
Test status
Simulation time 584957110813 ps
CPU time 241.94 seconds
Started Jan 25 03:56:32 AM PST 24
Finished Jan 25 04:00:36 AM PST 24
Peak memory 183564 kb
Host smart-3f2b7e29-5606-4de2-9293-4166858c538f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391435198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1391435198
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.189105767
Short name T313
Test name
Test status
Simulation time 531197362364 ps
CPU time 614.88 seconds
Started Jan 25 03:56:44 AM PST 24
Finished Jan 25 04:07:00 AM PST 24
Peak memory 191740 kb
Host smart-c0ffe25d-27bd-4c20-bdd5-50c13b8de87e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189105767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.189105767
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.4238575172
Short name T592
Test name
Test status
Simulation time 1513568413 ps
CPU time 1.31 seconds
Started Jan 25 03:56:33 AM PST 24
Finished Jan 25 03:56:37 AM PST 24
Peak memory 191584 kb
Host smart-cab6af25-3322-40c2-b8b9-7ca4d7adf977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238575172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.4238575172
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2932257548
Short name T504
Test name
Test status
Simulation time 6687395480 ps
CPU time 9.96 seconds
Started Jan 25 03:56:35 AM PST 24
Finished Jan 25 03:56:47 AM PST 24
Peak memory 183296 kb
Host smart-f2b0d982-0a83-41f8-a659-812214f34b3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932257548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2932257548
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.2627072635
Short name T599
Test name
Test status
Simulation time 427592903136 ps
CPU time 761.6 seconds
Started Jan 25 03:56:32 AM PST 24
Finished Jan 25 04:09:17 AM PST 24
Peak memory 206324 kb
Host smart-31e65c0d-0c52-41db-8383-fef5c35a5ae2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627072635 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.2627072635
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.1402953590
Short name T309
Test name
Test status
Simulation time 188805606837 ps
CPU time 333.34 seconds
Started Jan 25 04:09:10 AM PST 24
Finished Jan 25 04:14:56 AM PST 24
Peak memory 194244 kb
Host smart-bcb4fb98-ff88-4b3f-9a1d-84349fdf84b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402953590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.1402953590
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.3702301655
Short name T213
Test name
Test status
Simulation time 129791637616 ps
CPU time 204.73 seconds
Started Jan 25 04:09:08 AM PST 24
Finished Jan 25 04:12:47 AM PST 24
Peak memory 191536 kb
Host smart-12cd3507-9cc3-4669-a1f9-50400a55a76a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702301655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3702301655
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.201976412
Short name T526
Test name
Test status
Simulation time 193554115676 ps
CPU time 382.7 seconds
Started Jan 25 04:09:08 AM PST 24
Finished Jan 25 04:15:45 AM PST 24
Peak memory 191256 kb
Host smart-cd582686-9c49-4900-a9f3-d6e30da27778
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201976412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.201976412
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.4244220458
Short name T574
Test name
Test status
Simulation time 13878332450 ps
CPU time 21.96 seconds
Started Jan 25 04:09:38 AM PST 24
Finished Jan 25 04:10:00 AM PST 24
Peak memory 183540 kb
Host smart-4f7910be-f7be-4c56-8eeb-56553e16ae39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244220458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.4244220458
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.3911338890
Short name T358
Test name
Test status
Simulation time 148632846031 ps
CPU time 47.79 seconds
Started Jan 25 04:42:55 AM PST 24
Finished Jan 25 04:43:54 AM PST 24
Peak memory 183556 kb
Host smart-6b95fae0-84d5-4473-9e35-6fbc6e47e1d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911338890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.3911338890
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2911957527
Short name T191
Test name
Test status
Simulation time 70917650484 ps
CPU time 112.39 seconds
Started Jan 25 04:42:13 AM PST 24
Finished Jan 25 04:44:16 AM PST 24
Peak memory 194984 kb
Host smart-292e0775-9f02-4a49-9c9b-c0effa5d0e7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911957527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2911957527
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.864628786
Short name T315
Test name
Test status
Simulation time 59529413301 ps
CPU time 157.06 seconds
Started Jan 25 04:09:36 AM PST 24
Finished Jan 25 04:12:13 AM PST 24
Peak memory 191708 kb
Host smart-13d6aba6-31ef-439a-9129-4382bfec841f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864628786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.864628786
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1940427658
Short name T180
Test name
Test status
Simulation time 24474174407 ps
CPU time 45.13 seconds
Started Jan 25 03:56:47 AM PST 24
Finished Jan 25 03:57:33 AM PST 24
Peak memory 183472 kb
Host smart-6276b2cc-820e-45a5-b02d-6ba9cb26b2c9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940427658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1940427658
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1929649203
Short name T43
Test name
Test status
Simulation time 182472620877 ps
CPU time 58.6 seconds
Started Jan 25 03:56:32 AM PST 24
Finished Jan 25 03:57:33 AM PST 24
Peak memory 183492 kb
Host smart-540507df-34a2-49e2-b6cf-b2c7b169c474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929649203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1929649203
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.907162744
Short name T611
Test name
Test status
Simulation time 178479577804 ps
CPU time 87.08 seconds
Started Jan 25 03:56:35 AM PST 24
Finished Jan 25 03:58:04 AM PST 24
Peak memory 191708 kb
Host smart-aef735a2-6b02-407f-af8f-fee536a144b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907162744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.907162744
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.3211856525
Short name T128
Test name
Test status
Simulation time 503960241654 ps
CPU time 271.93 seconds
Started Jan 25 03:56:36 AM PST 24
Finished Jan 25 04:01:10 AM PST 24
Peak memory 194432 kb
Host smart-b087bb77-1657-420b-95de-7a149e405de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211856525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3211856525
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.2390989500
Short name T567
Test name
Test status
Simulation time 243805757048 ps
CPU time 923.66 seconds
Started Jan 25 03:56:36 AM PST 24
Finished Jan 25 04:12:02 AM PST 24
Peak memory 214148 kb
Host smart-4e69f555-ee0a-405b-ade3-19cf99d6f97a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390989500 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.2390989500
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.365032091
Short name T129
Test name
Test status
Simulation time 381955563514 ps
CPU time 280 seconds
Started Jan 25 04:09:37 AM PST 24
Finished Jan 25 04:14:18 AM PST 24
Peak memory 191724 kb
Host smart-57e6bcf7-dc74-428c-987d-0f32a9116856
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365032091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.365032091
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.3694633093
Short name T8
Test name
Test status
Simulation time 32207809517 ps
CPU time 313.06 seconds
Started Jan 25 04:09:57 AM PST 24
Finished Jan 25 04:15:11 AM PST 24
Peak memory 183524 kb
Host smart-b11751ac-be6b-487e-a2f0-198142322731
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694633093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3694633093
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3201807714
Short name T573
Test name
Test status
Simulation time 23279586284 ps
CPU time 7.34 seconds
Started Jan 25 06:55:13 AM PST 24
Finished Jan 25 06:55:22 AM PST 24
Peak memory 183612 kb
Host smart-97457384-3f53-4685-9b31-e23fad620f7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201807714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3201807714
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.4130494247
Short name T350
Test name
Test status
Simulation time 362682910355 ps
CPU time 1175.48 seconds
Started Jan 25 05:31:30 AM PST 24
Finished Jan 25 05:51:14 AM PST 24
Peak memory 193876 kb
Host smart-8bb85528-cbca-4cf7-a466-b2936a40149e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130494247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.4130494247
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.876087912
Short name T575
Test name
Test status
Simulation time 118783457641 ps
CPU time 135.29 seconds
Started Jan 25 04:09:57 AM PST 24
Finished Jan 25 04:12:13 AM PST 24
Peak memory 191732 kb
Host smart-356f28ae-96c7-4b57-8ccf-0e6e6ccd4b4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876087912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.876087912
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3123695878
Short name T365
Test name
Test status
Simulation time 19456134116 ps
CPU time 240.55 seconds
Started Jan 25 04:09:59 AM PST 24
Finished Jan 25 04:14:01 AM PST 24
Peak memory 183540 kb
Host smart-0450713b-3b0f-4af0-b39d-b5b4c57fd430
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123695878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3123695878
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.1867678604
Short name T606
Test name
Test status
Simulation time 133872945473 ps
CPU time 130.3 seconds
Started Jan 25 06:03:31 AM PST 24
Finished Jan 25 06:05:43 AM PST 24
Peak memory 191812 kb
Host smart-e70962d8-aba7-40e0-8556-756bf4301ce8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867678604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1867678604
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.1388246131
Short name T208
Test name
Test status
Simulation time 88760076558 ps
CPU time 216.78 seconds
Started Jan 25 04:10:03 AM PST 24
Finished Jan 25 04:13:52 AM PST 24
Peak memory 191688 kb
Host smart-b5f058ef-3f7d-4a2c-84dd-8d62b1e5c3d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388246131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1388246131
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.276550538
Short name T203
Test name
Test status
Simulation time 545000968699 ps
CPU time 1955.34 seconds
Started Jan 25 04:10:02 AM PST 24
Finished Jan 25 04:42:39 AM PST 24
Peak memory 191688 kb
Host smart-2e4b7a71-cc5c-44e9-8d2a-be183edee30d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276550538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.276550538
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.3813130232
Short name T23
Test name
Test status
Simulation time 461991259600 ps
CPU time 446.37 seconds
Started Jan 25 04:10:02 AM PST 24
Finished Jan 25 04:17:30 AM PST 24
Peak memory 191732 kb
Host smart-e6c474d9-9082-4784-bc47-53dc8606211e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813130232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3813130232
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1879383877
Short name T218
Test name
Test status
Simulation time 391783060842 ps
CPU time 362.35 seconds
Started Jan 25 03:58:51 AM PST 24
Finished Jan 25 04:04:54 AM PST 24
Peak memory 183488 kb
Host smart-2d8d8642-022d-42df-8c35-ffef567c8c20
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879383877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1879383877
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3738380584
Short name T517
Test name
Test status
Simulation time 358290992605 ps
CPU time 130.59 seconds
Started Jan 25 03:58:47 AM PST 24
Finished Jan 25 04:00:59 AM PST 24
Peak memory 183524 kb
Host smart-1d8941b6-f538-40b2-aa16-0b1b211d65dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738380584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3738380584
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.1261845967
Short name T214
Test name
Test status
Simulation time 83021868761 ps
CPU time 152.75 seconds
Started Jan 25 03:58:48 AM PST 24
Finished Jan 25 04:01:23 AM PST 24
Peak memory 191728 kb
Host smart-20c383ae-daa4-4e48-95f6-98265b38bb68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261845967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1261845967
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.694277297
Short name T22
Test name
Test status
Simulation time 55718749230 ps
CPU time 96.34 seconds
Started Jan 25 03:58:45 AM PST 24
Finished Jan 25 04:00:24 AM PST 24
Peak memory 191752 kb
Host smart-186daf65-18dc-4a50-8d78-7e0d38738e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694277297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.694277297
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2919055229
Short name T537
Test name
Test status
Simulation time 816452232720 ps
CPU time 243.07 seconds
Started Jan 25 03:58:47 AM PST 24
Finished Jan 25 04:02:52 AM PST 24
Peak memory 194900 kb
Host smart-c517e72b-0a09-4dca-95eb-089c4e8f469e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919055229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2919055229
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.4008175518
Short name T32
Test name
Test status
Simulation time 258933730906 ps
CPU time 703.17 seconds
Started Jan 25 03:58:48 AM PST 24
Finished Jan 25 04:10:32 AM PST 24
Peak memory 209752 kb
Host smart-7fd4f6b7-f216-4420-8b2f-685cd9fde50e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008175518 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.4008175518
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.3856464768
Short name T264
Test name
Test status
Simulation time 260832854373 ps
CPU time 385.52 seconds
Started Jan 25 04:09:59 AM PST 24
Finished Jan 25 04:16:25 AM PST 24
Peak memory 191696 kb
Host smart-9f031f8c-17a3-4996-83d9-5a93e9de0907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856464768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3856464768
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.2820013105
Short name T127
Test name
Test status
Simulation time 274439428497 ps
CPU time 1326.43 seconds
Started Jan 25 04:10:02 AM PST 24
Finished Jan 25 04:32:16 AM PST 24
Peak memory 191688 kb
Host smart-b6ec5373-23da-4a66-9fcd-48b5416abaef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820013105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2820013105
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.1480381643
Short name T278
Test name
Test status
Simulation time 38555529321 ps
CPU time 1232.39 seconds
Started Jan 25 04:10:14 AM PST 24
Finished Jan 25 04:30:56 AM PST 24
Peak memory 191696 kb
Host smart-9350460d-1d87-41a4-8d9a-af6fe589b6b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480381643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1480381643
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2556583699
Short name T225
Test name
Test status
Simulation time 249558573359 ps
CPU time 140.06 seconds
Started Jan 25 04:10:14 AM PST 24
Finished Jan 25 04:12:44 AM PST 24
Peak memory 191744 kb
Host smart-60436708-85ff-4ac0-9c79-ea9ef3f88bff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556583699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2556583699
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.2147780510
Short name T230
Test name
Test status
Simulation time 59778772222 ps
CPU time 119.81 seconds
Started Jan 25 04:10:13 AM PST 24
Finished Jan 25 04:12:19 AM PST 24
Peak memory 194776 kb
Host smart-f71efac5-8ea6-4f11-8a1b-74f7e1379dd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147780510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2147780510
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2603962434
Short name T186
Test name
Test status
Simulation time 131956758809 ps
CPU time 492.59 seconds
Started Jan 25 04:10:14 AM PST 24
Finished Jan 25 04:18:36 AM PST 24
Peak memory 194800 kb
Host smart-9e587aa8-e498-4f13-9427-ab41aae31b65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603962434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2603962434
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.2266503103
Short name T344
Test name
Test status
Simulation time 118743160099 ps
CPU time 115.5 seconds
Started Jan 25 05:45:11 AM PST 24
Finished Jan 25 05:47:09 AM PST 24
Peak memory 194656 kb
Host smart-1a3b8676-0c8a-4559-89b5-35bf1ab09e87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266503103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2266503103
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.236396777
Short name T601
Test name
Test status
Simulation time 129550631707 ps
CPU time 848.32 seconds
Started Jan 25 04:10:11 AM PST 24
Finished Jan 25 04:24:26 AM PST 24
Peak memory 192800 kb
Host smart-ac37d973-8c7b-45f9-a892-7debbac4c4fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236396777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.236396777
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2745058941
Short name T263
Test name
Test status
Simulation time 447772447842 ps
CPU time 286.45 seconds
Started Jan 25 03:58:47 AM PST 24
Finished Jan 25 04:03:36 AM PST 24
Peak memory 183480 kb
Host smart-6699ee78-c178-450d-8cdf-295151a8f02c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745058941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2745058941
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.3115289253
Short name T566
Test name
Test status
Simulation time 121118031315 ps
CPU time 177.17 seconds
Started Jan 25 03:58:49 AM PST 24
Finished Jan 25 04:01:47 AM PST 24
Peak memory 183524 kb
Host smart-5e5342ea-2b0d-4362-8c78-5bf93b626df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115289253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.3115289253
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.270385089
Short name T124
Test name
Test status
Simulation time 61551158708 ps
CPU time 127.2 seconds
Started Jan 25 03:58:52 AM PST 24
Finished Jan 25 04:01:00 AM PST 24
Peak memory 195056 kb
Host smart-45581cf5-6198-4fbb-9f11-f7c836df9333
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270385089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.270385089
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2911504014
Short name T598
Test name
Test status
Simulation time 189267567719 ps
CPU time 83.56 seconds
Started Jan 25 03:58:53 AM PST 24
Finished Jan 25 04:00:18 AM PST 24
Peak memory 183496 kb
Host smart-a8609511-dd8d-43d5-8fbc-c7344fa552a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911504014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2911504014
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1082418875
Short name T284
Test name
Test status
Simulation time 1458308683925 ps
CPU time 947.93 seconds
Started Jan 25 03:58:46 AM PST 24
Finished Jan 25 04:14:36 AM PST 24
Peak memory 191656 kb
Host smart-17583da9-1f65-44ca-938c-fd5d4385d80a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082418875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1082418875
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.571608498
Short name T491
Test name
Test status
Simulation time 694355779729 ps
CPU time 370.68 seconds
Started Jan 25 03:58:51 AM PST 24
Finished Jan 25 04:05:03 AM PST 24
Peak memory 206356 kb
Host smart-ad28490e-8f94-4502-861f-0464948fb311
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571608498 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.571608498
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.rv_timer_random.2090641393
Short name T125
Test name
Test status
Simulation time 694980371868 ps
CPU time 475.25 seconds
Started Jan 25 04:10:12 AM PST 24
Finished Jan 25 04:18:14 AM PST 24
Peak memory 191680 kb
Host smart-d967da74-b43b-457b-948c-04ac6da229b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090641393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2090641393
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.177367622
Short name T245
Test name
Test status
Simulation time 126012803329 ps
CPU time 215.89 seconds
Started Jan 25 04:10:30 AM PST 24
Finished Jan 25 04:14:11 AM PST 24
Peak memory 191660 kb
Host smart-711f7333-8681-47a5-99a6-95da7548149c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177367622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.177367622
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.840999301
Short name T345
Test name
Test status
Simulation time 49611623016 ps
CPU time 54.44 seconds
Started Jan 25 04:10:27 AM PST 24
Finished Jan 25 04:11:26 AM PST 24
Peak memory 183504 kb
Host smart-de19071b-1622-408a-9915-344f814a97a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840999301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.840999301
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.1752681404
Short name T583
Test name
Test status
Simulation time 273718823585 ps
CPU time 202.82 seconds
Started Jan 25 04:10:29 AM PST 24
Finished Jan 25 04:13:56 AM PST 24
Peak memory 183452 kb
Host smart-1fdca4fa-7aa8-4701-bded-adfd2358475f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752681404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1752681404
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.4168344017
Short name T325
Test name
Test status
Simulation time 29804937178 ps
CPU time 74.86 seconds
Started Jan 25 04:10:29 AM PST 24
Finished Jan 25 04:11:48 AM PST 24
Peak memory 183548 kb
Host smart-52fcd23a-e795-4762-a1b1-31468337d4d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168344017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.4168344017
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.515588572
Short name T199
Test name
Test status
Simulation time 32980332906 ps
CPU time 83.32 seconds
Started Jan 25 04:10:32 AM PST 24
Finished Jan 25 04:11:59 AM PST 24
Peak memory 191740 kb
Host smart-3643781c-6a36-4f7a-9d98-1a91c9c1841a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515588572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.515588572
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1870246608
Short name T581
Test name
Test status
Simulation time 46125131884 ps
CPU time 78.09 seconds
Started Jan 25 04:10:34 AM PST 24
Finished Jan 25 04:11:56 AM PST 24
Peak memory 183452 kb
Host smart-f3ee48d2-e332-4ffe-ba64-16ac7b4fd9ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870246608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1870246608
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.881879073
Short name T374
Test name
Test status
Simulation time 575422341536 ps
CPU time 166.88 seconds
Started Jan 25 04:10:42 AM PST 24
Finished Jan 25 04:13:30 AM PST 24
Peak memory 191748 kb
Host smart-a93e9252-98a1-4d13-b49c-3ac9947ace8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881879073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.881879073
Directory /workspace/99.rv_timer_random/latest
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