Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.55 99.36 98.73 100.00 100.00 100.00 99.21


Total test records in report: 620
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html
T123 /workspace/coverage/default/111.rv_timer_random.2893928440 Feb 04 12:58:14 PM PST 24 Feb 04 01:03:01 PM PST 24 465110535893 ps
T142 /workspace/coverage/default/44.rv_timer_stress_all.1231799192 Feb 04 12:57:33 PM PST 24 Feb 04 01:41:54 PM PST 24 1017481725530 ps
T307 /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3156527051 Feb 04 12:57:03 PM PST 24 Feb 04 12:59:51 PM PST 24 91462993932 ps
T228 /workspace/coverage/default/131.rv_timer_random.3679073926 Feb 04 12:58:12 PM PST 24 Feb 04 01:06:29 PM PST 24 1007716616311 ps
T205 /workspace/coverage/default/108.rv_timer_random.4122009420 Feb 04 12:58:15 PM PST 24 Feb 04 01:07:06 PM PST 24 1047610280050 ps
T566 /workspace/coverage/default/42.rv_timer_disabled.4235546274 Feb 04 12:57:32 PM PST 24 Feb 04 12:57:49 PM PST 24 34640760352 ps
T567 /workspace/coverage/default/30.rv_timer_disabled.2075367842 Feb 04 12:57:25 PM PST 24 Feb 04 12:59:22 PM PST 24 267601599882 ps
T568 /workspace/coverage/default/56.rv_timer_random.3348101489 Feb 04 12:57:43 PM PST 24 Feb 04 01:03:49 PM PST 24 347038005265 ps
T298 /workspace/coverage/default/59.rv_timer_random.3762164628 Feb 04 12:57:47 PM PST 24 Feb 04 12:58:33 PM PST 24 41318664967 ps
T253 /workspace/coverage/default/54.rv_timer_random.3695912271 Feb 04 12:57:41 PM PST 24 Feb 04 01:00:11 PM PST 24 76030515237 ps
T569 /workspace/coverage/default/36.rv_timer_disabled.2787118822 Feb 04 12:57:27 PM PST 24 Feb 04 12:59:55 PM PST 24 207656391686 ps
T334 /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.489240889 Feb 04 12:57:39 PM PST 24 Feb 04 01:05:33 PM PST 24 807781711395 ps
T570 /workspace/coverage/default/173.rv_timer_random.4238358048 Feb 04 12:58:50 PM PST 24 Feb 04 12:58:57 PM PST 24 8239638281 ps
T201 /workspace/coverage/default/183.rv_timer_random.1643045425 Feb 04 12:58:50 PM PST 24 Feb 04 01:02:32 PM PST 24 389303845439 ps
T325 /workspace/coverage/default/3.rv_timer_random.3976417574 Feb 04 12:57:04 PM PST 24 Feb 04 01:04:17 PM PST 24 73458831624 ps
T286 /workspace/coverage/default/33.rv_timer_stress_all.2647901031 Feb 04 12:57:27 PM PST 24 Feb 04 01:21:19 PM PST 24 988455662593 ps
T251 /workspace/coverage/default/199.rv_timer_random.2645421007 Feb 04 12:58:56 PM PST 24 Feb 04 01:04:21 PM PST 24 618485180828 ps
T198 /workspace/coverage/default/176.rv_timer_random.1372732964 Feb 04 12:58:44 PM PST 24 Feb 04 01:00:51 PM PST 24 43192104269 ps
T188 /workspace/coverage/default/41.rv_timer_stress_all.1264701975 Feb 04 12:57:35 PM PST 24 Feb 04 01:25:19 PM PST 24 564842329690 ps
T571 /workspace/coverage/default/44.rv_timer_random.1395256585 Feb 04 12:57:38 PM PST 24 Feb 04 01:02:40 PM PST 24 145478304135 ps
T231 /workspace/coverage/default/98.rv_timer_random.4215673321 Feb 04 12:57:59 PM PST 24 Feb 04 01:00:39 PM PST 24 69057502000 ps
T305 /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.2952782959 Feb 04 12:56:56 PM PST 24 Feb 04 01:01:08 PM PST 24 151446145466 ps
T572 /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.1795996088 Feb 04 12:57:22 PM PST 24 Feb 04 01:01:21 PM PST 24 31372163031 ps
T213 /workspace/coverage/default/90.rv_timer_random.3952896909 Feb 04 12:57:48 PM PST 24 Feb 04 01:17:02 PM PST 24 536828479554 ps
T573 /workspace/coverage/default/27.rv_timer_random.1814257858 Feb 04 12:57:11 PM PST 24 Feb 04 12:59:17 PM PST 24 63585058891 ps
T574 /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.3789903661 Feb 04 12:57:30 PM PST 24 Feb 04 01:05:52 PM PST 24 134852123327 ps
T170 /workspace/coverage/default/154.rv_timer_random.2703487698 Feb 04 12:58:35 PM PST 24 Feb 04 01:06:24 PM PST 24 416006380504 ps
T575 /workspace/coverage/default/47.rv_timer_disabled.2837493006 Feb 04 12:57:38 PM PST 24 Feb 04 01:01:04 PM PST 24 519029787272 ps
T576 /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.4014056330 Feb 04 12:57:04 PM PST 24 Feb 04 01:03:36 PM PST 24 44028514384 ps
T577 /workspace/coverage/default/47.rv_timer_stress_all.2530898767 Feb 04 12:57:32 PM PST 24 Feb 04 12:57:34 PM PST 24 76762212 ps
T242 /workspace/coverage/default/155.rv_timer_random.280910901 Feb 04 12:58:45 PM PST 24 Feb 04 01:10:51 PM PST 24 344854588663 ps
T352 /workspace/coverage/default/14.rv_timer_random_reset.2342756776 Feb 04 12:57:10 PM PST 24 Feb 04 12:59:33 PM PST 24 100255793284 ps
T578 /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.3039802336 Feb 04 12:57:04 PM PST 24 Feb 04 12:58:40 PM PST 24 126566967965 ps
T154 /workspace/coverage/default/105.rv_timer_random.1537291725 Feb 04 12:58:03 PM PST 24 Feb 04 01:00:30 PM PST 24 325141592509 ps
T303 /workspace/coverage/default/42.rv_timer_random_reset.2147282399 Feb 04 12:57:38 PM PST 24 Feb 04 12:58:33 PM PST 24 31649597601 ps
T579 /workspace/coverage/default/34.rv_timer_random_reset.2716671204 Feb 04 12:57:28 PM PST 24 Feb 04 01:15:35 PM PST 24 58678971350 ps
T580 /workspace/coverage/default/44.rv_timer_disabled.50084220 Feb 04 12:57:55 PM PST 24 Feb 04 01:00:47 PM PST 24 656508113233 ps
T581 /workspace/coverage/default/9.rv_timer_random.1064574248 Feb 04 12:57:05 PM PST 24 Feb 04 12:57:34 PM PST 24 31748019388 ps
T234 /workspace/coverage/default/93.rv_timer_random.3163750298 Feb 04 12:57:49 PM PST 24 Feb 04 01:00:28 PM PST 24 90802249194 ps
T312 /workspace/coverage/default/7.rv_timer_random.26773478 Feb 04 12:56:56 PM PST 24 Feb 04 01:09:18 PM PST 24 410926327111 ps
T582 /workspace/coverage/default/66.rv_timer_random.577610825 Feb 04 12:57:52 PM PST 24 Feb 04 12:58:38 PM PST 24 53293233444 ps
T583 /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.1682700527 Feb 04 12:57:22 PM PST 24 Feb 04 12:59:34 PM PST 24 31132668915 ps
T584 /workspace/coverage/default/27.rv_timer_disabled.1187667274 Feb 04 12:57:09 PM PST 24 Feb 04 01:02:40 PM PST 24 188147850049 ps
T240 /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.71852374 Feb 04 12:57:44 PM PST 24 Feb 04 01:02:49 PM PST 24 165722188472 ps
T351 /workspace/coverage/default/180.rv_timer_random.3615498832 Feb 04 12:58:43 PM PST 24 Feb 04 01:04:50 PM PST 24 222428057567 ps
T585 /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1668800262 Feb 04 12:57:37 PM PST 24 Feb 04 01:18:46 PM PST 24 2417635098714 ps
T586 /workspace/coverage/default/2.rv_timer_disabled.716309996 Feb 04 12:56:44 PM PST 24 Feb 04 12:58:01 PM PST 24 43809902252 ps
T587 /workspace/coverage/default/4.rv_timer_disabled.3176900484 Feb 04 12:56:49 PM PST 24 Feb 04 12:58:28 PM PST 24 211700052688 ps
T588 /workspace/coverage/default/182.rv_timer_random.1238811227 Feb 04 12:58:41 PM PST 24 Feb 04 12:58:49 PM PST 24 16443617538 ps
T128 /workspace/coverage/default/190.rv_timer_random.4289383530 Feb 04 12:58:50 PM PST 24 Feb 04 01:03:43 PM PST 24 185428465985 ps
T589 /workspace/coverage/default/46.rv_timer_disabled.3405085941 Feb 04 12:57:35 PM PST 24 Feb 04 12:58:45 PM PST 24 43271712337 ps
T590 /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.759267043 Feb 04 12:57:09 PM PST 24 Feb 04 12:58:02 PM PST 24 17236411956 ps
T278 /workspace/coverage/default/51.rv_timer_random.3377334913 Feb 04 12:57:52 PM PST 24 Feb 04 01:00:22 PM PST 24 824103856476 ps
T591 /workspace/coverage/default/45.rv_timer_random.3085116591 Feb 04 12:57:30 PM PST 24 Feb 04 12:59:49 PM PST 24 637042037880 ps
T247 /workspace/coverage/default/21.rv_timer_random.2608111396 Feb 04 12:57:08 PM PST 24 Feb 04 12:57:34 PM PST 24 26407437924 ps
T592 /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.446199077 Feb 04 12:59:22 PM PST 24 Feb 04 01:05:35 PM PST 24 777719910502 ps
T255 /workspace/coverage/default/168.rv_timer_random.3408480861 Feb 04 12:58:41 PM PST 24 Feb 04 01:03:44 PM PST 24 122119914797 ps
T327 /workspace/coverage/default/43.rv_timer_random_reset.1082879118 Feb 04 12:57:38 PM PST 24 Feb 04 12:58:28 PM PST 24 95233726298 ps
T339 /workspace/coverage/default/1.rv_timer_random_reset.6988603 Feb 04 12:56:46 PM PST 24 Feb 04 12:57:22 PM PST 24 36587097309 ps
T593 /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.2969286093 Feb 04 12:57:07 PM PST 24 Feb 04 01:00:58 PM PST 24 67844705317 ps
T159 /workspace/coverage/default/193.rv_timer_random.1983683385 Feb 04 12:59:21 PM PST 24 Feb 04 01:03:39 PM PST 24 122657253997 ps
T594 /workspace/coverage/default/20.rv_timer_disabled.3741482136 Feb 04 12:57:07 PM PST 24 Feb 04 12:57:44 PM PST 24 25482835778 ps
T155 /workspace/coverage/default/4.rv_timer_random_reset.3332840831 Feb 04 12:56:44 PM PST 24 Feb 04 12:58:03 PM PST 24 31690313991 ps
T595 /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.191916050 Feb 04 12:57:05 PM PST 24 Feb 04 01:06:30 PM PST 24 131710206627 ps
T315 /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2196989938 Feb 04 12:57:07 PM PST 24 Feb 04 01:00:33 PM PST 24 359061255883 ps
T287 /workspace/coverage/default/79.rv_timer_random.960886143 Feb 04 12:57:47 PM PST 24 Feb 04 01:02:30 PM PST 24 834658905005 ps
T349 /workspace/coverage/default/8.rv_timer_stress_all.1064420560 Feb 04 12:56:58 PM PST 24 Feb 04 01:05:20 PM PST 24 703486643202 ps
T143 /workspace/coverage/default/142.rv_timer_random.3231670090 Feb 04 12:58:16 PM PST 24 Feb 04 01:02:09 PM PST 24 179221923336 ps
T296 /workspace/coverage/default/64.rv_timer_random.3145724235 Feb 04 12:57:58 PM PST 24 Feb 04 01:09:41 PM PST 24 707290922320 ps
T596 /workspace/coverage/default/55.rv_timer_random.3288013638 Feb 04 12:57:43 PM PST 24 Feb 04 01:01:15 PM PST 24 290812615614 ps
T172 /workspace/coverage/default/52.rv_timer_random.2579788632 Feb 04 12:57:37 PM PST 24 Feb 04 01:04:20 PM PST 24 261179907162 ps
T597 /workspace/coverage/default/8.rv_timer_disabled.3045502619 Feb 04 12:57:00 PM PST 24 Feb 04 01:01:43 PM PST 24 648291890985 ps
T341 /workspace/coverage/default/102.rv_timer_random.2185323211 Feb 04 12:57:56 PM PST 24 Feb 04 12:59:05 PM PST 24 406208183878 ps
T598 /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.2283061002 Feb 04 12:57:23 PM PST 24 Feb 04 01:08:36 PM PST 24 92156273242 ps
T599 /workspace/coverage/default/0.rv_timer_random_reset.4241041077 Feb 04 12:56:43 PM PST 24 Feb 04 12:57:31 PM PST 24 69462909043 ps
T362 /workspace/coverage/default/17.rv_timer_random_reset.2460554810 Feb 04 12:57:10 PM PST 24 Feb 04 01:12:05 PM PST 24 277607215282 ps
T600 /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.2810776965 Feb 04 12:57:04 PM PST 24 Feb 04 01:07:17 PM PST 24 205820926248 ps
T601 /workspace/coverage/default/18.rv_timer_random_reset.1633914151 Feb 04 12:57:09 PM PST 24 Feb 04 12:57:30 PM PST 24 35586373823 ps
T602 /workspace/coverage/default/34.rv_timer_stress_all.2998935630 Feb 04 12:59:04 PM PST 24 Feb 04 01:01:54 PM PST 24 116747582306 ps
T316 /workspace/coverage/default/97.rv_timer_random.3685303824 Feb 04 12:57:55 PM PST 24 Feb 04 01:03:53 PM PST 24 338257253010 ps
T232 /workspace/coverage/default/32.rv_timer_stress_all.2983939147 Feb 04 12:57:20 PM PST 24 Feb 04 01:25:16 PM PST 24 2759532744361 ps
T124 /workspace/coverage/default/140.rv_timer_random.2522238357 Feb 04 12:58:14 PM PST 24 Feb 04 01:01:35 PM PST 24 484818890460 ps
T214 /workspace/coverage/default/134.rv_timer_random.3724592512 Feb 04 12:58:14 PM PST 24 Feb 04 01:00:06 PM PST 24 65547275709 ps
T267 /workspace/coverage/default/100.rv_timer_random.2818034684 Feb 04 12:58:00 PM PST 24 Feb 04 01:03:23 PM PST 24 177807988966 ps
T258 /workspace/coverage/default/38.rv_timer_random_reset.2493470273 Feb 04 12:59:18 PM PST 24 Feb 04 01:00:53 PM PST 24 203981984554 ps
T289 /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.975733649 Feb 04 12:56:49 PM PST 24 Feb 04 01:16:49 PM PST 24 113741954794 ps
T603 /workspace/coverage/default/32.rv_timer_disabled.2366079021 Feb 04 12:57:24 PM PST 24 Feb 04 01:02:56 PM PST 24 803140031554 ps
T125 /workspace/coverage/default/30.rv_timer_random.2269786066 Feb 04 12:57:24 PM PST 24 Feb 04 01:49:54 PM PST 24 152504694837 ps
T604 /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.4123953973 Feb 04 12:57:08 PM PST 24 Feb 04 01:04:02 PM PST 24 223290840099 ps
T605 /workspace/coverage/default/15.rv_timer_random.4010974707 Feb 04 12:57:10 PM PST 24 Feb 04 12:58:58 PM PST 24 64519928662 ps
T606 /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1775122971 Feb 04 12:57:39 PM PST 24 Feb 04 12:57:50 PM PST 24 9323071883 ps
T607 /workspace/coverage/default/162.rv_timer_random.4111014054 Feb 04 12:58:41 PM PST 24 Feb 04 01:00:08 PM PST 24 26353352579 ps
T139 /workspace/coverage/default/122.rv_timer_random.3526674473 Feb 04 12:58:10 PM PST 24 Feb 04 01:29:35 PM PST 24 923200422134 ps
T608 /workspace/coverage/default/38.rv_timer_disabled.703194350 Feb 04 12:57:37 PM PST 24 Feb 04 12:59:19 PM PST 24 148714397078 ps
T609 /workspace/coverage/default/12.rv_timer_random_reset.924631692 Feb 04 12:57:04 PM PST 24 Feb 04 12:57:11 PM PST 24 2914481958 ps
T350 /workspace/coverage/default/177.rv_timer_random.3193808024 Feb 04 12:58:42 PM PST 24 Feb 04 01:12:05 PM PST 24 266087097972 ps
T610 /workspace/coverage/default/31.rv_timer_random.46251535 Feb 04 12:57:25 PM PST 24 Feb 04 01:05:09 PM PST 24 451393824545 ps
T212 /workspace/coverage/default/39.rv_timer_stress_all.3190980462 Feb 04 12:57:40 PM PST 24 Feb 04 01:16:20 PM PST 24 339517722155 ps
T342 /workspace/coverage/default/9.rv_timer_stress_all.547414157 Feb 04 12:56:59 PM PST 24 Feb 04 01:48:44 PM PST 24 527386865135 ps
T611 /workspace/coverage/default/137.rv_timer_random.3185102133 Feb 04 12:58:17 PM PST 24 Feb 04 01:01:04 PM PST 24 84963579708 ps
T285 /workspace/coverage/default/159.rv_timer_random.787283648 Feb 04 12:58:35 PM PST 24 Feb 04 01:07:36 PM PST 24 49929619476 ps
T160 /workspace/coverage/default/3.rv_timer_stress_all.4092258819 Feb 04 12:56:51 PM PST 24 Feb 04 01:39:21 PM PST 24 3091863337978 ps
T612 /workspace/coverage/default/8.rv_timer_random_reset.1086892657 Feb 04 12:57:04 PM PST 24 Feb 04 01:00:33 PM PST 24 288146339713 ps
T348 /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.1348778296 Feb 04 12:57:02 PM PST 24 Feb 04 12:57:29 PM PST 24 12105011809 ps
T136 /workspace/coverage/default/24.rv_timer_stress_all.251153300 Feb 04 12:57:23 PM PST 24 Feb 04 01:12:48 PM PST 24 401666444935 ps
T613 /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1983551534 Feb 04 12:57:05 PM PST 24 Feb 04 01:00:10 PM PST 24 503209633259 ps
T335 /workspace/coverage/default/133.rv_timer_random.4275020537 Feb 04 12:58:09 PM PST 24 Feb 04 01:01:38 PM PST 24 384586835659 ps
T614 /workspace/coverage/default/29.rv_timer_stress_all.633874330 Feb 04 12:57:22 PM PST 24 Feb 04 12:57:23 PM PST 24 20750798 ps
T158 /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3607987801 Feb 04 12:57:11 PM PST 24 Feb 04 01:02:35 PM PST 24 618547358807 ps
T615 /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.153348912 Feb 04 12:57:25 PM PST 24 Feb 04 12:57:52 PM PST 24 45649316256 ps
T360 /workspace/coverage/default/4.rv_timer_random.728949993 Feb 04 12:57:07 PM PST 24 Feb 04 01:01:55 PM PST 24 400424027481 ps
T283 /workspace/coverage/default/112.rv_timer_random.1345243884 Feb 04 12:58:21 PM PST 24 Feb 04 01:02:28 PM PST 24 228866218875 ps
T356 /workspace/coverage/default/156.rv_timer_random.1460690932 Feb 04 12:58:35 PM PST 24 Feb 04 01:08:04 PM PST 24 260009980438 ps
T227 /workspace/coverage/default/86.rv_timer_random.1342530735 Feb 04 12:57:59 PM PST 24 Feb 04 01:02:23 PM PST 24 560406311791 ps
T616 /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.795814115 Feb 04 12:59:22 PM PST 24 Feb 04 01:02:34 PM PST 24 347859190040 ps
T617 /workspace/coverage/default/126.rv_timer_random.3112636305 Feb 04 12:58:08 PM PST 24 Feb 04 01:09:07 PM PST 24 202091760479 ps
T363 /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.2499192422 Feb 04 12:56:44 PM PST 24 Feb 04 01:12:13 PM PST 24 423495659513 ps
T618 /workspace/coverage/default/13.rv_timer_random_reset.2465824209 Feb 04 12:56:56 PM PST 24 Feb 04 12:56:59 PM PST 24 608438768 ps
T619 /workspace/coverage/default/48.rv_timer_disabled.1292113721 Feb 04 12:57:43 PM PST 24 Feb 04 01:00:50 PM PST 24 140485185008 ps
T620 /workspace/coverage/default/36.rv_timer_stress_all.482179560 Feb 04 12:57:33 PM PST 24 Feb 04 01:07:51 PM PST 24 680019840936 ps

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.796278473
Short name T3
Test name
Test status
Simulation time 133494024080 ps
CPU time 1068.33 seconds
Started Feb 04 12:57:37 PM PST 24
Finished Feb 04 01:15:28 PM PST 24
Peak memory 211708 kb
Host smart-474c50b2-ab4d-47b8-81a7-556fd487c959
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796278473 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.796278473
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.550134331
Short name T52
Test name
Test status
Simulation time 837091710888 ps
CPU time 1959.15 seconds
Started Feb 04 12:57:13 PM PST 24
Finished Feb 04 01:29:54 PM PST 24
Peak memory 190696 kb
Host smart-63edccc7-65b1-48d7-91d6-604c778d98c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550134331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.
550134331
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.2123389382
Short name T2
Test name
Test status
Simulation time 2977388423686 ps
CPU time 6169.55 seconds
Started Feb 04 12:57:20 PM PST 24
Finished Feb 04 02:40:11 PM PST 24
Peak memory 190656 kb
Host smart-cd0494e3-e3f8-4560-8fc2-b7f8a21b6bc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123389382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.2123389382
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2734763649
Short name T31
Test name
Test status
Simulation time 93959426 ps
CPU time 1.13 seconds
Started Feb 04 04:17:36 PM PST 24
Finished Feb 04 04:17:44 PM PST 24
Peak memory 194544 kb
Host smart-ab53cfed-fea4-493b-9332-5064203a5b59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734763649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.2734763649
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.4226062440
Short name T113
Test name
Test status
Simulation time 2707744021729 ps
CPU time 6968.23 seconds
Started Feb 04 12:57:17 PM PST 24
Finished Feb 04 02:53:27 PM PST 24
Peak memory 190700 kb
Host smart-a1a7b348-4545-4b4c-9823-3dce0d898442
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226062440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.4226062440
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.2936060535
Short name T95
Test name
Test status
Simulation time 486560547772 ps
CPU time 1256.25 seconds
Started Feb 04 12:56:57 PM PST 24
Finished Feb 04 01:17:57 PM PST 24
Peak memory 194716 kb
Host smart-3b32ce58-3bdc-4749-b7ed-c74236e1d7ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936060535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
2936060535
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3541944407
Short name T44
Test name
Test status
Simulation time 275870175 ps
CPU time 0.88 seconds
Started Feb 04 04:17:23 PM PST 24
Finished Feb 04 04:17:25 PM PST 24
Peak memory 191608 kb
Host smart-50473987-991b-46cc-8c66-c415f032dca9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541944407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3541944407
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.4092258819
Short name T160
Test name
Test status
Simulation time 3091863337978 ps
CPU time 2544.73 seconds
Started Feb 04 12:56:51 PM PST 24
Finished Feb 04 01:39:21 PM PST 24
Peak memory 195644 kb
Host smart-69262c2d-7f1d-4e5a-a8ff-2610b06763bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092258819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
4092258819
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.547414157
Short name T342
Test name
Test status
Simulation time 527386865135 ps
CPU time 3101.74 seconds
Started Feb 04 12:56:59 PM PST 24
Finished Feb 04 01:48:44 PM PST 24
Peak memory 190780 kb
Host smart-4d79d7c0-7ebb-4511-92cf-0c1cd55313a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547414157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.547414157
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.3743595494
Short name T161
Test name
Test status
Simulation time 440735724745 ps
CPU time 2897.4 seconds
Started Feb 04 12:57:00 PM PST 24
Finished Feb 04 01:45:20 PM PST 24
Peak memory 195460 kb
Host smart-89ac9957-80fe-429c-93ee-dc709b43a5fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743595494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.3743595494
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.917267387
Short name T141
Test name
Test status
Simulation time 1011096004817 ps
CPU time 1355 seconds
Started Feb 04 12:57:11 PM PST 24
Finished Feb 04 01:19:50 PM PST 24
Peak memory 190676 kb
Host smart-056a5e2b-0d3d-495c-bd3e-409c27f5e449
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917267387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.
917267387
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3679402632
Short name T101
Test name
Test status
Simulation time 564428407657 ps
CPU time 1346.17 seconds
Started Feb 04 12:56:56 PM PST 24
Finished Feb 04 01:19:24 PM PST 24
Peak memory 194984 kb
Host smart-fa306f65-64af-4dd0-a6d5-fb1510ac7162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679402632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3679402632
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2286886445
Short name T192
Test name
Test status
Simulation time 1381910785966 ps
CPU time 1518.65 seconds
Started Feb 04 12:57:07 PM PST 24
Finished Feb 04 01:22:31 PM PST 24
Peak memory 195348 kb
Host smart-df0d54cb-190b-4514-8df6-69bb20065370
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286886445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2286886445
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1560122323
Short name T148
Test name
Test status
Simulation time 1000994904402 ps
CPU time 2409.14 seconds
Started Feb 04 12:59:19 PM PST 24
Finished Feb 04 01:39:30 PM PST 24
Peak memory 190304 kb
Host smart-26880996-71a9-46d8-b6bf-fbd6d606d529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560122323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1560122323
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.84751161
Short name T17
Test name
Test status
Simulation time 325083453 ps
CPU time 0.91 seconds
Started Feb 04 12:56:55 PM PST 24
Finished Feb 04 12:56:58 PM PST 24
Peak memory 213912 kb
Host smart-c8e2e532-3cbf-41da-b5bd-a3568738ef52
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84751161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.84751161
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2983939147
Short name T232
Test name
Test status
Simulation time 2759532744361 ps
CPU time 1674.84 seconds
Started Feb 04 12:57:20 PM PST 24
Finished Feb 04 01:25:16 PM PST 24
Peak memory 195028 kb
Host smart-2a48c987-ffa0-4f54-8773-5ee6906a81df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983939147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2983939147
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.4103047859
Short name T145
Test name
Test status
Simulation time 1155805378308 ps
CPU time 931.82 seconds
Started Feb 04 12:57:37 PM PST 24
Finished Feb 04 01:13:12 PM PST 24
Peak memory 190596 kb
Host smart-cc56982a-e4e6-4977-bb52-3df1612f849a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103047859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.4103047859
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2841642
Short name T134
Test name
Test status
Simulation time 1875434321005 ps
CPU time 2039.11 seconds
Started Feb 04 12:57:12 PM PST 24
Finished Feb 04 01:31:14 PM PST 24
Peak memory 190696 kb
Host smart-cb602b62-dd87-4402-8f46-7cf6424f176f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.2841642
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.80526440
Short name T15
Test name
Test status
Simulation time 63041818 ps
CPU time 0.87 seconds
Started Feb 04 04:18:02 PM PST 24
Finished Feb 04 04:18:07 PM PST 24
Peak memory 192880 kb
Host smart-d1a0bb46-4e1f-4374-8401-2d8740853c95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80526440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_tim
er_same_csr_outstanding.80526440
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3394782457
Short name T190
Test name
Test status
Simulation time 503028743023 ps
CPU time 948.88 seconds
Started Feb 04 12:56:42 PM PST 24
Finished Feb 04 01:12:34 PM PST 24
Peak memory 190764 kb
Host smart-a5a362b5-4b37-404a-bce6-fbb8fb8360e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394782457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3394782457
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3068198123
Short name T127
Test name
Test status
Simulation time 1247260530031 ps
CPU time 3760.47 seconds
Started Feb 04 12:57:40 PM PST 24
Finished Feb 04 02:00:22 PM PST 24
Peak memory 190668 kb
Host smart-64bbca8c-51dd-4f94-adc2-a60ec78393b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068198123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3068198123
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.626117663
Short name T217
Test name
Test status
Simulation time 2655002913797 ps
CPU time 1423.29 seconds
Started Feb 04 12:57:27 PM PST 24
Finished Feb 04 01:21:12 PM PST 24
Peak memory 190732 kb
Host smart-58bd42e4-074c-4e9f-a22b-d04c3019ad45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626117663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
626117663
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_random.3083194106
Short name T179
Test name
Test status
Simulation time 535675359135 ps
CPU time 331.92 seconds
Started Feb 04 12:57:30 PM PST 24
Finished Feb 04 01:03:05 PM PST 24
Peak memory 194168 kb
Host smart-35463acf-60cd-4c89-9081-0918e2f0fe33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083194106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3083194106
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.4009059389
Short name T222
Test name
Test status
Simulation time 321545121426 ps
CPU time 595.9 seconds
Started Feb 04 12:56:54 PM PST 24
Finished Feb 04 01:06:52 PM PST 24
Peak memory 190708 kb
Host smart-3a7d1a5f-17af-49dc-ad62-88bad9c8e833
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009059389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
4009059389
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.760796507
Short name T23
Test name
Test status
Simulation time 545881627359 ps
CPU time 1357.91 seconds
Started Feb 04 12:57:00 PM PST 24
Finished Feb 04 01:19:40 PM PST 24
Peak memory 190692 kb
Host smart-29ddc027-1b9c-4fc0-a104-8f1c185b0c60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760796507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
760796507
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/155.rv_timer_random.280910901
Short name T242
Test name
Test status
Simulation time 344854588663 ps
CPU time 725.06 seconds
Started Feb 04 12:58:45 PM PST 24
Finished Feb 04 01:10:51 PM PST 24
Peak memory 190660 kb
Host smart-d5837c76-7f47-41a8-a789-690d62820056
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280910901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.280910901
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2647901031
Short name T286
Test name
Test status
Simulation time 988455662593 ps
CPU time 1431.54 seconds
Started Feb 04 12:57:27 PM PST 24
Finished Feb 04 01:21:19 PM PST 24
Peak memory 190608 kb
Host smart-828c806a-4507-465a-8765-1edcc8b63942
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647901031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2647901031
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/131.rv_timer_random.3679073926
Short name T228
Test name
Test status
Simulation time 1007716616311 ps
CPU time 496.12 seconds
Started Feb 04 12:58:12 PM PST 24
Finished Feb 04 01:06:29 PM PST 24
Peak memory 190512 kb
Host smart-a41cd6c6-1064-43bb-8fa4-1cf7bb9a4551
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679073926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3679073926
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1460690932
Short name T356
Test name
Test status
Simulation time 260009980438 ps
CPU time 567.67 seconds
Started Feb 04 12:58:35 PM PST 24
Finished Feb 04 01:08:04 PM PST 24
Peak memory 190728 kb
Host smart-c1aaa13c-5e11-44ba-94cd-2324f6bb5e72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460690932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1460690932
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2306872389
Short name T27
Test name
Test status
Simulation time 938763618902 ps
CPU time 500.58 seconds
Started Feb 04 12:59:22 PM PST 24
Finished Feb 04 01:07:43 PM PST 24
Peak memory 181984 kb
Host smart-35cbfd8b-3a74-4b87-afa2-7c3330c16d2f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306872389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2306872389
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/128.rv_timer_random.3365969218
Short name T171
Test name
Test status
Simulation time 419251004758 ps
CPU time 608.18 seconds
Started Feb 04 12:58:08 PM PST 24
Finished Feb 04 01:08:20 PM PST 24
Peak memory 190656 kb
Host smart-aa063cbc-bd5d-4697-bc39-7859ae64e5fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365969218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3365969218
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.3974606553
Short name T257
Test name
Test status
Simulation time 116041323305 ps
CPU time 520.5 seconds
Started Feb 04 12:58:17 PM PST 24
Finished Feb 04 01:06:59 PM PST 24
Peak memory 190760 kb
Host smart-855ee6f4-b902-4d19-b44c-7fba844122f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974606553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3974606553
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.1264701975
Short name T188
Test name
Test status
Simulation time 564842329690 ps
CPU time 1659.49 seconds
Started Feb 04 12:57:35 PM PST 24
Finished Feb 04 01:25:19 PM PST 24
Peak memory 190668 kb
Host smart-485253f7-c407-4398-a655-d08ca46a9e5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264701975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.1264701975
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/125.rv_timer_random.3827938388
Short name T279
Test name
Test status
Simulation time 113418083612 ps
CPU time 2267.42 seconds
Started Feb 04 12:58:16 PM PST 24
Finished Feb 04 01:36:05 PM PST 24
Peak memory 190692 kb
Host smart-b86c317a-2860-4c83-b32e-edd98a139d02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827938388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3827938388
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.2604724526
Short name T291
Test name
Test status
Simulation time 169017371183 ps
CPU time 381.12 seconds
Started Feb 04 12:58:27 PM PST 24
Finished Feb 04 01:04:51 PM PST 24
Peak memory 190632 kb
Host smart-e8328531-e4d4-4d18-8e72-1e7ea9239331
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604724526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2604724526
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3607987801
Short name T158
Test name
Test status
Simulation time 618547358807 ps
CPU time 321.22 seconds
Started Feb 04 12:57:11 PM PST 24
Finished Feb 04 01:02:35 PM PST 24
Peak memory 182480 kb
Host smart-b9915213-b12d-4e25-9250-e0f3d4292a1c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607987801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.3607987801
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/178.rv_timer_random.4245702277
Short name T163
Test name
Test status
Simulation time 597875564886 ps
CPU time 431.58 seconds
Started Feb 04 12:58:40 PM PST 24
Finished Feb 04 01:05:53 PM PST 24
Peak memory 190740 kb
Host smart-dbda48af-8c2b-49c3-bcf3-d27edb9846b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245702277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.4245702277
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1643045425
Short name T201
Test name
Test status
Simulation time 389303845439 ps
CPU time 219.22 seconds
Started Feb 04 12:58:50 PM PST 24
Finished Feb 04 01:02:32 PM PST 24
Peak memory 190676 kb
Host smart-f461c31d-d6fc-4f18-9a6b-e2ad8a4cc410
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643045425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1643045425
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.3867119156
Short name T321
Test name
Test status
Simulation time 303290190418 ps
CPU time 483.73 seconds
Started Feb 04 12:57:14 PM PST 24
Finished Feb 04 01:05:19 PM PST 24
Peak memory 194432 kb
Host smart-025b8d27-9d39-4491-badc-b16e02fc1aa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867119156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.3867119156
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_random.1381317283
Short name T311
Test name
Test status
Simulation time 575588094995 ps
CPU time 503.31 seconds
Started Feb 04 12:57:32 PM PST 24
Finished Feb 04 01:05:57 PM PST 24
Peak memory 190704 kb
Host smart-b64e0407-c6a5-419d-8a46-5517064382de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381317283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.1381317283
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.519477819
Short name T110
Test name
Test status
Simulation time 49059679683 ps
CPU time 197.68 seconds
Started Feb 04 12:57:44 PM PST 24
Finished Feb 04 01:01:04 PM PST 24
Peak memory 190524 kb
Host smart-fa6bb332-5463-49bd-a050-b77803a4b0db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519477819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.519477819
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3209121474
Short name T207
Test name
Test status
Simulation time 594364466760 ps
CPU time 273.79 seconds
Started Feb 04 12:57:59 PM PST 24
Finished Feb 04 01:02:33 PM PST 24
Peak memory 190684 kb
Host smart-cdc675be-7a1b-4a4d-8b23-31967a107437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209121474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3209121474
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.952632868
Short name T153
Test name
Test status
Simulation time 162616768507 ps
CPU time 268.39 seconds
Started Feb 04 12:56:59 PM PST 24
Finished Feb 04 01:01:31 PM PST 24
Peak memory 182516 kb
Host smart-c2adc51d-4dce-4ce9-838f-4ecd8ca4cf35
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952632868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.rv_timer_cfg_update_on_fly.952632868
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/122.rv_timer_random.3526674473
Short name T139
Test name
Test status
Simulation time 923200422134 ps
CPU time 1882.89 seconds
Started Feb 04 12:58:10 PM PST 24
Finished Feb 04 01:29:35 PM PST 24
Peak memory 190712 kb
Host smart-cf7c802c-c532-434d-bc62-269843786291
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526674473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3526674473
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2494411898
Short name T144
Test name
Test status
Simulation time 1314170281150 ps
CPU time 938.73 seconds
Started Feb 04 12:57:08 PM PST 24
Finished Feb 04 01:12:53 PM PST 24
Peak memory 190808 kb
Host smart-b092a101-a9bd-4f8c-a973-a0cde332f0c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494411898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2494411898
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_random.633223923
Short name T225
Test name
Test status
Simulation time 154425075107 ps
CPU time 206.82 seconds
Started Feb 04 12:57:09 PM PST 24
Finished Feb 04 01:00:41 PM PST 24
Peak memory 190668 kb
Host smart-77a726c8-5ad8-4536-8e09-3c9713e0ae20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633223923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.633223923
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2217374832
Short name T173
Test name
Test status
Simulation time 139858887911 ps
CPU time 231.07 seconds
Started Feb 04 12:56:46 PM PST 24
Finished Feb 04 01:00:40 PM PST 24
Peak memory 182516 kb
Host smart-a51f1c56-2481-40bb-b3b6-b03d807afd17
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217374832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.2217374832
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_random.899468489
Short name T565
Test name
Test status
Simulation time 275050254821 ps
CPU time 121.65 seconds
Started Feb 04 12:57:31 PM PST 24
Finished Feb 04 12:59:35 PM PST 24
Peak memory 190748 kb
Host smart-6c738c99-008d-483b-8f1a-01dc69a47390
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899468489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.899468489
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2349770809
Short name T47
Test name
Test status
Simulation time 1422488329781 ps
CPU time 830.13 seconds
Started Feb 04 12:57:31 PM PST 24
Finished Feb 04 01:11:23 PM PST 24
Peak memory 190624 kb
Host smart-4d65d95f-8732-41a0-83d2-8c3a74d59755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349770809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2349770809
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/84.rv_timer_random.3872068195
Short name T133
Test name
Test status
Simulation time 386971598020 ps
CPU time 2288.97 seconds
Started Feb 04 12:57:47 PM PST 24
Finished Feb 04 01:35:58 PM PST 24
Peak memory 190736 kb
Host smart-9ab05bf0-dba7-4cc8-af7e-5dddb9a8398d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872068195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3872068195
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.1342530735
Short name T227
Test name
Test status
Simulation time 560406311791 ps
CPU time 263.25 seconds
Started Feb 04 12:57:59 PM PST 24
Finished Feb 04 01:02:23 PM PST 24
Peak memory 190884 kb
Host smart-97369f5d-1995-4cfd-9790-02e8dd29fe3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342530735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.1342530735
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1745587523
Short name T51
Test name
Test status
Simulation time 74414434 ps
CPU time 0.68 seconds
Started Feb 04 04:17:34 PM PST 24
Finished Feb 04 04:17:37 PM PST 24
Peak memory 182376 kb
Host smart-a7615b5b-c971-4a92-83e3-c1409209cdc6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745587523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1745587523
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.355218084
Short name T57
Test name
Test status
Simulation time 68919169 ps
CPU time 1.22 seconds
Started Feb 04 04:18:21 PM PST 24
Finished Feb 04 04:18:23 PM PST 24
Peak memory 194536 kb
Host smart-9a589b22-d89b-4c0d-bee1-74a85e69c9f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355218084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_in
tg_err.355218084
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/109.rv_timer_random.1716532358
Short name T98
Test name
Test status
Simulation time 2403505844268 ps
CPU time 692.26 seconds
Started Feb 04 12:58:10 PM PST 24
Finished Feb 04 01:09:44 PM PST 24
Peak memory 194420 kb
Host smart-b610d6f8-8a9d-4efe-be4a-80a12738508a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716532358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1716532358
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.2600785392
Short name T137
Test name
Test status
Simulation time 382627211134 ps
CPU time 416.86 seconds
Started Feb 04 12:58:09 PM PST 24
Finished Feb 04 01:05:09 PM PST 24
Peak memory 190724 kb
Host smart-f95c84b6-27a0-45bf-a928-b92cf271412a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600785392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2600785392
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.2522238357
Short name T124
Test name
Test status
Simulation time 484818890460 ps
CPU time 199.43 seconds
Started Feb 04 12:58:14 PM PST 24
Finished Feb 04 01:01:35 PM PST 24
Peak memory 190592 kb
Host smart-cddc0e23-28e3-42ec-bf5c-248ae85e8c4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522238357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.2522238357
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.504894660
Short name T157
Test name
Test status
Simulation time 107229285843 ps
CPU time 552.23 seconds
Started Feb 04 12:58:37 PM PST 24
Finished Feb 04 01:07:50 PM PST 24
Peak memory 194232 kb
Host smart-4cb5e79d-0826-4a75-bae9-1e4ceef3263c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504894660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.504894660
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.3630142261
Short name T45
Test name
Test status
Simulation time 478590143954 ps
CPU time 551.29 seconds
Started Feb 04 12:58:55 PM PST 24
Finished Feb 04 01:08:11 PM PST 24
Peak memory 190612 kb
Host smart-fb480d8c-97ce-44a7-aa57-8ba1b69ffb55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630142261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3630142261
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.2075610734
Short name T215
Test name
Test status
Simulation time 115158278511 ps
CPU time 1854.18 seconds
Started Feb 04 12:59:03 PM PST 24
Finished Feb 04 01:29:58 PM PST 24
Peak memory 190692 kb
Host smart-985ef581-ad75-48a9-bd5d-24b39c7d4946
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075610734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2075610734
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.251153300
Short name T136
Test name
Test status
Simulation time 401666444935 ps
CPU time 923.68 seconds
Started Feb 04 12:57:23 PM PST 24
Finished Feb 04 01:12:48 PM PST 24
Peak memory 194588 kb
Host smart-8395a1c2-eda2-45f8-b634-a1c39684c7f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251153300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
251153300
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_random.3976417574
Short name T325
Test name
Test status
Simulation time 73458831624 ps
CPU time 430.5 seconds
Started Feb 04 12:57:04 PM PST 24
Finished Feb 04 01:04:17 PM PST 24
Peak memory 190528 kb
Host smart-53192f0e-2ec6-493b-8d8f-a6d654bda200
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976417574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3976417574
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.39002249
Short name T219
Test name
Test status
Simulation time 106626592287 ps
CPU time 187.58 seconds
Started Feb 04 12:57:30 PM PST 24
Finished Feb 04 01:00:40 PM PST 24
Peak memory 182508 kb
Host smart-f234a8a8-0289-4fb0-8b24-9936d823fa01
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39002249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.rv_timer_cfg_update_on_fly.39002249
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3461523115
Short name T343
Test name
Test status
Simulation time 7661308873 ps
CPU time 13.64 seconds
Started Feb 04 12:57:28 PM PST 24
Finished Feb 04 12:57:43 PM PST 24
Peak memory 182468 kb
Host smart-a2d6ed76-1311-4971-a8f1-156a559eabd0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461523115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3461523115
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3190980462
Short name T212
Test name
Test status
Simulation time 339517722155 ps
CPU time 1118.71 seconds
Started Feb 04 12:57:40 PM PST 24
Finished Feb 04 01:16:20 PM PST 24
Peak memory 190712 kb
Host smart-c7a4e983-6249-4534-806a-946aba11d558
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190980462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3190980462
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1231799192
Short name T142
Test name
Test status
Simulation time 1017481725530 ps
CPU time 2655.26 seconds
Started Feb 04 12:57:33 PM PST 24
Finished Feb 04 01:41:54 PM PST 24
Peak memory 193876 kb
Host smart-606bdc33-2462-4f05-b8ba-3f35f7585ef1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231799192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1231799192
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.1259008480
Short name T210
Test name
Test status
Simulation time 353306611598 ps
CPU time 1598.61 seconds
Started Feb 04 12:57:58 PM PST 24
Finished Feb 04 01:24:37 PM PST 24
Peak memory 190660 kb
Host smart-53df2bb2-e2d2-47e2-a039-51853b77f0fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259008480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.1259008480
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.4051258310
Short name T36
Test name
Test status
Simulation time 118913954 ps
CPU time 1.05 seconds
Started Feb 04 04:17:22 PM PST 24
Finished Feb 04 04:17:25 PM PST 24
Peak memory 197184 kb
Host smart-61c8dea0-f554-4a80-bae5-ae298a49f338
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051258310 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.4051258310
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1161008458
Short name T88
Test name
Test status
Simulation time 127953663 ps
CPU time 1.45 seconds
Started Feb 04 04:18:25 PM PST 24
Finished Feb 04 04:18:27 PM PST 24
Peak memory 194836 kb
Host smart-69002cfa-57cb-4c2a-a155-26a9d9103a5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161008458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.1161008458
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.6988603
Short name T339
Test name
Test status
Simulation time 36587097309 ps
CPU time 33.7 seconds
Started Feb 04 12:56:46 PM PST 24
Finished Feb 04 12:57:22 PM PST 24
Peak memory 191376 kb
Host smart-57f74d8b-0f7a-4aa9-8d2b-b476a2823acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6988603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.6988603
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/102.rv_timer_random.2185323211
Short name T341
Test name
Test status
Simulation time 406208183878 ps
CPU time 68.44 seconds
Started Feb 04 12:57:56 PM PST 24
Finished Feb 04 12:59:05 PM PST 24
Peak memory 182536 kb
Host smart-127707c8-b79b-4264-8458-22de9a27a481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185323211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2185323211
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.649572804
Short name T102
Test name
Test status
Simulation time 800370876437 ps
CPU time 1572.23 seconds
Started Feb 04 12:58:07 PM PST 24
Finished Feb 04 01:24:24 PM PST 24
Peak memory 190728 kb
Host smart-d398c364-fcf7-417b-9086-363a48ff0988
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649572804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.649572804
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.1345243884
Short name T283
Test name
Test status
Simulation time 228866218875 ps
CPU time 245.69 seconds
Started Feb 04 12:58:21 PM PST 24
Finished Feb 04 01:02:28 PM PST 24
Peak memory 190704 kb
Host smart-11cfad3d-f1d7-4a2b-a9bc-c25ce5a49c36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345243884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1345243884
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.1591553483
Short name T48
Test name
Test status
Simulation time 1132206819418 ps
CPU time 744.94 seconds
Started Feb 04 12:58:08 PM PST 24
Finished Feb 04 01:10:37 PM PST 24
Peak memory 190692 kb
Host smart-e58dd257-ae3d-458c-866c-552560359a83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591553483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1591553483
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.3723035463
Short name T107
Test name
Test status
Simulation time 452013122042 ps
CPU time 630.55 seconds
Started Feb 04 12:58:10 PM PST 24
Finished Feb 04 01:08:42 PM PST 24
Peak memory 190652 kb
Host smart-aace4320-09dd-458d-a5b0-71690075f1a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723035463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3723035463
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3151348027
Short name T182
Test name
Test status
Simulation time 168814471803 ps
CPU time 541.45 seconds
Started Feb 04 12:58:16 PM PST 24
Finished Feb 04 01:07:18 PM PST 24
Peak memory 193752 kb
Host smart-3d80135a-828f-4cd8-895a-0569adaf54fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151348027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3151348027
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3339821357
Short name T300
Test name
Test status
Simulation time 72050206642 ps
CPU time 33.05 seconds
Started Feb 04 12:58:18 PM PST 24
Finished Feb 04 12:58:52 PM PST 24
Peak memory 190596 kb
Host smart-fb3d1622-5d8e-4d15-afb1-8d46813102e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339821357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3339821357
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.1101960099
Short name T129
Test name
Test status
Simulation time 457792325961 ps
CPU time 265.59 seconds
Started Feb 04 12:58:24 PM PST 24
Finished Feb 04 01:02:50 PM PST 24
Peak memory 193684 kb
Host smart-1a92627f-d762-4e84-8b42-889a29b4e3e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101960099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1101960099
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.2164986203
Short name T112
Test name
Test status
Simulation time 75009455232 ps
CPU time 102.81 seconds
Started Feb 04 12:58:15 PM PST 24
Finished Feb 04 12:59:59 PM PST 24
Peak memory 193332 kb
Host smart-88f2aac8-0144-4e9b-ab15-fe68e4085f50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164986203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.2164986203
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.2703487698
Short name T170
Test name
Test status
Simulation time 416006380504 ps
CPU time 467.71 seconds
Started Feb 04 12:58:35 PM PST 24
Finished Feb 04 01:06:24 PM PST 24
Peak memory 190744 kb
Host smart-d965471a-6d7f-47a7-aaaa-40af33988dcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703487698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2703487698
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.1788609969
Short name T164
Test name
Test status
Simulation time 72179299501 ps
CPU time 149.14 seconds
Started Feb 04 12:58:37 PM PST 24
Finished Feb 04 01:01:07 PM PST 24
Peak memory 191844 kb
Host smart-48698efd-5873-422a-a4fe-a895eb3945fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788609969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1788609969
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1203995166
Short name T49
Test name
Test status
Simulation time 80063264327 ps
CPU time 148.45 seconds
Started Feb 04 12:57:08 PM PST 24
Finished Feb 04 12:59:43 PM PST 24
Peak memory 190712 kb
Host smart-8f983feb-820b-4426-a5db-a2a28afbc267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203995166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1203995166
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.469467857
Short name T93
Test name
Test status
Simulation time 87502293212 ps
CPU time 167.07 seconds
Started Feb 04 12:58:41 PM PST 24
Finished Feb 04 01:01:29 PM PST 24
Peak memory 190796 kb
Host smart-c2774e26-a47d-4c13-a512-7bf8c98ac146
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469467857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.469467857
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.738102070
Short name T297
Test name
Test status
Simulation time 87837901922 ps
CPU time 263.99 seconds
Started Feb 04 12:58:46 PM PST 24
Finished Feb 04 01:03:10 PM PST 24
Peak memory 190784 kb
Host smart-19f50efa-02dd-4367-9acc-a2a24c6e9568
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738102070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.738102070
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.3615498832
Short name T351
Test name
Test status
Simulation time 222428057567 ps
CPU time 366.72 seconds
Started Feb 04 12:58:43 PM PST 24
Finished Feb 04 01:04:50 PM PST 24
Peak memory 190776 kb
Host smart-2e12e844-b4c2-4d5b-90fe-9565985e78c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615498832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3615498832
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.1596266955
Short name T165
Test name
Test status
Simulation time 246563012977 ps
CPU time 252.1 seconds
Started Feb 04 12:59:07 PM PST 24
Finished Feb 04 01:03:20 PM PST 24
Peak memory 190676 kb
Host smart-c622fd7a-ff76-4267-93d5-2d779c465695
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596266955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1596266955
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.464600010
Short name T150
Test name
Test status
Simulation time 611354774816 ps
CPU time 576.37 seconds
Started Feb 04 12:57:23 PM PST 24
Finished Feb 04 01:07:01 PM PST 24
Peak memory 182072 kb
Host smart-7643e0fb-6d36-497b-b8e1-ac114a6a9aed
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464600010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.rv_timer_cfg_update_on_fly.464600010
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_random.2559354644
Short name T359
Test name
Test status
Simulation time 149927161143 ps
CPU time 150.55 seconds
Started Feb 04 12:57:23 PM PST 24
Finished Feb 04 12:59:55 PM PST 24
Peak memory 190636 kb
Host smart-e00fd15c-f13c-4b0e-8c32-c291d5498af5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559354644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2559354644
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.523121285
Short name T175
Test name
Test status
Simulation time 16224367756 ps
CPU time 32.8 seconds
Started Feb 04 12:57:15 PM PST 24
Finished Feb 04 12:57:48 PM PST 24
Peak memory 182460 kb
Host smart-313e256f-fcd6-4f23-be68-8d98f26380ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523121285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.523121285
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.1767377622
Short name T178
Test name
Test status
Simulation time 22996403985 ps
CPU time 173.49 seconds
Started Feb 04 12:57:25 PM PST 24
Finished Feb 04 01:00:19 PM PST 24
Peak memory 197288 kb
Host smart-b8817fcd-bab5-4a99-92dc-f6bba5e8ed1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767377622 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.1767377622
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.692543117
Short name T46
Test name
Test status
Simulation time 53596996751 ps
CPU time 117.18 seconds
Started Feb 04 12:57:03 PM PST 24
Finished Feb 04 12:59:03 PM PST 24
Peak memory 190688 kb
Host smart-a9fa1160-14cb-494d-bd82-f2fbd6505818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692543117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.692543117
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1624798844
Short name T187
Test name
Test status
Simulation time 307508140287 ps
CPU time 1931.51 seconds
Started Feb 04 12:57:24 PM PST 24
Finished Feb 04 01:29:37 PM PST 24
Peak memory 182500 kb
Host smart-72b05512-ec0b-4a32-bc4e-20a54bb31b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624798844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1624798844
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2147282399
Short name T303
Test name
Test status
Simulation time 31649597601 ps
CPU time 53.34 seconds
Started Feb 04 12:57:38 PM PST 24
Finished Feb 04 12:58:33 PM PST 24
Peak memory 182188 kb
Host smart-23198f0a-d26b-4323-9a36-cf536cfa5f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147282399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2147282399
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3847310579
Short name T103
Test name
Test status
Simulation time 31748543890 ps
CPU time 52.73 seconds
Started Feb 04 12:57:35 PM PST 24
Finished Feb 04 12:58:32 PM PST 24
Peak memory 182280 kb
Host smart-c0530e95-800c-4b25-b162-776d270c3971
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847310579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3847310579
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.971459367
Short name T284
Test name
Test status
Simulation time 129464178841 ps
CPU time 270.92 seconds
Started Feb 04 12:57:52 PM PST 24
Finished Feb 04 01:02:26 PM PST 24
Peak memory 182332 kb
Host smart-55ec835e-973e-4aa3-8f93-e20a5037a197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971459367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.971459367
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/62.rv_timer_random.3711502682
Short name T272
Test name
Test status
Simulation time 103247141099 ps
CPU time 204.25 seconds
Started Feb 04 12:57:40 PM PST 24
Finished Feb 04 01:01:05 PM PST 24
Peak memory 190716 kb
Host smart-20d28608-c2f0-41e3-89c8-0d7f3f4c73c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711502682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3711502682
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2565751027
Short name T209
Test name
Test status
Simulation time 2051434983072 ps
CPU time 439.34 seconds
Started Feb 04 12:56:54 PM PST 24
Finished Feb 04 01:04:16 PM PST 24
Peak memory 182348 kb
Host smart-a54ce5cf-bab6-4ae7-b072-9e74409b1258
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565751027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2565751027
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3934359162
Short name T437
Test name
Test status
Simulation time 45224184 ps
CPU time 0.74 seconds
Started Feb 04 04:17:03 PM PST 24
Finished Feb 04 04:17:05 PM PST 24
Peak memory 182360 kb
Host smart-c173cf17-89b6-4311-9e05-e910d464d0d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934359162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3934359162
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3023528084
Short name T86
Test name
Test status
Simulation time 40513862 ps
CPU time 1.5 seconds
Started Feb 04 04:17:05 PM PST 24
Finished Feb 04 04:17:07 PM PST 24
Peak memory 190776 kb
Host smart-3532e7dd-2b87-4534-bdb1-d9ef7468a1c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023528084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3023528084
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2183733151
Short name T409
Test name
Test status
Simulation time 44799964 ps
CPU time 0.62 seconds
Started Feb 04 04:17:03 PM PST 24
Finished Feb 04 04:17:05 PM PST 24
Peak memory 182400 kb
Host smart-24f1c074-5617-43bb-9a6f-d856e09c8160
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183733151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2183733151
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1551372221
Short name T37
Test name
Test status
Simulation time 87253257 ps
CPU time 1.32 seconds
Started Feb 04 04:17:04 PM PST 24
Finished Feb 04 04:17:07 PM PST 24
Peak memory 197220 kb
Host smart-6652539f-7260-4b34-9fd5-31333dd18488
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551372221 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.1551372221
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2896705963
Short name T389
Test name
Test status
Simulation time 11999510 ps
CPU time 0.59 seconds
Started Feb 04 04:17:05 PM PST 24
Finished Feb 04 04:17:06 PM PST 24
Peak memory 182040 kb
Host smart-ab16e032-ba7e-41ab-a8d4-21636a1d5360
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896705963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.2896705963
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.348538783
Short name T468
Test name
Test status
Simulation time 15042444 ps
CPU time 0.58 seconds
Started Feb 04 04:17:01 PM PST 24
Finished Feb 04 04:17:05 PM PST 24
Peak memory 181948 kb
Host smart-57547877-000b-4b4a-9b84-3a13fa10ee21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348538783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.348538783
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1185663489
Short name T82
Test name
Test status
Simulation time 16551170 ps
CPU time 0.82 seconds
Started Feb 04 04:17:03 PM PST 24
Finished Feb 04 04:17:05 PM PST 24
Peak memory 192680 kb
Host smart-8e5cf42d-3c2e-4f3b-9488-3a48cc227271
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185663489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1185663489
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1665306591
Short name T443
Test name
Test status
Simulation time 187256791 ps
CPU time 1.78 seconds
Started Feb 04 04:17:14 PM PST 24
Finished Feb 04 04:17:19 PM PST 24
Peak memory 197188 kb
Host smart-c1575bf4-8380-4b77-bca5-822dbf81e9a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665306591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1665306591
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1450624566
Short name T406
Test name
Test status
Simulation time 583495478 ps
CPU time 0.86 seconds
Started Feb 04 04:17:06 PM PST 24
Finished Feb 04 04:17:07 PM PST 24
Peak memory 182748 kb
Host smart-f8a1cba2-4c49-4b52-8e3d-6f1c413cbf08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450624566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1450624566
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1523901003
Short name T387
Test name
Test status
Simulation time 45840856 ps
CPU time 0.78 seconds
Started Feb 04 04:17:29 PM PST 24
Finished Feb 04 04:17:30 PM PST 24
Peak memory 182392 kb
Host smart-7d185bf7-4233-4920-b636-2f5b5f196560
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523901003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1523901003
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2420473590
Short name T14
Test name
Test status
Simulation time 313936903 ps
CPU time 3.2 seconds
Started Feb 04 04:17:23 PM PST 24
Finished Feb 04 04:17:27 PM PST 24
Peak memory 192124 kb
Host smart-f8d5ff6c-4991-4d92-8909-dcf8af66b72f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420473590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2420473590
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2994921823
Short name T391
Test name
Test status
Simulation time 24818233 ps
CPU time 0.65 seconds
Started Feb 04 04:17:19 PM PST 24
Finished Feb 04 04:17:21 PM PST 24
Peak memory 182344 kb
Host smart-8f2d39fc-2b54-4a42-85c1-c15d5d11311e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994921823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2994921823
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.875996495
Short name T70
Test name
Test status
Simulation time 15197058 ps
CPU time 0.6 seconds
Started Feb 04 04:17:19 PM PST 24
Finished Feb 04 04:17:21 PM PST 24
Peak memory 182276 kb
Host smart-0d474f99-39c3-4225-93c6-368a4b214300
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875996495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.875996495
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2946837474
Short name T63
Test name
Test status
Simulation time 64743074 ps
CPU time 0.82 seconds
Started Feb 04 04:17:13 PM PST 24
Finished Feb 04 04:17:18 PM PST 24
Peak memory 191764 kb
Host smart-fd3ac301-349d-4be3-80d4-d229fb148a19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946837474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2946837474
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3116427943
Short name T440
Test name
Test status
Simulation time 48490405 ps
CPU time 2.37 seconds
Started Feb 04 04:17:24 PM PST 24
Finished Feb 04 04:17:27 PM PST 24
Peak memory 197176 kb
Host smart-de74b735-dfdb-4401-accd-cc484543940d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116427943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3116427943
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2981294776
Short name T435
Test name
Test status
Simulation time 149458411 ps
CPU time 0.86 seconds
Started Feb 04 04:17:23 PM PST 24
Finished Feb 04 04:17:25 PM PST 24
Peak memory 182708 kb
Host smart-d9512bba-f640-4f28-9d3b-c7651757a110
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981294776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.2981294776
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1155967992
Short name T448
Test name
Test status
Simulation time 197680071 ps
CPU time 1.35 seconds
Started Feb 04 04:18:17 PM PST 24
Finished Feb 04 04:18:19 PM PST 24
Peak memory 197200 kb
Host smart-f72297fa-7282-4f85-88b3-f71f57429e94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155967992 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.1155967992
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3837939391
Short name T386
Test name
Test status
Simulation time 20032713 ps
CPU time 0.59 seconds
Started Feb 04 04:18:06 PM PST 24
Finished Feb 04 04:18:09 PM PST 24
Peak memory 182096 kb
Host smart-013ead50-30ab-4ac7-a6fa-6f1b1dc54b28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837939391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3837939391
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.171728092
Short name T58
Test name
Test status
Simulation time 41016240 ps
CPU time 0.56 seconds
Started Feb 04 04:18:02 PM PST 24
Finished Feb 04 04:18:07 PM PST 24
Peak memory 181868 kb
Host smart-452e7c49-6565-4ed3-9850-03fa25233a62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171728092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.171728092
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.39462321
Short name T43
Test name
Test status
Simulation time 116996214 ps
CPU time 2.22 seconds
Started Feb 04 04:17:52 PM PST 24
Finished Feb 04 04:17:55 PM PST 24
Peak memory 197236 kb
Host smart-16bb6a43-299a-43fc-8bb3-8abcd3529350
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39462321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.39462321
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3702972836
Short name T475
Test name
Test status
Simulation time 93434220 ps
CPU time 1.13 seconds
Started Feb 04 04:17:52 PM PST 24
Finished Feb 04 04:17:54 PM PST 24
Peak memory 194820 kb
Host smart-8f31f0f9-0fa1-4b8b-9349-20242e2096d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702972836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.3702972836
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.706912965
Short name T380
Test name
Test status
Simulation time 62708775 ps
CPU time 1.02 seconds
Started Feb 04 04:18:05 PM PST 24
Finished Feb 04 04:18:08 PM PST 24
Peak memory 196108 kb
Host smart-8852b726-3dc7-49b2-81fb-3acb9d3d3dcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706912965 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.706912965
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2092089390
Short name T80
Test name
Test status
Simulation time 12267183 ps
CPU time 0.59 seconds
Started Feb 04 04:18:01 PM PST 24
Finished Feb 04 04:18:02 PM PST 24
Peak memory 182344 kb
Host smart-be0a6451-9a08-4b05-a616-eff89d729b6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092089390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2092089390
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.4011277094
Short name T478
Test name
Test status
Simulation time 25564372 ps
CPU time 0.61 seconds
Started Feb 04 04:18:04 PM PST 24
Finished Feb 04 04:18:07 PM PST 24
Peak memory 182248 kb
Host smart-7bddbd74-c68a-4724-b312-334c7ebb6fd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011277094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.4011277094
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1020322577
Short name T414
Test name
Test status
Simulation time 180669574 ps
CPU time 0.86 seconds
Started Feb 04 04:18:17 PM PST 24
Finished Feb 04 04:18:19 PM PST 24
Peak memory 192824 kb
Host smart-108b2e6c-141e-4a3a-b5e5-39df2e254ad8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020322577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.1020322577
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3918148608
Short name T431
Test name
Test status
Simulation time 157083824 ps
CPU time 1.56 seconds
Started Feb 04 04:18:10 PM PST 24
Finished Feb 04 04:18:13 PM PST 24
Peak memory 197244 kb
Host smart-82629019-e33b-41dc-a6f4-5a1771629622
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918148608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3918148608
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3955210469
Short name T90
Test name
Test status
Simulation time 76275315 ps
CPU time 0.9 seconds
Started Feb 04 04:18:04 PM PST 24
Finished Feb 04 04:18:08 PM PST 24
Peak memory 182692 kb
Host smart-c0c23c5d-3b79-4ce3-8e4e-aacd2f7b7b1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955210469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3955210469
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.464067848
Short name T403
Test name
Test status
Simulation time 145449953 ps
CPU time 0.98 seconds
Started Feb 04 04:18:19 PM PST 24
Finished Feb 04 04:18:20 PM PST 24
Peak memory 196496 kb
Host smart-f8ddb5aa-5018-469c-a364-6c61ccc65ca2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464067848 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.464067848
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1266914395
Short name T79
Test name
Test status
Simulation time 53991322 ps
CPU time 0.63 seconds
Started Feb 04 04:18:03 PM PST 24
Finished Feb 04 04:18:07 PM PST 24
Peak memory 182404 kb
Host smart-13ff06f9-e68c-45ff-b53f-33fd48bde13f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266914395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1266914395
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3653476752
Short name T397
Test name
Test status
Simulation time 103101047 ps
CPU time 0.58 seconds
Started Feb 04 04:18:12 PM PST 24
Finished Feb 04 04:18:17 PM PST 24
Peak memory 182076 kb
Host smart-5a194817-d64e-4e62-9746-826f117e8c41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653476752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3653476752
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1683222793
Short name T470
Test name
Test status
Simulation time 61996336 ps
CPU time 0.73 seconds
Started Feb 04 04:18:20 PM PST 24
Finished Feb 04 04:18:22 PM PST 24
Peak memory 191348 kb
Host smart-4c1da486-36fe-4ef6-88ac-1afbf5d250b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683222793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1683222793
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.4121774620
Short name T438
Test name
Test status
Simulation time 88451662 ps
CPU time 1.84 seconds
Started Feb 04 04:18:09 PM PST 24
Finished Feb 04 04:18:12 PM PST 24
Peak memory 196876 kb
Host smart-5aa28c61-5798-4042-86ed-a2351841f0b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121774620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.4121774620
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.375766889
Short name T452
Test name
Test status
Simulation time 53036642 ps
CPU time 0.93 seconds
Started Feb 04 04:18:12 PM PST 24
Finished Feb 04 04:18:17 PM PST 24
Peak memory 192988 kb
Host smart-c84a8c3e-c830-41e7-b199-e0c15b2d404e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375766889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_in
tg_err.375766889
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2435304856
Short name T429
Test name
Test status
Simulation time 96699824 ps
CPU time 1.49 seconds
Started Feb 04 04:18:17 PM PST 24
Finished Feb 04 04:18:20 PM PST 24
Peak memory 197188 kb
Host smart-84ace24c-39f6-4888-b79a-d5207bd230a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435304856 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2435304856
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2802092890
Short name T72
Test name
Test status
Simulation time 35400293 ps
CPU time 0.65 seconds
Started Feb 04 04:18:17 PM PST 24
Finished Feb 04 04:18:18 PM PST 24
Peak memory 182392 kb
Host smart-5826e1b1-824b-48d0-848e-ffbea72501de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802092890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2802092890
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3432921080
Short name T394
Test name
Test status
Simulation time 18962280 ps
CPU time 0.64 seconds
Started Feb 04 04:18:15 PM PST 24
Finished Feb 04 04:18:17 PM PST 24
Peak memory 182240 kb
Host smart-14b83098-1b8a-4944-88c3-29f02ea4960a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432921080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3432921080
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3438149202
Short name T84
Test name
Test status
Simulation time 80076407 ps
CPU time 0.85 seconds
Started Feb 04 04:18:16 PM PST 24
Finished Feb 04 04:18:18 PM PST 24
Peak memory 192984 kb
Host smart-933277df-6ba9-4fd5-91af-56e3d505d85d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438149202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.3438149202
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3761330100
Short name T412
Test name
Test status
Simulation time 32809308 ps
CPU time 1.66 seconds
Started Feb 04 04:18:16 PM PST 24
Finished Feb 04 04:18:19 PM PST 24
Peak memory 197216 kb
Host smart-9ba853e3-ed59-44f9-a87f-15e93299d197
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761330100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3761330100
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1000353634
Short name T450
Test name
Test status
Simulation time 19436212 ps
CPU time 1.09 seconds
Started Feb 04 04:18:20 PM PST 24
Finished Feb 04 04:18:22 PM PST 24
Peak memory 196836 kb
Host smart-9b0aba97-7377-4172-a910-d015a21a4ed4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000353634 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.1000353634
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.4191530991
Short name T78
Test name
Test status
Simulation time 16714064 ps
CPU time 0.6 seconds
Started Feb 04 04:18:19 PM PST 24
Finished Feb 04 04:18:20 PM PST 24
Peak memory 182404 kb
Host smart-0e711d82-e4f6-4c7f-83fc-9bf6cba0e542
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191530991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.4191530991
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.4022755521
Short name T467
Test name
Test status
Simulation time 46401458 ps
CPU time 0.55 seconds
Started Feb 04 04:18:22 PM PST 24
Finished Feb 04 04:18:23 PM PST 24
Peak memory 182184 kb
Host smart-80af8443-5cfa-46af-ad2d-65e4c8b2c7e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022755521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.4022755521
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1147507051
Short name T41
Test name
Test status
Simulation time 59692211 ps
CPU time 0.63 seconds
Started Feb 04 04:18:22 PM PST 24
Finished Feb 04 04:18:23 PM PST 24
Peak memory 190856 kb
Host smart-e6c8ad9e-9cc8-446c-9101-5ecb427da462
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147507051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.1147507051
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1031570692
Short name T436
Test name
Test status
Simulation time 82035541 ps
CPU time 1.14 seconds
Started Feb 04 04:18:13 PM PST 24
Finished Feb 04 04:18:18 PM PST 24
Peak memory 196056 kb
Host smart-1ff42f33-ee23-4a0c-b89d-d8d41aabd80d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031570692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1031570692
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1339749466
Short name T32
Test name
Test status
Simulation time 104943862 ps
CPU time 1.2 seconds
Started Feb 04 04:18:18 PM PST 24
Finished Feb 04 04:18:20 PM PST 24
Peak memory 182720 kb
Host smart-9a9d0260-268e-4bdb-b415-95d3c1c68f26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339749466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1339749466
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3680895875
Short name T453
Test name
Test status
Simulation time 14409600 ps
CPU time 0.65 seconds
Started Feb 04 04:18:22 PM PST 24
Finished Feb 04 04:18:23 PM PST 24
Peak memory 192508 kb
Host smart-a533ef66-baef-4444-8031-39ed9be071e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680895875 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3680895875
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1087435192
Short name T423
Test name
Test status
Simulation time 111088009 ps
CPU time 0.59 seconds
Started Feb 04 04:18:21 PM PST 24
Finished Feb 04 04:18:22 PM PST 24
Peak memory 182376 kb
Host smart-2ab6400e-1a13-4b76-9927-6b8d57c33283
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087435192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1087435192
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.497210771
Short name T434
Test name
Test status
Simulation time 38729619 ps
CPU time 0.63 seconds
Started Feb 04 04:18:25 PM PST 24
Finished Feb 04 04:18:27 PM PST 24
Peak memory 182204 kb
Host smart-e567d627-f34e-4908-91ca-37cc7577701e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497210771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.497210771
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1609134618
Short name T59
Test name
Test status
Simulation time 28337024 ps
CPU time 0.79 seconds
Started Feb 04 04:18:21 PM PST 24
Finished Feb 04 04:18:23 PM PST 24
Peak memory 191340 kb
Host smart-c69af680-fdc3-4130-ba0f-f167bad2e0f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609134618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.1609134618
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1329730082
Short name T35
Test name
Test status
Simulation time 51812420 ps
CPU time 2.65 seconds
Started Feb 04 04:18:24 PM PST 24
Finished Feb 04 04:18:28 PM PST 24
Peak memory 197180 kb
Host smart-e6001a14-d754-4c08-ad6d-7e183a864baa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329730082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1329730082
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2447210172
Short name T457
Test name
Test status
Simulation time 403466930 ps
CPU time 1.49 seconds
Started Feb 04 04:18:27 PM PST 24
Finished Feb 04 04:18:29 PM PST 24
Peak memory 194960 kb
Host smart-d1d8de32-0ce6-4668-9743-3a6fb4b81675
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447210172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2447210172
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.4202502233
Short name T479
Test name
Test status
Simulation time 32154781 ps
CPU time 1.59 seconds
Started Feb 04 04:18:24 PM PST 24
Finished Feb 04 04:18:26 PM PST 24
Peak memory 197240 kb
Host smart-34356ec0-01bc-4045-8bc5-0615db327b43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202502233 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.4202502233
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2178525871
Short name T40
Test name
Test status
Simulation time 14202905 ps
CPU time 0.54 seconds
Started Feb 04 04:18:19 PM PST 24
Finished Feb 04 04:18:21 PM PST 24
Peak memory 182348 kb
Host smart-c790aecb-688e-4460-b906-cde9de26c590
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178525871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.2178525871
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.248537156
Short name T54
Test name
Test status
Simulation time 50018429 ps
CPU time 0.58 seconds
Started Feb 04 04:18:19 PM PST 24
Finished Feb 04 04:18:20 PM PST 24
Peak memory 182212 kb
Host smart-e95f110a-4321-46bd-b025-37b4d22ff62c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248537156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.248537156
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2972230081
Short name T85
Test name
Test status
Simulation time 44587273 ps
CPU time 0.6 seconds
Started Feb 04 04:18:22 PM PST 24
Finished Feb 04 04:18:23 PM PST 24
Peak memory 191612 kb
Host smart-c5311535-fcd3-42b5-b18c-c000ddc5d5d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972230081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2972230081
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1367446231
Short name T384
Test name
Test status
Simulation time 1628522502 ps
CPU time 2.55 seconds
Started Feb 04 04:18:24 PM PST 24
Finished Feb 04 04:18:27 PM PST 24
Peak memory 197168 kb
Host smart-3c37f7ce-c2ca-4161-9c0c-09d21bb7004c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367446231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1367446231
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.65388441
Short name T430
Test name
Test status
Simulation time 20936148 ps
CPU time 0.74 seconds
Started Feb 04 04:18:21 PM PST 24
Finished Feb 04 04:18:22 PM PST 24
Peak memory 195140 kb
Host smart-b1704384-0acb-4081-85a2-9db076588380
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65388441 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.65388441
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3525842551
Short name T61
Test name
Test status
Simulation time 14387277 ps
CPU time 0.59 seconds
Started Feb 04 04:18:20 PM PST 24
Finished Feb 04 04:18:21 PM PST 24
Peak memory 182388 kb
Host smart-450706b6-e95c-4486-af8d-264185580fa7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525842551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.3525842551
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.4187891756
Short name T458
Test name
Test status
Simulation time 74853632 ps
CPU time 0.56 seconds
Started Feb 04 04:18:25 PM PST 24
Finished Feb 04 04:18:27 PM PST 24
Peak memory 182136 kb
Host smart-850fe036-2988-47d1-bc12-852deef83e3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187891756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.4187891756
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1845308928
Short name T460
Test name
Test status
Simulation time 64402412 ps
CPU time 0.9 seconds
Started Feb 04 04:18:25 PM PST 24
Finished Feb 04 04:18:27 PM PST 24
Peak memory 192996 kb
Host smart-c420c7c6-30ed-4d62-8a10-b94019d4783b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845308928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.1845308928
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1944847191
Short name T432
Test name
Test status
Simulation time 205934122 ps
CPU time 2.38 seconds
Started Feb 04 04:18:24 PM PST 24
Finished Feb 04 04:18:28 PM PST 24
Peak memory 197208 kb
Host smart-760451fe-d8bf-41f1-8bee-11a184790bc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944847191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1944847191
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1614086844
Short name T33
Test name
Test status
Simulation time 47341566 ps
CPU time 0.99 seconds
Started Feb 04 04:18:24 PM PST 24
Finished Feb 04 04:18:26 PM PST 24
Peak memory 193320 kb
Host smart-6431a0d7-f21e-46e0-b5b6-39d5d83b4b6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614086844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1614086844
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3304221267
Short name T395
Test name
Test status
Simulation time 24585530 ps
CPU time 0.86 seconds
Started Feb 04 04:18:31 PM PST 24
Finished Feb 04 04:18:33 PM PST 24
Peak memory 195644 kb
Host smart-6c2e2d85-eeb4-4165-8b88-bac7c946dde3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304221267 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3304221267
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.488780459
Short name T73
Test name
Test status
Simulation time 49718484 ps
CPU time 0.58 seconds
Started Feb 04 04:18:24 PM PST 24
Finished Feb 04 04:18:26 PM PST 24
Peak memory 182364 kb
Host smart-839e6537-d060-4243-a8d5-ad130fa51fd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488780459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.488780459
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.19864737
Short name T369
Test name
Test status
Simulation time 15327733 ps
CPU time 0.59 seconds
Started Feb 04 04:18:21 PM PST 24
Finished Feb 04 04:18:23 PM PST 24
Peak memory 182204 kb
Host smart-66dee01a-fd05-4d2c-9d68-2dfc5dc5c2d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19864737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.19864737
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3252961344
Short name T425
Test name
Test status
Simulation time 19533588 ps
CPU time 0.63 seconds
Started Feb 04 04:18:29 PM PST 24
Finished Feb 04 04:18:30 PM PST 24
Peak memory 191548 kb
Host smart-acaa02a1-c2d6-4b41-bae4-81f10d021c26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252961344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.3252961344
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3403095632
Short name T418
Test name
Test status
Simulation time 1453213306 ps
CPU time 2.04 seconds
Started Feb 04 04:18:22 PM PST 24
Finished Feb 04 04:18:25 PM PST 24
Peak memory 197220 kb
Host smart-d879c333-db94-4f51-8950-c52445042a1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403095632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3403095632
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1099678195
Short name T92
Test name
Test status
Simulation time 137256357 ps
CPU time 1.12 seconds
Started Feb 04 04:18:24 PM PST 24
Finished Feb 04 04:18:26 PM PST 24
Peak memory 194524 kb
Host smart-1b62f6e6-f143-42b5-8cbb-b80662896608
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099678195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1099678195
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1152750663
Short name T408
Test name
Test status
Simulation time 20566752 ps
CPU time 0.69 seconds
Started Feb 04 04:18:37 PM PST 24
Finished Feb 04 04:18:39 PM PST 24
Peak memory 193488 kb
Host smart-b15a206d-8c9f-4a2f-b2b2-57e0947187a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152750663 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1152750663
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1967075345
Short name T77
Test name
Test status
Simulation time 14527634 ps
CPU time 0.6 seconds
Started Feb 04 04:18:32 PM PST 24
Finished Feb 04 04:18:34 PM PST 24
Peak memory 182340 kb
Host smart-66f0de21-10ba-4d98-8561-5a4877770eb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967075345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1967075345
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.179028550
Short name T461
Test name
Test status
Simulation time 55406962 ps
CPU time 0.59 seconds
Started Feb 04 04:18:40 PM PST 24
Finished Feb 04 04:18:45 PM PST 24
Peak memory 182192 kb
Host smart-6f8d178c-0fa8-4c36-953a-c364aec926d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179028550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.179028550
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2202421184
Short name T83
Test name
Test status
Simulation time 36186885 ps
CPU time 0.73 seconds
Started Feb 04 04:18:43 PM PST 24
Finished Feb 04 04:18:46 PM PST 24
Peak memory 190876 kb
Host smart-adf46da2-5f20-4d8c-8da3-ab36e40f006e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202421184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2202421184
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1400144103
Short name T421
Test name
Test status
Simulation time 35688446 ps
CPU time 1.82 seconds
Started Feb 04 04:18:27 PM PST 24
Finished Feb 04 04:18:30 PM PST 24
Peak memory 197212 kb
Host smart-3bbaa9ea-ab04-47b1-9cad-e4cf512293cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400144103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1400144103
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1282611028
Short name T417
Test name
Test status
Simulation time 207132233 ps
CPU time 0.82 seconds
Started Feb 04 04:18:30 PM PST 24
Finished Feb 04 04:18:31 PM PST 24
Peak memory 193240 kb
Host smart-e50c5d7d-4207-4d87-b9c6-4e831058ab0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282611028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1282611028
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2346439660
Short name T87
Test name
Test status
Simulation time 196999301 ps
CPU time 2.55 seconds
Started Feb 04 04:17:42 PM PST 24
Finished Feb 04 04:17:46 PM PST 24
Peak memory 190676 kb
Host smart-0412c162-6bac-4dc4-88f8-2f95c523a64a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346439660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.2346439660
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3421651639
Short name T42
Test name
Test status
Simulation time 27699252 ps
CPU time 0.57 seconds
Started Feb 04 04:17:34 PM PST 24
Finished Feb 04 04:17:37 PM PST 24
Peak memory 181728 kb
Host smart-c8b9b87a-5187-447d-9f5e-3de519ed5e1a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421651639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.3421651639
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2536293615
Short name T419
Test name
Test status
Simulation time 48899506 ps
CPU time 0.72 seconds
Started Feb 04 04:17:38 PM PST 24
Finished Feb 04 04:17:44 PM PST 24
Peak memory 193492 kb
Host smart-1e271640-d2f6-43fd-b5de-0bf0d8c93355
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536293615 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2536293615
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2391278111
Short name T474
Test name
Test status
Simulation time 44967817 ps
CPU time 0.57 seconds
Started Feb 04 04:17:26 PM PST 24
Finished Feb 04 04:17:27 PM PST 24
Peak memory 182376 kb
Host smart-3d425850-3356-4ce2-97d5-ade3aeee8f5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391278111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2391278111
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1115088107
Short name T462
Test name
Test status
Simulation time 39026630 ps
CPU time 0.6 seconds
Started Feb 04 04:17:32 PM PST 24
Finished Feb 04 04:17:36 PM PST 24
Peak memory 182164 kb
Host smart-1ea232e0-7599-4fdb-97d5-3dc929b5af5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115088107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1115088107
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2569172073
Short name T454
Test name
Test status
Simulation time 31239991 ps
CPU time 0.88 seconds
Started Feb 04 04:17:54 PM PST 24
Finished Feb 04 04:17:56 PM PST 24
Peak memory 192740 kb
Host smart-98683887-6fee-4de2-8772-964d4cdde0ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569172073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2569172073
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3854674755
Short name T400
Test name
Test status
Simulation time 282021916 ps
CPU time 1.68 seconds
Started Feb 04 04:17:23 PM PST 24
Finished Feb 04 04:17:26 PM PST 24
Peak memory 197200 kb
Host smart-bdc5dcd7-f610-4839-8df2-13397ed39cab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854674755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.3854674755
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3747772590
Short name T416
Test name
Test status
Simulation time 128239705 ps
CPU time 1.44 seconds
Started Feb 04 04:17:24 PM PST 24
Finished Feb 04 04:17:27 PM PST 24
Peak memory 194972 kb
Host smart-78a60d8e-3e90-4ceb-87bd-47ebb798c39e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747772590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.3747772590
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1326234603
Short name T466
Test name
Test status
Simulation time 11735401 ps
CPU time 0.56 seconds
Started Feb 04 04:18:34 PM PST 24
Finished Feb 04 04:18:37 PM PST 24
Peak memory 181668 kb
Host smart-2cfbc1a1-adaa-4ee2-9a84-e1a61123a4b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326234603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1326234603
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1506905863
Short name T455
Test name
Test status
Simulation time 20857818 ps
CPU time 0.55 seconds
Started Feb 04 04:18:34 PM PST 24
Finished Feb 04 04:18:37 PM PST 24
Peak memory 181648 kb
Host smart-8f14e929-619f-48cc-941a-9102bd7639b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506905863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1506905863
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3451977449
Short name T62
Test name
Test status
Simulation time 35432652 ps
CPU time 0.65 seconds
Started Feb 04 04:18:41 PM PST 24
Finished Feb 04 04:18:45 PM PST 24
Peak memory 181720 kb
Host smart-4ad88c10-6666-446e-8a25-b3046f9947c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451977449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3451977449
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3375015853
Short name T378
Test name
Test status
Simulation time 55258424 ps
CPU time 0.59 seconds
Started Feb 04 04:18:38 PM PST 24
Finished Feb 04 04:18:44 PM PST 24
Peak memory 182224 kb
Host smart-d441d673-c4d3-4090-9390-6060eefac83f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375015853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3375015853
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1105546539
Short name T371
Test name
Test status
Simulation time 112791660 ps
CPU time 0.59 seconds
Started Feb 04 04:18:37 PM PST 24
Finished Feb 04 04:18:39 PM PST 24
Peak memory 182208 kb
Host smart-4f775876-f365-4c8c-a7b0-9ebef4861603
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105546539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1105546539
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2214845626
Short name T393
Test name
Test status
Simulation time 13565204 ps
CPU time 0.55 seconds
Started Feb 04 04:18:34 PM PST 24
Finished Feb 04 04:18:37 PM PST 24
Peak memory 181820 kb
Host smart-ad99cb08-ba63-483a-ae51-f2ccb80f5f09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214845626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2214845626
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3748789882
Short name T439
Test name
Test status
Simulation time 118218241 ps
CPU time 0.55 seconds
Started Feb 04 04:18:33 PM PST 24
Finished Feb 04 04:18:34 PM PST 24
Peak memory 182184 kb
Host smart-80e38d12-a7ce-43e6-bbd1-a3b39f7530ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748789882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.3748789882
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.976214736
Short name T68
Test name
Test status
Simulation time 44536677 ps
CPU time 0.58 seconds
Started Feb 04 04:18:37 PM PST 24
Finished Feb 04 04:18:42 PM PST 24
Peak memory 182356 kb
Host smart-e5da9a56-f5d6-4f1c-b1e8-37386d53dbca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976214736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.976214736
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1311485192
Short name T377
Test name
Test status
Simulation time 11342236 ps
CPU time 0.6 seconds
Started Feb 04 04:18:39 PM PST 24
Finished Feb 04 04:18:45 PM PST 24
Peak memory 182204 kb
Host smart-bb63cfdd-8127-405d-b9b4-942ad6509f46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311485192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1311485192
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1917393388
Short name T383
Test name
Test status
Simulation time 22534842 ps
CPU time 0.65 seconds
Started Feb 04 04:18:41 PM PST 24
Finished Feb 04 04:18:45 PM PST 24
Peak memory 182136 kb
Host smart-09e972e4-1e6c-4223-a522-37772dd15792
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917393388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1917393388
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1414776130
Short name T64
Test name
Test status
Simulation time 61638104 ps
CPU time 0.79 seconds
Started Feb 04 04:17:37 PM PST 24
Finished Feb 04 04:17:44 PM PST 24
Peak memory 191628 kb
Host smart-34956c4c-519e-4d22-8b90-be5123bd3228
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414776130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.1414776130
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3101848777
Short name T449
Test name
Test status
Simulation time 382699673 ps
CPU time 1.68 seconds
Started Feb 04 04:17:40 PM PST 24
Finished Feb 04 04:17:45 PM PST 24
Peak memory 190780 kb
Host smart-5b9914a5-3bad-4af7-bef8-d04a63393922
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101848777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.3101848777
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1425481275
Short name T74
Test name
Test status
Simulation time 84619596 ps
CPU time 0.59 seconds
Started Feb 04 04:17:36 PM PST 24
Finished Feb 04 04:17:44 PM PST 24
Peak memory 182384 kb
Host smart-745c5e48-f157-423b-8c58-11bea447e37d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425481275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.1425481275
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2071942881
Short name T407
Test name
Test status
Simulation time 16508648 ps
CPU time 0.75 seconds
Started Feb 04 04:17:34 PM PST 24
Finished Feb 04 04:17:36 PM PST 24
Peak memory 194856 kb
Host smart-76fbf36a-14c9-44c7-b2c7-5955ec3f4f38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071942881 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2071942881
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2443367258
Short name T76
Test name
Test status
Simulation time 14677934 ps
CPU time 0.62 seconds
Started Feb 04 04:17:40 PM PST 24
Finished Feb 04 04:17:44 PM PST 24
Peak memory 182372 kb
Host smart-354ae8ec-201c-4128-805e-76a62fa2de63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443367258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2443367258
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.992007208
Short name T399
Test name
Test status
Simulation time 68412149 ps
CPU time 0.55 seconds
Started Feb 04 04:17:33 PM PST 24
Finished Feb 04 04:17:36 PM PST 24
Peak memory 182184 kb
Host smart-47e0d580-31f3-4348-b192-b07199defc16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992007208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.992007208
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.4257750168
Short name T413
Test name
Test status
Simulation time 33814768 ps
CPU time 0.87 seconds
Started Feb 04 04:17:43 PM PST 24
Finished Feb 04 04:17:46 PM PST 24
Peak memory 191360 kb
Host smart-ae6bc82c-15dd-4fad-acd9-41106e1c1acb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257750168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.4257750168
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3351307647
Short name T388
Test name
Test status
Simulation time 133198757 ps
CPU time 2.87 seconds
Started Feb 04 04:17:28 PM PST 24
Finished Feb 04 04:17:31 PM PST 24
Peak memory 197160 kb
Host smart-1a5dcf6c-e70a-471e-90e3-53cb3e11a283
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351307647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3351307647
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.518028013
Short name T89
Test name
Test status
Simulation time 1258596007 ps
CPU time 1.39 seconds
Started Feb 04 04:17:36 PM PST 24
Finished Feb 04 04:17:42 PM PST 24
Peak memory 182792 kb
Host smart-ae382ed6-d4fb-4e39-902e-8b9c43fcd983
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518028013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_int
g_err.518028013
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1652970624
Short name T428
Test name
Test status
Simulation time 17452119 ps
CPU time 0.63 seconds
Started Feb 04 04:18:35 PM PST 24
Finished Feb 04 04:18:38 PM PST 24
Peak memory 182176 kb
Host smart-b4148e8f-3e11-4bc8-a819-5a474ed88067
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652970624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1652970624
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2059032315
Short name T381
Test name
Test status
Simulation time 20901374 ps
CPU time 0.54 seconds
Started Feb 04 04:18:34 PM PST 24
Finished Feb 04 04:18:37 PM PST 24
Peak memory 181864 kb
Host smart-8b3d0e53-2bd5-4d9a-bde5-37c301305cd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059032315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2059032315
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.4088436184
Short name T401
Test name
Test status
Simulation time 107943682 ps
CPU time 0.63 seconds
Started Feb 04 04:18:36 PM PST 24
Finished Feb 04 04:18:38 PM PST 24
Peak memory 182236 kb
Host smart-311c589a-fe7d-4415-8497-54e3aa4fd26c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088436184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.4088436184
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3036906217
Short name T402
Test name
Test status
Simulation time 36912808 ps
CPU time 0.58 seconds
Started Feb 04 04:18:38 PM PST 24
Finished Feb 04 04:18:44 PM PST 24
Peak memory 182144 kb
Host smart-76657758-037d-42ee-9887-dbd6ab69a408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036906217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3036906217
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2142618632
Short name T469
Test name
Test status
Simulation time 114424947 ps
CPU time 0.57 seconds
Started Feb 04 04:18:41 PM PST 24
Finished Feb 04 04:18:45 PM PST 24
Peak memory 182168 kb
Host smart-2e61eee6-4e1c-49fb-8aaa-91f761c64ee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142618632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2142618632
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2707755825
Short name T56
Test name
Test status
Simulation time 14036883 ps
CPU time 0.64 seconds
Started Feb 04 04:18:38 PM PST 24
Finished Feb 04 04:18:45 PM PST 24
Peak memory 181608 kb
Host smart-92c345f8-3897-4431-8672-a77618943370
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707755825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2707755825
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1752229235
Short name T441
Test name
Test status
Simulation time 13410993 ps
CPU time 0.58 seconds
Started Feb 04 04:18:39 PM PST 24
Finished Feb 04 04:18:45 PM PST 24
Peak memory 182196 kb
Host smart-6385f37a-4113-44b5-8486-3f1147c4cec9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752229235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1752229235
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.4270716572
Short name T473
Test name
Test status
Simulation time 14238609 ps
CPU time 0.57 seconds
Started Feb 04 04:18:41 PM PST 24
Finished Feb 04 04:18:45 PM PST 24
Peak memory 181616 kb
Host smart-20bf0890-7077-4d9d-a0ae-0fcbdb725792
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270716572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.4270716572
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3615940369
Short name T376
Test name
Test status
Simulation time 33730242 ps
CPU time 0.63 seconds
Started Feb 04 04:18:41 PM PST 24
Finished Feb 04 04:18:45 PM PST 24
Peak memory 182156 kb
Host smart-0e7f7ed3-8f6e-4756-a111-f4720837acb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615940369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3615940369
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1341800709
Short name T404
Test name
Test status
Simulation time 58423540 ps
CPU time 0.56 seconds
Started Feb 04 04:18:38 PM PST 24
Finished Feb 04 04:18:45 PM PST 24
Peak memory 181796 kb
Host smart-8ba6cc02-34b4-44f7-b51b-25a1a4cf9919
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341800709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1341800709
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1837018937
Short name T60
Test name
Test status
Simulation time 57397841 ps
CPU time 0.89 seconds
Started Feb 04 04:17:50 PM PST 24
Finished Feb 04 04:17:52 PM PST 24
Peak memory 182360 kb
Host smart-3be59c2d-96ed-4267-b903-9fba6d6fe2ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837018937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1837018937
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3841069614
Short name T65
Test name
Test status
Simulation time 102653394 ps
CPU time 1.44 seconds
Started Feb 04 04:17:38 PM PST 24
Finished Feb 04 04:17:45 PM PST 24
Peak memory 191880 kb
Host smart-f2dfdb36-8170-47d2-bba0-0eb3499e2b0f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841069614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3841069614
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1996428007
Short name T433
Test name
Test status
Simulation time 17763354 ps
CPU time 0.63 seconds
Started Feb 04 04:17:39 PM PST 24
Finished Feb 04 04:17:44 PM PST 24
Peak memory 182388 kb
Host smart-9b3258d0-7d21-4a69-a29a-f5d35f3d396f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996428007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1996428007
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1357549666
Short name T477
Test name
Test status
Simulation time 27855896 ps
CPU time 1.36 seconds
Started Feb 04 04:17:44 PM PST 24
Finished Feb 04 04:17:47 PM PST 24
Peak memory 197148 kb
Host smart-4771f694-4c40-480c-b9d7-010c1e709596
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357549666 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1357549666
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1619371164
Short name T451
Test name
Test status
Simulation time 17299611 ps
CPU time 0.71 seconds
Started Feb 04 04:17:45 PM PST 24
Finished Feb 04 04:17:47 PM PST 24
Peak memory 182312 kb
Host smart-50e64d43-f00b-483d-8cab-ad2c57b961bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619371164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1619371164
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2538256545
Short name T472
Test name
Test status
Simulation time 62244302 ps
CPU time 0.57 seconds
Started Feb 04 04:17:35 PM PST 24
Finished Feb 04 04:17:37 PM PST 24
Peak memory 182124 kb
Host smart-322772ec-012f-4334-8ef0-baa6c3efd627
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538256545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2538256545
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.895467637
Short name T444
Test name
Test status
Simulation time 32531162 ps
CPU time 0.73 seconds
Started Feb 04 04:17:33 PM PST 24
Finished Feb 04 04:17:36 PM PST 24
Peak memory 191352 kb
Host smart-152c83f9-5a41-4e86-8dba-0e30f5997b74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895467637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.895467637
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1334744474
Short name T392
Test name
Test status
Simulation time 158168250 ps
CPU time 2.78 seconds
Started Feb 04 04:17:36 PM PST 24
Finished Feb 04 04:17:45 PM PST 24
Peak memory 197252 kb
Host smart-ceeadfc0-3efa-482f-9ec9-aa75b4808ca7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334744474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1334744474
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2795903657
Short name T415
Test name
Test status
Simulation time 76550875 ps
CPU time 0.99 seconds
Started Feb 04 04:17:38 PM PST 24
Finished Feb 04 04:17:45 PM PST 24
Peak memory 192776 kb
Host smart-9b8a2c93-bd61-490d-868e-76da310dd040
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795903657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2795903657
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2440101201
Short name T379
Test name
Test status
Simulation time 46296699 ps
CPU time 0.54 seconds
Started Feb 04 04:18:40 PM PST 24
Finished Feb 04 04:18:45 PM PST 24
Peak memory 181596 kb
Host smart-e9df430c-b5b9-435d-a1e9-f3c64e486763
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440101201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2440101201
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3458576979
Short name T465
Test name
Test status
Simulation time 54821514 ps
CPU time 0.65 seconds
Started Feb 04 04:18:43 PM PST 24
Finished Feb 04 04:18:46 PM PST 24
Peak memory 182060 kb
Host smart-0eea6267-31e8-4498-997c-f53cb5355933
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458576979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3458576979
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1917908411
Short name T373
Test name
Test status
Simulation time 15354704 ps
CPU time 0.59 seconds
Started Feb 04 04:18:38 PM PST 24
Finished Feb 04 04:18:45 PM PST 24
Peak memory 182216 kb
Host smart-03eb67dd-3981-44de-ab41-68a5a7b0dcd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917908411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1917908411
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.4161480732
Short name T374
Test name
Test status
Simulation time 31358853 ps
CPU time 0.59 seconds
Started Feb 04 04:18:36 PM PST 24
Finished Feb 04 04:18:38 PM PST 24
Peak memory 182296 kb
Host smart-486de1e4-0ae2-46ad-b326-402385d020b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161480732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.4161480732
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3918630956
Short name T372
Test name
Test status
Simulation time 19951987 ps
CPU time 0.55 seconds
Started Feb 04 04:18:35 PM PST 24
Finished Feb 04 04:18:38 PM PST 24
Peak memory 182296 kb
Host smart-d6ffdd48-d5e5-4c31-9554-614e490e2079
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918630956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3918630956
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.4131930978
Short name T385
Test name
Test status
Simulation time 32456105 ps
CPU time 0.57 seconds
Started Feb 04 04:18:39 PM PST 24
Finished Feb 04 04:18:45 PM PST 24
Peak memory 182308 kb
Host smart-240c2871-9e75-4049-8e26-c444e58fcb4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131930978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.4131930978
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.4259890732
Short name T71
Test name
Test status
Simulation time 23669217 ps
CPU time 0.56 seconds
Started Feb 04 04:18:35 PM PST 24
Finished Feb 04 04:18:38 PM PST 24
Peak memory 181660 kb
Host smart-62d0851b-06f7-4d31-890a-6fd8a2aa6263
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259890732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.4259890732
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2710407988
Short name T370
Test name
Test status
Simulation time 35733563 ps
CPU time 0.58 seconds
Started Feb 04 04:18:40 PM PST 24
Finished Feb 04 04:18:45 PM PST 24
Peak memory 182180 kb
Host smart-666056f4-f79c-4e5e-9814-fc1a48feecc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710407988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2710407988
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1419599308
Short name T445
Test name
Test status
Simulation time 23176910 ps
CPU time 0.61 seconds
Started Feb 04 04:18:56 PM PST 24
Finished Feb 04 04:18:59 PM PST 24
Peak memory 182272 kb
Host smart-902bf2a6-2389-4da0-9569-a14df0e6bbe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419599308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1419599308
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.774976665
Short name T69
Test name
Test status
Simulation time 42493051 ps
CPU time 0.56 seconds
Started Feb 04 04:18:44 PM PST 24
Finished Feb 04 04:18:47 PM PST 24
Peak memory 181680 kb
Host smart-5965f501-1dfd-4daa-8051-245fa58835e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774976665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.774976665
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.4159853629
Short name T447
Test name
Test status
Simulation time 11255008 ps
CPU time 0.66 seconds
Started Feb 04 04:17:50 PM PST 24
Finished Feb 04 04:17:52 PM PST 24
Peak memory 192584 kb
Host smart-495b2047-da2e-4c31-9fbe-1e0e1630b796
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159853629 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.4159853629
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1056327896
Short name T75
Test name
Test status
Simulation time 16077220 ps
CPU time 0.55 seconds
Started Feb 04 04:17:43 PM PST 24
Finished Feb 04 04:17:45 PM PST 24
Peak memory 182288 kb
Host smart-d0ad6c03-7d68-4703-a6d7-75aa1a42548e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056327896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1056327896
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3851461058
Short name T396
Test name
Test status
Simulation time 18117140 ps
CPU time 0.62 seconds
Started Feb 04 04:17:44 PM PST 24
Finished Feb 04 04:17:46 PM PST 24
Peak memory 182184 kb
Host smart-e3ba8ff2-4b30-4ac4-86ea-f58f488ab599
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851461058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.3851461058
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1519621328
Short name T16
Test name
Test status
Simulation time 77041300 ps
CPU time 0.75 seconds
Started Feb 04 04:17:36 PM PST 24
Finished Feb 04 04:17:44 PM PST 24
Peak memory 192804 kb
Host smart-def941dd-6b80-46f7-b874-385c7e63709c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519621328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1519621328
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3476306816
Short name T38
Test name
Test status
Simulation time 497440722 ps
CPU time 2.82 seconds
Started Feb 04 04:17:37 PM PST 24
Finished Feb 04 04:17:46 PM PST 24
Peak memory 197220 kb
Host smart-f2bf8797-ad98-488a-ba8c-dbf628c22af0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476306816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3476306816
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2701069969
Short name T398
Test name
Test status
Simulation time 116243536 ps
CPU time 0.94 seconds
Started Feb 04 04:17:37 PM PST 24
Finished Feb 04 04:17:44 PM PST 24
Peak memory 196068 kb
Host smart-e1be4a8b-1d1b-4caf-9772-f30fe2238252
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701069969 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2701069969
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.2036191668
Short name T375
Test name
Test status
Simulation time 19968575 ps
CPU time 0.57 seconds
Started Feb 04 04:17:44 PM PST 24
Finished Feb 04 04:17:46 PM PST 24
Peak memory 182288 kb
Host smart-1f9e6782-61eb-4554-a131-8990960a5c67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036191668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.2036191668
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.61477205
Short name T410
Test name
Test status
Simulation time 46233151 ps
CPU time 0.53 seconds
Started Feb 04 04:17:43 PM PST 24
Finished Feb 04 04:17:45 PM PST 24
Peak memory 181568 kb
Host smart-2da293af-a20e-42b3-ae23-4a38542a82ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61477205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.61477205
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1970541620
Short name T405
Test name
Test status
Simulation time 20336444 ps
CPU time 0.82 seconds
Started Feb 04 04:17:38 PM PST 24
Finished Feb 04 04:17:44 PM PST 24
Peak memory 191260 kb
Host smart-a51dd22d-cc26-4573-a8d1-67a0db6e73d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970541620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1970541620
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1950729815
Short name T422
Test name
Test status
Simulation time 126840702 ps
CPU time 1.61 seconds
Started Feb 04 04:17:44 PM PST 24
Finished Feb 04 04:17:47 PM PST 24
Peak memory 197148 kb
Host smart-f918abe6-dfcc-42fe-9abc-f7834e02ad7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950729815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1950729815
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3194412091
Short name T91
Test name
Test status
Simulation time 139249604 ps
CPU time 0.83 seconds
Started Feb 04 04:17:45 PM PST 24
Finished Feb 04 04:17:47 PM PST 24
Peak memory 192672 kb
Host smart-fadecd6c-8dfb-40b8-b51d-054355c3caaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194412091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.3194412091
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3366442191
Short name T67
Test name
Test status
Simulation time 158969991 ps
CPU time 0.73 seconds
Started Feb 04 04:17:41 PM PST 24
Finished Feb 04 04:17:45 PM PST 24
Peak memory 194300 kb
Host smart-bee069a4-db62-4ea6-a330-ca17970ad1f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366442191 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3366442191
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2742338596
Short name T459
Test name
Test status
Simulation time 23606303 ps
CPU time 0.59 seconds
Started Feb 04 04:17:52 PM PST 24
Finished Feb 04 04:17:53 PM PST 24
Peak memory 182064 kb
Host smart-89942e34-6ff8-4975-8456-42fddbe39bac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742338596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2742338596
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3551022116
Short name T442
Test name
Test status
Simulation time 34501880 ps
CPU time 0.57 seconds
Started Feb 04 04:17:41 PM PST 24
Finished Feb 04 04:17:44 PM PST 24
Peak memory 182196 kb
Host smart-ba861827-9a68-4eab-bd76-9e090b342def
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551022116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3551022116
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.685710410
Short name T66
Test name
Test status
Simulation time 54219484 ps
CPU time 0.75 seconds
Started Feb 04 04:17:48 PM PST 24
Finished Feb 04 04:17:49 PM PST 24
Peak memory 191408 kb
Host smart-d14f6fad-ef12-494b-8c33-cf005c34e112
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685710410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_tim
er_same_csr_outstanding.685710410
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2331304423
Short name T476
Test name
Test status
Simulation time 209573479 ps
CPU time 2.37 seconds
Started Feb 04 04:17:43 PM PST 24
Finished Feb 04 04:17:46 PM PST 24
Peak memory 197212 kb
Host smart-31b89be5-4456-4339-bb8a-9cd81dcc5888
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331304423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2331304423
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.81948527
Short name T471
Test name
Test status
Simulation time 47444773 ps
CPU time 0.82 seconds
Started Feb 04 04:17:44 PM PST 24
Finished Feb 04 04:17:47 PM PST 24
Peak memory 182464 kb
Host smart-848fe8ff-a41c-43c5-8d19-5b2df668b78c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81948527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_intg
_err.81948527
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3217554635
Short name T382
Test name
Test status
Simulation time 35979415 ps
CPU time 1.14 seconds
Started Feb 04 04:17:52 PM PST 24
Finished Feb 04 04:17:53 PM PST 24
Peak memory 197064 kb
Host smart-3217512e-3b6d-4219-82df-96400655210c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217554635 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3217554635
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1076359675
Short name T456
Test name
Test status
Simulation time 13738965 ps
CPU time 0.6 seconds
Started Feb 04 04:17:50 PM PST 24
Finished Feb 04 04:17:52 PM PST 24
Peak memory 182476 kb
Host smart-01b1fe24-60a6-477b-9b31-c275a8347b8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076359675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1076359675
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2283039344
Short name T55
Test name
Test status
Simulation time 60181247 ps
CPU time 0.57 seconds
Started Feb 04 04:17:50 PM PST 24
Finished Feb 04 04:17:51 PM PST 24
Peak memory 182204 kb
Host smart-4a5c3533-4863-475f-8866-e379d575596a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283039344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2283039344
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.397945844
Short name T427
Test name
Test status
Simulation time 25731051 ps
CPU time 0.68 seconds
Started Feb 04 04:17:49 PM PST 24
Finished Feb 04 04:17:50 PM PST 24
Peak memory 191564 kb
Host smart-c724a06c-b4c4-49a2-802a-3b5e751b896f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397945844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim
er_same_csr_outstanding.397945844
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1266756511
Short name T464
Test name
Test status
Simulation time 258676975 ps
CPU time 3.43 seconds
Started Feb 04 04:17:44 PM PST 24
Finished Feb 04 04:17:49 PM PST 24
Peak memory 197232 kb
Host smart-2f47ad16-7685-4724-acae-d2f7e0b960a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266756511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1266756511
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2162767145
Short name T446
Test name
Test status
Simulation time 79906971 ps
CPU time 1.15 seconds
Started Feb 04 04:17:43 PM PST 24
Finished Feb 04 04:17:45 PM PST 24
Peak memory 194788 kb
Host smart-53229f10-e0a2-4824-9392-38b31b253386
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162767145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2162767145
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3953621862
Short name T426
Test name
Test status
Simulation time 53279707 ps
CPU time 0.9 seconds
Started Feb 04 04:17:55 PM PST 24
Finished Feb 04 04:17:56 PM PST 24
Peak memory 195876 kb
Host smart-433136c8-eda9-4bf2-9e70-d0d4a0f34e8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953621862 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3953621862
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1923823456
Short name T390
Test name
Test status
Simulation time 55358375 ps
CPU time 0.61 seconds
Started Feb 04 04:17:50 PM PST 24
Finished Feb 04 04:17:52 PM PST 24
Peak memory 182308 kb
Host smart-1f57d204-8cee-4f4f-a227-66bfd9b835cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923823456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1923823456
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2295931027
Short name T424
Test name
Test status
Simulation time 12918884 ps
CPU time 0.64 seconds
Started Feb 04 04:17:54 PM PST 24
Finished Feb 04 04:17:56 PM PST 24
Peak memory 182212 kb
Host smart-bdaeea03-1aa2-42b9-9d32-ea6e662118b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295931027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2295931027
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.749685061
Short name T411
Test name
Test status
Simulation time 31634973 ps
CPU time 0.67 seconds
Started Feb 04 04:18:02 PM PST 24
Finished Feb 04 04:18:07 PM PST 24
Peak memory 191528 kb
Host smart-6ac36e78-fe3b-41b6-b4ac-61aa1a1bb27b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749685061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_tim
er_same_csr_outstanding.749685061
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2236162590
Short name T463
Test name
Test status
Simulation time 150212165 ps
CPU time 3.13 seconds
Started Feb 04 04:17:54 PM PST 24
Finished Feb 04 04:17:58 PM PST 24
Peak memory 197212 kb
Host smart-230d0065-b075-40e4-b26b-357369f6ece1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236162590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2236162590
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3096650958
Short name T420
Test name
Test status
Simulation time 401243848 ps
CPU time 1.59 seconds
Started Feb 04 04:17:50 PM PST 24
Finished Feb 04 04:17:53 PM PST 24
Peak memory 182964 kb
Host smart-f438bc84-5b15-424a-937a-653548978d5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096650958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3096650958
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1626610059
Short name T174
Test name
Test status
Simulation time 73000952636 ps
CPU time 140.35 seconds
Started Feb 04 12:57:07 PM PST 24
Finished Feb 04 12:59:33 PM PST 24
Peak memory 182432 kb
Host smart-a37ff23a-2966-480d-ac0f-8ec354ef1f64
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626610059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1626610059
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3710739303
Short name T548
Test name
Test status
Simulation time 52711476211 ps
CPU time 21.65 seconds
Started Feb 04 12:57:03 PM PST 24
Finished Feb 04 12:57:28 PM PST 24
Peak memory 182400 kb
Host smart-90cf9719-1776-4013-830e-a551d3939511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710739303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3710739303
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.1995069089
Short name T361
Test name
Test status
Simulation time 59443449230 ps
CPU time 44.07 seconds
Started Feb 04 12:57:07 PM PST 24
Finished Feb 04 12:57:56 PM PST 24
Peak memory 182528 kb
Host smart-5d00a1d2-cb02-4822-bd49-7a204e781d10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995069089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1995069089
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.4241041077
Short name T599
Test name
Test status
Simulation time 69462909043 ps
CPU time 44.41 seconds
Started Feb 04 12:56:43 PM PST 24
Finished Feb 04 12:57:31 PM PST 24
Peak memory 182504 kb
Host smart-f29a44c7-796e-4f62-93e5-54a2a71ef8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241041077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.4241041077
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.4014056330
Short name T576
Test name
Test status
Simulation time 44028514384 ps
CPU time 390.05 seconds
Started Feb 04 12:57:04 PM PST 24
Finished Feb 04 01:03:36 PM PST 24
Peak memory 206312 kb
Host smart-7579da87-9eda-41b7-965b-f3f048acedeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014056330 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.4014056330
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1578891604
Short name T552
Test name
Test status
Simulation time 38398059803 ps
CPU time 69.14 seconds
Started Feb 04 12:56:49 PM PST 24
Finished Feb 04 12:58:05 PM PST 24
Peak memory 182388 kb
Host smart-3dc9d033-ee43-44a3-8619-9352f384ae19
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578891604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1578891604
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2459537553
Short name T504
Test name
Test status
Simulation time 457829707868 ps
CPU time 254.8 seconds
Started Feb 04 12:56:46 PM PST 24
Finished Feb 04 01:01:04 PM PST 24
Peak memory 182544 kb
Host smart-95724cc1-9a04-4a5e-8a8c-6f2ba0b1e192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459537553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2459537553
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.1208165940
Short name T194
Test name
Test status
Simulation time 183970846263 ps
CPU time 487.71 seconds
Started Feb 04 12:56:43 PM PST 24
Finished Feb 04 01:04:53 PM PST 24
Peak memory 190776 kb
Host smart-f2219193-6227-4b9d-b7a0-1a8683b23a20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208165940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1208165940
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1193944003
Short name T21
Test name
Test status
Simulation time 70644123 ps
CPU time 0.84 seconds
Started Feb 04 12:56:52 PM PST 24
Finished Feb 04 12:56:57 PM PST 24
Peak memory 212832 kb
Host smart-86511cf1-0554-48bb-a5db-1fd332aa4d5f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193944003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1193944003
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.2969286093
Short name T593
Test name
Test status
Simulation time 67844705317 ps
CPU time 225.67 seconds
Started Feb 04 12:57:07 PM PST 24
Finished Feb 04 01:00:58 PM PST 24
Peak memory 197128 kb
Host smart-e3dd69c3-f46f-4f61-b046-83a8fe202629
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969286093 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.2969286093
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3915356829
Short name T167
Test name
Test status
Simulation time 612800218776 ps
CPU time 344.33 seconds
Started Feb 04 12:57:00 PM PST 24
Finished Feb 04 01:02:47 PM PST 24
Peak memory 182476 kb
Host smart-14b18a9d-4aab-4f9c-b002-3850f172c151
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915356829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3915356829
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3210380742
Short name T368
Test name
Test status
Simulation time 150741351339 ps
CPU time 231.59 seconds
Started Feb 04 12:57:01 PM PST 24
Finished Feb 04 01:00:55 PM PST 24
Peak memory 182536 kb
Host smart-cc9c8b2a-4b51-4b25-bb21-e175ec4116d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210380742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3210380742
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.1463104340
Short name T177
Test name
Test status
Simulation time 144213161542 ps
CPU time 344.99 seconds
Started Feb 04 12:57:04 PM PST 24
Finished Feb 04 01:02:52 PM PST 24
Peak memory 190700 kb
Host smart-8779fd51-c3e0-412d-aa39-db5390b94906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463104340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1463104340
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.785025998
Short name T528
Test name
Test status
Simulation time 2031148634 ps
CPU time 1.29 seconds
Started Feb 04 12:57:03 PM PST 24
Finished Feb 04 12:57:07 PM PST 24
Peak memory 192828 kb
Host smart-fd3be851-b996-46dc-b08e-5e910e97a5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785025998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.785025998
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.223214610
Short name T484
Test name
Test status
Simulation time 66953019513 ps
CPU time 244.9 seconds
Started Feb 04 12:56:53 PM PST 24
Finished Feb 04 01:01:01 PM PST 24
Peak memory 205328 kb
Host smart-92ee866f-9852-41fc-9cdf-f47757128d06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223214610 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.223214610
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.2818034684
Short name T267
Test name
Test status
Simulation time 177807988966 ps
CPU time 322.5 seconds
Started Feb 04 12:58:00 PM PST 24
Finished Feb 04 01:03:23 PM PST 24
Peak memory 190748 kb
Host smart-1551afcd-fe3e-4344-a44f-cef179aeefd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818034684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2818034684
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.4078622858
Short name T304
Test name
Test status
Simulation time 31284868564 ps
CPU time 370.75 seconds
Started Feb 04 12:57:57 PM PST 24
Finished Feb 04 01:04:09 PM PST 24
Peak memory 182504 kb
Host smart-a53e748f-c907-4a8b-a535-8dfebd64bad0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078622858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.4078622858
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.2147261993
Short name T96
Test name
Test status
Simulation time 463658681828 ps
CPU time 245.52 seconds
Started Feb 04 12:57:56 PM PST 24
Finished Feb 04 01:02:03 PM PST 24
Peak memory 190732 kb
Host smart-e56052b2-35c3-42b3-a19e-4cfa57e06036
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147261993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2147261993
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.124725904
Short name T22
Test name
Test status
Simulation time 86103785683 ps
CPU time 301.06 seconds
Started Feb 04 12:57:56 PM PST 24
Finished Feb 04 01:02:58 PM PST 24
Peak memory 190704 kb
Host smart-2e833749-c1b6-4593-86fd-fd68d3d60bf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124725904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.124725904
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1537291725
Short name T154
Test name
Test status
Simulation time 325141592509 ps
CPU time 145.13 seconds
Started Feb 04 12:58:03 PM PST 24
Finished Feb 04 01:00:30 PM PST 24
Peak memory 190684 kb
Host smart-26d1347f-e7a9-4db1-b8e9-b09a0fe9ac0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537291725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1537291725
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.3432609362
Short name T29
Test name
Test status
Simulation time 44203486075 ps
CPU time 16.52 seconds
Started Feb 04 12:57:55 PM PST 24
Finished Feb 04 12:58:12 PM PST 24
Peak memory 182444 kb
Host smart-d891f24b-0cf9-483c-a77b-7bc22dbcdbcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432609362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3432609362
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.4122009420
Short name T205
Test name
Test status
Simulation time 1047610280050 ps
CPU time 529.75 seconds
Started Feb 04 12:58:15 PM PST 24
Finished Feb 04 01:07:06 PM PST 24
Peak memory 190768 kb
Host smart-53d6454a-4747-4ae2-bbb9-5e3647fd730e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122009420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.4122009420
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3156527051
Short name T307
Test name
Test status
Simulation time 91462993932 ps
CPU time 165.23 seconds
Started Feb 04 12:57:03 PM PST 24
Finished Feb 04 12:59:51 PM PST 24
Peak memory 182524 kb
Host smart-34b1394b-cf28-47a3-9c24-87fd857a2dd4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156527051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3156527051
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.515529324
Short name T505
Test name
Test status
Simulation time 100597732153 ps
CPU time 150.15 seconds
Started Feb 04 12:57:07 PM PST 24
Finished Feb 04 12:59:43 PM PST 24
Peak memory 182448 kb
Host smart-56dad35d-4fcd-419d-a954-c41ca5923a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515529324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.515529324
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.35319828
Short name T345
Test name
Test status
Simulation time 322319607459 ps
CPU time 354.19 seconds
Started Feb 04 12:57:04 PM PST 24
Finished Feb 04 01:03:01 PM PST 24
Peak memory 190780 kb
Host smart-bbd7019a-4dc1-4ebf-9b0c-bbc868d31a69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35319828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.35319828
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2474759870
Short name T482
Test name
Test status
Simulation time 211155378 ps
CPU time 7.53 seconds
Started Feb 04 12:57:07 PM PST 24
Finished Feb 04 12:57:20 PM PST 24
Peak memory 190660 kb
Host smart-b8590176-a6a8-4207-8ba5-404fe12a509f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474759870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2474759870
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.3039802336
Short name T578
Test name
Test status
Simulation time 126566967965 ps
CPU time 93.49 seconds
Started Feb 04 12:57:04 PM PST 24
Finished Feb 04 12:58:40 PM PST 24
Peak memory 205428 kb
Host smart-49d54a2d-f1a9-49ac-ab2e-9433658dfe0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039802336 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.3039802336
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.rv_timer_random.2893928440
Short name T123
Test name
Test status
Simulation time 465110535893 ps
CPU time 285.1 seconds
Started Feb 04 12:58:14 PM PST 24
Finished Feb 04 01:03:01 PM PST 24
Peak memory 190768 kb
Host smart-aca88368-acf3-4039-a121-ec519a32014d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893928440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2893928440
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.1126356019
Short name T319
Test name
Test status
Simulation time 98629579137 ps
CPU time 65.41 seconds
Started Feb 04 12:58:10 PM PST 24
Finished Feb 04 12:59:17 PM PST 24
Peak memory 182472 kb
Host smart-06247845-f729-46ea-addd-84acdd7e1f45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126356019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1126356019
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.1327041127
Short name T118
Test name
Test status
Simulation time 94488913558 ps
CPU time 893.86 seconds
Started Feb 04 12:58:10 PM PST 24
Finished Feb 04 01:13:06 PM PST 24
Peak memory 193916 kb
Host smart-d383d72a-2f19-4e41-9b0f-be79839454a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327041127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1327041127
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3973691828
Short name T265
Test name
Test status
Simulation time 2948270596 ps
CPU time 5.71 seconds
Started Feb 04 12:58:09 PM PST 24
Finished Feb 04 12:58:17 PM PST 24
Peak memory 182512 kb
Host smart-96d0329d-01a2-4ada-a33c-68f530d0260c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973691828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3973691828
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.1998926442
Short name T211
Test name
Test status
Simulation time 155901325455 ps
CPU time 89.04 seconds
Started Feb 04 12:58:14 PM PST 24
Finished Feb 04 12:59:44 PM PST 24
Peak memory 190636 kb
Host smart-819073f3-b8ba-453d-b1cb-828dba42f25b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998926442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1998926442
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.2872526517
Short name T317
Test name
Test status
Simulation time 212775945906 ps
CPU time 1698.78 seconds
Started Feb 04 12:58:15 PM PST 24
Finished Feb 04 01:26:35 PM PST 24
Peak memory 182536 kb
Host smart-3ef5c4fa-c0b4-424f-9e38-c95c5f75b3a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872526517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2872526517
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.740367585
Short name T185
Test name
Test status
Simulation time 137349899598 ps
CPU time 299.23 seconds
Started Feb 04 12:58:11 PM PST 24
Finished Feb 04 01:03:11 PM PST 24
Peak memory 190752 kb
Host smart-8ac8410a-9918-4f81-9a24-fd5d562bb9bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740367585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.740367585
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3852080719
Short name T532
Test name
Test status
Simulation time 7116908664 ps
CPU time 6.09 seconds
Started Feb 04 12:57:03 PM PST 24
Finished Feb 04 12:57:11 PM PST 24
Peak memory 182340 kb
Host smart-b2ef325d-fc31-4749-884b-8f25d313c93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852080719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3852080719
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.179224779
Short name T266
Test name
Test status
Simulation time 543910123712 ps
CPU time 1034.25 seconds
Started Feb 04 12:57:02 PM PST 24
Finished Feb 04 01:14:19 PM PST 24
Peak memory 190744 kb
Host smart-8d88b9cf-ad52-4bc6-a6ed-b323110a1ed9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179224779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.179224779
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.924631692
Short name T609
Test name
Test status
Simulation time 2914481958 ps
CPU time 4.35 seconds
Started Feb 04 12:57:04 PM PST 24
Finished Feb 04 12:57:11 PM PST 24
Peak memory 182592 kb
Host smart-b8e7044d-1069-41dc-bfcd-d397e9d9bb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924631692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.924631692
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.1673547137
Short name T554
Test name
Test status
Simulation time 74178732284 ps
CPU time 809.22 seconds
Started Feb 04 12:57:04 PM PST 24
Finished Feb 04 01:10:36 PM PST 24
Peak memory 208272 kb
Host smart-89353001-b4e8-40f7-92e8-d99fa8adeb14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673547137 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.1673547137
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/121.rv_timer_random.3432763264
Short name T337
Test name
Test status
Simulation time 43808458607 ps
CPU time 75.06 seconds
Started Feb 04 12:58:08 PM PST 24
Finished Feb 04 12:59:27 PM PST 24
Peak memory 182456 kb
Host smart-b40ff25c-e0f7-431b-bccf-ec03f810b312
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432763264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3432763264
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.2505374420
Short name T104
Test name
Test status
Simulation time 13369472869 ps
CPU time 25.55 seconds
Started Feb 04 12:58:13 PM PST 24
Finished Feb 04 12:58:39 PM PST 24
Peak memory 190688 kb
Host smart-3ecc3e14-b350-4354-99fa-1f711784520f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505374420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.2505374420
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2162210033
Short name T11
Test name
Test status
Simulation time 142546020414 ps
CPU time 2164.68 seconds
Started Feb 04 12:58:14 PM PST 24
Finished Feb 04 01:34:20 PM PST 24
Peak memory 190728 kb
Host smart-177dca84-5556-4bf4-85ee-5b118d877431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162210033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2162210033
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3112636305
Short name T617
Test name
Test status
Simulation time 202091760479 ps
CPU time 655.29 seconds
Started Feb 04 12:58:08 PM PST 24
Finished Feb 04 01:09:07 PM PST 24
Peak memory 190696 kb
Host smart-0821bc5a-f656-4b0d-a5c6-6c27b73ddd8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112636305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3112636305
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3033332276
Short name T280
Test name
Test status
Simulation time 636264840137 ps
CPU time 1887.93 seconds
Started Feb 04 12:58:21 PM PST 24
Finished Feb 04 01:29:50 PM PST 24
Peak memory 190708 kb
Host smart-6ca1eb82-c019-4eeb-9483-b5d1e8f660be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033332276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3033332276
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2460875437
Short name T355
Test name
Test status
Simulation time 229898717299 ps
CPU time 129.01 seconds
Started Feb 04 12:57:07 PM PST 24
Finished Feb 04 12:59:21 PM PST 24
Peak memory 182484 kb
Host smart-02dabbd9-2241-4326-a459-11672dea1263
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460875437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2460875437
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1785154497
Short name T506
Test name
Test status
Simulation time 135668572700 ps
CPU time 206.17 seconds
Started Feb 04 12:57:06 PM PST 24
Finished Feb 04 01:00:34 PM PST 24
Peak memory 182256 kb
Host smart-d5ba3eb4-cbe9-4766-9069-897c998d332a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785154497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1785154497
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.2669148937
Short name T314
Test name
Test status
Simulation time 22246620147 ps
CPU time 35.31 seconds
Started Feb 04 12:57:00 PM PST 24
Finished Feb 04 12:57:38 PM PST 24
Peak memory 182520 kb
Host smart-41f11c25-67df-4aee-b110-4d2cb46e66ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669148937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2669148937
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2465824209
Short name T618
Test name
Test status
Simulation time 608438768 ps
CPU time 1 seconds
Started Feb 04 12:56:56 PM PST 24
Finished Feb 04 12:56:59 PM PST 24
Peak memory 182360 kb
Host smart-5a4a8326-f960-4f96-9b4a-0e8811df38ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465824209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2465824209
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.576538080
Short name T516
Test name
Test status
Simulation time 1477440614171 ps
CPU time 638.21 seconds
Started Feb 04 12:57:08 PM PST 24
Finished Feb 04 01:07:53 PM PST 24
Peak memory 190320 kb
Host smart-e3ac6985-db58-487a-9140-14791d64d97a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576538080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.
576538080
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.3563555129
Short name T485
Test name
Test status
Simulation time 67958801420 ps
CPU time 721.05 seconds
Started Feb 04 12:56:53 PM PST 24
Finished Feb 04 01:08:57 PM PST 24
Peak memory 205280 kb
Host smart-8b3f8634-2e11-4490-9d50-6cd91fcd628d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563555129 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.3563555129
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.2920681853
Short name T299
Test name
Test status
Simulation time 698647015224 ps
CPU time 160.14 seconds
Started Feb 04 12:58:15 PM PST 24
Finished Feb 04 01:00:57 PM PST 24
Peak memory 190768 kb
Host smart-3d0f5e2b-2e39-4218-a347-e9ed4a3aa5bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920681853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2920681853
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.3240438702
Short name T263
Test name
Test status
Simulation time 127512323231 ps
CPU time 588.59 seconds
Started Feb 04 12:58:11 PM PST 24
Finished Feb 04 01:08:01 PM PST 24
Peak memory 190732 kb
Host smart-419051a6-db41-4931-968a-57754e808a70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240438702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3240438702
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.4275020537
Short name T335
Test name
Test status
Simulation time 384586835659 ps
CPU time 206.37 seconds
Started Feb 04 12:58:09 PM PST 24
Finished Feb 04 01:01:38 PM PST 24
Peak memory 190696 kb
Host smart-757670f3-870c-446e-8e92-e0d1841fa513
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275020537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.4275020537
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3724592512
Short name T214
Test name
Test status
Simulation time 65547275709 ps
CPU time 111.48 seconds
Started Feb 04 12:58:14 PM PST 24
Finished Feb 04 01:00:06 PM PST 24
Peak memory 190760 kb
Host smart-2f9505b4-3648-4646-9e5e-3dbb0fd9f761
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724592512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3724592512
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.706352040
Short name T271
Test name
Test status
Simulation time 35837821287 ps
CPU time 55.57 seconds
Started Feb 04 12:58:17 PM PST 24
Finished Feb 04 12:59:14 PM PST 24
Peak memory 194072 kb
Host smart-fc7f6162-1462-4a68-b8c7-45e5cb43abf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706352040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.706352040
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3867800211
Short name T169
Test name
Test status
Simulation time 579816497588 ps
CPU time 620.64 seconds
Started Feb 04 12:58:21 PM PST 24
Finished Feb 04 01:08:43 PM PST 24
Peak memory 193336 kb
Host smart-73a8e97f-74f0-4a48-89fe-e3c3a3cf85b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867800211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3867800211
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3185102133
Short name T611
Test name
Test status
Simulation time 84963579708 ps
CPU time 165.71 seconds
Started Feb 04 12:58:17 PM PST 24
Finished Feb 04 01:01:04 PM PST 24
Peak memory 190652 kb
Host smart-b59ee764-7001-4ba4-9353-8ad5926a3cf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185102133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3185102133
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2402441226
Short name T561
Test name
Test status
Simulation time 1793475037 ps
CPU time 40.55 seconds
Started Feb 04 12:58:23 PM PST 24
Finished Feb 04 12:59:04 PM PST 24
Peak memory 182376 kb
Host smart-bcbf2472-bd69-4339-a9a1-5de71355a532
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402441226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2402441226
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.1348778296
Short name T348
Test name
Test status
Simulation time 12105011809 ps
CPU time 23.56 seconds
Started Feb 04 12:57:02 PM PST 24
Finished Feb 04 12:57:29 PM PST 24
Peak memory 182536 kb
Host smart-10d1f18f-31e2-4246-8b8a-ae89e32a5807
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348778296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.1348778296
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.1754646077
Short name T500
Test name
Test status
Simulation time 74645347847 ps
CPU time 63.37 seconds
Started Feb 04 12:57:08 PM PST 24
Finished Feb 04 12:58:18 PM PST 24
Peak memory 182484 kb
Host smart-a1c62e15-6144-480d-9856-3322d89ec20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754646077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.1754646077
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.3627145997
Short name T4
Test name
Test status
Simulation time 879824841746 ps
CPU time 366.66 seconds
Started Feb 04 12:57:00 PM PST 24
Finished Feb 04 01:03:09 PM PST 24
Peak memory 190724 kb
Host smart-d051ce51-50f2-456c-8ec0-4f40df3fbe40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627145997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3627145997
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.2342756776
Short name T352
Test name
Test status
Simulation time 100255793284 ps
CPU time 138.84 seconds
Started Feb 04 12:57:10 PM PST 24
Finished Feb 04 12:59:33 PM PST 24
Peak memory 182364 kb
Host smart-b68d6e90-adca-47d4-ae55-3ecd818677f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342756776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2342756776
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.3995266213
Short name T551
Test name
Test status
Simulation time 715708040855 ps
CPU time 113.17 seconds
Started Feb 04 12:57:11 PM PST 24
Finished Feb 04 12:59:07 PM PST 24
Peak memory 182532 kb
Host smart-a1f72080-22b8-4f95-a56e-c1fc6d483d29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995266213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.3995266213
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.3214276055
Short name T30
Test name
Test status
Simulation time 712489547401 ps
CPU time 868.79 seconds
Started Feb 04 12:57:09 PM PST 24
Finished Feb 04 01:11:43 PM PST 24
Peak memory 210052 kb
Host smart-706ba0a9-209f-4b0d-9780-2bd60d063637
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214276055 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.3214276055
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/142.rv_timer_random.3231670090
Short name T143
Test name
Test status
Simulation time 179221923336 ps
CPU time 232.62 seconds
Started Feb 04 12:58:16 PM PST 24
Finished Feb 04 01:02:09 PM PST 24
Peak memory 190744 kb
Host smart-cf2388ac-8a04-4c84-ace4-da4b893066c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231670090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3231670090
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.3323759719
Short name T151
Test name
Test status
Simulation time 1209325540219 ps
CPU time 1413.31 seconds
Started Feb 04 12:58:24 PM PST 24
Finished Feb 04 01:21:58 PM PST 24
Peak memory 190472 kb
Host smart-6125857e-e211-45b1-a927-1fe52ed87eaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323759719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3323759719
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.462028576
Short name T183
Test name
Test status
Simulation time 260419936818 ps
CPU time 487.21 seconds
Started Feb 04 12:58:25 PM PST 24
Finished Feb 04 01:06:34 PM PST 24
Peak memory 190796 kb
Host smart-821ee6c5-1465-4c45-9e7c-5f386afcfb3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462028576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.462028576
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.3978963552
Short name T130
Test name
Test status
Simulation time 124051691960 ps
CPU time 600.41 seconds
Started Feb 04 12:58:25 PM PST 24
Finished Feb 04 01:08:27 PM PST 24
Peak memory 194152 kb
Host smart-2ead259a-561b-456a-8228-7c97a3fc827c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978963552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3978963552
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3970746370
Short name T277
Test name
Test status
Simulation time 45472370702 ps
CPU time 74.27 seconds
Started Feb 04 12:58:17 PM PST 24
Finished Feb 04 12:59:32 PM PST 24
Peak memory 190704 kb
Host smart-8c362e3a-9fa9-4222-81ba-ff126d30a266
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970746370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3970746370
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.257699368
Short name T132
Test name
Test status
Simulation time 379526648591 ps
CPU time 243.94 seconds
Started Feb 04 12:57:08 PM PST 24
Finished Feb 04 01:01:18 PM PST 24
Peak memory 182484 kb
Host smart-42e62665-7597-4f74-8bb7-50a5f3cf7e2a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257699368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.rv_timer_cfg_update_on_fly.257699368
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.186861019
Short name T523
Test name
Test status
Simulation time 186809621770 ps
CPU time 82.13 seconds
Started Feb 04 12:57:07 PM PST 24
Finished Feb 04 12:58:35 PM PST 24
Peak memory 182304 kb
Host smart-b88c60f7-7362-495a-93ed-5c2a20818a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186861019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.186861019
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.4010974707
Short name T605
Test name
Test status
Simulation time 64519928662 ps
CPU time 103.91 seconds
Started Feb 04 12:57:10 PM PST 24
Finished Feb 04 12:58:58 PM PST 24
Peak memory 190716 kb
Host smart-c14c3679-5173-4e68-93eb-968bfbf76db4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010974707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.4010974707
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3183305375
Short name T515
Test name
Test status
Simulation time 1071149915 ps
CPU time 4.78 seconds
Started Feb 04 12:57:10 PM PST 24
Finished Feb 04 12:57:19 PM PST 24
Peak memory 182440 kb
Host smart-6d3fe4aa-e0d6-4833-b1e3-fb9f55782ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183305375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3183305375
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.4251760850
Short name T221
Test name
Test status
Simulation time 547363882291 ps
CPU time 476.72 seconds
Started Feb 04 12:57:06 PM PST 24
Finished Feb 04 01:05:04 PM PST 24
Peak memory 190720 kb
Host smart-b4a4b0d3-c57e-43e1-9c79-3611ccc84415
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251760850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.4251760850
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.500354664
Short name T507
Test name
Test status
Simulation time 270288568586 ps
CPU time 446 seconds
Started Feb 04 12:57:08 PM PST 24
Finished Feb 04 01:04:40 PM PST 24
Peak memory 208940 kb
Host smart-beb55c9e-dc44-4e28-8495-a0605ea719f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500354664 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.500354664
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.3387260387
Short name T353
Test name
Test status
Simulation time 1074521774 ps
CPU time 2.37 seconds
Started Feb 04 12:58:33 PM PST 24
Finished Feb 04 12:58:38 PM PST 24
Peak memory 182280 kb
Host smart-3cf7d33e-1138-4ad2-a199-67af0c0b1210
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387260387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3387260387
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.2920204401
Short name T553
Test name
Test status
Simulation time 619633810821 ps
CPU time 652.13 seconds
Started Feb 04 12:58:18 PM PST 24
Finished Feb 04 01:09:12 PM PST 24
Peak memory 190680 kb
Host smart-93136e24-a902-4f6b-b007-9d43a5f2e323
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920204401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2920204401
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.1640653212
Short name T100
Test name
Test status
Simulation time 112358609858 ps
CPU time 202.51 seconds
Started Feb 04 12:58:15 PM PST 24
Finished Feb 04 01:01:38 PM PST 24
Peak memory 190564 kb
Host smart-8491ce19-63f6-431d-9185-d32b07b0c3b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640653212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1640653212
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.185221208
Short name T274
Test name
Test status
Simulation time 318212215146 ps
CPU time 175.75 seconds
Started Feb 04 12:58:41 PM PST 24
Finished Feb 04 01:01:39 PM PST 24
Peak memory 190776 kb
Host smart-3c2c04a9-86dc-4418-99cf-9357756dbcb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185221208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.185221208
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.787283648
Short name T285
Test name
Test status
Simulation time 49929619476 ps
CPU time 539.42 seconds
Started Feb 04 12:58:35 PM PST 24
Finished Feb 04 01:07:36 PM PST 24
Peak memory 190728 kb
Host smart-2141faf9-b34c-4e8f-908c-734e2d023c93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787283648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.787283648
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.832711128
Short name T489
Test name
Test status
Simulation time 712805913115 ps
CPU time 306.89 seconds
Started Feb 04 12:57:07 PM PST 24
Finished Feb 04 01:02:19 PM PST 24
Peak memory 182460 kb
Host smart-9f22210d-e5f7-4208-9e1d-39af4f69b845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832711128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.832711128
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.2749947806
Short name T293
Test name
Test status
Simulation time 79493153926 ps
CPU time 138.53 seconds
Started Feb 04 12:57:09 PM PST 24
Finished Feb 04 12:59:33 PM PST 24
Peak memory 190640 kb
Host smart-035df37a-ca1f-440e-8292-a6e4e99fefa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749947806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.2749947806
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.994975546
Short name T146
Test name
Test status
Simulation time 508729736817 ps
CPU time 1020.96 seconds
Started Feb 04 12:57:04 PM PST 24
Finished Feb 04 01:14:08 PM PST 24
Peak memory 212196 kb
Host smart-9aa14a22-3826-43a3-a80f-3892abdc8362
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994975546 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.994975546
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.rv_timer_random.2009797096
Short name T513
Test name
Test status
Simulation time 24491413569 ps
CPU time 47.99 seconds
Started Feb 04 12:58:51 PM PST 24
Finished Feb 04 12:59:42 PM PST 24
Peak memory 182688 kb
Host smart-ad2eb459-cb66-48b5-b3d7-2a72ec2ef29b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009797096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2009797096
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.4111014054
Short name T607
Test name
Test status
Simulation time 26353352579 ps
CPU time 86.22 seconds
Started Feb 04 12:58:41 PM PST 24
Finished Feb 04 01:00:08 PM PST 24
Peak memory 191976 kb
Host smart-a0a59f53-db54-4406-a96f-93ac34c5aac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111014054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.4111014054
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.4173819955
Short name T338
Test name
Test status
Simulation time 74071203823 ps
CPU time 40.07 seconds
Started Feb 04 12:58:35 PM PST 24
Finished Feb 04 12:59:16 PM PST 24
Peak memory 182460 kb
Host smart-0f415e29-5eac-442e-9062-7e40e3439307
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173819955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.4173819955
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.3835182537
Short name T156
Test name
Test status
Simulation time 2231023441642 ps
CPU time 1231.41 seconds
Started Feb 04 12:58:36 PM PST 24
Finished Feb 04 01:19:08 PM PST 24
Peak memory 193096 kb
Host smart-1240b0dc-deda-4392-963e-d02495c90cbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835182537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3835182537
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.2605334155
Short name T357
Test name
Test status
Simulation time 211496706990 ps
CPU time 86.88 seconds
Started Feb 04 12:58:40 PM PST 24
Finished Feb 04 01:00:08 PM PST 24
Peak memory 192956 kb
Host smart-602a84b3-8ab1-40d7-9c3c-a2e632344d36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605334155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2605334155
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3408480861
Short name T255
Test name
Test status
Simulation time 122119914797 ps
CPU time 301.03 seconds
Started Feb 04 12:58:41 PM PST 24
Finished Feb 04 01:03:44 PM PST 24
Peak memory 190752 kb
Host smart-eda14301-5b98-4b60-820b-f72d5fca0895
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408480861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3408480861
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.1419165235
Short name T246
Test name
Test status
Simulation time 318812029447 ps
CPU time 1718.43 seconds
Started Feb 04 12:58:45 PM PST 24
Finished Feb 04 01:27:25 PM PST 24
Peak memory 190704 kb
Host smart-50783a82-c886-4cd6-969e-bc9a8d1ed6fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419165235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1419165235
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1983551534
Short name T613
Test name
Test status
Simulation time 503209633259 ps
CPU time 182.51 seconds
Started Feb 04 12:57:05 PM PST 24
Finished Feb 04 01:00:10 PM PST 24
Peak memory 182440 kb
Host smart-ed6c4be0-384e-4711-892b-3f25c14c1168
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983551534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1983551534
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.531940883
Short name T365
Test name
Test status
Simulation time 606504524146 ps
CPU time 265.59 seconds
Started Feb 04 12:57:08 PM PST 24
Finished Feb 04 01:01:40 PM PST 24
Peak memory 182552 kb
Host smart-19c61d26-48e8-4bec-bee2-5936be6ddb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531940883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.531940883
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.2460554810
Short name T362
Test name
Test status
Simulation time 277607215282 ps
CPU time 890.8 seconds
Started Feb 04 12:57:10 PM PST 24
Finished Feb 04 01:12:05 PM PST 24
Peak memory 193816 kb
Host smart-f1eb9964-693d-4839-a5f8-a59f01f67c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460554810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2460554810
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.759267043
Short name T590
Test name
Test status
Simulation time 17236411956 ps
CPU time 47.34 seconds
Started Feb 04 12:57:09 PM PST 24
Finished Feb 04 12:58:02 PM PST 24
Peak memory 197260 kb
Host smart-88803031-ffff-4c6c-bd26-8f9824e950f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759267043 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.759267043
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.1705423910
Short name T248
Test name
Test status
Simulation time 65819792880 ps
CPU time 61.15 seconds
Started Feb 04 12:58:42 PM PST 24
Finished Feb 04 12:59:45 PM PST 24
Peak memory 190760 kb
Host smart-e54fd865-9300-4863-8e43-98e6f37d64ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705423910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1705423910
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.4109817859
Short name T97
Test name
Test status
Simulation time 856147361233 ps
CPU time 474.37 seconds
Started Feb 04 12:58:42 PM PST 24
Finished Feb 04 01:06:38 PM PST 24
Peak memory 190664 kb
Host smart-116ad645-0274-4032-b966-6140f8c9d51d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109817859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.4109817859
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.851054433
Short name T6
Test name
Test status
Simulation time 546618984700 ps
CPU time 502.24 seconds
Started Feb 04 12:58:42 PM PST 24
Finished Feb 04 01:07:06 PM PST 24
Peak memory 190676 kb
Host smart-296016f8-9e53-4319-9a88-5270f094cc7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851054433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.851054433
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.4238358048
Short name T570
Test name
Test status
Simulation time 8239638281 ps
CPU time 5.42 seconds
Started Feb 04 12:58:50 PM PST 24
Finished Feb 04 12:58:57 PM PST 24
Peak memory 182508 kb
Host smart-f96ade71-0ffb-48b9-9701-d1e37e71ef30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238358048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.4238358048
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.1668617737
Short name T249
Test name
Test status
Simulation time 90282539568 ps
CPU time 111.28 seconds
Started Feb 04 12:58:40 PM PST 24
Finished Feb 04 01:00:32 PM PST 24
Peak memory 190756 kb
Host smart-07992a31-4d94-4cfa-b867-c7338d74a554
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668617737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.1668617737
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.409680739
Short name T229
Test name
Test status
Simulation time 199149567419 ps
CPU time 817.51 seconds
Started Feb 04 12:58:44 PM PST 24
Finished Feb 04 01:12:23 PM PST 24
Peak memory 190788 kb
Host smart-63b9a7fd-f2ed-43e7-beaf-b79756629121
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409680739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.409680739
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.1372732964
Short name T198
Test name
Test status
Simulation time 43192104269 ps
CPU time 125.13 seconds
Started Feb 04 12:58:44 PM PST 24
Finished Feb 04 01:00:51 PM PST 24
Peak memory 182444 kb
Host smart-7fa98d3e-5fde-4a44-9608-4acb1c31282a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372732964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1372732964
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.3193808024
Short name T350
Test name
Test status
Simulation time 266087097972 ps
CPU time 800.79 seconds
Started Feb 04 12:58:42 PM PST 24
Finished Feb 04 01:12:05 PM PST 24
Peak memory 190608 kb
Host smart-03eb4b88-034a-4fc4-b36e-3d6008f75d3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193808024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3193808024
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1661860594
Short name T224
Test name
Test status
Simulation time 19358705089 ps
CPU time 18.3 seconds
Started Feb 04 12:58:49 PM PST 24
Finished Feb 04 12:59:09 PM PST 24
Peak memory 182552 kb
Host smart-f539c7ae-1614-46de-bf15-bc0d3c7d48de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661860594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1661860594
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.303521487
Short name T203
Test name
Test status
Simulation time 329150366378 ps
CPU time 592.98 seconds
Started Feb 04 12:57:09 PM PST 24
Finished Feb 04 01:07:07 PM PST 24
Peak memory 182452 kb
Host smart-b234a698-499d-4b42-97ae-9e6aade5e43f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303521487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.303521487
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1339241700
Short name T502
Test name
Test status
Simulation time 84684344252 ps
CPU time 30.85 seconds
Started Feb 04 12:57:02 PM PST 24
Finished Feb 04 12:57:35 PM PST 24
Peak memory 182632 kb
Host smart-d1374050-32fe-45f4-9e9a-2303cb4f66d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339241700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1339241700
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.502010739
Short name T318
Test name
Test status
Simulation time 344794950265 ps
CPU time 221.64 seconds
Started Feb 04 12:57:08 PM PST 24
Finished Feb 04 01:00:56 PM PST 24
Peak memory 190528 kb
Host smart-38a2b140-7b71-4161-972b-11cd5e592434
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502010739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.502010739
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1633914151
Short name T601
Test name
Test status
Simulation time 35586373823 ps
CPU time 15.57 seconds
Started Feb 04 12:57:09 PM PST 24
Finished Feb 04 12:57:30 PM PST 24
Peak memory 182400 kb
Host smart-66ad8fed-bc71-4e22-8192-9d08c489ddbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633914151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1633914151
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3649788445
Short name T243
Test name
Test status
Simulation time 249286391217 ps
CPU time 209.06 seconds
Started Feb 04 12:57:07 PM PST 24
Finished Feb 04 01:00:42 PM PST 24
Peak memory 190260 kb
Host smart-72cdd22b-f133-46bc-9994-9c36bfc9c646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649788445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3649788445
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.433078915
Short name T491
Test name
Test status
Simulation time 78203045266 ps
CPU time 328.73 seconds
Started Feb 04 12:57:06 PM PST 24
Finished Feb 04 01:02:36 PM PST 24
Peak memory 205468 kb
Host smart-7dedeacc-c91f-40f5-928f-37182a8d5125
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433078915 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.433078915
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.rv_timer_random.3746649679
Short name T162
Test name
Test status
Simulation time 63856846601 ps
CPU time 123.91 seconds
Started Feb 04 12:58:44 PM PST 24
Finished Feb 04 01:00:49 PM PST 24
Peak memory 190652 kb
Host smart-7e7694c6-bf47-4032-9351-0663f5f09bdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746649679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3746649679
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.1238811227
Short name T588
Test name
Test status
Simulation time 16443617538 ps
CPU time 7.83 seconds
Started Feb 04 12:58:41 PM PST 24
Finished Feb 04 12:58:49 PM PST 24
Peak memory 182540 kb
Host smart-e477daad-0a3f-48aa-8c0e-bd2d393a308f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238811227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1238811227
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.3459289637
Short name T328
Test name
Test status
Simulation time 48420359101 ps
CPU time 746.51 seconds
Started Feb 04 12:59:19 PM PST 24
Finished Feb 04 01:11:47 PM PST 24
Peak memory 182444 kb
Host smart-374ac211-ae73-423f-a577-be4cdc39b019
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459289637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3459289637
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1081296459
Short name T256
Test name
Test status
Simulation time 35257693318 ps
CPU time 14.48 seconds
Started Feb 04 12:58:51 PM PST 24
Finished Feb 04 12:59:09 PM PST 24
Peak memory 182348 kb
Host smart-597ce368-8571-4829-8fef-164ad2ad97eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081296459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1081296459
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2152246221
Short name T176
Test name
Test status
Simulation time 78059505835 ps
CPU time 367.72 seconds
Started Feb 04 12:58:49 PM PST 24
Finished Feb 04 01:04:59 PM PST 24
Peak memory 190640 kb
Host smart-c67b7125-4e2f-4274-bbde-b5fa0a48190e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152246221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2152246221
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1618389229
Short name T324
Test name
Test status
Simulation time 825938263301 ps
CPU time 719.83 seconds
Started Feb 04 12:58:49 PM PST 24
Finished Feb 04 01:10:51 PM PST 24
Peak memory 190756 kb
Host smart-bdd86cde-2ea7-4d5d-98df-a08ee1f9c8f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618389229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1618389229
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.4240167414
Short name T126
Test name
Test status
Simulation time 245573630130 ps
CPU time 437.66 seconds
Started Feb 04 12:57:06 PM PST 24
Finished Feb 04 01:04:25 PM PST 24
Peak memory 182428 kb
Host smart-bccd511a-a7a4-4872-b2d1-e5adb99b433c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240167414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.4240167414
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.69145425
Short name T557
Test name
Test status
Simulation time 624698482480 ps
CPU time 273.94 seconds
Started Feb 04 12:57:10 PM PST 24
Finished Feb 04 01:01:48 PM PST 24
Peak memory 182532 kb
Host smart-0fe0e1a4-88a8-4ad8-b709-bf4333483b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69145425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.69145425
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.2222070500
Short name T260
Test name
Test status
Simulation time 54251680437 ps
CPU time 258.07 seconds
Started Feb 04 12:57:07 PM PST 24
Finished Feb 04 01:01:31 PM PST 24
Peak memory 190356 kb
Host smart-9015eedc-ef1c-43bc-b69e-6043d6f1640f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222070500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2222070500
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.272927389
Short name T50
Test name
Test status
Simulation time 2136303020 ps
CPU time 0.99 seconds
Started Feb 04 12:57:05 PM PST 24
Finished Feb 04 12:57:08 PM PST 24
Peak memory 193312 kb
Host smart-8cbfbdc8-2e9b-4fce-b4c2-aad426351370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272927389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.272927389
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.2569286382
Short name T294
Test name
Test status
Simulation time 100064546493 ps
CPU time 1065.82 seconds
Started Feb 04 12:57:13 PM PST 24
Finished Feb 04 01:15:01 PM PST 24
Peak memory 210484 kb
Host smart-88e35037-9bbc-433a-8fe9-8e22270c688f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569286382 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.2569286382
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.4289383530
Short name T128
Test name
Test status
Simulation time 185428465985 ps
CPU time 290.66 seconds
Started Feb 04 12:58:50 PM PST 24
Finished Feb 04 01:03:43 PM PST 24
Peak memory 190684 kb
Host smart-eaf9ff3d-ca0e-4515-b965-1866377c51d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289383530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.4289383530
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.3822051626
Short name T115
Test name
Test status
Simulation time 269077450694 ps
CPU time 426.8 seconds
Started Feb 04 12:58:53 PM PST 24
Finished Feb 04 01:06:01 PM PST 24
Peak memory 190760 kb
Host smart-c1155d53-61a3-4c9c-81c8-a2c112aed4a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822051626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3822051626
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.1454370701
Short name T259
Test name
Test status
Simulation time 204626362640 ps
CPU time 103.72 seconds
Started Feb 04 12:58:54 PM PST 24
Finished Feb 04 01:00:43 PM PST 24
Peak memory 182516 kb
Host smart-0017dedb-e8bf-483b-b6f9-29521e612a3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454370701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1454370701
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.1983683385
Short name T159
Test name
Test status
Simulation time 122657253997 ps
CPU time 257.43 seconds
Started Feb 04 12:59:21 PM PST 24
Finished Feb 04 01:03:39 PM PST 24
Peak memory 190756 kb
Host smart-39befbb8-c7d2-40a8-b218-77b6bb30039b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983683385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1983683385
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.3679410436
Short name T197
Test name
Test status
Simulation time 112893033989 ps
CPU time 347.37 seconds
Started Feb 04 12:59:22 PM PST 24
Finished Feb 04 01:05:10 PM PST 24
Peak memory 190676 kb
Host smart-0f58be5d-2d3a-417d-9bcc-0aa72972fc5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679410436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3679410436
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.2612419582
Short name T270
Test name
Test status
Simulation time 59981107242 ps
CPU time 152.36 seconds
Started Feb 04 12:58:52 PM PST 24
Finished Feb 04 01:01:26 PM PST 24
Peak memory 182544 kb
Host smart-d7aee1ce-1999-44ef-ab33-c6da4e337067
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612419582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2612419582
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.151604875
Short name T326
Test name
Test status
Simulation time 60961521656 ps
CPU time 34.63 seconds
Started Feb 04 12:58:52 PM PST 24
Finished Feb 04 12:59:29 PM PST 24
Peak memory 182448 kb
Host smart-041bdd10-23fe-4123-b571-5008297bc78d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151604875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.151604875
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.4284282011
Short name T135
Test name
Test status
Simulation time 100991913369 ps
CPU time 191.58 seconds
Started Feb 04 12:58:58 PM PST 24
Finished Feb 04 01:02:11 PM PST 24
Peak memory 193760 kb
Host smart-83e45732-af7d-48f8-86c3-4712c3a16589
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284282011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.4284282011
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.2645421007
Short name T251
Test name
Test status
Simulation time 618485180828 ps
CPU time 321.78 seconds
Started Feb 04 12:58:56 PM PST 24
Finished Feb 04 01:04:21 PM PST 24
Peak memory 190776 kb
Host smart-183ef6e2-c949-43f7-b296-8b165d37f49d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645421007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2645421007
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.4123953973
Short name T604
Test name
Test status
Simulation time 223290840099 ps
CPU time 407.73 seconds
Started Feb 04 12:57:08 PM PST 24
Finished Feb 04 01:04:02 PM PST 24
Peak memory 182148 kb
Host smart-01c4a131-e8f4-400c-817f-d12ea7b2502a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123953973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.4123953973
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.716309996
Short name T586
Test name
Test status
Simulation time 43809902252 ps
CPU time 73.29 seconds
Started Feb 04 12:56:44 PM PST 24
Finished Feb 04 12:58:01 PM PST 24
Peak memory 182568 kb
Host smart-65a763cd-3fab-4056-9819-d9781c3f98d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716309996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.716309996
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3911627688
Short name T122
Test name
Test status
Simulation time 245060591469 ps
CPU time 249.35 seconds
Started Feb 04 12:56:44 PM PST 24
Finished Feb 04 01:00:57 PM PST 24
Peak memory 190728 kb
Host smart-15382407-c4f7-4ed7-b526-b0b13123c177
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911627688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3911627688
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.2966755849
Short name T310
Test name
Test status
Simulation time 65889995282 ps
CPU time 54.17 seconds
Started Feb 04 12:56:52 PM PST 24
Finished Feb 04 12:57:50 PM PST 24
Peak memory 194324 kb
Host smart-e9146bbd-bbd6-467a-aa8c-4d8faa6e8af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966755849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2966755849
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.2290385893
Short name T20
Test name
Test status
Simulation time 59936163 ps
CPU time 0.84 seconds
Started Feb 04 12:56:53 PM PST 24
Finished Feb 04 12:56:57 PM PST 24
Peak memory 212944 kb
Host smart-3e7f16ff-2bd2-424a-817b-13f867f13ed0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290385893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.2290385893
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.4260489368
Short name T492
Test name
Test status
Simulation time 92709451936 ps
CPU time 729.44 seconds
Started Feb 04 12:56:49 PM PST 24
Finished Feb 04 01:09:05 PM PST 24
Peak memory 199392 kb
Host smart-7411a610-385b-434d-b2f6-1a9824735f20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260489368 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.4260489368
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3462218062
Short name T204
Test name
Test status
Simulation time 357675445007 ps
CPU time 206.2 seconds
Started Feb 04 12:57:13 PM PST 24
Finished Feb 04 01:00:41 PM PST 24
Peak memory 182440 kb
Host smart-f12d215a-7694-4d9a-b20b-4b8e8e60443c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462218062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.3462218062
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.3741482136
Short name T594
Test name
Test status
Simulation time 25482835778 ps
CPU time 30.8 seconds
Started Feb 04 12:57:07 PM PST 24
Finished Feb 04 12:57:44 PM PST 24
Peak memory 182564 kb
Host smart-70160cb4-72ee-461b-90b1-66b089f53acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741482136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3741482136
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.3721070960
Short name T235
Test name
Test status
Simulation time 341172478326 ps
CPU time 226.55 seconds
Started Feb 04 12:57:10 PM PST 24
Finished Feb 04 01:01:01 PM PST 24
Peak memory 190788 kb
Host smart-8d856b6a-a4a8-490a-bf15-e81613dc3e92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721070960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3721070960
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.1512051853
Short name T202
Test name
Test status
Simulation time 8393266556 ps
CPU time 8.4 seconds
Started Feb 04 12:57:10 PM PST 24
Finished Feb 04 12:57:23 PM PST 24
Peak memory 194088 kb
Host smart-078d34fa-463c-4f4a-b51d-8a8efcb56ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512051853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.1512051853
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.2905057738
Short name T525
Test name
Test status
Simulation time 156219959157 ps
CPU time 559.82 seconds
Started Feb 04 12:57:09 PM PST 24
Finished Feb 04 01:06:34 PM PST 24
Peak memory 205776 kb
Host smart-32de973e-21a7-4432-a138-3c922e4f55e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905057738 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.2905057738
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2206814366
Short name T105
Test name
Test status
Simulation time 1597841662196 ps
CPU time 876.33 seconds
Started Feb 04 12:57:17 PM PST 24
Finished Feb 04 01:11:54 PM PST 24
Peak memory 182504 kb
Host smart-e742ced3-9ef3-4747-9802-76aa406a5115
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206814366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2206814366
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.2172709777
Short name T549
Test name
Test status
Simulation time 318021890508 ps
CPU time 105.87 seconds
Started Feb 04 12:57:14 PM PST 24
Finished Feb 04 12:59:01 PM PST 24
Peak memory 182508 kb
Host smart-b6a521a2-d587-4432-96fe-6f3bfcadeac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172709777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2172709777
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.2608111396
Short name T247
Test name
Test status
Simulation time 26407437924 ps
CPU time 19.4 seconds
Started Feb 04 12:57:08 PM PST 24
Finished Feb 04 12:57:34 PM PST 24
Peak memory 182424 kb
Host smart-79f7a5b3-f4cd-4bf2-904d-78488b177342
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608111396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2608111396
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3434224769
Short name T264
Test name
Test status
Simulation time 164600107690 ps
CPU time 101.89 seconds
Started Feb 04 12:57:14 PM PST 24
Finished Feb 04 12:58:57 PM PST 24
Peak memory 182464 kb
Host smart-71fcf40d-1f60-4564-9303-110857cab551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434224769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3434224769
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.3269836364
Short name T34
Test name
Test status
Simulation time 90976732610 ps
CPU time 598.5 seconds
Started Feb 04 12:57:17 PM PST 24
Finished Feb 04 01:07:16 PM PST 24
Peak memory 205424 kb
Host smart-44fb1e79-760c-45c0-afc4-e5eef676782a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269836364 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.3269836364
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3313574764
Short name T244
Test name
Test status
Simulation time 232870124958 ps
CPU time 128.45 seconds
Started Feb 04 12:57:18 PM PST 24
Finished Feb 04 12:59:27 PM PST 24
Peak memory 182520 kb
Host smart-6086db15-be34-48df-8501-77370ca8094c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313574764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3313574764
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.240569973
Short name T481
Test name
Test status
Simulation time 61949681235 ps
CPU time 101.61 seconds
Started Feb 04 12:57:17 PM PST 24
Finished Feb 04 12:58:59 PM PST 24
Peak memory 182536 kb
Host smart-14ce36b2-c028-4e14-bd1d-e7c92d5135b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240569973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.240569973
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.494542009
Short name T191
Test name
Test status
Simulation time 7488832450 ps
CPU time 16.83 seconds
Started Feb 04 12:57:17 PM PST 24
Finished Feb 04 12:57:35 PM PST 24
Peak memory 182572 kb
Host smart-352ca5b0-f38d-437a-a959-e0020244b9d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494542009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.494542009
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.893924371
Short name T509
Test name
Test status
Simulation time 2390934087 ps
CPU time 1.2 seconds
Started Feb 04 12:57:18 PM PST 24
Finished Feb 04 12:57:20 PM PST 24
Peak memory 191748 kb
Host smart-b72d7f85-130d-4f01-b826-8dafab727e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893924371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.893924371
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.701294660
Short name T546
Test name
Test status
Simulation time 594524328748 ps
CPU time 487.17 seconds
Started Feb 04 12:57:09 PM PST 24
Finished Feb 04 01:05:22 PM PST 24
Peak memory 194832 kb
Host smart-3594edf7-81c7-4a1c-b35d-23405cab1fec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701294660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.
701294660
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.1828778306
Short name T295
Test name
Test status
Simulation time 58793773910 ps
CPU time 1038.53 seconds
Started Feb 04 12:57:23 PM PST 24
Finished Feb 04 01:14:43 PM PST 24
Peak memory 205900 kb
Host smart-cd9341e8-a182-499b-9a35-5e0d36e85723
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828778306 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.1828778306
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1524752057
Short name T250
Test name
Test status
Simulation time 143848696024 ps
CPU time 184.05 seconds
Started Feb 04 12:57:13 PM PST 24
Finished Feb 04 01:00:19 PM PST 24
Peak memory 182376 kb
Host smart-5d6e5d20-023a-4b0e-9cee-b89cc12af48c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524752057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1524752057
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.4067184125
Short name T535
Test name
Test status
Simulation time 661330535807 ps
CPU time 259.06 seconds
Started Feb 04 12:57:23 PM PST 24
Finished Feb 04 01:01:43 PM PST 24
Peak memory 182404 kb
Host smart-7f939663-cb68-49e5-bf6c-e098d3c066a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067184125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.4067184125
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1707255033
Short name T220
Test name
Test status
Simulation time 107522402452 ps
CPU time 56.57 seconds
Started Feb 04 12:57:13 PM PST 24
Finished Feb 04 12:58:11 PM PST 24
Peak memory 182492 kb
Host smart-ffc4c499-c67d-4b95-aba5-0b1fe21c58bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707255033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1707255033
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2592461005
Short name T480
Test name
Test status
Simulation time 93316198 ps
CPU time 0.76 seconds
Started Feb 04 12:59:16 PM PST 24
Finished Feb 04 12:59:18 PM PST 24
Peak memory 179976 kb
Host smart-7b95af34-3eec-4ea2-b6dc-fd97c82af6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592461005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2592461005
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.1717491147
Short name T216
Test name
Test status
Simulation time 369899046536 ps
CPU time 846.35 seconds
Started Feb 04 12:57:12 PM PST 24
Finished Feb 04 01:11:21 PM PST 24
Peak memory 208696 kb
Host smart-0ab4a9cf-62da-49f1-81ff-084a78f75907
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717491147 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.1717491147
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.4040384922
Short name T536
Test name
Test status
Simulation time 238809568779 ps
CPU time 376.51 seconds
Started Feb 04 12:57:12 PM PST 24
Finished Feb 04 01:03:31 PM PST 24
Peak memory 182404 kb
Host smart-64156102-4e4a-4ac6-a937-0a03e0bd6c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040384922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.4040384922
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.1851013519
Short name T233
Test name
Test status
Simulation time 633471983234 ps
CPU time 648.55 seconds
Started Feb 04 12:57:11 PM PST 24
Finished Feb 04 01:08:03 PM PST 24
Peak memory 190672 kb
Host smart-51211cb5-b9a1-45ae-af4f-1252cb9c834b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851013519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.1851013519
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2376128339
Short name T273
Test name
Test status
Simulation time 559297924 ps
CPU time 1.71 seconds
Started Feb 04 12:57:23 PM PST 24
Finished Feb 04 12:57:26 PM PST 24
Peak memory 190292 kb
Host smart-075fedff-c09b-4c6a-8c82-416bbed3cf5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376128339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2376128339
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.2631917507
Short name T537
Test name
Test status
Simulation time 29910711859 ps
CPU time 209.81 seconds
Started Feb 04 12:57:23 PM PST 24
Finished Feb 04 01:00:54 PM PST 24
Peak memory 205268 kb
Host smart-3ca618b9-b918-42ca-977c-8dce34b50fdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631917507 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.2631917507
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.1210334790
Short name T288
Test name
Test status
Simulation time 50921787849 ps
CPU time 84.35 seconds
Started Feb 04 12:59:16 PM PST 24
Finished Feb 04 01:00:41 PM PST 24
Peak memory 180036 kb
Host smart-304f053f-68f4-4690-9b72-224c544f6b11
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210334790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.1210334790
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.2795957409
Short name T533
Test name
Test status
Simulation time 69700913908 ps
CPU time 118.1 seconds
Started Feb 04 12:59:16 PM PST 24
Finished Feb 04 01:01:15 PM PST 24
Peak memory 180160 kb
Host smart-c105dd64-46f7-41bb-b24a-3fc481a3af5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795957409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2795957409
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.783045257
Short name T534
Test name
Test status
Simulation time 219753555 ps
CPU time 1.49 seconds
Started Feb 04 12:57:23 PM PST 24
Finished Feb 04 12:57:26 PM PST 24
Peak memory 182356 kb
Host smart-e640eeaf-6627-4a92-b3e8-71f3b3c38294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783045257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.783045257
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2399188989
Short name T53
Test name
Test status
Simulation time 1030645178724 ps
CPU time 436.79 seconds
Started Feb 04 12:57:10 PM PST 24
Finished Feb 04 01:04:31 PM PST 24
Peak memory 195144 kb
Host smart-8f328769-8aa4-4580-a560-b5f1f49a0047
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399188989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2399188989
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.2283061002
Short name T598
Test name
Test status
Simulation time 92156273242 ps
CPU time 672.07 seconds
Started Feb 04 12:57:23 PM PST 24
Finished Feb 04 01:08:36 PM PST 24
Peak memory 205380 kb
Host smart-48dbd390-b1ca-4664-a2f8-9ea5fe68248b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283061002 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.2283061002
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.342924914
Short name T292
Test name
Test status
Simulation time 70662803508 ps
CPU time 64.71 seconds
Started Feb 04 12:57:10 PM PST 24
Finished Feb 04 12:58:19 PM PST 24
Peak memory 182532 kb
Host smart-93cde0b4-5e88-4a90-aea6-faeaf71296ca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342924914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.342924914
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.1574424056
Short name T547
Test name
Test status
Simulation time 215658208845 ps
CPU time 79.27 seconds
Started Feb 04 12:57:15 PM PST 24
Finished Feb 04 12:58:35 PM PST 24
Peak memory 182444 kb
Host smart-6634cf9f-9a0c-4cf0-8ff9-3e151581b912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574424056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1574424056
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.1730985390
Short name T282
Test name
Test status
Simulation time 11525945888 ps
CPU time 21.42 seconds
Started Feb 04 12:59:16 PM PST 24
Finished Feb 04 12:59:39 PM PST 24
Peak memory 180364 kb
Host smart-fbcc4a3e-1362-444e-9268-4efc5595add6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730985390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1730985390
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.544554158
Short name T226
Test name
Test status
Simulation time 2221568280205 ps
CPU time 1456.24 seconds
Started Feb 04 12:57:18 PM PST 24
Finished Feb 04 01:21:35 PM PST 24
Peak memory 190728 kb
Host smart-a206b231-67a9-4a05-af5b-a9c767faec06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544554158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.
544554158
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.1795996088
Short name T572
Test name
Test status
Simulation time 31372163031 ps
CPU time 237.49 seconds
Started Feb 04 12:57:22 PM PST 24
Finished Feb 04 01:01:21 PM PST 24
Peak memory 197132 kb
Host smart-c5ef16c8-9b2b-4548-a232-ff0df2dc248f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795996088 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.1795996088
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1885229469
Short name T116
Test name
Test status
Simulation time 493114403954 ps
CPU time 285.47 seconds
Started Feb 04 12:57:12 PM PST 24
Finished Feb 04 01:02:00 PM PST 24
Peak memory 182472 kb
Host smart-31bd8580-9808-48e4-90b7-558780ed1fdc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885229469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1885229469
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1187667274
Short name T584
Test name
Test status
Simulation time 188147850049 ps
CPU time 325.7 seconds
Started Feb 04 12:57:09 PM PST 24
Finished Feb 04 01:02:40 PM PST 24
Peak memory 182520 kb
Host smart-4fa7aa30-b410-497b-92b6-8fda0da1dc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187667274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1187667274
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.1814257858
Short name T573
Test name
Test status
Simulation time 63585058891 ps
CPU time 123.15 seconds
Started Feb 04 12:57:11 PM PST 24
Finished Feb 04 12:59:17 PM PST 24
Peak memory 190796 kb
Host smart-0b043213-114a-4b8e-a49d-03936c7ad75a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814257858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1814257858
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.531500732
Short name T114
Test name
Test status
Simulation time 6643053644 ps
CPU time 11.48 seconds
Started Feb 04 12:57:15 PM PST 24
Finished Feb 04 12:57:27 PM PST 24
Peak memory 193788 kb
Host smart-f00c2cfb-9636-4d22-b82f-d863cc6bab57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531500732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.531500732
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2073606736
Short name T329
Test name
Test status
Simulation time 7236813893171 ps
CPU time 1396.78 seconds
Started Feb 04 12:57:21 PM PST 24
Finished Feb 04 01:20:39 PM PST 24
Peak memory 190704 kb
Host smart-f6e4a929-db83-4b73-9d2c-0dce8bab7caa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073606736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2073606736
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3570587554
Short name T559
Test name
Test status
Simulation time 141417749338 ps
CPU time 125.57 seconds
Started Feb 04 12:57:24 PM PST 24
Finished Feb 04 12:59:31 PM PST 24
Peak memory 182260 kb
Host smart-3ca3bea3-cca6-43a1-9f82-8d88ceb50316
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570587554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.3570587554
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.255494464
Short name T496
Test name
Test status
Simulation time 662318734824 ps
CPU time 169.44 seconds
Started Feb 04 12:57:22 PM PST 24
Finished Feb 04 01:00:12 PM PST 24
Peak memory 182432 kb
Host smart-08e1b12f-bbb3-4da9-af66-2d6e6563cd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255494464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.255494464
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.1742905034
Short name T200
Test name
Test status
Simulation time 144450673633 ps
CPU time 241.13 seconds
Started Feb 04 12:57:10 PM PST 24
Finished Feb 04 01:01:15 PM PST 24
Peak memory 190728 kb
Host smart-ebee2200-b81c-488b-8edd-63fcab7134f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742905034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1742905034
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2622931814
Short name T5
Test name
Test status
Simulation time 556411630708 ps
CPU time 643.59 seconds
Started Feb 04 12:57:27 PM PST 24
Finished Feb 04 01:08:12 PM PST 24
Peak memory 193976 kb
Host smart-7df52bd1-6e3e-44ed-b0fc-e65c4a1926eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622931814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2622931814
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.2956022054
Short name T12
Test name
Test status
Simulation time 158792312552 ps
CPU time 308.95 seconds
Started Feb 04 12:57:22 PM PST 24
Finished Feb 04 01:02:31 PM PST 24
Peak memory 205500 kb
Host smart-7a167cd6-24e9-450b-ae4c-add14faef1e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956022054 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.2956022054
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3931619769
Short name T344
Test name
Test status
Simulation time 75977136996 ps
CPU time 75.24 seconds
Started Feb 04 12:57:21 PM PST 24
Finished Feb 04 12:58:37 PM PST 24
Peak memory 182512 kb
Host smart-9bf884ec-d471-40fe-92e2-a6e97d4089b0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931619769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.3931619769
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2298781408
Short name T366
Test name
Test status
Simulation time 123778490571 ps
CPU time 184.71 seconds
Started Feb 04 12:57:21 PM PST 24
Finished Feb 04 01:00:27 PM PST 24
Peak memory 182404 kb
Host smart-3a042375-7128-4130-b577-f7aad01db567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298781408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2298781408
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.3504145254
Short name T313
Test name
Test status
Simulation time 94056909623 ps
CPU time 92.26 seconds
Started Feb 04 12:57:27 PM PST 24
Finished Feb 04 12:59:01 PM PST 24
Peak memory 182544 kb
Host smart-4564507f-6fa1-4f59-a42c-f583314356c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504145254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3504145254
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1539073341
Short name T487
Test name
Test status
Simulation time 114201430 ps
CPU time 0.71 seconds
Started Feb 04 12:57:21 PM PST 24
Finished Feb 04 12:57:22 PM PST 24
Peak memory 182264 kb
Host smart-88d09c19-8c13-46f7-b66b-4f853f18199b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539073341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1539073341
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.633874330
Short name T614
Test name
Test status
Simulation time 20750798 ps
CPU time 0.59 seconds
Started Feb 04 12:57:22 PM PST 24
Finished Feb 04 12:57:23 PM PST 24
Peak memory 181984 kb
Host smart-1e360ed3-6acb-4d9b-91d0-79a83633f1b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633874330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.
633874330
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.1919555587
Short name T346
Test name
Test status
Simulation time 23896929991 ps
CPU time 176.11 seconds
Started Feb 04 12:57:25 PM PST 24
Finished Feb 04 01:00:22 PM PST 24
Peak memory 197256 kb
Host smart-dadb101b-b587-4e14-9e6d-3be04ec8ead3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919555587 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.1919555587
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2196989938
Short name T315
Test name
Test status
Simulation time 359061255883 ps
CPU time 200.8 seconds
Started Feb 04 12:57:07 PM PST 24
Finished Feb 04 01:00:33 PM PST 24
Peak memory 182496 kb
Host smart-2e8a557a-9038-4dcf-ae3e-d70e8cae6267
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196989938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2196989938
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1112077791
Short name T542
Test name
Test status
Simulation time 241766523660 ps
CPU time 102.39 seconds
Started Feb 04 12:56:49 PM PST 24
Finished Feb 04 12:58:37 PM PST 24
Peak memory 182468 kb
Host smart-39b8a455-403e-43f8-982e-4743eadd0ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112077791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1112077791
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.1399874847
Short name T18
Test name
Test status
Simulation time 171312407 ps
CPU time 0.79 seconds
Started Feb 04 12:56:44 PM PST 24
Finished Feb 04 12:56:49 PM PST 24
Peak memory 212712 kb
Host smart-71b7a51e-d68a-4284-a34d-2fcf9f06f59e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399874847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1399874847
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.975733649
Short name T289
Test name
Test status
Simulation time 113741954794 ps
CPU time 1193.14 seconds
Started Feb 04 12:56:49 PM PST 24
Finished Feb 04 01:16:49 PM PST 24
Peak memory 209424 kb
Host smart-c8794a64-bfa0-46f6-b727-29a8ffa3f801
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975733649 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.975733649
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.795814115
Short name T616
Test name
Test status
Simulation time 347859190040 ps
CPU time 191.22 seconds
Started Feb 04 12:59:22 PM PST 24
Finished Feb 04 01:02:34 PM PST 24
Peak memory 182268 kb
Host smart-06c76d0f-f1cc-41d2-a827-ddb47b1d61eb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795814115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.rv_timer_cfg_update_on_fly.795814115
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2075367842
Short name T567
Test name
Test status
Simulation time 267601599882 ps
CPU time 115.71 seconds
Started Feb 04 12:57:25 PM PST 24
Finished Feb 04 12:59:22 PM PST 24
Peak memory 182600 kb
Host smart-a29c6fa8-8c41-40b4-8119-ff5fbc7d0018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075367842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2075367842
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2269786066
Short name T125
Test name
Test status
Simulation time 152504694837 ps
CPU time 3149.26 seconds
Started Feb 04 12:57:24 PM PST 24
Finished Feb 04 01:49:54 PM PST 24
Peak memory 190756 kb
Host smart-f66420a4-87c5-43c5-adc9-ad31090edd12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269786066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2269786066
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1175349306
Short name T527
Test name
Test status
Simulation time 83192606 ps
CPU time 0.77 seconds
Started Feb 04 12:57:26 PM PST 24
Finished Feb 04 12:57:27 PM PST 24
Peak memory 182388 kb
Host smart-a0671f0c-f23e-4ff0-ae55-e51a18117da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175349306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1175349306
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.4149539773
Short name T276
Test name
Test status
Simulation time 447054078817 ps
CPU time 976.57 seconds
Started Feb 04 12:57:30 PM PST 24
Finished Feb 04 01:13:49 PM PST 24
Peak memory 207016 kb
Host smart-d627a832-85b9-4b38-bd20-29a271363bf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149539773 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.4149539773
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2566392965
Short name T281
Test name
Test status
Simulation time 125806539104 ps
CPU time 193.97 seconds
Started Feb 04 12:57:19 PM PST 24
Finished Feb 04 01:00:33 PM PST 24
Peak memory 182508 kb
Host smart-8f044b39-6d4d-44f5-aa89-99c30b841a77
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566392965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2566392965
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.2868182961
Short name T501
Test name
Test status
Simulation time 130522494394 ps
CPU time 200.59 seconds
Started Feb 04 12:57:20 PM PST 24
Finished Feb 04 01:00:42 PM PST 24
Peak memory 182560 kb
Host smart-0eb9f05b-e8f2-4955-bab0-16f6065fb7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868182961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.2868182961
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.46251535
Short name T610
Test name
Test status
Simulation time 451393824545 ps
CPU time 462.31 seconds
Started Feb 04 12:57:25 PM PST 24
Finished Feb 04 01:05:09 PM PST 24
Peak memory 190800 kb
Host smart-f25c148e-f102-4a7b-b0f2-8a1894720293
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46251535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.46251535
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3433008016
Short name T261
Test name
Test status
Simulation time 259125764394 ps
CPU time 117.9 seconds
Started Feb 04 12:57:24 PM PST 24
Finished Feb 04 12:59:23 PM PST 24
Peak memory 190776 kb
Host smart-6386371c-1866-4208-a247-bd0949d6d9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433008016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3433008016
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.3990158259
Short name T562
Test name
Test status
Simulation time 181839755837 ps
CPU time 318.67 seconds
Started Feb 04 12:57:25 PM PST 24
Finished Feb 04 01:02:45 PM PST 24
Peak memory 190676 kb
Host smart-1085bf47-1be3-4b8b-bd43-6b194bd5d622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990158259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.3990158259
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.1682700527
Short name T583
Test name
Test status
Simulation time 31132668915 ps
CPU time 130.4 seconds
Started Feb 04 12:57:22 PM PST 24
Finished Feb 04 12:59:34 PM PST 24
Peak memory 197220 kb
Host smart-16291051-00b4-497d-8519-93e238b9c082
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682700527 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.1682700527
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3720707268
Short name T268
Test name
Test status
Simulation time 2302417064701 ps
CPU time 680.74 seconds
Started Feb 04 12:57:20 PM PST 24
Finished Feb 04 01:08:42 PM PST 24
Peak memory 182448 kb
Host smart-36c4118c-c552-4547-87c9-d509dc3e6012
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720707268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3720707268
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2366079021
Short name T603
Test name
Test status
Simulation time 803140031554 ps
CPU time 331.1 seconds
Started Feb 04 12:57:24 PM PST 24
Finished Feb 04 01:02:56 PM PST 24
Peak memory 182180 kb
Host smart-ec96eb96-91bd-4fc0-91a4-9bb7e0db6fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366079021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2366079021
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.372448001
Short name T545
Test name
Test status
Simulation time 40381768860 ps
CPU time 718.74 seconds
Started Feb 04 12:57:24 PM PST 24
Finished Feb 04 01:09:24 PM PST 24
Peak memory 182468 kb
Host smart-3d2a51b3-63ed-4bc1-be1e-37ed0dc666ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372448001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.372448001
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1002126857
Short name T131
Test name
Test status
Simulation time 255263362509 ps
CPU time 30.31 seconds
Started Feb 04 12:57:26 PM PST 24
Finished Feb 04 12:57:57 PM PST 24
Peak memory 182448 kb
Host smart-23cb54f3-5d99-4183-a093-8391e3f14db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002126857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1002126857
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.2190919060
Short name T237
Test name
Test status
Simulation time 314917040793 ps
CPU time 573.21 seconds
Started Feb 04 12:59:20 PM PST 24
Finished Feb 04 01:08:54 PM PST 24
Peak memory 212736 kb
Host smart-ef07b2a2-4110-40bb-ad81-f5821b1853e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190919060 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.2190919060
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.153348912
Short name T615
Test name
Test status
Simulation time 45649316256 ps
CPU time 26.29 seconds
Started Feb 04 12:57:25 PM PST 24
Finished Feb 04 12:57:52 PM PST 24
Peak memory 182452 kb
Host smart-0d447577-2fd9-4474-be91-f85084954da3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153348912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.153348912
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.1001248471
Short name T367
Test name
Test status
Simulation time 232038884036 ps
CPU time 304.01 seconds
Started Feb 04 12:57:25 PM PST 24
Finished Feb 04 01:02:30 PM PST 24
Peak memory 182432 kb
Host smart-dbfe61ef-5b0f-4889-90d4-b6d945565884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001248471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1001248471
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.446175664
Short name T196
Test name
Test status
Simulation time 71219979565 ps
CPU time 235.6 seconds
Started Feb 04 12:57:22 PM PST 24
Finished Feb 04 01:01:19 PM PST 24
Peak memory 190708 kb
Host smart-330050db-0508-4af2-93b9-7f24d006deeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446175664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.446175664
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.297432298
Short name T530
Test name
Test status
Simulation time 113198958 ps
CPU time 1.05 seconds
Started Feb 04 12:57:24 PM PST 24
Finished Feb 04 12:57:26 PM PST 24
Peak memory 182520 kb
Host smart-21fc893f-847a-42ba-8a91-ac50b2766e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297432298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.297432298
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.2580204792
Short name T539
Test name
Test status
Simulation time 879277697614 ps
CPU time 797.29 seconds
Started Feb 04 12:57:24 PM PST 24
Finished Feb 04 01:10:43 PM PST 24
Peak memory 201468 kb
Host smart-f9a11882-a91d-40c6-9197-15042e3419ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580204792 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.2580204792
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3910360406
Short name T208
Test name
Test status
Simulation time 279731277944 ps
CPU time 287.3 seconds
Started Feb 04 12:57:24 PM PST 24
Finished Feb 04 01:02:13 PM PST 24
Peak memory 182484 kb
Host smart-773eab33-586d-4fdb-8a87-5bb9cf6e0140
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910360406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3910360406
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.2898522901
Short name T493
Test name
Test status
Simulation time 221058496741 ps
CPU time 179.25 seconds
Started Feb 04 12:57:23 PM PST 24
Finished Feb 04 01:00:23 PM PST 24
Peak memory 182516 kb
Host smart-5cd77174-0c2c-4bc0-9f01-36683deea039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898522901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2898522901
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.193120539
Short name T117
Test name
Test status
Simulation time 50874901324 ps
CPU time 45.95 seconds
Started Feb 04 12:57:22 PM PST 24
Finished Feb 04 12:58:09 PM PST 24
Peak memory 192088 kb
Host smart-81ddf470-8ff5-4ecc-b9c6-15071d9d4667
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193120539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.193120539
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2716671204
Short name T579
Test name
Test status
Simulation time 58678971350 ps
CPU time 1085.91 seconds
Started Feb 04 12:57:28 PM PST 24
Finished Feb 04 01:15:35 PM PST 24
Peak memory 190728 kb
Host smart-d5769c23-9f44-4b01-8da3-172509f4a739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716671204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2716671204
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.2998935630
Short name T602
Test name
Test status
Simulation time 116747582306 ps
CPU time 169.19 seconds
Started Feb 04 12:59:04 PM PST 24
Finished Feb 04 01:01:54 PM PST 24
Peak memory 189772 kb
Host smart-2dea0f52-d719-49ec-acc3-2154e5223f02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998935630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.2998935630
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.2300283010
Short name T490
Test name
Test status
Simulation time 50509769750 ps
CPU time 314.49 seconds
Started Feb 04 12:57:25 PM PST 24
Finished Feb 04 01:02:41 PM PST 24
Peak memory 205336 kb
Host smart-a0f8dc2e-11d4-49ba-bd07-ea07c869ad0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300283010 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.2300283010
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.446199077
Short name T592
Test name
Test status
Simulation time 777719910502 ps
CPU time 372.33 seconds
Started Feb 04 12:59:22 PM PST 24
Finished Feb 04 01:05:35 PM PST 24
Peak memory 182264 kb
Host smart-dccee985-fc41-4d5f-a06b-7b5be229ae22
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446199077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.rv_timer_cfg_update_on_fly.446199077
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3011573610
Short name T10
Test name
Test status
Simulation time 30147927223 ps
CPU time 46.36 seconds
Started Feb 04 12:59:19 PM PST 24
Finished Feb 04 01:00:07 PM PST 24
Peak memory 182172 kb
Host smart-7e9f3882-4744-4294-82c5-19fd4941290a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011573610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3011573610
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.2550363191
Short name T168
Test name
Test status
Simulation time 1010243265776 ps
CPU time 473.56 seconds
Started Feb 04 12:57:22 PM PST 24
Finished Feb 04 01:05:16 PM PST 24
Peak memory 190628 kb
Host smart-2e41df96-0e5f-43bb-8f5c-54df5887f9da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550363191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2550363191
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.448947894
Short name T486
Test name
Test status
Simulation time 31565573 ps
CPU time 0.53 seconds
Started Feb 04 12:59:18 PM PST 24
Finished Feb 04 12:59:19 PM PST 24
Peak memory 181280 kb
Host smart-c5602083-94f4-4cb3-b8bc-1be955398d9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448947894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.
448947894
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.1345245176
Short name T521
Test name
Test status
Simulation time 75423517931 ps
CPU time 857.34 seconds
Started Feb 04 12:57:22 PM PST 24
Finished Feb 04 01:11:41 PM PST 24
Peak memory 213556 kb
Host smart-7a6d113c-54bc-421a-b41b-40edd8934026
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345245176 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.1345245176
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.4034791954
Short name T181
Test name
Test status
Simulation time 538035224876 ps
CPU time 492.26 seconds
Started Feb 04 12:57:28 PM PST 24
Finished Feb 04 01:05:42 PM PST 24
Peak memory 182480 kb
Host smart-1ef8b1ed-8a6d-4e0a-9ae1-56baada9077a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034791954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.4034791954
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.2787118822
Short name T569
Test name
Test status
Simulation time 207656391686 ps
CPU time 146.64 seconds
Started Feb 04 12:57:27 PM PST 24
Finished Feb 04 12:59:55 PM PST 24
Peak memory 182540 kb
Host smart-a5dac93d-023f-4d6e-afa6-dcb4779268e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787118822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2787118822
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.3132125781
Short name T550
Test name
Test status
Simulation time 49380494408 ps
CPU time 35.27 seconds
Started Feb 04 12:59:22 PM PST 24
Finished Feb 04 12:59:58 PM PST 24
Peak memory 181868 kb
Host smart-479ed018-0d48-49e3-9204-8c234496377b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132125781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3132125781
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3075418015
Short name T236
Test name
Test status
Simulation time 215566763494 ps
CPU time 331.72 seconds
Started Feb 04 12:59:19 PM PST 24
Finished Feb 04 01:04:52 PM PST 24
Peak memory 190360 kb
Host smart-c4904306-1e17-41b7-be1d-8f7f42dad284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075418015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3075418015
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.482179560
Short name T620
Test name
Test status
Simulation time 680019840936 ps
CPU time 612.31 seconds
Started Feb 04 12:57:33 PM PST 24
Finished Feb 04 01:07:51 PM PST 24
Peak memory 190676 kb
Host smart-622f0f2b-0374-4628-bddc-69d9dfba6c8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482179560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.
482179560
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.1813652998
Short name T320
Test name
Test status
Simulation time 158724079593 ps
CPU time 561.01 seconds
Started Feb 04 12:57:32 PM PST 24
Finished Feb 04 01:06:55 PM PST 24
Peak memory 205512 kb
Host smart-ac14b00b-8332-431c-bf0d-3ddcfc76fc27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813652998 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.1813652998
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1936038509
Short name T364
Test name
Test status
Simulation time 41496978003 ps
CPU time 65.41 seconds
Started Feb 04 12:57:36 PM PST 24
Finished Feb 04 12:58:45 PM PST 24
Peak memory 182528 kb
Host smart-8ff691dc-88ff-4fa8-92fb-1018d0b276cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936038509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1936038509
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1071210700
Short name T541
Test name
Test status
Simulation time 54570130 ps
CPU time 0.55 seconds
Started Feb 04 12:57:32 PM PST 24
Finished Feb 04 12:57:34 PM PST 24
Peak memory 182172 kb
Host smart-c73fe10b-e815-4c01-b44c-bbcfe0920b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071210700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1071210700
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.1356594560
Short name T323
Test name
Test status
Simulation time 706262620030 ps
CPU time 1118.97 seconds
Started Feb 04 12:57:33 PM PST 24
Finished Feb 04 01:16:18 PM PST 24
Peak memory 190732 kb
Host smart-fed62c9a-7f73-4251-a446-0c23d75d2804
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356594560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.1356594560
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.3789903661
Short name T574
Test name
Test status
Simulation time 134852123327 ps
CPU time 500.11 seconds
Started Feb 04 12:57:30 PM PST 24
Finished Feb 04 01:05:52 PM PST 24
Peak memory 205304 kb
Host smart-28aa1283-cc83-4f2e-820c-63fe040bd7a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789903661 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.3789903661
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1775122971
Short name T606
Test name
Test status
Simulation time 9323071883 ps
CPU time 9.96 seconds
Started Feb 04 12:57:39 PM PST 24
Finished Feb 04 12:57:50 PM PST 24
Peak memory 182448 kb
Host smart-14d47693-e9f0-4cc4-b683-78c3cc7c5bca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775122971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1775122971
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.703194350
Short name T608
Test name
Test status
Simulation time 148714397078 ps
CPU time 99.54 seconds
Started Feb 04 12:57:37 PM PST 24
Finished Feb 04 12:59:19 PM PST 24
Peak memory 182544 kb
Host smart-95777498-60e4-4d1e-be1c-023318cf38ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703194350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.703194350
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.4293123771
Short name T140
Test name
Test status
Simulation time 110941833008 ps
CPU time 241.87 seconds
Started Feb 04 12:57:29 PM PST 24
Finished Feb 04 01:01:33 PM PST 24
Peak memory 190608 kb
Host smart-0d3dcc3a-710e-4a3d-9cb3-f066337cde08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293123771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.4293123771
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2493470273
Short name T258
Test name
Test status
Simulation time 203981984554 ps
CPU time 94.27 seconds
Started Feb 04 12:59:18 PM PST 24
Finished Feb 04 01:00:53 PM PST 24
Peak memory 192964 kb
Host smart-56f1b770-f23d-465c-a433-48fae0e5108f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493470273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2493470273
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.924846011
Short name T499
Test name
Test status
Simulation time 1953022257097 ps
CPU time 739.27 seconds
Started Feb 04 12:57:31 PM PST 24
Finished Feb 04 01:09:52 PM PST 24
Peak memory 190692 kb
Host smart-9bf76f1d-a2a1-44ea-b612-42e1bd36bc8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924846011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.
924846011
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.2509411491
Short name T508
Test name
Test status
Simulation time 24282473632 ps
CPU time 261.51 seconds
Started Feb 04 12:57:29 PM PST 24
Finished Feb 04 01:01:53 PM PST 24
Peak memory 197148 kb
Host smart-214258a7-a18c-4b44-b1f0-b39a0eb2af1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509411491 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.2509411491
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.1508123186
Short name T511
Test name
Test status
Simulation time 205669295373 ps
CPU time 115.87 seconds
Started Feb 04 12:57:45 PM PST 24
Finished Feb 04 12:59:43 PM PST 24
Peak memory 182524 kb
Host smart-01930883-2d1b-475a-886b-a59e8d31f9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508123186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1508123186
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.54271661
Short name T106
Test name
Test status
Simulation time 656005261975 ps
CPU time 465.1 seconds
Started Feb 04 12:57:38 PM PST 24
Finished Feb 04 01:05:25 PM PST 24
Peak memory 192840 kb
Host smart-1570e2fe-d2c9-4d62-837c-e3cdc60aeb56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54271661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.54271661
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.513159041
Short name T302
Test name
Test status
Simulation time 89383841157 ps
CPU time 479.87 seconds
Started Feb 04 12:57:30 PM PST 24
Finished Feb 04 01:05:32 PM PST 24
Peak memory 190736 kb
Host smart-dee72ef9-8731-473b-9fb6-c419c4321607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513159041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.513159041
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.2763709733
Short name T13
Test name
Test status
Simulation time 113265543582 ps
CPU time 850.59 seconds
Started Feb 04 12:57:30 PM PST 24
Finished Feb 04 01:11:43 PM PST 24
Peak memory 205408 kb
Host smart-9dc848e6-05e7-4bd4-a1d4-228b8e4e4eac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763709733 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.2763709733
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3176900484
Short name T587
Test name
Test status
Simulation time 211700052688 ps
CPU time 93.09 seconds
Started Feb 04 12:56:49 PM PST 24
Finished Feb 04 12:58:28 PM PST 24
Peak memory 182528 kb
Host smart-33a65af7-d544-4b5b-a590-ea465d292d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176900484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3176900484
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.728949993
Short name T360
Test name
Test status
Simulation time 400424027481 ps
CPU time 282.95 seconds
Started Feb 04 12:57:07 PM PST 24
Finished Feb 04 01:01:55 PM PST 24
Peak memory 193672 kb
Host smart-65a5e24b-e2dc-4baa-84fa-b19ac9ed3f1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728949993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.728949993
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3332840831
Short name T155
Test name
Test status
Simulation time 31690313991 ps
CPU time 76.06 seconds
Started Feb 04 12:56:44 PM PST 24
Finished Feb 04 12:58:03 PM PST 24
Peak memory 190716 kb
Host smart-6b37af2e-c822-4562-b2eb-596532cda52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332840831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3332840831
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.158702305
Short name T19
Test name
Test status
Simulation time 464788640 ps
CPU time 0.82 seconds
Started Feb 04 12:57:08 PM PST 24
Finished Feb 04 12:57:15 PM PST 24
Peak memory 212448 kb
Host smart-6c92a720-e64f-4c4a-9751-8672886b5de3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158702305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.158702305
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3534004048
Short name T531
Test name
Test status
Simulation time 56209738330 ps
CPU time 47.5 seconds
Started Feb 04 12:57:08 PM PST 24
Finished Feb 04 12:58:02 PM PST 24
Peak memory 182196 kb
Host smart-3f69c5ee-cd04-4282-9168-51edcbdaa009
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534004048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3534004048
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.2499192422
Short name T363
Test name
Test status
Simulation time 423495659513 ps
CPU time 925.4 seconds
Started Feb 04 12:56:44 PM PST 24
Finished Feb 04 01:12:13 PM PST 24
Peak memory 208184 kb
Host smart-9925e721-3a6c-4a93-8d76-bcd4ac690e1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499192422 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.2499192422
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.489240889
Short name T334
Test name
Test status
Simulation time 807781711395 ps
CPU time 472.69 seconds
Started Feb 04 12:57:39 PM PST 24
Finished Feb 04 01:05:33 PM PST 24
Peak memory 182412 kb
Host smart-b87ae3fb-4ff7-4f3d-9517-516e9ff4e7d3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489240889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.rv_timer_cfg_update_on_fly.489240889
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2723598432
Short name T540
Test name
Test status
Simulation time 151281705809 ps
CPU time 67.61 seconds
Started Feb 04 12:57:31 PM PST 24
Finished Feb 04 12:58:40 PM PST 24
Peak memory 182488 kb
Host smart-6b2f961e-9cc4-4710-b399-a90776f013db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723598432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2723598432
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.38632886
Short name T180
Test name
Test status
Simulation time 104442771740 ps
CPU time 85.93 seconds
Started Feb 04 12:57:32 PM PST 24
Finished Feb 04 12:58:59 PM PST 24
Peak memory 190744 kb
Host smart-c659a873-d963-4c20-8cfa-60717aae3d86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38632886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.38632886
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.3809607996
Short name T322
Test name
Test status
Simulation time 89818084411 ps
CPU time 1232.57 seconds
Started Feb 04 12:57:33 PM PST 24
Finished Feb 04 01:18:12 PM PST 24
Peak memory 193880 kb
Host smart-be556d48-a98d-4b3c-b006-76477a7819ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809607996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3809607996
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.2032596285
Short name T518
Test name
Test status
Simulation time 181698417519 ps
CPU time 395.52 seconds
Started Feb 04 12:57:55 PM PST 24
Finished Feb 04 01:04:31 PM PST 24
Peak memory 205436 kb
Host smart-a679d05a-bb13-43cd-a6f7-ed882e45e4d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032596285 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.2032596285
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2295917645
Short name T121
Test name
Test status
Simulation time 996427817828 ps
CPU time 583.4 seconds
Started Feb 04 12:57:32 PM PST 24
Finished Feb 04 01:07:17 PM PST 24
Peak memory 182476 kb
Host smart-8e6a1357-2d18-40d4-a2f6-c50d9b88fbc2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295917645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2295917645
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2326970583
Short name T494
Test name
Test status
Simulation time 43898232763 ps
CPU time 59.43 seconds
Started Feb 04 12:57:31 PM PST 24
Finished Feb 04 12:58:32 PM PST 24
Peak memory 182424 kb
Host smart-e212c4ee-7ba8-4680-8a49-136807fd37b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326970583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2326970583
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.2337665965
Short name T99
Test name
Test status
Simulation time 167039834508 ps
CPU time 163.59 seconds
Started Feb 04 12:57:43 PM PST 24
Finished Feb 04 01:00:27 PM PST 24
Peak memory 193932 kb
Host smart-7017dce6-b80f-44b6-9459-7c19fb0a5e5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337665965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2337665965
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2078897648
Short name T347
Test name
Test status
Simulation time 30275172958 ps
CPU time 51.5 seconds
Started Feb 04 12:57:28 PM PST 24
Finished Feb 04 12:58:21 PM PST 24
Peak memory 182400 kb
Host smart-10617ba8-4f02-4f5d-b55d-db6748816621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078897648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2078897648
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.3337615839
Short name T498
Test name
Test status
Simulation time 26549355727 ps
CPU time 225.71 seconds
Started Feb 04 12:57:31 PM PST 24
Finished Feb 04 01:01:19 PM PST 24
Peak memory 197116 kb
Host smart-f8d796d5-47d2-4ce9-9c14-db7c30b0a872
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337615839 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.3337615839
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.4235546274
Short name T566
Test name
Test status
Simulation time 34640760352 ps
CPU time 14.89 seconds
Started Feb 04 12:57:32 PM PST 24
Finished Feb 04 12:57:49 PM PST 24
Peak memory 182552 kb
Host smart-9a5e1e60-0acb-46f9-997d-f02693d793fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235546274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.4235546274
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.248924685
Short name T483
Test name
Test status
Simulation time 132073013815 ps
CPU time 366.96 seconds
Started Feb 04 12:57:36 PM PST 24
Finished Feb 04 01:03:47 PM PST 24
Peak memory 205452 kb
Host smart-e706eb93-1b0e-49f7-a375-b76165d9fe9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248924685 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.248924685
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3798094751
Short name T230
Test name
Test status
Simulation time 166202149995 ps
CPU time 278.29 seconds
Started Feb 04 12:57:31 PM PST 24
Finished Feb 04 01:02:11 PM PST 24
Peak memory 182476 kb
Host smart-0cf6934b-3f00-4501-a4d4-37f1b4150605
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798094751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3798094751
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.2807863030
Short name T517
Test name
Test status
Simulation time 399073745428 ps
CPU time 185.81 seconds
Started Feb 04 12:57:32 PM PST 24
Finished Feb 04 01:00:39 PM PST 24
Peak memory 182308 kb
Host smart-233140ed-4fda-44a2-afda-7df3bd042be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807863030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2807863030
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.3411479379
Short name T152
Test name
Test status
Simulation time 166585728815 ps
CPU time 221.89 seconds
Started Feb 04 12:57:43 PM PST 24
Finished Feb 04 01:01:25 PM PST 24
Peak memory 190808 kb
Host smart-6045d1e3-42ab-4305-868b-7b37b77148e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411479379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3411479379
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.1082879118
Short name T327
Test name
Test status
Simulation time 95233726298 ps
CPU time 48.01 seconds
Started Feb 04 12:57:38 PM PST 24
Finished Feb 04 12:58:28 PM PST 24
Peak memory 190480 kb
Host smart-0c1de6c9-030f-4685-bd25-dabd5ff2ee2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082879118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1082879118
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.1236902644
Short name T520
Test name
Test status
Simulation time 37284582551 ps
CPU time 61.81 seconds
Started Feb 04 12:57:55 PM PST 24
Finished Feb 04 12:58:57 PM PST 24
Peak memory 182532 kb
Host smart-eaf2bb89-b65c-493e-93ec-ce497fe7b2e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236902644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.1236902644
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.2575052001
Short name T488
Test name
Test status
Simulation time 52910879972 ps
CPU time 652.37 seconds
Started Feb 04 12:57:33 PM PST 24
Finished Feb 04 01:08:31 PM PST 24
Peak memory 205344 kb
Host smart-d8f2805c-740d-4e82-a692-e424678da388
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575052001 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.2575052001
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1183440452
Short name T94
Test name
Test status
Simulation time 71406701611 ps
CPU time 127.53 seconds
Started Feb 04 12:57:48 PM PST 24
Finished Feb 04 12:59:56 PM PST 24
Peak memory 182496 kb
Host smart-69a0cee8-20c3-49e2-afae-5e79d75df109
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183440452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1183440452
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.50084220
Short name T580
Test name
Test status
Simulation time 656508113233 ps
CPU time 170.51 seconds
Started Feb 04 12:57:55 PM PST 24
Finished Feb 04 01:00:47 PM PST 24
Peak memory 182580 kb
Host smart-c39aafee-7f17-4c41-bf2b-d92330b89988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50084220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.50084220
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1395256585
Short name T571
Test name
Test status
Simulation time 145478304135 ps
CPU time 300.17 seconds
Started Feb 04 12:57:38 PM PST 24
Finished Feb 04 01:02:40 PM PST 24
Peak memory 190704 kb
Host smart-38fa3594-1735-46a4-9260-52ec51a82568
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395256585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1395256585
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1843488976
Short name T564
Test name
Test status
Simulation time 38076802521 ps
CPU time 68.63 seconds
Started Feb 04 12:57:38 PM PST 24
Finished Feb 04 12:58:48 PM PST 24
Peak memory 190572 kb
Host smart-589f0c92-0a9b-4808-8f09-dd67027e821a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843488976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1843488976
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.3482158391
Short name T538
Test name
Test status
Simulation time 208001151457 ps
CPU time 424.72 seconds
Started Feb 04 12:57:33 PM PST 24
Finished Feb 04 01:04:43 PM PST 24
Peak memory 205292 kb
Host smart-e6523867-a996-49e4-b54b-18cd3bd1aa33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482158391 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.3482158391
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.2964222884
Short name T111
Test name
Test status
Simulation time 51315426988 ps
CPU time 29.07 seconds
Started Feb 04 12:57:29 PM PST 24
Finished Feb 04 12:58:01 PM PST 24
Peak memory 182520 kb
Host smart-f49c041c-6ee7-4a7e-bac9-cd6de10cae12
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964222884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.2964222884
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2367046222
Short name T558
Test name
Test status
Simulation time 520053212403 ps
CPU time 212.29 seconds
Started Feb 04 12:57:39 PM PST 24
Finished Feb 04 01:01:12 PM PST 24
Peak memory 182444 kb
Host smart-87efd2ec-d619-4466-a254-3dc64a23372f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367046222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2367046222
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.3085116591
Short name T591
Test name
Test status
Simulation time 637042037880 ps
CPU time 136.26 seconds
Started Feb 04 12:57:30 PM PST 24
Finished Feb 04 12:59:49 PM PST 24
Peak memory 190752 kb
Host smart-b4a9d729-cc7c-4960-bf1e-5fd7a34d17c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085116591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3085116591
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2324750834
Short name T28
Test name
Test status
Simulation time 112947764334 ps
CPU time 1490.75 seconds
Started Feb 04 12:57:35 PM PST 24
Finished Feb 04 01:22:31 PM PST 24
Peak memory 182452 kb
Host smart-c4b67d96-f682-4d7c-ae7a-6f7ec2011c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324750834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2324750834
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.1341117759
Short name T186
Test name
Test status
Simulation time 239004371324 ps
CPU time 115.81 seconds
Started Feb 04 12:57:38 PM PST 24
Finished Feb 04 12:59:36 PM PST 24
Peak memory 182408 kb
Host smart-1fa4d9bd-b1e9-4c44-a321-4700c8a5e76d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341117759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.1341117759
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.770160851
Short name T503
Test name
Test status
Simulation time 22035847549 ps
CPU time 223.43 seconds
Started Feb 04 12:57:38 PM PST 24
Finished Feb 04 01:01:23 PM PST 24
Peak memory 197072 kb
Host smart-27bc1a26-fc60-4600-a5bf-1fc9464b30d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770160851 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.770160851
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3405085941
Short name T589
Test name
Test status
Simulation time 43271712337 ps
CPU time 65.5 seconds
Started Feb 04 12:57:35 PM PST 24
Finished Feb 04 12:58:45 PM PST 24
Peak memory 182348 kb
Host smart-db90e73f-b767-4750-a79a-639a4df7b6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405085941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3405085941
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.2885508089
Short name T184
Test name
Test status
Simulation time 37433158348 ps
CPU time 63.1 seconds
Started Feb 04 12:57:35 PM PST 24
Finished Feb 04 12:58:43 PM PST 24
Peak memory 190700 kb
Host smart-ebd8220a-014b-4896-b11a-6267dd98dd2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885508089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2885508089
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3542122953
Short name T556
Test name
Test status
Simulation time 396194053327 ps
CPU time 256.34 seconds
Started Feb 04 12:57:36 PM PST 24
Finished Feb 04 01:01:56 PM PST 24
Peak memory 190696 kb
Host smart-b620376e-2cc6-4ad3-ae6b-598b61084da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542122953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3542122953
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.2579645567
Short name T526
Test name
Test status
Simulation time 545750987136 ps
CPU time 798.15 seconds
Started Feb 04 12:57:32 PM PST 24
Finished Feb 04 01:10:56 PM PST 24
Peak memory 208028 kb
Host smart-24ea7b55-cf12-4c01-8b85-ef14c8320605
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579645567 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.2579645567
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1668800262
Short name T585
Test name
Test status
Simulation time 2417635098714 ps
CPU time 1266.04 seconds
Started Feb 04 12:57:37 PM PST 24
Finished Feb 04 01:18:46 PM PST 24
Peak memory 182460 kb
Host smart-aee86930-e892-43e5-97b4-bf4ff710b14c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668800262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1668800262
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2837493006
Short name T575
Test name
Test status
Simulation time 519029787272 ps
CPU time 203.94 seconds
Started Feb 04 12:57:38 PM PST 24
Finished Feb 04 01:01:04 PM PST 24
Peak memory 182340 kb
Host smart-806a844c-1390-4a99-8e52-407537563a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837493006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2837493006
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3460206611
Short name T555
Test name
Test status
Simulation time 85280787709 ps
CPU time 181.96 seconds
Started Feb 04 12:57:30 PM PST 24
Finished Feb 04 01:00:34 PM PST 24
Peak memory 194232 kb
Host smart-d952de4c-307d-4563-8642-f47711cbe561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460206611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3460206611
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.2530898767
Short name T577
Test name
Test status
Simulation time 76762212 ps
CPU time 0.53 seconds
Started Feb 04 12:57:32 PM PST 24
Finished Feb 04 12:57:34 PM PST 24
Peak memory 181720 kb
Host smart-d1eb4ac1-8332-4d14-85ea-24921b9b732b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530898767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.2530898767
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.229147719
Short name T24
Test name
Test status
Simulation time 782670042931 ps
CPU time 692.65 seconds
Started Feb 04 12:57:44 PM PST 24
Finished Feb 04 01:09:19 PM PST 24
Peak memory 182484 kb
Host smart-b5eab9f9-b25a-4725-90ec-f9ff26927319
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229147719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.229147719
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1292113721
Short name T619
Test name
Test status
Simulation time 140485185008 ps
CPU time 184.12 seconds
Started Feb 04 12:57:43 PM PST 24
Finished Feb 04 01:00:50 PM PST 24
Peak memory 182532 kb
Host smart-b85e2f45-70d4-4370-93e4-822fdd1c46ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292113721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1292113721
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.4177899132
Short name T109
Test name
Test status
Simulation time 1591370820737 ps
CPU time 444.01 seconds
Started Feb 04 12:57:52 PM PST 24
Finished Feb 04 01:05:19 PM PST 24
Peak memory 189772 kb
Host smart-9979a444-330f-432e-85e3-9cbca4895470
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177899132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.4177899132
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.1555772075
Short name T519
Test name
Test status
Simulation time 67234874391 ps
CPU time 550.51 seconds
Started Feb 04 12:57:44 PM PST 24
Finished Feb 04 01:06:56 PM PST 24
Peak memory 205240 kb
Host smart-2493a352-8a4d-4b1b-a9f5-70eedc98a91b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555772075 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.1555772075
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.71852374
Short name T240
Test name
Test status
Simulation time 165722188472 ps
CPU time 302.62 seconds
Started Feb 04 12:57:44 PM PST 24
Finished Feb 04 01:02:49 PM PST 24
Peak memory 182484 kb
Host smart-355e6200-3242-41b4-bf20-ba3a1352767e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71852374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.rv_timer_cfg_update_on_fly.71852374
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1130604805
Short name T544
Test name
Test status
Simulation time 255161685032 ps
CPU time 276.2 seconds
Started Feb 04 12:57:39 PM PST 24
Finished Feb 04 01:02:17 PM PST 24
Peak memory 182432 kb
Host smart-9ffdc7f5-b625-4cbb-a7f7-51db16e36d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130604805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1130604805
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.822335279
Short name T39
Test name
Test status
Simulation time 130365216667 ps
CPU time 64.3 seconds
Started Feb 04 12:57:40 PM PST 24
Finished Feb 04 12:58:45 PM PST 24
Peak memory 182516 kb
Host smart-63f3f671-1176-4081-8b6d-115fc719f9da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822335279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.822335279
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1649154141
Short name T358
Test name
Test status
Simulation time 33333835075 ps
CPU time 53.5 seconds
Started Feb 04 12:57:39 PM PST 24
Finished Feb 04 12:58:34 PM PST 24
Peak memory 182524 kb
Host smart-c0930ca9-acfc-4e44-8e1b-33d18d068b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649154141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1649154141
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.756077843
Short name T138
Test name
Test status
Simulation time 635254868884 ps
CPU time 2210.79 seconds
Started Feb 04 12:57:44 PM PST 24
Finished Feb 04 01:34:37 PM PST 24
Peak memory 190740 kb
Host smart-5a45bcd6-4c82-445a-9ae7-526a757d7a0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756077843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
756077843
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.2123336113
Short name T81
Test name
Test status
Simulation time 2556110175246 ps
CPU time 1168.12 seconds
Started Feb 04 12:57:44 PM PST 24
Finished Feb 04 01:17:15 PM PST 24
Peak memory 211004 kb
Host smart-35d5b4ab-313a-469f-84e7-32209c3a9394
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123336113 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.2123336113
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.2952782959
Short name T305
Test name
Test status
Simulation time 151446145466 ps
CPU time 249.76 seconds
Started Feb 04 12:56:56 PM PST 24
Finished Feb 04 01:01:08 PM PST 24
Peak memory 182508 kb
Host smart-3e2d6bab-10f6-4d4f-9732-4a5ce296d2cd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952782959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.2952782959
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3474442153
Short name T522
Test name
Test status
Simulation time 183195694083 ps
CPU time 283.82 seconds
Started Feb 04 12:57:03 PM PST 24
Finished Feb 04 01:01:49 PM PST 24
Peak memory 182572 kb
Host smart-ac4591bb-f50c-438b-939a-b1ac8d7805e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474442153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3474442153
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.3135013442
Short name T206
Test name
Test status
Simulation time 277127399650 ps
CPU time 172.39 seconds
Started Feb 04 12:56:46 PM PST 24
Finished Feb 04 12:59:41 PM PST 24
Peak memory 193868 kb
Host smart-5bd372b8-572a-483b-bd87-97d26f37626d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135013442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3135013442
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.1538057733
Short name T514
Test name
Test status
Simulation time 601602232 ps
CPU time 1.33 seconds
Started Feb 04 12:56:59 PM PST 24
Finished Feb 04 12:57:03 PM PST 24
Peak memory 182388 kb
Host smart-6aec9baf-82a8-4f36-acaf-b3a49295bda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538057733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1538057733
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.2898947768
Short name T495
Test name
Test status
Simulation time 137039115374 ps
CPU time 216.35 seconds
Started Feb 04 12:57:01 PM PST 24
Finished Feb 04 01:00:40 PM PST 24
Peak memory 182452 kb
Host smart-628347e2-1592-4219-aad5-dad650621caa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898947768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
2898947768
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.3135349957
Short name T497
Test name
Test status
Simulation time 126176539363 ps
CPU time 574.54 seconds
Started Feb 04 12:57:10 PM PST 24
Finished Feb 04 01:06:49 PM PST 24
Peak memory 205324 kb
Host smart-6721ba48-d5a1-4ec4-9354-84e9e6464e30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135349957 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.3135349957
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.412654093
Short name T269
Test name
Test status
Simulation time 119084432798 ps
CPU time 109.87 seconds
Started Feb 04 12:57:43 PM PST 24
Finished Feb 04 12:59:34 PM PST 24
Peak memory 190792 kb
Host smart-182b1b72-02f7-4e30-a640-deeaa4d8b8e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412654093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.412654093
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.3377334913
Short name T278
Test name
Test status
Simulation time 824103856476 ps
CPU time 147.68 seconds
Started Feb 04 12:57:52 PM PST 24
Finished Feb 04 01:00:22 PM PST 24
Peak memory 189908 kb
Host smart-72f39b31-2319-4180-ba85-e925e4a502a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377334913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3377334913
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.2579788632
Short name T172
Test name
Test status
Simulation time 261179907162 ps
CPU time 400.42 seconds
Started Feb 04 12:57:37 PM PST 24
Finished Feb 04 01:04:20 PM PST 24
Peak memory 190760 kb
Host smart-a6c29913-8538-44b4-bb3c-646a53d30964
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579788632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2579788632
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.730169516
Short name T218
Test name
Test status
Simulation time 179028157506 ps
CPU time 237.8 seconds
Started Feb 04 12:57:52 PM PST 24
Finished Feb 04 01:01:53 PM PST 24
Peak memory 190560 kb
Host smart-d98d80f1-0b33-4b01-996b-54f21273ddd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730169516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.730169516
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.3695912271
Short name T253
Test name
Test status
Simulation time 76030515237 ps
CPU time 148.93 seconds
Started Feb 04 12:57:41 PM PST 24
Finished Feb 04 01:00:11 PM PST 24
Peak memory 190740 kb
Host smart-84c88db4-0d8f-4045-b33d-efc619292f2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695912271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3695912271
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.3288013638
Short name T596
Test name
Test status
Simulation time 290812615614 ps
CPU time 209.76 seconds
Started Feb 04 12:57:43 PM PST 24
Finished Feb 04 01:01:15 PM PST 24
Peak memory 190484 kb
Host smart-65ac18b1-dd15-43d0-8981-04846492cbc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288013638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.3288013638
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3348101489
Short name T568
Test name
Test status
Simulation time 347038005265 ps
CPU time 364.83 seconds
Started Feb 04 12:57:43 PM PST 24
Finished Feb 04 01:03:49 PM PST 24
Peak memory 190796 kb
Host smart-3437bdf7-355d-4a09-8309-46d9ab30255f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348101489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3348101489
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1655760757
Short name T1
Test name
Test status
Simulation time 97210880085 ps
CPU time 560.35 seconds
Started Feb 04 12:57:37 PM PST 24
Finished Feb 04 01:07:00 PM PST 24
Peak memory 190744 kb
Host smart-01a13205-d856-44aa-823d-f8920fdaee0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655760757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1655760757
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.3762164628
Short name T298
Test name
Test status
Simulation time 41318664967 ps
CPU time 44.12 seconds
Started Feb 04 12:57:47 PM PST 24
Finished Feb 04 12:58:33 PM PST 24
Peak memory 190616 kb
Host smart-0dfa2b0d-e9e5-42ca-974b-31f91f3d9c75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762164628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3762164628
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.445017921
Short name T336
Test name
Test status
Simulation time 32028750835 ps
CPU time 18.95 seconds
Started Feb 04 12:56:57 PM PST 24
Finished Feb 04 12:57:17 PM PST 24
Peak memory 182524 kb
Host smart-77d18171-7e7a-4e0d-8b23-8ffcdd0f89e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445017921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.445017921
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.3406702878
Short name T560
Test name
Test status
Simulation time 504753842640 ps
CPU time 188.41 seconds
Started Feb 04 12:57:04 PM PST 24
Finished Feb 04 01:00:15 PM PST 24
Peak memory 182500 kb
Host smart-f4a2939c-fe65-4477-bdd0-9a5188742e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406702878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3406702878
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.3752400103
Short name T330
Test name
Test status
Simulation time 17448977245 ps
CPU time 30.81 seconds
Started Feb 04 12:57:03 PM PST 24
Finished Feb 04 12:57:37 PM PST 24
Peak memory 182548 kb
Host smart-04ac25ae-016a-47a4-b7a1-7360c4ffd547
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752400103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3752400103
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2886351644
Short name T7
Test name
Test status
Simulation time 296336662962 ps
CPU time 153.65 seconds
Started Feb 04 12:57:04 PM PST 24
Finished Feb 04 12:59:41 PM PST 24
Peak memory 194524 kb
Host smart-46f2b857-b535-4193-a621-59c84cc2bb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886351644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2886351644
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2614947396
Short name T8
Test name
Test status
Simulation time 730858535538 ps
CPU time 349.77 seconds
Started Feb 04 12:57:00 PM PST 24
Finished Feb 04 01:02:52 PM PST 24
Peak memory 190692 kb
Host smart-55086c74-f3bf-43d4-a384-d9bef09224a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614947396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2614947396
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.191916050
Short name T595
Test name
Test status
Simulation time 131710206627 ps
CPU time 562.38 seconds
Started Feb 04 12:57:05 PM PST 24
Finished Feb 04 01:06:30 PM PST 24
Peak memory 197808 kb
Host smart-6d70b391-3f81-443c-9533-49dedfa1a607
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191916050 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.191916050
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.938181154
Short name T189
Test name
Test status
Simulation time 1394808300177 ps
CPU time 821.89 seconds
Started Feb 04 12:57:43 PM PST 24
Finished Feb 04 01:11:27 PM PST 24
Peak memory 190796 kb
Host smart-9a435153-4b8d-487e-bfa3-4ff7cefe3190
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938181154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.938181154
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2640506954
Short name T9
Test name
Test status
Simulation time 38392877607 ps
CPU time 61.74 seconds
Started Feb 04 12:57:52 PM PST 24
Finished Feb 04 12:58:57 PM PST 24
Peak memory 190620 kb
Host smart-ae23d898-dd82-4e76-bb6a-0c8e627dbc38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640506954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2640506954
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.4102899997
Short name T331
Test name
Test status
Simulation time 60184677824 ps
CPU time 102.89 seconds
Started Feb 04 12:57:55 PM PST 24
Finished Feb 04 12:59:39 PM PST 24
Peak memory 193968 kb
Host smart-4b15cdbc-128b-43c3-b9c2-59f1308cd30c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102899997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.4102899997
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.3145724235
Short name T296
Test name
Test status
Simulation time 707290922320 ps
CPU time 702.98 seconds
Started Feb 04 12:57:58 PM PST 24
Finished Feb 04 01:09:41 PM PST 24
Peak memory 193168 kb
Host smart-a2f6e898-68aa-46ca-9861-ba8e2e818acb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145724235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3145724235
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.2582512221
Short name T193
Test name
Test status
Simulation time 32241629050 ps
CPU time 1145.14 seconds
Started Feb 04 12:57:54 PM PST 24
Finished Feb 04 01:17:00 PM PST 24
Peak memory 182528 kb
Host smart-6043a943-785b-4a0f-99dd-9c2cb94071ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582512221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2582512221
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.577610825
Short name T582
Test name
Test status
Simulation time 53293233444 ps
CPU time 43.53 seconds
Started Feb 04 12:57:52 PM PST 24
Finished Feb 04 12:58:38 PM PST 24
Peak memory 182604 kb
Host smart-f4949053-61fc-4330-aad0-601eb9ae2dba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577610825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.577610825
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1011090002
Short name T563
Test name
Test status
Simulation time 13801615638 ps
CPU time 26.53 seconds
Started Feb 04 12:57:54 PM PST 24
Finished Feb 04 12:58:22 PM PST 24
Peak memory 181784 kb
Host smart-782003bc-c0c1-45e9-901c-1aefab98e833
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011090002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1011090002
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.1960593062
Short name T308
Test name
Test status
Simulation time 218851340239 ps
CPU time 491.43 seconds
Started Feb 04 12:57:56 PM PST 24
Finished Feb 04 01:06:08 PM PST 24
Peak memory 190692 kb
Host smart-32bc576c-049f-48b4-bf10-7bbdc6103957
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960593062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1960593062
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.1143499841
Short name T252
Test name
Test status
Simulation time 1018379360123 ps
CPU time 814.13 seconds
Started Feb 04 12:57:56 PM PST 24
Finished Feb 04 01:11:31 PM PST 24
Peak memory 193844 kb
Host smart-1868a724-8505-4deb-a958-bd34eb57fd85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143499841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1143499841
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.2566803206
Short name T301
Test name
Test status
Simulation time 1614793821021 ps
CPU time 888.35 seconds
Started Feb 04 12:57:07 PM PST 24
Finished Feb 04 01:12:01 PM PST 24
Peak memory 182528 kb
Host smart-18c6bedd-852c-411c-b0d4-a225da8eb5df
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566803206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.2566803206
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.27044005
Short name T512
Test name
Test status
Simulation time 81194504005 ps
CPU time 70.37 seconds
Started Feb 04 12:56:57 PM PST 24
Finished Feb 04 12:58:11 PM PST 24
Peak memory 182596 kb
Host smart-58005ba2-2c09-4f24-a0b1-e2eadaed1e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27044005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.27044005
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.26773478
Short name T312
Test name
Test status
Simulation time 410926327111 ps
CPU time 740.21 seconds
Started Feb 04 12:56:56 PM PST 24
Finished Feb 04 01:09:18 PM PST 24
Peak memory 193864 kb
Host smart-1be41bab-29f2-4489-8f32-59abe7d14133
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26773478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.26773478
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1824244490
Short name T309
Test name
Test status
Simulation time 153890527387 ps
CPU time 107.12 seconds
Started Feb 04 12:56:55 PM PST 24
Finished Feb 04 12:58:44 PM PST 24
Peak memory 194240 kb
Host smart-685f4b95-ac13-42e6-b6c2-640dfd3c3b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824244490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1824244490
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.2810776965
Short name T600
Test name
Test status
Simulation time 205820926248 ps
CPU time 610.82 seconds
Started Feb 04 12:57:04 PM PST 24
Finished Feb 04 01:07:17 PM PST 24
Peak memory 209664 kb
Host smart-8df59fb3-9ab1-4ab9-b0d3-6033424f045e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810776965 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.2810776965
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.rv_timer_random.2812650424
Short name T529
Test name
Test status
Simulation time 5780371464 ps
CPU time 54.1 seconds
Started Feb 04 12:57:58 PM PST 24
Finished Feb 04 12:58:53 PM PST 24
Peak memory 182644 kb
Host smart-0c7710b6-39b5-4dfb-8b08-3a9b0ed699cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812650424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2812650424
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3931758426
Short name T108
Test name
Test status
Simulation time 259065468541 ps
CPU time 214.43 seconds
Started Feb 04 12:57:54 PM PST 24
Finished Feb 04 01:01:29 PM PST 24
Peak memory 190784 kb
Host smart-2f22a45a-80c7-4b65-b43e-03acc501386b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931758426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3931758426
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2018426538
Short name T332
Test name
Test status
Simulation time 23229664712 ps
CPU time 115.83 seconds
Started Feb 04 12:57:48 PM PST 24
Finished Feb 04 12:59:45 PM PST 24
Peak memory 194248 kb
Host smart-2386e99a-8ae5-45c5-9112-2949149ed31f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018426538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2018426538
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.4283636329
Short name T199
Test name
Test status
Simulation time 50518789211 ps
CPU time 91 seconds
Started Feb 04 12:57:50 PM PST 24
Finished Feb 04 12:59:26 PM PST 24
Peak memory 190680 kb
Host smart-76fc5573-0342-4894-87ce-54cf0a6d28ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283636329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.4283636329
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.2495363931
Short name T239
Test name
Test status
Simulation time 58042658096 ps
CPU time 94.68 seconds
Started Feb 04 12:58:00 PM PST 24
Finished Feb 04 12:59:35 PM PST 24
Peak memory 190844 kb
Host smart-49892c98-3edd-4ebe-96a1-59912bae9328
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495363931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2495363931
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.1396174691
Short name T25
Test name
Test status
Simulation time 105005665556 ps
CPU time 98.15 seconds
Started Feb 04 12:57:53 PM PST 24
Finished Feb 04 12:59:33 PM PST 24
Peak memory 190776 kb
Host smart-c48bd7a8-38e9-42f5-8335-13de23dc1be2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396174691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1396174691
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.668682932
Short name T543
Test name
Test status
Simulation time 38250825573 ps
CPU time 42.43 seconds
Started Feb 04 12:57:49 PM PST 24
Finished Feb 04 12:58:36 PM PST 24
Peak memory 190768 kb
Host smart-70724106-2bc7-4ca0-a2ca-fa0ed060570f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668682932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.668682932
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.2680221408
Short name T340
Test name
Test status
Simulation time 234825854139 ps
CPU time 26.35 seconds
Started Feb 04 12:58:00 PM PST 24
Finished Feb 04 12:58:27 PM PST 24
Peak memory 182688 kb
Host smart-ed960a2e-8155-4272-8827-a0e575f78a01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680221408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2680221408
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.960886143
Short name T287
Test name
Test status
Simulation time 834658905005 ps
CPU time 281.8 seconds
Started Feb 04 12:57:47 PM PST 24
Finished Feb 04 01:02:30 PM PST 24
Peak memory 190768 kb
Host smart-3014298e-bd7a-4560-815c-791690f61a63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960886143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.960886143
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3661694757
Short name T119
Test name
Test status
Simulation time 19925121937 ps
CPU time 40.05 seconds
Started Feb 04 12:57:00 PM PST 24
Finished Feb 04 12:57:42 PM PST 24
Peak memory 182424 kb
Host smart-bf6a2cc3-a6c3-4e74-9718-749018d54222
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661694757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3661694757
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3045502619
Short name T597
Test name
Test status
Simulation time 648291890985 ps
CPU time 280.46 seconds
Started Feb 04 12:57:00 PM PST 24
Finished Feb 04 01:01:43 PM PST 24
Peak memory 182480 kb
Host smart-993c8765-e65f-472b-b974-28d68e949546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045502619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3045502619
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3747430785
Short name T238
Test name
Test status
Simulation time 1143952080146 ps
CPU time 608.14 seconds
Started Feb 04 12:57:02 PM PST 24
Finished Feb 04 01:07:13 PM PST 24
Peak memory 190688 kb
Host smart-b510b17d-06e2-4e2a-86da-d32740ad1772
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747430785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3747430785
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1086892657
Short name T612
Test name
Test status
Simulation time 288146339713 ps
CPU time 206.28 seconds
Started Feb 04 12:57:04 PM PST 24
Finished Feb 04 01:00:33 PM PST 24
Peak memory 182520 kb
Host smart-46e3c5db-4115-4935-8658-d66de4541486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086892657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1086892657
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.1064420560
Short name T349
Test name
Test status
Simulation time 703486643202 ps
CPU time 498.53 seconds
Started Feb 04 12:56:58 PM PST 24
Finished Feb 04 01:05:20 PM PST 24
Peak memory 190724 kb
Host smart-58fbd276-5111-4565-beb0-8e03efb95ab0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064420560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
1064420560
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.748380355
Short name T524
Test name
Test status
Simulation time 180172949172 ps
CPU time 680.16 seconds
Started Feb 04 12:56:57 PM PST 24
Finished Feb 04 01:08:19 PM PST 24
Peak memory 213548 kb
Host smart-a9fabcb3-3369-4f7f-8353-1a24e9add188
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748380355 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.748380355
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.381254303
Short name T26
Test name
Test status
Simulation time 775732649339 ps
CPU time 392.65 seconds
Started Feb 04 12:57:57 PM PST 24
Finished Feb 04 01:04:31 PM PST 24
Peak memory 192996 kb
Host smart-6f54de39-ef7f-41fc-937f-f257a2eba1df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381254303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.381254303
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.4156172550
Short name T241
Test name
Test status
Simulation time 31262858285 ps
CPU time 52.61 seconds
Started Feb 04 12:58:00 PM PST 24
Finished Feb 04 12:58:53 PM PST 24
Peak memory 182684 kb
Host smart-2e46720d-e5df-48d0-8ef3-42e08149a305
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156172550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.4156172550
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.3707247020
Short name T166
Test name
Test status
Simulation time 151319186541 ps
CPU time 760.32 seconds
Started Feb 04 12:57:51 PM PST 24
Finished Feb 04 01:10:35 PM PST 24
Peak memory 190740 kb
Host smart-fa3d54e1-e6eb-4801-b6d6-08cc6f42e7b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707247020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3707247020
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3150692082
Short name T275
Test name
Test status
Simulation time 426478677364 ps
CPU time 208.84 seconds
Started Feb 04 12:57:51 PM PST 24
Finished Feb 04 01:01:24 PM PST 24
Peak memory 190720 kb
Host smart-55f07f39-07bb-48dd-a83e-c4d3ae473624
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150692082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3150692082
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.1728538941
Short name T245
Test name
Test status
Simulation time 235693601085 ps
CPU time 199.76 seconds
Started Feb 04 12:57:50 PM PST 24
Finished Feb 04 01:01:14 PM PST 24
Peak memory 190744 kb
Host smart-5903f744-608a-444d-ae2f-1deb4ca6d19b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728538941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1728538941
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.1685880199
Short name T290
Test name
Test status
Simulation time 299090219483 ps
CPU time 1241.6 seconds
Started Feb 04 12:57:59 PM PST 24
Finished Feb 04 01:18:42 PM PST 24
Peak memory 194012 kb
Host smart-3da565e5-b816-4455-bedb-4f2e7d6d48cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685880199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1685880199
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.1220972374
Short name T354
Test name
Test status
Simulation time 141562658780 ps
CPU time 87.61 seconds
Started Feb 04 12:57:57 PM PST 24
Finished Feb 04 12:59:26 PM PST 24
Peak memory 182516 kb
Host smart-e6adbe89-cf16-4e1f-8da2-e187aa656c8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220972374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1220972374
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.2083885110
Short name T147
Test name
Test status
Simulation time 706406629072 ps
CPU time 428.39 seconds
Started Feb 04 12:57:54 PM PST 24
Finished Feb 04 01:05:04 PM PST 24
Peak memory 192136 kb
Host smart-af54d7ea-1ea6-4cac-a75f-e6abcb5039cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083885110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2083885110
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.4226537060
Short name T510
Test name
Test status
Simulation time 488022293002 ps
CPU time 196.3 seconds
Started Feb 04 12:56:57 PM PST 24
Finished Feb 04 01:00:15 PM PST 24
Peak memory 182548 kb
Host smart-e16048b5-0bc9-4cf6-b815-45a507404abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226537060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.4226537060
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.1064574248
Short name T581
Test name
Test status
Simulation time 31748019388 ps
CPU time 26.61 seconds
Started Feb 04 12:57:05 PM PST 24
Finished Feb 04 12:57:34 PM PST 24
Peak memory 190756 kb
Host smart-5fed3dc3-3371-485a-82b5-99ab6f696875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064574248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.1064574248
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3298316931
Short name T262
Test name
Test status
Simulation time 13216311960 ps
CPU time 23.91 seconds
Started Feb 04 12:57:08 PM PST 24
Finished Feb 04 12:57:38 PM PST 24
Peak memory 190688 kb
Host smart-ac910279-c218-40ed-b6c6-346c1b16320b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298316931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3298316931
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.1479676995
Short name T195
Test name
Test status
Simulation time 945451732351 ps
CPU time 1516.54 seconds
Started Feb 04 12:57:04 PM PST 24
Finished Feb 04 01:22:24 PM PST 24
Peak memory 213640 kb
Host smart-a7978606-2b8b-4810-bfd1-314638f442bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479676995 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.1479676995
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.3952896909
Short name T213
Test name
Test status
Simulation time 536828479554 ps
CPU time 1153.07 seconds
Started Feb 04 12:57:48 PM PST 24
Finished Feb 04 01:17:02 PM PST 24
Peak memory 190724 kb
Host smart-a20b0c60-fb0b-48dd-8f17-a960f5ccc05c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952896909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3952896909
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.1264019720
Short name T333
Test name
Test status
Simulation time 36737508526 ps
CPU time 43.97 seconds
Started Feb 04 12:57:59 PM PST 24
Finished Feb 04 12:58:43 PM PST 24
Peak memory 182644 kb
Host smart-d74eab9b-a6ab-4cbc-a30f-9cf9303aa306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264019720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1264019720
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3005600462
Short name T120
Test name
Test status
Simulation time 1184851896465 ps
CPU time 1552.01 seconds
Started Feb 04 12:57:59 PM PST 24
Finished Feb 04 01:23:52 PM PST 24
Peak memory 190844 kb
Host smart-e2340ef1-9de3-42d9-af3f-e815eba1974c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005600462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3005600462
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3163750298
Short name T234
Test name
Test status
Simulation time 90802249194 ps
CPU time 153.4 seconds
Started Feb 04 12:57:49 PM PST 24
Finished Feb 04 01:00:28 PM PST 24
Peak memory 190568 kb
Host smart-4c04c6d9-1fcf-452c-a3a4-1a714d95a459
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163750298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3163750298
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3657911884
Short name T223
Test name
Test status
Simulation time 1258139715089 ps
CPU time 484.54 seconds
Started Feb 04 12:58:05 PM PST 24
Finished Feb 04 01:06:10 PM PST 24
Peak memory 190756 kb
Host smart-4e809b22-18d4-4034-97ef-82a89b26e7e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657911884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3657911884
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.192092750
Short name T254
Test name
Test status
Simulation time 153124300882 ps
CPU time 301.62 seconds
Started Feb 04 12:57:58 PM PST 24
Finished Feb 04 01:03:00 PM PST 24
Peak memory 182424 kb
Host smart-ed0fe490-da80-4f48-bbaa-069da4aad1ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192092750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.192092750
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.1793833201
Short name T306
Test name
Test status
Simulation time 22775356391 ps
CPU time 22.16 seconds
Started Feb 04 12:57:55 PM PST 24
Finished Feb 04 12:58:18 PM PST 24
Peak memory 182464 kb
Host smart-de182bc9-9c6f-427b-ae1b-3f18201d6fcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793833201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1793833201
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.3685303824
Short name T316
Test name
Test status
Simulation time 338257253010 ps
CPU time 356.96 seconds
Started Feb 04 12:57:55 PM PST 24
Finished Feb 04 01:03:53 PM PST 24
Peak memory 190784 kb
Host smart-15291860-66cb-4af1-8ca2-61bffb79a09c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685303824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3685303824
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.4215673321
Short name T231
Test name
Test status
Simulation time 69057502000 ps
CPU time 159.52 seconds
Started Feb 04 12:57:59 PM PST 24
Finished Feb 04 01:00:39 PM PST 24
Peak memory 190884 kb
Host smart-dfef340e-f2e0-45cb-bd9d-9010c4f5b034
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215673321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.4215673321
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.219878516
Short name T149
Test name
Test status
Simulation time 2353902603464 ps
CPU time 628.61 seconds
Started Feb 04 12:58:08 PM PST 24
Finished Feb 04 01:08:40 PM PST 24
Peak memory 190700 kb
Host smart-cd999a83-5d3e-445d-a21c-d0a36827209f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219878516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.219878516
Directory /workspace/99.rv_timer_random/latest
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