| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.66 | 99.36 | 98.73 | 100.00 | 100.00 | 100.00 | 99.89 |
| T563 | /workspace/coverage/default/41.rv_timer_disabled.1139722039 | Feb 07 12:36:42 PM PST 24 | Feb 07 12:38:23 PM PST 24 | 68654921589 ps | ||
| T564 | /workspace/coverage/default/48.rv_timer_disabled.2363541466 | Feb 07 12:36:47 PM PST 24 | Feb 07 12:38:44 PM PST 24 | 76120536122 ps | ||
| T277 | /workspace/coverage/default/154.rv_timer_random.1489163839 | Feb 07 12:36:50 PM PST 24 | Feb 07 12:43:52 PM PST 24 | 107851831670 ps | ||
| T295 | /workspace/coverage/default/15.rv_timer_stress_all.1695684532 | Feb 07 12:36:34 PM PST 24 | Feb 07 12:55:33 PM PST 24 | 1665267705774 ps | ||
| T565 | /workspace/coverage/default/130.rv_timer_random.296077628 | Feb 07 12:36:52 PM PST 24 | Feb 07 12:38:45 PM PST 24 | 517394727732 ps | ||
| T250 | /workspace/coverage/default/141.rv_timer_random.776470825 | Feb 07 12:36:55 PM PST 24 | Feb 07 12:43:01 PM PST 24 | 111285326709 ps | ||
| T566 | /workspace/coverage/default/45.rv_timer_disabled.2755032136 | Feb 07 12:36:46 PM PST 24 | Feb 07 12:37:56 PM PST 24 | 163896930583 ps | ||
| T241 | /workspace/coverage/default/153.rv_timer_random.2240548394 | Feb 07 12:36:50 PM PST 24 | Feb 07 12:41:33 PM PST 24 | 129809286776 ps | ||
| T333 | /workspace/coverage/default/56.rv_timer_random.3448941341 | Feb 07 12:37:35 PM PST 24 | Feb 07 12:37:51 PM PST 24 | 37710458141 ps | ||
| T567 | /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.2616608152 | Feb 07 12:36:45 PM PST 24 | Feb 07 12:53:12 PM PST 24 | 722722800889 ps | ||
| T568 | /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.1848248914 | Feb 07 12:36:40 PM PST 24 | Feb 07 12:48:19 PM PST 24 | 1490362017647 ps | ||
| T355 | /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2101093979 | Feb 07 12:36:24 PM PST 24 | Feb 07 12:46:02 PM PST 24 | 298245176243 ps | ||
| T146 | /workspace/coverage/default/48.rv_timer_stress_all.2832245930 | Feb 07 12:36:41 PM PST 24 | Feb 07 12:53:41 PM PST 24 | 1501567117396 ps | ||
| T569 | /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.3237138787 | Feb 07 12:36:41 PM PST 24 | Feb 07 12:39:25 PM PST 24 | 137480953239 ps | ||
| T296 | /workspace/coverage/default/105.rv_timer_random.980839253 | Feb 07 12:36:38 PM PST 24 | Feb 07 12:57:27 PM PST 24 | 1251009491477 ps | ||
| T320 | /workspace/coverage/default/36.rv_timer_random_reset.1101971076 | Feb 07 12:36:46 PM PST 24 | Feb 07 12:37:20 PM PST 24 | 19868990764 ps | ||
| T570 | /workspace/coverage/default/38.rv_timer_random_reset.3683129023 | Feb 07 12:36:44 PM PST 24 | Feb 07 12:37:24 PM PST 24 | 59720232622 ps | ||
| T571 | /workspace/coverage/default/33.rv_timer_random_reset.3346791745 | Feb 07 12:36:44 PM PST 24 | Feb 07 12:36:46 PM PST 24 | 362417749 ps | ||
| T192 | /workspace/coverage/default/45.rv_timer_random.3107947828 | Feb 07 12:36:34 PM PST 24 | Feb 07 12:43:50 PM PST 24 | 195821313644 ps | ||
| T193 | /workspace/coverage/default/36.rv_timer_random.1871161056 | Feb 07 12:36:44 PM PST 24 | Feb 07 12:37:23 PM PST 24 | 13334309847 ps | ||
| T222 | /workspace/coverage/default/12.rv_timer_random.2139412664 | Feb 07 12:36:38 PM PST 24 | Feb 07 12:59:17 PM PST 24 | 1993899205720 ps | ||
| T572 | /workspace/coverage/default/4.rv_timer_random_reset.4206680998 | Feb 07 12:36:01 PM PST 24 | Feb 07 12:36:04 PM PST 24 | 1139670257 ps | ||
| T316 | /workspace/coverage/default/178.rv_timer_random.406434159 | Feb 07 12:37:01 PM PST 24 | Feb 07 01:10:43 PM PST 24 | 382077519672 ps | ||
| T573 | /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.3129822754 | Feb 07 12:36:29 PM PST 24 | Feb 07 12:43:03 PM PST 24 | 124831048180 ps | ||
| T299 | /workspace/coverage/default/25.rv_timer_random.3465580902 | Feb 07 12:36:26 PM PST 24 | Feb 07 12:50:03 PM PST 24 | 2668866704690 ps | ||
| T236 | /workspace/coverage/default/186.rv_timer_random.40346220 | Feb 07 12:37:07 PM PST 24 | Feb 07 12:51:12 PM PST 24 | 152062977264 ps | ||
| T574 | /workspace/coverage/default/26.rv_timer_random_reset.2431092829 | Feb 07 12:36:34 PM PST 24 | Feb 07 12:36:37 PM PST 24 | 1812520589 ps | ||
| T224 | /workspace/coverage/default/183.rv_timer_random.1768678847 | Feb 07 12:37:04 PM PST 24 | Feb 07 12:38:05 PM PST 24 | 159701247134 ps | ||
| T326 | /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2028259356 | Feb 07 12:36:37 PM PST 24 | Feb 07 12:51:37 PM PST 24 | 1699379432925 ps | ||
| T575 | /workspace/coverage/default/33.rv_timer_random.4207790313 | Feb 07 12:36:42 PM PST 24 | Feb 07 12:44:45 PM PST 24 | 337873017587 ps | ||
| T576 | /workspace/coverage/default/84.rv_timer_random.734740129 | Feb 07 12:36:36 PM PST 24 | Feb 07 12:42:24 PM PST 24 | 155752831184 ps | ||
| T577 | /workspace/coverage/default/18.rv_timer_disabled.3995353318 | Feb 07 12:36:13 PM PST 24 | Feb 07 12:36:29 PM PST 24 | 19215308486 ps | ||
| T159 | /workspace/coverage/default/22.rv_timer_stress_all.2667684781 | Feb 07 12:36:23 PM PST 24 | Feb 07 01:23:30 PM PST 24 | 815952444951 ps | ||
| T578 | /workspace/coverage/default/74.rv_timer_random.4149845295 | Feb 07 12:36:37 PM PST 24 | Feb 07 12:48:06 PM PST 24 | 33835870985 ps | ||
| T349 | /workspace/coverage/default/122.rv_timer_random.1499447758 | Feb 07 12:36:50 PM PST 24 | Feb 07 01:15:03 PM PST 24 | 595152395458 ps | ||
| T139 | /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.267387238 | Feb 07 12:36:17 PM PST 24 | Feb 07 12:48:54 PM PST 24 | 78537825691 ps | ||
| T368 | /workspace/coverage/default/90.rv_timer_random.1187589784 | Feb 07 12:36:39 PM PST 24 | Feb 07 12:44:45 PM PST 24 | 478346745379 ps | ||
| T579 | /workspace/coverage/default/41.rv_timer_random.848361880 | Feb 07 12:36:46 PM PST 24 | Feb 07 12:44:20 PM PST 24 | 160803777326 ps | ||
| T580 | /workspace/coverage/default/179.rv_timer_random.4217400911 | Feb 07 12:36:56 PM PST 24 | Feb 07 12:37:28 PM PST 24 | 31784323782 ps | ||
| T581 | /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.862627798 | Feb 07 12:36:49 PM PST 24 | Feb 07 12:59:56 PM PST 24 | 189754393888 ps | ||
| T201 | /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1083637891 | Feb 07 12:36:42 PM PST 24 | Feb 07 12:41:09 PM PST 24 | 733943837435 ps | ||
| T196 | /workspace/coverage/default/69.rv_timer_random.2284862655 | Feb 07 12:36:30 PM PST 24 | Feb 07 12:39:14 PM PST 24 | 151827969599 ps | ||
| T582 | /workspace/coverage/default/41.rv_timer_random_reset.4020276566 | Feb 07 12:36:45 PM PST 24 | Feb 07 12:37:59 PM PST 24 | 100156855060 ps | ||
| T356 | /workspace/coverage/default/0.rv_timer_stress_all.3788694155 | Feb 07 12:36:01 PM PST 24 | Feb 07 12:49:00 PM PST 24 | 388777031305 ps | ||
| T583 | /workspace/coverage/default/39.rv_timer_random_reset.1709265669 | Feb 07 12:36:53 PM PST 24 | Feb 07 12:37:06 PM PST 24 | 10575231208 ps | ||
| T584 | /workspace/coverage/default/8.rv_timer_random_reset.2466086742 | Feb 07 12:36:13 PM PST 24 | Feb 07 12:37:52 PM PST 24 | 112824142350 ps | ||
| T361 | /workspace/coverage/default/29.rv_timer_random.534938030 | Feb 07 12:36:47 PM PST 24 | Feb 07 12:41:19 PM PST 24 | 235263869029 ps | ||
| T585 | /workspace/coverage/default/40.rv_timer_disabled.1479515393 | Feb 07 12:36:54 PM PST 24 | Feb 07 12:37:32 PM PST 24 | 47426675384 ps | ||
| T270 | /workspace/coverage/default/29.rv_timer_random_reset.3261818417 | Feb 07 12:36:34 PM PST 24 | Feb 07 12:59:25 PM PST 24 | 97333467546 ps | ||
| T586 | /workspace/coverage/default/25.rv_timer_disabled.805019783 | Feb 07 12:36:28 PM PST 24 | Feb 07 12:37:47 PM PST 24 | 454097531886 ps | ||
| T587 | /workspace/coverage/default/113.rv_timer_random.2978329583 | Feb 07 12:36:50 PM PST 24 | Feb 07 12:37:41 PM PST 24 | 111669223448 ps | ||
| T588 | /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3585285542 | Feb 07 12:37:43 PM PST 24 | Feb 07 12:43:05 PM PST 24 | 713151274191 ps | ||
| T589 | /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.4166168252 | Feb 07 12:36:04 PM PST 24 | Feb 07 12:49:03 PM PST 24 | 62510204617 ps | ||
| T19 | /workspace/coverage/default/3.rv_timer_sec_cm.1110069704 | Feb 07 12:36:17 PM PST 24 | Feb 07 12:36:18 PM PST 24 | 456919370 ps | ||
| T26 | /workspace/coverage/default/15.rv_timer_random_reset.1137637848 | Feb 07 12:36:11 PM PST 24 | Feb 07 01:04:13 PM PST 24 | 195592224524 ps | ||
| T27 | /workspace/coverage/default/58.rv_timer_random.2159265115 | Feb 07 12:36:41 PM PST 24 | Feb 07 12:48:51 PM PST 24 | 443011663980 ps | ||
| T28 | /workspace/coverage/default/46.rv_timer_stress_all.2700073890 | Feb 07 12:36:42 PM PST 24 | Feb 07 12:47:37 PM PST 24 | 351804090771 ps | ||
| T29 | /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1178515081 | Feb 07 12:36:48 PM PST 24 | Feb 07 12:41:10 PM PST 24 | 292437091320 ps | ||
| T30 | /workspace/coverage/default/13.rv_timer_random_reset.1232898203 | Feb 07 12:36:25 PM PST 24 | Feb 07 12:36:29 PM PST 24 | 2211909693 ps | ||
| T590 | /workspace/coverage/default/164.rv_timer_random.1801265225 | Feb 07 12:37:00 PM PST 24 | Feb 07 12:38:30 PM PST 24 | 103803476535 ps | ||
| T283 | /workspace/coverage/default/16.rv_timer_stress_all.4126535151 | Feb 07 12:36:11 PM PST 24 | Feb 07 12:40:03 PM PST 24 | 590677692662 ps | ||
| T591 | /workspace/coverage/default/75.rv_timer_random.1816241224 | Feb 07 12:36:46 PM PST 24 | Feb 07 12:41:12 PM PST 24 | 451704140174 ps | ||
| T350 | /workspace/coverage/default/13.rv_timer_random.322777680 | Feb 07 12:36:18 PM PST 24 | Feb 07 12:46:29 PM PST 24 | 385234340176 ps | ||
| T344 | /workspace/coverage/default/42.rv_timer_random_reset.1534627348 | Feb 07 12:37:35 PM PST 24 | Feb 07 12:38:31 PM PST 24 | 5441764343 ps | ||
| T345 | /workspace/coverage/default/161.rv_timer_random.1928542506 | Feb 07 12:36:57 PM PST 24 | Feb 07 12:39:27 PM PST 24 | 87727981734 ps | ||
| T592 | /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.1371300616 | Feb 07 12:36:47 PM PST 24 | Feb 07 12:52:58 PM PST 24 | 452525861794 ps | ||
| T228 | /workspace/coverage/default/138.rv_timer_random.2975271948 | Feb 07 12:36:52 PM PST 24 | Feb 07 12:44:59 PM PST 24 | 3258526707260 ps | ||
| T593 | /workspace/coverage/default/46.rv_timer_random_reset.603733373 | Feb 07 12:36:29 PM PST 24 | Feb 07 12:36:30 PM PST 24 | 17123905 ps | ||
| T594 | /workspace/coverage/default/40.rv_timer_random.3666578505 | Feb 07 12:36:32 PM PST 24 | Feb 07 12:45:24 PM PST 24 | 670754548035 ps | ||
| T352 | /workspace/coverage/default/188.rv_timer_random.90003891 | Feb 07 12:37:10 PM PST 24 | Feb 07 12:42:30 PM PST 24 | 281502563789 ps | ||
| T235 | /workspace/coverage/default/126.rv_timer_random.1074819162 | Feb 07 12:36:39 PM PST 24 | Feb 07 12:58:59 PM PST 24 | 830831643804 ps | ||
| T595 | /workspace/coverage/default/18.rv_timer_stress_all.409873065 | Feb 07 12:36:05 PM PST 24 | Feb 07 12:36:07 PM PST 24 | 20547973 ps | ||
| T256 | /workspace/coverage/default/47.rv_timer_random.616900796 | Feb 07 12:36:14 PM PST 24 | Feb 07 12:36:22 PM PST 24 | 14676276967 ps | ||
| T314 | /workspace/coverage/default/170.rv_timer_random.3755824312 | Feb 07 12:36:55 PM PST 24 | Feb 07 12:51:08 PM PST 24 | 73291190800 ps | ||
| T596 | /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.25163844 | Feb 07 12:37:34 PM PST 24 | Feb 07 12:47:09 PM PST 24 | 82467343726 ps | ||
| T597 | /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3975256460 | Feb 07 12:36:04 PM PST 24 | Feb 07 12:36:43 PM PST 24 | 20254670363 ps | ||
| T370 | /workspace/coverage/default/38.rv_timer_stress_all.1414057135 | Feb 07 12:36:37 PM PST 24 | Feb 07 12:41:23 PM PST 24 | 458639368599 ps | ||
| T369 | /workspace/coverage/default/29.rv_timer_stress_all.1323611005 | Feb 07 12:36:39 PM PST 24 | Feb 07 12:41:08 PM PST 24 | 153329120352 ps | ||
| T266 | /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.270395333 | Feb 07 12:36:04 PM PST 24 | Feb 07 12:47:41 PM PST 24 | 679556276799 ps | ||
| T598 | /workspace/coverage/default/26.rv_timer_random.3482615514 | Feb 07 12:36:24 PM PST 24 | Feb 07 12:38:33 PM PST 24 | 145752311314 ps | ||
| T330 | /workspace/coverage/default/44.rv_timer_random.727399713 | Feb 07 12:36:45 PM PST 24 | Feb 07 12:38:12 PM PST 24 | 104390833850 ps | ||
| T599 | /workspace/coverage/default/59.rv_timer_random.1656346300 | Feb 07 12:36:31 PM PST 24 | Feb 07 12:40:15 PM PST 24 | 298130191259 ps | ||
| T171 | /workspace/coverage/default/191.rv_timer_random.38751302 | Feb 07 12:37:09 PM PST 24 | Feb 07 12:38:54 PM PST 24 | 179411162624 ps | ||
| T600 | /workspace/coverage/default/8.rv_timer_disabled.2138657149 | Feb 07 12:36:32 PM PST 24 | Feb 07 12:37:22 PM PST 24 | 35833843839 ps | ||
| T601 | /workspace/coverage/default/88.rv_timer_random.1897960593 | Feb 07 12:36:44 PM PST 24 | Feb 07 12:38:36 PM PST 24 | 49017939439 ps | ||
| T20 | /workspace/coverage/default/1.rv_timer_sec_cm.2980466459 | Feb 07 12:36:05 PM PST 24 | Feb 07 12:36:07 PM PST 24 | 233331594 ps | ||
| T602 | /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.312497860 | Feb 07 12:36:44 PM PST 24 | Feb 07 12:41:10 PM PST 24 | 32652071404 ps | ||
| T21 | /workspace/coverage/default/4.rv_timer_sec_cm.3220791471 | Feb 07 12:36:02 PM PST 24 | Feb 07 12:36:04 PM PST 24 | 229359279 ps | ||
| T308 | /workspace/coverage/default/43.rv_timer_random.653332227 | Feb 07 12:37:44 PM PST 24 | Feb 07 12:39:20 PM PST 24 | 185830018756 ps | ||
| T603 | /workspace/coverage/default/70.rv_timer_random.13262593 | Feb 07 12:36:42 PM PST 24 | Feb 07 12:38:16 PM PST 24 | 114987622572 ps | ||
| T207 | /workspace/coverage/default/25.rv_timer_stress_all.524463140 | Feb 07 12:36:42 PM PST 24 | Feb 07 12:42:51 PM PST 24 | 759387622880 ps | ||
| T604 | /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.134917541 | Feb 07 12:36:41 PM PST 24 | Feb 07 12:47:55 PM PST 24 | 737590574660 ps | ||
| T335 | /workspace/coverage/default/35.rv_timer_random_reset.3598014618 | Feb 07 12:37:44 PM PST 24 | Feb 07 12:42:54 PM PST 24 | 222119810749 ps | ||
| T605 | /workspace/coverage/default/18.rv_timer_random_reset.2773339867 | Feb 07 12:36:08 PM PST 24 | Feb 07 12:37:37 PM PST 24 | 52404414081 ps | ||
| T606 | /workspace/coverage/default/54.rv_timer_random.688571754 | Feb 07 12:36:41 PM PST 24 | Feb 07 12:37:09 PM PST 24 | 15853320553 ps | ||
| T100 | /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.2838083016 | Feb 07 12:36:05 PM PST 24 | Feb 07 12:56:58 PM PST 24 | 408288803489 ps | ||
| T607 | /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.3845452962 | Feb 07 12:36:37 PM PST 24 | Feb 07 12:56:24 PM PST 24 | 381487495534 ps | ||
| T608 | /workspace/coverage/default/2.rv_timer_stress_all.2146367678 | Feb 07 12:36:02 PM PST 24 | Feb 07 12:51:15 PM PST 24 | 329968793456 ps | ||
| T609 | /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1726352489 | Feb 07 12:36:52 PM PST 24 | Feb 07 12:40:43 PM PST 24 | 132345137983 ps | ||
| T610 | /workspace/coverage/default/16.rv_timer_random.3125267033 | Feb 07 12:36:13 PM PST 24 | Feb 07 12:38:06 PM PST 24 | 62672544106 ps | ||
| T611 | /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.984737012 | Feb 07 12:35:52 PM PST 24 | Feb 07 12:47:10 PM PST 24 | 1251323294084 ps | ||
| T289 | /workspace/coverage/default/43.rv_timer_random_reset.1972879849 | Feb 07 12:36:30 PM PST 24 | Feb 07 12:38:33 PM PST 24 | 66187280565 ps | ||
| T365 | /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2154176554 | Feb 07 12:36:49 PM PST 24 | Feb 07 12:43:21 PM PST 24 | 1429662370011 ps | ||
| T612 | /workspace/coverage/default/159.rv_timer_random.1351702897 | Feb 07 12:36:50 PM PST 24 | Feb 07 01:05:21 PM PST 24 | 798106605685 ps | ||
| T269 | /workspace/coverage/default/4.rv_timer_random.2109474204 | Feb 07 12:36:06 PM PST 24 | Feb 07 12:56:45 PM PST 24 | 526359099163 ps | ||
| T613 | /workspace/coverage/default/123.rv_timer_random.1999787935 | Feb 07 12:36:53 PM PST 24 | Feb 07 12:44:42 PM PST 24 | 1195709747463 ps | ||
| T614 | /workspace/coverage/default/13.rv_timer_disabled.1971509333 | Feb 07 12:36:25 PM PST 24 | Feb 07 12:37:23 PM PST 24 | 36774331843 ps | ||
| T615 | /workspace/coverage/default/23.rv_timer_disabled.1198570510 | Feb 07 12:36:11 PM PST 24 | Feb 07 12:37:09 PM PST 24 | 319598178698 ps | ||
| T375 | /workspace/coverage/default/38.rv_timer_random.4079987228 | Feb 07 12:36:46 PM PST 24 | Feb 07 12:44:22 PM PST 24 | 530892408120 ps | ||
| T174 | /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1382825221 | Feb 07 12:36:30 PM PST 24 | Feb 07 12:40:26 PM PST 24 | 458569505451 ps | ||
| T212 | /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.736374769 | Feb 07 12:36:24 PM PST 24 | Feb 07 12:44:14 PM PST 24 | 257310974783 ps | ||
| T616 | /workspace/coverage/default/160.rv_timer_random.775594120 | Feb 07 12:36:52 PM PST 24 | Feb 07 12:42:58 PM PST 24 | 85339152630 ps | ||
| T617 | /workspace/coverage/default/27.rv_timer_disabled.673931461 | Feb 07 12:36:49 PM PST 24 | Feb 07 12:39:28 PM PST 24 | 105187405898 ps | ||
| T618 | /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1299241322 | Feb 07 12:36:42 PM PST 24 | Feb 07 12:56:00 PM PST 24 | 1942948594819 ps | ||
| T619 | /workspace/coverage/default/39.rv_timer_random.4011156288 | Feb 07 12:36:48 PM PST 24 | Feb 07 12:46:54 PM PST 24 | 32760656948 ps | ||
| T163 | /workspace/coverage/default/119.rv_timer_random.4177747890 | Feb 07 12:36:44 PM PST 24 | Feb 07 12:39:29 PM PST 24 | 98578425338 ps | ||
| T150 | /workspace/coverage/default/76.rv_timer_random.2008203094 | Feb 07 12:36:45 PM PST 24 | Feb 07 12:46:03 PM PST 24 | 272906763201 ps | ||
| T22 | /workspace/coverage/default/0.rv_timer_sec_cm.2528135892 | Feb 07 12:35:51 PM PST 24 | Feb 07 12:35:54 PM PST 24 | 39834857 ps | ||
| T223 | /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.818309736 | Feb 07 12:36:07 PM PST 24 | Feb 07 12:39:19 PM PST 24 | 107865950413 ps |
| Test location | /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.4048077748 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 1079566752972 ps |
| CPU time | 756.4 seconds |
| Started | Feb 07 12:36:11 PM PST 24 |
| Finished | Feb 07 12:48:50 PM PST 24 |
| Peak memory | 206420 kb |
| Host | smart-e2294ad6-0bb0-4f38-a9c0-7f617a4d9cda |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048077748 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.4048077748 |
| Directory | /workspace/8.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.rv_timer_stress_all.602719639 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 771119528288 ps |
| CPU time | 6652.95 seconds |
| Started | Feb 07 12:36:29 PM PST 24 |
| Finished | Feb 07 02:27:24 PM PST 24 |
| Peak memory | 190576 kb |
| Host | smart-4cf3256b-d3f7-4315-9042-de552f0a210d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602719639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.602719639 |
| Directory | /workspace/6.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/45.rv_timer_stress_all.242400287 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1930254447294 ps |
| CPU time | 2986.82 seconds |
| Started | Feb 07 12:36:30 PM PST 24 |
| Finished | Feb 07 01:26:19 PM PST 24 |
| Peak memory | 190528 kb |
| Host | smart-a2f52c1a-0754-4c4d-9578-3ddf1e96dec4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242400287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all. 242400287 |
| Directory | /workspace/45.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/11.rv_timer_stress_all.3886612971 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 567404276403 ps |
| CPU time | 1072.62 seconds |
| Started | Feb 07 12:36:18 PM PST 24 |
| Finished | Feb 07 12:54:12 PM PST 24 |
| Peak memory | 194988 kb |
| Host | smart-21816d11-ba36-40bc-b9b6-a4b458fae625 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886612971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all .3886612971 |
| Directory | /workspace/11.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/22.rv_timer_stress_all.2667684781 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 815952444951 ps |
| CPU time | 2826.06 seconds |
| Started | Feb 07 12:36:23 PM PST 24 |
| Finished | Feb 07 01:23:30 PM PST 24 |
| Peak memory | 190512 kb |
| Host | smart-82dd7d74-741c-46bc-8ab0-16bdae1448ec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667684781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all .2667684781 |
| Directory | /workspace/22.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1186249762 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 64182156 ps |
| CPU time | 0.64 seconds |
| Started | Feb 07 01:06:04 PM PST 24 |
| Finished | Feb 07 01:06:05 PM PST 24 |
| Peak memory | 191652 kb |
| Host | smart-4e0625e6-73d2-487b-ae8f-a8611129998a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186249762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti mer_same_csr_outstanding.1186249762 |
| Directory | /workspace/3.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2099579487 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 624730445 ps |
| CPU time | 1.09 seconds |
| Started | Feb 07 01:06:51 PM PST 24 |
| Finished | Feb 07 01:06:56 PM PST 24 |
| Peak memory | 194556 kb |
| Host | smart-69fac2f5-23c8-49ca-8cf2-af03ded62894 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099579487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i ntg_err.2099579487 |
| Directory | /workspace/15.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/27.rv_timer_stress_all.3755026278 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 479477634029 ps |
| CPU time | 1793.03 seconds |
| Started | Feb 07 12:36:49 PM PST 24 |
| Finished | Feb 07 01:06:43 PM PST 24 |
| Peak memory | 190532 kb |
| Host | smart-edf83a84-fe01-4003-8118-2bc672010ec6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755026278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all .3755026278 |
| Directory | /workspace/27.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/31.rv_timer_stress_all.375231568 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 575020244010 ps |
| CPU time | 1138.43 seconds |
| Started | Feb 07 12:36:29 PM PST 24 |
| Finished | Feb 07 12:55:29 PM PST 24 |
| Peak memory | 190428 kb |
| Host | smart-d91d2f40-dcb4-4cd5-a9f6-df097d2deb42 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375231568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all. 375231568 |
| Directory | /workspace/31.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/107.rv_timer_random.3438596523 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 773703573858 ps |
| CPU time | 751.45 seconds |
| Started | Feb 07 12:36:50 PM PST 24 |
| Finished | Feb 07 12:49:22 PM PST 24 |
| Peak memory | 190496 kb |
| Host | smart-35706565-a58c-4968-9b26-ac79b6c47813 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438596523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3438596523 |
| Directory | /workspace/107.rv_timer_random/latest |
| Test location | /workspace/coverage/default/21.rv_timer_stress_all.4194562993 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 3103919093751 ps |
| CPU time | 1653.5 seconds |
| Started | Feb 07 12:36:41 PM PST 24 |
| Finished | Feb 07 01:04:16 PM PST 24 |
| Peak memory | 195196 kb |
| Host | smart-6c2b99c8-564b-4bf7-bff7-3af4c7552304 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194562993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all .4194562993 |
| Directory | /workspace/21.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2695786055 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 20880198 ps |
| CPU time | 0.61 seconds |
| Started | Feb 07 01:06:10 PM PST 24 |
| Finished | Feb 07 01:06:11 PM PST 24 |
| Peak memory | 191568 kb |
| Host | smart-ef31a939-9332-4068-84dd-3d2dff5b23d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695786055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r eset.2695786055 |
| Directory | /workspace/3.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/7.rv_timer_stress_all.59058095 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 642038336698 ps |
| CPU time | 1370.79 seconds |
| Started | Feb 07 12:36:05 PM PST 24 |
| Finished | Feb 07 12:58:57 PM PST 24 |
| Peak memory | 190600 kb |
| Host | smart-17dad8de-6bfd-4f83-a40c-30817b2a0da1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59058095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_ all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.59058095 |
| Directory | /workspace/7.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/0.rv_timer_sec_cm.2528135892 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 39834857 ps |
| CPU time | 0.78 seconds |
| Started | Feb 07 12:35:51 PM PST 24 |
| Finished | Feb 07 12:35:54 PM PST 24 |
| Peak memory | 212596 kb |
| Host | smart-426366a4-f415-43cf-aa07-6a16eebca3c4 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528135892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2528135892 |
| Directory | /workspace/0.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/12.rv_timer_stress_all.2197117364 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 1866808427423 ps |
| CPU time | 1960.67 seconds |
| Started | Feb 07 12:36:12 PM PST 24 |
| Finished | Feb 07 01:08:55 PM PST 24 |
| Peak memory | 190520 kb |
| Host | smart-7120f9aa-4cd6-4ea7-9f7a-22de6e4ef4a1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197117364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all .2197117364 |
| Directory | /workspace/12.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/43.rv_timer_stress_all.1601125054 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 3157977240723 ps |
| CPU time | 1953.49 seconds |
| Started | Feb 07 12:36:35 PM PST 24 |
| Finished | Feb 07 01:09:10 PM PST 24 |
| Peak memory | 194684 kb |
| Host | smart-76ca0d7a-af3f-42e1-8d2e-f6933ae18513 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601125054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all .1601125054 |
| Directory | /workspace/43.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/47.rv_timer_stress_all.1214849691 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1407475218272 ps |
| CPU time | 4334.03 seconds |
| Started | Feb 07 12:36:31 PM PST 24 |
| Finished | Feb 07 01:48:47 PM PST 24 |
| Peak memory | 190688 kb |
| Host | smart-8518d787-8526-4222-ab7d-477ea9f404e2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214849691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all .1214849691 |
| Directory | /workspace/47.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/15.rv_timer_random.3543664537 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 263295347476 ps |
| CPU time | 501.35 seconds |
| Started | Feb 07 12:36:13 PM PST 24 |
| Finished | Feb 07 12:44:38 PM PST 24 |
| Peak memory | 193704 kb |
| Host | smart-99805bea-364b-482e-87f7-5df0709173ba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543664537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3543664537 |
| Directory | /workspace/15.rv_timer_random/latest |
| Test location | /workspace/coverage/default/0.rv_timer_random.1590204614 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 874407506055 ps |
| CPU time | 658.03 seconds |
| Started | Feb 07 12:35:55 PM PST 24 |
| Finished | Feb 07 12:46:56 PM PST 24 |
| Peak memory | 190656 kb |
| Host | smart-fe13c030-5d4c-41e6-87c8-7c0ee9a04e09 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590204614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1590204614 |
| Directory | /workspace/0.rv_timer_random/latest |
| Test location | /workspace/coverage/default/1.rv_timer_stress_all.3738910756 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 281607455137 ps |
| CPU time | 921.91 seconds |
| Started | Feb 07 12:36:16 PM PST 24 |
| Finished | Feb 07 12:51:40 PM PST 24 |
| Peak memory | 194600 kb |
| Host | smart-065ed2aa-4ab7-49c0-8917-a90e9ea967e5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738910756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all. 3738910756 |
| Directory | /workspace/1.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/46.rv_timer_random.1863455662 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 125507861779 ps |
| CPU time | 464.61 seconds |
| Started | Feb 07 12:36:30 PM PST 24 |
| Finished | Feb 07 12:44:16 PM PST 24 |
| Peak memory | 192716 kb |
| Host | smart-02e11ffd-5513-4391-a743-bba26ba32d34 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863455662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1863455662 |
| Directory | /workspace/46.rv_timer_random/latest |
| Test location | /workspace/coverage/default/15.rv_timer_stress_all.1695684532 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 1665267705774 ps |
| CPU time | 1137.68 seconds |
| Started | Feb 07 12:36:34 PM PST 24 |
| Finished | Feb 07 12:55:33 PM PST 24 |
| Peak memory | 190504 kb |
| Host | smart-f577a727-3c30-4cde-a031-f81fdbd6819c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695684532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all .1695684532 |
| Directory | /workspace/15.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/2.rv_timer_stress_all.2146367678 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 329968793456 ps |
| CPU time | 911 seconds |
| Started | Feb 07 12:36:02 PM PST 24 |
| Finished | Feb 07 12:51:15 PM PST 24 |
| Peak memory | 190524 kb |
| Host | smart-a9e9b5da-b4f5-49d9-b22e-15b0b80761ac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146367678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all. 2146367678 |
| Directory | /workspace/2.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/126.rv_timer_random.1074819162 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 830831643804 ps |
| CPU time | 1338.38 seconds |
| Started | Feb 07 12:36:39 PM PST 24 |
| Finished | Feb 07 12:58:59 PM PST 24 |
| Peak memory | 190408 kb |
| Host | smart-4194cf47-56b4-461e-8774-07a310ae7d59 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074819162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1074819162 |
| Directory | /workspace/126.rv_timer_random/latest |
| Test location | /workspace/coverage/default/81.rv_timer_random.3113040270 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 687640525122 ps |
| CPU time | 1713.78 seconds |
| Started | Feb 07 12:36:33 PM PST 24 |
| Finished | Feb 07 01:05:08 PM PST 24 |
| Peak memory | 190612 kb |
| Host | smart-e77814df-7f5a-4060-b737-dd3b0c4483c5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113040270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.3113040270 |
| Directory | /workspace/81.rv_timer_random/latest |
| Test location | /workspace/coverage/default/29.rv_timer_stress_all.1323611005 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 153329120352 ps |
| CPU time | 267.42 seconds |
| Started | Feb 07 12:36:39 PM PST 24 |
| Finished | Feb 07 12:41:08 PM PST 24 |
| Peak memory | 190576 kb |
| Host | smart-a3a7c79f-2a81-4d72-be2d-7fe3a96fa8d9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323611005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all .1323611005 |
| Directory | /workspace/29.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/36.rv_timer_stress_all.1803590132 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 407879426410 ps |
| CPU time | 725.87 seconds |
| Started | Feb 07 12:36:37 PM PST 24 |
| Finished | Feb 07 12:48:44 PM PST 24 |
| Peak memory | 194844 kb |
| Host | smart-305ab4c3-fe3c-43ad-9653-b2189e5c7f1f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803590132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all .1803590132 |
| Directory | /workspace/36.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/42.rv_timer_stress_all.1874877015 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 722630288077 ps |
| CPU time | 1602.92 seconds |
| Started | Feb 07 12:36:39 PM PST 24 |
| Finished | Feb 07 01:03:22 PM PST 24 |
| Peak memory | 190532 kb |
| Host | smart-bda63883-2d5f-4f17-a2d4-9530f75c2e6f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874877015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all .1874877015 |
| Directory | /workspace/42.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/44.rv_timer_stress_all.1752897556 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 908796762806 ps |
| CPU time | 1190.87 seconds |
| Started | Feb 07 12:36:33 PM PST 24 |
| Finished | Feb 07 12:56:25 PM PST 24 |
| Peak memory | 190568 kb |
| Host | smart-6e8d0e39-034e-42b0-a5ed-765315be475a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752897556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all .1752897556 |
| Directory | /workspace/44.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/63.rv_timer_random.894849527 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 142882552641 ps |
| CPU time | 646.62 seconds |
| Started | Feb 07 12:36:45 PM PST 24 |
| Finished | Feb 07 12:47:32 PM PST 24 |
| Peak memory | 190592 kb |
| Host | smart-e74f2fbd-9ecd-4b20-8b76-d84d8ad469fb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894849527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.894849527 |
| Directory | /workspace/63.rv_timer_random/latest |
| Test location | /workspace/coverage/default/109.rv_timer_random.1081961441 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 692628546354 ps |
| CPU time | 360.98 seconds |
| Started | Feb 07 12:36:45 PM PST 24 |
| Finished | Feb 07 12:42:47 PM PST 24 |
| Peak memory | 192744 kb |
| Host | smart-269d11ad-d8d6-4bb9-85b9-41237cb52b98 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081961441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1081961441 |
| Directory | /workspace/109.rv_timer_random/latest |
| Test location | /workspace/coverage/default/5.rv_timer_stress_all.3484662339 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 2547734488453 ps |
| CPU time | 3854.3 seconds |
| Started | Feb 07 12:36:06 PM PST 24 |
| Finished | Feb 07 01:40:22 PM PST 24 |
| Peak memory | 190492 kb |
| Host | smart-f622ef57-aa37-41df-86f7-9c38fc2851db |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484662339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all. 3484662339 |
| Directory | /workspace/5.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/115.rv_timer_random.2760859026 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1676648229798 ps |
| CPU time | 399.19 seconds |
| Started | Feb 07 12:36:39 PM PST 24 |
| Finished | Feb 07 12:43:19 PM PST 24 |
| Peak memory | 190560 kb |
| Host | smart-0fa0772c-5421-4f9d-8b45-b29447e6514c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760859026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2760859026 |
| Directory | /workspace/115.rv_timer_random/latest |
| Test location | /workspace/coverage/default/12.rv_timer_random.2139412664 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 1993899205720 ps |
| CPU time | 1358.05 seconds |
| Started | Feb 07 12:36:38 PM PST 24 |
| Finished | Feb 07 12:59:17 PM PST 24 |
| Peak memory | 190592 kb |
| Host | smart-35b9a6b4-10ce-4bf6-807f-8566d105d966 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139412664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2139412664 |
| Directory | /workspace/12.rv_timer_random/latest |
| Test location | /workspace/coverage/default/141.rv_timer_random.776470825 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 111285326709 ps |
| CPU time | 364.66 seconds |
| Started | Feb 07 12:36:55 PM PST 24 |
| Finished | Feb 07 12:43:01 PM PST 24 |
| Peak memory | 193972 kb |
| Host | smart-de549f32-4b77-43b5-be43-0cdae672414b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776470825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.776470825 |
| Directory | /workspace/141.rv_timer_random/latest |
| Test location | /workspace/coverage/default/186.rv_timer_random.40346220 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 152062977264 ps |
| CPU time | 843.34 seconds |
| Started | Feb 07 12:37:07 PM PST 24 |
| Finished | Feb 07 12:51:12 PM PST 24 |
| Peak memory | 190496 kb |
| Host | smart-6d8df522-63a4-4137-b5cb-2838ca9d9d7f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40346220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.40346220 |
| Directory | /workspace/186.rv_timer_random/latest |
| Test location | /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3901318464 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 392600867485 ps |
| CPU time | 721.48 seconds |
| Started | Feb 07 12:36:34 PM PST 24 |
| Finished | Feb 07 12:48:37 PM PST 24 |
| Peak memory | 182152 kb |
| Host | smart-7a8e3900-2faf-4db2-a016-bb4f0598b15b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901318464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.3901318464 |
| Directory | /workspace/40.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/40.rv_timer_random.3666578505 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 670754548035 ps |
| CPU time | 531.04 seconds |
| Started | Feb 07 12:36:32 PM PST 24 |
| Finished | Feb 07 12:45:24 PM PST 24 |
| Peak memory | 190472 kb |
| Host | smart-32e28408-05b6-41b8-b84e-3b508dd1e5a0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666578505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3666578505 |
| Directory | /workspace/40.rv_timer_random/latest |
| Test location | /workspace/coverage/default/48.rv_timer_random.106927237 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 774468176672 ps |
| CPU time | 343.16 seconds |
| Started | Feb 07 12:36:33 PM PST 24 |
| Finished | Feb 07 12:42:18 PM PST 24 |
| Peak memory | 192692 kb |
| Host | smart-e5817fac-67a2-4e02-bc49-39424ddc8cae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106927237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.106927237 |
| Directory | /workspace/48.rv_timer_random/latest |
| Test location | /workspace/coverage/default/6.rv_timer_random.2471095716 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 184837721629 ps |
| CPU time | 162.34 seconds |
| Started | Feb 07 12:36:01 PM PST 24 |
| Finished | Feb 07 12:38:45 PM PST 24 |
| Peak memory | 190516 kb |
| Host | smart-9832853a-6003-41b9-99ba-27a8ba776713 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471095716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2471095716 |
| Directory | /workspace/6.rv_timer_random/latest |
| Test location | /workspace/coverage/default/87.rv_timer_random.49267124 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 82723908844 ps |
| CPU time | 908.32 seconds |
| Started | Feb 07 12:36:46 PM PST 24 |
| Finished | Feb 07 12:51:56 PM PST 24 |
| Peak memory | 190572 kb |
| Host | smart-9001e8bc-0866-4125-ba4c-d33b4aede5c0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49267124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.49267124 |
| Directory | /workspace/87.rv_timer_random/latest |
| Test location | /workspace/coverage/default/145.rv_timer_random.3404684001 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 200261399198 ps |
| CPU time | 189.01 seconds |
| Started | Feb 07 12:36:57 PM PST 24 |
| Finished | Feb 07 12:40:07 PM PST 24 |
| Peak memory | 190596 kb |
| Host | smart-947fcd3c-b630-4714-b618-c59c0d99eea9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404684001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3404684001 |
| Directory | /workspace/145.rv_timer_random/latest |
| Test location | /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.270395333 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 679556276799 ps |
| CPU time | 695.32 seconds |
| Started | Feb 07 12:36:04 PM PST 24 |
| Finished | Feb 07 12:47:41 PM PST 24 |
| Peak memory | 182308 kb |
| Host | smart-831d745c-86af-4c41-8986-64bc39517e86 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270395333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .rv_timer_cfg_update_on_fly.270395333 |
| Directory | /workspace/3.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/46.rv_timer_stress_all.2700073890 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 351804090771 ps |
| CPU time | 654.71 seconds |
| Started | Feb 07 12:36:42 PM PST 24 |
| Finished | Feb 07 12:47:37 PM PST 24 |
| Peak memory | 190424 kb |
| Host | smart-297d7973-6315-4f8d-81b2-76ebf8ceacb1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700073890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all .2700073890 |
| Directory | /workspace/46.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/10.rv_timer_random_reset.3948679267 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 65037975028 ps |
| CPU time | 244.27 seconds |
| Started | Feb 07 12:36:18 PM PST 24 |
| Finished | Feb 07 12:40:23 PM PST 24 |
| Peak memory | 190568 kb |
| Host | smart-de3f4417-b233-424f-9b83-cc89ab126cf4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3948679267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3948679267 |
| Directory | /workspace/10.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2784423716 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 2657319214006 ps |
| CPU time | 1547.38 seconds |
| Started | Feb 07 12:36:31 PM PST 24 |
| Finished | Feb 07 01:02:19 PM PST 24 |
| Peak memory | 182304 kb |
| Host | smart-8be3281e-4084-4853-894b-be385cad00d4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784423716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.2784423716 |
| Directory | /workspace/13.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.2358594399 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 235251865704 ps |
| CPU time | 429.9 seconds |
| Started | Feb 07 12:36:11 PM PST 24 |
| Finished | Feb 07 12:43:24 PM PST 24 |
| Peak memory | 182320 kb |
| Host | smart-91127b99-681b-47d0-8650-3d69c92f77bf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358594399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.2358594399 |
| Directory | /workspace/17.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/17.rv_timer_random.2274987288 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 252579197468 ps |
| CPU time | 289.93 seconds |
| Started | Feb 07 12:36:05 PM PST 24 |
| Finished | Feb 07 12:40:56 PM PST 24 |
| Peak memory | 190612 kb |
| Host | smart-bbd490d6-f466-4e56-855c-ce396bfdf75b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274987288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2274987288 |
| Directory | /workspace/17.rv_timer_random/latest |
| Test location | /workspace/coverage/default/19.rv_timer_stress_all.8369712 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 2538874636870 ps |
| CPU time | 1258.41 seconds |
| Started | Feb 07 12:36:27 PM PST 24 |
| Finished | Feb 07 12:57:27 PM PST 24 |
| Peak memory | 190604 kb |
| Host | smart-3970b480-89a5-45f0-be49-56c8bb7c98e5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8369712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_a ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.8369712 |
| Directory | /workspace/19.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/24.rv_timer_random.4003274039 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 140532053012 ps |
| CPU time | 281.49 seconds |
| Started | Feb 07 12:36:24 PM PST 24 |
| Finished | Feb 07 12:41:07 PM PST 24 |
| Peak memory | 190568 kb |
| Host | smart-9d22e907-8fa3-4910-8188-66bff83548a7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003274039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.4003274039 |
| Directory | /workspace/24.rv_timer_random/latest |
| Test location | /workspace/coverage/default/25.rv_timer_stress_all.524463140 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 759387622880 ps |
| CPU time | 367.7 seconds |
| Started | Feb 07 12:36:42 PM PST 24 |
| Finished | Feb 07 12:42:51 PM PST 24 |
| Peak memory | 190528 kb |
| Host | smart-2a3d0d2e-d189-4621-8f9f-ac0d2d96bf6d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524463140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all. 524463140 |
| Directory | /workspace/25.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3915602094 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 82584812583 ps |
| CPU time | 144.21 seconds |
| Started | Feb 07 12:36:47 PM PST 24 |
| Finished | Feb 07 12:39:12 PM PST 24 |
| Peak memory | 182324 kb |
| Host | smart-9ed7d119-e690-4ce8-8949-ccdaacf29654 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915602094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_cfg_update_on_fly.3915602094 |
| Directory | /workspace/28.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1538414037 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 762256103328 ps |
| CPU time | 1449.88 seconds |
| Started | Feb 07 12:36:58 PM PST 24 |
| Finished | Feb 07 01:01:09 PM PST 24 |
| Peak memory | 182280 kb |
| Host | smart-1efe734a-9113-4e0e-8c5b-cbde0ac9807c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538414037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_cfg_update_on_fly.1538414037 |
| Directory | /workspace/45.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/57.rv_timer_random.513127752 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 160856652133 ps |
| CPU time | 482.66 seconds |
| Started | Feb 07 12:37:34 PM PST 24 |
| Finished | Feb 07 12:45:38 PM PST 24 |
| Peak memory | 189376 kb |
| Host | smart-90747906-9257-4838-bb74-230d01e69f6b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513127752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.513127752 |
| Directory | /workspace/57.rv_timer_random/latest |
| Test location | /workspace/coverage/default/92.rv_timer_random.3524024331 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 110629919749 ps |
| CPU time | 215.89 seconds |
| Started | Feb 07 12:36:42 PM PST 24 |
| Finished | Feb 07 12:40:19 PM PST 24 |
| Peak memory | 190588 kb |
| Host | smart-27073542-04ee-49cd-a78c-56c52b86d79d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524024331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3524024331 |
| Directory | /workspace/92.rv_timer_random/latest |
| Test location | /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1227711915 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 329518462421 ps |
| CPU time | 597.03 seconds |
| Started | Feb 07 12:35:58 PM PST 24 |
| Finished | Feb 07 12:45:59 PM PST 24 |
| Peak memory | 182308 kb |
| Host | smart-7564e822-33d2-457c-841d-c1bfdb8c06da |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227711915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_cfg_update_on_fly.1227711915 |
| Directory | /workspace/1.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/104.rv_timer_random.3506728941 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 364688924925 ps |
| CPU time | 200.84 seconds |
| Started | Feb 07 12:36:29 PM PST 24 |
| Finished | Feb 07 12:39:51 PM PST 24 |
| Peak memory | 190560 kb |
| Host | smart-d2709cfb-4aaf-491d-a101-4a9eff0cfb86 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506728941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3506728941 |
| Directory | /workspace/104.rv_timer_random/latest |
| Test location | /workspace/coverage/default/106.rv_timer_random.2558895534 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 480846479495 ps |
| CPU time | 833.94 seconds |
| Started | Feb 07 12:36:43 PM PST 24 |
| Finished | Feb 07 12:50:38 PM PST 24 |
| Peak memory | 190536 kb |
| Host | smart-d4d8a978-c71e-434e-9740-33fe07a0b647 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558895534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2558895534 |
| Directory | /workspace/106.rv_timer_random/latest |
| Test location | /workspace/coverage/default/116.rv_timer_random.2510770719 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 87094914687 ps |
| CPU time | 454.76 seconds |
| Started | Feb 07 12:36:46 PM PST 24 |
| Finished | Feb 07 12:44:22 PM PST 24 |
| Peak memory | 182372 kb |
| Host | smart-ca9c3046-b19e-4d65-ae1d-cf36a30e77d7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510770719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2510770719 |
| Directory | /workspace/116.rv_timer_random/latest |
| Test location | /workspace/coverage/default/118.rv_timer_random.2053339735 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 132713792128 ps |
| CPU time | 213.19 seconds |
| Started | Feb 07 12:36:49 PM PST 24 |
| Finished | Feb 07 12:40:23 PM PST 24 |
| Peak memory | 190560 kb |
| Host | smart-a8792e7a-ee91-43ba-a2fb-2e32e0310708 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053339735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2053339735 |
| Directory | /workspace/118.rv_timer_random/latest |
| Test location | /workspace/coverage/default/124.rv_timer_random.173867336 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 2686172057116 ps |
| CPU time | 736.37 seconds |
| Started | Feb 07 12:36:46 PM PST 24 |
| Finished | Feb 07 12:49:03 PM PST 24 |
| Peak memory | 190592 kb |
| Host | smart-ed59820d-298d-49a7-ab04-1142141cfdc4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173867336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.173867336 |
| Directory | /workspace/124.rv_timer_random/latest |
| Test location | /workspace/coverage/default/128.rv_timer_random.867587009 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 160606027488 ps |
| CPU time | 446.68 seconds |
| Started | Feb 07 12:37:02 PM PST 24 |
| Finished | Feb 07 12:44:30 PM PST 24 |
| Peak memory | 190592 kb |
| Host | smart-b6b91a45-f42b-4bbb-ab81-5029985793da |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867587009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.867587009 |
| Directory | /workspace/128.rv_timer_random/latest |
| Test location | /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.2006166703 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 253041752650 ps |
| CPU time | 1113.16 seconds |
| Started | Feb 07 12:36:29 PM PST 24 |
| Finished | Feb 07 12:55:03 PM PST 24 |
| Peak memory | 207912 kb |
| Host | smart-fd8a4f1b-4e32-49aa-8701-fedd471e1d2d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006166703 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.2006166703 |
| Directory | /workspace/14.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/168.rv_timer_random.3272144864 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 643239046721 ps |
| CPU time | 1231.07 seconds |
| Started | Feb 07 12:36:56 PM PST 24 |
| Finished | Feb 07 12:57:28 PM PST 24 |
| Peak memory | 190532 kb |
| Host | smart-67005385-77eb-4320-8815-8428862b32ec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272144864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3272144864 |
| Directory | /workspace/168.rv_timer_random/latest |
| Test location | /workspace/coverage/default/191.rv_timer_random.38751302 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 179411162624 ps |
| CPU time | 104.63 seconds |
| Started | Feb 07 12:37:09 PM PST 24 |
| Finished | Feb 07 12:38:54 PM PST 24 |
| Peak memory | 190444 kb |
| Host | smart-203eace9-d349-4dcf-b385-998fadaae92f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38751302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.38751302 |
| Directory | /workspace/191.rv_timer_random/latest |
| Test location | /workspace/coverage/default/194.rv_timer_random.3505645733 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 322336595965 ps |
| CPU time | 1911.92 seconds |
| Started | Feb 07 12:37:32 PM PST 24 |
| Finished | Feb 07 01:09:25 PM PST 24 |
| Peak memory | 190532 kb |
| Host | smart-540152f8-7999-43fe-8b49-6f39b3cbdc68 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505645733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3505645733 |
| Directory | /workspace/194.rv_timer_random/latest |
| Test location | /workspace/coverage/default/26.rv_timer_stress_all.4037723412 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 846260115917 ps |
| CPU time | 569.37 seconds |
| Started | Feb 07 12:36:39 PM PST 24 |
| Finished | Feb 07 12:46:09 PM PST 24 |
| Peak memory | 194556 kb |
| Host | smart-94b88e86-9c43-4d72-9887-33d454c0b5dd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037723412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all .4037723412 |
| Directory | /workspace/26.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/29.rv_timer_random_reset.3261818417 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 97333467546 ps |
| CPU time | 1369.52 seconds |
| Started | Feb 07 12:36:34 PM PST 24 |
| Finished | Feb 07 12:59:25 PM PST 24 |
| Peak memory | 190504 kb |
| Host | smart-74a030fa-5535-43f6-b184-ceba2009f77d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3261818417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3261818417 |
| Directory | /workspace/29.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/49.rv_timer_random.4193505301 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 467160464650 ps |
| CPU time | 741.54 seconds |
| Started | Feb 07 12:36:46 PM PST 24 |
| Finished | Feb 07 12:49:09 PM PST 24 |
| Peak memory | 190496 kb |
| Host | smart-078e66c3-9a76-40c1-927d-e5d342b92471 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193505301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.4193505301 |
| Directory | /workspace/49.rv_timer_random/latest |
| Test location | /workspace/coverage/default/60.rv_timer_random.3906964589 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 495004468034 ps |
| CPU time | 355.4 seconds |
| Started | Feb 07 12:37:35 PM PST 24 |
| Finished | Feb 07 12:43:32 PM PST 24 |
| Peak memory | 188424 kb |
| Host | smart-e53996a5-5a24-4f64-b236-edb704ee84ba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906964589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3906964589 |
| Directory | /workspace/60.rv_timer_random/latest |
| Test location | /workspace/coverage/default/61.rv_timer_random.3704620247 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 737514263243 ps |
| CPU time | 344.42 seconds |
| Started | Feb 07 12:36:35 PM PST 24 |
| Finished | Feb 07 12:42:21 PM PST 24 |
| Peak memory | 193052 kb |
| Host | smart-093f1d2d-6225-4e75-954d-dd7ddef378a0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704620247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3704620247 |
| Directory | /workspace/61.rv_timer_random/latest |
| Test location | /workspace/coverage/default/62.rv_timer_random.4076832170 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 44467036441 ps |
| CPU time | 40.51 seconds |
| Started | Feb 07 12:36:37 PM PST 24 |
| Finished | Feb 07 12:37:19 PM PST 24 |
| Peak memory | 190548 kb |
| Host | smart-1517663e-86bf-42df-81a6-768d798b635a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076832170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.4076832170 |
| Directory | /workspace/62.rv_timer_random/latest |
| Test location | /workspace/coverage/default/66.rv_timer_random.2752284416 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 918017861118 ps |
| CPU time | 610.98 seconds |
| Started | Feb 07 12:36:29 PM PST 24 |
| Finished | Feb 07 12:46:41 PM PST 24 |
| Peak memory | 193752 kb |
| Host | smart-eeae6d23-eeb9-45e0-a2a2-7114fbd808d1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752284416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2752284416 |
| Directory | /workspace/66.rv_timer_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3037649231 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 88887452 ps |
| CPU time | 1.15 seconds |
| Started | Feb 07 01:06:59 PM PST 24 |
| Finished | Feb 07 01:07:03 PM PST 24 |
| Peak memory | 194488 kb |
| Host | smart-7e953eea-3716-4af4-b0c8-eba5c65f16a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037649231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i ntg_err.3037649231 |
| Directory | /workspace/12.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/103.rv_timer_random.171670045 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 385044498367 ps |
| CPU time | 283.44 seconds |
| Started | Feb 07 12:37:02 PM PST 24 |
| Finished | Feb 07 12:41:46 PM PST 24 |
| Peak memory | 190588 kb |
| Host | smart-1793ffd4-60bc-436f-8b09-d7167b71f06b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171670045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.171670045 |
| Directory | /workspace/103.rv_timer_random/latest |
| Test location | /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2445886303 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 45122156910 ps |
| CPU time | 75.4 seconds |
| Started | Feb 07 12:36:15 PM PST 24 |
| Finished | Feb 07 12:37:33 PM PST 24 |
| Peak memory | 182292 kb |
| Host | smart-f531dfd4-0cee-45ff-abea-150ccf553b19 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445886303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.2445886303 |
| Directory | /workspace/11.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/11.rv_timer_random.2638131829 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 90079389693 ps |
| CPU time | 161.49 seconds |
| Started | Feb 07 12:36:14 PM PST 24 |
| Finished | Feb 07 12:38:58 PM PST 24 |
| Peak memory | 194084 kb |
| Host | smart-515f80ec-0585-45db-ac89-b94188e6fcba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638131829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2638131829 |
| Directory | /workspace/11.rv_timer_random/latest |
| Test location | /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.4103365769 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 374297568252 ps |
| CPU time | 765.7 seconds |
| Started | Feb 07 12:36:12 PM PST 24 |
| Finished | Feb 07 12:49:00 PM PST 24 |
| Peak memory | 207420 kb |
| Host | smart-292a33b7-c606-4777-9384-f1e5e1c2a427 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103365769 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.4103365769 |
| Directory | /workspace/12.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/136.rv_timer_random.3960399066 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 45157489047 ps |
| CPU time | 306.5 seconds |
| Started | Feb 07 12:36:51 PM PST 24 |
| Finished | Feb 07 12:41:59 PM PST 24 |
| Peak memory | 190532 kb |
| Host | smart-2fa8830a-0198-48a9-b6d9-6649000b9997 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960399066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3960399066 |
| Directory | /workspace/136.rv_timer_random/latest |
| Test location | /workspace/coverage/default/14.rv_timer_random_reset.2707352602 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 16128117784 ps |
| CPU time | 24.94 seconds |
| Started | Feb 07 12:36:37 PM PST 24 |
| Finished | Feb 07 12:37:03 PM PST 24 |
| Peak memory | 182176 kb |
| Host | smart-c496e18f-2155-4cf6-aa0f-bbdd3f14ff67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2707352602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2707352602 |
| Directory | /workspace/14.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/146.rv_timer_random.3030775378 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 557516088054 ps |
| CPU time | 899.53 seconds |
| Started | Feb 07 12:36:45 PM PST 24 |
| Finished | Feb 07 12:51:46 PM PST 24 |
| Peak memory | 191920 kb |
| Host | smart-d936d0ca-ffe5-4574-b867-636c9960f902 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030775378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3030775378 |
| Directory | /workspace/146.rv_timer_random/latest |
| Test location | /workspace/coverage/default/151.rv_timer_random.1761713956 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 623181975288 ps |
| CPU time | 564.29 seconds |
| Started | Feb 07 12:36:57 PM PST 24 |
| Finished | Feb 07 12:46:23 PM PST 24 |
| Peak memory | 190616 kb |
| Host | smart-2b5cffda-0b3b-4eb6-a115-aef757b005a8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761713956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1761713956 |
| Directory | /workspace/151.rv_timer_random/latest |
| Test location | /workspace/coverage/default/17.rv_timer_stress_all.4035702767 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 350902078218 ps |
| CPU time | 285.96 seconds |
| Started | Feb 07 12:36:04 PM PST 24 |
| Finished | Feb 07 12:40:51 PM PST 24 |
| Peak memory | 190524 kb |
| Host | smart-2913ae92-4615-4a31-8c82-b1f795202f78 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035702767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all .4035702767 |
| Directory | /workspace/17.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/180.rv_timer_random.2171102004 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 486451807351 ps |
| CPU time | 920.37 seconds |
| Started | Feb 07 12:37:02 PM PST 24 |
| Finished | Feb 07 12:52:24 PM PST 24 |
| Peak memory | 190620 kb |
| Host | smart-b0aad7ac-f848-42e0-9aea-f0cba02e39ef |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171102004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.2171102004 |
| Directory | /workspace/180.rv_timer_random/latest |
| Test location | /workspace/coverage/default/196.rv_timer_random.3229065823 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 142304382426 ps |
| CPU time | 297.34 seconds |
| Started | Feb 07 12:37:08 PM PST 24 |
| Finished | Feb 07 12:42:06 PM PST 24 |
| Peak memory | 190384 kb |
| Host | smart-18b3b358-e872-42cc-a848-414408e61db4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229065823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3229065823 |
| Directory | /workspace/196.rv_timer_random/latest |
| Test location | /workspace/coverage/default/199.rv_timer_random.2225575721 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 836836070356 ps |
| CPU time | 392.4 seconds |
| Started | Feb 07 12:37:02 PM PST 24 |
| Finished | Feb 07 12:43:36 PM PST 24 |
| Peak memory | 190572 kb |
| Host | smart-eb3d8d1c-adca-4520-8486-f3ef14b4f79e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225575721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2225575721 |
| Directory | /workspace/199.rv_timer_random/latest |
| Test location | /workspace/coverage/default/21.rv_timer_random.2497238987 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 69154042039 ps |
| CPU time | 1233.27 seconds |
| Started | Feb 07 12:36:38 PM PST 24 |
| Finished | Feb 07 12:57:13 PM PST 24 |
| Peak memory | 190472 kb |
| Host | smart-387b38d6-d51f-4bff-b168-2a47018c6079 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497238987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2497238987 |
| Directory | /workspace/21.rv_timer_random/latest |
| Test location | /workspace/coverage/default/22.rv_timer_random.1233408815 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 415340935709 ps |
| CPU time | 2005.6 seconds |
| Started | Feb 07 12:36:22 PM PST 24 |
| Finished | Feb 07 01:09:49 PM PST 24 |
| Peak memory | 194092 kb |
| Host | smart-d32ae222-2526-4941-a93a-0894b307199a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233408815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1233408815 |
| Directory | /workspace/22.rv_timer_random/latest |
| Test location | /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1008989549 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 2757680339003 ps |
| CPU time | 1038.39 seconds |
| Started | Feb 07 12:36:49 PM PST 24 |
| Finished | Feb 07 12:54:08 PM PST 24 |
| Peak memory | 182304 kb |
| Host | smart-07809b68-9d39-4fd1-8711-dd3447f524c8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008989549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.1008989549 |
| Directory | /workspace/23.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.2867585838 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 297750245652 ps |
| CPU time | 988.47 seconds |
| Started | Feb 07 12:36:49 PM PST 24 |
| Finished | Feb 07 12:53:18 PM PST 24 |
| Peak memory | 211776 kb |
| Host | smart-070dd36c-8d9f-490b-bd6a-8a755c342dbc |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867585838 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.2867585838 |
| Directory | /workspace/24.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/28.rv_timer_random_reset.2455677663 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 184154574655 ps |
| CPU time | 224.62 seconds |
| Started | Feb 07 12:36:47 PM PST 24 |
| Finished | Feb 07 12:40:32 PM PST 24 |
| Peak memory | 182320 kb |
| Host | smart-41330bd6-b233-4660-89aa-9e8da88b8e9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2455677663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2455677663 |
| Directory | /workspace/28.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/36.rv_timer_random_reset.1101971076 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 19868990764 ps |
| CPU time | 32.78 seconds |
| Started | Feb 07 12:36:46 PM PST 24 |
| Finished | Feb 07 12:37:20 PM PST 24 |
| Peak memory | 190580 kb |
| Host | smart-43bb7790-450e-49eb-9eb7-ba402626afe4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1101971076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.1101971076 |
| Directory | /workspace/36.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/39.rv_timer_stress_all.1932254052 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 279823649269 ps |
| CPU time | 379.65 seconds |
| Started | Feb 07 12:36:43 PM PST 24 |
| Finished | Feb 07 12:43:03 PM PST 24 |
| Peak memory | 190416 kb |
| Host | smart-194057fb-8e83-4725-b188-ab2ee71f9498 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932254052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all .1932254052 |
| Directory | /workspace/39.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/48.rv_timer_stress_all.2832245930 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1501567117396 ps |
| CPU time | 1018.39 seconds |
| Started | Feb 07 12:36:41 PM PST 24 |
| Finished | Feb 07 12:53:41 PM PST 24 |
| Peak memory | 190412 kb |
| Host | smart-ed3417b3-5c7c-4bab-a16c-fe24df33668e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832245930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all .2832245930 |
| Directory | /workspace/48.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/78.rv_timer_random.1230592291 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 78996231252 ps |
| CPU time | 129.72 seconds |
| Started | Feb 07 12:36:46 PM PST 24 |
| Finished | Feb 07 12:38:57 PM PST 24 |
| Peak memory | 190552 kb |
| Host | smart-76338146-18f9-4d90-87f5-f479e4ae279b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230592291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1230592291 |
| Directory | /workspace/78.rv_timer_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3049727532 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 231060086 ps |
| CPU time | 0.85 seconds |
| Started | Feb 07 01:05:54 PM PST 24 |
| Finished | Feb 07 01:05:56 PM PST 24 |
| Peak memory | 191840 kb |
| Host | smart-a30ef6b3-0ba3-43f4-8da9-82b6029dd6d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049727532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia sing.3049727532 |
| Directory | /workspace/0.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.766412349 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 845025281 ps |
| CPU time | 1.56 seconds |
| Started | Feb 07 01:05:53 PM PST 24 |
| Finished | Feb 07 01:05:55 PM PST 24 |
| Peak memory | 193032 kb |
| Host | smart-d8562b9e-00b5-4e5c-a832-6f21ed08d296 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766412349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b ash.766412349 |
| Directory | /workspace/0.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2950589383 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 78066272 ps |
| CPU time | 0.56 seconds |
| Started | Feb 07 01:05:48 PM PST 24 |
| Finished | Feb 07 01:05:49 PM PST 24 |
| Peak memory | 182320 kb |
| Host | smart-a978178e-51bd-4b50-8ad8-5e64c0ecd16b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950589383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r eset.2950589383 |
| Directory | /workspace/0.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2983669596 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 24586410 ps |
| CPU time | 0.64 seconds |
| Started | Feb 07 01:05:54 PM PST 24 |
| Finished | Feb 07 01:05:56 PM PST 24 |
| Peak memory | 192552 kb |
| Host | smart-8b2dbaac-1600-442f-a2e9-1208d6eae369 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983669596 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2983669596 |
| Directory | /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1681545594 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 12291827 ps |
| CPU time | 0.58 seconds |
| Started | Feb 07 01:05:53 PM PST 24 |
| Finished | Feb 07 01:05:54 PM PST 24 |
| Peak memory | 182372 kb |
| Host | smart-196fa4dc-b089-4b73-9c80-4a7f0a665b12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681545594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1681545594 |
| Directory | /workspace/0.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3288179471 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 13805919 ps |
| CPU time | 0.53 seconds |
| Started | Feb 07 01:05:53 PM PST 24 |
| Finished | Feb 07 01:05:54 PM PST 24 |
| Peak memory | 182240 kb |
| Host | smart-31eded57-cc29-4f90-9114-cbee312158f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288179471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3288179471 |
| Directory | /workspace/0.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1689618395 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 119038532 ps |
| CPU time | 0.69 seconds |
| Started | Feb 07 01:05:49 PM PST 24 |
| Finished | Feb 07 01:05:51 PM PST 24 |
| Peak memory | 191292 kb |
| Host | smart-4513b2a5-8db0-4b67-85a6-fa46aa41d9ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689618395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti mer_same_csr_outstanding.1689618395 |
| Directory | /workspace/0.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2785983046 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 190988455 ps |
| CPU time | 1.69 seconds |
| Started | Feb 07 01:05:54 PM PST 24 |
| Finished | Feb 07 01:05:57 PM PST 24 |
| Peak memory | 197172 kb |
| Host | smart-75d355a9-58be-4c35-b3c8-b5005c88c271 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785983046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2785983046 |
| Directory | /workspace/0.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.868788810 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 302012977 ps |
| CPU time | 1.28 seconds |
| Started | Feb 07 01:05:52 PM PST 24 |
| Finished | Feb 07 01:05:54 PM PST 24 |
| Peak memory | 182672 kb |
| Host | smart-c397f91c-9a02-44ba-9e61-70cd0a3f904e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868788810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_int g_err.868788810 |
| Directory | /workspace/0.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.889530151 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 36829598 ps |
| CPU time | 0.86 seconds |
| Started | Feb 07 01:05:55 PM PST 24 |
| Finished | Feb 07 01:05:56 PM PST 24 |
| Peak memory | 192032 kb |
| Host | smart-485599a7-913f-4a3f-a300-ca9e47257bc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889530151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias ing.889530151 |
| Directory | /workspace/1.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1442631301 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 105771315 ps |
| CPU time | 3.34 seconds |
| Started | Feb 07 01:05:55 PM PST 24 |
| Finished | Feb 07 01:05:59 PM PST 24 |
| Peak memory | 190736 kb |
| Host | smart-946a4584-b2bc-400c-832b-c293352c8ebf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442631301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_ bash.1442631301 |
| Directory | /workspace/1.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2739767507 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 51415665 ps |
| CPU time | 0.56 seconds |
| Started | Feb 07 01:05:53 PM PST 24 |
| Finished | Feb 07 01:05:54 PM PST 24 |
| Peak memory | 182388 kb |
| Host | smart-044c5220-759f-4917-bd79-8b072139b51a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739767507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r eset.2739767507 |
| Directory | /workspace/1.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1265423063 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 34417691 ps |
| CPU time | 0.85 seconds |
| Started | Feb 07 01:05:53 PM PST 24 |
| Finished | Feb 07 01:05:54 PM PST 24 |
| Peak memory | 195596 kb |
| Host | smart-1ac44536-835d-4f8f-a9a1-755de94bd894 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265423063 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.1265423063 |
| Directory | /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2391512715 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 22292570 ps |
| CPU time | 0.57 seconds |
| Started | Feb 07 01:05:50 PM PST 24 |
| Finished | Feb 07 01:05:51 PM PST 24 |
| Peak memory | 182352 kb |
| Host | smart-807690cd-8805-4cce-b9f9-34dae4da102f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391512715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2391512715 |
| Directory | /workspace/1.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.27563077 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 10482978 ps |
| CPU time | 0.52 seconds |
| Started | Feb 07 01:05:51 PM PST 24 |
| Finished | Feb 07 01:05:53 PM PST 24 |
| Peak memory | 181600 kb |
| Host | smart-e9d18360-439b-441e-a90b-608f7fa2d0fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27563077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.27563077 |
| Directory | /workspace/1.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2103094124 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 26875026 ps |
| CPU time | 0.61 seconds |
| Started | Feb 07 01:05:53 PM PST 24 |
| Finished | Feb 07 01:05:54 PM PST 24 |
| Peak memory | 191564 kb |
| Host | smart-30441927-4c1a-4896-b5ff-a1921b9be89e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103094124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti mer_same_csr_outstanding.2103094124 |
| Directory | /workspace/1.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3807917553 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 150425706 ps |
| CPU time | 1.94 seconds |
| Started | Feb 07 01:05:50 PM PST 24 |
| Finished | Feb 07 01:05:54 PM PST 24 |
| Peak memory | 197164 kb |
| Host | smart-3ef3901b-376d-46ad-947d-793df044c50e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807917553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3807917553 |
| Directory | /workspace/1.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3712262700 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 132325826 ps |
| CPU time | 1.41 seconds |
| Started | Feb 07 01:05:50 PM PST 24 |
| Finished | Feb 07 01:05:53 PM PST 24 |
| Peak memory | 182884 kb |
| Host | smart-1abb1c5d-aa7a-46ce-ba92-bcdd373c2442 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712262700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in tg_err.3712262700 |
| Directory | /workspace/1.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.4005345800 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 31664888 ps |
| CPU time | 0.88 seconds |
| Started | Feb 07 01:06:27 PM PST 24 |
| Finished | Feb 07 01:06:33 PM PST 24 |
| Peak memory | 196848 kb |
| Host | smart-adb94e04-b22f-4686-98a8-0f278838c8a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005345800 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.4005345800 |
| Directory | /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.336845451 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 21945081 ps |
| CPU time | 0.56 seconds |
| Started | Feb 07 01:06:29 PM PST 24 |
| Finished | Feb 07 01:06:33 PM PST 24 |
| Peak memory | 181972 kb |
| Host | smart-546c56c1-4110-483c-b9c8-072d1d1ebb16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336845451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.336845451 |
| Directory | /workspace/10.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1446590184 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 61988031 ps |
| CPU time | 0.56 seconds |
| Started | Feb 07 01:06:30 PM PST 24 |
| Finished | Feb 07 01:06:33 PM PST 24 |
| Peak memory | 182200 kb |
| Host | smart-0a1bfd4b-ef01-43c6-a126-a1a63f7fe09e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446590184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1446590184 |
| Directory | /workspace/10.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1042361915 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 141445202 ps |
| CPU time | 0.85 seconds |
| Started | Feb 07 01:06:30 PM PST 24 |
| Finished | Feb 07 01:06:33 PM PST 24 |
| Peak memory | 192944 kb |
| Host | smart-dc22b0d8-8a2d-4b15-989e-191e8a789cba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042361915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t imer_same_csr_outstanding.1042361915 |
| Directory | /workspace/10.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2309507356 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 179034033 ps |
| CPU time | 2.59 seconds |
| Started | Feb 07 01:06:30 PM PST 24 |
| Finished | Feb 07 01:06:35 PM PST 24 |
| Peak memory | 197180 kb |
| Host | smart-b6e44908-dd52-42eb-a2d2-bc528bc39627 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309507356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.2309507356 |
| Directory | /workspace/10.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3515655140 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 147798093 ps |
| CPU time | 1.04 seconds |
| Started | Feb 07 01:06:26 PM PST 24 |
| Finished | Feb 07 01:06:28 PM PST 24 |
| Peak memory | 194788 kb |
| Host | smart-59c717d7-2e18-4ec3-a72c-b69a07daf455 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515655140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i ntg_err.3515655140 |
| Directory | /workspace/10.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.580506367 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 26467846 ps |
| CPU time | 1.11 seconds |
| Started | Feb 07 01:06:27 PM PST 24 |
| Finished | Feb 07 01:06:32 PM PST 24 |
| Peak memory | 197056 kb |
| Host | smart-3f6b255c-334d-4c69-a829-5ef4d81e9e26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580506367 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.580506367 |
| Directory | /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3034529251 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 51070804 ps |
| CPU time | 0.57 seconds |
| Started | Feb 07 01:06:30 PM PST 24 |
| Finished | Feb 07 01:06:33 PM PST 24 |
| Peak memory | 182388 kb |
| Host | smart-442238f4-df8e-4a68-b50d-4da6fd531319 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034529251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3034529251 |
| Directory | /workspace/11.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.4267859279 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 16994654 ps |
| CPU time | 0.58 seconds |
| Started | Feb 07 01:06:26 PM PST 24 |
| Finished | Feb 07 01:06:28 PM PST 24 |
| Peak memory | 182116 kb |
| Host | smart-c7aee881-15b5-4825-b850-298470ffd6bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267859279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.4267859279 |
| Directory | /workspace/11.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.361742493 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 57300485 ps |
| CPU time | 0.62 seconds |
| Started | Feb 07 01:06:27 PM PST 24 |
| Finished | Feb 07 01:06:32 PM PST 24 |
| Peak memory | 190996 kb |
| Host | smart-d08b4311-00ca-45ac-9e77-73ad6de7bbf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361742493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_ti mer_same_csr_outstanding.361742493 |
| Directory | /workspace/11.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.782598079 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 102372651 ps |
| CPU time | 1.36 seconds |
| Started | Feb 07 01:06:30 PM PST 24 |
| Finished | Feb 07 01:06:34 PM PST 24 |
| Peak memory | 197232 kb |
| Host | smart-1f2f6849-0d7c-4ea8-ba23-51b9e17a819d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782598079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.782598079 |
| Directory | /workspace/11.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.4121363311 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 178850732 ps |
| CPU time | 0.84 seconds |
| Started | Feb 07 01:06:27 PM PST 24 |
| Finished | Feb 07 01:06:32 PM PST 24 |
| Peak memory | 192824 kb |
| Host | smart-30de8e09-93d7-4f78-870d-d2b72560e32c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121363311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i ntg_err.4121363311 |
| Directory | /workspace/11.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.205657857 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 38672363 ps |
| CPU time | 1.63 seconds |
| Started | Feb 07 01:06:54 PM PST 24 |
| Finished | Feb 07 01:06:59 PM PST 24 |
| Peak memory | 197168 kb |
| Host | smart-cf918ec8-82ea-423c-995c-aae701db1403 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205657857 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.205657857 |
| Directory | /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2797193745 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 13994754 ps |
| CPU time | 0.6 seconds |
| Started | Feb 07 01:06:55 PM PST 24 |
| Finished | Feb 07 01:07:00 PM PST 24 |
| Peak memory | 182284 kb |
| Host | smart-6bde6650-bd9a-4d92-81a2-d733547737d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797193745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2797193745 |
| Directory | /workspace/12.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.4133326853 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 23182221 ps |
| CPU time | 0.54 seconds |
| Started | Feb 07 01:06:53 PM PST 24 |
| Finished | Feb 07 01:06:56 PM PST 24 |
| Peak memory | 181540 kb |
| Host | smart-14343e68-45e7-49cf-835b-80338e4fa774 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133326853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.4133326853 |
| Directory | /workspace/12.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3463357637 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 24533762 ps |
| CPU time | 0.72 seconds |
| Started | Feb 07 01:06:52 PM PST 24 |
| Finished | Feb 07 01:06:56 PM PST 24 |
| Peak memory | 191136 kb |
| Host | smart-cc0f5aa9-0ed7-43e7-8fbe-79ec93f2a9a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463357637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t imer_same_csr_outstanding.3463357637 |
| Directory | /workspace/12.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1046078794 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 375308866 ps |
| CPU time | 1.62 seconds |
| Started | Feb 07 01:06:29 PM PST 24 |
| Finished | Feb 07 01:06:34 PM PST 24 |
| Peak memory | 197212 kb |
| Host | smart-74144fbf-5dda-44a2-a236-cbf999ca0dbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046078794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1046078794 |
| Directory | /workspace/12.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2741305974 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 116300643 ps |
| CPU time | 0.85 seconds |
| Started | Feb 07 01:06:54 PM PST 24 |
| Finished | Feb 07 01:06:58 PM PST 24 |
| Peak memory | 196452 kb |
| Host | smart-96c04445-6749-4418-b4fe-2bb92f97ec97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741305974 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2741305974 |
| Directory | /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1015539552 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 50416037 ps |
| CPU time | 0.54 seconds |
| Started | Feb 07 01:06:53 PM PST 24 |
| Finished | Feb 07 01:06:56 PM PST 24 |
| Peak memory | 181996 kb |
| Host | smart-6a605634-15c3-4640-ab9e-1a9fd9cec8af |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015539552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1015539552 |
| Directory | /workspace/13.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.690264284 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 28137319 ps |
| CPU time | 0.55 seconds |
| Started | Feb 07 01:06:56 PM PST 24 |
| Finished | Feb 07 01:07:01 PM PST 24 |
| Peak memory | 182152 kb |
| Host | smart-c61317b9-821b-42cb-9cd4-0d06a9fa403c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690264284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.690264284 |
| Directory | /workspace/13.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3714228415 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 20668112 ps |
| CPU time | 0.8 seconds |
| Started | Feb 07 01:06:59 PM PST 24 |
| Finished | Feb 07 01:07:04 PM PST 24 |
| Peak memory | 191268 kb |
| Host | smart-61024df4-1d2b-4eb5-ab56-b3dca8378d23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714228415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t imer_same_csr_outstanding.3714228415 |
| Directory | /workspace/13.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1172800342 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 175315090 ps |
| CPU time | 2.13 seconds |
| Started | Feb 07 01:06:53 PM PST 24 |
| Finished | Feb 07 01:06:57 PM PST 24 |
| Peak memory | 190656 kb |
| Host | smart-dc1144bc-4c23-4e91-9ce9-7ca808b3b1ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172800342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1172800342 |
| Directory | /workspace/13.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3426063099 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 148971255 ps |
| CPU time | 1.32 seconds |
| Started | Feb 07 01:06:51 PM PST 24 |
| Finished | Feb 07 01:06:56 PM PST 24 |
| Peak memory | 194692 kb |
| Host | smart-5f919a97-6263-4f56-99fe-9b43bcb0244b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426063099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i ntg_err.3426063099 |
| Directory | /workspace/13.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.8424129 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 52250477 ps |
| CPU time | 0.82 seconds |
| Started | Feb 07 01:06:55 PM PST 24 |
| Finished | Feb 07 01:07:01 PM PST 24 |
| Peak memory | 196252 kb |
| Host | smart-c5f036c9-9943-4c2b-8557-b460f88d7055 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8424129 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.8424129 |
| Directory | /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3256335269 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 14183044 ps |
| CPU time | 0.6 seconds |
| Started | Feb 07 01:06:53 PM PST 24 |
| Finished | Feb 07 01:06:56 PM PST 24 |
| Peak memory | 182268 kb |
| Host | smart-e7b15473-91f4-48a2-ac0c-b3ffd196934b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256335269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3256335269 |
| Directory | /workspace/14.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1138927063 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 13495890 ps |
| CPU time | 0.54 seconds |
| Started | Feb 07 01:06:54 PM PST 24 |
| Finished | Feb 07 01:06:57 PM PST 24 |
| Peak memory | 182144 kb |
| Host | smart-3b9f9094-f536-4fc9-83ee-632c1d5ec97f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138927063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1138927063 |
| Directory | /workspace/14.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3786727694 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 49604493 ps |
| CPU time | 0.74 seconds |
| Started | Feb 07 01:06:53 PM PST 24 |
| Finished | Feb 07 01:06:56 PM PST 24 |
| Peak memory | 191576 kb |
| Host | smart-0e1af403-73ce-4dce-bcdd-aa2f1f54874c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786727694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t imer_same_csr_outstanding.3786727694 |
| Directory | /workspace/14.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2451915076 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 113696563 ps |
| CPU time | 2.14 seconds |
| Started | Feb 07 01:06:55 PM PST 24 |
| Finished | Feb 07 01:07:02 PM PST 24 |
| Peak memory | 197240 kb |
| Host | smart-f457e147-2e54-4e3b-92c4-00093bc2bfca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451915076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2451915076 |
| Directory | /workspace/14.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2088212613 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 429222515 ps |
| CPU time | 1.46 seconds |
| Started | Feb 07 01:06:56 PM PST 24 |
| Finished | Feb 07 01:07:02 PM PST 24 |
| Peak memory | 182696 kb |
| Host | smart-0f55e896-c41f-4f35-9796-efd830a0f677 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088212613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i ntg_err.2088212613 |
| Directory | /workspace/14.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1204789463 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 42127781 ps |
| CPU time | 0.63 seconds |
| Started | Feb 07 01:06:53 PM PST 24 |
| Finished | Feb 07 01:06:56 PM PST 24 |
| Peak memory | 192800 kb |
| Host | smart-07c5e1a9-6210-40ec-a8ff-cddd872bd611 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204789463 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1204789463 |
| Directory | /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.48789614 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 11747508 ps |
| CPU time | 0.61 seconds |
| Started | Feb 07 01:06:54 PM PST 24 |
| Finished | Feb 07 01:07:00 PM PST 24 |
| Peak memory | 182260 kb |
| Host | smart-2cb2e387-f082-409f-91bc-9267bfa7cb9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48789614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.48789614 |
| Directory | /workspace/15.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1973909672 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 10304761 ps |
| CPU time | 0.53 seconds |
| Started | Feb 07 01:06:54 PM PST 24 |
| Finished | Feb 07 01:07:00 PM PST 24 |
| Peak memory | 181772 kb |
| Host | smart-ddbfd3eb-0b07-4e50-944d-4b54a7da10fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973909672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1973909672 |
| Directory | /workspace/15.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1121675258 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 78520111 ps |
| CPU time | 0.65 seconds |
| Started | Feb 07 01:06:54 PM PST 24 |
| Finished | Feb 07 01:06:56 PM PST 24 |
| Peak memory | 191560 kb |
| Host | smart-0435064b-51db-452f-9d90-85a8bee70d8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121675258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t imer_same_csr_outstanding.1121675258 |
| Directory | /workspace/15.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2330456618 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 188362233 ps |
| CPU time | 2.65 seconds |
| Started | Feb 07 01:06:58 PM PST 24 |
| Finished | Feb 07 01:07:05 PM PST 24 |
| Peak memory | 197236 kb |
| Host | smart-5404c315-36fc-42ea-b39c-99a4af04e405 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330456618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2330456618 |
| Directory | /workspace/15.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1471217405 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 36999126 ps |
| CPU time | 1.59 seconds |
| Started | Feb 07 01:06:56 PM PST 24 |
| Finished | Feb 07 01:07:02 PM PST 24 |
| Peak memory | 197188 kb |
| Host | smart-daa77d48-d641-4ce2-baad-24a7eb7c520a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471217405 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.1471217405 |
| Directory | /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3048508741 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 13019334 ps |
| CPU time | 0.58 seconds |
| Started | Feb 07 01:06:53 PM PST 24 |
| Finished | Feb 07 01:06:56 PM PST 24 |
| Peak memory | 182344 kb |
| Host | smart-bd6acc9d-c623-4394-93f4-c7b98489fa6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048508741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3048508741 |
| Directory | /workspace/16.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.794508874 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 27523311 ps |
| CPU time | 0.6 seconds |
| Started | Feb 07 01:06:54 PM PST 24 |
| Finished | Feb 07 01:06:58 PM PST 24 |
| Peak memory | 182096 kb |
| Host | smart-7e5a5ace-40ad-4bb0-bb04-cc57a9aaa943 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794508874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.794508874 |
| Directory | /workspace/16.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2353062624 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 18558287 ps |
| CPU time | 0.77 seconds |
| Started | Feb 07 01:06:55 PM PST 24 |
| Finished | Feb 07 01:07:01 PM PST 24 |
| Peak memory | 191316 kb |
| Host | smart-9fa1c323-3cd5-435b-8eb7-465514584cf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353062624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t imer_same_csr_outstanding.2353062624 |
| Directory | /workspace/16.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1986780884 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 236260437 ps |
| CPU time | 1.92 seconds |
| Started | Feb 07 01:06:56 PM PST 24 |
| Finished | Feb 07 01:07:02 PM PST 24 |
| Peak memory | 197176 kb |
| Host | smart-6a1d6379-4b83-45ea-a098-95e4aab077dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986780884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1986780884 |
| Directory | /workspace/16.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.242768791 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 53166357 ps |
| CPU time | 0.84 seconds |
| Started | Feb 07 01:06:53 PM PST 24 |
| Finished | Feb 07 01:06:56 PM PST 24 |
| Peak memory | 182384 kb |
| Host | smart-e8208aba-3c0b-4027-b4b9-9e6d8c0d8940 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242768791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in tg_err.242768791 |
| Directory | /workspace/16.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2240552443 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 150903139 ps |
| CPU time | 1.03 seconds |
| Started | Feb 07 01:06:54 PM PST 24 |
| Finished | Feb 07 01:07:01 PM PST 24 |
| Peak memory | 196908 kb |
| Host | smart-15d1d1f1-d343-4f1a-b784-eadcb3a34221 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240552443 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2240552443 |
| Directory | /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1764029939 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 18360206 ps |
| CPU time | 0.61 seconds |
| Started | Feb 07 01:06:52 PM PST 24 |
| Finished | Feb 07 01:06:56 PM PST 24 |
| Peak memory | 182336 kb |
| Host | smart-c84b532d-7daf-40a5-911c-e5570faf85f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764029939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1764029939 |
| Directory | /workspace/17.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.925126794 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 12945561 ps |
| CPU time | 0.57 seconds |
| Started | Feb 07 01:06:55 PM PST 24 |
| Finished | Feb 07 01:07:01 PM PST 24 |
| Peak memory | 182192 kb |
| Host | smart-439aa84a-fe28-4c66-ad49-5eefe51c5038 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925126794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.925126794 |
| Directory | /workspace/17.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1352144367 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 35935986 ps |
| CPU time | 0.63 seconds |
| Started | Feb 07 01:06:54 PM PST 24 |
| Finished | Feb 07 01:07:00 PM PST 24 |
| Peak memory | 191216 kb |
| Host | smart-801b845b-92ed-4b7b-921d-170fe0d90795 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352144367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t imer_same_csr_outstanding.1352144367 |
| Directory | /workspace/17.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.676046408 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 129779147 ps |
| CPU time | 1.86 seconds |
| Started | Feb 07 01:06:56 PM PST 24 |
| Finished | Feb 07 01:07:02 PM PST 24 |
| Peak memory | 197168 kb |
| Host | smart-4a08a798-92d2-420f-9bb3-badda2ae483f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676046408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.676046408 |
| Directory | /workspace/17.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.830651283 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 86915058 ps |
| CPU time | 1.08 seconds |
| Started | Feb 07 01:06:53 PM PST 24 |
| Finished | Feb 07 01:06:56 PM PST 24 |
| Peak memory | 194484 kb |
| Host | smart-aed2f851-fca1-4a87-ac82-19c373b61cb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830651283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in tg_err.830651283 |
| Directory | /workspace/17.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.104987959 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 102818934 ps |
| CPU time | 0.94 seconds |
| Started | Feb 07 01:06:54 PM PST 24 |
| Finished | Feb 07 01:07:00 PM PST 24 |
| Peak memory | 197044 kb |
| Host | smart-c6dd3072-9d54-49f9-bce0-847568ed14d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104987959 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.104987959 |
| Directory | /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3683357191 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 25240700 ps |
| CPU time | 0.57 seconds |
| Started | Feb 07 01:06:53 PM PST 24 |
| Finished | Feb 07 01:06:56 PM PST 24 |
| Peak memory | 182348 kb |
| Host | smart-6235bfa1-415a-43f1-afea-60cd04829611 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683357191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3683357191 |
| Directory | /workspace/18.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1579116959 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 38041135 ps |
| CPU time | 0.56 seconds |
| Started | Feb 07 01:06:52 PM PST 24 |
| Finished | Feb 07 01:06:56 PM PST 24 |
| Peak memory | 182152 kb |
| Host | smart-0500d6d4-8bda-4f44-8af0-a96a85fb9aa9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579116959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1579116959 |
| Directory | /workspace/18.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2530786524 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 276973862 ps |
| CPU time | 0.78 seconds |
| Started | Feb 07 01:06:51 PM PST 24 |
| Finished | Feb 07 01:06:56 PM PST 24 |
| Peak memory | 192792 kb |
| Host | smart-3ea91875-db96-4253-80ad-829540a14ee8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530786524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t imer_same_csr_outstanding.2530786524 |
| Directory | /workspace/18.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.4268007899 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 179865909 ps |
| CPU time | 2.33 seconds |
| Started | Feb 07 01:06:54 PM PST 24 |
| Finished | Feb 07 01:07:01 PM PST 24 |
| Peak memory | 197256 kb |
| Host | smart-00912ae6-b318-4824-baa5-3b87af3e9490 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268007899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.4268007899 |
| Directory | /workspace/18.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1187086929 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 81499977 ps |
| CPU time | 1.13 seconds |
| Started | Feb 07 01:06:50 PM PST 24 |
| Finished | Feb 07 01:06:55 PM PST 24 |
| Peak memory | 194768 kb |
| Host | smart-7677b99a-7cd4-4afa-b71f-ccece314debb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187086929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i ntg_err.1187086929 |
| Directory | /workspace/18.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.721741322 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 91632205 ps |
| CPU time | 0.76 seconds |
| Started | Feb 07 01:06:53 PM PST 24 |
| Finished | Feb 07 01:06:56 PM PST 24 |
| Peak memory | 195544 kb |
| Host | smart-36dd4a63-8a42-4483-a2f5-156d313601cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721741322 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.721741322 |
| Directory | /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2550202380 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 14700258 ps |
| CPU time | 0.54 seconds |
| Started | Feb 07 01:07:01 PM PST 24 |
| Finished | Feb 07 01:07:05 PM PST 24 |
| Peak memory | 181928 kb |
| Host | smart-64d5d84e-bfb4-42b2-bcc5-57cff2308ef4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550202380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2550202380 |
| Directory | /workspace/19.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.142868092 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 26337688 ps |
| CPU time | 0.54 seconds |
| Started | Feb 07 01:06:54 PM PST 24 |
| Finished | Feb 07 01:06:56 PM PST 24 |
| Peak memory | 182140 kb |
| Host | smart-7ede2f98-5e8d-496a-85d3-9afde8be8f57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142868092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.142868092 |
| Directory | /workspace/19.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2566908728 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 41271126 ps |
| CPU time | 0.83 seconds |
| Started | Feb 07 01:06:53 PM PST 24 |
| Finished | Feb 07 01:06:56 PM PST 24 |
| Peak memory | 192816 kb |
| Host | smart-076209d7-1dcd-45a3-ae3d-cfcba41c1b53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566908728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t imer_same_csr_outstanding.2566908728 |
| Directory | /workspace/19.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.993060152 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 61723337 ps |
| CPU time | 0.81 seconds |
| Started | Feb 07 01:06:54 PM PST 24 |
| Finished | Feb 07 01:06:58 PM PST 24 |
| Peak memory | 194344 kb |
| Host | smart-011a8e0b-c98c-4c7c-b49e-a74ca0ea01ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993060152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.993060152 |
| Directory | /workspace/19.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.424196787 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 259184621 ps |
| CPU time | 1.09 seconds |
| Started | Feb 07 01:06:55 PM PST 24 |
| Finished | Feb 07 01:07:01 PM PST 24 |
| Peak memory | 194540 kb |
| Host | smart-9a679837-8e36-4a6b-b5de-afb1668b60d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424196787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_in tg_err.424196787 |
| Directory | /workspace/19.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2037527526 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 25015867 ps |
| CPU time | 0.6 seconds |
| Started | Feb 07 01:06:11 PM PST 24 |
| Finished | Feb 07 01:06:12 PM PST 24 |
| Peak memory | 182416 kb |
| Host | smart-0550db84-a498-4308-8ee3-30bc4dff01dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037527526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia sing.2037527526 |
| Directory | /workspace/2.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1477511609 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 1428484773 ps |
| CPU time | 3.72 seconds |
| Started | Feb 07 01:06:03 PM PST 24 |
| Finished | Feb 07 01:06:07 PM PST 24 |
| Peak memory | 190760 kb |
| Host | smart-530fb78c-c77d-40b7-af75-81d2ebc0db27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477511609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_ bash.1477511609 |
| Directory | /workspace/2.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.274559705 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 14186162 ps |
| CPU time | 0.57 seconds |
| Started | Feb 07 01:06:02 PM PST 24 |
| Finished | Feb 07 01:06:03 PM PST 24 |
| Peak memory | 182364 kb |
| Host | smart-28ae8fc7-a6c8-4b1e-acb1-86e6f11bfd37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274559705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re set.274559705 |
| Directory | /workspace/2.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.676588043 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 23129078 ps |
| CPU time | 1.08 seconds |
| Started | Feb 07 01:06:07 PM PST 24 |
| Finished | Feb 07 01:06:08 PM PST 24 |
| Peak memory | 197032 kb |
| Host | smart-2f7188b6-e599-47b7-b897-b8613e1b1cfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676588043 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.676588043 |
| Directory | /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1930704054 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 68601115 ps |
| CPU time | 0.55 seconds |
| Started | Feb 07 01:06:10 PM PST 24 |
| Finished | Feb 07 01:06:11 PM PST 24 |
| Peak memory | 182320 kb |
| Host | smart-154d955c-a11d-4499-a041-b5480b35dc87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930704054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1930704054 |
| Directory | /workspace/2.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1647533174 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 34266711 ps |
| CPU time | 0.53 seconds |
| Started | Feb 07 01:06:02 PM PST 24 |
| Finished | Feb 07 01:06:03 PM PST 24 |
| Peak memory | 182184 kb |
| Host | smart-dc0e4278-4f5a-464b-997c-607b2047dbf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647533174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1647533174 |
| Directory | /workspace/2.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2715859222 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 19808815 ps |
| CPU time | 0.64 seconds |
| Started | Feb 07 01:06:02 PM PST 24 |
| Finished | Feb 07 01:06:04 PM PST 24 |
| Peak memory | 191588 kb |
| Host | smart-5a112ab3-382f-45ac-b723-533f918df2dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715859222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti mer_same_csr_outstanding.2715859222 |
| Directory | /workspace/2.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.4247697253 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 81859953 ps |
| CPU time | 1.35 seconds |
| Started | Feb 07 01:05:53 PM PST 24 |
| Finished | Feb 07 01:05:55 PM PST 24 |
| Peak memory | 197076 kb |
| Host | smart-fb1b359a-7699-4235-9ae3-b4b77d3b0c43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247697253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.4247697253 |
| Directory | /workspace/2.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.622074749 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 262276230 ps |
| CPU time | 1.04 seconds |
| Started | Feb 07 01:06:02 PM PST 24 |
| Finished | Feb 07 01:06:04 PM PST 24 |
| Peak memory | 194524 kb |
| Host | smart-346851c2-0565-4bba-b048-8eee5d08e23e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622074749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_int g_err.622074749 |
| Directory | /workspace/2.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2115445139 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 16963052 ps |
| CPU time | 0.56 seconds |
| Started | Feb 07 01:07:04 PM PST 24 |
| Finished | Feb 07 01:07:06 PM PST 24 |
| Peak memory | 182252 kb |
| Host | smart-db020fec-e4a6-488e-a1a2-0f0963082955 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115445139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2115445139 |
| Directory | /workspace/20.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3418841939 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 38241588 ps |
| CPU time | 0.62 seconds |
| Started | Feb 07 01:06:51 PM PST 24 |
| Finished | Feb 07 01:06:56 PM PST 24 |
| Peak memory | 182208 kb |
| Host | smart-64c7ae85-5e0e-4067-9363-2838e37177ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418841939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3418841939 |
| Directory | /workspace/21.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1763562541 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 30360135 ps |
| CPU time | 0.58 seconds |
| Started | Feb 07 01:06:53 PM PST 24 |
| Finished | Feb 07 01:06:56 PM PST 24 |
| Peak memory | 182188 kb |
| Host | smart-46529edb-e1f6-4549-afda-3cde93a0679b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763562541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.1763562541 |
| Directory | /workspace/22.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.4026313361 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 29734641 ps |
| CPU time | 0.56 seconds |
| Started | Feb 07 01:06:56 PM PST 24 |
| Finished | Feb 07 01:07:01 PM PST 24 |
| Peak memory | 182152 kb |
| Host | smart-2447b51b-b7fd-4361-88d6-06322bb932b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026313361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.4026313361 |
| Directory | /workspace/23.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3352953659 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 65145606 ps |
| CPU time | 0.6 seconds |
| Started | Feb 07 01:06:52 PM PST 24 |
| Finished | Feb 07 01:06:56 PM PST 24 |
| Peak memory | 181824 kb |
| Host | smart-8cb666cd-da58-4d8a-b5d4-4766e1e625f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352953659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3352953659 |
| Directory | /workspace/24.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1430851240 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 26414360 ps |
| CPU time | 0.58 seconds |
| Started | Feb 07 01:07:05 PM PST 24 |
| Finished | Feb 07 01:07:07 PM PST 24 |
| Peak memory | 182260 kb |
| Host | smart-108205b4-d7c1-4e26-9918-2fa08980332a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430851240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1430851240 |
| Directory | /workspace/25.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1974727267 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 47655988 ps |
| CPU time | 0.58 seconds |
| Started | Feb 07 01:06:56 PM PST 24 |
| Finished | Feb 07 01:07:01 PM PST 24 |
| Peak memory | 182128 kb |
| Host | smart-3079be07-c100-4314-b14f-29177a2e4b08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974727267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1974727267 |
| Directory | /workspace/26.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2551036693 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 17574177 ps |
| CPU time | 0.58 seconds |
| Started | Feb 07 01:06:59 PM PST 24 |
| Finished | Feb 07 01:07:03 PM PST 24 |
| Peak memory | 182172 kb |
| Host | smart-00133d94-4c28-4ba1-93e0-330ad85e90e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551036693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2551036693 |
| Directory | /workspace/27.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1173295390 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 14389213 ps |
| CPU time | 0.56 seconds |
| Started | Feb 07 01:07:05 PM PST 24 |
| Finished | Feb 07 01:07:06 PM PST 24 |
| Peak memory | 182188 kb |
| Host | smart-c58e942d-713d-41e2-a08b-cfc5e86457a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173295390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1173295390 |
| Directory | /workspace/28.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.591403623 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 20656584 ps |
| CPU time | 0.53 seconds |
| Started | Feb 07 01:06:55 PM PST 24 |
| Finished | Feb 07 01:07:01 PM PST 24 |
| Peak memory | 182144 kb |
| Host | smart-b6647ec7-08e7-445b-9d44-6b6c6b403cda |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591403623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.591403623 |
| Directory | /workspace/29.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3365083835 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 301683679 ps |
| CPU time | 0.89 seconds |
| Started | Feb 07 01:06:02 PM PST 24 |
| Finished | Feb 07 01:06:04 PM PST 24 |
| Peak memory | 182280 kb |
| Host | smart-d5f0dcec-2312-4769-a3eb-af5be3b7d5a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365083835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia sing.3365083835 |
| Directory | /workspace/3.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1578496839 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 170223212 ps |
| CPU time | 3.23 seconds |
| Started | Feb 07 01:06:02 PM PST 24 |
| Finished | Feb 07 01:06:05 PM PST 24 |
| Peak memory | 182680 kb |
| Host | smart-ebb886cb-e2cd-45ca-80ff-deab796464e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578496839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_ bash.1578496839 |
| Directory | /workspace/3.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.8024168 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 58670530 ps |
| CPU time | 0.8 seconds |
| Started | Feb 07 01:06:05 PM PST 24 |
| Finished | Feb 07 01:06:07 PM PST 24 |
| Peak memory | 195976 kb |
| Host | smart-3800b4bd-b8c6-40ee-ace7-f6b8eb535b12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8024168 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.8024168 |
| Directory | /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2284300910 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 17180871 ps |
| CPU time | 0.58 seconds |
| Started | Feb 07 01:06:09 PM PST 24 |
| Finished | Feb 07 01:06:10 PM PST 24 |
| Peak memory | 182336 kb |
| Host | smart-cf65535a-2880-4cec-a899-a441e1af65fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284300910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2284300910 |
| Directory | /workspace/3.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2366896878 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 47356248 ps |
| CPU time | 0.56 seconds |
| Started | Feb 07 01:06:03 PM PST 24 |
| Finished | Feb 07 01:06:05 PM PST 24 |
| Peak memory | 182192 kb |
| Host | smart-04c88d28-9547-48d4-ba9e-803e72bd0d99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366896878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2366896878 |
| Directory | /workspace/3.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.740181191 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 227440370 ps |
| CPU time | 2.15 seconds |
| Started | Feb 07 01:06:04 PM PST 24 |
| Finished | Feb 07 01:06:06 PM PST 24 |
| Peak memory | 197212 kb |
| Host | smart-26f32790-7ed6-40c3-bc6b-498ad1f92b32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740181191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.740181191 |
| Directory | /workspace/3.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2886008652 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 161695559 ps |
| CPU time | 1.19 seconds |
| Started | Feb 07 01:06:03 PM PST 24 |
| Finished | Feb 07 01:06:05 PM PST 24 |
| Peak memory | 194492 kb |
| Host | smart-a6e58230-f5a2-4db2-adb7-f5a8eeee5317 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886008652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in tg_err.2886008652 |
| Directory | /workspace/3.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2080286789 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 73016543 ps |
| CPU time | 0.54 seconds |
| Started | Feb 07 01:06:56 PM PST 24 |
| Finished | Feb 07 01:07:01 PM PST 24 |
| Peak memory | 182112 kb |
| Host | smart-0b5997f0-1dc1-4d03-9e89-38fe7aceb726 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080286789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2080286789 |
| Directory | /workspace/30.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1189765930 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 14216454 ps |
| CPU time | 0.57 seconds |
| Started | Feb 07 01:06:52 PM PST 24 |
| Finished | Feb 07 01:06:56 PM PST 24 |
| Peak memory | 182060 kb |
| Host | smart-1345ec77-6893-4e42-a8fb-9eee39cb872b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189765930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1189765930 |
| Directory | /workspace/31.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.867405893 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 55514527 ps |
| CPU time | 0.56 seconds |
| Started | Feb 07 01:06:56 PM PST 24 |
| Finished | Feb 07 01:07:01 PM PST 24 |
| Peak memory | 182140 kb |
| Host | smart-53a63cbb-a94d-4a7f-9e1a-81003d7e8c8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867405893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.867405893 |
| Directory | /workspace/32.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3837324767 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 16354877 ps |
| CPU time | 0.55 seconds |
| Started | Feb 07 01:07:04 PM PST 24 |
| Finished | Feb 07 01:07:06 PM PST 24 |
| Peak memory | 182256 kb |
| Host | smart-c12edf35-1996-478c-ad32-00c2221a316c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837324767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3837324767 |
| Directory | /workspace/33.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2632987100 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 96397516 ps |
| CPU time | 0.57 seconds |
| Started | Feb 07 01:07:04 PM PST 24 |
| Finished | Feb 07 01:07:06 PM PST 24 |
| Peak memory | 182144 kb |
| Host | smart-7f84208e-74d4-4c70-8459-449383ebfd23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632987100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2632987100 |
| Directory | /workspace/34.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2769761775 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 34263673 ps |
| CPU time | 0.52 seconds |
| Started | Feb 07 01:06:57 PM PST 24 |
| Finished | Feb 07 01:07:01 PM PST 24 |
| Peak memory | 181584 kb |
| Host | smart-b4ddfe35-4757-43d1-bce7-bd30a229a58e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769761775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2769761775 |
| Directory | /workspace/35.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3662299754 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 22376166 ps |
| CPU time | 0.55 seconds |
| Started | Feb 07 01:06:58 PM PST 24 |
| Finished | Feb 07 01:07:03 PM PST 24 |
| Peak memory | 182184 kb |
| Host | smart-fdac4699-c78e-4bc5-b1e3-557fbec11fb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662299754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3662299754 |
| Directory | /workspace/36.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.649972293 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 12541694 ps |
| CPU time | 0.57 seconds |
| Started | Feb 07 01:06:59 PM PST 24 |
| Finished | Feb 07 01:07:04 PM PST 24 |
| Peak memory | 182188 kb |
| Host | smart-eadad804-873f-435a-b6a6-23f85b65de44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649972293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.649972293 |
| Directory | /workspace/37.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1292436252 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 62824550 ps |
| CPU time | 0.55 seconds |
| Started | Feb 07 01:06:58 PM PST 24 |
| Finished | Feb 07 01:07:03 PM PST 24 |
| Peak memory | 182256 kb |
| Host | smart-23dcd19f-d651-4f11-966b-9a48e5703438 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292436252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1292436252 |
| Directory | /workspace/38.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2978405847 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 20677054 ps |
| CPU time | 0.57 seconds |
| Started | Feb 07 01:06:57 PM PST 24 |
| Finished | Feb 07 01:07:02 PM PST 24 |
| Peak memory | 182248 kb |
| Host | smart-5e63512a-6651-47e8-a56c-4606399f728b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978405847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2978405847 |
| Directory | /workspace/39.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.563683399 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 137661984 ps |
| CPU time | 0.85 seconds |
| Started | Feb 07 01:06:09 PM PST 24 |
| Finished | Feb 07 01:06:10 PM PST 24 |
| Peak memory | 192068 kb |
| Host | smart-cbfa5884-0792-4ca6-814a-056f84522f70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563683399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alias ing.563683399 |
| Directory | /workspace/4.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2603543769 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 94063182 ps |
| CPU time | 3.13 seconds |
| Started | Feb 07 01:06:02 PM PST 24 |
| Finished | Feb 07 01:06:06 PM PST 24 |
| Peak memory | 190656 kb |
| Host | smart-ca205b24-4b0f-45e4-8890-47a526184652 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603543769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_ bash.2603543769 |
| Directory | /workspace/4.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2061792043 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 34702772 ps |
| CPU time | 0.56 seconds |
| Started | Feb 07 01:06:02 PM PST 24 |
| Finished | Feb 07 01:06:03 PM PST 24 |
| Peak memory | 182340 kb |
| Host | smart-5ebf67a3-5ef3-4926-b846-78cb1948ae2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061792043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r eset.2061792043 |
| Directory | /workspace/4.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3754692824 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 123169777 ps |
| CPU time | 1.53 seconds |
| Started | Feb 07 01:06:04 PM PST 24 |
| Finished | Feb 07 01:06:06 PM PST 24 |
| Peak memory | 197200 kb |
| Host | smart-8ccf36da-05a4-4ecf-9517-a3255e9c774d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754692824 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3754692824 |
| Directory | /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2746624612 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 11457945 ps |
| CPU time | 0.56 seconds |
| Started | Feb 07 01:06:01 PM PST 24 |
| Finished | Feb 07 01:06:03 PM PST 24 |
| Peak memory | 182320 kb |
| Host | smart-69e98af1-008b-4fc8-8b7f-1687fffb36aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746624612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2746624612 |
| Directory | /workspace/4.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2612546239 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 11723717 ps |
| CPU time | 0.62 seconds |
| Started | Feb 07 01:06:12 PM PST 24 |
| Finished | Feb 07 01:06:13 PM PST 24 |
| Peak memory | 182152 kb |
| Host | smart-3af888f6-d555-4a70-add7-1d3db6934a96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612546239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2612546239 |
| Directory | /workspace/4.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2653253687 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 123274595 ps |
| CPU time | 0.76 seconds |
| Started | Feb 07 01:06:03 PM PST 24 |
| Finished | Feb 07 01:06:04 PM PST 24 |
| Peak memory | 191336 kb |
| Host | smart-065d8cd9-0183-4844-b7cf-0fa1bd6744c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653253687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti mer_same_csr_outstanding.2653253687 |
| Directory | /workspace/4.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2774501657 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 38020732 ps |
| CPU time | 1.77 seconds |
| Started | Feb 07 01:06:03 PM PST 24 |
| Finished | Feb 07 01:06:05 PM PST 24 |
| Peak memory | 197204 kb |
| Host | smart-f2e6bbaa-d473-457e-8aba-a72d084bd83e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774501657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2774501657 |
| Directory | /workspace/4.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1703913645 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 90937347 ps |
| CPU time | 1.12 seconds |
| Started | Feb 07 01:06:03 PM PST 24 |
| Finished | Feb 07 01:06:05 PM PST 24 |
| Peak memory | 194608 kb |
| Host | smart-2c267ac4-0e67-4f6f-b446-4fd29d4712fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703913645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in tg_err.1703913645 |
| Directory | /workspace/4.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1551657534 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 14975065 ps |
| CPU time | 0.53 seconds |
| Started | Feb 07 01:06:58 PM PST 24 |
| Finished | Feb 07 01:07:03 PM PST 24 |
| Peak memory | 182244 kb |
| Host | smart-1a583970-726e-4114-b92b-23d1021a171d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551657534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1551657534 |
| Directory | /workspace/40.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3161011494 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 13553364 ps |
| CPU time | 0.53 seconds |
| Started | Feb 07 01:06:59 PM PST 24 |
| Finished | Feb 07 01:07:03 PM PST 24 |
| Peak memory | 181612 kb |
| Host | smart-21e441c6-d7e4-4f2e-b5b5-944c1b80c76f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161011494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3161011494 |
| Directory | /workspace/41.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2746852358 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 14146434 ps |
| CPU time | 0.53 seconds |
| Started | Feb 07 01:06:53 PM PST 24 |
| Finished | Feb 07 01:06:56 PM PST 24 |
| Peak memory | 181624 kb |
| Host | smart-0b778fbc-0135-4dfb-a520-d4ceda5e580f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746852358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2746852358 |
| Directory | /workspace/42.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2973106402 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 29656035 ps |
| CPU time | 0.57 seconds |
| Started | Feb 07 01:06:59 PM PST 24 |
| Finished | Feb 07 01:07:03 PM PST 24 |
| Peak memory | 181612 kb |
| Host | smart-cc7b5abd-c7a0-448f-baa0-8520b2b4a4bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973106402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2973106402 |
| Directory | /workspace/43.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1508121017 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 30715679 ps |
| CPU time | 0.56 seconds |
| Started | Feb 07 01:06:58 PM PST 24 |
| Finished | Feb 07 01:07:03 PM PST 24 |
| Peak memory | 181636 kb |
| Host | smart-30612bec-8884-4b20-9197-a287c94af2d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508121017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1508121017 |
| Directory | /workspace/44.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.714377705 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 16766850 ps |
| CPU time | 0.57 seconds |
| Started | Feb 07 01:06:58 PM PST 24 |
| Finished | Feb 07 01:07:03 PM PST 24 |
| Peak memory | 181808 kb |
| Host | smart-6925a097-5aa8-465a-99c9-fc7957644ea9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714377705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.714377705 |
| Directory | /workspace/45.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2571836038 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 29257605 ps |
| CPU time | 0.57 seconds |
| Started | Feb 07 01:06:59 PM PST 24 |
| Finished | Feb 07 01:07:04 PM PST 24 |
| Peak memory | 182156 kb |
| Host | smart-a386bd0e-2c7f-41d3-9418-11baa3adcf0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571836038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2571836038 |
| Directory | /workspace/46.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.66447036 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 17768833 ps |
| CPU time | 0.57 seconds |
| Started | Feb 07 01:07:04 PM PST 24 |
| Finished | Feb 07 01:07:06 PM PST 24 |
| Peak memory | 182200 kb |
| Host | smart-df0ce5c7-3123-4569-9368-d24737c3b4dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66447036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.66447036 |
| Directory | /workspace/47.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3135996164 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 35765920 ps |
| CPU time | 0.56 seconds |
| Started | Feb 07 01:06:58 PM PST 24 |
| Finished | Feb 07 01:07:03 PM PST 24 |
| Peak memory | 181868 kb |
| Host | smart-941e65e5-ee63-4ed1-9697-fc820967a250 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135996164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3135996164 |
| Directory | /workspace/48.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1979669287 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 79421786 ps |
| CPU time | 0.57 seconds |
| Started | Feb 07 01:07:04 PM PST 24 |
| Finished | Feb 07 01:07:06 PM PST 24 |
| Peak memory | 182276 kb |
| Host | smart-cdcbadfd-4b57-424f-b50b-f393ae874d43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979669287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1979669287 |
| Directory | /workspace/49.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3277292423 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 44862467 ps |
| CPU time | 0.82 seconds |
| Started | Feb 07 01:06:27 PM PST 24 |
| Finished | Feb 07 01:06:31 PM PST 24 |
| Peak memory | 194460 kb |
| Host | smart-df493059-5faf-4373-b02d-4c1d8bb8eee4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277292423 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.3277292423 |
| Directory | /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.369073825 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 19661092 ps |
| CPU time | 0.52 seconds |
| Started | Feb 07 01:06:30 PM PST 24 |
| Finished | Feb 07 01:06:33 PM PST 24 |
| Peak memory | 181944 kb |
| Host | smart-7934a684-4601-4a2f-a433-4962238f98d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369073825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.369073825 |
| Directory | /workspace/5.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3412575254 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 14995122 ps |
| CPU time | 0.54 seconds |
| Started | Feb 07 01:06:29 PM PST 24 |
| Finished | Feb 07 01:06:33 PM PST 24 |
| Peak memory | 182316 kb |
| Host | smart-48e75727-87c4-4593-a4b7-4aeed51c7ff9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412575254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.3412575254 |
| Directory | /workspace/5.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1683128283 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 24371276 ps |
| CPU time | 0.73 seconds |
| Started | Feb 07 01:06:29 PM PST 24 |
| Finished | Feb 07 01:06:33 PM PST 24 |
| Peak memory | 191572 kb |
| Host | smart-bf404931-c711-44bd-b24f-8b211d47d640 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683128283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti mer_same_csr_outstanding.1683128283 |
| Directory | /workspace/5.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2460906261 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 207310770 ps |
| CPU time | 1.32 seconds |
| Started | Feb 07 01:06:03 PM PST 24 |
| Finished | Feb 07 01:06:05 PM PST 24 |
| Peak memory | 195204 kb |
| Host | smart-dc6f54db-f180-4711-bf08-28cbc625d725 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460906261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2460906261 |
| Directory | /workspace/5.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.980694299 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 78384155 ps |
| CPU time | 0.8 seconds |
| Started | Feb 07 01:06:29 PM PST 24 |
| Finished | Feb 07 01:06:33 PM PST 24 |
| Peak memory | 192800 kb |
| Host | smart-462a4f5f-5e3b-436c-bf73-7da5e425b2a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980694299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int g_err.980694299 |
| Directory | /workspace/5.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2063253577 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 27549255 ps |
| CPU time | 0.84 seconds |
| Started | Feb 07 01:06:28 PM PST 24 |
| Finished | Feb 07 01:06:33 PM PST 24 |
| Peak memory | 195168 kb |
| Host | smart-dd4b24c8-7ba3-4dcf-9550-944438fb992e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063253577 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2063253577 |
| Directory | /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.889832222 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 11992302 ps |
| CPU time | 0.58 seconds |
| Started | Feb 07 01:06:29 PM PST 24 |
| Finished | Feb 07 01:06:33 PM PST 24 |
| Peak memory | 182364 kb |
| Host | smart-5e201b0b-fb94-4ce3-a4e0-392024f696ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889832222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.889832222 |
| Directory | /workspace/6.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1087320508 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 28431461 ps |
| CPU time | 0.56 seconds |
| Started | Feb 07 01:06:28 PM PST 24 |
| Finished | Feb 07 01:06:33 PM PST 24 |
| Peak memory | 181632 kb |
| Host | smart-bd8ed44e-b76c-4614-a476-560d53fb68ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087320508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1087320508 |
| Directory | /workspace/6.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1175028021 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 88237655 ps |
| CPU time | 0.69 seconds |
| Started | Feb 07 01:06:28 PM PST 24 |
| Finished | Feb 07 01:06:33 PM PST 24 |
| Peak memory | 191060 kb |
| Host | smart-d6030d7f-e618-4c22-8924-573d69ed7e84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175028021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti mer_same_csr_outstanding.1175028021 |
| Directory | /workspace/6.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.199247434 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 53673767 ps |
| CPU time | 2.61 seconds |
| Started | Feb 07 01:06:30 PM PST 24 |
| Finished | Feb 07 01:06:35 PM PST 24 |
| Peak memory | 197232 kb |
| Host | smart-0ee60d9a-ccd5-411c-807c-145436ae7a32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199247434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.199247434 |
| Directory | /workspace/6.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1274632643 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 207648481 ps |
| CPU time | 1.35 seconds |
| Started | Feb 07 01:06:30 PM PST 24 |
| Finished | Feb 07 01:06:34 PM PST 24 |
| Peak memory | 194896 kb |
| Host | smart-5bf7f2a4-b697-4722-a14e-39a64d21252a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274632643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in tg_err.1274632643 |
| Directory | /workspace/6.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1709284308 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 156784755 ps |
| CPU time | 0.91 seconds |
| Started | Feb 07 01:06:26 PM PST 24 |
| Finished | Feb 07 01:06:28 PM PST 24 |
| Peak memory | 196916 kb |
| Host | smart-c9317e76-a84f-4c8e-8697-e4992843b3ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709284308 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1709284308 |
| Directory | /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.971801016 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 47750977 ps |
| CPU time | 0.59 seconds |
| Started | Feb 07 01:06:30 PM PST 24 |
| Finished | Feb 07 01:06:33 PM PST 24 |
| Peak memory | 182332 kb |
| Host | smart-b9e41c5f-4e80-46f3-aa4f-bd111d8783f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971801016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.971801016 |
| Directory | /workspace/7.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1688125213 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 12618522 ps |
| CPU time | 0.52 seconds |
| Started | Feb 07 01:06:30 PM PST 24 |
| Finished | Feb 07 01:06:33 PM PST 24 |
| Peak memory | 181412 kb |
| Host | smart-2ba6e574-29fc-4e0c-a286-966e1cb3fcf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688125213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1688125213 |
| Directory | /workspace/7.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2290402987 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 103652188 ps |
| CPU time | 0.66 seconds |
| Started | Feb 07 01:06:30 PM PST 24 |
| Finished | Feb 07 01:06:33 PM PST 24 |
| Peak memory | 191732 kb |
| Host | smart-577a7b38-885e-4c8f-b329-28b3bd3b9dc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290402987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti mer_same_csr_outstanding.2290402987 |
| Directory | /workspace/7.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.236852151 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 39151734 ps |
| CPU time | 1.93 seconds |
| Started | Feb 07 01:06:27 PM PST 24 |
| Finished | Feb 07 01:06:29 PM PST 24 |
| Peak memory | 197236 kb |
| Host | smart-072cea10-9259-4a4a-89a1-3ad3b9c6793c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236852151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.236852151 |
| Directory | /workspace/7.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2860957192 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 50870588 ps |
| CPU time | 0.83 seconds |
| Started | Feb 07 01:06:30 PM PST 24 |
| Finished | Feb 07 01:06:33 PM PST 24 |
| Peak memory | 192616 kb |
| Host | smart-b1e4ac02-0c8c-4ba5-a02c-b7afb2a70b48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860957192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in tg_err.2860957192 |
| Directory | /workspace/7.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3957593975 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 13139412 ps |
| CPU time | 0.66 seconds |
| Started | Feb 07 01:06:30 PM PST 24 |
| Finished | Feb 07 01:06:33 PM PST 24 |
| Peak memory | 193744 kb |
| Host | smart-027f43c5-4f7d-4987-a133-c572c2212e42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957593975 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3957593975 |
| Directory | /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.482242669 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 47379609 ps |
| CPU time | 0.58 seconds |
| Started | Feb 07 01:06:28 PM PST 24 |
| Finished | Feb 07 01:06:33 PM PST 24 |
| Peak memory | 181900 kb |
| Host | smart-5f94b1ba-0b05-48ce-ad1a-81852c75b4fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482242669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.482242669 |
| Directory | /workspace/8.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1227308618 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 21095742 ps |
| CPU time | 0.53 seconds |
| Started | Feb 07 01:06:27 PM PST 24 |
| Finished | Feb 07 01:06:31 PM PST 24 |
| Peak memory | 181664 kb |
| Host | smart-50054608-d073-4599-953d-be2b44723a26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227308618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1227308618 |
| Directory | /workspace/8.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.799268302 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 18919304 ps |
| CPU time | 0.63 seconds |
| Started | Feb 07 01:06:30 PM PST 24 |
| Finished | Feb 07 01:06:33 PM PST 24 |
| Peak memory | 191208 kb |
| Host | smart-d7b0229c-71e5-47ca-aae1-568d81dfee48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799268302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim er_same_csr_outstanding.799268302 |
| Directory | /workspace/8.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.744456330 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 463670129 ps |
| CPU time | 1.63 seconds |
| Started | Feb 07 01:06:28 PM PST 24 |
| Finished | Feb 07 01:06:34 PM PST 24 |
| Peak memory | 197200 kb |
| Host | smart-26979a8c-81bb-4e05-9369-9f590348ff4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744456330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.744456330 |
| Directory | /workspace/8.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.4196237718 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 102875306 ps |
| CPU time | 0.83 seconds |
| Started | Feb 07 01:06:27 PM PST 24 |
| Finished | Feb 07 01:06:28 PM PST 24 |
| Peak memory | 193176 kb |
| Host | smart-2d7ba360-b8b5-4e78-813e-9345fe0e7736 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196237718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in tg_err.4196237718 |
| Directory | /workspace/8.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.4197961688 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 20013926 ps |
| CPU time | 0.81 seconds |
| Started | Feb 07 01:06:28 PM PST 24 |
| Finished | Feb 07 01:06:33 PM PST 24 |
| Peak memory | 196360 kb |
| Host | smart-28fb4feb-166b-4c8e-a91b-1f11dae1c9fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197961688 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.4197961688 |
| Directory | /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1510636004 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 14311019 ps |
| CPU time | 0.55 seconds |
| Started | Feb 07 01:06:29 PM PST 24 |
| Finished | Feb 07 01:06:33 PM PST 24 |
| Peak memory | 181736 kb |
| Host | smart-53f39dea-fc68-4c13-ba08-c46d34f5a5c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510636004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1510636004 |
| Directory | /workspace/9.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2213301019 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 12935583 ps |
| CPU time | 0.55 seconds |
| Started | Feb 07 01:06:30 PM PST 24 |
| Finished | Feb 07 01:06:33 PM PST 24 |
| Peak memory | 182188 kb |
| Host | smart-6e3ae75c-f6d6-45ba-8df0-7f623a53e6c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213301019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2213301019 |
| Directory | /workspace/9.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3432788775 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 49054830 ps |
| CPU time | 0.69 seconds |
| Started | Feb 07 01:06:29 PM PST 24 |
| Finished | Feb 07 01:06:33 PM PST 24 |
| Peak memory | 191500 kb |
| Host | smart-5ba0af35-9919-4fc2-9848-62ee2d11d857 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432788775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti mer_same_csr_outstanding.3432788775 |
| Directory | /workspace/9.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.903718451 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 265244094 ps |
| CPU time | 1.31 seconds |
| Started | Feb 07 01:06:30 PM PST 24 |
| Finished | Feb 07 01:06:34 PM PST 24 |
| Peak memory | 197068 kb |
| Host | smart-3996c35c-5da1-4865-a04f-4b693befbefc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903718451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.903718451 |
| Directory | /workspace/9.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2977675072 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 86554284 ps |
| CPU time | 1.07 seconds |
| Started | Feb 07 01:06:35 PM PST 24 |
| Finished | Feb 07 01:06:37 PM PST 24 |
| Peak memory | 194496 kb |
| Host | smart-30ae8d07-78c6-4b6c-a4af-a5f6c8c00ea7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977675072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in tg_err.2977675072 |
| Directory | /workspace/9.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.984737012 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 1251323294084 ps |
| CPU time | 674.63 seconds |
| Started | Feb 07 12:35:52 PM PST 24 |
| Finished | Feb 07 12:47:10 PM PST 24 |
| Peak memory | 182300 kb |
| Host | smart-bdab7014-44a4-4034-b1ec-0d8f841451c8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984737012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .rv_timer_cfg_update_on_fly.984737012 |
| Directory | /workspace/0.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/0.rv_timer_disabled.2260244353 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 123753937347 ps |
| CPU time | 45.86 seconds |
| Started | Feb 07 12:35:50 PM PST 24 |
| Finished | Feb 07 12:36:38 PM PST 24 |
| Peak memory | 182296 kb |
| Host | smart-8c7e612f-bd65-4aa4-8bfb-a108dd838874 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2260244353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2260244353 |
| Directory | /workspace/0.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/0.rv_timer_random_reset.3561634789 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 4704051978 ps |
| CPU time | 62.29 seconds |
| Started | Feb 07 12:35:55 PM PST 24 |
| Finished | Feb 07 12:37:01 PM PST 24 |
| Peak memory | 190552 kb |
| Host | smart-c15051d7-b3d3-4e94-8790-11704a2764a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3561634789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3561634789 |
| Directory | /workspace/0.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/0.rv_timer_stress_all.3788694155 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 388777031305 ps |
| CPU time | 776.68 seconds |
| Started | Feb 07 12:36:01 PM PST 24 |
| Finished | Feb 07 12:49:00 PM PST 24 |
| Peak memory | 195100 kb |
| Host | smart-bb504294-8520-4d45-bbbc-5128aa4151c6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788694155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all. 3788694155 |
| Directory | /workspace/0.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.2161302174 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 94670759371 ps |
| CPU time | 378.58 seconds |
| Started | Feb 07 12:35:51 PM PST 24 |
| Finished | Feb 07 12:42:11 PM PST 24 |
| Peak memory | 205548 kb |
| Host | smart-95d57ec8-105d-4e75-a210-44ba1c197d42 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161302174 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.2161302174 |
| Directory | /workspace/0.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.rv_timer_disabled.2875485691 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 403044562248 ps |
| CPU time | 158.82 seconds |
| Started | Feb 07 12:35:54 PM PST 24 |
| Finished | Feb 07 12:38:35 PM PST 24 |
| Peak memory | 182344 kb |
| Host | smart-1ffa9285-30b0-4f9f-9ba6-98bf1857e05e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2875485691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2875485691 |
| Directory | /workspace/1.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/1.rv_timer_random.2388773704 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 323225018087 ps |
| CPU time | 356.24 seconds |
| Started | Feb 07 12:35:57 PM PST 24 |
| Finished | Feb 07 12:41:56 PM PST 24 |
| Peak memory | 190560 kb |
| Host | smart-7c7f9050-0829-4edb-9b7f-a126126dcad5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388773704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2388773704 |
| Directory | /workspace/1.rv_timer_random/latest |
| Test location | /workspace/coverage/default/1.rv_timer_random_reset.135601448 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 67598343363 ps |
| CPU time | 118.25 seconds |
| Started | Feb 07 12:35:59 PM PST 24 |
| Finished | Feb 07 12:38:00 PM PST 24 |
| Peak memory | 190584 kb |
| Host | smart-32ded564-d93b-4959-b42b-c042023f9227 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=135601448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.135601448 |
| Directory | /workspace/1.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/1.rv_timer_sec_cm.2980466459 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 233331594 ps |
| CPU time | 0.83 seconds |
| Started | Feb 07 12:36:05 PM PST 24 |
| Finished | Feb 07 12:36:07 PM PST 24 |
| Peak memory | 212704 kb |
| Host | smart-cb3953ed-838f-418a-847b-e4589cbb50fb |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980466459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2980466459 |
| Directory | /workspace/1.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.441433131 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 579287586848 ps |
| CPU time | 1045.06 seconds |
| Started | Feb 07 12:36:03 PM PST 24 |
| Finished | Feb 07 12:53:30 PM PST 24 |
| Peak memory | 208468 kb |
| Host | smart-392b8839-8f13-488f-84b7-268d24ce19c7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441433131 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.441433131 |
| Directory | /workspace/1.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.1848248914 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 1490362017647 ps |
| CPU time | 697.65 seconds |
| Started | Feb 07 12:36:40 PM PST 24 |
| Finished | Feb 07 12:48:19 PM PST 24 |
| Peak memory | 182308 kb |
| Host | smart-dbc3903a-d0d5-4c6f-85a6-1030ede55c88 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848248914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_cfg_update_on_fly.1848248914 |
| Directory | /workspace/10.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/10.rv_timer_disabled.2275012771 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 11482826186 ps |
| CPU time | 16.61 seconds |
| Started | Feb 07 12:36:12 PM PST 24 |
| Finished | Feb 07 12:36:31 PM PST 24 |
| Peak memory | 182160 kb |
| Host | smart-e00d6c54-0b97-4526-af6b-f3e21ac42f57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2275012771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2275012771 |
| Directory | /workspace/10.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/10.rv_timer_random.2922090763 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 84838642122 ps |
| CPU time | 71.09 seconds |
| Started | Feb 07 12:36:30 PM PST 24 |
| Finished | Feb 07 12:37:42 PM PST 24 |
| Peak memory | 192696 kb |
| Host | smart-1bc50b87-d57a-48e9-a3d6-749cdd9bd045 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922090763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2922090763 |
| Directory | /workspace/10.rv_timer_random/latest |
| Test location | /workspace/coverage/default/10.rv_timer_stress_all.697201995 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 411535646610 ps |
| CPU time | 542.8 seconds |
| Started | Feb 07 12:36:07 PM PST 24 |
| Finished | Feb 07 12:45:11 PM PST 24 |
| Peak memory | 190468 kb |
| Host | smart-fe888fc8-9036-4a10-9b88-b9569372e3a1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697201995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all. 697201995 |
| Directory | /workspace/10.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.1656715529 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 112314032671 ps |
| CPU time | 260.29 seconds |
| Started | Feb 07 12:36:03 PM PST 24 |
| Finished | Feb 07 12:40:25 PM PST 24 |
| Peak memory | 205320 kb |
| Host | smart-283a8fb6-acba-474e-9b58-5a2de69a82ad |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656715529 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.1656715529 |
| Directory | /workspace/10.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/100.rv_timer_random.583753383 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 77580942479 ps |
| CPU time | 70.28 seconds |
| Started | Feb 07 12:36:52 PM PST 24 |
| Finished | Feb 07 12:38:03 PM PST 24 |
| Peak memory | 190472 kb |
| Host | smart-eba2df52-9814-435e-a1be-e7a695e469e4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583753383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.583753383 |
| Directory | /workspace/100.rv_timer_random/latest |
| Test location | /workspace/coverage/default/101.rv_timer_random.1384076572 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 306395228474 ps |
| CPU time | 428.46 seconds |
| Started | Feb 07 12:36:47 PM PST 24 |
| Finished | Feb 07 12:43:56 PM PST 24 |
| Peak memory | 190540 kb |
| Host | smart-f93d9b1f-d443-42ac-92e6-642637135216 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384076572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1384076572 |
| Directory | /workspace/101.rv_timer_random/latest |
| Test location | /workspace/coverage/default/102.rv_timer_random.581534215 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 124798342495 ps |
| CPU time | 101.34 seconds |
| Started | Feb 07 12:36:53 PM PST 24 |
| Finished | Feb 07 12:38:35 PM PST 24 |
| Peak memory | 190568 kb |
| Host | smart-f6a735e1-fb62-45b6-8199-952d0e311563 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581534215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.581534215 |
| Directory | /workspace/102.rv_timer_random/latest |
| Test location | /workspace/coverage/default/105.rv_timer_random.980839253 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 1251009491477 ps |
| CPU time | 1247.97 seconds |
| Started | Feb 07 12:36:38 PM PST 24 |
| Finished | Feb 07 12:57:27 PM PST 24 |
| Peak memory | 190532 kb |
| Host | smart-926efd2b-40bc-49bf-bf96-dea470e1ae4d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980839253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.980839253 |
| Directory | /workspace/105.rv_timer_random/latest |
| Test location | /workspace/coverage/default/108.rv_timer_random.3812722211 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 212747230430 ps |
| CPU time | 105.61 seconds |
| Started | Feb 07 12:36:43 PM PST 24 |
| Finished | Feb 07 12:38:30 PM PST 24 |
| Peak memory | 190552 kb |
| Host | smart-bf1fb00e-0c65-46d8-aec8-528ce707f388 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812722211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3812722211 |
| Directory | /workspace/108.rv_timer_random/latest |
| Test location | /workspace/coverage/default/11.rv_timer_disabled.2554185210 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 227132775029 ps |
| CPU time | 88.24 seconds |
| Started | Feb 07 12:36:07 PM PST 24 |
| Finished | Feb 07 12:37:37 PM PST 24 |
| Peak memory | 182468 kb |
| Host | smart-d13cae23-1850-4be7-8142-1b2a2dd8980c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2554185210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2554185210 |
| Directory | /workspace/11.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/11.rv_timer_random_reset.478450098 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 58040736533 ps |
| CPU time | 330.47 seconds |
| Started | Feb 07 12:36:15 PM PST 24 |
| Finished | Feb 07 12:41:48 PM PST 24 |
| Peak memory | 182360 kb |
| Host | smart-2f020e15-120c-4a69-8ad4-ab2bbb703bd9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=478450098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.478450098 |
| Directory | /workspace/11.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.36331523 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 231349806652 ps |
| CPU time | 829.25 seconds |
| Started | Feb 07 12:36:15 PM PST 24 |
| Finished | Feb 07 12:50:07 PM PST 24 |
| Peak memory | 208564 kb |
| Host | smart-7749a097-f72d-42f5-8a9d-47a2faac5bad |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36331523 -assert nopos tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.36331523 |
| Directory | /workspace/11.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/110.rv_timer_random.3549419241 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 209606507508 ps |
| CPU time | 643.93 seconds |
| Started | Feb 07 12:36:54 PM PST 24 |
| Finished | Feb 07 12:47:39 PM PST 24 |
| Peak memory | 190576 kb |
| Host | smart-2e509c71-f320-4097-bf13-a58a233ffaa2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549419241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3549419241 |
| Directory | /workspace/110.rv_timer_random/latest |
| Test location | /workspace/coverage/default/111.rv_timer_random.203555601 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 478041802943 ps |
| CPU time | 547.19 seconds |
| Started | Feb 07 12:36:48 PM PST 24 |
| Finished | Feb 07 12:45:56 PM PST 24 |
| Peak memory | 190600 kb |
| Host | smart-e3fb6c91-7fe9-4087-9820-040985681f1b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203555601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.203555601 |
| Directory | /workspace/111.rv_timer_random/latest |
| Test location | /workspace/coverage/default/112.rv_timer_random.1749542665 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 50777758525 ps |
| CPU time | 76.76 seconds |
| Started | Feb 07 12:36:49 PM PST 24 |
| Finished | Feb 07 12:38:06 PM PST 24 |
| Peak memory | 182304 kb |
| Host | smart-b88e0c46-9cdf-45dd-81d9-fb21c7495cbd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749542665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1749542665 |
| Directory | /workspace/112.rv_timer_random/latest |
| Test location | /workspace/coverage/default/113.rv_timer_random.2978329583 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 111669223448 ps |
| CPU time | 49.98 seconds |
| Started | Feb 07 12:36:50 PM PST 24 |
| Finished | Feb 07 12:37:41 PM PST 24 |
| Peak memory | 182460 kb |
| Host | smart-b504dea7-44af-4bb1-af0a-1e8a555ffeab |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978329583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2978329583 |
| Directory | /workspace/113.rv_timer_random/latest |
| Test location | /workspace/coverage/default/114.rv_timer_random.2108392076 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 439594493268 ps |
| CPU time | 184.79 seconds |
| Started | Feb 07 12:36:45 PM PST 24 |
| Finished | Feb 07 12:39:51 PM PST 24 |
| Peak memory | 190544 kb |
| Host | smart-7e83b3d6-2331-4493-8362-feb738ca6c4a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108392076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2108392076 |
| Directory | /workspace/114.rv_timer_random/latest |
| Test location | /workspace/coverage/default/117.rv_timer_random.3524310062 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 42129466654 ps |
| CPU time | 73.48 seconds |
| Started | Feb 07 12:36:46 PM PST 24 |
| Finished | Feb 07 12:38:00 PM PST 24 |
| Peak memory | 190744 kb |
| Host | smart-d0da6023-a932-4e81-adb8-326ad7fd9b25 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524310062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3524310062 |
| Directory | /workspace/117.rv_timer_random/latest |
| Test location | /workspace/coverage/default/119.rv_timer_random.4177747890 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 98578425338 ps |
| CPU time | 163.59 seconds |
| Started | Feb 07 12:36:44 PM PST 24 |
| Finished | Feb 07 12:39:29 PM PST 24 |
| Peak memory | 190540 kb |
| Host | smart-e3b7f617-e923-4a63-9997-8722b0793516 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177747890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.4177747890 |
| Directory | /workspace/119.rv_timer_random/latest |
| Test location | /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.107664302 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 66540441244 ps |
| CPU time | 40.55 seconds |
| Started | Feb 07 12:36:09 PM PST 24 |
| Finished | Feb 07 12:36:54 PM PST 24 |
| Peak memory | 182324 kb |
| Host | smart-83cbe348-6bc6-4656-8a19-5b26dc10767a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107664302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.rv_timer_cfg_update_on_fly.107664302 |
| Directory | /workspace/12.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/12.rv_timer_disabled.3397824970 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 54185208125 ps |
| CPU time | 87.32 seconds |
| Started | Feb 07 12:36:12 PM PST 24 |
| Finished | Feb 07 12:37:41 PM PST 24 |
| Peak memory | 182320 kb |
| Host | smart-54dbfc4c-a11f-44e5-ad7a-8946606bb855 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3397824970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3397824970 |
| Directory | /workspace/12.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/12.rv_timer_random_reset.304291188 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 224311425499 ps |
| CPU time | 99.75 seconds |
| Started | Feb 07 12:36:16 PM PST 24 |
| Finished | Feb 07 12:37:57 PM PST 24 |
| Peak memory | 190580 kb |
| Host | smart-abc8d3cb-b0ce-4075-9c80-5768dafd1ded |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=304291188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.304291188 |
| Directory | /workspace/12.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/120.rv_timer_random.3372085533 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 302236049813 ps |
| CPU time | 1005.91 seconds |
| Started | Feb 07 12:36:44 PM PST 24 |
| Finished | Feb 07 12:53:31 PM PST 24 |
| Peak memory | 190500 kb |
| Host | smart-fa329bd8-19f7-4312-a351-6c26734bc53e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372085533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3372085533 |
| Directory | /workspace/120.rv_timer_random/latest |
| Test location | /workspace/coverage/default/121.rv_timer_random.2162746424 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 325150549778 ps |
| CPU time | 459.91 seconds |
| Started | Feb 07 12:36:42 PM PST 24 |
| Finished | Feb 07 12:44:23 PM PST 24 |
| Peak memory | 190560 kb |
| Host | smart-70b13bf9-2d95-4685-8915-98d55c9a6ed6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162746424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2162746424 |
| Directory | /workspace/121.rv_timer_random/latest |
| Test location | /workspace/coverage/default/122.rv_timer_random.1499447758 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 595152395458 ps |
| CPU time | 2292.39 seconds |
| Started | Feb 07 12:36:50 PM PST 24 |
| Finished | Feb 07 01:15:03 PM PST 24 |
| Peak memory | 190616 kb |
| Host | smart-686c7953-2a91-4eac-a4b8-549e3f3c69c5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499447758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.1499447758 |
| Directory | /workspace/122.rv_timer_random/latest |
| Test location | /workspace/coverage/default/123.rv_timer_random.1999787935 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 1195709747463 ps |
| CPU time | 467.99 seconds |
| Started | Feb 07 12:36:53 PM PST 24 |
| Finished | Feb 07 12:44:42 PM PST 24 |
| Peak memory | 193700 kb |
| Host | smart-6a633dfa-780c-4820-b3e4-8b8f933f5942 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999787935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1999787935 |
| Directory | /workspace/123.rv_timer_random/latest |
| Test location | /workspace/coverage/default/125.rv_timer_random.1957906468 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 15573397316 ps |
| CPU time | 10.58 seconds |
| Started | Feb 07 12:36:38 PM PST 24 |
| Finished | Feb 07 12:36:49 PM PST 24 |
| Peak memory | 182356 kb |
| Host | smart-0d38a560-486c-4b31-bb40-7f0a811d5b75 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957906468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1957906468 |
| Directory | /workspace/125.rv_timer_random/latest |
| Test location | /workspace/coverage/default/127.rv_timer_random.3457115763 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 115891161966 ps |
| CPU time | 318.62 seconds |
| Started | Feb 07 12:36:42 PM PST 24 |
| Finished | Feb 07 12:42:01 PM PST 24 |
| Peak memory | 190560 kb |
| Host | smart-1e3a7f98-faca-4c41-8c15-b40bb1318f78 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457115763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3457115763 |
| Directory | /workspace/127.rv_timer_random/latest |
| Test location | /workspace/coverage/default/129.rv_timer_random.1299852461 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 121975586062 ps |
| CPU time | 1234.69 seconds |
| Started | Feb 07 12:36:55 PM PST 24 |
| Finished | Feb 07 12:57:31 PM PST 24 |
| Peak memory | 190524 kb |
| Host | smart-af2a738c-5c56-4b68-9905-1fc34430420e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299852461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1299852461 |
| Directory | /workspace/129.rv_timer_random/latest |
| Test location | /workspace/coverage/default/13.rv_timer_disabled.1971509333 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 36774331843 ps |
| CPU time | 56.61 seconds |
| Started | Feb 07 12:36:25 PM PST 24 |
| Finished | Feb 07 12:37:23 PM PST 24 |
| Peak memory | 182292 kb |
| Host | smart-c3bd3025-c3a8-465a-90be-c5ec064e61cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1971509333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1971509333 |
| Directory | /workspace/13.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/13.rv_timer_random.322777680 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 385234340176 ps |
| CPU time | 609.63 seconds |
| Started | Feb 07 12:36:18 PM PST 24 |
| Finished | Feb 07 12:46:29 PM PST 24 |
| Peak memory | 190516 kb |
| Host | smart-f1d7c17b-62bd-414a-821c-94a06d9e0104 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322777680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.322777680 |
| Directory | /workspace/13.rv_timer_random/latest |
| Test location | /workspace/coverage/default/13.rv_timer_random_reset.1232898203 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 2211909693 ps |
| CPU time | 3.15 seconds |
| Started | Feb 07 12:36:25 PM PST 24 |
| Finished | Feb 07 12:36:29 PM PST 24 |
| Peak memory | 190560 kb |
| Host | smart-aab59b50-be9a-497e-bff5-30441cdac670 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1232898203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1232898203 |
| Directory | /workspace/13.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/13.rv_timer_stress_all.3837585300 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 423104387696 ps |
| CPU time | 1004.96 seconds |
| Started | Feb 07 12:36:21 PM PST 24 |
| Finished | Feb 07 12:53:06 PM PST 24 |
| Peak memory | 190520 kb |
| Host | smart-17d8f89d-f9cf-4782-8fde-1347e06da966 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837585300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all .3837585300 |
| Directory | /workspace/13.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.3997160333 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 346156593581 ps |
| CPU time | 253.25 seconds |
| Started | Feb 07 12:36:27 PM PST 24 |
| Finished | Feb 07 12:40:41 PM PST 24 |
| Peak memory | 205268 kb |
| Host | smart-ade71c2a-01b8-4737-b310-e3d7cfc4a370 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997160333 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.3997160333 |
| Directory | /workspace/13.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/130.rv_timer_random.296077628 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 517394727732 ps |
| CPU time | 112.11 seconds |
| Started | Feb 07 12:36:52 PM PST 24 |
| Finished | Feb 07 12:38:45 PM PST 24 |
| Peak memory | 182400 kb |
| Host | smart-502904a4-723c-48be-9ace-9b81f50b62c6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296077628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.296077628 |
| Directory | /workspace/130.rv_timer_random/latest |
| Test location | /workspace/coverage/default/131.rv_timer_random.2260087914 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 81537481707 ps |
| CPU time | 188.36 seconds |
| Started | Feb 07 12:36:59 PM PST 24 |
| Finished | Feb 07 12:40:08 PM PST 24 |
| Peak memory | 193768 kb |
| Host | smart-7842ec80-d039-477f-8594-6498190ca0f3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260087914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2260087914 |
| Directory | /workspace/131.rv_timer_random/latest |
| Test location | /workspace/coverage/default/132.rv_timer_random.1951609300 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 481949650785 ps |
| CPU time | 717.51 seconds |
| Started | Feb 07 12:36:56 PM PST 24 |
| Finished | Feb 07 12:48:54 PM PST 24 |
| Peak memory | 190572 kb |
| Host | smart-7e15f148-ead5-4d79-ba2f-2e654214e31b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951609300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1951609300 |
| Directory | /workspace/132.rv_timer_random/latest |
| Test location | /workspace/coverage/default/133.rv_timer_random.3378901463 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 543863342578 ps |
| CPU time | 571.41 seconds |
| Started | Feb 07 12:37:01 PM PST 24 |
| Finished | Feb 07 12:46:34 PM PST 24 |
| Peak memory | 190540 kb |
| Host | smart-767780b3-5c66-4c2f-9b80-4931cc6849f4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378901463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3378901463 |
| Directory | /workspace/133.rv_timer_random/latest |
| Test location | /workspace/coverage/default/134.rv_timer_random.3806472999 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 7374449786 ps |
| CPU time | 27.7 seconds |
| Started | Feb 07 12:36:58 PM PST 24 |
| Finished | Feb 07 12:37:27 PM PST 24 |
| Peak memory | 192588 kb |
| Host | smart-bf0bd912-1917-4d11-b6bd-2ed03f72c7dc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806472999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3806472999 |
| Directory | /workspace/134.rv_timer_random/latest |
| Test location | /workspace/coverage/default/135.rv_timer_random.3848801746 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 30078394097 ps |
| CPU time | 47.46 seconds |
| Started | Feb 07 12:37:01 PM PST 24 |
| Finished | Feb 07 12:37:50 PM PST 24 |
| Peak memory | 182352 kb |
| Host | smart-07fc74c2-a149-4567-ba8e-fdaccdc1ff44 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848801746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3848801746 |
| Directory | /workspace/135.rv_timer_random/latest |
| Test location | /workspace/coverage/default/137.rv_timer_random.200837212 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 46394165282 ps |
| CPU time | 86.43 seconds |
| Started | Feb 07 12:37:01 PM PST 24 |
| Finished | Feb 07 12:38:29 PM PST 24 |
| Peak memory | 182308 kb |
| Host | smart-f6542939-397b-4c3b-b7c9-3eb20c024101 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200837212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.200837212 |
| Directory | /workspace/137.rv_timer_random/latest |
| Test location | /workspace/coverage/default/138.rv_timer_random.2975271948 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 3258526707260 ps |
| CPU time | 485.7 seconds |
| Started | Feb 07 12:36:52 PM PST 24 |
| Finished | Feb 07 12:44:59 PM PST 24 |
| Peak memory | 190548 kb |
| Host | smart-ef27d727-b4b0-4661-9923-3570697e7ffe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975271948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2975271948 |
| Directory | /workspace/138.rv_timer_random/latest |
| Test location | /workspace/coverage/default/139.rv_timer_random.2457668847 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 212115239662 ps |
| CPU time | 702.37 seconds |
| Started | Feb 07 12:36:51 PM PST 24 |
| Finished | Feb 07 12:48:34 PM PST 24 |
| Peak memory | 190540 kb |
| Host | smart-12572029-76d6-47b0-97a7-d190afabadc3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457668847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2457668847 |
| Directory | /workspace/139.rv_timer_random/latest |
| Test location | /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.1396346605 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 939020002428 ps |
| CPU time | 964.88 seconds |
| Started | Feb 07 12:36:33 PM PST 24 |
| Finished | Feb 07 12:52:39 PM PST 24 |
| Peak memory | 182244 kb |
| Host | smart-879539fd-8f40-4af4-b1bf-198f2129a479 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396346605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.1396346605 |
| Directory | /workspace/14.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/14.rv_timer_disabled.2299227082 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 424660740092 ps |
| CPU time | 176.4 seconds |
| Started | Feb 07 12:36:16 PM PST 24 |
| Finished | Feb 07 12:39:14 PM PST 24 |
| Peak memory | 182352 kb |
| Host | smart-11b9bffe-7a51-4347-a7f3-5e3e6effbb82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2299227082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2299227082 |
| Directory | /workspace/14.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/14.rv_timer_random.3861259551 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 120281702294 ps |
| CPU time | 1873.53 seconds |
| Started | Feb 07 12:36:45 PM PST 24 |
| Finished | Feb 07 01:08:00 PM PST 24 |
| Peak memory | 190524 kb |
| Host | smart-fe5e8ae1-9e4f-4434-93ee-f17610c54c5b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861259551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3861259551 |
| Directory | /workspace/14.rv_timer_random/latest |
| Test location | /workspace/coverage/default/14.rv_timer_stress_all.510564347 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 174905181238 ps |
| CPU time | 253.78 seconds |
| Started | Feb 07 12:36:18 PM PST 24 |
| Finished | Feb 07 12:40:33 PM PST 24 |
| Peak memory | 194992 kb |
| Host | smart-44dacad6-9b61-4140-825a-af42cec66eee |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510564347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all. 510564347 |
| Directory | /workspace/14.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/140.rv_timer_random.1021231590 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 46036533680 ps |
| CPU time | 70.22 seconds |
| Started | Feb 07 12:36:57 PM PST 24 |
| Finished | Feb 07 12:38:09 PM PST 24 |
| Peak memory | 190628 kb |
| Host | smart-fd31f873-331e-47cc-a457-f1d2103dc76b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021231590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1021231590 |
| Directory | /workspace/140.rv_timer_random/latest |
| Test location | /workspace/coverage/default/142.rv_timer_random.630421297 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 89131076989 ps |
| CPU time | 1036.07 seconds |
| Started | Feb 07 12:36:43 PM PST 24 |
| Finished | Feb 07 12:54:00 PM PST 24 |
| Peak memory | 190536 kb |
| Host | smart-c0ccabc9-a1cf-41ec-be75-c52d79af61f3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630421297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.630421297 |
| Directory | /workspace/142.rv_timer_random/latest |
| Test location | /workspace/coverage/default/143.rv_timer_random.514516776 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 927684985216 ps |
| CPU time | 233.9 seconds |
| Started | Feb 07 12:36:55 PM PST 24 |
| Finished | Feb 07 12:40:49 PM PST 24 |
| Peak memory | 190584 kb |
| Host | smart-23e9ef84-45b1-4791-92da-3602992a82e6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514516776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.514516776 |
| Directory | /workspace/143.rv_timer_random/latest |
| Test location | /workspace/coverage/default/144.rv_timer_random.1839597171 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 151348994288 ps |
| CPU time | 79.43 seconds |
| Started | Feb 07 12:37:02 PM PST 24 |
| Finished | Feb 07 12:38:22 PM PST 24 |
| Peak memory | 182420 kb |
| Host | smart-9eb635ea-f20f-49c7-bbca-c3f5523b768d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839597171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1839597171 |
| Directory | /workspace/144.rv_timer_random/latest |
| Test location | /workspace/coverage/default/147.rv_timer_random.1884884019 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 383130262643 ps |
| CPU time | 1695.07 seconds |
| Started | Feb 07 12:36:55 PM PST 24 |
| Finished | Feb 07 01:05:11 PM PST 24 |
| Peak memory | 190516 kb |
| Host | smart-7131a0e3-b8d2-44a0-9edc-18cfd9a41e21 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884884019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1884884019 |
| Directory | /workspace/147.rv_timer_random/latest |
| Test location | /workspace/coverage/default/148.rv_timer_random.3290282640 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 228527476728 ps |
| CPU time | 236.96 seconds |
| Started | Feb 07 12:37:02 PM PST 24 |
| Finished | Feb 07 12:41:00 PM PST 24 |
| Peak memory | 190572 kb |
| Host | smart-a268014a-0ae7-42d4-8325-4cfccf34e905 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290282640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3290282640 |
| Directory | /workspace/148.rv_timer_random/latest |
| Test location | /workspace/coverage/default/149.rv_timer_random.4159807200 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 217577971113 ps |
| CPU time | 272.51 seconds |
| Started | Feb 07 12:36:54 PM PST 24 |
| Finished | Feb 07 12:41:27 PM PST 24 |
| Peak memory | 190744 kb |
| Host | smart-ae346937-c477-418d-af49-2f61f4da3cec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159807200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.4159807200 |
| Directory | /workspace/149.rv_timer_random/latest |
| Test location | /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1256528899 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 9913848814 ps |
| CPU time | 19.71 seconds |
| Started | Feb 07 12:36:13 PM PST 24 |
| Finished | Feb 07 12:36:35 PM PST 24 |
| Peak memory | 182448 kb |
| Host | smart-3be5c9f5-70e7-4763-9665-1a0f887eb0d4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256528899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.1256528899 |
| Directory | /workspace/15.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/15.rv_timer_disabled.461058967 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 166433166996 ps |
| CPU time | 75.14 seconds |
| Started | Feb 07 12:36:22 PM PST 24 |
| Finished | Feb 07 12:37:39 PM PST 24 |
| Peak memory | 182380 kb |
| Host | smart-b7f91b0c-bd1b-49f9-bf49-4ddc5e82884c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=461058967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.461058967 |
| Directory | /workspace/15.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/15.rv_timer_random_reset.1137637848 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 195592224524 ps |
| CPU time | 1679.27 seconds |
| Started | Feb 07 12:36:11 PM PST 24 |
| Finished | Feb 07 01:04:13 PM PST 24 |
| Peak memory | 190504 kb |
| Host | smart-eb25c7aa-b8fa-4430-bf10-e419e85aed57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1137637848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1137637848 |
| Directory | /workspace/15.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.2838083016 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 408288803489 ps |
| CPU time | 1252.01 seconds |
| Started | Feb 07 12:36:05 PM PST 24 |
| Finished | Feb 07 12:56:58 PM PST 24 |
| Peak memory | 213468 kb |
| Host | smart-ef57e4de-f7df-4332-bf40-8ef08b7dba63 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838083016 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.2838083016 |
| Directory | /workspace/15.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/150.rv_timer_random.563004664 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 382868490314 ps |
| CPU time | 202.91 seconds |
| Started | Feb 07 12:36:51 PM PST 24 |
| Finished | Feb 07 12:40:15 PM PST 24 |
| Peak memory | 190508 kb |
| Host | smart-6e05336e-df38-4062-82aa-1b2c0f265fb0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563004664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.563004664 |
| Directory | /workspace/150.rv_timer_random/latest |
| Test location | /workspace/coverage/default/152.rv_timer_random.639398291 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 136527913274 ps |
| CPU time | 681.79 seconds |
| Started | Feb 07 12:36:51 PM PST 24 |
| Finished | Feb 07 12:48:14 PM PST 24 |
| Peak memory | 192864 kb |
| Host | smart-06a6a29f-3640-45c0-a732-a4e0e4a879ed |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639398291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.639398291 |
| Directory | /workspace/152.rv_timer_random/latest |
| Test location | /workspace/coverage/default/153.rv_timer_random.2240548394 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 129809286776 ps |
| CPU time | 282.34 seconds |
| Started | Feb 07 12:36:50 PM PST 24 |
| Finished | Feb 07 12:41:33 PM PST 24 |
| Peak memory | 194344 kb |
| Host | smart-6fe14d1a-7b60-4a72-9c41-0fd0a00fc381 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240548394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2240548394 |
| Directory | /workspace/153.rv_timer_random/latest |
| Test location | /workspace/coverage/default/154.rv_timer_random.1489163839 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 107851831670 ps |
| CPU time | 420.95 seconds |
| Started | Feb 07 12:36:50 PM PST 24 |
| Finished | Feb 07 12:43:52 PM PST 24 |
| Peak memory | 190528 kb |
| Host | smart-45dcfc0e-81b3-48c9-9f8b-b1d3bc8d916a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489163839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1489163839 |
| Directory | /workspace/154.rv_timer_random/latest |
| Test location | /workspace/coverage/default/155.rv_timer_random.4162581589 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 37622989242 ps |
| CPU time | 66.72 seconds |
| Started | Feb 07 12:37:02 PM PST 24 |
| Finished | Feb 07 12:38:10 PM PST 24 |
| Peak memory | 190524 kb |
| Host | smart-813a9efa-0071-46ef-a0db-649ac8de2aa4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162581589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.4162581589 |
| Directory | /workspace/155.rv_timer_random/latest |
| Test location | /workspace/coverage/default/156.rv_timer_random.1058633315 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 152333309802 ps |
| CPU time | 814.58 seconds |
| Started | Feb 07 12:36:50 PM PST 24 |
| Finished | Feb 07 12:50:26 PM PST 24 |
| Peak memory | 190532 kb |
| Host | smart-ae10fbb7-1780-4abf-a2fa-d69d1a054783 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058633315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1058633315 |
| Directory | /workspace/156.rv_timer_random/latest |
| Test location | /workspace/coverage/default/157.rv_timer_random.1364019661 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 57677897044 ps |
| CPU time | 1015.14 seconds |
| Started | Feb 07 12:36:55 PM PST 24 |
| Finished | Feb 07 12:53:51 PM PST 24 |
| Peak memory | 182356 kb |
| Host | smart-e7c10021-8505-481e-8655-665354b4e6de |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364019661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1364019661 |
| Directory | /workspace/157.rv_timer_random/latest |
| Test location | /workspace/coverage/default/158.rv_timer_random.2369701728 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 11827530636 ps |
| CPU time | 19.67 seconds |
| Started | Feb 07 12:36:55 PM PST 24 |
| Finished | Feb 07 12:37:16 PM PST 24 |
| Peak memory | 190612 kb |
| Host | smart-66c6a520-b326-4ca7-8afc-c52ca810bad6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369701728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2369701728 |
| Directory | /workspace/158.rv_timer_random/latest |
| Test location | /workspace/coverage/default/159.rv_timer_random.1351702897 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 798106605685 ps |
| CPU time | 1710.19 seconds |
| Started | Feb 07 12:36:50 PM PST 24 |
| Finished | Feb 07 01:05:21 PM PST 24 |
| Peak memory | 190528 kb |
| Host | smart-a85dabad-5a5b-4fda-beb3-b10be475db9c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351702897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1351702897 |
| Directory | /workspace/159.rv_timer_random/latest |
| Test location | /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1707062937 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 354626677006 ps |
| CPU time | 690.57 seconds |
| Started | Feb 07 12:36:11 PM PST 24 |
| Finished | Feb 07 12:47:45 PM PST 24 |
| Peak memory | 182276 kb |
| Host | smart-b6462482-523c-47b9-aa7c-0648c324a91a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707062937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.1707062937 |
| Directory | /workspace/16.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/16.rv_timer_disabled.3805794341 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 161325021697 ps |
| CPU time | 248.8 seconds |
| Started | Feb 07 12:36:06 PM PST 24 |
| Finished | Feb 07 12:40:16 PM PST 24 |
| Peak memory | 182240 kb |
| Host | smart-cfe1cee8-30aa-4dec-93c8-528c01bb92bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3805794341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3805794341 |
| Directory | /workspace/16.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/16.rv_timer_random.3125267033 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 62672544106 ps |
| CPU time | 110.55 seconds |
| Started | Feb 07 12:36:13 PM PST 24 |
| Finished | Feb 07 12:38:06 PM PST 24 |
| Peak memory | 189840 kb |
| Host | smart-be671150-4553-433a-880f-0a57053b6798 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125267033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3125267033 |
| Directory | /workspace/16.rv_timer_random/latest |
| Test location | /workspace/coverage/default/16.rv_timer_random_reset.3486041691 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 20915255 ps |
| CPU time | 0.54 seconds |
| Started | Feb 07 12:36:11 PM PST 24 |
| Finished | Feb 07 12:36:14 PM PST 24 |
| Peak memory | 182204 kb |
| Host | smart-64300d36-a988-4886-aba9-9ce4c9cb912d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3486041691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.3486041691 |
| Directory | /workspace/16.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/16.rv_timer_stress_all.4126535151 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 590677692662 ps |
| CPU time | 228.66 seconds |
| Started | Feb 07 12:36:11 PM PST 24 |
| Finished | Feb 07 12:40:03 PM PST 24 |
| Peak memory | 190516 kb |
| Host | smart-990c05cb-feb7-43da-841a-d2f483c2fb3a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126535151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all .4126535151 |
| Directory | /workspace/16.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.3077457503 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 74566279675 ps |
| CPU time | 437.69 seconds |
| Started | Feb 07 12:36:12 PM PST 24 |
| Finished | Feb 07 12:43:32 PM PST 24 |
| Peak memory | 205284 kb |
| Host | smart-7bc93a1a-8a7c-42f5-848e-855f5bb754d0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077457503 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.3077457503 |
| Directory | /workspace/16.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/160.rv_timer_random.775594120 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 85339152630 ps |
| CPU time | 365.46 seconds |
| Started | Feb 07 12:36:52 PM PST 24 |
| Finished | Feb 07 12:42:58 PM PST 24 |
| Peak memory | 190516 kb |
| Host | smart-60b4f5a1-c8e0-4a21-b3a0-314bfe43e02a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775594120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.775594120 |
| Directory | /workspace/160.rv_timer_random/latest |
| Test location | /workspace/coverage/default/161.rv_timer_random.1928542506 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 87727981734 ps |
| CPU time | 148.4 seconds |
| Started | Feb 07 12:36:57 PM PST 24 |
| Finished | Feb 07 12:39:27 PM PST 24 |
| Peak memory | 182372 kb |
| Host | smart-35487e05-5693-4627-83af-85c7f6cdf4c9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928542506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1928542506 |
| Directory | /workspace/161.rv_timer_random/latest |
| Test location | /workspace/coverage/default/162.rv_timer_random.3305423814 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 168960839245 ps |
| CPU time | 916.56 seconds |
| Started | Feb 07 12:36:55 PM PST 24 |
| Finished | Feb 07 12:52:13 PM PST 24 |
| Peak memory | 190580 kb |
| Host | smart-a6dfa765-0b51-4e2e-8752-8b2452c974fe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305423814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3305423814 |
| Directory | /workspace/162.rv_timer_random/latest |
| Test location | /workspace/coverage/default/163.rv_timer_random.1379651915 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 5328824308 ps |
| CPU time | 2.16 seconds |
| Started | Feb 07 12:36:48 PM PST 24 |
| Finished | Feb 07 12:36:51 PM PST 24 |
| Peak memory | 182200 kb |
| Host | smart-b8b9136f-fea2-42df-a0ed-f153e87696b2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379651915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1379651915 |
| Directory | /workspace/163.rv_timer_random/latest |
| Test location | /workspace/coverage/default/164.rv_timer_random.1801265225 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 103803476535 ps |
| CPU time | 87.94 seconds |
| Started | Feb 07 12:37:00 PM PST 24 |
| Finished | Feb 07 12:38:30 PM PST 24 |
| Peak memory | 182336 kb |
| Host | smart-51c38a1b-a248-43d9-98e0-635584151165 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801265225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1801265225 |
| Directory | /workspace/164.rv_timer_random/latest |
| Test location | /workspace/coverage/default/165.rv_timer_random.794871427 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 146051716414 ps |
| CPU time | 645.87 seconds |
| Started | Feb 07 12:36:54 PM PST 24 |
| Finished | Feb 07 12:47:41 PM PST 24 |
| Peak memory | 190568 kb |
| Host | smart-36ae772c-9ff8-454b-b513-ca81885f469a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794871427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.794871427 |
| Directory | /workspace/165.rv_timer_random/latest |
| Test location | /workspace/coverage/default/166.rv_timer_random.1916976502 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 77939959152 ps |
| CPU time | 1501.47 seconds |
| Started | Feb 07 12:36:52 PM PST 24 |
| Finished | Feb 07 01:01:54 PM PST 24 |
| Peak memory | 190536 kb |
| Host | smart-479da3e7-0ac0-49ae-b343-bd0a8b9ba9cc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916976502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1916976502 |
| Directory | /workspace/166.rv_timer_random/latest |
| Test location | /workspace/coverage/default/167.rv_timer_random.1539702505 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 73629968097 ps |
| CPU time | 134.4 seconds |
| Started | Feb 07 12:37:00 PM PST 24 |
| Finished | Feb 07 12:39:16 PM PST 24 |
| Peak memory | 190520 kb |
| Host | smart-9abeb9ff-f59a-4d90-8c0d-6bb3a307f5b9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539702505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1539702505 |
| Directory | /workspace/167.rv_timer_random/latest |
| Test location | /workspace/coverage/default/169.rv_timer_random.3026128840 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 65497572173 ps |
| CPU time | 602.91 seconds |
| Started | Feb 07 12:36:55 PM PST 24 |
| Finished | Feb 07 12:46:58 PM PST 24 |
| Peak memory | 190696 kb |
| Host | smart-355ab23e-cfbc-4b1e-a080-a46678a9ff5a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026128840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3026128840 |
| Directory | /workspace/169.rv_timer_random/latest |
| Test location | /workspace/coverage/default/17.rv_timer_disabled.1850696226 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 471056416852 ps |
| CPU time | 177.78 seconds |
| Started | Feb 07 12:36:11 PM PST 24 |
| Finished | Feb 07 12:39:12 PM PST 24 |
| Peak memory | 182344 kb |
| Host | smart-ff364d8a-af43-438d-a015-627876cf0dce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1850696226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1850696226 |
| Directory | /workspace/17.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/17.rv_timer_random_reset.783188151 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 25712062422 ps |
| CPU time | 130.96 seconds |
| Started | Feb 07 12:36:07 PM PST 24 |
| Finished | Feb 07 12:38:19 PM PST 24 |
| Peak memory | 182348 kb |
| Host | smart-7d682bce-ba83-4a72-9d0c-0f90e90b7bb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=783188151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.783188151 |
| Directory | /workspace/17.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.2774583042 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 402445974945 ps |
| CPU time | 1055.31 seconds |
| Started | Feb 07 12:36:11 PM PST 24 |
| Finished | Feb 07 12:53:49 PM PST 24 |
| Peak memory | 205192 kb |
| Host | smart-685bf4c0-b6a7-4b4e-9b91-1631572d168a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774583042 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.2774583042 |
| Directory | /workspace/17.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/170.rv_timer_random.3755824312 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 73291190800 ps |
| CPU time | 851.45 seconds |
| Started | Feb 07 12:36:55 PM PST 24 |
| Finished | Feb 07 12:51:08 PM PST 24 |
| Peak memory | 194484 kb |
| Host | smart-d70f4cd1-e4e5-499b-89a7-ea0651b5786a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755824312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3755824312 |
| Directory | /workspace/170.rv_timer_random/latest |
| Test location | /workspace/coverage/default/171.rv_timer_random.3848907265 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 464296311116 ps |
| CPU time | 436.67 seconds |
| Started | Feb 07 12:36:55 PM PST 24 |
| Finished | Feb 07 12:44:12 PM PST 24 |
| Peak memory | 190692 kb |
| Host | smart-973b6c36-8546-46be-b947-4b80fddf6c9d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848907265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.3848907265 |
| Directory | /workspace/171.rv_timer_random/latest |
| Test location | /workspace/coverage/default/172.rv_timer_random.1922754260 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 72789708396 ps |
| CPU time | 307.24 seconds |
| Started | Feb 07 12:37:00 PM PST 24 |
| Finished | Feb 07 12:42:09 PM PST 24 |
| Peak memory | 182316 kb |
| Host | smart-3646223d-c03d-4c84-8570-2a9803b6b9ae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922754260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1922754260 |
| Directory | /workspace/172.rv_timer_random/latest |
| Test location | /workspace/coverage/default/173.rv_timer_random.4222391384 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 64143936295 ps |
| CPU time | 109.31 seconds |
| Started | Feb 07 12:36:57 PM PST 24 |
| Finished | Feb 07 12:38:47 PM PST 24 |
| Peak memory | 190528 kb |
| Host | smart-589c0581-bbba-4a58-b086-08517eb7bb78 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222391384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.4222391384 |
| Directory | /workspace/173.rv_timer_random/latest |
| Test location | /workspace/coverage/default/174.rv_timer_random.531584322 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 412577244413 ps |
| CPU time | 224.68 seconds |
| Started | Feb 07 12:37:01 PM PST 24 |
| Finished | Feb 07 12:40:47 PM PST 24 |
| Peak memory | 194020 kb |
| Host | smart-a83ee2d6-6e9b-4237-bbce-252e2dfe00d0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531584322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.531584322 |
| Directory | /workspace/174.rv_timer_random/latest |
| Test location | /workspace/coverage/default/175.rv_timer_random.3953385728 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 21300772588 ps |
| CPU time | 5.05 seconds |
| Started | Feb 07 12:36:59 PM PST 24 |
| Finished | Feb 07 12:37:05 PM PST 24 |
| Peak memory | 182412 kb |
| Host | smart-2eb6b896-7cd2-4c7d-90af-a40294717f6f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953385728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3953385728 |
| Directory | /workspace/175.rv_timer_random/latest |
| Test location | /workspace/coverage/default/176.rv_timer_random.3831688644 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 78701437023 ps |
| CPU time | 89.84 seconds |
| Started | Feb 07 12:37:00 PM PST 24 |
| Finished | Feb 07 12:38:32 PM PST 24 |
| Peak memory | 190476 kb |
| Host | smart-f49baa59-b34c-47fd-945e-6acb545c101a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831688644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3831688644 |
| Directory | /workspace/176.rv_timer_random/latest |
| Test location | /workspace/coverage/default/177.rv_timer_random.2204396896 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 30958034313 ps |
| CPU time | 73.74 seconds |
| Started | Feb 07 12:37:03 PM PST 24 |
| Finished | Feb 07 12:38:18 PM PST 24 |
| Peak memory | 190612 kb |
| Host | smart-f912e362-b6e2-4691-aec8-fe616972237d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204396896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2204396896 |
| Directory | /workspace/177.rv_timer_random/latest |
| Test location | /workspace/coverage/default/178.rv_timer_random.406434159 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 382077519672 ps |
| CPU time | 2020.36 seconds |
| Started | Feb 07 12:37:01 PM PST 24 |
| Finished | Feb 07 01:10:43 PM PST 24 |
| Peak memory | 192716 kb |
| Host | smart-4e9466e5-81d3-4cc7-bfc1-11b7e95b060f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406434159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.406434159 |
| Directory | /workspace/178.rv_timer_random/latest |
| Test location | /workspace/coverage/default/179.rv_timer_random.4217400911 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 31784323782 ps |
| CPU time | 31.39 seconds |
| Started | Feb 07 12:36:56 PM PST 24 |
| Finished | Feb 07 12:37:28 PM PST 24 |
| Peak memory | 182396 kb |
| Host | smart-b5de375d-6328-446b-af8e-5d73215cd7da |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217400911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.4217400911 |
| Directory | /workspace/179.rv_timer_random/latest |
| Test location | /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2306295682 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 18208859454 ps |
| CPU time | 30.24 seconds |
| Started | Feb 07 12:36:07 PM PST 24 |
| Finished | Feb 07 12:36:39 PM PST 24 |
| Peak memory | 182420 kb |
| Host | smart-f236af27-d1b7-4663-ba18-8742d4d34999 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306295682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_cfg_update_on_fly.2306295682 |
| Directory | /workspace/18.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/18.rv_timer_disabled.3995353318 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 19215308486 ps |
| CPU time | 14.4 seconds |
| Started | Feb 07 12:36:13 PM PST 24 |
| Finished | Feb 07 12:36:29 PM PST 24 |
| Peak memory | 182372 kb |
| Host | smart-0504c2ca-b055-4abf-8a13-e6b8fb9bfa00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3995353318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3995353318 |
| Directory | /workspace/18.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/18.rv_timer_random.3160994779 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 477800852706 ps |
| CPU time | 2087.92 seconds |
| Started | Feb 07 12:36:43 PM PST 24 |
| Finished | Feb 07 01:11:32 PM PST 24 |
| Peak memory | 192716 kb |
| Host | smart-a7ede9fa-c69b-4a85-872f-7a0d11d3a083 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160994779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3160994779 |
| Directory | /workspace/18.rv_timer_random/latest |
| Test location | /workspace/coverage/default/18.rv_timer_random_reset.2773339867 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 52404414081 ps |
| CPU time | 83.94 seconds |
| Started | Feb 07 12:36:08 PM PST 24 |
| Finished | Feb 07 12:37:37 PM PST 24 |
| Peak memory | 192368 kb |
| Host | smart-91970ff9-7498-42d7-81c3-b681c4ed8b47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2773339867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2773339867 |
| Directory | /workspace/18.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/18.rv_timer_stress_all.409873065 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 20547973 ps |
| CPU time | 0.54 seconds |
| Started | Feb 07 12:36:05 PM PST 24 |
| Finished | Feb 07 12:36:07 PM PST 24 |
| Peak memory | 181944 kb |
| Host | smart-d0d8c90b-aeaf-4d80-83a0-0a5fc6b3c443 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409873065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all. 409873065 |
| Directory | /workspace/18.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.267387238 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 78537825691 ps |
| CPU time | 755.29 seconds |
| Started | Feb 07 12:36:17 PM PST 24 |
| Finished | Feb 07 12:48:54 PM PST 24 |
| Peak memory | 206204 kb |
| Host | smart-141690a3-f227-4670-9c0a-86a20c0dd7f6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267387238 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.267387238 |
| Directory | /workspace/18.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/181.rv_timer_random.3278484540 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 187097886515 ps |
| CPU time | 603.65 seconds |
| Started | Feb 07 12:37:09 PM PST 24 |
| Finished | Feb 07 12:47:13 PM PST 24 |
| Peak memory | 190520 kb |
| Host | smart-0d500e7d-74ff-4545-9012-2586c900f6a5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278484540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3278484540 |
| Directory | /workspace/181.rv_timer_random/latest |
| Test location | /workspace/coverage/default/182.rv_timer_random.4127048736 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 144244435072 ps |
| CPU time | 227.83 seconds |
| Started | Feb 07 12:37:01 PM PST 24 |
| Finished | Feb 07 12:40:50 PM PST 24 |
| Peak memory | 190576 kb |
| Host | smart-bb00b5e9-3f33-4388-b402-8149dbc81140 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127048736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.4127048736 |
| Directory | /workspace/182.rv_timer_random/latest |
| Test location | /workspace/coverage/default/183.rv_timer_random.1768678847 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 159701247134 ps |
| CPU time | 60.1 seconds |
| Started | Feb 07 12:37:04 PM PST 24 |
| Finished | Feb 07 12:38:05 PM PST 24 |
| Peak memory | 192984 kb |
| Host | smart-fa1c7b34-04e3-4b73-9dcf-8210e8a3a9de |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768678847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1768678847 |
| Directory | /workspace/183.rv_timer_random/latest |
| Test location | /workspace/coverage/default/184.rv_timer_random.2785556991 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 190309579521 ps |
| CPU time | 329.51 seconds |
| Started | Feb 07 12:37:03 PM PST 24 |
| Finished | Feb 07 12:42:34 PM PST 24 |
| Peak memory | 194340 kb |
| Host | smart-ba7d5e0a-34c0-4a81-9488-753693c09de1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785556991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2785556991 |
| Directory | /workspace/184.rv_timer_random/latest |
| Test location | /workspace/coverage/default/185.rv_timer_random.710421792 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 533284374967 ps |
| CPU time | 816.12 seconds |
| Started | Feb 07 12:37:02 PM PST 24 |
| Finished | Feb 07 12:50:40 PM PST 24 |
| Peak memory | 190620 kb |
| Host | smart-66ae0de6-4f59-4909-8934-c44a13ef433a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710421792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.710421792 |
| Directory | /workspace/185.rv_timer_random/latest |
| Test location | /workspace/coverage/default/187.rv_timer_random.1477440102 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 239892735912 ps |
| CPU time | 600.97 seconds |
| Started | Feb 07 12:37:04 PM PST 24 |
| Finished | Feb 07 12:47:06 PM PST 24 |
| Peak memory | 190528 kb |
| Host | smart-71e6c3af-cc3f-40cd-bb6c-99d35f345f0f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477440102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1477440102 |
| Directory | /workspace/187.rv_timer_random/latest |
| Test location | /workspace/coverage/default/188.rv_timer_random.90003891 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 281502563789 ps |
| CPU time | 319.05 seconds |
| Started | Feb 07 12:37:10 PM PST 24 |
| Finished | Feb 07 12:42:30 PM PST 24 |
| Peak memory | 190424 kb |
| Host | smart-47634b74-4a0e-4b7b-9492-2c5dfe451584 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90003891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.90003891 |
| Directory | /workspace/188.rv_timer_random/latest |
| Test location | /workspace/coverage/default/189.rv_timer_random.2618770592 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 244788502519 ps |
| CPU time | 253.58 seconds |
| Started | Feb 07 12:37:10 PM PST 24 |
| Finished | Feb 07 12:41:24 PM PST 24 |
| Peak memory | 190424 kb |
| Host | smart-a01a0aa3-cfad-494f-b5ad-26492a1673da |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618770592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2618770592 |
| Directory | /workspace/189.rv_timer_random/latest |
| Test location | /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.1555196468 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 135123888283 ps |
| CPU time | 236.82 seconds |
| Started | Feb 07 12:36:12 PM PST 24 |
| Finished | Feb 07 12:40:11 PM PST 24 |
| Peak memory | 182256 kb |
| Host | smart-d776d742-11a2-45d2-b497-57c964cdff29 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555196468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.1555196468 |
| Directory | /workspace/19.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/19.rv_timer_disabled.2873192995 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 189347136808 ps |
| CPU time | 290.77 seconds |
| Started | Feb 07 12:36:19 PM PST 24 |
| Finished | Feb 07 12:41:11 PM PST 24 |
| Peak memory | 182316 kb |
| Host | smart-e33f8d0c-bd85-4c10-94c4-a2fc3795e99d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2873192995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2873192995 |
| Directory | /workspace/19.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/19.rv_timer_random.3058905797 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 91250719676 ps |
| CPU time | 167.06 seconds |
| Started | Feb 07 12:36:30 PM PST 24 |
| Finished | Feb 07 12:39:19 PM PST 24 |
| Peak memory | 190532 kb |
| Host | smart-5462a5eb-5a7f-4281-938b-92460e483ec3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058905797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3058905797 |
| Directory | /workspace/19.rv_timer_random/latest |
| Test location | /workspace/coverage/default/19.rv_timer_random_reset.1905771635 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 17527160827 ps |
| CPU time | 18.68 seconds |
| Started | Feb 07 12:36:29 PM PST 24 |
| Finished | Feb 07 12:36:49 PM PST 24 |
| Peak memory | 193760 kb |
| Host | smart-a53d8618-e96a-4f72-89f0-20bdb254ce98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1905771635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1905771635 |
| Directory | /workspace/19.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.3133229437 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 19906554887 ps |
| CPU time | 220.74 seconds |
| Started | Feb 07 12:36:40 PM PST 24 |
| Finished | Feb 07 12:40:21 PM PST 24 |
| Peak memory | 197104 kb |
| Host | smart-e1bd4dfb-2669-476c-b442-51bb7904c340 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133229437 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.3133229437 |
| Directory | /workspace/19.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/190.rv_timer_random.1673007951 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 149251602974 ps |
| CPU time | 406.29 seconds |
| Started | Feb 07 12:36:59 PM PST 24 |
| Finished | Feb 07 12:43:46 PM PST 24 |
| Peak memory | 182356 kb |
| Host | smart-a5745ce9-b317-4504-af86-0ddded4544d8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673007951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1673007951 |
| Directory | /workspace/190.rv_timer_random/latest |
| Test location | /workspace/coverage/default/192.rv_timer_random.4217188485 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 898197226302 ps |
| CPU time | 401.61 seconds |
| Started | Feb 07 12:37:11 PM PST 24 |
| Finished | Feb 07 12:43:54 PM PST 24 |
| Peak memory | 190500 kb |
| Host | smart-573494cd-81ff-4529-8272-61aa36e97666 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217188485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.4217188485 |
| Directory | /workspace/192.rv_timer_random/latest |
| Test location | /workspace/coverage/default/193.rv_timer_random.1835559063 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 79514883897 ps |
| CPU time | 187.97 seconds |
| Started | Feb 07 12:37:04 PM PST 24 |
| Finished | Feb 07 12:40:13 PM PST 24 |
| Peak memory | 190552 kb |
| Host | smart-bb16e283-79e9-4373-af3d-3c5c0b14e33f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835559063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1835559063 |
| Directory | /workspace/193.rv_timer_random/latest |
| Test location | /workspace/coverage/default/195.rv_timer_random.869531107 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 2228000578 ps |
| CPU time | 3.76 seconds |
| Started | Feb 07 12:37:09 PM PST 24 |
| Finished | Feb 07 12:37:14 PM PST 24 |
| Peak memory | 182032 kb |
| Host | smart-a680fc46-7861-438a-bd05-302829aeb6cc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869531107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.869531107 |
| Directory | /workspace/195.rv_timer_random/latest |
| Test location | /workspace/coverage/default/197.rv_timer_random.1647981399 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 621804540944 ps |
| CPU time | 103.81 seconds |
| Started | Feb 07 12:37:01 PM PST 24 |
| Finished | Feb 07 12:38:46 PM PST 24 |
| Peak memory | 190548 kb |
| Host | smart-cdafe903-8f60-420e-96a7-c01a363041bf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647981399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1647981399 |
| Directory | /workspace/197.rv_timer_random/latest |
| Test location | /workspace/coverage/default/198.rv_timer_random.3283915724 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 776116534844 ps |
| CPU time | 553.34 seconds |
| Started | Feb 07 12:37:12 PM PST 24 |
| Finished | Feb 07 12:46:27 PM PST 24 |
| Peak memory | 192500 kb |
| Host | smart-f905be07-15e1-4716-a42e-86b3d8167316 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283915724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3283915724 |
| Directory | /workspace/198.rv_timer_random/latest |
| Test location | /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3975256460 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 20254670363 ps |
| CPU time | 37.57 seconds |
| Started | Feb 07 12:36:04 PM PST 24 |
| Finished | Feb 07 12:36:43 PM PST 24 |
| Peak memory | 182288 kb |
| Host | smart-fc29d9d1-0994-4f74-982f-75509a036669 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975256460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_cfg_update_on_fly.3975256460 |
| Directory | /workspace/2.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/2.rv_timer_disabled.425316476 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 130509407863 ps |
| CPU time | 105.57 seconds |
| Started | Feb 07 12:36:01 PM PST 24 |
| Finished | Feb 07 12:37:49 PM PST 24 |
| Peak memory | 182304 kb |
| Host | smart-55b64cca-6a15-4d6d-b528-41af53ec3707 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=425316476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.425316476 |
| Directory | /workspace/2.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/2.rv_timer_random.3435309994 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 26375673049 ps |
| CPU time | 51.54 seconds |
| Started | Feb 07 12:36:05 PM PST 24 |
| Finished | Feb 07 12:36:58 PM PST 24 |
| Peak memory | 182348 kb |
| Host | smart-0798317d-03d2-499e-b0bf-3784fae74b29 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435309994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3435309994 |
| Directory | /workspace/2.rv_timer_random/latest |
| Test location | /workspace/coverage/default/2.rv_timer_random_reset.1922233716 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 643325585153 ps |
| CPU time | 238.36 seconds |
| Started | Feb 07 12:36:06 PM PST 24 |
| Finished | Feb 07 12:40:06 PM PST 24 |
| Peak memory | 193664 kb |
| Host | smart-c1fdf3e3-4717-4c88-8914-cde5b1bd69e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1922233716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1922233716 |
| Directory | /workspace/2.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/2.rv_timer_sec_cm.1421931603 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 654342889 ps |
| CPU time | 0.9 seconds |
| Started | Feb 07 12:36:07 PM PST 24 |
| Finished | Feb 07 12:36:09 PM PST 24 |
| Peak memory | 213868 kb |
| Host | smart-3e7ed225-1ee6-4026-983d-6a22467cf409 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421931603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1421931603 |
| Directory | /workspace/2.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.424979758 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 66392921743 ps |
| CPU time | 634.65 seconds |
| Started | Feb 07 12:36:02 PM PST 24 |
| Finished | Feb 07 12:46:38 PM PST 24 |
| Peak memory | 206720 kb |
| Host | smart-73016c48-4e9c-400e-adcc-8306d1648b7a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424979758 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.424979758 |
| Directory | /workspace/2.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2101093979 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 298245176243 ps |
| CPU time | 577.06 seconds |
| Started | Feb 07 12:36:24 PM PST 24 |
| Finished | Feb 07 12:46:02 PM PST 24 |
| Peak memory | 182324 kb |
| Host | smart-46cfb825-19eb-4649-89cd-a2d4285894ba |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101093979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.2101093979 |
| Directory | /workspace/20.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/20.rv_timer_disabled.216704092 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 166083860421 ps |
| CPU time | 217.28 seconds |
| Started | Feb 07 12:36:17 PM PST 24 |
| Finished | Feb 07 12:39:56 PM PST 24 |
| Peak memory | 182332 kb |
| Host | smart-0e84557e-cfc1-41cb-af28-d397d5d7c467 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=216704092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.216704092 |
| Directory | /workspace/20.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/20.rv_timer_random.3846122697 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 138634091757 ps |
| CPU time | 1431.71 seconds |
| Started | Feb 07 12:36:20 PM PST 24 |
| Finished | Feb 07 01:00:13 PM PST 24 |
| Peak memory | 182348 kb |
| Host | smart-bec543cf-3419-44d6-9ca6-0b3d8ab89a52 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846122697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3846122697 |
| Directory | /workspace/20.rv_timer_random/latest |
| Test location | /workspace/coverage/default/20.rv_timer_random_reset.3976564093 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 83263137705 ps |
| CPU time | 1415 seconds |
| Started | Feb 07 12:36:24 PM PST 24 |
| Finished | Feb 07 01:00:00 PM PST 24 |
| Peak memory | 194236 kb |
| Host | smart-9a80e235-3fd9-4de7-90b2-6f3560eb0e78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3976564093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3976564093 |
| Directory | /workspace/20.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/20.rv_timer_stress_all.924530231 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 37301436523 ps |
| CPU time | 68.25 seconds |
| Started | Feb 07 12:36:13 PM PST 24 |
| Finished | Feb 07 12:37:25 PM PST 24 |
| Peak memory | 182380 kb |
| Host | smart-1b0fa101-1df5-46c1-89ad-29150d5f9f07 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924530231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all. 924530231 |
| Directory | /workspace/20.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.2386940261 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 78441491981 ps |
| CPU time | 637.12 seconds |
| Started | Feb 07 12:36:17 PM PST 24 |
| Finished | Feb 07 12:46:56 PM PST 24 |
| Peak memory | 206248 kb |
| Host | smart-646f14bf-8ed7-4349-8d42-35b2ff822bdf |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386940261 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.2386940261 |
| Directory | /workspace/20.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3040461070 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 3799774498 ps |
| CPU time | 7.6 seconds |
| Started | Feb 07 12:36:44 PM PST 24 |
| Finished | Feb 07 12:36:52 PM PST 24 |
| Peak memory | 182308 kb |
| Host | smart-3e3ee5d1-9185-49af-a270-55fc573f0189 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040461070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_cfg_update_on_fly.3040461070 |
| Directory | /workspace/21.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/21.rv_timer_disabled.4183746921 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 311624434928 ps |
| CPU time | 274.59 seconds |
| Started | Feb 07 12:36:41 PM PST 24 |
| Finished | Feb 07 12:41:17 PM PST 24 |
| Peak memory | 182264 kb |
| Host | smart-ee53fc9f-0d50-49af-8e0c-05de3f19f6c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4183746921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.4183746921 |
| Directory | /workspace/21.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/21.rv_timer_random_reset.3210143579 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 158333298921 ps |
| CPU time | 164.8 seconds |
| Started | Feb 07 12:36:35 PM PST 24 |
| Finished | Feb 07 12:39:21 PM PST 24 |
| Peak memory | 190452 kb |
| Host | smart-5392b288-b988-4aed-b63e-2fc37cde2e05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3210143579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3210143579 |
| Directory | /workspace/21.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.3684471047 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 742693071537 ps |
| CPU time | 1498.26 seconds |
| Started | Feb 07 12:36:43 PM PST 24 |
| Finished | Feb 07 01:01:42 PM PST 24 |
| Peak memory | 212844 kb |
| Host | smart-c033bb1f-5b76-460e-9445-75d1889f5b8a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684471047 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.3684471047 |
| Directory | /workspace/21.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1083637891 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 733943837435 ps |
| CPU time | 265.58 seconds |
| Started | Feb 07 12:36:42 PM PST 24 |
| Finished | Feb 07 12:41:09 PM PST 24 |
| Peak memory | 182336 kb |
| Host | smart-a2d8a0f8-5e55-4753-a808-19329e9dae8c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083637891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_cfg_update_on_fly.1083637891 |
| Directory | /workspace/22.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/22.rv_timer_disabled.3337249783 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 228848820496 ps |
| CPU time | 113.05 seconds |
| Started | Feb 07 12:36:27 PM PST 24 |
| Finished | Feb 07 12:38:22 PM PST 24 |
| Peak memory | 182456 kb |
| Host | smart-55530964-2ccd-45a3-8e40-ce902ad00e3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3337249783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3337249783 |
| Directory | /workspace/22.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/22.rv_timer_random_reset.3131653201 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 3846672223 ps |
| CPU time | 21.1 seconds |
| Started | Feb 07 12:36:49 PM PST 24 |
| Finished | Feb 07 12:37:11 PM PST 24 |
| Peak memory | 190516 kb |
| Host | smart-fcbd818d-f644-4dc5-a8a8-11448a71ab70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3131653201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3131653201 |
| Directory | /workspace/22.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.3663644975 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 434761485627 ps |
| CPU time | 643.41 seconds |
| Started | Feb 07 12:36:32 PM PST 24 |
| Finished | Feb 07 12:47:17 PM PST 24 |
| Peak memory | 213064 kb |
| Host | smart-d965d11a-e202-44c9-86a4-4207f0cf138a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663644975 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.3663644975 |
| Directory | /workspace/22.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/23.rv_timer_disabled.1198570510 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 319598178698 ps |
| CPU time | 54.66 seconds |
| Started | Feb 07 12:36:11 PM PST 24 |
| Finished | Feb 07 12:37:09 PM PST 24 |
| Peak memory | 182324 kb |
| Host | smart-456d0939-f9da-4625-9de9-28335c4dc454 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1198570510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1198570510 |
| Directory | /workspace/23.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/23.rv_timer_random.4163914427 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 697469923727 ps |
| CPU time | 1090.96 seconds |
| Started | Feb 07 12:36:40 PM PST 24 |
| Finished | Feb 07 12:54:53 PM PST 24 |
| Peak memory | 190556 kb |
| Host | smart-bb09ef81-d7b3-4252-a424-ef00e91726dc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163914427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.4163914427 |
| Directory | /workspace/23.rv_timer_random/latest |
| Test location | /workspace/coverage/default/23.rv_timer_random_reset.1594034351 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 482047799041 ps |
| CPU time | 552.56 seconds |
| Started | Feb 07 12:36:24 PM PST 24 |
| Finished | Feb 07 12:45:43 PM PST 24 |
| Peak memory | 190552 kb |
| Host | smart-64d25649-fcb6-4159-868c-c1916fa8b854 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1594034351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1594034351 |
| Directory | /workspace/23.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/23.rv_timer_stress_all.2336417288 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 542177056485 ps |
| CPU time | 1201.18 seconds |
| Started | Feb 07 12:36:42 PM PST 24 |
| Finished | Feb 07 12:56:44 PM PST 24 |
| Peak memory | 190584 kb |
| Host | smart-69799e8d-04e0-47e9-84d0-9029f028cf50 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336417288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all .2336417288 |
| Directory | /workspace/23.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.2600422648 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 256239606916 ps |
| CPU time | 659.92 seconds |
| Started | Feb 07 12:36:30 PM PST 24 |
| Finished | Feb 07 12:47:31 PM PST 24 |
| Peak memory | 207076 kb |
| Host | smart-0bd6b929-d426-460c-b089-447b8c1aa266 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600422648 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.2600422648 |
| Directory | /workspace/23.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.30781426 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 247962057339 ps |
| CPU time | 440.6 seconds |
| Started | Feb 07 12:36:30 PM PST 24 |
| Finished | Feb 07 12:43:52 PM PST 24 |
| Peak memory | 182404 kb |
| Host | smart-eda6a1b0-0c8d-4178-ae65-91c8e6fe75b2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30781426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24 .rv_timer_cfg_update_on_fly.30781426 |
| Directory | /workspace/24.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/24.rv_timer_disabled.3679983091 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 80500143243 ps |
| CPU time | 113.09 seconds |
| Started | Feb 07 12:36:35 PM PST 24 |
| Finished | Feb 07 12:38:29 PM PST 24 |
| Peak memory | 182240 kb |
| Host | smart-231ff154-20f7-4dd8-bd91-3508cbf308a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3679983091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3679983091 |
| Directory | /workspace/24.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/24.rv_timer_random_reset.812799919 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 109396589721 ps |
| CPU time | 525.32 seconds |
| Started | Feb 07 12:36:43 PM PST 24 |
| Finished | Feb 07 12:45:29 PM PST 24 |
| Peak memory | 182316 kb |
| Host | smart-fca8491d-e4be-42a9-a36c-2f0099d47a6a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=812799919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.812799919 |
| Directory | /workspace/24.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/24.rv_timer_stress_all.3407149098 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 856920775837 ps |
| CPU time | 630.68 seconds |
| Started | Feb 07 12:36:42 PM PST 24 |
| Finished | Feb 07 12:47:13 PM PST 24 |
| Peak memory | 190532 kb |
| Host | smart-4f6b45d5-652b-40ed-b8f6-cbc762b6f78f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407149098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all .3407149098 |
| Directory | /workspace/24.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.3564006576 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 645565284229 ps |
| CPU time | 466.74 seconds |
| Started | Feb 07 12:36:47 PM PST 24 |
| Finished | Feb 07 12:44:34 PM PST 24 |
| Peak memory | 182196 kb |
| Host | smart-dd3f5754-d3a6-4d4d-9e0d-59d7d7fbc52e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564006576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_cfg_update_on_fly.3564006576 |
| Directory | /workspace/25.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/25.rv_timer_disabled.805019783 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 454097531886 ps |
| CPU time | 78.24 seconds |
| Started | Feb 07 12:36:28 PM PST 24 |
| Finished | Feb 07 12:37:47 PM PST 24 |
| Peak memory | 182448 kb |
| Host | smart-1dc6a867-08e0-4518-bdeb-1353bf34b48b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=805019783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.805019783 |
| Directory | /workspace/25.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/25.rv_timer_random.3465580902 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 2668866704690 ps |
| CPU time | 811.38 seconds |
| Started | Feb 07 12:36:26 PM PST 24 |
| Finished | Feb 07 12:50:03 PM PST 24 |
| Peak memory | 190596 kb |
| Host | smart-c9d5b338-ad4c-43eb-933f-fe1ffe8adb86 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465580902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3465580902 |
| Directory | /workspace/25.rv_timer_random/latest |
| Test location | /workspace/coverage/default/25.rv_timer_random_reset.4212448529 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 46210472 ps |
| CPU time | 0.53 seconds |
| Started | Feb 07 12:36:22 PM PST 24 |
| Finished | Feb 07 12:36:23 PM PST 24 |
| Peak memory | 182152 kb |
| Host | smart-466b68a5-42be-4695-9830-8fc171013956 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4212448529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.4212448529 |
| Directory | /workspace/25.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.608759896 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 132577969997 ps |
| CPU time | 1084.24 seconds |
| Started | Feb 07 12:36:24 PM PST 24 |
| Finished | Feb 07 12:54:29 PM PST 24 |
| Peak memory | 210836 kb |
| Host | smart-8f315f92-1fb9-4b23-b64e-a902ac5dc2a2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608759896 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.608759896 |
| Directory | /workspace/25.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.2230936701 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 2342999734261 ps |
| CPU time | 813.05 seconds |
| Started | Feb 07 12:36:41 PM PST 24 |
| Finished | Feb 07 12:50:15 PM PST 24 |
| Peak memory | 182320 kb |
| Host | smart-c3a77b68-ec44-4f54-9290-5f1240adc476 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230936701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_cfg_update_on_fly.2230936701 |
| Directory | /workspace/26.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/26.rv_timer_disabled.3648225413 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 319735643994 ps |
| CPU time | 131.97 seconds |
| Started | Feb 07 12:36:42 PM PST 24 |
| Finished | Feb 07 12:38:55 PM PST 24 |
| Peak memory | 182328 kb |
| Host | smart-e537ed8e-4ed1-4d72-8cd2-82103be3dc42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3648225413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3648225413 |
| Directory | /workspace/26.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/26.rv_timer_random.3482615514 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 145752311314 ps |
| CPU time | 127.94 seconds |
| Started | Feb 07 12:36:24 PM PST 24 |
| Finished | Feb 07 12:38:33 PM PST 24 |
| Peak memory | 190572 kb |
| Host | smart-eab622af-e641-4a63-adc7-47096b07127a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482615514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3482615514 |
| Directory | /workspace/26.rv_timer_random/latest |
| Test location | /workspace/coverage/default/26.rv_timer_random_reset.2431092829 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 1812520589 ps |
| CPU time | 1.91 seconds |
| Started | Feb 07 12:36:34 PM PST 24 |
| Finished | Feb 07 12:36:37 PM PST 24 |
| Peak memory | 190604 kb |
| Host | smart-2a301b1a-142d-470a-879d-ea01305e2a4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2431092829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2431092829 |
| Directory | /workspace/26.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.211887989 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 115256659683 ps |
| CPU time | 813.77 seconds |
| Started | Feb 07 12:36:42 PM PST 24 |
| Finished | Feb 07 12:50:17 PM PST 24 |
| Peak memory | 197076 kb |
| Host | smart-bff52b81-5c9a-422a-9bed-7a790d75eaf9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211887989 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.211887989 |
| Directory | /workspace/26.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2154176554 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 1429662370011 ps |
| CPU time | 391.33 seconds |
| Started | Feb 07 12:36:49 PM PST 24 |
| Finished | Feb 07 12:43:21 PM PST 24 |
| Peak memory | 182300 kb |
| Host | smart-fd77da1d-ff19-40e6-a3cd-d076dad0f38d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154176554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.2154176554 |
| Directory | /workspace/27.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/27.rv_timer_disabled.673931461 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 105187405898 ps |
| CPU time | 157.88 seconds |
| Started | Feb 07 12:36:49 PM PST 24 |
| Finished | Feb 07 12:39:28 PM PST 24 |
| Peak memory | 182276 kb |
| Host | smart-e4fe6261-d9aa-44c8-a4c4-d9ff88ad1e76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=673931461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.673931461 |
| Directory | /workspace/27.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/27.rv_timer_random.2888903400 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 130860813266 ps |
| CPU time | 82.16 seconds |
| Started | Feb 07 12:36:49 PM PST 24 |
| Finished | Feb 07 12:38:12 PM PST 24 |
| Peak memory | 190572 kb |
| Host | smart-08f543c1-3029-457d-92e0-1bf9400df073 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888903400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2888903400 |
| Directory | /workspace/27.rv_timer_random/latest |
| Test location | /workspace/coverage/default/27.rv_timer_random_reset.1082495984 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 1942523417 ps |
| CPU time | 5.01 seconds |
| Started | Feb 07 12:36:40 PM PST 24 |
| Finished | Feb 07 12:36:46 PM PST 24 |
| Peak memory | 182264 kb |
| Host | smart-804ad3c6-8d1e-4e5f-8f3f-6057b48175a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1082495984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1082495984 |
| Directory | /workspace/27.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.2779835776 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 332239925079 ps |
| CPU time | 1344.59 seconds |
| Started | Feb 07 12:36:38 PM PST 24 |
| Finished | Feb 07 12:59:04 PM PST 24 |
| Peak memory | 213468 kb |
| Host | smart-0dabbad0-1a49-4915-84c0-b2540e154b8a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779835776 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.2779835776 |
| Directory | /workspace/27.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/28.rv_timer_disabled.3590554542 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 45754459432 ps |
| CPU time | 71.19 seconds |
| Started | Feb 07 12:36:47 PM PST 24 |
| Finished | Feb 07 12:37:59 PM PST 24 |
| Peak memory | 182368 kb |
| Host | smart-6b7e8497-1c76-44cf-82e0-ee2cb739fa30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3590554542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3590554542 |
| Directory | /workspace/28.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/28.rv_timer_random.1432551964 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 24751014644 ps |
| CPU time | 228.43 seconds |
| Started | Feb 07 12:36:47 PM PST 24 |
| Finished | Feb 07 12:40:36 PM PST 24 |
| Peak memory | 182392 kb |
| Host | smart-187bfdac-9c16-4ff8-bffb-ff6c8e4c9330 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432551964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1432551964 |
| Directory | /workspace/28.rv_timer_random/latest |
| Test location | /workspace/coverage/default/28.rv_timer_stress_all.1590204164 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 1115002237011 ps |
| CPU time | 952.16 seconds |
| Started | Feb 07 12:36:46 PM PST 24 |
| Finished | Feb 07 12:52:39 PM PST 24 |
| Peak memory | 193572 kb |
| Host | smart-574f2e0a-c5c7-4205-9adf-5deb7b2eb74e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590204164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all .1590204164 |
| Directory | /workspace/28.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.289691460 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 1680844330455 ps |
| CPU time | 1116.85 seconds |
| Started | Feb 07 12:36:45 PM PST 24 |
| Finished | Feb 07 12:55:24 PM PST 24 |
| Peak memory | 205236 kb |
| Host | smart-fa82bc1c-584e-4686-9c9e-86516175585e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289691460 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.289691460 |
| Directory | /workspace/28.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2598439660 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 255405616412 ps |
| CPU time | 100.68 seconds |
| Started | Feb 07 12:36:25 PM PST 24 |
| Finished | Feb 07 12:38:06 PM PST 24 |
| Peak memory | 182328 kb |
| Host | smart-9b30f65f-6883-42e5-a068-96ae43d626e1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598439660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.2598439660 |
| Directory | /workspace/29.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/29.rv_timer_disabled.1385212774 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 222643527662 ps |
| CPU time | 189.64 seconds |
| Started | Feb 07 12:36:43 PM PST 24 |
| Finished | Feb 07 12:39:54 PM PST 24 |
| Peak memory | 182348 kb |
| Host | smart-3864662d-e66a-488a-a356-6c9570c0d8c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1385212774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1385212774 |
| Directory | /workspace/29.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/29.rv_timer_random.534938030 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 235263869029 ps |
| CPU time | 271.17 seconds |
| Started | Feb 07 12:36:47 PM PST 24 |
| Finished | Feb 07 12:41:19 PM PST 24 |
| Peak memory | 190440 kb |
| Host | smart-652731be-4a4d-4a65-b62f-3ed62dc68305 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534938030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.534938030 |
| Directory | /workspace/29.rv_timer_random/latest |
| Test location | /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.1371300616 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 452525861794 ps |
| CPU time | 970.47 seconds |
| Started | Feb 07 12:36:47 PM PST 24 |
| Finished | Feb 07 12:52:58 PM PST 24 |
| Peak memory | 212812 kb |
| Host | smart-b096cb22-61c2-4048-b0fd-8c82da5073ee |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371300616 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.1371300616 |
| Directory | /workspace/29.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.rv_timer_disabled.2921138269 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 188192152482 ps |
| CPU time | 68.44 seconds |
| Started | Feb 07 12:36:06 PM PST 24 |
| Finished | Feb 07 12:37:16 PM PST 24 |
| Peak memory | 182368 kb |
| Host | smart-71acde7b-c2bc-434f-ba35-fade261d86f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2921138269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2921138269 |
| Directory | /workspace/3.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/3.rv_timer_random.1161455541 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 82145415559 ps |
| CPU time | 165.81 seconds |
| Started | Feb 07 12:36:01 PM PST 24 |
| Finished | Feb 07 12:38:49 PM PST 24 |
| Peak memory | 190576 kb |
| Host | smart-7174b46d-e0f5-4e70-96da-092f35ace801 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161455541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1161455541 |
| Directory | /workspace/3.rv_timer_random/latest |
| Test location | /workspace/coverage/default/3.rv_timer_random_reset.763540534 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 570101517074 ps |
| CPU time | 229.03 seconds |
| Started | Feb 07 12:35:58 PM PST 24 |
| Finished | Feb 07 12:39:50 PM PST 24 |
| Peak memory | 182352 kb |
| Host | smart-96e74eff-7606-4427-bf35-ea3d82b16abe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=763540534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.763540534 |
| Directory | /workspace/3.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/3.rv_timer_sec_cm.1110069704 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 456919370 ps |
| CPU time | 0.73 seconds |
| Started | Feb 07 12:36:17 PM PST 24 |
| Finished | Feb 07 12:36:18 PM PST 24 |
| Peak memory | 212620 kb |
| Host | smart-d8ad61cc-c58c-4296-86a4-68511d294957 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110069704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1110069704 |
| Directory | /workspace/3.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/3.rv_timer_stress_all.4138460220 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 447450169619 ps |
| CPU time | 248.5 seconds |
| Started | Feb 07 12:36:00 PM PST 24 |
| Finished | Feb 07 12:40:11 PM PST 24 |
| Peak memory | 190440 kb |
| Host | smart-0583fdd4-1bb7-48e9-b846-5c4034df3e59 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138460220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all. 4138460220 |
| Directory | /workspace/3.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.1165695324 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 51343545114 ps |
| CPU time | 388.92 seconds |
| Started | Feb 07 12:36:01 PM PST 24 |
| Finished | Feb 07 12:42:32 PM PST 24 |
| Peak memory | 197056 kb |
| Host | smart-52860d9d-22dd-46ab-9dac-96fd5fcef947 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165695324 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.1165695324 |
| Directory | /workspace/3.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3945062246 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 335871682846 ps |
| CPU time | 189.39 seconds |
| Started | Feb 07 12:36:32 PM PST 24 |
| Finished | Feb 07 12:39:43 PM PST 24 |
| Peak memory | 182312 kb |
| Host | smart-c9498ffc-674d-420e-b851-124cb9212b2e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945062246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.3945062246 |
| Directory | /workspace/30.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/30.rv_timer_disabled.640424286 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 425460255733 ps |
| CPU time | 96.46 seconds |
| Started | Feb 07 12:36:41 PM PST 24 |
| Finished | Feb 07 12:38:19 PM PST 24 |
| Peak memory | 182324 kb |
| Host | smart-6382458e-6b7a-4f83-ba88-1f5e0fcfee39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=640424286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.640424286 |
| Directory | /workspace/30.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/30.rv_timer_random.291956375 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 635967206515 ps |
| CPU time | 1115.1 seconds |
| Started | Feb 07 12:36:40 PM PST 24 |
| Finished | Feb 07 12:55:17 PM PST 24 |
| Peak memory | 190456 kb |
| Host | smart-c3aebe59-5784-49bc-920f-bca6ef08c33f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291956375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.291956375 |
| Directory | /workspace/30.rv_timer_random/latest |
| Test location | /workspace/coverage/default/30.rv_timer_random_reset.2903086255 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 951439952 ps |
| CPU time | 0.8 seconds |
| Started | Feb 07 12:36:40 PM PST 24 |
| Finished | Feb 07 12:36:42 PM PST 24 |
| Peak memory | 182084 kb |
| Host | smart-7e906046-f5b2-4d06-b798-44396b89c240 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2903086255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2903086255 |
| Directory | /workspace/30.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/30.rv_timer_stress_all.1920721389 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 129012574 ps |
| CPU time | 0.57 seconds |
| Started | Feb 07 12:36:32 PM PST 24 |
| Finished | Feb 07 12:36:33 PM PST 24 |
| Peak memory | 182148 kb |
| Host | smart-861b2f0f-24de-443e-b05b-fc62df61b362 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920721389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all .1920721389 |
| Directory | /workspace/30.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.300109793 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 183076644733 ps |
| CPU time | 922.8 seconds |
| Started | Feb 07 12:36:43 PM PST 24 |
| Finished | Feb 07 12:52:07 PM PST 24 |
| Peak memory | 210352 kb |
| Host | smart-5bbe45c9-a6ee-4a84-bb9d-86edeecb4d56 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300109793 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.300109793 |
| Directory | /workspace/30.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1371680240 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 1235666110257 ps |
| CPU time | 498.18 seconds |
| Started | Feb 07 12:36:29 PM PST 24 |
| Finished | Feb 07 12:44:48 PM PST 24 |
| Peak memory | 182312 kb |
| Host | smart-2312ecf8-6bd7-4bec-9d08-5eda98aee71e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371680240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_cfg_update_on_fly.1371680240 |
| Directory | /workspace/31.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/31.rv_timer_disabled.3235920910 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 22629775578 ps |
| CPU time | 33.74 seconds |
| Started | Feb 07 12:36:45 PM PST 24 |
| Finished | Feb 07 12:37:19 PM PST 24 |
| Peak memory | 182340 kb |
| Host | smart-8519362d-74c7-49e4-be97-9e0e8f201704 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3235920910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3235920910 |
| Directory | /workspace/31.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/31.rv_timer_random.3992456649 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 83092576439 ps |
| CPU time | 120.6 seconds |
| Started | Feb 07 12:36:41 PM PST 24 |
| Finished | Feb 07 12:38:43 PM PST 24 |
| Peak memory | 192660 kb |
| Host | smart-806ad4c2-e96f-4ebe-9ce4-4a9717e9403b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992456649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3992456649 |
| Directory | /workspace/31.rv_timer_random/latest |
| Test location | /workspace/coverage/default/31.rv_timer_random_reset.383976911 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 178422366973 ps |
| CPU time | 1736.9 seconds |
| Started | Feb 07 12:36:34 PM PST 24 |
| Finished | Feb 07 01:05:32 PM PST 24 |
| Peak memory | 190408 kb |
| Host | smart-d0e1e9b6-dfe9-4169-b162-18b0b6cce965 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=383976911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.383976911 |
| Directory | /workspace/31.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.2960053911 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 104907450838 ps |
| CPU time | 977.51 seconds |
| Started | Feb 07 12:36:30 PM PST 24 |
| Finished | Feb 07 12:52:49 PM PST 24 |
| Peak memory | 208500 kb |
| Host | smart-5b4d34dd-3b32-40e1-a384-8ebabf74895b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960053911 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.2960053911 |
| Directory | /workspace/31.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.745268273 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 560349428818 ps |
| CPU time | 570.05 seconds |
| Started | Feb 07 12:36:25 PM PST 24 |
| Finished | Feb 07 12:45:56 PM PST 24 |
| Peak memory | 182328 kb |
| Host | smart-eb19a9e3-d4df-47b8-92cd-d384b1aa0fad |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745268273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.rv_timer_cfg_update_on_fly.745268273 |
| Directory | /workspace/32.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/32.rv_timer_disabled.4228378686 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 290689345691 ps |
| CPU time | 181.7 seconds |
| Started | Feb 07 12:36:46 PM PST 24 |
| Finished | Feb 07 12:39:49 PM PST 24 |
| Peak memory | 182256 kb |
| Host | smart-37265d3f-54b9-4658-918f-d749c33d1791 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4228378686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.4228378686 |
| Directory | /workspace/32.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/32.rv_timer_random.1937983472 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 281208610360 ps |
| CPU time | 99.97 seconds |
| Started | Feb 07 12:36:41 PM PST 24 |
| Finished | Feb 07 12:38:23 PM PST 24 |
| Peak memory | 182300 kb |
| Host | smart-4ed7bd24-d6e7-4b76-b2a4-ab66ace81148 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937983472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1937983472 |
| Directory | /workspace/32.rv_timer_random/latest |
| Test location | /workspace/coverage/default/32.rv_timer_random_reset.3981805935 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 93162239646 ps |
| CPU time | 93.89 seconds |
| Started | Feb 07 12:36:34 PM PST 24 |
| Finished | Feb 07 12:38:09 PM PST 24 |
| Peak memory | 190460 kb |
| Host | smart-03ebb751-772d-43f4-bbf5-03e232a1474b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3981805935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3981805935 |
| Directory | /workspace/32.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/32.rv_timer_stress_all.248524698 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 460602618549 ps |
| CPU time | 816.59 seconds |
| Started | Feb 07 12:36:36 PM PST 24 |
| Finished | Feb 07 12:50:14 PM PST 24 |
| Peak memory | 190588 kb |
| Host | smart-8e090746-8494-4263-93af-88a9c7dfb10c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248524698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all. 248524698 |
| Directory | /workspace/32.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.312497860 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 32652071404 ps |
| CPU time | 265.31 seconds |
| Started | Feb 07 12:36:44 PM PST 24 |
| Finished | Feb 07 12:41:10 PM PST 24 |
| Peak memory | 205292 kb |
| Host | smart-1ad1c75e-a2c2-4553-8038-b460ace70fa0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312497860 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.312497860 |
| Directory | /workspace/32.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.4072351679 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 83104621684 ps |
| CPU time | 32.34 seconds |
| Started | Feb 07 12:36:36 PM PST 24 |
| Finished | Feb 07 12:37:09 PM PST 24 |
| Peak memory | 182284 kb |
| Host | smart-fdf7d26f-f542-4269-879b-671d6792079f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072351679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.4072351679 |
| Directory | /workspace/33.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/33.rv_timer_disabled.4061348619 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 91807886016 ps |
| CPU time | 48.35 seconds |
| Started | Feb 07 12:36:30 PM PST 24 |
| Finished | Feb 07 12:37:20 PM PST 24 |
| Peak memory | 182312 kb |
| Host | smart-ffa72b20-8f44-4407-a055-0d62fd450feb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4061348619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.4061348619 |
| Directory | /workspace/33.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/33.rv_timer_random.4207790313 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 337873017587 ps |
| CPU time | 481.83 seconds |
| Started | Feb 07 12:36:42 PM PST 24 |
| Finished | Feb 07 12:44:45 PM PST 24 |
| Peak memory | 190552 kb |
| Host | smart-19152237-314a-49ac-8a26-5650cc80a6fd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207790313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.4207790313 |
| Directory | /workspace/33.rv_timer_random/latest |
| Test location | /workspace/coverage/default/33.rv_timer_random_reset.3346791745 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 362417749 ps |
| CPU time | 0.81 seconds |
| Started | Feb 07 12:36:44 PM PST 24 |
| Finished | Feb 07 12:36:46 PM PST 24 |
| Peak memory | 182084 kb |
| Host | smart-3cb717c4-0b3b-449f-8756-9f9cb8cd2f35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3346791745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3346791745 |
| Directory | /workspace/33.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/33.rv_timer_stress_all.2892710115 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 2085315124020 ps |
| CPU time | 2515.64 seconds |
| Started | Feb 07 12:36:41 PM PST 24 |
| Finished | Feb 07 01:18:38 PM PST 24 |
| Peak memory | 190484 kb |
| Host | smart-c78da06a-6fcb-47fa-8656-14d38c23b9d7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892710115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all .2892710115 |
| Directory | /workspace/33.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.3129822754 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 124831048180 ps |
| CPU time | 393.5 seconds |
| Started | Feb 07 12:36:29 PM PST 24 |
| Finished | Feb 07 12:43:03 PM PST 24 |
| Peak memory | 205296 kb |
| Host | smart-0e477127-d8d4-42ed-96c6-727d8525296d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129822754 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.3129822754 |
| Directory | /workspace/33.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1710015033 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 119446932048 ps |
| CPU time | 225.28 seconds |
| Started | Feb 07 12:36:43 PM PST 24 |
| Finished | Feb 07 12:40:29 PM PST 24 |
| Peak memory | 182308 kb |
| Host | smart-4a6e4415-6ea1-4ad5-98ff-fcd87f1440b9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710015033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.1710015033 |
| Directory | /workspace/34.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/34.rv_timer_disabled.715178114 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 55730750106 ps |
| CPU time | 49.53 seconds |
| Started | Feb 07 12:36:45 PM PST 24 |
| Finished | Feb 07 12:37:36 PM PST 24 |
| Peak memory | 182280 kb |
| Host | smart-02ca2fdb-0419-4a45-87e8-e3b5a7b9386b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=715178114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.715178114 |
| Directory | /workspace/34.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/34.rv_timer_random.3449388498 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 57430892035 ps |
| CPU time | 60.94 seconds |
| Started | Feb 07 12:36:45 PM PST 24 |
| Finished | Feb 07 12:37:47 PM PST 24 |
| Peak memory | 190596 kb |
| Host | smart-e43f9b89-d3b6-455f-9474-5bffe77c71f4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449388498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3449388498 |
| Directory | /workspace/34.rv_timer_random/latest |
| Test location | /workspace/coverage/default/34.rv_timer_random_reset.2283615920 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 23438166221 ps |
| CPU time | 19.28 seconds |
| Started | Feb 07 12:36:45 PM PST 24 |
| Finished | Feb 07 12:37:06 PM PST 24 |
| Peak memory | 193516 kb |
| Host | smart-2b44ff4c-92a8-41d3-8b8a-d0197d9a5cdf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2283615920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2283615920 |
| Directory | /workspace/34.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/34.rv_timer_stress_all.2553221846 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 663995174539 ps |
| CPU time | 787.77 seconds |
| Started | Feb 07 12:36:34 PM PST 24 |
| Finished | Feb 07 12:49:43 PM PST 24 |
| Peak memory | 190528 kb |
| Host | smart-17c98065-aa47-4902-94ee-6bd05b5588bf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553221846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all .2553221846 |
| Directory | /workspace/34.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.424174116 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 27985078356 ps |
| CPU time | 151.67 seconds |
| Started | Feb 07 12:36:35 PM PST 24 |
| Finished | Feb 07 12:39:08 PM PST 24 |
| Peak memory | 197012 kb |
| Host | smart-42512c83-1312-4362-8543-7a6fa230bbd2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424174116 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.424174116 |
| Directory | /workspace/34.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1726352489 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 132345137983 ps |
| CPU time | 230.31 seconds |
| Started | Feb 07 12:36:52 PM PST 24 |
| Finished | Feb 07 12:40:43 PM PST 24 |
| Peak memory | 182536 kb |
| Host | smart-9fb79e66-8eec-4084-9ea2-9ca79fa2cae7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726352489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.1726352489 |
| Directory | /workspace/35.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/35.rv_timer_disabled.3873151058 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 214430732486 ps |
| CPU time | 172.99 seconds |
| Started | Feb 07 12:37:35 PM PST 24 |
| Finished | Feb 07 12:40:29 PM PST 24 |
| Peak memory | 181488 kb |
| Host | smart-3a467313-cbfa-4bf8-960f-72401acb9b41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3873151058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3873151058 |
| Directory | /workspace/35.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/35.rv_timer_random.1479762175 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 68102299914 ps |
| CPU time | 106.68 seconds |
| Started | Feb 07 12:37:40 PM PST 24 |
| Finished | Feb 07 12:39:27 PM PST 24 |
| Peak memory | 192492 kb |
| Host | smart-4ab69f75-9ee6-44e7-bccd-28aa369d7bf8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479762175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1479762175 |
| Directory | /workspace/35.rv_timer_random/latest |
| Test location | /workspace/coverage/default/35.rv_timer_random_reset.3598014618 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 222119810749 ps |
| CPU time | 309.06 seconds |
| Started | Feb 07 12:37:44 PM PST 24 |
| Finished | Feb 07 12:42:54 PM PST 24 |
| Peak memory | 181900 kb |
| Host | smart-f22fecda-e50b-4889-8191-1c67a2aa3e08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3598014618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3598014618 |
| Directory | /workspace/35.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/35.rv_timer_stress_all.2712883764 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 413380169101 ps |
| CPU time | 375.15 seconds |
| Started | Feb 07 12:36:46 PM PST 24 |
| Finished | Feb 07 12:43:02 PM PST 24 |
| Peak memory | 190444 kb |
| Host | smart-1bea34c4-e411-4f4f-a6be-edf478a7e46d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712883764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all .2712883764 |
| Directory | /workspace/35.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.2714424330 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 2169775265301 ps |
| CPU time | 1704.04 seconds |
| Started | Feb 07 12:37:44 PM PST 24 |
| Finished | Feb 07 01:06:09 PM PST 24 |
| Peak memory | 210292 kb |
| Host | smart-94400f38-425c-47f9-b253-b35e65ec783b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714424330 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.2714424330 |
| Directory | /workspace/35.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.134917541 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 737590574660 ps |
| CPU time | 672.35 seconds |
| Started | Feb 07 12:36:41 PM PST 24 |
| Finished | Feb 07 12:47:55 PM PST 24 |
| Peak memory | 182324 kb |
| Host | smart-4528cf31-d1c4-4652-ab5a-398322312783 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134917541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.rv_timer_cfg_update_on_fly.134917541 |
| Directory | /workspace/36.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/36.rv_timer_disabled.1281112536 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 158480965186 ps |
| CPU time | 275.99 seconds |
| Started | Feb 07 12:36:46 PM PST 24 |
| Finished | Feb 07 12:41:23 PM PST 24 |
| Peak memory | 182276 kb |
| Host | smart-b6b3e840-2175-4ff7-b345-6a31b4ccdd53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1281112536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1281112536 |
| Directory | /workspace/36.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/36.rv_timer_random.1871161056 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 13334309847 ps |
| CPU time | 38.18 seconds |
| Started | Feb 07 12:36:44 PM PST 24 |
| Finished | Feb 07 12:37:23 PM PST 24 |
| Peak memory | 182396 kb |
| Host | smart-de66a3ab-bc03-47f9-a1b1-fdca6d0399b6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871161056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1871161056 |
| Directory | /workspace/36.rv_timer_random/latest |
| Test location | /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.369774120 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 10780156578 ps |
| CPU time | 91 seconds |
| Started | Feb 07 12:36:42 PM PST 24 |
| Finished | Feb 07 12:38:14 PM PST 24 |
| Peak memory | 197064 kb |
| Host | smart-9553f093-4d47-47c3-bd14-7bd58f7905cb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369774120 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.369774120 |
| Directory | /workspace/36.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1299241322 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 1942948594819 ps |
| CPU time | 1157.03 seconds |
| Started | Feb 07 12:36:42 PM PST 24 |
| Finished | Feb 07 12:56:00 PM PST 24 |
| Peak memory | 182232 kb |
| Host | smart-4afba26e-8162-4a53-9de4-3d9d99bb521e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299241322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.1299241322 |
| Directory | /workspace/37.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/37.rv_timer_disabled.4108057187 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 210966162338 ps |
| CPU time | 76.72 seconds |
| Started | Feb 07 12:36:44 PM PST 24 |
| Finished | Feb 07 12:38:02 PM PST 24 |
| Peak memory | 182328 kb |
| Host | smart-8263dbbf-3b1e-4355-a4f5-803e56cbaceb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4108057187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.4108057187 |
| Directory | /workspace/37.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/37.rv_timer_random.3758009546 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 184640713122 ps |
| CPU time | 1484.98 seconds |
| Started | Feb 07 12:36:46 PM PST 24 |
| Finished | Feb 07 01:01:32 PM PST 24 |
| Peak memory | 193232 kb |
| Host | smart-2f770b96-eab1-4119-a1db-e8ff4ef4f748 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758009546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3758009546 |
| Directory | /workspace/37.rv_timer_random/latest |
| Test location | /workspace/coverage/default/37.rv_timer_random_reset.1704206155 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 42594242101 ps |
| CPU time | 249.3 seconds |
| Started | Feb 07 12:36:49 PM PST 24 |
| Finished | Feb 07 12:40:59 PM PST 24 |
| Peak memory | 182376 kb |
| Host | smart-0907276f-c460-4604-afe1-cf28834ac370 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1704206155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1704206155 |
| Directory | /workspace/37.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/37.rv_timer_stress_all.2546124812 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 218391294350 ps |
| CPU time | 91.64 seconds |
| Started | Feb 07 12:36:44 PM PST 24 |
| Finished | Feb 07 12:38:16 PM PST 24 |
| Peak memory | 182288 kb |
| Host | smart-00b7e68d-bf2d-430c-9ba4-a72f77f0957b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546124812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all .2546124812 |
| Directory | /workspace/37.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.2917079109 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 15688378189 ps |
| CPU time | 60.91 seconds |
| Started | Feb 07 12:36:47 PM PST 24 |
| Finished | Feb 07 12:37:48 PM PST 24 |
| Peak memory | 197016 kb |
| Host | smart-406c4720-5405-4d7b-96cd-4f51f6c576f4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917079109 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.2917079109 |
| Directory | /workspace/37.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1215786707 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 42756469364 ps |
| CPU time | 23.47 seconds |
| Started | Feb 07 12:36:41 PM PST 24 |
| Finished | Feb 07 12:37:06 PM PST 24 |
| Peak memory | 182224 kb |
| Host | smart-97c06e0e-7f83-4452-8c94-318479062a41 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215786707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_cfg_update_on_fly.1215786707 |
| Directory | /workspace/38.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/38.rv_timer_disabled.2969768785 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 947684488851 ps |
| CPU time | 160.7 seconds |
| Started | Feb 07 12:36:38 PM PST 24 |
| Finished | Feb 07 12:39:20 PM PST 24 |
| Peak memory | 182276 kb |
| Host | smart-3013f002-76a5-495e-b4b9-31e19e488850 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2969768785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2969768785 |
| Directory | /workspace/38.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/38.rv_timer_random.4079987228 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 530892408120 ps |
| CPU time | 454.74 seconds |
| Started | Feb 07 12:36:46 PM PST 24 |
| Finished | Feb 07 12:44:22 PM PST 24 |
| Peak memory | 190492 kb |
| Host | smart-e84ef787-2f4c-4016-847a-1c06ee217c17 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079987228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.4079987228 |
| Directory | /workspace/38.rv_timer_random/latest |
| Test location | /workspace/coverage/default/38.rv_timer_random_reset.3683129023 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 59720232622 ps |
| CPU time | 38.62 seconds |
| Started | Feb 07 12:36:44 PM PST 24 |
| Finished | Feb 07 12:37:24 PM PST 24 |
| Peak memory | 190472 kb |
| Host | smart-1b81bffc-b382-48e3-80a5-5b9225ece121 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3683129023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.3683129023 |
| Directory | /workspace/38.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/38.rv_timer_stress_all.1414057135 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 458639368599 ps |
| CPU time | 285.06 seconds |
| Started | Feb 07 12:36:37 PM PST 24 |
| Finished | Feb 07 12:41:23 PM PST 24 |
| Peak memory | 190324 kb |
| Host | smart-d3d13e30-1360-4308-95c9-1455421f8669 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414057135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all .1414057135 |
| Directory | /workspace/38.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.3317626485 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 423012038215 ps |
| CPU time | 1425.39 seconds |
| Started | Feb 07 12:36:38 PM PST 24 |
| Finished | Feb 07 01:00:25 PM PST 24 |
| Peak memory | 212892 kb |
| Host | smart-9c96298c-e313-4c79-bedc-fb2aed717211 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317626485 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.3317626485 |
| Directory | /workspace/38.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2975238491 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 42593920814 ps |
| CPU time | 32.33 seconds |
| Started | Feb 07 12:36:42 PM PST 24 |
| Finished | Feb 07 12:37:15 PM PST 24 |
| Peak memory | 182216 kb |
| Host | smart-f057ee57-2450-4817-9a3c-87e310e74d99 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975238491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.2975238491 |
| Directory | /workspace/39.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/39.rv_timer_disabled.1758008021 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 83656478897 ps |
| CPU time | 69.46 seconds |
| Started | Feb 07 12:36:44 PM PST 24 |
| Finished | Feb 07 12:37:54 PM PST 24 |
| Peak memory | 182492 kb |
| Host | smart-ec8c7969-5dba-49a6-9c5c-a58f92c37f41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1758008021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1758008021 |
| Directory | /workspace/39.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/39.rv_timer_random.4011156288 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 32760656948 ps |
| CPU time | 604.59 seconds |
| Started | Feb 07 12:36:48 PM PST 24 |
| Finished | Feb 07 12:46:54 PM PST 24 |
| Peak memory | 182240 kb |
| Host | smart-ac243ecd-89f0-46e1-ba13-ac16065ebe23 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011156288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.4011156288 |
| Directory | /workspace/39.rv_timer_random/latest |
| Test location | /workspace/coverage/default/39.rv_timer_random_reset.1709265669 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 10575231208 ps |
| CPU time | 12.15 seconds |
| Started | Feb 07 12:36:53 PM PST 24 |
| Finished | Feb 07 12:37:06 PM PST 24 |
| Peak memory | 182228 kb |
| Host | smart-231ba542-4153-4043-8de7-942f7347c766 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1709265669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1709265669 |
| Directory | /workspace/39.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.3053283952 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 45395025184 ps |
| CPU time | 158.22 seconds |
| Started | Feb 07 12:36:40 PM PST 24 |
| Finished | Feb 07 12:39:20 PM PST 24 |
| Peak memory | 196936 kb |
| Host | smart-de67c2d6-1acb-48a9-9aaa-a5e1164e3022 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053283952 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.3053283952 |
| Directory | /workspace/39.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.417540177 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1342733303477 ps |
| CPU time | 770.6 seconds |
| Started | Feb 07 12:36:04 PM PST 24 |
| Finished | Feb 07 12:48:56 PM PST 24 |
| Peak memory | 182252 kb |
| Host | smart-66a8acb2-25af-4a79-9145-d79b69a3bbf9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417540177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .rv_timer_cfg_update_on_fly.417540177 |
| Directory | /workspace/4.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/4.rv_timer_disabled.376980261 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 61845009428 ps |
| CPU time | 89.35 seconds |
| Started | Feb 07 12:36:06 PM PST 24 |
| Finished | Feb 07 12:37:37 PM PST 24 |
| Peak memory | 182308 kb |
| Host | smart-3a47aeb4-8d8e-4cca-b005-f9135aa093cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=376980261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.376980261 |
| Directory | /workspace/4.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/4.rv_timer_random.2109474204 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 526359099163 ps |
| CPU time | 1237.78 seconds |
| Started | Feb 07 12:36:06 PM PST 24 |
| Finished | Feb 07 12:56:45 PM PST 24 |
| Peak memory | 190536 kb |
| Host | smart-5fc959f5-0a7c-4829-9d02-3fbfd7498ee0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109474204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2109474204 |
| Directory | /workspace/4.rv_timer_random/latest |
| Test location | /workspace/coverage/default/4.rv_timer_random_reset.4206680998 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 1139670257 ps |
| CPU time | 1.41 seconds |
| Started | Feb 07 12:36:01 PM PST 24 |
| Finished | Feb 07 12:36:04 PM PST 24 |
| Peak memory | 192580 kb |
| Host | smart-a037b561-1cd1-4a1d-9524-de1246586ea9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4206680998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.4206680998 |
| Directory | /workspace/4.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/4.rv_timer_sec_cm.3220791471 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 229359279 ps |
| CPU time | 0.8 seconds |
| Started | Feb 07 12:36:02 PM PST 24 |
| Finished | Feb 07 12:36:04 PM PST 24 |
| Peak memory | 212628 kb |
| Host | smart-3e7dd137-6018-4cf7-8038-7daf811b9028 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220791471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3220791471 |
| Directory | /workspace/4.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/4.rv_timer_stress_all.4153599575 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 1634811848436 ps |
| CPU time | 585.08 seconds |
| Started | Feb 07 12:36:12 PM PST 24 |
| Finished | Feb 07 12:45:59 PM PST 24 |
| Peak memory | 190496 kb |
| Host | smart-0ce05bb6-5641-4b0a-92b1-60334f4de88c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153599575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all. 4153599575 |
| Directory | /workspace/4.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.3212246980 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 103641796041 ps |
| CPU time | 1747.11 seconds |
| Started | Feb 07 12:36:03 PM PST 24 |
| Finished | Feb 07 01:05:20 PM PST 24 |
| Peak memory | 212876 kb |
| Host | smart-4aa12654-77bf-4073-85c5-a9ad622fb653 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212246980 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.3212246980 |
| Directory | /workspace/4.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/40.rv_timer_disabled.1479515393 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 47426675384 ps |
| CPU time | 36.81 seconds |
| Started | Feb 07 12:36:54 PM PST 24 |
| Finished | Feb 07 12:37:32 PM PST 24 |
| Peak memory | 182276 kb |
| Host | smart-54e3c3d7-16db-4f17-9a89-2bcab0b82a8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1479515393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1479515393 |
| Directory | /workspace/40.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/40.rv_timer_random_reset.417165392 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 21667348028 ps |
| CPU time | 38.4 seconds |
| Started | Feb 07 12:36:46 PM PST 24 |
| Finished | Feb 07 12:37:26 PM PST 24 |
| Peak memory | 193244 kb |
| Host | smart-c79a06a1-e540-4dc2-9e8a-5bbd84440c46 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=417165392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.417165392 |
| Directory | /workspace/40.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/40.rv_timer_stress_all.1380245003 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 55929968 ps |
| CPU time | 0.55 seconds |
| Started | Feb 07 12:36:31 PM PST 24 |
| Finished | Feb 07 12:36:33 PM PST 24 |
| Peak memory | 182036 kb |
| Host | smart-56d56042-4632-47ae-a51b-9d71a2a7a36f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380245003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all .1380245003 |
| Directory | /workspace/40.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.3379393623 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 12879913627 ps |
| CPU time | 108.1 seconds |
| Started | Feb 07 12:36:34 PM PST 24 |
| Finished | Feb 07 12:38:24 PM PST 24 |
| Peak memory | 195736 kb |
| Host | smart-bc059b01-1537-4c16-a756-fd571f55a03e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379393623 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.3379393623 |
| Directory | /workspace/40.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2028259356 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 1699379432925 ps |
| CPU time | 898.8 seconds |
| Started | Feb 07 12:36:37 PM PST 24 |
| Finished | Feb 07 12:51:37 PM PST 24 |
| Peak memory | 182280 kb |
| Host | smart-5d3a35a0-d0d8-4e29-8ad2-bb67d1c8dc8f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028259356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.2028259356 |
| Directory | /workspace/41.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/41.rv_timer_disabled.1139722039 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 68654921589 ps |
| CPU time | 99.71 seconds |
| Started | Feb 07 12:36:42 PM PST 24 |
| Finished | Feb 07 12:38:23 PM PST 24 |
| Peak memory | 182308 kb |
| Host | smart-5e4a7d79-9ccf-4780-a5eb-019908eedaf8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1139722039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1139722039 |
| Directory | /workspace/41.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/41.rv_timer_random.848361880 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 160803777326 ps |
| CPU time | 452.34 seconds |
| Started | Feb 07 12:36:46 PM PST 24 |
| Finished | Feb 07 12:44:20 PM PST 24 |
| Peak memory | 182300 kb |
| Host | smart-1e130c00-190d-4d4c-9a21-49bb62fe686c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848361880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.848361880 |
| Directory | /workspace/41.rv_timer_random/latest |
| Test location | /workspace/coverage/default/41.rv_timer_random_reset.4020276566 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 100156855060 ps |
| CPU time | 72.79 seconds |
| Started | Feb 07 12:36:45 PM PST 24 |
| Finished | Feb 07 12:37:59 PM PST 24 |
| Peak memory | 182284 kb |
| Host | smart-2e38178e-b8af-44b5-a903-1a7760653e5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4020276566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.4020276566 |
| Directory | /workspace/41.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/41.rv_timer_stress_all.1212340562 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 226138558490 ps |
| CPU time | 384.55 seconds |
| Started | Feb 07 12:36:40 PM PST 24 |
| Finished | Feb 07 12:43:06 PM PST 24 |
| Peak memory | 190520 kb |
| Host | smart-c1248e23-f418-49fb-9a66-5ce213e6b353 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212340562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all .1212340562 |
| Directory | /workspace/41.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.2646636689 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 203757709270 ps |
| CPU time | 643.87 seconds |
| Started | Feb 07 12:36:46 PM PST 24 |
| Finished | Feb 07 12:47:31 PM PST 24 |
| Peak memory | 205156 kb |
| Host | smart-71614ae6-7c55-4d8b-a33f-182513896de8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646636689 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.2646636689 |
| Directory | /workspace/41.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.292569811 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 876110003439 ps |
| CPU time | 479.88 seconds |
| Started | Feb 07 12:37:36 PM PST 24 |
| Finished | Feb 07 12:45:36 PM PST 24 |
| Peak memory | 181932 kb |
| Host | smart-e0b8cc0e-7a82-4c73-9238-3c0c809d80b5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292569811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.rv_timer_cfg_update_on_fly.292569811 |
| Directory | /workspace/42.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/42.rv_timer_disabled.4010986569 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 172476279827 ps |
| CPU time | 127.41 seconds |
| Started | Feb 07 12:36:36 PM PST 24 |
| Finished | Feb 07 12:38:44 PM PST 24 |
| Peak memory | 182372 kb |
| Host | smart-ee62d934-c681-4420-9688-bb41bb78c9fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4010986569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.4010986569 |
| Directory | /workspace/42.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/42.rv_timer_random.4155707384 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 213910572448 ps |
| CPU time | 789.36 seconds |
| Started | Feb 07 12:36:37 PM PST 24 |
| Finished | Feb 07 12:49:47 PM PST 24 |
| Peak memory | 190556 kb |
| Host | smart-6bd81cd5-9e11-444a-84b3-33857b836efc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155707384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.4155707384 |
| Directory | /workspace/42.rv_timer_random/latest |
| Test location | /workspace/coverage/default/42.rv_timer_random_reset.1534627348 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 5441764343 ps |
| CPU time | 54.85 seconds |
| Started | Feb 07 12:37:35 PM PST 24 |
| Finished | Feb 07 12:38:31 PM PST 24 |
| Peak memory | 189728 kb |
| Host | smart-5810ee61-04f7-48ba-af03-66d8eae30a04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1534627348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1534627348 |
| Directory | /workspace/42.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.638335336 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 62779385318 ps |
| CPU time | 540.43 seconds |
| Started | Feb 07 12:36:30 PM PST 24 |
| Finished | Feb 07 12:45:31 PM PST 24 |
| Peak memory | 197052 kb |
| Host | smart-ef170190-b03a-412f-a14d-da9054080ab3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638335336 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.638335336 |
| Directory | /workspace/42.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3585285542 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 713151274191 ps |
| CPU time | 321.2 seconds |
| Started | Feb 07 12:37:43 PM PST 24 |
| Finished | Feb 07 12:43:05 PM PST 24 |
| Peak memory | 181988 kb |
| Host | smart-f7d8cb78-a1cf-4b59-a25e-0891a81a3a4c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585285542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.3585285542 |
| Directory | /workspace/43.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/43.rv_timer_disabled.3686556892 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 124795169819 ps |
| CPU time | 210.53 seconds |
| Started | Feb 07 12:36:38 PM PST 24 |
| Finished | Feb 07 12:40:10 PM PST 24 |
| Peak memory | 182276 kb |
| Host | smart-e91cee3f-b177-40b3-be29-999675256d28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3686556892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3686556892 |
| Directory | /workspace/43.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/43.rv_timer_random.653332227 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 185830018756 ps |
| CPU time | 95.55 seconds |
| Started | Feb 07 12:37:44 PM PST 24 |
| Finished | Feb 07 12:39:20 PM PST 24 |
| Peak memory | 182016 kb |
| Host | smart-f510a821-614d-496a-9178-19374819c079 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653332227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.653332227 |
| Directory | /workspace/43.rv_timer_random/latest |
| Test location | /workspace/coverage/default/43.rv_timer_random_reset.1972879849 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 66187280565 ps |
| CPU time | 121.86 seconds |
| Started | Feb 07 12:36:30 PM PST 24 |
| Finished | Feb 07 12:38:33 PM PST 24 |
| Peak memory | 190472 kb |
| Host | smart-4d088f00-4e47-4c94-86b9-3eb125e5d105 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1972879849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1972879849 |
| Directory | /workspace/43.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.1126929357 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 292183471822 ps |
| CPU time | 259.07 seconds |
| Started | Feb 07 12:37:40 PM PST 24 |
| Finished | Feb 07 12:42:00 PM PST 24 |
| Peak memory | 204952 kb |
| Host | smart-68b6100a-6153-40cf-aef7-ac5323b7d884 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126929357 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.1126929357 |
| Directory | /workspace/43.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2792541510 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 11989581993 ps |
| CPU time | 11.22 seconds |
| Started | Feb 07 12:36:46 PM PST 24 |
| Finished | Feb 07 12:36:58 PM PST 24 |
| Peak memory | 182324 kb |
| Host | smart-96c96ad4-a413-467a-83e3-91c8a78151e2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792541510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_cfg_update_on_fly.2792541510 |
| Directory | /workspace/44.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/44.rv_timer_disabled.930840002 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 2482669127 ps |
| CPU time | 3.61 seconds |
| Started | Feb 07 12:36:40 PM PST 24 |
| Finished | Feb 07 12:36:45 PM PST 24 |
| Peak memory | 182180 kb |
| Host | smart-c2e79206-d9e7-4613-aff4-e4f026ab9036 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=930840002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.930840002 |
| Directory | /workspace/44.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/44.rv_timer_random.727399713 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 104390833850 ps |
| CPU time | 86.55 seconds |
| Started | Feb 07 12:36:45 PM PST 24 |
| Finished | Feb 07 12:38:12 PM PST 24 |
| Peak memory | 182352 kb |
| Host | smart-64234764-9cbd-41fe-adaf-3add1eb3f2e3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727399713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.727399713 |
| Directory | /workspace/44.rv_timer_random/latest |
| Test location | /workspace/coverage/default/44.rv_timer_random_reset.3983859717 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 103400966 ps |
| CPU time | 1.58 seconds |
| Started | Feb 07 12:36:28 PM PST 24 |
| Finished | Feb 07 12:36:30 PM PST 24 |
| Peak memory | 190516 kb |
| Host | smart-d95b0407-7d9b-4dff-a681-bebd4057291c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3983859717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3983859717 |
| Directory | /workspace/44.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.25163844 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 82467343726 ps |
| CPU time | 573.53 seconds |
| Started | Feb 07 12:37:34 PM PST 24 |
| Finished | Feb 07 12:47:09 PM PST 24 |
| Peak memory | 203944 kb |
| Host | smart-fbf70bb8-2b71-49e3-af92-af7274e0634a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25163844 -assert nopos tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.25163844 |
| Directory | /workspace/44.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/45.rv_timer_disabled.2755032136 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 163896930583 ps |
| CPU time | 68.54 seconds |
| Started | Feb 07 12:36:46 PM PST 24 |
| Finished | Feb 07 12:37:56 PM PST 24 |
| Peak memory | 182328 kb |
| Host | smart-3cb84c6c-54ab-4b57-8d10-23ffbdf632b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2755032136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2755032136 |
| Directory | /workspace/45.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/45.rv_timer_random.3107947828 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 195821313644 ps |
| CPU time | 435.15 seconds |
| Started | Feb 07 12:36:34 PM PST 24 |
| Finished | Feb 07 12:43:50 PM PST 24 |
| Peak memory | 190568 kb |
| Host | smart-cec5912b-2c40-42bd-865c-b77f59951843 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107947828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3107947828 |
| Directory | /workspace/45.rv_timer_random/latest |
| Test location | /workspace/coverage/default/45.rv_timer_random_reset.443615857 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 912462986 ps |
| CPU time | 2.05 seconds |
| Started | Feb 07 12:36:41 PM PST 24 |
| Finished | Feb 07 12:36:44 PM PST 24 |
| Peak memory | 190488 kb |
| Host | smart-404b1edd-727a-4e83-b3ae-ebdde6a82524 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=443615857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.443615857 |
| Directory | /workspace/45.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.2616608152 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 722722800889 ps |
| CPU time | 985.91 seconds |
| Started | Feb 07 12:36:45 PM PST 24 |
| Finished | Feb 07 12:53:12 PM PST 24 |
| Peak memory | 210156 kb |
| Host | smart-5b3ad91a-5144-454c-a832-25594f5701da |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616608152 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.2616608152 |
| Directory | /workspace/45.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1382825221 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 458569505451 ps |
| CPU time | 233.77 seconds |
| Started | Feb 07 12:36:30 PM PST 24 |
| Finished | Feb 07 12:40:26 PM PST 24 |
| Peak memory | 182312 kb |
| Host | smart-e0862bb6-6cfb-47c8-acc1-1c48c897f0d2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382825221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_cfg_update_on_fly.1382825221 |
| Directory | /workspace/46.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/46.rv_timer_disabled.108714621 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 258914439558 ps |
| CPU time | 118.03 seconds |
| Started | Feb 07 12:36:43 PM PST 24 |
| Finished | Feb 07 12:38:42 PM PST 24 |
| Peak memory | 182272 kb |
| Host | smart-9c86c2ad-cab0-468d-b2df-be75f9ff4369 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=108714621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.108714621 |
| Directory | /workspace/46.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/46.rv_timer_random_reset.603733373 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 17123905 ps |
| CPU time | 0.52 seconds |
| Started | Feb 07 12:36:29 PM PST 24 |
| Finished | Feb 07 12:36:30 PM PST 24 |
| Peak memory | 182024 kb |
| Host | smart-cdada800-63e3-477a-aeb9-ef4f4ce7f411 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=603733373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.603733373 |
| Directory | /workspace/46.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.3237138787 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 137480953239 ps |
| CPU time | 162.41 seconds |
| Started | Feb 07 12:36:41 PM PST 24 |
| Finished | Feb 07 12:39:25 PM PST 24 |
| Peak memory | 208148 kb |
| Host | smart-679303a6-996d-4943-b833-73ab55f63fde |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237138787 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.3237138787 |
| Directory | /workspace/46.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1125745116 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 50796169907 ps |
| CPU time | 48.51 seconds |
| Started | Feb 07 12:36:44 PM PST 24 |
| Finished | Feb 07 12:37:33 PM PST 24 |
| Peak memory | 182292 kb |
| Host | smart-e1dbeb49-013a-46c1-b95a-e61a224733fd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125745116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_cfg_update_on_fly.1125745116 |
| Directory | /workspace/47.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/47.rv_timer_disabled.436845985 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 335793419942 ps |
| CPU time | 184.31 seconds |
| Started | Feb 07 12:36:49 PM PST 24 |
| Finished | Feb 07 12:39:54 PM PST 24 |
| Peak memory | 182212 kb |
| Host | smart-89dea32d-fc0a-4cb4-aa27-53a74e28173f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=436845985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.436845985 |
| Directory | /workspace/47.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/47.rv_timer_random.616900796 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 14676276967 ps |
| CPU time | 5.29 seconds |
| Started | Feb 07 12:36:14 PM PST 24 |
| Finished | Feb 07 12:36:22 PM PST 24 |
| Peak memory | 182320 kb |
| Host | smart-8c581aea-12d3-4ea6-a52d-02d74d03e454 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616900796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.616900796 |
| Directory | /workspace/47.rv_timer_random/latest |
| Test location | /workspace/coverage/default/47.rv_timer_random_reset.4023126974 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 7187673492 ps |
| CPU time | 12.72 seconds |
| Started | Feb 07 12:36:30 PM PST 24 |
| Finished | Feb 07 12:36:44 PM PST 24 |
| Peak memory | 190624 kb |
| Host | smart-bf225a6c-662a-4a2c-8a87-0e20bfe24fba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4023126974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.4023126974 |
| Directory | /workspace/47.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.862627798 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 189754393888 ps |
| CPU time | 1386.25 seconds |
| Started | Feb 07 12:36:49 PM PST 24 |
| Finished | Feb 07 12:59:56 PM PST 24 |
| Peak memory | 213360 kb |
| Host | smart-0ba11594-0721-4c9f-b15a-c21affaeebfd |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862627798 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.862627798 |
| Directory | /workspace/47.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.2010166617 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 168671782542 ps |
| CPU time | 93.47 seconds |
| Started | Feb 07 12:36:46 PM PST 24 |
| Finished | Feb 07 12:38:21 PM PST 24 |
| Peak memory | 182244 kb |
| Host | smart-eb8dd998-2623-419d-98c9-1c9b870d02d9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010166617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_cfg_update_on_fly.2010166617 |
| Directory | /workspace/48.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/48.rv_timer_disabled.2363541466 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 76120536122 ps |
| CPU time | 116.64 seconds |
| Started | Feb 07 12:36:47 PM PST 24 |
| Finished | Feb 07 12:38:44 PM PST 24 |
| Peak memory | 182368 kb |
| Host | smart-9f436e11-ec54-4dc2-be20-0dac9e8efb76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2363541466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.2363541466 |
| Directory | /workspace/48.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/48.rv_timer_random_reset.1433967480 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 90064240549 ps |
| CPU time | 68.72 seconds |
| Started | Feb 07 12:36:34 PM PST 24 |
| Finished | Feb 07 12:37:44 PM PST 24 |
| Peak memory | 190488 kb |
| Host | smart-eadc5285-54b3-4458-a1c2-a504c2eea367 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1433967480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1433967480 |
| Directory | /workspace/48.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.3880625935 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 218235892211 ps |
| CPU time | 1166.3 seconds |
| Started | Feb 07 12:36:45 PM PST 24 |
| Finished | Feb 07 12:56:12 PM PST 24 |
| Peak memory | 205292 kb |
| Host | smart-752cf9de-d83a-40c6-9bf8-20f255468d29 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880625935 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.3880625935 |
| Directory | /workspace/48.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1178515081 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 292437091320 ps |
| CPU time | 261.33 seconds |
| Started | Feb 07 12:36:48 PM PST 24 |
| Finished | Feb 07 12:41:10 PM PST 24 |
| Peak memory | 182284 kb |
| Host | smart-4608ba5d-f450-4084-a1d4-149366a01856 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178515081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.1178515081 |
| Directory | /workspace/49.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/49.rv_timer_disabled.2526096077 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 534486006389 ps |
| CPU time | 234.18 seconds |
| Started | Feb 07 12:37:35 PM PST 24 |
| Finished | Feb 07 12:41:30 PM PST 24 |
| Peak memory | 180244 kb |
| Host | smart-75135620-0bc4-4916-9305-ffebb646feed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2526096077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.2526096077 |
| Directory | /workspace/49.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/49.rv_timer_random_reset.2875748515 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 13223023840 ps |
| CPU time | 19.01 seconds |
| Started | Feb 07 12:36:40 PM PST 24 |
| Finished | Feb 07 12:37:00 PM PST 24 |
| Peak memory | 190524 kb |
| Host | smart-fece4040-3401-4d05-b682-d2f9d183139f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2875748515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2875748515 |
| Directory | /workspace/49.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/49.rv_timer_stress_all.1225288503 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 405806760555 ps |
| CPU time | 152.68 seconds |
| Started | Feb 07 12:36:25 PM PST 24 |
| Finished | Feb 07 12:38:58 PM PST 24 |
| Peak memory | 193972 kb |
| Host | smart-bba4a8c4-b7b4-4c8f-87c6-a2c75d12c7ec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225288503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all .1225288503 |
| Directory | /workspace/49.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.1083461601 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 350277418699 ps |
| CPU time | 880.79 seconds |
| Started | Feb 07 12:36:36 PM PST 24 |
| Finished | Feb 07 12:51:17 PM PST 24 |
| Peak memory | 208312 kb |
| Host | smart-bd30cc8f-030c-4cc6-bd56-58aacf2cf869 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083461601 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.1083461601 |
| Directory | /workspace/49.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.736374769 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 257310974783 ps |
| CPU time | 468.95 seconds |
| Started | Feb 07 12:36:24 PM PST 24 |
| Finished | Feb 07 12:44:14 PM PST 24 |
| Peak memory | 182328 kb |
| Host | smart-56fcdfe3-6e06-4160-8f09-6ccc36866a11 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736374769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .rv_timer_cfg_update_on_fly.736374769 |
| Directory | /workspace/5.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/5.rv_timer_disabled.3767924538 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 548931152766 ps |
| CPU time | 224.34 seconds |
| Started | Feb 07 12:36:06 PM PST 24 |
| Finished | Feb 07 12:39:52 PM PST 24 |
| Peak memory | 182248 kb |
| Host | smart-a771267f-c654-462b-a5a5-952a1825d3a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3767924538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3767924538 |
| Directory | /workspace/5.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/5.rv_timer_random.2884172075 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 229211757162 ps |
| CPU time | 151.97 seconds |
| Started | Feb 07 12:36:04 PM PST 24 |
| Finished | Feb 07 12:38:37 PM PST 24 |
| Peak memory | 190548 kb |
| Host | smart-233e464a-7e52-430b-8154-00173b3fcdc8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884172075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2884172075 |
| Directory | /workspace/5.rv_timer_random/latest |
| Test location | /workspace/coverage/default/5.rv_timer_random_reset.680756828 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 336871584117 ps |
| CPU time | 171.12 seconds |
| Started | Feb 07 12:36:13 PM PST 24 |
| Finished | Feb 07 12:39:06 PM PST 24 |
| Peak memory | 182464 kb |
| Host | smart-ccde2e24-6e6f-4c84-a53a-4a34a34d19d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=680756828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.680756828 |
| Directory | /workspace/5.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.4166168252 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 62510204617 ps |
| CPU time | 777.29 seconds |
| Started | Feb 07 12:36:04 PM PST 24 |
| Finished | Feb 07 12:49:03 PM PST 24 |
| Peak memory | 197032 kb |
| Host | smart-fbaf62e9-e3c3-404f-889c-24fd21edaa9b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166168252 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.4166168252 |
| Directory | /workspace/5.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/50.rv_timer_random.3861821028 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 45883577169 ps |
| CPU time | 10.86 seconds |
| Started | Feb 07 12:36:37 PM PST 24 |
| Finished | Feb 07 12:36:49 PM PST 24 |
| Peak memory | 182400 kb |
| Host | smart-6568baff-e525-4822-80ec-5185b8786343 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861821028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3861821028 |
| Directory | /workspace/50.rv_timer_random/latest |
| Test location | /workspace/coverage/default/51.rv_timer_random.3219885350 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 108509992276 ps |
| CPU time | 1303.73 seconds |
| Started | Feb 07 12:36:42 PM PST 24 |
| Finished | Feb 07 12:58:26 PM PST 24 |
| Peak memory | 190452 kb |
| Host | smart-38bfeaa8-cef4-4ae7-adea-4936886d0202 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219885350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3219885350 |
| Directory | /workspace/51.rv_timer_random/latest |
| Test location | /workspace/coverage/default/52.rv_timer_random.992039219 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 79272963460 ps |
| CPU time | 130.41 seconds |
| Started | Feb 07 12:37:43 PM PST 24 |
| Finished | Feb 07 12:39:54 PM PST 24 |
| Peak memory | 190208 kb |
| Host | smart-9c5984ee-da8d-4485-9486-de1fa3e62811 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992039219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.992039219 |
| Directory | /workspace/52.rv_timer_random/latest |
| Test location | /workspace/coverage/default/53.rv_timer_random.1364386216 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 82505376229 ps |
| CPU time | 86.59 seconds |
| Started | Feb 07 12:36:36 PM PST 24 |
| Finished | Feb 07 12:38:04 PM PST 24 |
| Peak memory | 182356 kb |
| Host | smart-cff8a7b1-77fc-4d81-81d4-e3369a895adb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364386216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1364386216 |
| Directory | /workspace/53.rv_timer_random/latest |
| Test location | /workspace/coverage/default/54.rv_timer_random.688571754 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 15853320553 ps |
| CPU time | 27 seconds |
| Started | Feb 07 12:36:41 PM PST 24 |
| Finished | Feb 07 12:37:09 PM PST 24 |
| Peak memory | 182256 kb |
| Host | smart-0ee76fdd-990a-47fb-bc59-99ecd80e0b2e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688571754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.688571754 |
| Directory | /workspace/54.rv_timer_random/latest |
| Test location | /workspace/coverage/default/55.rv_timer_random.3723842832 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 333225983750 ps |
| CPU time | 238.96 seconds |
| Started | Feb 07 12:36:55 PM PST 24 |
| Finished | Feb 07 12:40:55 PM PST 24 |
| Peak memory | 190488 kb |
| Host | smart-d8c28e88-1e4e-4a14-8c65-fe41e1a3d53b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723842832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.3723842832 |
| Directory | /workspace/55.rv_timer_random/latest |
| Test location | /workspace/coverage/default/56.rv_timer_random.3448941341 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 37710458141 ps |
| CPU time | 14.71 seconds |
| Started | Feb 07 12:37:35 PM PST 24 |
| Finished | Feb 07 12:37:51 PM PST 24 |
| Peak memory | 180200 kb |
| Host | smart-574baac8-b8bd-437f-b171-319395bcee3a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448941341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3448941341 |
| Directory | /workspace/56.rv_timer_random/latest |
| Test location | /workspace/coverage/default/58.rv_timer_random.2159265115 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 443011663980 ps |
| CPU time | 729.38 seconds |
| Started | Feb 07 12:36:41 PM PST 24 |
| Finished | Feb 07 12:48:51 PM PST 24 |
| Peak memory | 190548 kb |
| Host | smart-74cc4f7b-f1d3-4078-b528-92aa30566a56 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159265115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.2159265115 |
| Directory | /workspace/58.rv_timer_random/latest |
| Test location | /workspace/coverage/default/59.rv_timer_random.1656346300 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 298130191259 ps |
| CPU time | 222.95 seconds |
| Started | Feb 07 12:36:31 PM PST 24 |
| Finished | Feb 07 12:40:15 PM PST 24 |
| Peak memory | 190692 kb |
| Host | smart-8d005cc3-c331-48ea-91d6-f5897bc8f6bc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656346300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1656346300 |
| Directory | /workspace/59.rv_timer_random/latest |
| Test location | /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.2866819665 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 157223950983 ps |
| CPU time | 263.65 seconds |
| Started | Feb 07 12:36:12 PM PST 24 |
| Finished | Feb 07 12:40:38 PM PST 24 |
| Peak memory | 182388 kb |
| Host | smart-51a40597-3bd9-4726-9fa8-db0897b56822 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866819665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.2866819665 |
| Directory | /workspace/6.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/6.rv_timer_disabled.2502156294 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 594264308707 ps |
| CPU time | 259.81 seconds |
| Started | Feb 07 12:36:04 PM PST 24 |
| Finished | Feb 07 12:40:25 PM PST 24 |
| Peak memory | 182352 kb |
| Host | smart-787d1a94-0e35-46db-8cac-c91da90923c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2502156294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2502156294 |
| Directory | /workspace/6.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/6.rv_timer_random_reset.3671655361 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 22083568243 ps |
| CPU time | 238.22 seconds |
| Started | Feb 07 12:36:13 PM PST 24 |
| Finished | Feb 07 12:40:13 PM PST 24 |
| Peak memory | 181608 kb |
| Host | smart-d295f34c-bf4a-4914-8b64-fcf783bce954 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3671655361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3671655361 |
| Directory | /workspace/6.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.3668578699 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 36604031059 ps |
| CPU time | 318.6 seconds |
| Started | Feb 07 12:36:26 PM PST 24 |
| Finished | Feb 07 12:41:46 PM PST 24 |
| Peak memory | 205252 kb |
| Host | smart-64ddabfd-875d-4f20-8a64-4f1a560be81c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668578699 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.3668578699 |
| Directory | /workspace/6.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/64.rv_timer_random.3245887774 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 421263908327 ps |
| CPU time | 400.14 seconds |
| Started | Feb 07 12:36:30 PM PST 24 |
| Finished | Feb 07 12:43:12 PM PST 24 |
| Peak memory | 190600 kb |
| Host | smart-7d3e64d7-2196-4233-b97c-b077faf80129 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245887774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3245887774 |
| Directory | /workspace/64.rv_timer_random/latest |
| Test location | /workspace/coverage/default/65.rv_timer_random.2836443796 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 88400802029 ps |
| CPU time | 85.69 seconds |
| Started | Feb 07 12:36:47 PM PST 24 |
| Finished | Feb 07 12:38:13 PM PST 24 |
| Peak memory | 190508 kb |
| Host | smart-6aaa545d-10b2-4eab-a901-30169a335947 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836443796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2836443796 |
| Directory | /workspace/65.rv_timer_random/latest |
| Test location | /workspace/coverage/default/67.rv_timer_random.1289237906 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 25879307378 ps |
| CPU time | 46.62 seconds |
| Started | Feb 07 12:37:40 PM PST 24 |
| Finished | Feb 07 12:38:28 PM PST 24 |
| Peak memory | 182096 kb |
| Host | smart-527147f0-73fc-49c5-a468-4d7a93ef96a0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289237906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1289237906 |
| Directory | /workspace/67.rv_timer_random/latest |
| Test location | /workspace/coverage/default/68.rv_timer_random.1024819835 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 128881953778 ps |
| CPU time | 683.65 seconds |
| Started | Feb 07 12:36:43 PM PST 24 |
| Finished | Feb 07 12:48:08 PM PST 24 |
| Peak memory | 192676 kb |
| Host | smart-00f648d6-604b-4e77-954c-9c8e87ec02e8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024819835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1024819835 |
| Directory | /workspace/68.rv_timer_random/latest |
| Test location | /workspace/coverage/default/69.rv_timer_random.2284862655 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 151827969599 ps |
| CPU time | 162.52 seconds |
| Started | Feb 07 12:36:30 PM PST 24 |
| Finished | Feb 07 12:39:14 PM PST 24 |
| Peak memory | 194324 kb |
| Host | smart-b2da7f1f-0d12-435a-b545-a259a4475f61 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284862655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2284862655 |
| Directory | /workspace/69.rv_timer_random/latest |
| Test location | /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3817100550 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 227188935955 ps |
| CPU time | 372.77 seconds |
| Started | Feb 07 12:36:11 PM PST 24 |
| Finished | Feb 07 12:42:27 PM PST 24 |
| Peak memory | 182296 kb |
| Host | smart-5b46446d-e7ae-4757-a66c-e673eb94582b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817100550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.3817100550 |
| Directory | /workspace/7.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/7.rv_timer_disabled.497927162 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 119295967080 ps |
| CPU time | 181.22 seconds |
| Started | Feb 07 12:36:06 PM PST 24 |
| Finished | Feb 07 12:39:09 PM PST 24 |
| Peak memory | 182252 kb |
| Host | smart-5e555493-93b4-4c26-aec6-5b04b4472a20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=497927162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.497927162 |
| Directory | /workspace/7.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/7.rv_timer_random.3670103402 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 555400769918 ps |
| CPU time | 374.54 seconds |
| Started | Feb 07 12:36:12 PM PST 24 |
| Finished | Feb 07 12:42:29 PM PST 24 |
| Peak memory | 193604 kb |
| Host | smart-95665378-cc05-4fd9-af25-26090f6f519f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670103402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3670103402 |
| Directory | /workspace/7.rv_timer_random/latest |
| Test location | /workspace/coverage/default/7.rv_timer_random_reset.2440257685 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 24759982 ps |
| CPU time | 0.54 seconds |
| Started | Feb 07 12:36:06 PM PST 24 |
| Finished | Feb 07 12:36:08 PM PST 24 |
| Peak memory | 182000 kb |
| Host | smart-e513fcff-d176-44f5-9b8b-8b57cb4e90b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2440257685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2440257685 |
| Directory | /workspace/7.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.156786513 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 56518847947 ps |
| CPU time | 215.44 seconds |
| Started | Feb 07 12:36:29 PM PST 24 |
| Finished | Feb 07 12:40:06 PM PST 24 |
| Peak memory | 197064 kb |
| Host | smart-f6c9e677-0fdd-4031-939d-23c16cc7e1f8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156786513 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.156786513 |
| Directory | /workspace/7.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/70.rv_timer_random.13262593 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 114987622572 ps |
| CPU time | 92.82 seconds |
| Started | Feb 07 12:36:42 PM PST 24 |
| Finished | Feb 07 12:38:16 PM PST 24 |
| Peak memory | 190508 kb |
| Host | smart-d9f805ab-402b-43e5-abc7-6cba809eda7d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13262593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.13262593 |
| Directory | /workspace/70.rv_timer_random/latest |
| Test location | /workspace/coverage/default/71.rv_timer_random.796337969 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 97753953410 ps |
| CPU time | 479.7 seconds |
| Started | Feb 07 12:36:45 PM PST 24 |
| Finished | Feb 07 12:44:46 PM PST 24 |
| Peak memory | 190616 kb |
| Host | smart-f54f7988-54c3-4c6a-97b3-d5125b416abb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796337969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.796337969 |
| Directory | /workspace/71.rv_timer_random/latest |
| Test location | /workspace/coverage/default/72.rv_timer_random.2019314873 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 8740775669 ps |
| CPU time | 8.55 seconds |
| Started | Feb 07 12:36:35 PM PST 24 |
| Finished | Feb 07 12:36:45 PM PST 24 |
| Peak memory | 182396 kb |
| Host | smart-90a58a14-7891-4661-824e-0e6da383e666 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019314873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2019314873 |
| Directory | /workspace/72.rv_timer_random/latest |
| Test location | /workspace/coverage/default/73.rv_timer_random.904163955 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 708970789638 ps |
| CPU time | 223.64 seconds |
| Started | Feb 07 12:36:53 PM PST 24 |
| Finished | Feb 07 12:40:37 PM PST 24 |
| Peak memory | 190552 kb |
| Host | smart-b29123f9-37d6-40d5-9133-9062db148652 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904163955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.904163955 |
| Directory | /workspace/73.rv_timer_random/latest |
| Test location | /workspace/coverage/default/74.rv_timer_random.4149845295 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 33835870985 ps |
| CPU time | 687.89 seconds |
| Started | Feb 07 12:36:37 PM PST 24 |
| Finished | Feb 07 12:48:06 PM PST 24 |
| Peak memory | 190520 kb |
| Host | smart-550b80e1-c1d5-468a-915c-b0f77403c0a2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149845295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.4149845295 |
| Directory | /workspace/74.rv_timer_random/latest |
| Test location | /workspace/coverage/default/75.rv_timer_random.1816241224 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 451704140174 ps |
| CPU time | 265.67 seconds |
| Started | Feb 07 12:36:46 PM PST 24 |
| Finished | Feb 07 12:41:12 PM PST 24 |
| Peak memory | 190572 kb |
| Host | smart-406e53be-29a2-4a88-ab39-38b01f9d9927 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816241224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1816241224 |
| Directory | /workspace/75.rv_timer_random/latest |
| Test location | /workspace/coverage/default/76.rv_timer_random.2008203094 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 272906763201 ps |
| CPU time | 556.58 seconds |
| Started | Feb 07 12:36:45 PM PST 24 |
| Finished | Feb 07 12:46:03 PM PST 24 |
| Peak memory | 190700 kb |
| Host | smart-c7b84da8-3a7a-4dd5-be83-c4c162511474 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008203094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.2008203094 |
| Directory | /workspace/76.rv_timer_random/latest |
| Test location | /workspace/coverage/default/77.rv_timer_random.1151146309 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 367987144965 ps |
| CPU time | 536.67 seconds |
| Started | Feb 07 12:36:47 PM PST 24 |
| Finished | Feb 07 12:45:44 PM PST 24 |
| Peak memory | 192784 kb |
| Host | smart-cc8981a0-0d1a-4cbb-97d4-21d116fe0a47 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151146309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1151146309 |
| Directory | /workspace/77.rv_timer_random/latest |
| Test location | /workspace/coverage/default/79.rv_timer_random.50446615 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 663651128521 ps |
| CPU time | 2006.41 seconds |
| Started | Feb 07 12:36:33 PM PST 24 |
| Finished | Feb 07 01:10:01 PM PST 24 |
| Peak memory | 193012 kb |
| Host | smart-055a60eb-648b-4c16-8e2d-35502ae5742b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50446615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.50446615 |
| Directory | /workspace/79.rv_timer_random/latest |
| Test location | /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.2511249978 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 243819671556 ps |
| CPU time | 233.61 seconds |
| Started | Feb 07 12:36:03 PM PST 24 |
| Finished | Feb 07 12:39:58 PM PST 24 |
| Peak memory | 182316 kb |
| Host | smart-45281936-d8c1-4c15-a2f0-1698048b756a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511249978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_cfg_update_on_fly.2511249978 |
| Directory | /workspace/8.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/8.rv_timer_disabled.2138657149 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 35833843839 ps |
| CPU time | 49.51 seconds |
| Started | Feb 07 12:36:32 PM PST 24 |
| Finished | Feb 07 12:37:22 PM PST 24 |
| Peak memory | 182316 kb |
| Host | smart-4e15f13a-7dc4-4100-89db-54332a9bcb84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2138657149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2138657149 |
| Directory | /workspace/8.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/8.rv_timer_random.2101113061 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 24122494080 ps |
| CPU time | 42.91 seconds |
| Started | Feb 07 12:36:27 PM PST 24 |
| Finished | Feb 07 12:37:11 PM PST 24 |
| Peak memory | 182336 kb |
| Host | smart-0d6ace21-e5ca-46c2-80d9-2305afe91024 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101113061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2101113061 |
| Directory | /workspace/8.rv_timer_random/latest |
| Test location | /workspace/coverage/default/8.rv_timer_random_reset.2466086742 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 112824142350 ps |
| CPU time | 92.63 seconds |
| Started | Feb 07 12:36:13 PM PST 24 |
| Finished | Feb 07 12:37:52 PM PST 24 |
| Peak memory | 182364 kb |
| Host | smart-2ddef52c-38ea-4044-8faa-58e1fb1c15c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2466086742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2466086742 |
| Directory | /workspace/8.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/8.rv_timer_stress_all.3101950631 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 641031842941 ps |
| CPU time | 1275.49 seconds |
| Started | Feb 07 12:36:04 PM PST 24 |
| Finished | Feb 07 12:57:21 PM PST 24 |
| Peak memory | 190500 kb |
| Host | smart-ee19e381-347c-485f-8ee1-d665628e4fe4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101950631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all. 3101950631 |
| Directory | /workspace/8.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/80.rv_timer_random.3536550732 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 104963197153 ps |
| CPU time | 468.88 seconds |
| Started | Feb 07 12:36:45 PM PST 24 |
| Finished | Feb 07 12:44:36 PM PST 24 |
| Peak memory | 190556 kb |
| Host | smart-dde0b1aa-cf26-443c-87e2-a177062aa4fb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536550732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3536550732 |
| Directory | /workspace/80.rv_timer_random/latest |
| Test location | /workspace/coverage/default/82.rv_timer_random.3988525808 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 112261209164 ps |
| CPU time | 403.58 seconds |
| Started | Feb 07 12:36:32 PM PST 24 |
| Finished | Feb 07 12:43:16 PM PST 24 |
| Peak memory | 190596 kb |
| Host | smart-f1920f97-6473-4e0a-8350-a3ad3e270685 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988525808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3988525808 |
| Directory | /workspace/82.rv_timer_random/latest |
| Test location | /workspace/coverage/default/83.rv_timer_random.307565066 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 181792282270 ps |
| CPU time | 170.07 seconds |
| Started | Feb 07 12:36:50 PM PST 24 |
| Finished | Feb 07 12:39:41 PM PST 24 |
| Peak memory | 190680 kb |
| Host | smart-8ba8c588-5de5-4721-b8e1-3a9d3a0ec420 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307565066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.307565066 |
| Directory | /workspace/83.rv_timer_random/latest |
| Test location | /workspace/coverage/default/84.rv_timer_random.734740129 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 155752831184 ps |
| CPU time | 346.54 seconds |
| Started | Feb 07 12:36:36 PM PST 24 |
| Finished | Feb 07 12:42:24 PM PST 24 |
| Peak memory | 182392 kb |
| Host | smart-06c44abb-94ba-47be-b9aa-6f208278b8f5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734740129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.734740129 |
| Directory | /workspace/84.rv_timer_random/latest |
| Test location | /workspace/coverage/default/85.rv_timer_random.447619842 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 38657270216 ps |
| CPU time | 31.13 seconds |
| Started | Feb 07 12:36:50 PM PST 24 |
| Finished | Feb 07 12:37:22 PM PST 24 |
| Peak memory | 182400 kb |
| Host | smart-0eed7ff5-0215-4bb4-a273-793a0e5b8080 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447619842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.447619842 |
| Directory | /workspace/85.rv_timer_random/latest |
| Test location | /workspace/coverage/default/86.rv_timer_random.1807437523 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 285035943524 ps |
| CPU time | 456 seconds |
| Started | Feb 07 12:36:44 PM PST 24 |
| Finished | Feb 07 12:44:21 PM PST 24 |
| Peak memory | 193036 kb |
| Host | smart-18544381-8f5e-427c-84d5-ad86bebdee94 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807437523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.1807437523 |
| Directory | /workspace/86.rv_timer_random/latest |
| Test location | /workspace/coverage/default/88.rv_timer_random.1897960593 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 49017939439 ps |
| CPU time | 110.52 seconds |
| Started | Feb 07 12:36:44 PM PST 24 |
| Finished | Feb 07 12:38:36 PM PST 24 |
| Peak memory | 182416 kb |
| Host | smart-142126b7-e212-4ff1-b742-260102f6450c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897960593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1897960593 |
| Directory | /workspace/88.rv_timer_random/latest |
| Test location | /workspace/coverage/default/89.rv_timer_random.4140088874 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 155525150898 ps |
| CPU time | 423.54 seconds |
| Started | Feb 07 12:36:47 PM PST 24 |
| Finished | Feb 07 12:43:51 PM PST 24 |
| Peak memory | 190516 kb |
| Host | smart-166722e7-7aaa-4548-85a6-cc3e8ec37865 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140088874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.4140088874 |
| Directory | /workspace/89.rv_timer_random/latest |
| Test location | /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.818309736 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 107865950413 ps |
| CPU time | 190.91 seconds |
| Started | Feb 07 12:36:07 PM PST 24 |
| Finished | Feb 07 12:39:19 PM PST 24 |
| Peak memory | 182376 kb |
| Host | smart-effbc379-aa2b-4b70-92a7-a1d15ebe74e2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818309736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .rv_timer_cfg_update_on_fly.818309736 |
| Directory | /workspace/9.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/9.rv_timer_disabled.1436949416 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 337905839337 ps |
| CPU time | 125.48 seconds |
| Started | Feb 07 12:36:02 PM PST 24 |
| Finished | Feb 07 12:38:09 PM PST 24 |
| Peak memory | 182324 kb |
| Host | smart-2de71368-9527-4524-b168-ed7efa98a375 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1436949416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1436949416 |
| Directory | /workspace/9.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/9.rv_timer_random.292773392 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 430031349064 ps |
| CPU time | 536.75 seconds |
| Started | Feb 07 12:36:10 PM PST 24 |
| Finished | Feb 07 12:45:11 PM PST 24 |
| Peak memory | 190524 kb |
| Host | smart-98f89e25-a648-4812-bc05-dcfe5f38e819 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292773392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.292773392 |
| Directory | /workspace/9.rv_timer_random/latest |
| Test location | /workspace/coverage/default/9.rv_timer_random_reset.205281112 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 38731388225 ps |
| CPU time | 21.64 seconds |
| Started | Feb 07 12:36:11 PM PST 24 |
| Finished | Feb 07 12:36:36 PM PST 24 |
| Peak memory | 190552 kb |
| Host | smart-edb5a93e-0d00-43e2-9424-03f3af94e70d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=205281112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.205281112 |
| Directory | /workspace/9.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.3845452962 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 381487495534 ps |
| CPU time | 1185.99 seconds |
| Started | Feb 07 12:36:37 PM PST 24 |
| Finished | Feb 07 12:56:24 PM PST 24 |
| Peak memory | 211968 kb |
| Host | smart-1a9bf3ff-cff5-4d14-a8de-4f6f70a86824 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845452962 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.3845452962 |
| Directory | /workspace/9.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/90.rv_timer_random.1187589784 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 478346745379 ps |
| CPU time | 485.14 seconds |
| Started | Feb 07 12:36:39 PM PST 24 |
| Finished | Feb 07 12:44:45 PM PST 24 |
| Peak memory | 193004 kb |
| Host | smart-39f04bf7-8b26-49af-9ca3-f2cfe75b1295 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187589784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1187589784 |
| Directory | /workspace/90.rv_timer_random/latest |
| Test location | /workspace/coverage/default/91.rv_timer_random.1395123570 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 1333733488384 ps |
| CPU time | 737.51 seconds |
| Started | Feb 07 12:36:28 PM PST 24 |
| Finished | Feb 07 12:48:46 PM PST 24 |
| Peak memory | 190476 kb |
| Host | smart-5bc50f45-2d7a-4bda-ac63-6c989c03c804 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395123570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1395123570 |
| Directory | /workspace/91.rv_timer_random/latest |
| Test location | /workspace/coverage/default/93.rv_timer_random.2088684758 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 9114512069 ps |
| CPU time | 46.41 seconds |
| Started | Feb 07 12:36:56 PM PST 24 |
| Finished | Feb 07 12:37:43 PM PST 24 |
| Peak memory | 182396 kb |
| Host | smart-39fa25e3-2dd2-4687-b347-48f0e01b7451 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088684758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2088684758 |
| Directory | /workspace/93.rv_timer_random/latest |
| Test location | /workspace/coverage/default/94.rv_timer_random.1030138382 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 394604285933 ps |
| CPU time | 289.28 seconds |
| Started | Feb 07 12:36:47 PM PST 24 |
| Finished | Feb 07 12:41:37 PM PST 24 |
| Peak memory | 190596 kb |
| Host | smart-4be370d6-813c-45ec-865a-5bd6a2ea3b7c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030138382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1030138382 |
| Directory | /workspace/94.rv_timer_random/latest |
| Test location | /workspace/coverage/default/95.rv_timer_random.4062259270 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 568880532090 ps |
| CPU time | 618.56 seconds |
| Started | Feb 07 12:36:47 PM PST 24 |
| Finished | Feb 07 12:47:07 PM PST 24 |
| Peak memory | 190600 kb |
| Host | smart-0ddf72e2-f8b8-43f9-8927-4afc69ed798f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062259270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.4062259270 |
| Directory | /workspace/95.rv_timer_random/latest |
| Test location | /workspace/coverage/default/96.rv_timer_random.3167584127 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 215540730226 ps |
| CPU time | 103.54 seconds |
| Started | Feb 07 12:36:37 PM PST 24 |
| Finished | Feb 07 12:38:21 PM PST 24 |
| Peak memory | 191800 kb |
| Host | smart-06e368fe-a9b2-436b-981b-db81bd127b0b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167584127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3167584127 |
| Directory | /workspace/96.rv_timer_random/latest |
| Test location | /workspace/coverage/default/97.rv_timer_random.2407564987 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 469631742406 ps |
| CPU time | 153.51 seconds |
| Started | Feb 07 12:36:45 PM PST 24 |
| Finished | Feb 07 12:39:19 PM PST 24 |
| Peak memory | 190556 kb |
| Host | smart-853c501b-c884-4c4f-9c8b-a5c1fc18af81 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407564987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2407564987 |
| Directory | /workspace/97.rv_timer_random/latest |
| Test location | /workspace/coverage/default/98.rv_timer_random.1378018646 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 403084332291 ps |
| CPU time | 455.1 seconds |
| Started | Feb 07 12:36:45 PM PST 24 |
| Finished | Feb 07 12:44:22 PM PST 24 |
| Peak memory | 190592 kb |
| Host | smart-a183e106-d652-4bee-ac26-0e5aacf52ca1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378018646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1378018646 |
| Directory | /workspace/98.rv_timer_random/latest |
| Test location | /workspace/coverage/default/99.rv_timer_random.4140847923 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 296899893283 ps |
| CPU time | 163.6 seconds |
| Started | Feb 07 12:36:36 PM PST 24 |
| Finished | Feb 07 12:39:21 PM PST 24 |
| Peak memory | 190552 kb |
| Host | smart-ce571738-f2cf-4bb4-9b5a-c26565259d30 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140847923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.4140847923 |
| Directory | /workspace/99.rv_timer_random/latest |
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