Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.51 99.36 98.73 100.00 100.00 100.00 98.98


Total test records in report: 601
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T509 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.4101061472 Feb 18 12:28:20 PM PST 24 Feb 18 12:28:27 PM PST 24 147517591 ps
T510 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.454760049 Feb 18 12:28:07 PM PST 24 Feb 18 12:28:15 PM PST 24 69139975 ps
T511 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3843691128 Feb 18 12:28:23 PM PST 24 Feb 18 12:28:30 PM PST 24 91685999 ps
T512 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1784551168 Feb 18 12:28:36 PM PST 24 Feb 18 12:28:39 PM PST 24 31961755 ps
T98 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1579642577 Feb 18 12:28:13 PM PST 24 Feb 18 12:28:19 PM PST 24 30359607 ps
T99 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2879957010 Feb 18 12:28:20 PM PST 24 Feb 18 12:28:27 PM PST 24 106288055 ps
T513 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1625608802 Feb 18 12:28:04 PM PST 24 Feb 18 12:28:10 PM PST 24 250511755 ps
T514 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1494664706 Feb 18 12:28:05 PM PST 24 Feb 18 12:28:11 PM PST 24 12024925 ps
T515 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.8761575 Feb 18 12:28:40 PM PST 24 Feb 18 12:28:44 PM PST 24 15823744 ps
T516 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.4136545214 Feb 18 12:35:19 PM PST 24 Feb 18 12:35:23 PM PST 24 59531607 ps
T517 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1844181718 Feb 18 12:28:10 PM PST 24 Feb 18 12:28:17 PM PST 24 15537167 ps
T518 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1287486465 Feb 18 12:28:12 PM PST 24 Feb 18 12:28:21 PM PST 24 156880386 ps
T519 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.4189711028 Feb 18 12:28:35 PM PST 24 Feb 18 12:28:37 PM PST 24 16536860 ps
T520 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1367476736 Feb 18 12:28:36 PM PST 24 Feb 18 12:28:38 PM PST 24 74677106 ps
T521 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1365593996 Feb 18 12:28:39 PM PST 24 Feb 18 12:28:43 PM PST 24 97383825 ps
T522 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2296384044 Feb 18 12:28:32 PM PST 24 Feb 18 12:28:36 PM PST 24 1745693776 ps
T523 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2531047952 Feb 18 12:28:13 PM PST 24 Feb 18 12:28:24 PM PST 24 47429500 ps
T524 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2346423585 Feb 18 12:28:24 PM PST 24 Feb 18 12:28:31 PM PST 24 167541256 ps
T525 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3856301289 Feb 18 12:28:28 PM PST 24 Feb 18 12:28:33 PM PST 24 23145192 ps
T526 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3353259960 Feb 18 12:28:15 PM PST 24 Feb 18 12:28:22 PM PST 24 136176617 ps
T527 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.344664587 Feb 18 12:28:05 PM PST 24 Feb 18 12:28:12 PM PST 24 174923152 ps
T528 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2868444713 Feb 18 12:28:15 PM PST 24 Feb 18 12:28:21 PM PST 24 14697653 ps
T529 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3455988166 Feb 18 12:28:32 PM PST 24 Feb 18 12:28:35 PM PST 24 17692605 ps
T530 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1489214406 Feb 18 12:28:22 PM PST 24 Feb 18 12:28:30 PM PST 24 22859328 ps
T531 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2853801236 Feb 18 12:28:07 PM PST 24 Feb 18 12:28:15 PM PST 24 174335865 ps
T532 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.4253906614 Feb 18 12:28:04 PM PST 24 Feb 18 12:28:10 PM PST 24 424646571 ps
T533 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1141527498 Feb 18 12:28:20 PM PST 24 Feb 18 12:28:27 PM PST 24 60819440 ps
T534 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1036220189 Feb 18 12:28:37 PM PST 24 Feb 18 12:28:41 PM PST 24 31875247 ps
T535 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1298769756 Feb 18 12:28:07 PM PST 24 Feb 18 12:28:14 PM PST 24 134428271 ps
T536 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3820604661 Feb 18 12:28:37 PM PST 24 Feb 18 12:28:41 PM PST 24 230771047 ps
T537 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3767688238 Feb 18 12:28:43 PM PST 24 Feb 18 12:28:47 PM PST 24 45241549 ps
T115 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3339728518 Feb 18 12:28:33 PM PST 24 Feb 18 12:28:36 PM PST 24 59001306 ps
T538 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.4022835654 Feb 18 12:28:20 PM PST 24 Feb 18 12:28:26 PM PST 24 63866261 ps
T539 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3698979610 Feb 18 12:28:30 PM PST 24 Feb 18 12:28:34 PM PST 24 16014342 ps
T540 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1926095828 Feb 18 12:28:13 PM PST 24 Feb 18 12:28:19 PM PST 24 22649237 ps
T541 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1811097812 Feb 18 12:28:07 PM PST 24 Feb 18 12:28:16 PM PST 24 181045627 ps
T542 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3263179244 Feb 18 12:28:13 PM PST 24 Feb 18 12:28:20 PM PST 24 666686733 ps
T543 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1868989686 Feb 18 12:28:22 PM PST 24 Feb 18 12:28:30 PM PST 24 87085066 ps
T544 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1379094742 Feb 18 12:28:32 PM PST 24 Feb 18 12:28:35 PM PST 24 47644316 ps
T545 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3824518290 Feb 18 12:28:23 PM PST 24 Feb 18 12:28:30 PM PST 24 32520309 ps
T546 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2520028694 Feb 18 12:28:22 PM PST 24 Feb 18 12:28:30 PM PST 24 331561125 ps
T547 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1613424626 Feb 18 12:28:17 PM PST 24 Feb 18 12:28:26 PM PST 24 291420177 ps
T548 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3048867833 Feb 18 12:28:21 PM PST 24 Feb 18 12:28:29 PM PST 24 15528686 ps
T549 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1656975814 Feb 18 12:28:12 PM PST 24 Feb 18 12:28:28 PM PST 24 62651614 ps
T550 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2876858863 Feb 18 12:28:34 PM PST 24 Feb 18 12:28:38 PM PST 24 129977294 ps
T551 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3227546316 Feb 18 12:28:43 PM PST 24 Feb 18 12:28:46 PM PST 24 92037248 ps
T552 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2840741391 Feb 18 12:28:08 PM PST 24 Feb 18 12:28:16 PM PST 24 30676114 ps
T553 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2728679310 Feb 18 12:28:26 PM PST 24 Feb 18 12:28:32 PM PST 24 15350010 ps
T554 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3871487136 Feb 18 12:28:09 PM PST 24 Feb 18 12:28:17 PM PST 24 15596263 ps
T555 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2093120076 Feb 18 12:28:19 PM PST 24 Feb 18 12:28:27 PM PST 24 326877165 ps
T109 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2258322801 Feb 18 12:28:12 PM PST 24 Feb 18 12:28:19 PM PST 24 54015473 ps
T556 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.893852187 Feb 18 12:28:16 PM PST 24 Feb 18 12:28:23 PM PST 24 67051297 ps
T557 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1000102801 Feb 18 12:28:21 PM PST 24 Feb 18 12:28:28 PM PST 24 57851983 ps
T85 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3535834082 Feb 18 12:28:21 PM PST 24 Feb 18 12:28:28 PM PST 24 36305707 ps
T558 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1718433857 Feb 18 12:28:11 PM PST 24 Feb 18 12:28:18 PM PST 24 73117941 ps
T559 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.898674880 Feb 18 12:28:22 PM PST 24 Feb 18 12:28:31 PM PST 24 1249164595 ps
T560 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1173758135 Feb 18 12:28:21 PM PST 24 Feb 18 12:28:29 PM PST 24 194801243 ps
T561 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3550412053 Feb 18 12:28:33 PM PST 24 Feb 18 12:28:36 PM PST 24 33917047 ps
T86 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1548595531 Feb 18 12:28:07 PM PST 24 Feb 18 12:28:14 PM PST 24 25944977 ps
T562 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.481551057 Feb 18 12:28:34 PM PST 24 Feb 18 12:28:37 PM PST 24 295872654 ps
T563 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1271042516 Feb 18 12:28:17 PM PST 24 Feb 18 12:28:25 PM PST 24 554957967 ps
T564 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.86687797 Feb 18 12:28:17 PM PST 24 Feb 18 12:28:23 PM PST 24 18019827 ps
T565 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.4257176371 Feb 18 12:28:39 PM PST 24 Feb 18 12:28:43 PM PST 24 126786944 ps
T566 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2271492075 Feb 18 12:28:45 PM PST 24 Feb 18 12:28:49 PM PST 24 17171407 ps
T567 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3751043842 Feb 18 12:28:37 PM PST 24 Feb 18 12:28:40 PM PST 24 38761209 ps
T568 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.130320985 Feb 18 12:28:23 PM PST 24 Feb 18 12:28:30 PM PST 24 32902063 ps
T569 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.923989985 Feb 18 12:28:31 PM PST 24 Feb 18 12:28:34 PM PST 24 28658139 ps
T570 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3243218809 Feb 18 12:28:22 PM PST 24 Feb 18 12:28:29 PM PST 24 67269070 ps
T571 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1418674865 Feb 18 12:28:21 PM PST 24 Feb 18 12:28:29 PM PST 24 12468028 ps
T572 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3969479736 Feb 18 12:28:20 PM PST 24 Feb 18 12:28:31 PM PST 24 13562297 ps
T573 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2547624832 Feb 18 12:28:13 PM PST 24 Feb 18 12:28:21 PM PST 24 55242493 ps
T574 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.51765527 Feb 18 12:28:17 PM PST 24 Feb 18 12:28:23 PM PST 24 13007380 ps
T575 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1857424518 Feb 18 12:28:13 PM PST 24 Feb 18 12:28:20 PM PST 24 39703515 ps
T87 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3770973147 Feb 18 12:28:20 PM PST 24 Feb 18 12:28:26 PM PST 24 12897557 ps
T88 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.352699125 Feb 18 12:28:20 PM PST 24 Feb 18 12:28:26 PM PST 24 15090330 ps
T576 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3536680365 Feb 18 12:28:37 PM PST 24 Feb 18 12:28:40 PM PST 24 111279130 ps
T577 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3868785474 Feb 18 12:28:27 PM PST 24 Feb 18 12:28:33 PM PST 24 12975396 ps
T578 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2384930267 Feb 18 12:28:14 PM PST 24 Feb 18 12:28:21 PM PST 24 25045675 ps
T579 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2745837079 Feb 18 12:28:19 PM PST 24 Feb 18 12:28:28 PM PST 24 207132293 ps
T580 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1142393658 Feb 18 12:28:44 PM PST 24 Feb 18 12:28:48 PM PST 24 33471560 ps
T581 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1140178325 Feb 18 12:28:30 PM PST 24 Feb 18 12:28:34 PM PST 24 81156406 ps
T582 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1513291850 Feb 18 12:28:10 PM PST 24 Feb 18 12:28:17 PM PST 24 34384233 ps
T583 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2537158304 Feb 18 12:28:42 PM PST 24 Feb 18 12:28:45 PM PST 24 146324163 ps
T584 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.4046621321 Feb 18 12:28:06 PM PST 24 Feb 18 12:28:14 PM PST 24 141004069 ps
T585 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3229771644 Feb 18 12:28:13 PM PST 24 Feb 18 12:28:19 PM PST 24 45041547 ps
T586 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3440982232 Feb 18 12:28:32 PM PST 24 Feb 18 12:28:37 PM PST 24 154722309 ps
T587 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2755971655 Feb 18 12:28:18 PM PST 24 Feb 18 12:28:24 PM PST 24 48882837 ps
T588 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1321485783 Feb 18 12:28:32 PM PST 24 Feb 18 12:28:36 PM PST 24 50738000 ps
T589 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.340062024 Feb 18 12:28:39 PM PST 24 Feb 18 12:28:41 PM PST 24 24677690 ps
T590 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2123224930 Feb 18 12:28:34 PM PST 24 Feb 18 12:28:37 PM PST 24 16873316 ps
T591 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1664154682 Feb 18 12:28:20 PM PST 24 Feb 18 12:28:26 PM PST 24 90456256 ps
T592 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.924708287 Feb 18 12:28:23 PM PST 24 Feb 18 12:28:30 PM PST 24 30770599 ps
T593 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1825709014 Feb 18 12:28:27 PM PST 24 Feb 18 12:28:33 PM PST 24 48463701 ps
T594 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2519856561 Feb 18 12:28:12 PM PST 24 Feb 18 12:28:19 PM PST 24 45389002 ps
T595 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.456883553 Feb 18 12:28:12 PM PST 24 Feb 18 12:28:18 PM PST 24 53855058 ps
T596 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3509983262 Feb 18 12:28:30 PM PST 24 Feb 18 12:28:34 PM PST 24 31082805 ps
T597 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.420369193 Feb 18 12:28:12 PM PST 24 Feb 18 12:28:19 PM PST 24 18889515 ps
T598 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.186080016 Feb 18 12:28:13 PM PST 24 Feb 18 12:28:19 PM PST 24 41439087 ps
T599 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3501513278 Feb 18 12:28:11 PM PST 24 Feb 18 12:28:18 PM PST 24 27265577 ps
T600 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2441727953 Feb 18 12:28:38 PM PST 24 Feb 18 12:28:41 PM PST 24 101542374 ps
T601 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.720627378 Feb 18 12:28:40 PM PST 24 Feb 18 12:28:44 PM PST 24 15571203 ps

Test location /workspace/coverage/default/54.rv_timer_random.722857311
Short name T8
Test name
Test status
Simulation time 164167910709 ps
CPU time 164.78 seconds
Started Feb 18 12:31:13 PM PST 24
Finished Feb 18 12:33:59 PM PST 24
Peak memory 190528 kb
Host smart-4dc919a5-ac5e-44cf-9edc-dd238fb2087e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722857311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.722857311
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.594854759
Short name T13
Test name
Test status
Simulation time 469089243424 ps
CPU time 270.9 seconds
Started Feb 18 12:30:46 PM PST 24
Finished Feb 18 12:35:20 PM PST 24
Peak memory 205256 kb
Host smart-5ec35db5-cd41-4b2b-8296-937de68b8816
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594854759 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.594854759
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.3877065439
Short name T22
Test name
Test status
Simulation time 497024163220 ps
CPU time 2546.28 seconds
Started Feb 18 12:30:25 PM PST 24
Finished Feb 18 01:13:01 PM PST 24
Peak memory 190452 kb
Host smart-c5bded2c-dbb6-4e9f-b22c-fa03550b76c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877065439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
3877065439
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.4184970825
Short name T150
Test name
Test status
Simulation time 2710847769299 ps
CPU time 3014.94 seconds
Started Feb 18 12:30:33 PM PST 24
Finished Feb 18 01:20:56 PM PST 24
Peak memory 190344 kb
Host smart-a5257f9f-bf89-45e2-a255-3d4c1c0e4827
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184970825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.4184970825
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1895452944
Short name T28
Test name
Test status
Simulation time 702349191 ps
CPU time 1.12 seconds
Started Feb 18 12:28:19 PM PST 24
Finished Feb 18 12:28:26 PM PST 24
Peak memory 182732 kb
Host smart-b29ab9d5-f881-456b-a3ac-b41efd686bbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895452944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1895452944
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.4184065725
Short name T68
Test name
Test status
Simulation time 609656856874 ps
CPU time 3113.55 seconds
Started Feb 18 12:30:24 PM PST 24
Finished Feb 18 01:22:26 PM PST 24
Peak memory 194768 kb
Host smart-1e8c45ad-63bf-4e7a-8bae-2e6e7925648b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184065725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.4184065725
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.1905653040
Short name T250
Test name
Test status
Simulation time 1005149163929 ps
CPU time 1330.94 seconds
Started Feb 18 12:30:37 PM PST 24
Finished Feb 18 12:52:54 PM PST 24
Peak memory 190544 kb
Host smart-5ef0cda9-e255-4434-9a9a-a5a1096ed371
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905653040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1905653040
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1490042580
Short name T157
Test name
Test status
Simulation time 2000602890151 ps
CPU time 1190.33 seconds
Started Feb 18 12:30:45 PM PST 24
Finished Feb 18 12:50:39 PM PST 24
Peak memory 190456 kb
Host smart-955cc10b-8d40-4949-8e40-830fb337971e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490042580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1490042580
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1402103156
Short name T208
Test name
Test status
Simulation time 1710358050630 ps
CPU time 4300.11 seconds
Started Feb 18 12:30:47 PM PST 24
Finished Feb 18 01:42:30 PM PST 24
Peak memory 190548 kb
Host smart-8cae5007-1fee-4ae2-bd83-259273483b84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402103156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1402103156
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1409694038
Short name T229
Test name
Test status
Simulation time 3606247045897 ps
CPU time 2433.48 seconds
Started Feb 18 12:31:05 PM PST 24
Finished Feb 18 01:11:40 PM PST 24
Peak memory 194260 kb
Host smart-d34b4c89-e0d5-43d8-bb01-6144a34810bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409694038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1409694038
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.392181693
Short name T263
Test name
Test status
Simulation time 365772497733 ps
CPU time 3619.68 seconds
Started Feb 18 12:30:56 PM PST 24
Finished Feb 18 01:31:19 PM PST 24
Peak memory 195872 kb
Host smart-079a0a03-e2ce-49f2-b9d7-d4a3f931fdaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392181693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.
392181693
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/51.rv_timer_random.3747048991
Short name T136
Test name
Test status
Simulation time 165226485202 ps
CPU time 325.92 seconds
Started Feb 18 12:31:13 PM PST 24
Finished Feb 18 12:36:40 PM PST 24
Peak memory 193604 kb
Host smart-da850657-9304-4c2e-a145-7af2ea36865f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747048991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3747048991
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.539478265
Short name T21
Test name
Test status
Simulation time 272220214427 ps
CPU time 208.52 seconds
Started Feb 18 12:31:12 PM PST 24
Finished Feb 18 12:34:42 PM PST 24
Peak memory 192488 kb
Host smart-271add45-7445-43b3-8a8b-4da253f12658
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539478265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.539478265
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.3201636520
Short name T18
Test name
Test status
Simulation time 84902067 ps
CPU time 0.92 seconds
Started Feb 18 12:30:30 PM PST 24
Finished Feb 18 12:30:41 PM PST 24
Peak memory 213624 kb
Host smart-dc4002f8-d937-4349-a2df-3ccfd461b3c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201636520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.3201636520
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.2827127756
Short name T179
Test name
Test status
Simulation time 670473561288 ps
CPU time 1299.06 seconds
Started Feb 18 12:30:24 PM PST 24
Finished Feb 18 12:52:17 PM PST 24
Peak memory 195656 kb
Host smart-17568d43-7491-4931-a162-62f188457e5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827127756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
2827127756
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.1466787772
Short name T120
Test name
Test status
Simulation time 2583253348676 ps
CPU time 2962.01 seconds
Started Feb 18 12:30:48 PM PST 24
Finished Feb 18 01:20:16 PM PST 24
Peak memory 190552 kb
Host smart-461ecdbe-4e20-45cb-b75d-bd3990fbcf59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466787772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.1466787772
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.944209911
Short name T285
Test name
Test status
Simulation time 379102827728 ps
CPU time 1235.1 seconds
Started Feb 18 12:30:53 PM PST 24
Finished Feb 18 12:51:30 PM PST 24
Peak memory 196012 kb
Host smart-4b39dc31-6083-428b-966f-f6af3c562193
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944209911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.
944209911
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.1111037825
Short name T103
Test name
Test status
Simulation time 935905507331 ps
CPU time 1120.38 seconds
Started Feb 18 12:31:07 PM PST 24
Finished Feb 18 12:49:49 PM PST 24
Peak memory 190500 kb
Host smart-565c50d8-69c6-4a36-a598-43d502a8763b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111037825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.1111037825
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/104.rv_timer_random.2647041659
Short name T66
Test name
Test status
Simulation time 390798947678 ps
CPU time 410.59 seconds
Started Feb 18 12:31:17 PM PST 24
Finished Feb 18 12:38:12 PM PST 24
Peak memory 190564 kb
Host smart-33a82872-7e03-4a0f-bce1-875f2c4406ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647041659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2647041659
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.551432172
Short name T74
Test name
Test status
Simulation time 13930235 ps
CPU time 0.64 seconds
Started Feb 18 12:28:24 PM PST 24
Finished Feb 18 12:28:31 PM PST 24
Peak memory 182396 kb
Host smart-767107aa-ddd6-4007-a775-7fd909ed2de9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551432172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.551432172
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1813476044
Short name T199
Test name
Test status
Simulation time 619297386858 ps
CPU time 1528.9 seconds
Started Feb 18 12:30:42 PM PST 24
Finished Feb 18 12:56:15 PM PST 24
Peak memory 190504 kb
Host smart-9704f554-7b29-4303-852d-f04daf491731
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813476044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1813476044
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.24904167
Short name T61
Test name
Test status
Simulation time 4778720271065 ps
CPU time 1265.81 seconds
Started Feb 18 12:30:43 PM PST 24
Finished Feb 18 12:51:52 PM PST 24
Peak memory 190532 kb
Host smart-249131fb-70eb-4bdd-a859-da3a9f957aa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24904167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.24904167
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.4137687447
Short name T182
Test name
Test status
Simulation time 360991649428 ps
CPU time 863.9 seconds
Started Feb 18 12:30:35 PM PST 24
Finished Feb 18 12:45:06 PM PST 24
Peak memory 190492 kb
Host smart-c9ff3366-0c9a-4dea-b0f5-6fe91086fdd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137687447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.4137687447
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/59.rv_timer_random.2805300799
Short name T216
Test name
Test status
Simulation time 3020861672511 ps
CPU time 3572.59 seconds
Started Feb 18 12:30:57 PM PST 24
Finished Feb 18 01:30:33 PM PST 24
Peak memory 190480 kb
Host smart-8972fa1a-eb47-4101-aa96-9664943d38b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805300799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2805300799
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1020483203
Short name T193
Test name
Test status
Simulation time 1548210922763 ps
CPU time 3503.41 seconds
Started Feb 18 12:30:44 PM PST 24
Finished Feb 18 01:29:11 PM PST 24
Peak memory 190528 kb
Host smart-a60e51e6-b74e-4e5a-a513-b3147f7a1e4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020483203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1020483203
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/119.rv_timer_random.1133104757
Short name T46
Test name
Test status
Simulation time 156112316615 ps
CPU time 315.16 seconds
Started Feb 18 12:31:19 PM PST 24
Finished Feb 18 12:36:38 PM PST 24
Peak memory 190216 kb
Host smart-5728b993-5bfd-45b8-a277-adc133cc1828
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133104757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1133104757
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2135245550
Short name T236
Test name
Test status
Simulation time 411085625123 ps
CPU time 220.49 seconds
Started Feb 18 12:30:35 PM PST 24
Finished Feb 18 12:34:22 PM PST 24
Peak memory 182324 kb
Host smart-968dfa5f-a2f2-4444-9a57-71c42dc887d1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135245550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2135245550
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_random.1544433252
Short name T9
Test name
Test status
Simulation time 98251631595 ps
CPU time 551.87 seconds
Started Feb 18 12:31:11 PM PST 24
Finished Feb 18 12:40:25 PM PST 24
Peak memory 190516 kb
Host smart-e7774168-5e0f-4c7c-bc75-1726c5d3b8f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544433252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1544433252
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3101814108
Short name T218
Test name
Test status
Simulation time 146623477377 ps
CPU time 651.76 seconds
Started Feb 18 12:31:07 PM PST 24
Finished Feb 18 12:42:00 PM PST 24
Peak memory 190500 kb
Host smart-9be80480-b610-4271-b4e3-2cf93b27bbea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101814108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3101814108
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3326319623
Short name T185
Test name
Test status
Simulation time 404494208261 ps
CPU time 453.57 seconds
Started Feb 18 12:31:19 PM PST 24
Finished Feb 18 12:38:56 PM PST 24
Peak memory 190552 kb
Host smart-7a43727d-f741-4445-ab98-3ea033f2f140
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326319623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3326319623
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.3669280187
Short name T327
Test name
Test status
Simulation time 115097777838 ps
CPU time 1451.15 seconds
Started Feb 18 12:31:22 PM PST 24
Finished Feb 18 12:55:35 PM PST 24
Peak memory 190584 kb
Host smart-0e8b7326-fc04-4387-9eb7-ad497cb817e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669280187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3669280187
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random.4227772795
Short name T173
Test name
Test status
Simulation time 406819987760 ps
CPU time 215.95 seconds
Started Feb 18 12:30:55 PM PST 24
Finished Feb 18 12:34:33 PM PST 24
Peak memory 194336 kb
Host smart-f8574235-9288-430f-854a-f4256f2f02af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227772795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.4227772795
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.105077061
Short name T190
Test name
Test status
Simulation time 619770253685 ps
CPU time 1526.58 seconds
Started Feb 18 12:31:13 PM PST 24
Finished Feb 18 12:56:42 PM PST 24
Peak memory 190532 kb
Host smart-a0008910-caca-4fcd-9ecc-01cb0f13eefb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105077061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
105077061
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/101.rv_timer_random.3133368861
Short name T245
Test name
Test status
Simulation time 680656450852 ps
CPU time 514.59 seconds
Started Feb 18 12:31:17 PM PST 24
Finished Feb 18 12:39:55 PM PST 24
Peak memory 192716 kb
Host smart-c8b8e3fa-315e-4733-b395-46b090943785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133368861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3133368861
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.1093340641
Short name T39
Test name
Test status
Simulation time 124686303742 ps
CPU time 225.38 seconds
Started Feb 18 12:31:18 PM PST 24
Finished Feb 18 12:35:07 PM PST 24
Peak memory 190548 kb
Host smart-3b4cdcf5-7504-4e56-802a-20d9d7f90663
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093340641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1093340641
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/70.rv_timer_random.2603490649
Short name T231
Test name
Test status
Simulation time 147348018908 ps
CPU time 795.67 seconds
Started Feb 18 12:31:01 PM PST 24
Finished Feb 18 12:44:18 PM PST 24
Peak memory 193872 kb
Host smart-c870356d-bdf1-4fca-b5ff-57fafaea2a6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603490649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.2603490649
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.312513517
Short name T44
Test name
Test status
Simulation time 1688694479815 ps
CPU time 502.98 seconds
Started Feb 18 12:31:15 PM PST 24
Finished Feb 18 12:39:42 PM PST 24
Peak memory 194096 kb
Host smart-69c89325-bcdb-474e-a0ab-24e0051a94fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312513517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.312513517
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.84361430
Short name T210
Test name
Test status
Simulation time 743373569553 ps
CPU time 1177.67 seconds
Started Feb 18 12:31:13 PM PST 24
Finished Feb 18 12:50:54 PM PST 24
Peak memory 190576 kb
Host smart-6816f991-b299-4651-b0a3-52dce90a1a04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84361430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.84361430
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.2866109490
Short name T310
Test name
Test status
Simulation time 283080748381 ps
CPU time 358.47 seconds
Started Feb 18 12:31:20 PM PST 24
Finished Feb 18 12:37:22 PM PST 24
Peak memory 190556 kb
Host smart-6cd023fb-99ea-4caa-9bbb-e7a0f520580d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866109490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2866109490
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3369119682
Short name T104
Test name
Test status
Simulation time 55324093105 ps
CPU time 101.65 seconds
Started Feb 18 12:30:47 PM PST 24
Finished Feb 18 12:32:31 PM PST 24
Peak memory 182300 kb
Host smart-e78792f3-2a7e-4a38-bffb-a1a656d71fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369119682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3369119682
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/106.rv_timer_random.99193550
Short name T314
Test name
Test status
Simulation time 346049108850 ps
CPU time 342.58 seconds
Started Feb 18 12:31:12 PM PST 24
Finished Feb 18 12:36:57 PM PST 24
Peak memory 190580 kb
Host smart-5d6b013f-4856-42d2-9f13-ec1ed248cbf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99193550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.99193550
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.3522425147
Short name T174
Test name
Test status
Simulation time 96586615743 ps
CPU time 170.66 seconds
Started Feb 18 12:30:43 PM PST 24
Finished Feb 18 12:33:37 PM PST 24
Peak memory 190580 kb
Host smart-4ac04d74-a5cc-4b67-9f23-1174f6c108a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522425147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3522425147
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2841298567
Short name T338
Test name
Test status
Simulation time 102809967597 ps
CPU time 288.29 seconds
Started Feb 18 12:31:30 PM PST 24
Finished Feb 18 12:36:23 PM PST 24
Peak memory 190548 kb
Host smart-889be442-af38-4889-ada5-84dddfea133a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841298567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2841298567
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.530731002
Short name T156
Test name
Test status
Simulation time 130103525197 ps
CPU time 609.72 seconds
Started Feb 18 12:31:16 PM PST 24
Finished Feb 18 12:41:30 PM PST 24
Peak memory 190568 kb
Host smart-670f5b9c-28ec-4ece-b3c1-c8a4df8a9f47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530731002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.530731002
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random.1194681934
Short name T326
Test name
Test status
Simulation time 84743749258 ps
CPU time 380.07 seconds
Started Feb 18 12:30:41 PM PST 24
Finished Feb 18 12:37:06 PM PST 24
Peak memory 182336 kb
Host smart-f461a541-ec87-4e72-a59d-b70c79e99ec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194681934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1194681934
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.1141309605
Short name T188
Test name
Test status
Simulation time 303937415456 ps
CPU time 879.96 seconds
Started Feb 18 12:31:09 PM PST 24
Finished Feb 18 12:45:50 PM PST 24
Peak memory 192576 kb
Host smart-60e2b965-74b7-48e8-9945-a0ef229a34bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141309605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1141309605
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3432379859
Short name T312
Test name
Test status
Simulation time 14813439011 ps
CPU time 20.73 seconds
Started Feb 18 12:30:30 PM PST 24
Finished Feb 18 12:31:00 PM PST 24
Peak memory 182308 kb
Host smart-0f9bd76f-27d7-4471-8073-1f9105de3e3a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432379859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.3432379859
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3113251945
Short name T239
Test name
Test status
Simulation time 1222077804586 ps
CPU time 563.84 seconds
Started Feb 18 12:30:26 PM PST 24
Finished Feb 18 12:40:00 PM PST 24
Peak memory 190520 kb
Host smart-e9f43e98-1c32-4663-9ba1-4b65d1beba7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113251945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3113251945
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/110.rv_timer_random.1902448013
Short name T164
Test name
Test status
Simulation time 587344686167 ps
CPU time 1356.41 seconds
Started Feb 18 12:31:04 PM PST 24
Finished Feb 18 12:53:42 PM PST 24
Peak memory 190512 kb
Host smart-f55ba4a1-7e9c-4e60-9f0d-dc93238b02e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902448013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1902448013
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.2682194793
Short name T191
Test name
Test status
Simulation time 430328835345 ps
CPU time 727.59 seconds
Started Feb 18 12:31:23 PM PST 24
Finished Feb 18 12:43:33 PM PST 24
Peak memory 190560 kb
Host smart-4b55b500-1fc8-413a-bce0-04cbc71722c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682194793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.2682194793
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random.785745276
Short name T158
Test name
Test status
Simulation time 58269961561 ps
CPU time 202.03 seconds
Started Feb 18 12:30:43 PM PST 24
Finished Feb 18 12:34:08 PM PST 24
Peak memory 190528 kb
Host smart-1d0bafd9-d0fb-4a5e-a046-6153a71829e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785745276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.785745276
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random.3767705234
Short name T177
Test name
Test status
Simulation time 344214478818 ps
CPU time 343.53 seconds
Started Feb 18 12:31:03 PM PST 24
Finished Feb 18 12:36:48 PM PST 24
Peak memory 193636 kb
Host smart-511ebbea-a8b6-45be-ba35-edb437402eee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767705234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3767705234
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.4014698129
Short name T357
Test name
Test status
Simulation time 404126862384 ps
CPU time 722.71 seconds
Started Feb 18 12:31:15 PM PST 24
Finished Feb 18 12:43:21 PM PST 24
Peak memory 190584 kb
Host smart-a7985faf-6736-4deb-b73f-63b546d39fca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014698129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.4014698129
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.249280876
Short name T141
Test name
Test status
Simulation time 480465087872 ps
CPU time 612.7 seconds
Started Feb 18 12:31:09 PM PST 24
Finished Feb 18 12:41:22 PM PST 24
Peak memory 192840 kb
Host smart-54095e9d-7483-4367-95b6-9249e32ea1f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249280876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.249280876
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1637030709
Short name T59
Test name
Test status
Simulation time 56043582670 ps
CPU time 101.76 seconds
Started Feb 18 12:31:09 PM PST 24
Finished Feb 18 12:32:52 PM PST 24
Peak memory 193060 kb
Host smart-a77ee48a-efc7-476e-bd37-2763811a4a43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637030709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1637030709
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.1541607675
Short name T167
Test name
Test status
Simulation time 158965004260 ps
CPU time 662.46 seconds
Started Feb 18 12:31:15 PM PST 24
Finished Feb 18 12:42:22 PM PST 24
Peak memory 190516 kb
Host smart-f84554ae-608b-4f9e-9eaa-9465f551343b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541607675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1541607675
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.1121581921
Short name T42
Test name
Test status
Simulation time 633740543209 ps
CPU time 496.74 seconds
Started Feb 18 12:31:15 PM PST 24
Finished Feb 18 12:39:35 PM PST 24
Peak memory 190524 kb
Host smart-2bbe1d49-cc69-4850-bd79-9dab44bc649b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121581921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1121581921
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2102936638
Short name T80
Test name
Test status
Simulation time 46751431 ps
CPU time 0.61 seconds
Started Feb 18 12:28:19 PM PST 24
Finished Feb 18 12:28:25 PM PST 24
Peak memory 191560 kb
Host smart-46a02cfb-0aee-446f-98af-fef3462c25ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102936638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2102936638
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_timer_random.2055935842
Short name T301
Test name
Test status
Simulation time 306251970517 ps
CPU time 636.46 seconds
Started Feb 18 12:30:26 PM PST 24
Finished Feb 18 12:41:13 PM PST 24
Peak memory 190556 kb
Host smart-a8fe995b-6269-4df2-a5a9-2c1240ca3356
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055935842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2055935842
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/130.rv_timer_random.2656591420
Short name T331
Test name
Test status
Simulation time 409808644069 ps
CPU time 142.71 seconds
Started Feb 18 12:35:19 PM PST 24
Finished Feb 18 12:37:45 PM PST 24
Peak memory 189768 kb
Host smart-691fef2e-9af5-4b1d-9fe0-50a1d1e76929
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656591420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2656591420
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.42378468
Short name T442
Test name
Test status
Simulation time 196085747931 ps
CPU time 221.89 seconds
Started Feb 18 12:31:13 PM PST 24
Finished Feb 18 12:34:57 PM PST 24
Peak memory 190504 kb
Host smart-4fc932b8-e0b6-4efe-b134-638979baa0dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42378468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.42378468
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2809966122
Short name T201
Test name
Test status
Simulation time 355770973952 ps
CPU time 1546.37 seconds
Started Feb 18 12:31:15 PM PST 24
Finished Feb 18 12:57:06 PM PST 24
Peak memory 193872 kb
Host smart-40a7bc13-4d84-4fcc-b22d-4b7544bbe354
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809966122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2809966122
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.3819994069
Short name T304
Test name
Test status
Simulation time 648277499487 ps
CPU time 3564.07 seconds
Started Feb 18 12:31:23 PM PST 24
Finished Feb 18 01:30:50 PM PST 24
Peak memory 190576 kb
Host smart-e69b5307-f2c1-4275-bac6-18f448f52e52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819994069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3819994069
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.147201818
Short name T144
Test name
Test status
Simulation time 188855366612 ps
CPU time 662.57 seconds
Started Feb 18 12:31:27 PM PST 24
Finished Feb 18 12:42:33 PM PST 24
Peak memory 190708 kb
Host smart-677a9ca9-b39a-4ee9-b4f7-3502bed4204d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147201818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.147201818
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.816757230
Short name T95
Test name
Test status
Simulation time 276775533642 ps
CPU time 153.5 seconds
Started Feb 18 12:30:37 PM PST 24
Finished Feb 18 12:33:16 PM PST 24
Peak memory 182448 kb
Host smart-0cfcbb91-b176-4935-adf8-7debe74cc8b0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816757230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.rv_timer_cfg_update_on_fly.816757230
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.875137059
Short name T293
Test name
Test status
Simulation time 504024468390 ps
CPU time 998.15 seconds
Started Feb 18 12:31:06 PM PST 24
Finished Feb 18 12:47:45 PM PST 24
Peak memory 190552 kb
Host smart-8a75a269-191a-4acb-991c-5e70cd1897b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875137059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
875137059
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2520028694
Short name T546
Test name
Test status
Simulation time 331561125 ps
CPU time 1.11 seconds
Started Feb 18 12:28:22 PM PST 24
Finished Feb 18 12:28:30 PM PST 24
Peak memory 194592 kb
Host smart-e3bb60bc-fbb3-411a-a856-93cfb5df98a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520028694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.2520028694
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.215758296
Short name T240
Test name
Test status
Simulation time 81044114632 ps
CPU time 331.11 seconds
Started Feb 18 12:30:55 PM PST 24
Finished Feb 18 12:36:28 PM PST 24
Peak memory 182328 kb
Host smart-fa6e19b0-8be4-4561-b910-ea963043f623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215758296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.215758296
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/105.rv_timer_random.2217095603
Short name T265
Test name
Test status
Simulation time 250988213346 ps
CPU time 223.71 seconds
Started Feb 18 12:30:56 PM PST 24
Finished Feb 18 12:34:43 PM PST 24
Peak memory 190548 kb
Host smart-4283cc99-59c7-47d6-9e97-081f630a6b37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217095603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2217095603
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.2659317371
Short name T278
Test name
Test status
Simulation time 515978714638 ps
CPU time 220.34 seconds
Started Feb 18 12:31:15 PM PST 24
Finished Feb 18 12:34:59 PM PST 24
Peak memory 190504 kb
Host smart-c2e29a22-38c2-4be6-8980-4f7bb524efe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659317371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2659317371
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.3609617890
Short name T176
Test name
Test status
Simulation time 66788314083 ps
CPU time 477.17 seconds
Started Feb 18 12:31:20 PM PST 24
Finished Feb 18 12:39:20 PM PST 24
Peak memory 190548 kb
Host smart-3490bb01-0884-41e4-9738-6e3265764264
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609617890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3609617890
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.2702518688
Short name T241
Test name
Test status
Simulation time 406410086727 ps
CPU time 138.61 seconds
Started Feb 18 12:31:17 PM PST 24
Finished Feb 18 12:33:40 PM PST 24
Peak memory 190548 kb
Host smart-8349d336-10d8-4452-bcc3-218693ded92a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702518688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.2702518688
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1341014650
Short name T271
Test name
Test status
Simulation time 179229546497 ps
CPU time 283.37 seconds
Started Feb 18 12:31:19 PM PST 24
Finished Feb 18 12:36:06 PM PST 24
Peak memory 190484 kb
Host smart-009cc0ff-321c-4292-b2b3-b83868c4670e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341014650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1341014650
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1986842462
Short name T223
Test name
Test status
Simulation time 1194451791504 ps
CPU time 662.02 seconds
Started Feb 18 12:31:31 PM PST 24
Finished Feb 18 12:42:38 PM PST 24
Peak memory 190600 kb
Host smart-8fe559d0-4604-4cae-99aa-af647a838dc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986842462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1986842462
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.769364529
Short name T184
Test name
Test status
Simulation time 107477056855 ps
CPU time 183.82 seconds
Started Feb 18 12:31:22 PM PST 24
Finished Feb 18 12:34:28 PM PST 24
Peak memory 190128 kb
Host smart-096fe1b8-110f-4230-9047-d7ac02ed41df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769364529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.769364529
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.886738443
Short name T267
Test name
Test status
Simulation time 187331865001 ps
CPU time 268.67 seconds
Started Feb 18 12:31:17 PM PST 24
Finished Feb 18 12:35:49 PM PST 24
Peak memory 190584 kb
Host smart-a76debf7-c25e-4716-9ede-ef80f1d21f6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886738443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.886738443
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.3274299383
Short name T334
Test name
Test status
Simulation time 217692826312 ps
CPU time 627.48 seconds
Started Feb 18 12:31:23 PM PST 24
Finished Feb 18 12:41:54 PM PST 24
Peak memory 190476 kb
Host smart-a9b4ebfb-2396-4c9d-a944-4fb80a773990
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274299383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3274299383
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.2215911951
Short name T355
Test name
Test status
Simulation time 17481405374 ps
CPU time 43.92 seconds
Started Feb 18 12:31:31 PM PST 24
Finished Feb 18 12:32:20 PM PST 24
Peak memory 182356 kb
Host smart-0ee1124a-c757-498a-84de-54b1297ef23c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215911951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2215911951
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.467978637
Short name T148
Test name
Test status
Simulation time 581203995550 ps
CPU time 532.7 seconds
Started Feb 18 12:31:20 PM PST 24
Finished Feb 18 12:40:15 PM PST 24
Peak memory 190580 kb
Host smart-fa504415-7f6b-4ed0-bb11-009f946630ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467978637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.467978637
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2402062237
Short name T163
Test name
Test status
Simulation time 33182887509 ps
CPU time 37.42 seconds
Started Feb 18 12:31:29 PM PST 24
Finished Feb 18 12:32:10 PM PST 24
Peak memory 190476 kb
Host smart-536cb26c-3f42-4acc-a401-a0b3b08fd19a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402062237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2402062237
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.737264942
Short name T123
Test name
Test status
Simulation time 361605328569 ps
CPU time 1188.98 seconds
Started Feb 18 12:31:33 PM PST 24
Finished Feb 18 12:51:29 PM PST 24
Peak memory 190540 kb
Host smart-1434cb76-3dc9-406a-b25c-02244c64ca27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737264942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.737264942
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.3724861482
Short name T367
Test name
Test status
Simulation time 121261906582 ps
CPU time 104.83 seconds
Started Feb 18 12:30:55 PM PST 24
Finished Feb 18 12:32:42 PM PST 24
Peak memory 194044 kb
Host smart-b812ceb0-638e-4761-8079-0a47edece430
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724861482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3724861482
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.174329983
Short name T330
Test name
Test status
Simulation time 1021456079233 ps
CPU time 251.4 seconds
Started Feb 18 12:31:24 PM PST 24
Finished Feb 18 12:35:38 PM PST 24
Peak memory 190488 kb
Host smart-5e7148a0-ba6f-45a9-93e2-c8d152b82407
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174329983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.174329983
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random.47838108
Short name T187
Test name
Test status
Simulation time 646276990741 ps
CPU time 1100.63 seconds
Started Feb 18 12:30:43 PM PST 24
Finished Feb 18 12:49:07 PM PST 24
Peak memory 190536 kb
Host smart-cd970f58-4382-442c-95d9-c6a274a6888e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47838108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.47838108
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.4155181141
Short name T40
Test name
Test status
Simulation time 334015535443 ps
CPU time 284.53 seconds
Started Feb 18 12:30:44 PM PST 24
Finished Feb 18 12:35:32 PM PST 24
Peak memory 190592 kb
Host smart-475239f1-3c41-4fcb-bfac-4714e7876bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155181141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.4155181141
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1554070152
Short name T371
Test name
Test status
Simulation time 5082040897945 ps
CPU time 1414.74 seconds
Started Feb 18 12:30:27 PM PST 24
Finished Feb 18 12:54:12 PM PST 24
Peak memory 182328 kb
Host smart-7bc331c4-9935-4b8a-b9f8-3026b1287cbd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554070152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1554070152
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_random.1632423336
Short name T171
Test name
Test status
Simulation time 336808897670 ps
CPU time 476.92 seconds
Started Feb 18 12:30:21 PM PST 24
Finished Feb 18 12:38:25 PM PST 24
Peak memory 193768 kb
Host smart-0b491477-2593-4d67-8d49-4ba22e1a074a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632423336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1632423336
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1992289412
Short name T325
Test name
Test status
Simulation time 2289875814999 ps
CPU time 1111.67 seconds
Started Feb 18 12:31:47 PM PST 24
Finished Feb 18 12:50:20 PM PST 24
Peak memory 190164 kb
Host smart-5fca2ea9-03f8-4060-a3b1-ab7da9394345
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992289412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1992289412
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_random.3322633311
Short name T198
Test name
Test status
Simulation time 4533050146 ps
CPU time 2.53 seconds
Started Feb 18 12:30:42 PM PST 24
Finished Feb 18 12:30:48 PM PST 24
Peak memory 181648 kb
Host smart-f181a649-3fd1-4f89-a905-20a79eef200c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322633311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3322633311
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.735429002
Short name T38
Test name
Test status
Simulation time 262345208409 ps
CPU time 511.25 seconds
Started Feb 18 12:30:43 PM PST 24
Finished Feb 18 12:39:18 PM PST 24
Peak memory 205260 kb
Host smart-0d4743a8-100b-47b1-814f-7221c9998675
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735429002 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.735429002
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3563271752
Short name T215
Test name
Test status
Simulation time 659976409816 ps
CPU time 592.12 seconds
Started Feb 18 12:30:50 PM PST 24
Finished Feb 18 12:40:43 PM PST 24
Peak memory 182316 kb
Host smart-f9e73776-131b-422e-b113-3b747893cb1f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563271752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.3563271752
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_random.3858007895
Short name T287
Test name
Test status
Simulation time 1129909807565 ps
CPU time 294.81 seconds
Started Feb 18 12:31:08 PM PST 24
Finished Feb 18 12:36:04 PM PST 24
Peak memory 190516 kb
Host smart-f258634b-f49e-4c7c-bac3-c2cf488ebbb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858007895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3858007895
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.2378044597
Short name T261
Test name
Test status
Simulation time 155868406644 ps
CPU time 634.43 seconds
Started Feb 18 12:31:07 PM PST 24
Finished Feb 18 12:41:43 PM PST 24
Peak memory 190580 kb
Host smart-00f8fdd1-fa07-49af-8412-68b633a04c5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378044597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2378044597
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.204316979
Short name T306
Test name
Test status
Simulation time 287893820407 ps
CPU time 307.93 seconds
Started Feb 18 12:31:11 PM PST 24
Finished Feb 18 12:36:21 PM PST 24
Peak memory 190564 kb
Host smart-8d920ee6-39d1-4692-83a8-5ce7f2952970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204316979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.204316979
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1037879047
Short name T189
Test name
Test status
Simulation time 86361319717 ps
CPU time 112.28 seconds
Started Feb 18 12:31:10 PM PST 24
Finished Feb 18 12:33:04 PM PST 24
Peak memory 190524 kb
Host smart-c38cbd67-9bb6-4c17-b218-a04c4e3d0c7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037879047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1037879047
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/90.rv_timer_random.1511153375
Short name T140
Test name
Test status
Simulation time 126489542748 ps
CPU time 738.49 seconds
Started Feb 18 12:31:13 PM PST 24
Finished Feb 18 12:43:33 PM PST 24
Peak memory 190568 kb
Host smart-11a095d5-d90b-4fcc-af4c-550e59237686
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511153375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1511153375
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3809078839
Short name T491
Test name
Test status
Simulation time 44094872 ps
CPU time 0.61 seconds
Started Feb 18 12:28:14 PM PST 24
Finished Feb 18 12:28:20 PM PST 24
Peak memory 182372 kb
Host smart-b5a38c78-13f2-444c-8b78-b6f9f77152d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809078839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3809078839
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3496737204
Short name T485
Test name
Test status
Simulation time 4554305214 ps
CPU time 2.77 seconds
Started Feb 18 12:27:59 PM PST 24
Finished Feb 18 12:28:09 PM PST 24
Peak memory 190096 kb
Host smart-532d98b8-f77e-4bfb-a628-96e39c642082
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496737204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3496737204
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1494664706
Short name T514
Test name
Test status
Simulation time 12024925 ps
CPU time 0.59 seconds
Started Feb 18 12:28:05 PM PST 24
Finished Feb 18 12:28:11 PM PST 24
Peak memory 181684 kb
Host smart-4c379173-5c98-485e-8b3b-0af782c8022e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494664706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.1494664706
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.898674880
Short name T559
Test name
Test status
Simulation time 1249164595 ps
CPU time 2.81 seconds
Started Feb 18 12:28:22 PM PST 24
Finished Feb 18 12:28:31 PM PST 24
Peak memory 196800 kb
Host smart-6f6aaafa-c605-4b67-9c2e-378d0aa5a1e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898674880 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.898674880
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3535834082
Short name T85
Test name
Test status
Simulation time 36305707 ps
CPU time 0.5 seconds
Started Feb 18 12:28:21 PM PST 24
Finished Feb 18 12:28:28 PM PST 24
Peak memory 182364 kb
Host smart-a9ec6a5c-7f58-4d77-91d0-c529eee13f1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535834082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3535834082
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2868444713
Short name T528
Test name
Test status
Simulation time 14697653 ps
CPU time 0.54 seconds
Started Feb 18 12:28:15 PM PST 24
Finished Feb 18 12:28:21 PM PST 24
Peak memory 182056 kb
Host smart-a8783b71-ec54-41ba-bb33-cbfdba41677a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868444713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2868444713
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2929723502
Short name T487
Test name
Test status
Simulation time 27576445 ps
CPU time 1.27 seconds
Started Feb 18 12:28:25 PM PST 24
Finished Feb 18 12:28:32 PM PST 24
Peak memory 197016 kb
Host smart-1c18754a-527d-436c-b425-89166067afa2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929723502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2929723502
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2877483876
Short name T130
Test name
Test status
Simulation time 72533083 ps
CPU time 0.83 seconds
Started Feb 18 12:28:18 PM PST 24
Finished Feb 18 12:28:24 PM PST 24
Peak memory 193196 kb
Host smart-2b7f6bdb-0a71-438e-b1f1-84dc88fd076b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877483876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2877483876
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3838932356
Short name T78
Test name
Test status
Simulation time 158042307 ps
CPU time 0.82 seconds
Started Feb 18 12:28:14 PM PST 24
Finished Feb 18 12:28:21 PM PST 24
Peak memory 192140 kb
Host smart-8517842c-2944-4d95-ac3d-83613c1de5a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838932356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3838932356
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.53444009
Short name T478
Test name
Test status
Simulation time 70420287 ps
CPU time 1.45 seconds
Started Feb 18 12:28:14 PM PST 24
Finished Feb 18 12:28:22 PM PST 24
Peak memory 192824 kb
Host smart-8893d5fd-985f-4244-a3cc-d6b1584124ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53444009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_ba
sh.53444009
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1656975814
Short name T549
Test name
Test status
Simulation time 62651614 ps
CPU time 0.53 seconds
Started Feb 18 12:28:12 PM PST 24
Finished Feb 18 12:28:28 PM PST 24
Peak memory 182532 kb
Host smart-c91c45bc-b3b9-41fc-b9bb-5d14d410809f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656975814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1656975814
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2547624832
Short name T573
Test name
Test status
Simulation time 55242493 ps
CPU time 2.65 seconds
Started Feb 18 12:28:13 PM PST 24
Finished Feb 18 12:28:21 PM PST 24
Peak memory 195492 kb
Host smart-3ee59a8e-8c0f-4483-a3e1-baf9065b112e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547624832 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2547624832
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2840741391
Short name T552
Test name
Test status
Simulation time 30676114 ps
CPU time 0.55 seconds
Started Feb 18 12:28:08 PM PST 24
Finished Feb 18 12:28:16 PM PST 24
Peak memory 182108 kb
Host smart-d69e9c52-5f64-4b4a-81d2-dc846915812f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840741391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2840741391
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2625605245
Short name T77
Test name
Test status
Simulation time 94907800 ps
CPU time 0.74 seconds
Started Feb 18 12:28:20 PM PST 24
Finished Feb 18 12:28:27 PM PST 24
Peak memory 192784 kb
Host smart-2e1b6170-1cec-4291-a17c-9f9cc0976fc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625605245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2625605245
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1811097812
Short name T541
Test name
Test status
Simulation time 181045627 ps
CPU time 2.57 seconds
Started Feb 18 12:28:07 PM PST 24
Finished Feb 18 12:28:16 PM PST 24
Peak memory 197076 kb
Host smart-8d522e03-2fd7-4eb4-b938-daa8cc71c0ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811097812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1811097812
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2351646345
Short name T493
Test name
Test status
Simulation time 213223085 ps
CPU time 2.95 seconds
Started Feb 18 12:28:30 PM PST 24
Finished Feb 18 12:28:37 PM PST 24
Peak memory 197136 kb
Host smart-abd0d65c-27d9-4b31-9dd4-a52937087596
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351646345 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2351646345
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.4202019555
Short name T79
Test name
Test status
Simulation time 50723475 ps
CPU time 0.59 seconds
Started Feb 18 12:28:36 PM PST 24
Finished Feb 18 12:28:39 PM PST 24
Peak memory 182288 kb
Host smart-c53a8f68-b5f3-4567-844a-47c52775ce1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202019555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.4202019555
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2901748945
Short name T498
Test name
Test status
Simulation time 62394348 ps
CPU time 0.55 seconds
Started Feb 18 12:28:15 PM PST 24
Finished Feb 18 12:28:21 PM PST 24
Peak memory 181896 kb
Host smart-45b0f61a-4388-42af-a330-8cbd1d9e3bf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901748945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2901748945
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2237836700
Short name T75
Test name
Test status
Simulation time 20807691 ps
CPU time 0.72 seconds
Started Feb 18 12:28:07 PM PST 24
Finished Feb 18 12:28:19 PM PST 24
Peak memory 192224 kb
Host smart-2eb5e26b-b978-4d3d-aa0f-5be551d304fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237836700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2237836700
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3528568683
Short name T501
Test name
Test status
Simulation time 52047340 ps
CPU time 2.32 seconds
Started Feb 18 12:28:12 PM PST 24
Finished Feb 18 12:28:20 PM PST 24
Peak memory 196868 kb
Host smart-5e09b01d-4f77-446d-ba2d-858612c964ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528568683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3528568683
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2531047952
Short name T523
Test name
Test status
Simulation time 47429500 ps
CPU time 0.86 seconds
Started Feb 18 12:28:13 PM PST 24
Finished Feb 18 12:28:24 PM PST 24
Peak memory 192032 kb
Host smart-6fdd2487-c4ca-4ae6-9d79-47a006bc16cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531047952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.2531047952
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1036220189
Short name T534
Test name
Test status
Simulation time 31875247 ps
CPU time 1.48 seconds
Started Feb 18 12:28:37 PM PST 24
Finished Feb 18 12:28:41 PM PST 24
Peak memory 197076 kb
Host smart-85beb1b5-8c74-48ba-a766-ed5127b44f56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036220189 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1036220189
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1849601924
Short name T82
Test name
Test status
Simulation time 19874203 ps
CPU time 0.54 seconds
Started Feb 18 12:28:24 PM PST 24
Finished Feb 18 12:28:31 PM PST 24
Peak memory 182152 kb
Host smart-b187aaaf-a22c-49e3-a3ca-6697fc7b1a8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849601924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1849601924
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.186080016
Short name T598
Test name
Test status
Simulation time 41439087 ps
CPU time 0.52 seconds
Started Feb 18 12:28:13 PM PST 24
Finished Feb 18 12:28:19 PM PST 24
Peak memory 181288 kb
Host smart-a48c8d39-fbaa-45cb-be75-62ce2e133b94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186080016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.186080016
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3466814229
Short name T111
Test name
Test status
Simulation time 31867889 ps
CPU time 0.81 seconds
Started Feb 18 12:28:13 PM PST 24
Finished Feb 18 12:28:20 PM PST 24
Peak memory 190096 kb
Host smart-447ad8a1-2465-4f50-8b56-c1ccca0dfb6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466814229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3466814229
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1857424518
Short name T575
Test name
Test status
Simulation time 39703515 ps
CPU time 1.14 seconds
Started Feb 18 12:28:13 PM PST 24
Finished Feb 18 12:28:20 PM PST 24
Peak memory 195172 kb
Host smart-424c23fd-9c70-48ae-84c7-8634a598f7a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857424518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1857424518
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3014274365
Short name T30
Test name
Test status
Simulation time 49430849 ps
CPU time 0.8 seconds
Started Feb 18 12:28:16 PM PST 24
Finished Feb 18 12:28:23 PM PST 24
Peak memory 192900 kb
Host smart-ccffcd0e-f8bb-425b-a80e-f284ea637044
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014274365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3014274365
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.4112974558
Short name T480
Test name
Test status
Simulation time 170021133 ps
CPU time 2.19 seconds
Started Feb 18 12:28:36 PM PST 24
Finished Feb 18 12:28:40 PM PST 24
Peak memory 197076 kb
Host smart-74373b0f-3038-4d1d-b6e1-9a8efb847b19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112974558 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.4112974558
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2881641439
Short name T84
Test name
Test status
Simulation time 48405150 ps
CPU time 0.57 seconds
Started Feb 18 12:28:19 PM PST 24
Finished Feb 18 12:28:26 PM PST 24
Peak memory 182300 kb
Host smart-299e53ab-ced4-4627-9ace-4fd0d8fcfc85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881641439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2881641439
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.86687797
Short name T564
Test name
Test status
Simulation time 18019827 ps
CPU time 0.52 seconds
Started Feb 18 12:28:17 PM PST 24
Finished Feb 18 12:28:23 PM PST 24
Peak memory 181928 kb
Host smart-c5327181-30cf-4beb-bb73-21a047d4a92b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86687797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.86687797
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1000102801
Short name T557
Test name
Test status
Simulation time 57851983 ps
CPU time 0.68 seconds
Started Feb 18 12:28:21 PM PST 24
Finished Feb 18 12:28:28 PM PST 24
Peak memory 192704 kb
Host smart-9e687285-f454-423f-b053-e49f322e33cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000102801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1000102801
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3353259960
Short name T526
Test name
Test status
Simulation time 136176617 ps
CPU time 1.63 seconds
Started Feb 18 12:28:15 PM PST 24
Finished Feb 18 12:28:22 PM PST 24
Peak memory 196968 kb
Host smart-57b9a98a-9c6f-4c45-8fe0-171c9313db45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353259960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.3353259960
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3937387463
Short name T131
Test name
Test status
Simulation time 114165434 ps
CPU time 1.26 seconds
Started Feb 18 12:28:23 PM PST 24
Finished Feb 18 12:28:31 PM PST 24
Peak memory 194540 kb
Host smart-7cac5953-43ed-4205-a9c4-cda3e4968e52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937387463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3937387463
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3440982232
Short name T586
Test name
Test status
Simulation time 154722309 ps
CPU time 2.09 seconds
Started Feb 18 12:28:32 PM PST 24
Finished Feb 18 12:28:37 PM PST 24
Peak memory 197128 kb
Host smart-d19e7cc6-39f9-4cb8-9608-baab9ea84944
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440982232 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3440982232
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.47080533
Short name T483
Test name
Test status
Simulation time 46673369 ps
CPU time 0.55 seconds
Started Feb 18 12:28:23 PM PST 24
Finished Feb 18 12:28:30 PM PST 24
Peak memory 182344 kb
Host smart-d0f29ab4-9c53-4431-b96d-ecf8345815d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47080533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.47080533
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.305501772
Short name T472
Test name
Test status
Simulation time 12259990 ps
CPU time 0.58 seconds
Started Feb 18 12:28:25 PM PST 24
Finished Feb 18 12:28:32 PM PST 24
Peak memory 180604 kb
Host smart-e216932a-d341-4a39-bb11-df39e02439aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305501772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.305501772
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.4050321234
Short name T114
Test name
Test status
Simulation time 21170547 ps
CPU time 0.62 seconds
Started Feb 18 12:28:30 PM PST 24
Finished Feb 18 12:28:34 PM PST 24
Peak memory 191612 kb
Host smart-bcd12bd9-9867-49a0-98f0-2f9c6373166a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050321234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.4050321234
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2180928424
Short name T475
Test name
Test status
Simulation time 733503586 ps
CPU time 3.03 seconds
Started Feb 18 12:28:35 PM PST 24
Finished Feb 18 12:28:40 PM PST 24
Peak memory 197156 kb
Host smart-2afee21e-0c49-4b50-88b2-79f58f7543ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180928424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2180928424
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.481551057
Short name T562
Test name
Test status
Simulation time 295872654 ps
CPU time 0.83 seconds
Started Feb 18 12:28:34 PM PST 24
Finished Feb 18 12:28:37 PM PST 24
Peak memory 182420 kb
Host smart-783baf1b-608b-4f64-a699-494f5f7ff76f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481551057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_in
tg_err.481551057
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3263179244
Short name T542
Test name
Test status
Simulation time 666686733 ps
CPU time 1.74 seconds
Started Feb 18 12:28:13 PM PST 24
Finished Feb 18 12:28:20 PM PST 24
Peak memory 197072 kb
Host smart-c45430d2-b76e-4659-91fc-d2fc566c7551
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263179244 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.3263179244
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.4175207763
Short name T83
Test name
Test status
Simulation time 23463741 ps
CPU time 0.64 seconds
Started Feb 18 12:28:24 PM PST 24
Finished Feb 18 12:28:32 PM PST 24
Peak memory 181684 kb
Host smart-6ae2ddd8-32ee-4cec-82c2-df46acf53c5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175207763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.4175207763
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2728679310
Short name T553
Test name
Test status
Simulation time 15350010 ps
CPU time 0.55 seconds
Started Feb 18 12:28:26 PM PST 24
Finished Feb 18 12:28:32 PM PST 24
Peak memory 181788 kb
Host smart-31aad6aa-3540-4416-8846-a9dee6481b8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728679310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2728679310
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3536680365
Short name T576
Test name
Test status
Simulation time 111279130 ps
CPU time 0.74 seconds
Started Feb 18 12:28:37 PM PST 24
Finished Feb 18 12:28:40 PM PST 24
Peak memory 192664 kb
Host smart-ff53303d-d706-437d-a021-b0538f8cdd94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536680365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3536680365
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.454760049
Short name T510
Test name
Test status
Simulation time 69139975 ps
CPU time 1.18 seconds
Started Feb 18 12:28:07 PM PST 24
Finished Feb 18 12:28:15 PM PST 24
Peak memory 196864 kb
Host smart-b3f27810-4d0c-4097-847e-838fab5ca785
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454760049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.454760049
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2813994381
Short name T132
Test name
Test status
Simulation time 81937831 ps
CPU time 0.77 seconds
Started Feb 18 12:28:22 PM PST 24
Finished Feb 18 12:28:29 PM PST 24
Peak memory 193124 kb
Host smart-1da54a53-1e1c-4d68-a6db-275fd4421eb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813994381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2813994381
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1770019579
Short name T489
Test name
Test status
Simulation time 115649774 ps
CPU time 2.23 seconds
Started Feb 18 12:28:35 PM PST 24
Finished Feb 18 12:28:39 PM PST 24
Peak memory 197072 kb
Host smart-60eede01-3fe8-421c-bd1c-d5aa2d44cc6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770019579 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1770019579
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.352699125
Short name T88
Test name
Test status
Simulation time 15090330 ps
CPU time 0.57 seconds
Started Feb 18 12:28:20 PM PST 24
Finished Feb 18 12:28:26 PM PST 24
Peak memory 182172 kb
Host smart-e50161d5-4d75-4c91-886d-23a4591efa98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352699125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.352699125
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1298769756
Short name T535
Test name
Test status
Simulation time 134428271 ps
CPU time 0.57 seconds
Started Feb 18 12:28:07 PM PST 24
Finished Feb 18 12:28:14 PM PST 24
Peak memory 181936 kb
Host smart-9ed0281c-52c1-4421-a7d4-297ce29a5668
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298769756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1298769756
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1664154682
Short name T591
Test name
Test status
Simulation time 90456256 ps
CPU time 0.79 seconds
Started Feb 18 12:28:20 PM PST 24
Finished Feb 18 12:28:26 PM PST 24
Peak memory 192924 kb
Host smart-119916cb-ad76-4638-8b8a-acc51cb3f4c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664154682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.1664154682
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1606393318
Short name T505
Test name
Test status
Simulation time 53160281 ps
CPU time 1.35 seconds
Started Feb 18 12:28:04 PM PST 24
Finished Feb 18 12:28:11 PM PST 24
Peak memory 196052 kb
Host smart-6fc94a72-8920-4e59-9ef4-45daddefb98e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606393318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1606393318
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2027880262
Short name T506
Test name
Test status
Simulation time 69360753 ps
CPU time 1.08 seconds
Started Feb 18 12:28:08 PM PST 24
Finished Feb 18 12:28:16 PM PST 24
Peak memory 194620 kb
Host smart-16677bdd-a29b-4919-8c7d-15b8e935e353
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027880262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2027880262
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2701601336
Short name T496
Test name
Test status
Simulation time 64287530 ps
CPU time 1.58 seconds
Started Feb 18 12:28:22 PM PST 24
Finished Feb 18 12:28:31 PM PST 24
Peak memory 196344 kb
Host smart-55a06605-ecb6-4bae-ba4b-3becee523401
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701601336 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2701601336
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1141527498
Short name T533
Test name
Test status
Simulation time 60819440 ps
CPU time 0.57 seconds
Started Feb 18 12:28:20 PM PST 24
Finished Feb 18 12:28:27 PM PST 24
Peak memory 182168 kb
Host smart-208fde82-fc31-40e0-925b-1f3aa376e511
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141527498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1141527498
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.420369193
Short name T597
Test name
Test status
Simulation time 18889515 ps
CPU time 0.6 seconds
Started Feb 18 12:28:12 PM PST 24
Finished Feb 18 12:28:19 PM PST 24
Peak memory 181376 kb
Host smart-1e42f6df-cf3d-43f3-97b4-a07ec6d0a39b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420369193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.420369193
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3751043842
Short name T567
Test name
Test status
Simulation time 38761209 ps
CPU time 0.59 seconds
Started Feb 18 12:28:37 PM PST 24
Finished Feb 18 12:28:40 PM PST 24
Peak memory 191576 kb
Host smart-1e1ac28b-0520-497f-a241-2a8d4c7a5639
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751043842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.3751043842
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3820604661
Short name T536
Test name
Test status
Simulation time 230771047 ps
CPU time 1.26 seconds
Started Feb 18 12:28:37 PM PST 24
Finished Feb 18 12:28:41 PM PST 24
Peak memory 196752 kb
Host smart-85f72efd-0cba-4507-8469-6adffc7ae756
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820604661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3820604661
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2876858863
Short name T550
Test name
Test status
Simulation time 129977294 ps
CPU time 1.34 seconds
Started Feb 18 12:28:34 PM PST 24
Finished Feb 18 12:28:38 PM PST 24
Peak memory 182760 kb
Host smart-d48eeea2-8d8c-4250-9eb3-ca042c39fdf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876858863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2876858863
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.4257176371
Short name T565
Test name
Test status
Simulation time 126786944 ps
CPU time 2.62 seconds
Started Feb 18 12:28:39 PM PST 24
Finished Feb 18 12:28:43 PM PST 24
Peak memory 197068 kb
Host smart-60937259-55a1-4389-af0b-8235c26a48ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257176371 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.4257176371
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.720627378
Short name T601
Test name
Test status
Simulation time 15571203 ps
CPU time 0.53 seconds
Started Feb 18 12:28:40 PM PST 24
Finished Feb 18 12:28:44 PM PST 24
Peak memory 181880 kb
Host smart-db270453-d548-4e59-8bb7-7813d7641766
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720627378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.720627378
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1489214406
Short name T530
Test name
Test status
Simulation time 22859328 ps
CPU time 0.62 seconds
Started Feb 18 12:28:22 PM PST 24
Finished Feb 18 12:28:30 PM PST 24
Peak memory 180784 kb
Host smart-27055aae-41dd-4eb8-bf43-d9d25fd7a64e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489214406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1489214406
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2425033929
Short name T112
Test name
Test status
Simulation time 20176790 ps
CPU time 0.88 seconds
Started Feb 18 12:28:02 PM PST 24
Finished Feb 18 12:28:08 PM PST 24
Peak memory 189864 kb
Host smart-dd067bdd-7592-4f4c-9a0c-fafadb907a7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425033929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2425033929
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.4060772670
Short name T477
Test name
Test status
Simulation time 184938830 ps
CPU time 1.11 seconds
Started Feb 18 12:28:27 PM PST 24
Finished Feb 18 12:28:36 PM PST 24
Peak memory 196968 kb
Host smart-1def2651-b5ac-442e-995e-a7380e936675
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060772670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.4060772670
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2853801236
Short name T531
Test name
Test status
Simulation time 174335865 ps
CPU time 1.32 seconds
Started Feb 18 12:28:07 PM PST 24
Finished Feb 18 12:28:15 PM PST 24
Peak memory 182356 kb
Host smart-606b0c67-93d4-43b4-a61c-2b4d2cdba423
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853801236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2853801236
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.479290549
Short name T503
Test name
Test status
Simulation time 1538270428 ps
CPU time 1.97 seconds
Started Feb 18 12:28:34 PM PST 24
Finished Feb 18 12:28:38 PM PST 24
Peak memory 197076 kb
Host smart-3555836e-41bd-4fc3-a718-7cf4b97bda06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479290549 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.479290549
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.924708287
Short name T592
Test name
Test status
Simulation time 30770599 ps
CPU time 0.56 seconds
Started Feb 18 12:28:23 PM PST 24
Finished Feb 18 12:28:30 PM PST 24
Peak memory 182340 kb
Host smart-a8043d51-cd1f-44c4-96ca-1bb1ca8dd32d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924708287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.924708287
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3969479736
Short name T572
Test name
Test status
Simulation time 13562297 ps
CPU time 0.53 seconds
Started Feb 18 12:28:20 PM PST 24
Finished Feb 18 12:28:31 PM PST 24
Peak memory 181280 kb
Host smart-d5e07263-7b99-44fa-90f0-e63c996f164d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969479736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3969479736
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3339728518
Short name T115
Test name
Test status
Simulation time 59001306 ps
CPU time 0.68 seconds
Started Feb 18 12:28:33 PM PST 24
Finished Feb 18 12:28:36 PM PST 24
Peak memory 192604 kb
Host smart-ac0d2bcc-ddeb-438b-9dbd-69c7536f5047
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339728518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.3339728518
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1016024642
Short name T473
Test name
Test status
Simulation time 21319185 ps
CPU time 1.11 seconds
Started Feb 18 12:28:43 PM PST 24
Finished Feb 18 12:28:48 PM PST 24
Peak memory 196912 kb
Host smart-a09443fe-594f-4904-b95b-2a3789e1fcde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016024642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1016024642
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2510488448
Short name T133
Test name
Test status
Simulation time 270853293 ps
CPU time 0.99 seconds
Started Feb 18 12:28:15 PM PST 24
Finished Feb 18 12:28:22 PM PST 24
Peak memory 192484 kb
Host smart-57002d54-068d-4e2a-b7e6-09167fd3efba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510488448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.2510488448
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3530932640
Short name T471
Test name
Test status
Simulation time 188118149 ps
CPU time 2.08 seconds
Started Feb 18 12:28:53 PM PST 24
Finished Feb 18 12:28:58 PM PST 24
Peak memory 197100 kb
Host smart-3bdcaa3a-6459-407b-9dbd-b6a7a505f432
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530932640 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3530932640
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3843691128
Short name T511
Test name
Test status
Simulation time 91685999 ps
CPU time 0.62 seconds
Started Feb 18 12:28:23 PM PST 24
Finished Feb 18 12:28:30 PM PST 24
Peak memory 182340 kb
Host smart-fa934526-1843-4180-adaa-7357ab3e82e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843691128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.3843691128
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1262692170
Short name T507
Test name
Test status
Simulation time 17463423 ps
CPU time 0.56 seconds
Started Feb 18 12:28:43 PM PST 24
Finished Feb 18 12:28:47 PM PST 24
Peak memory 182116 kb
Host smart-3df4c635-1bda-4627-853e-a36ad2c6f315
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262692170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1262692170
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2441727953
Short name T600
Test name
Test status
Simulation time 101542374 ps
CPU time 0.69 seconds
Started Feb 18 12:28:38 PM PST 24
Finished Feb 18 12:28:41 PM PST 24
Peak memory 191732 kb
Host smart-1affcd1d-b915-474b-aacd-19ef2b51b6cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441727953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2441727953
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3398990797
Short name T508
Test name
Test status
Simulation time 103212237 ps
CPU time 1.16 seconds
Started Feb 18 12:28:24 PM PST 24
Finished Feb 18 12:28:31 PM PST 24
Peak memory 196828 kb
Host smart-3669f44f-6d09-413c-a6a3-0624599a4f01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398990797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3398990797
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2296384044
Short name T522
Test name
Test status
Simulation time 1745693776 ps
CPU time 1.28 seconds
Started Feb 18 12:28:32 PM PST 24
Finished Feb 18 12:28:36 PM PST 24
Peak memory 194704 kb
Host smart-528b5698-139a-41a0-bccf-f7bd8ae2db0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296384044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2296384044
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2117910108
Short name T481
Test name
Test status
Simulation time 95967732 ps
CPU time 0.69 seconds
Started Feb 18 12:28:08 PM PST 24
Finished Feb 18 12:28:16 PM PST 24
Peak memory 182352 kb
Host smart-09bf5f32-04cd-4395-a4ae-45ed6caba255
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117910108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.2117910108
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1613424626
Short name T547
Test name
Test status
Simulation time 291420177 ps
CPU time 3.91 seconds
Started Feb 18 12:28:17 PM PST 24
Finished Feb 18 12:28:26 PM PST 24
Peak memory 193436 kb
Host smart-cb4834dc-45d7-48b1-8642-d5448eb77e68
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613424626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1613424626
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3692794779
Short name T76
Test name
Test status
Simulation time 20218842 ps
CPU time 0.66 seconds
Started Feb 18 12:28:13 PM PST 24
Finished Feb 18 12:28:19 PM PST 24
Peak memory 180640 kb
Host smart-2c0202c5-bdcd-4bf4-b419-790e1f610e60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692794779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.3692794779
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1287486465
Short name T518
Test name
Test status
Simulation time 156880386 ps
CPU time 3.01 seconds
Started Feb 18 12:28:12 PM PST 24
Finished Feb 18 12:28:21 PM PST 24
Peak memory 197132 kb
Host smart-3d3cedd5-8613-408e-8123-70fd962fa13d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287486465 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1287486465
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1579642577
Short name T98
Test name
Test status
Simulation time 30359607 ps
CPU time 0.64 seconds
Started Feb 18 12:28:13 PM PST 24
Finished Feb 18 12:28:19 PM PST 24
Peak memory 180808 kb
Host smart-c5db662a-fc70-4a85-a724-6527a8707262
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579642577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1579642577
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1844181718
Short name T517
Test name
Test status
Simulation time 15537167 ps
CPU time 0.53 seconds
Started Feb 18 12:28:10 PM PST 24
Finished Feb 18 12:28:17 PM PST 24
Peak memory 181288 kb
Host smart-b67576dc-e577-41a6-a9ec-33d3deede487
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844181718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1844181718
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.893852187
Short name T556
Test name
Test status
Simulation time 67051297 ps
CPU time 0.78 seconds
Started Feb 18 12:28:16 PM PST 24
Finished Feb 18 12:28:23 PM PST 24
Peak memory 192852 kb
Host smart-9d242b4c-5c51-4d33-b7cf-bb66bc515a25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893852187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_tim
er_same_csr_outstanding.893852187
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.4196887344
Short name T504
Test name
Test status
Simulation time 330990720 ps
CPU time 2.43 seconds
Started Feb 18 12:28:13 PM PST 24
Finished Feb 18 12:28:21 PM PST 24
Peak memory 195772 kb
Host smart-e7e70b49-38e7-4eff-88e7-ba154f9457cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196887344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.4196887344
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2519856561
Short name T594
Test name
Test status
Simulation time 45389002 ps
CPU time 0.81 seconds
Started Feb 18 12:28:12 PM PST 24
Finished Feb 18 12:28:19 PM PST 24
Peak memory 193088 kb
Host smart-fe8fd615-c96e-4954-92ac-933eccb34c83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519856561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2519856561
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3550412053
Short name T561
Test name
Test status
Simulation time 33917047 ps
CPU time 0.6 seconds
Started Feb 18 12:28:33 PM PST 24
Finished Feb 18 12:28:36 PM PST 24
Peak memory 182076 kb
Host smart-6a56a2f2-150a-4ef4-9f15-4b6d28cecc86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550412053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3550412053
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1685596570
Short name T497
Test name
Test status
Simulation time 41806779 ps
CPU time 0.55 seconds
Started Feb 18 12:28:40 PM PST 24
Finished Feb 18 12:28:43 PM PST 24
Peak memory 182064 kb
Host smart-ae7e57ca-800d-4769-aa96-6e2d88381d3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685596570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1685596570
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3868785474
Short name T577
Test name
Test status
Simulation time 12975396 ps
CPU time 0.61 seconds
Started Feb 18 12:28:27 PM PST 24
Finished Feb 18 12:28:33 PM PST 24
Peak memory 182128 kb
Host smart-4b524a57-e727-4927-86f2-3f95aeb08903
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868785474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3868785474
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3243218809
Short name T570
Test name
Test status
Simulation time 67269070 ps
CPU time 0.53 seconds
Started Feb 18 12:28:22 PM PST 24
Finished Feb 18 12:28:29 PM PST 24
Peak memory 181968 kb
Host smart-94b8e117-b304-4b08-9604-8bdfc7666746
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243218809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3243218809
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.340062024
Short name T589
Test name
Test status
Simulation time 24677690 ps
CPU time 0.6 seconds
Started Feb 18 12:28:39 PM PST 24
Finished Feb 18 12:28:41 PM PST 24
Peak memory 182048 kb
Host smart-2ac971af-0691-4e35-800b-4bef8e2e8250
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340062024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.340062024
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3673523975
Short name T482
Test name
Test status
Simulation time 25242708 ps
CPU time 0.55 seconds
Started Feb 18 12:28:25 PM PST 24
Finished Feb 18 12:28:32 PM PST 24
Peak memory 181280 kb
Host smart-ce7f3919-b411-4b1d-98f6-f7115a144f9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673523975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3673523975
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2736486394
Short name T502
Test name
Test status
Simulation time 184450550 ps
CPU time 0.53 seconds
Started Feb 18 12:28:47 PM PST 24
Finished Feb 18 12:28:50 PM PST 24
Peak memory 181276 kb
Host smart-3f1f075e-160b-4119-9d70-090a0e46e4f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736486394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2736486394
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3963624740
Short name T476
Test name
Test status
Simulation time 18319956 ps
CPU time 0.59 seconds
Started Feb 18 12:28:41 PM PST 24
Finished Feb 18 12:28:45 PM PST 24
Peak memory 182040 kb
Host smart-ec912e3c-2bf8-484f-9111-c667583293b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963624740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3963624740
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3698979610
Short name T539
Test name
Test status
Simulation time 16014342 ps
CPU time 0.54 seconds
Started Feb 18 12:28:30 PM PST 24
Finished Feb 18 12:28:34 PM PST 24
Peak memory 181916 kb
Host smart-9aab7c79-3a9b-41a0-bee4-2d49133075e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698979610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3698979610
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2123224930
Short name T590
Test name
Test status
Simulation time 16873316 ps
CPU time 0.58 seconds
Started Feb 18 12:28:34 PM PST 24
Finished Feb 18 12:28:37 PM PST 24
Peak memory 182112 kb
Host smart-42b0a45c-2dea-414f-a618-7aa934230f15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123224930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2123224930
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2879957010
Short name T99
Test name
Test status
Simulation time 106288055 ps
CPU time 0.74 seconds
Started Feb 18 12:28:20 PM PST 24
Finished Feb 18 12:28:27 PM PST 24
Peak memory 192064 kb
Host smart-8de84e20-9eeb-4641-bfef-0355e7a731be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879957010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.2879957010
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2241438473
Short name T490
Test name
Test status
Simulation time 92672369 ps
CPU time 3.05 seconds
Started Feb 18 12:28:22 PM PST 24
Finished Feb 18 12:28:31 PM PST 24
Peak memory 190644 kb
Host smart-710916c3-12fc-4088-9ac7-01a99acc1f1c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241438473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2241438473
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1548595531
Short name T86
Test name
Test status
Simulation time 25944977 ps
CPU time 0.58 seconds
Started Feb 18 12:28:07 PM PST 24
Finished Feb 18 12:28:14 PM PST 24
Peak memory 182412 kb
Host smart-85f6a827-739c-4ed2-a9b1-243ec00c80a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548595531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.1548595531
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1271042516
Short name T563
Test name
Test status
Simulation time 554957967 ps
CPU time 2.12 seconds
Started Feb 18 12:28:17 PM PST 24
Finished Feb 18 12:28:25 PM PST 24
Peak memory 197072 kb
Host smart-bc486ca1-e620-425e-ae31-9b73480eac98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271042516 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1271042516
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3048867833
Short name T548
Test name
Test status
Simulation time 15528686 ps
CPU time 0.59 seconds
Started Feb 18 12:28:21 PM PST 24
Finished Feb 18 12:28:29 PM PST 24
Peak memory 182348 kb
Host smart-beda879c-7887-449c-9293-f4f915812d64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048867833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3048867833
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3229771644
Short name T585
Test name
Test status
Simulation time 45041547 ps
CPU time 0.64 seconds
Started Feb 18 12:28:13 PM PST 24
Finished Feb 18 12:28:19 PM PST 24
Peak memory 180204 kb
Host smart-c1a55ea6-e8e6-4116-a40f-c070d2b310c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229771644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3229771644
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.4022835654
Short name T538
Test name
Test status
Simulation time 63866261 ps
CPU time 0.59 seconds
Started Feb 18 12:28:20 PM PST 24
Finished Feb 18 12:28:26 PM PST 24
Peak memory 190964 kb
Host smart-8a7b6639-89dc-4c82-bdbc-350ebd3fd6b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022835654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.4022835654
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2952081043
Short name T488
Test name
Test status
Simulation time 314016229 ps
CPU time 1.43 seconds
Started Feb 18 12:28:08 PM PST 24
Finished Feb 18 12:28:17 PM PST 24
Peak memory 197000 kb
Host smart-b5ba4086-8686-4620-bb65-10f564c2198f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952081043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2952081043
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3008029492
Short name T29
Test name
Test status
Simulation time 87727888 ps
CPU time 1.11 seconds
Started Feb 18 12:28:21 PM PST 24
Finished Feb 18 12:28:29 PM PST 24
Peak memory 194092 kb
Host smart-3793dfaa-26a1-4edb-b58c-6f0e05443975
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008029492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3008029492
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3767688238
Short name T537
Test name
Test status
Simulation time 45241549 ps
CPU time 0.6 seconds
Started Feb 18 12:28:43 PM PST 24
Finished Feb 18 12:28:47 PM PST 24
Peak memory 181276 kb
Host smart-8d5c935d-3ae0-4c38-8e25-82392af4ade9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767688238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3767688238
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3871487136
Short name T554
Test name
Test status
Simulation time 15596263 ps
CPU time 0.61 seconds
Started Feb 18 12:28:09 PM PST 24
Finished Feb 18 12:28:17 PM PST 24
Peak memory 180600 kb
Host smart-38ee224b-2cca-4b38-a937-8ec94e623d72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871487136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3871487136
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.4189711028
Short name T519
Test name
Test status
Simulation time 16536860 ps
CPU time 0.58 seconds
Started Feb 18 12:28:35 PM PST 24
Finished Feb 18 12:28:37 PM PST 24
Peak memory 182064 kb
Host smart-25142d1c-18e0-422f-bfb3-fb12ab2dcb81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189711028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.4189711028
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.130320985
Short name T568
Test name
Test status
Simulation time 32902063 ps
CPU time 0.59 seconds
Started Feb 18 12:28:23 PM PST 24
Finished Feb 18 12:28:30 PM PST 24
Peak memory 182164 kb
Host smart-e78859e8-937a-4c57-9d5b-3e2cedebc638
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130320985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.130320985
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2271492075
Short name T566
Test name
Test status
Simulation time 17171407 ps
CPU time 0.55 seconds
Started Feb 18 12:28:45 PM PST 24
Finished Feb 18 12:28:49 PM PST 24
Peak memory 182064 kb
Host smart-df4b3cd0-3010-489a-bbcd-f12731c87cd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271492075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2271492075
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3824518290
Short name T545
Test name
Test status
Simulation time 32520309 ps
CPU time 0.58 seconds
Started Feb 18 12:28:23 PM PST 24
Finished Feb 18 12:28:30 PM PST 24
Peak memory 182148 kb
Host smart-ffa6db35-29c0-4108-8e90-59661e499ef2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824518290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3824518290
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.8761575
Short name T515
Test name
Test status
Simulation time 15823744 ps
CPU time 0.56 seconds
Started Feb 18 12:28:40 PM PST 24
Finished Feb 18 12:28:44 PM PST 24
Peak memory 181284 kb
Host smart-a09421d5-eee6-4334-9a50-aee14bb722c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8761575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.8761575
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1321485783
Short name T588
Test name
Test status
Simulation time 50738000 ps
CPU time 0.63 seconds
Started Feb 18 12:28:32 PM PST 24
Finished Feb 18 12:28:36 PM PST 24
Peak memory 181028 kb
Host smart-cd1dff15-5559-45dd-9e2a-2bcf6de32606
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321485783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1321485783
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.51765527
Short name T574
Test name
Test status
Simulation time 13007380 ps
CPU time 0.6 seconds
Started Feb 18 12:28:17 PM PST 24
Finished Feb 18 12:28:23 PM PST 24
Peak memory 180608 kb
Host smart-88b0c3e6-1821-42c8-a646-f02fc8f9987a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51765527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.51765527
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1825709014
Short name T593
Test name
Test status
Simulation time 48463701 ps
CPU time 0.56 seconds
Started Feb 18 12:28:27 PM PST 24
Finished Feb 18 12:28:33 PM PST 24
Peak memory 181860 kb
Host smart-2548ec29-a333-4f27-aba9-65b0d9128c69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825709014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1825709014
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3280367055
Short name T81
Test name
Test status
Simulation time 14108487 ps
CPU time 0.6 seconds
Started Feb 18 12:28:15 PM PST 24
Finished Feb 18 12:28:22 PM PST 24
Peak memory 182364 kb
Host smart-7fb91549-0ebc-4cbf-a1a3-b0290be738a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280367055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3280367055
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2763745761
Short name T129
Test name
Test status
Simulation time 314279603 ps
CPU time 3.01 seconds
Started Feb 18 12:34:37 PM PST 24
Finished Feb 18 12:34:47 PM PST 24
Peak memory 181792 kb
Host smart-015f7090-97d8-4685-b84e-b84c8761cf0f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763745761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2763745761
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3770973147
Short name T87
Test name
Test status
Simulation time 12897557 ps
CPU time 0.53 seconds
Started Feb 18 12:28:20 PM PST 24
Finished Feb 18 12:28:26 PM PST 24
Peak memory 181716 kb
Host smart-456d3b75-6143-4e76-aebc-7735418f24d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770973147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3770973147
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.4136545214
Short name T516
Test name
Test status
Simulation time 59531607 ps
CPU time 1.53 seconds
Started Feb 18 12:35:19 PM PST 24
Finished Feb 18 12:35:23 PM PST 24
Peak memory 197204 kb
Host smart-59112b84-15fc-4d6d-b3fb-436701116dc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136545214 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.4136545214
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3690101988
Short name T500
Test name
Test status
Simulation time 30026172 ps
CPU time 0.53 seconds
Started Feb 18 12:28:17 PM PST 24
Finished Feb 18 12:28:23 PM PST 24
Peak memory 182320 kb
Host smart-382619f4-d3d8-45c5-af67-bceb284ca64a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690101988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3690101988
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1926095828
Short name T540
Test name
Test status
Simulation time 22649237 ps
CPU time 0.53 seconds
Started Feb 18 12:28:13 PM PST 24
Finished Feb 18 12:28:19 PM PST 24
Peak memory 182056 kb
Host smart-ea242a98-6e30-4fc7-b66c-afe7489ad784
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926095828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1926095828
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2755971655
Short name T587
Test name
Test status
Simulation time 48882837 ps
CPU time 0.74 seconds
Started Feb 18 12:28:18 PM PST 24
Finished Feb 18 12:28:24 PM PST 24
Peak memory 192796 kb
Host smart-012492df-5667-4f90-b3c5-9fb42eccc5d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755971655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.2755971655
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1173758135
Short name T560
Test name
Test status
Simulation time 194801243 ps
CPU time 2.07 seconds
Started Feb 18 12:28:21 PM PST 24
Finished Feb 18 12:28:29 PM PST 24
Peak memory 197080 kb
Host smart-903aff65-27a4-47c7-8132-b8c26037d05e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173758135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1173758135
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3856301289
Short name T525
Test name
Test status
Simulation time 23145192 ps
CPU time 0.51 seconds
Started Feb 18 12:28:28 PM PST 24
Finished Feb 18 12:28:33 PM PST 24
Peak memory 181096 kb
Host smart-b979026f-92c9-4f58-ba8b-ba4c4fc347e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856301289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3856301289
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.923989985
Short name T569
Test name
Test status
Simulation time 28658139 ps
CPU time 0.59 seconds
Started Feb 18 12:28:31 PM PST 24
Finished Feb 18 12:28:34 PM PST 24
Peak memory 182100 kb
Host smart-8de5c188-b256-4142-ac1a-cc9d1404e5b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923989985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.923989985
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1365593996
Short name T521
Test name
Test status
Simulation time 97383825 ps
CPU time 0.59 seconds
Started Feb 18 12:28:39 PM PST 24
Finished Feb 18 12:28:43 PM PST 24
Peak memory 182056 kb
Host smart-cf5c9910-5fc0-4626-8a18-433d4adc63bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365593996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1365593996
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1367476736
Short name T520
Test name
Test status
Simulation time 74677106 ps
CPU time 0.58 seconds
Started Feb 18 12:28:36 PM PST 24
Finished Feb 18 12:28:38 PM PST 24
Peak memory 182056 kb
Host smart-fdc43ae2-539d-4742-849c-a75cda2d7d8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367476736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1367476736
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3509983262
Short name T596
Test name
Test status
Simulation time 31082805 ps
CPU time 0.53 seconds
Started Feb 18 12:28:30 PM PST 24
Finished Feb 18 12:28:34 PM PST 24
Peak memory 182064 kb
Host smart-ff0a6d3f-5e02-4fdf-b3c5-9eeb4404dc41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509983262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3509983262
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1379094742
Short name T544
Test name
Test status
Simulation time 47644316 ps
CPU time 0.55 seconds
Started Feb 18 12:28:32 PM PST 24
Finished Feb 18 12:28:35 PM PST 24
Peak memory 182056 kb
Host smart-4528bc18-42bc-4110-99fa-d3d5dd2dcd1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379094742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1379094742
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2537158304
Short name T583
Test name
Test status
Simulation time 146324163 ps
CPU time 0.55 seconds
Started Feb 18 12:28:42 PM PST 24
Finished Feb 18 12:28:45 PM PST 24
Peak memory 182060 kb
Host smart-b9cf80cb-ecd3-473b-ae2e-3a6155e22d72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537158304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2537158304
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3455988166
Short name T529
Test name
Test status
Simulation time 17692605 ps
CPU time 0.58 seconds
Started Feb 18 12:28:32 PM PST 24
Finished Feb 18 12:28:35 PM PST 24
Peak memory 182056 kb
Host smart-f7671abb-31fe-4f54-ba11-344febdd8adf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455988166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3455988166
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3227546316
Short name T551
Test name
Test status
Simulation time 92037248 ps
CPU time 0.57 seconds
Started Feb 18 12:28:43 PM PST 24
Finished Feb 18 12:28:46 PM PST 24
Peak memory 182060 kb
Host smart-0a3f3663-fcc4-4a3f-8836-806490d1f32d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227546316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3227546316
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1418674865
Short name T571
Test name
Test status
Simulation time 12468028 ps
CPU time 0.58 seconds
Started Feb 18 12:28:21 PM PST 24
Finished Feb 18 12:28:29 PM PST 24
Peak memory 181960 kb
Host smart-909d156e-3e82-433b-9304-f183619c6386
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418674865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1418674865
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2986399153
Short name T31
Test name
Test status
Simulation time 155774736 ps
CPU time 3.07 seconds
Started Feb 18 12:28:05 PM PST 24
Finished Feb 18 12:28:13 PM PST 24
Peak memory 197036 kb
Host smart-df78c29e-db87-471c-94aa-ef3f53523dee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986399153 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2986399153
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1513291850
Short name T582
Test name
Test status
Simulation time 34384233 ps
CPU time 0.59 seconds
Started Feb 18 12:28:10 PM PST 24
Finished Feb 18 12:28:17 PM PST 24
Peak memory 181240 kb
Host smart-5236747b-be0f-4c4c-a0d9-e661e4fa58e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513291850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1513291850
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.456883553
Short name T595
Test name
Test status
Simulation time 53855058 ps
CPU time 0.53 seconds
Started Feb 18 12:28:12 PM PST 24
Finished Feb 18 12:28:18 PM PST 24
Peak memory 182100 kb
Host smart-25249274-bfeb-4703-bdd4-47eaa6035cd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456883553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.456883553
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2384930267
Short name T578
Test name
Test status
Simulation time 25045675 ps
CPU time 0.66 seconds
Started Feb 18 12:28:14 PM PST 24
Finished Feb 18 12:28:21 PM PST 24
Peak memory 191628 kb
Host smart-b356676b-2989-4238-9b4b-23ff7faf888f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384930267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2384930267
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1891937380
Short name T492
Test name
Test status
Simulation time 167321102 ps
CPU time 2.33 seconds
Started Feb 18 12:28:26 PM PST 24
Finished Feb 18 12:28:34 PM PST 24
Peak memory 197068 kb
Host smart-2c833fd6-5cd7-4e6f-8e4b-ffa27062ceda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891937380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1891937380
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1625608802
Short name T513
Test name
Test status
Simulation time 250511755 ps
CPU time 1.12 seconds
Started Feb 18 12:28:04 PM PST 24
Finished Feb 18 12:28:10 PM PST 24
Peak memory 194480 kb
Host smart-0eeafc88-015f-47b5-8c7c-f704e162f729
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625608802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1625608802
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.4101061472
Short name T509
Test name
Test status
Simulation time 147517591 ps
CPU time 1.26 seconds
Started Feb 18 12:28:20 PM PST 24
Finished Feb 18 12:28:27 PM PST 24
Peak memory 197104 kb
Host smart-0c6e0770-57b9-4960-927c-0ab5274d5489
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101061472 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.4101061472
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3729788647
Short name T499
Test name
Test status
Simulation time 33882999 ps
CPU time 0.55 seconds
Started Feb 18 12:28:16 PM PST 24
Finished Feb 18 12:28:22 PM PST 24
Peak memory 182164 kb
Host smart-5889c20d-ebaa-492d-8c2b-dde12740e426
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729788647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3729788647
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1784551168
Short name T512
Test name
Test status
Simulation time 31961755 ps
CPU time 0.56 seconds
Started Feb 18 12:28:36 PM PST 24
Finished Feb 18 12:28:39 PM PST 24
Peak memory 182016 kb
Host smart-157e66f8-a76a-4e91-b331-f987d421a0d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784551168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1784551168
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2524149384
Short name T113
Test name
Test status
Simulation time 71423925 ps
CPU time 0.68 seconds
Started Feb 18 12:28:08 PM PST 24
Finished Feb 18 12:28:15 PM PST 24
Peak memory 191696 kb
Host smart-5dc1c909-9f3e-4990-97ee-249c79041efd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524149384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.2524149384
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1802109369
Short name T486
Test name
Test status
Simulation time 227977422 ps
CPU time 1.35 seconds
Started Feb 18 12:28:05 PM PST 24
Finished Feb 18 12:28:11 PM PST 24
Peak memory 196664 kb
Host smart-f8884c1f-56af-49a1-b795-bb2af09d7fc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802109369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1802109369
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.4253906614
Short name T532
Test name
Test status
Simulation time 424646571 ps
CPU time 1.35 seconds
Started Feb 18 12:28:04 PM PST 24
Finished Feb 18 12:28:10 PM PST 24
Peak memory 194496 kb
Host smart-07610087-5e5e-465a-8747-6e0f06b1f317
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253906614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.4253906614
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2745837079
Short name T579
Test name
Test status
Simulation time 207132293 ps
CPU time 3.35 seconds
Started Feb 18 12:28:19 PM PST 24
Finished Feb 18 12:28:28 PM PST 24
Peak memory 197088 kb
Host smart-f84da249-ab76-4f6c-bed8-3ce451aaef52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745837079 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2745837079
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2258322801
Short name T109
Test name
Test status
Simulation time 54015473 ps
CPU time 0.57 seconds
Started Feb 18 12:28:12 PM PST 24
Finished Feb 18 12:28:19 PM PST 24
Peak memory 182340 kb
Host smart-5d72cb6d-c20e-4b74-95b6-73a906a59435
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258322801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2258322801
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1142393658
Short name T580
Test name
Test status
Simulation time 33471560 ps
CPU time 0.58 seconds
Started Feb 18 12:28:44 PM PST 24
Finished Feb 18 12:28:48 PM PST 24
Peak memory 182112 kb
Host smart-54e3fa57-841b-4010-81d1-7b93db2c7167
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142393658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1142393658
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2147094785
Short name T110
Test name
Test status
Simulation time 27036405 ps
CPU time 0.78 seconds
Started Feb 18 12:28:13 PM PST 24
Finished Feb 18 12:28:19 PM PST 24
Peak memory 189700 kb
Host smart-a090a3ab-8b72-4428-851e-428e586822c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147094785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2147094785
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3116143386
Short name T494
Test name
Test status
Simulation time 366620069 ps
CPU time 1.73 seconds
Started Feb 18 12:28:33 PM PST 24
Finished Feb 18 12:28:37 PM PST 24
Peak memory 196764 kb
Host smart-8a1e72d1-0642-4f3d-9997-cc04d092eaa3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116143386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3116143386
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.4046621321
Short name T584
Test name
Test status
Simulation time 141004069 ps
CPU time 1.34 seconds
Started Feb 18 12:28:06 PM PST 24
Finished Feb 18 12:28:14 PM PST 24
Peak memory 194636 kb
Host smart-c2b494d7-f24f-4efa-a225-85382e9bdb65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046621321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.4046621321
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.4170593215
Short name T474
Test name
Test status
Simulation time 98365644 ps
CPU time 1.41 seconds
Started Feb 18 12:28:50 PM PST 24
Finished Feb 18 12:28:53 PM PST 24
Peak memory 197068 kb
Host smart-4ea2f30f-0d67-43fb-b7b2-ba887dd42378
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170593215 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.4170593215
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3501513278
Short name T599
Test name
Test status
Simulation time 27265577 ps
CPU time 0.62 seconds
Started Feb 18 12:28:11 PM PST 24
Finished Feb 18 12:28:18 PM PST 24
Peak memory 181680 kb
Host smart-9ceb1d5d-3665-49ea-9c87-8d22022a3ceb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501513278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3501513278
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3791511741
Short name T495
Test name
Test status
Simulation time 13653331 ps
CPU time 0.56 seconds
Started Feb 18 12:28:14 PM PST 24
Finished Feb 18 12:28:21 PM PST 24
Peak memory 181272 kb
Host smart-fa815678-c5cc-447e-835c-894018434fcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791511741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3791511741
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1140178325
Short name T581
Test name
Test status
Simulation time 81156406 ps
CPU time 0.9 seconds
Started Feb 18 12:28:30 PM PST 24
Finished Feb 18 12:28:34 PM PST 24
Peak memory 191388 kb
Host smart-a3c7bc6d-52f2-46b1-937e-57d6aca189f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140178325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1140178325
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.344664587
Short name T527
Test name
Test status
Simulation time 174923152 ps
CPU time 2.82 seconds
Started Feb 18 12:28:05 PM PST 24
Finished Feb 18 12:28:12 PM PST 24
Peak memory 197068 kb
Host smart-58b7a0eb-4e4e-49cf-bf75-6035be28f13e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344664587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.344664587
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2346423585
Short name T524
Test name
Test status
Simulation time 167541256 ps
CPU time 0.84 seconds
Started Feb 18 12:28:24 PM PST 24
Finished Feb 18 12:28:31 PM PST 24
Peak memory 193292 kb
Host smart-c418f4b3-9669-4a72-ba9a-9e558357aa4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346423585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2346423585
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2093120076
Short name T555
Test name
Test status
Simulation time 326877165 ps
CPU time 1.6 seconds
Started Feb 18 12:28:19 PM PST 24
Finished Feb 18 12:28:27 PM PST 24
Peak memory 197080 kb
Host smart-350347b0-3ea0-4ed0-a000-f7f3fe4925df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093120076 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2093120076
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3975179559
Short name T97
Test name
Test status
Simulation time 12092732 ps
CPU time 0.6 seconds
Started Feb 18 12:28:09 PM PST 24
Finished Feb 18 12:28:17 PM PST 24
Peak memory 181808 kb
Host smart-a7ab1a56-6f8c-43d4-87d1-6bd1cc038a61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975179559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3975179559
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3206841568
Short name T484
Test name
Test status
Simulation time 27000240 ps
CPU time 0.55 seconds
Started Feb 18 12:28:14 PM PST 24
Finished Feb 18 12:28:20 PM PST 24
Peak memory 181284 kb
Host smart-00393153-5b48-4b59-929b-ed03ac1121e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206841568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3206841568
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1718433857
Short name T558
Test name
Test status
Simulation time 73117941 ps
CPU time 0.83 seconds
Started Feb 18 12:28:11 PM PST 24
Finished Feb 18 12:28:18 PM PST 24
Peak memory 190516 kb
Host smart-4f4737e9-6044-44d1-810e-280796d48ffb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718433857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1718433857
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3564387437
Short name T479
Test name
Test status
Simulation time 185371058 ps
CPU time 3.57 seconds
Started Feb 18 12:28:23 PM PST 24
Finished Feb 18 12:28:33 PM PST 24
Peak memory 197040 kb
Host smart-12209207-4e9e-44a2-a096-844b7b63ced1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564387437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3564387437
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1868989686
Short name T543
Test name
Test status
Simulation time 87085066 ps
CPU time 1.21 seconds
Started Feb 18 12:28:22 PM PST 24
Finished Feb 18 12:28:30 PM PST 24
Peak memory 194260 kb
Host smart-25fba12f-0828-4171-9704-0c7371667dab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868989686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1868989686
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.1108370441
Short name T24
Test name
Test status
Simulation time 671242647594 ps
CPU time 104.78 seconds
Started Feb 18 12:30:24 PM PST 24
Finished Feb 18 12:32:19 PM PST 24
Peak memory 182476 kb
Host smart-66414528-983c-42ad-a136-fbbccdb179cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108370441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.1108370441
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3444545379
Short name T399
Test name
Test status
Simulation time 43956249168 ps
CPU time 54.9 seconds
Started Feb 18 12:30:25 PM PST 24
Finished Feb 18 12:31:31 PM PST 24
Peak memory 190580 kb
Host smart-9b60e654-5733-4c33-9a3f-76db4ec6377f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444545379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3444545379
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1879231352
Short name T345
Test name
Test status
Simulation time 449839360295 ps
CPU time 246.52 seconds
Started Feb 18 12:30:30 PM PST 24
Finished Feb 18 12:34:46 PM PST 24
Peak memory 182256 kb
Host smart-aa1287a9-7db7-44a2-b3fb-113f283b2dd7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879231352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1879231352
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2126036672
Short name T395
Test name
Test status
Simulation time 163595247097 ps
CPU time 182.06 seconds
Started Feb 18 12:30:24 PM PST 24
Finished Feb 18 12:33:36 PM PST 24
Peak memory 182324 kb
Host smart-6d0f4c21-cb4c-46ff-b599-10750b9be414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126036672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2126036672
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.4079397758
Short name T169
Test name
Test status
Simulation time 41910712978 ps
CPU time 68.85 seconds
Started Feb 18 12:30:24 PM PST 24
Finished Feb 18 12:31:42 PM PST 24
Peak memory 190504 kb
Host smart-4c526f9f-c615-43b3-adb1-bf99701b8850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079397758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.4079397758
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.510052274
Short name T254
Test name
Test status
Simulation time 67204664994 ps
CPU time 42.13 seconds
Started Feb 18 12:30:22 PM PST 24
Finished Feb 18 12:31:11 PM PST 24
Peak memory 194364 kb
Host smart-eeb2008f-26e6-4bac-aa40-2f0fd18c1d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510052274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.510052274
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.260927509
Short name T14
Test name
Test status
Simulation time 39830459 ps
CPU time 0.77 seconds
Started Feb 18 12:30:37 PM PST 24
Finished Feb 18 12:30:43 PM PST 24
Peak memory 212564 kb
Host smart-177ea263-1445-4805-a110-11596146b28f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260927509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.260927509
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.363558761
Short name T346
Test name
Test status
Simulation time 70368169158 ps
CPU time 136.56 seconds
Started Feb 18 12:30:21 PM PST 24
Finished Feb 18 12:32:44 PM PST 24
Peak memory 182292 kb
Host smart-061c74fc-699a-4864-bdd7-10ec550a935b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363558761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.363558761
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.2343216495
Short name T107
Test name
Test status
Simulation time 206353586805 ps
CPU time 336.79 seconds
Started Feb 18 12:30:26 PM PST 24
Finished Feb 18 12:36:13 PM PST 24
Peak memory 182384 kb
Host smart-7b34873f-962a-4d84-9d15-7b91ebed8578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343216495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2343216495
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.516610955
Short name T253
Test name
Test status
Simulation time 51357647451 ps
CPU time 91.25 seconds
Started Feb 18 12:30:20 PM PST 24
Finished Feb 18 12:31:58 PM PST 24
Peak memory 190520 kb
Host smart-3a540dfa-cbfa-4930-a48d-5a41177b64f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516610955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.516610955
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.753820557
Short name T51
Test name
Test status
Simulation time 38913940557 ps
CPU time 306.07 seconds
Started Feb 18 12:30:26 PM PST 24
Finished Feb 18 12:35:42 PM PST 24
Peak memory 197108 kb
Host smart-38843fc0-3ce7-4b93-8a13-a311ad84fdcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753820557 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.753820557
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.1558325866
Short name T324
Test name
Test status
Simulation time 89851409282 ps
CPU time 54.42 seconds
Started Feb 18 12:31:18 PM PST 24
Finished Feb 18 12:32:16 PM PST 24
Peak memory 182304 kb
Host smart-f33205c3-9020-47c6-8e28-a8e5d72f5cfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558325866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1558325866
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.2115792997
Short name T365
Test name
Test status
Simulation time 260766165387 ps
CPU time 154.34 seconds
Started Feb 18 12:31:19 PM PST 24
Finished Feb 18 12:33:57 PM PST 24
Peak memory 182300 kb
Host smart-88019bf7-6490-4b53-89ef-d5f8ee278706
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115792997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2115792997
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.3549893895
Short name T455
Test name
Test status
Simulation time 320750119478 ps
CPU time 859.62 seconds
Started Feb 18 12:31:15 PM PST 24
Finished Feb 18 12:45:38 PM PST 24
Peak memory 190516 kb
Host smart-82f49bcb-4cf3-4b2c-bf9a-fb86e21d0114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549893895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3549893895
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.36460080
Short name T456
Test name
Test status
Simulation time 658735566585 ps
CPU time 2000.51 seconds
Started Feb 18 12:31:21 PM PST 24
Finished Feb 18 01:04:44 PM PST 24
Peak memory 190540 kb
Host smart-ac89def7-6472-43bb-a9fb-e0f5e9851534
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36460080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.36460080
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.396856242
Short name T441
Test name
Test status
Simulation time 1597349314275 ps
CPU time 315.56 seconds
Started Feb 18 12:31:13 PM PST 24
Finished Feb 18 12:36:31 PM PST 24
Peak memory 190580 kb
Host smart-dca9914c-d8f6-476a-beeb-db7c38aad36f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396856242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.396856242
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2444444503
Short name T422
Test name
Test status
Simulation time 9012925169 ps
CPU time 10.07 seconds
Started Feb 18 12:30:42 PM PST 24
Finished Feb 18 12:30:56 PM PST 24
Peak memory 182356 kb
Host smart-fd785866-c711-435f-a6c9-008c09fdd9c7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444444503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2444444503
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.76377218
Short name T437
Test name
Test status
Simulation time 92845383539 ps
CPU time 149.35 seconds
Started Feb 18 12:30:32 PM PST 24
Finished Feb 18 12:33:10 PM PST 24
Peak memory 182284 kb
Host smart-ec978fe9-af98-4511-8a8f-84d259ed6007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76377218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.76377218
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.2750418999
Short name T348
Test name
Test status
Simulation time 405376924930 ps
CPU time 636.13 seconds
Started Feb 18 12:30:42 PM PST 24
Finished Feb 18 12:41:26 PM PST 24
Peak memory 190620 kb
Host smart-8e9e0ca9-16a9-4576-9f7c-0d580bca00bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750418999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2750418999
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1179759469
Short name T374
Test name
Test status
Simulation time 258421029 ps
CPU time 1.03 seconds
Started Feb 18 12:30:40 PM PST 24
Finished Feb 18 12:30:45 PM PST 24
Peak memory 191988 kb
Host smart-b25863bc-6d1d-46c9-b8c6-e2686ae69fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179759469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1179759469
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.3039898570
Short name T32
Test name
Test status
Simulation time 58003261608 ps
CPU time 96.82 seconds
Started Feb 18 12:30:29 PM PST 24
Finished Feb 18 12:32:16 PM PST 24
Peak memory 197040 kb
Host smart-faeda284-525d-4fff-8f2d-2a369bb70e44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039898570 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.3039898570
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.rv_timer_random.1022194934
Short name T321
Test name
Test status
Simulation time 416456745549 ps
CPU time 269.38 seconds
Started Feb 18 12:31:17 PM PST 24
Finished Feb 18 12:35:51 PM PST 24
Peak memory 190564 kb
Host smart-e957d4a7-94eb-40da-9580-aa12ec1d167f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022194934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1022194934
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.660883914
Short name T58
Test name
Test status
Simulation time 55118998831 ps
CPU time 96.29 seconds
Started Feb 18 12:31:10 PM PST 24
Finished Feb 18 12:32:48 PM PST 24
Peak memory 190572 kb
Host smart-ac68a0ef-52a2-4916-9ccd-0033c627f4e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660883914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.660883914
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.1787302730
Short name T145
Test name
Test status
Simulation time 297058277142 ps
CPU time 271.25 seconds
Started Feb 18 12:31:13 PM PST 24
Finished Feb 18 12:35:46 PM PST 24
Peak memory 190512 kb
Host smart-1e9475be-bf20-4290-8945-df8b5b54349e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787302730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1787302730
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.812499258
Short name T298
Test name
Test status
Simulation time 134717692280 ps
CPU time 766.77 seconds
Started Feb 18 12:31:12 PM PST 24
Finished Feb 18 12:44:00 PM PST 24
Peak memory 192840 kb
Host smart-487b5446-5eb6-462c-b2f5-df08c01dd396
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812499258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.812499258
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3977378179
Short name T279
Test name
Test status
Simulation time 540769733972 ps
CPU time 535.45 seconds
Started Feb 18 12:31:15 PM PST 24
Finished Feb 18 12:40:14 PM PST 24
Peak memory 190548 kb
Host smart-fbb82e03-a3d7-4e81-b173-8af84a87f983
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977378179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3977378179
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.3294035471
Short name T277
Test name
Test status
Simulation time 203033344658 ps
CPU time 156.57 seconds
Started Feb 18 12:31:21 PM PST 24
Finished Feb 18 12:34:00 PM PST 24
Peak memory 190500 kb
Host smart-64235318-ad78-4113-8d00-5470cdcc3d5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294035471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3294035471
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.2473457674
Short name T159
Test name
Test status
Simulation time 119556904516 ps
CPU time 201.96 seconds
Started Feb 18 12:30:20 PM PST 24
Finished Feb 18 12:33:48 PM PST 24
Peak memory 182312 kb
Host smart-28129d3e-5ab6-48f3-8ddb-d9b6d2fe1bb6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473457674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.2473457674
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.721668346
Short name T389
Test name
Test status
Simulation time 133751775893 ps
CPU time 185.17 seconds
Started Feb 18 12:30:44 PM PST 24
Finished Feb 18 12:33:53 PM PST 24
Peak memory 182300 kb
Host smart-df783f2e-623f-460b-b0c2-255c5f0a2e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721668346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.721668346
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.844795630
Short name T440
Test name
Test status
Simulation time 18272241637 ps
CPU time 34.41 seconds
Started Feb 18 12:30:56 PM PST 24
Finished Feb 18 12:31:33 PM PST 24
Peak memory 182364 kb
Host smart-9de8e366-ef07-4b53-86e5-6cce8c687e38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844795630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.844795630
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1837655
Short name T354
Test name
Test status
Simulation time 70571796495 ps
CPU time 508.94 seconds
Started Feb 18 12:30:23 PM PST 24
Finished Feb 18 12:39:00 PM PST 24
Peak memory 190500 kb
Host smart-ab8855ad-c51b-48c0-b9eb-da05332d78cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1837655
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2881224823
Short name T209
Test name
Test status
Simulation time 196991320206 ps
CPU time 866.11 seconds
Started Feb 18 12:30:24 PM PST 24
Finished Feb 18 12:44:59 PM PST 24
Peak memory 190540 kb
Host smart-8791d145-d2bb-4c20-a6ee-12aa588111aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881224823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2881224823
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.2350165195
Short name T12
Test name
Test status
Simulation time 19831232880 ps
CPU time 153.1 seconds
Started Feb 18 12:30:31 PM PST 24
Finished Feb 18 12:33:17 PM PST 24
Peak memory 196204 kb
Host smart-a24a77ec-e2e0-440f-baed-d81c1be0b085
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350165195 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.2350165195
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/121.rv_timer_random.4230148445
Short name T234
Test name
Test status
Simulation time 74415864431 ps
CPU time 127.19 seconds
Started Feb 18 12:31:15 PM PST 24
Finished Feb 18 12:33:27 PM PST 24
Peak memory 193444 kb
Host smart-590cac44-cdbb-4402-9dc4-2370d7cfa616
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230148445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.4230148445
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.4270233884
Short name T347
Test name
Test status
Simulation time 73038404047 ps
CPU time 32.59 seconds
Started Feb 18 12:31:14 PM PST 24
Finished Feb 18 12:31:50 PM PST 24
Peak memory 182372 kb
Host smart-c2e27b34-8ab7-4dc7-bde4-0944c0da9226
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270233884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.4270233884
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.1233168388
Short name T5
Test name
Test status
Simulation time 195363027523 ps
CPU time 463.18 seconds
Started Feb 18 12:31:21 PM PST 24
Finished Feb 18 12:39:06 PM PST 24
Peak memory 190552 kb
Host smart-082a43ce-d2df-4c97-96dd-e2f03c6dba2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233168388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1233168388
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2792994302
Short name T143
Test name
Test status
Simulation time 53313739006 ps
CPU time 155.89 seconds
Started Feb 18 12:31:16 PM PST 24
Finished Feb 18 12:33:56 PM PST 24
Peak memory 190348 kb
Host smart-23958be4-bec2-4909-80dd-55e00223a6e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792994302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2792994302
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.2855176171
Short name T161
Test name
Test status
Simulation time 373071319018 ps
CPU time 460.09 seconds
Started Feb 18 12:31:23 PM PST 24
Finished Feb 18 12:39:05 PM PST 24
Peak memory 190520 kb
Host smart-20e4a909-8973-4b54-9574-66c75ecfd66b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855176171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2855176171
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.2289998173
Short name T383
Test name
Test status
Simulation time 62444262362 ps
CPU time 64.63 seconds
Started Feb 18 12:31:15 PM PST 24
Finished Feb 18 12:32:23 PM PST 24
Peak memory 182332 kb
Host smart-504bc1cf-a550-4e9e-84a9-032a6277a118
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289998173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2289998173
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.110674360
Short name T206
Test name
Test status
Simulation time 261457870246 ps
CPU time 253.66 seconds
Started Feb 18 12:30:25 PM PST 24
Finished Feb 18 12:34:49 PM PST 24
Peak memory 182152 kb
Host smart-704b47d4-b7b9-4356-ae57-057f1f0fc501
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110674360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.rv_timer_cfg_update_on_fly.110674360
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1667518555
Short name T396
Test name
Test status
Simulation time 64312782042 ps
CPU time 94.26 seconds
Started Feb 18 12:30:46 PM PST 24
Finished Feb 18 12:32:24 PM PST 24
Peak memory 182344 kb
Host smart-0b21e8a5-ecdf-46dc-b04e-69e8a7be415a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667518555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1667518555
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.628245099
Short name T368
Test name
Test status
Simulation time 48897122556 ps
CPU time 96.67 seconds
Started Feb 18 12:30:43 PM PST 24
Finished Feb 18 12:32:23 PM PST 24
Peak memory 190528 kb
Host smart-4102a3bf-5ad4-456c-bc4b-b7504f91a20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628245099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.628245099
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.1861282535
Short name T465
Test name
Test status
Simulation time 234837909673 ps
CPU time 282.35 seconds
Started Feb 18 12:30:38 PM PST 24
Finished Feb 18 12:35:26 PM PST 24
Peak memory 205248 kb
Host smart-f5ccd37d-8ce6-4d8b-9b7e-65261d0397f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861282535 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.1861282535
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/132.rv_timer_random.1039225589
Short name T222
Test name
Test status
Simulation time 65602418471 ps
CPU time 37.82 seconds
Started Feb 18 12:31:13 PM PST 24
Finished Feb 18 12:31:53 PM PST 24
Peak memory 190512 kb
Host smart-72402b3c-1249-4a85-b48a-481e5b0d051d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039225589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1039225589
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3564968066
Short name T181
Test name
Test status
Simulation time 134940560274 ps
CPU time 1131.56 seconds
Started Feb 18 12:31:10 PM PST 24
Finished Feb 18 12:50:03 PM PST 24
Peak memory 190476 kb
Host smart-a5412aca-44ec-4efd-aaae-ffc2167d928d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564968066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3564968066
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.2092256547
Short name T238
Test name
Test status
Simulation time 121640237234 ps
CPU time 628.65 seconds
Started Feb 18 12:31:16 PM PST 24
Finished Feb 18 12:41:49 PM PST 24
Peak memory 190396 kb
Host smart-761649de-48dd-46d4-8e91-e7d4811b5709
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092256547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2092256547
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.990593948
Short name T336
Test name
Test status
Simulation time 1250674423240 ps
CPU time 674.81 seconds
Started Feb 18 12:31:16 PM PST 24
Finished Feb 18 12:42:35 PM PST 24
Peak memory 190524 kb
Host smart-176a0fd2-48c6-47c3-a64e-60e656867916
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990593948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.990593948
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.3006256681
Short name T89
Test name
Test status
Simulation time 35010586222 ps
CPU time 17.6 seconds
Started Feb 18 12:31:15 PM PST 24
Finished Feb 18 12:31:36 PM PST 24
Peak memory 182348 kb
Host smart-1597efdc-fd06-4f98-89dc-c77c755625fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006256681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3006256681
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.659327588
Short name T117
Test name
Test status
Simulation time 194202390289 ps
CPU time 1883.78 seconds
Started Feb 18 12:31:22 PM PST 24
Finished Feb 18 01:02:49 PM PST 24
Peak memory 190592 kb
Host smart-7236a1e3-02e4-4e02-9afd-44fb5416bda6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659327588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.659327588
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2855303365
Short name T276
Test name
Test status
Simulation time 316780455040 ps
CPU time 176.36 seconds
Started Feb 18 12:30:23 PM PST 24
Finished Feb 18 12:33:27 PM PST 24
Peak memory 182316 kb
Host smart-15096b14-f2ce-4e0d-9634-0c4d8d5462d3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855303365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2855303365
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.1896271200
Short name T418
Test name
Test status
Simulation time 636399063792 ps
CPU time 263.37 seconds
Started Feb 18 12:30:22 PM PST 24
Finished Feb 18 12:35:00 PM PST 24
Peak memory 182304 kb
Host smart-8eaa0d4c-0487-4f53-a31c-c2a60e779331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896271200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.1896271200
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.1301317848
Short name T281
Test name
Test status
Simulation time 28591394672 ps
CPU time 104.16 seconds
Started Feb 18 12:30:31 PM PST 24
Finished Feb 18 12:32:24 PM PST 24
Peak memory 192568 kb
Host smart-9fdc9547-7a48-4ebb-9a3e-41143de2f152
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301317848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1301317848
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.2943068337
Short name T318
Test name
Test status
Simulation time 261807786614 ps
CPU time 2245.05 seconds
Started Feb 18 12:30:30 PM PST 24
Finished Feb 18 01:08:05 PM PST 24
Peak memory 193952 kb
Host smart-b8eab252-55cc-49e4-8854-b19e01b3c4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943068337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2943068337
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.4092387031
Short name T385
Test name
Test status
Simulation time 863845437155 ps
CPU time 334.16 seconds
Started Feb 18 12:30:55 PM PST 24
Finished Feb 18 12:36:32 PM PST 24
Peak memory 190496 kb
Host smart-67e5f3e5-4459-4073-adf6-15ebc8318f47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092387031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.4092387031
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.4069572244
Short name T415
Test name
Test status
Simulation time 67074229754 ps
CPU time 176.1 seconds
Started Feb 18 12:30:25 PM PST 24
Finished Feb 18 12:33:32 PM PST 24
Peak memory 205212 kb
Host smart-03c3bc6e-2858-41c2-8b25-71bd0e064b70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069572244 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.4069572244
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.1274371728
Short name T227
Test name
Test status
Simulation time 303507512748 ps
CPU time 1191.28 seconds
Started Feb 18 12:31:12 PM PST 24
Finished Feb 18 12:51:05 PM PST 24
Peak memory 190480 kb
Host smart-0c814b92-ce10-4541-852e-5b02f05d21f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274371728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1274371728
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.3563336734
Short name T360
Test name
Test status
Simulation time 126560582583 ps
CPU time 422.83 seconds
Started Feb 18 12:31:19 PM PST 24
Finished Feb 18 12:38:25 PM PST 24
Peak memory 190552 kb
Host smart-f4a11506-078d-4f9e-9295-c36eaea5e3a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563336734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3563336734
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.3568151718
Short name T92
Test name
Test status
Simulation time 133482628375 ps
CPU time 60.93 seconds
Started Feb 18 12:31:17 PM PST 24
Finished Feb 18 12:32:22 PM PST 24
Peak memory 182300 kb
Host smart-c60abc36-8311-4a08-8537-9ab82d2c638b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568151718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3568151718
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3197548430
Short name T153
Test name
Test status
Simulation time 293319014673 ps
CPU time 247.07 seconds
Started Feb 18 12:31:09 PM PST 24
Finished Feb 18 12:35:17 PM PST 24
Peak memory 190508 kb
Host smart-72cc6f82-f81f-43a2-994f-fbe215169f88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197548430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3197548430
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.232639216
Short name T319
Test name
Test status
Simulation time 54050052416 ps
CPU time 586.83 seconds
Started Feb 18 12:31:14 PM PST 24
Finished Feb 18 12:41:05 PM PST 24
Peak memory 190536 kb
Host smart-6ac78f55-fc07-4ce4-a87f-9dc330c4943a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232639216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.232639216
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1933329804
Short name T460
Test name
Test status
Simulation time 529823829533 ps
CPU time 260.15 seconds
Started Feb 18 12:31:22 PM PST 24
Finished Feb 18 12:35:44 PM PST 24
Peak memory 190700 kb
Host smart-85e9a0f5-7544-44e7-8376-71d8d725e851
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933329804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1933329804
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3045857075
Short name T94
Test name
Test status
Simulation time 315557016057 ps
CPU time 555.41 seconds
Started Feb 18 12:31:11 PM PST 24
Finished Feb 18 12:40:29 PM PST 24
Peak memory 190552 kb
Host smart-6657c172-701f-4351-b6cf-63e77e141fd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045857075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3045857075
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3627775630
Short name T363
Test name
Test status
Simulation time 107179605792 ps
CPU time 73.94 seconds
Started Feb 18 12:31:20 PM PST 24
Finished Feb 18 12:32:37 PM PST 24
Peak memory 182308 kb
Host smart-3966a1d8-eae3-4e9d-abf0-1c962de74bd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627775630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3627775630
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2817767324
Short name T417
Test name
Test status
Simulation time 186974133631 ps
CPU time 284.79 seconds
Started Feb 18 12:30:41 PM PST 24
Finished Feb 18 12:35:30 PM PST 24
Peak memory 182348 kb
Host smart-cef10eed-30b3-4e25-be2c-83e0fa9eec5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817767324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2817767324
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.513939377
Short name T274
Test name
Test status
Simulation time 39915041309 ps
CPU time 44.09 seconds
Started Feb 18 12:30:38 PM PST 24
Finished Feb 18 12:31:27 PM PST 24
Peak memory 190516 kb
Host smart-c62afebe-e286-4111-9e8c-015f613b3ca9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513939377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.513939377
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.516018801
Short name T408
Test name
Test status
Simulation time 57967663556 ps
CPU time 90.22 seconds
Started Feb 18 12:30:31 PM PST 24
Finished Feb 18 12:32:10 PM PST 24
Peak memory 182328 kb
Host smart-6ed2b907-99e6-4671-a7a7-69601e852ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516018801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.516018801
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2953265689
Short name T25
Test name
Test status
Simulation time 704595734686 ps
CPU time 340.28 seconds
Started Feb 18 12:30:25 PM PST 24
Finished Feb 18 12:36:15 PM PST 24
Peak memory 190500 kb
Host smart-8fe788fb-aa5c-43de-8fc8-f93a38504a03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953265689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2953265689
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/151.rv_timer_random.2096197681
Short name T303
Test name
Test status
Simulation time 345902623859 ps
CPU time 275.4 seconds
Started Feb 18 12:31:32 PM PST 24
Finished Feb 18 12:36:14 PM PST 24
Peak memory 190492 kb
Host smart-f8f44783-ddd3-4938-adfc-38e3ae7ceb9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096197681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2096197681
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.2758623881
Short name T67
Test name
Test status
Simulation time 288229941770 ps
CPU time 709.78 seconds
Started Feb 18 12:31:17 PM PST 24
Finished Feb 18 12:43:10 PM PST 24
Peak memory 190656 kb
Host smart-2ee368fd-a034-48bb-a349-489246ad7788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758623881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2758623881
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.675738910
Short name T122
Test name
Test status
Simulation time 152535210459 ps
CPU time 229.08 seconds
Started Feb 18 12:31:34 PM PST 24
Finished Feb 18 12:35:29 PM PST 24
Peak memory 193760 kb
Host smart-fe530f6a-8b74-48d9-b0d9-cc16c9075a29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675738910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.675738910
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2311195176
Short name T323
Test name
Test status
Simulation time 117868800503 ps
CPU time 62.78 seconds
Started Feb 18 12:31:22 PM PST 24
Finished Feb 18 12:32:27 PM PST 24
Peak memory 182420 kb
Host smart-b7f74aa5-d5ff-4324-8974-9acb8a3eab04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311195176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2311195176
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.409166285
Short name T309
Test name
Test status
Simulation time 175677091433 ps
CPU time 202 seconds
Started Feb 18 12:31:19 PM PST 24
Finished Feb 18 12:34:45 PM PST 24
Peak memory 190192 kb
Host smart-79f12a08-130b-4d36-8d3b-8109175bb535
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409166285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.409166285
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.28367412
Short name T186
Test name
Test status
Simulation time 63114297280 ps
CPU time 83.1 seconds
Started Feb 18 12:31:19 PM PST 24
Finished Feb 18 12:32:45 PM PST 24
Peak memory 190584 kb
Host smart-d710c200-47c5-4159-9d0a-172446663cf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28367412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.28367412
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.3531999788
Short name T343
Test name
Test status
Simulation time 126668271062 ps
CPU time 117.62 seconds
Started Feb 18 12:31:26 PM PST 24
Finished Feb 18 12:33:26 PM PST 24
Peak memory 190460 kb
Host smart-585fb95e-8b39-4182-b542-b41407e2cae1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531999788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3531999788
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2452038682
Short name T20
Test name
Test status
Simulation time 67443917822 ps
CPU time 27.64 seconds
Started Feb 18 12:31:23 PM PST 24
Finished Feb 18 12:31:53 PM PST 24
Peak memory 182228 kb
Host smart-c74bf0ca-0b3c-405c-8afd-67064032ba7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452038682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2452038682
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1144709229
Short name T180
Test name
Test status
Simulation time 1666867780199 ps
CPU time 985.51 seconds
Started Feb 18 12:30:29 PM PST 24
Finished Feb 18 12:47:05 PM PST 24
Peak memory 182304 kb
Host smart-81c4a91b-77e8-4932-a94b-cd04bedc7731
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144709229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1144709229
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.36765445
Short name T400
Test name
Test status
Simulation time 499714518575 ps
CPU time 127.05 seconds
Started Feb 18 12:30:45 PM PST 24
Finished Feb 18 12:32:55 PM PST 24
Peak memory 182320 kb
Host smart-0a99c30b-0bce-4b9c-ab98-9fa01e40a987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36765445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.36765445
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.910253032
Short name T295
Test name
Test status
Simulation time 261379759538 ps
CPU time 232.21 seconds
Started Feb 18 12:30:41 PM PST 24
Finished Feb 18 12:34:37 PM PST 24
Peak memory 190564 kb
Host smart-c0f38126-a94a-459e-8ef5-e6be7f81a3cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910253032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.910253032
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2283093585
Short name T470
Test name
Test status
Simulation time 162509856 ps
CPU time 0.64 seconds
Started Feb 18 12:30:44 PM PST 24
Finished Feb 18 12:30:48 PM PST 24
Peak memory 182292 kb
Host smart-5b248da3-416d-4aa3-8c00-a412c14a11f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283093585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2283093585
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1289178855
Short name T165
Test name
Test status
Simulation time 483555650251 ps
CPU time 247.19 seconds
Started Feb 18 12:30:22 PM PST 24
Finished Feb 18 12:34:37 PM PST 24
Peak memory 190508 kb
Host smart-830d97ad-00ea-4365-9206-3f1355c51bb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289178855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1289178855
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.1149171456
Short name T50
Test name
Test status
Simulation time 57358603487 ps
CPU time 237.79 seconds
Started Feb 18 12:30:46 PM PST 24
Finished Feb 18 12:34:47 PM PST 24
Peak memory 197200 kb
Host smart-a75e77fe-5062-41fd-9e3f-7e280f2494ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149171456 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.1149171456
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.2897797155
Short name T64
Test name
Test status
Simulation time 107069478246 ps
CPU time 150.63 seconds
Started Feb 18 12:31:22 PM PST 24
Finished Feb 18 12:33:55 PM PST 24
Peak memory 190524 kb
Host smart-3646cd1c-2c76-4994-ac75-6a06022f6949
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897797155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.2897797155
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.620827406
Short name T175
Test name
Test status
Simulation time 647989692258 ps
CPU time 407.17 seconds
Started Feb 18 12:31:17 PM PST 24
Finished Feb 18 12:38:08 PM PST 24
Peak memory 190664 kb
Host smart-09bc2b74-b71a-440e-931a-295006be456d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620827406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.620827406
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2695881580
Short name T146
Test name
Test status
Simulation time 288196391351 ps
CPU time 1282.3 seconds
Started Feb 18 12:31:29 PM PST 24
Finished Feb 18 12:52:55 PM PST 24
Peak memory 190516 kb
Host smart-6c2fefc0-7d95-43c2-ae43-ac53e6c046b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695881580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2695881580
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.560724350
Short name T294
Test name
Test status
Simulation time 135514501984 ps
CPU time 232.5 seconds
Started Feb 18 12:31:16 PM PST 24
Finished Feb 18 12:35:13 PM PST 24
Peak memory 190524 kb
Host smart-65568c69-3ae2-48e0-b445-db3be0703e5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560724350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.560724350
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.3567361844
Short name T246
Test name
Test status
Simulation time 256380257415 ps
CPU time 702.9 seconds
Started Feb 18 12:31:32 PM PST 24
Finished Feb 18 12:43:20 PM PST 24
Peak memory 193696 kb
Host smart-be7f8ba4-5a6f-4608-b896-01aeb0947218
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567361844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3567361844
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3167484578
Short name T320
Test name
Test status
Simulation time 1205977638796 ps
CPU time 943.84 seconds
Started Feb 18 12:30:23 PM PST 24
Finished Feb 18 12:46:16 PM PST 24
Peak memory 182164 kb
Host smart-c3173c42-dec4-4e79-a506-35ee035d59f2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167484578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3167484578
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3222667433
Short name T397
Test name
Test status
Simulation time 166008915940 ps
CPU time 284.31 seconds
Started Feb 18 12:30:30 PM PST 24
Finished Feb 18 12:35:24 PM PST 24
Peak memory 182296 kb
Host smart-c38da54e-446d-4c8c-bdc3-c33e92be5b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222667433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3222667433
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.2417055441
Short name T315
Test name
Test status
Simulation time 165987524989 ps
CPU time 488.62 seconds
Started Feb 18 12:30:44 PM PST 24
Finished Feb 18 12:38:56 PM PST 24
Peak memory 182484 kb
Host smart-11fbb0c4-5b07-4b56-b312-3b3d952cd7e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417055441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2417055441
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.4190283518
Short name T23
Test name
Test status
Simulation time 324195985 ps
CPU time 0.7 seconds
Started Feb 18 12:30:40 PM PST 24
Finished Feb 18 12:30:45 PM PST 24
Peak memory 182168 kb
Host smart-dc94ca08-ff9e-4566-ac8c-31532a5b460d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190283518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.4190283518
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.602679143
Short name T36
Test name
Test status
Simulation time 138059581721 ps
CPU time 360.57 seconds
Started Feb 18 12:30:22 PM PST 24
Finished Feb 18 12:36:31 PM PST 24
Peak memory 205252 kb
Host smart-6e82b351-0aeb-4b84-91c5-c89487320fda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602679143 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.602679143
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.3872771770
Short name T317
Test name
Test status
Simulation time 141654739719 ps
CPU time 99.6 seconds
Started Feb 18 12:31:29 PM PST 24
Finished Feb 18 12:33:13 PM PST 24
Peak memory 182340 kb
Host smart-5e0f85d2-fe0a-48a5-ad2c-4ee36ff343d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872771770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3872771770
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.2065860622
Short name T356
Test name
Test status
Simulation time 67536819384 ps
CPU time 111.28 seconds
Started Feb 18 12:31:24 PM PST 24
Finished Feb 18 12:33:18 PM PST 24
Peak memory 191444 kb
Host smart-4d51ed1f-30b2-4c9c-89ee-437dd94d1e4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065860622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2065860622
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.1802957550
Short name T202
Test name
Test status
Simulation time 179338924516 ps
CPU time 340.48 seconds
Started Feb 18 12:31:33 PM PST 24
Finished Feb 18 12:37:20 PM PST 24
Peak memory 190600 kb
Host smart-174cc699-16f0-4b95-b2ea-71cecbfc34f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802957550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1802957550
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.1398840790
Short name T6
Test name
Test status
Simulation time 29682910365 ps
CPU time 56.39 seconds
Started Feb 18 12:31:23 PM PST 24
Finished Feb 18 12:32:23 PM PST 24
Peak memory 190508 kb
Host smart-9b1265b1-589d-4feb-80b4-e7657587432a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398840790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1398840790
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.615909381
Short name T196
Test name
Test status
Simulation time 21674233827 ps
CPU time 38.86 seconds
Started Feb 18 12:31:27 PM PST 24
Finished Feb 18 12:32:09 PM PST 24
Peak memory 190548 kb
Host smart-5b34d33a-64f8-4d4e-8900-329cabbd4844
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615909381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.615909381
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.861657128
Short name T91
Test name
Test status
Simulation time 65215812696 ps
CPU time 1284.75 seconds
Started Feb 18 12:31:36 PM PST 24
Finished Feb 18 12:53:06 PM PST 24
Peak memory 190520 kb
Host smart-90deb1aa-a541-4d5a-961b-5fdbad56a92c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861657128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.861657128
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3490162565
Short name T211
Test name
Test status
Simulation time 1178073550127 ps
CPU time 452.07 seconds
Started Feb 18 12:30:45 PM PST 24
Finished Feb 18 12:38:20 PM PST 24
Peak memory 182308 kb
Host smart-d3344c2d-6462-4c77-98ad-ac46d1bf8925
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490162565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3490162565
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.2877081590
Short name T393
Test name
Test status
Simulation time 82987681556 ps
CPU time 99.14 seconds
Started Feb 18 12:30:25 PM PST 24
Finished Feb 18 12:32:15 PM PST 24
Peak memory 182368 kb
Host smart-425002de-9dc3-4555-b4ca-7be3453e90a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877081590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2877081590
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.232591027
Short name T205
Test name
Test status
Simulation time 897217291355 ps
CPU time 378.23 seconds
Started Feb 18 12:30:24 PM PST 24
Finished Feb 18 12:36:52 PM PST 24
Peak memory 190572 kb
Host smart-6beb0d70-95de-45ea-b3de-1ae13528d4fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232591027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.232591027
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3584314380
Short name T406
Test name
Test status
Simulation time 18695213967 ps
CPU time 10.14 seconds
Started Feb 18 12:30:34 PM PST 24
Finished Feb 18 12:30:51 PM PST 24
Peak memory 182332 kb
Host smart-cfd9b518-f554-4753-9ad5-5f01b37f4912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584314380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3584314380
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.2477828002
Short name T235
Test name
Test status
Simulation time 405441231318 ps
CPU time 727.41 seconds
Started Feb 18 12:30:42 PM PST 24
Finished Feb 18 12:42:53 PM PST 24
Peak memory 192300 kb
Host smart-525dc317-27c1-47d6-8d18-d56c4d753bc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477828002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.2477828002
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.1450349953
Short name T127
Test name
Test status
Simulation time 64377611359 ps
CPU time 291.69 seconds
Started Feb 18 12:30:24 PM PST 24
Finished Feb 18 12:35:24 PM PST 24
Peak memory 197008 kb
Host smart-b88aa9aa-405c-462b-98fa-1c8b1aab4ce7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450349953 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.1450349953
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.1966766545
Short name T219
Test name
Test status
Simulation time 589412913281 ps
CPU time 303.74 seconds
Started Feb 18 12:31:23 PM PST 24
Finished Feb 18 12:36:29 PM PST 24
Peak memory 190568 kb
Host smart-181d2484-ddf7-448d-b604-babe64952daa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966766545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1966766545
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.104920207
Short name T359
Test name
Test status
Simulation time 480583200295 ps
CPU time 2079.16 seconds
Started Feb 18 12:31:24 PM PST 24
Finished Feb 18 01:06:06 PM PST 24
Peak memory 191624 kb
Host smart-c966d954-25b1-4354-b6cf-7935dc0a566d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104920207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.104920207
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.575831012
Short name T237
Test name
Test status
Simulation time 94427821692 ps
CPU time 601.49 seconds
Started Feb 18 12:31:18 PM PST 24
Finished Feb 18 12:41:24 PM PST 24
Peak memory 190544 kb
Host smart-9dbd37d4-e31e-42c6-b10b-436775c0cf2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575831012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.575831012
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1501242679
Short name T352
Test name
Test status
Simulation time 63958729356 ps
CPU time 103.86 seconds
Started Feb 18 12:31:20 PM PST 24
Finished Feb 18 12:33:07 PM PST 24
Peak memory 193844 kb
Host smart-01c67f1c-c8dd-45c1-896b-b39b856bc8e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501242679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1501242679
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.4122284624
Short name T258
Test name
Test status
Simulation time 405253901 ps
CPU time 1.78 seconds
Started Feb 18 12:31:15 PM PST 24
Finished Feb 18 12:31:20 PM PST 24
Peak memory 182260 kb
Host smart-5732246d-aac1-4df5-9787-03ba209bb8d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122284624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.4122284624
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2269815322
Short name T453
Test name
Test status
Simulation time 1383553216790 ps
CPU time 512.43 seconds
Started Feb 18 12:31:17 PM PST 24
Finished Feb 18 12:39:53 PM PST 24
Peak memory 190552 kb
Host smart-b4473aa0-ae5f-4961-8636-b7cf535350d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269815322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2269815322
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3331582460
Short name T307
Test name
Test status
Simulation time 74603478687 ps
CPU time 51.82 seconds
Started Feb 18 12:31:24 PM PST 24
Finished Feb 18 12:32:18 PM PST 24
Peak memory 182364 kb
Host smart-c9161ef4-f94c-46c4-a8c9-12d936118344
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331582460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3331582460
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2250623847
Short name T124
Test name
Test status
Simulation time 64040025932 ps
CPU time 506.23 seconds
Started Feb 18 12:31:15 PM PST 24
Finished Feb 18 12:39:46 PM PST 24
Peak memory 190492 kb
Host smart-a4c5bcda-af70-4b2b-ab06-2f228f4aa543
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250623847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2250623847
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1330278210
Short name T342
Test name
Test status
Simulation time 167184901910 ps
CPU time 204.45 seconds
Started Feb 18 12:31:37 PM PST 24
Finished Feb 18 12:35:06 PM PST 24
Peak memory 190508 kb
Host smart-06defb60-3a18-4bce-9d11-0a8a82ddd28b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330278210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1330278210
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.671345092
Short name T192
Test name
Test status
Simulation time 139626039204 ps
CPU time 143.49 seconds
Started Feb 18 12:30:26 PM PST 24
Finished Feb 18 12:33:00 PM PST 24
Peak memory 182316 kb
Host smart-b98137ce-7e2b-44a4-b246-b57a80eb3142
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671345092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.671345092
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3482563565
Short name T387
Test name
Test status
Simulation time 106323882335 ps
CPU time 163.91 seconds
Started Feb 18 12:30:43 PM PST 24
Finished Feb 18 12:33:31 PM PST 24
Peak memory 182308 kb
Host smart-55af8e7c-f8f2-4643-9eba-feb9afa5965c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482563565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3482563565
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.1322405402
Short name T402
Test name
Test status
Simulation time 31648689645 ps
CPU time 59.74 seconds
Started Feb 18 12:30:24 PM PST 24
Finished Feb 18 12:31:33 PM PST 24
Peak memory 182356 kb
Host smart-fd3b4c7e-2e0c-40f9-a192-aa34b319828a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322405402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1322405402
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.2505892042
Short name T244
Test name
Test status
Simulation time 658750506962 ps
CPU time 1535.59 seconds
Started Feb 18 12:30:39 PM PST 24
Finished Feb 18 12:56:19 PM PST 24
Peak memory 190484 kb
Host smart-762c5edf-2b33-4ec5-b2a9-1e9ab4113ccb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505892042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.2505892042
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.3419206322
Short name T73
Test name
Test status
Simulation time 47756198372 ps
CPU time 589.77 seconds
Started Feb 18 12:30:25 PM PST 24
Finished Feb 18 12:40:26 PM PST 24
Peak memory 205068 kb
Host smart-98eb90b0-31ac-467b-9f52-e3ee1bf8f46e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419206322 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.3419206322
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.3711325668
Short name T162
Test name
Test status
Simulation time 170364224646 ps
CPU time 160.52 seconds
Started Feb 18 12:31:22 PM PST 24
Finished Feb 18 12:34:05 PM PST 24
Peak memory 190100 kb
Host smart-b8bf8547-2fb7-4fbd-a541-8e741e288e11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711325668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3711325668
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.159873557
Short name T270
Test name
Test status
Simulation time 1214242848109 ps
CPU time 286.43 seconds
Started Feb 18 12:31:27 PM PST 24
Finished Feb 18 12:36:18 PM PST 24
Peak memory 190580 kb
Host smart-d2c95be9-e18b-4071-bf52-fd3a7b50eedd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159873557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.159873557
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.3196860064
Short name T280
Test name
Test status
Simulation time 2499317003597 ps
CPU time 1351.72 seconds
Started Feb 18 12:31:31 PM PST 24
Finished Feb 18 12:54:08 PM PST 24
Peak memory 190504 kb
Host smart-e93f4272-8045-4174-a75f-c219dfa2670f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196860064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3196860064
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3296232183
Short name T427
Test name
Test status
Simulation time 99353262628 ps
CPU time 113.34 seconds
Started Feb 18 12:31:37 PM PST 24
Finished Feb 18 12:33:35 PM PST 24
Peak memory 192772 kb
Host smart-9eef1594-bdde-4f15-b74b-a006632f44d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296232183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3296232183
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.815738137
Short name T452
Test name
Test status
Simulation time 16128547398 ps
CPU time 42.76 seconds
Started Feb 18 12:31:23 PM PST 24
Finished Feb 18 12:32:09 PM PST 24
Peak memory 182380 kb
Host smart-ffd7c598-19aa-4d8a-a5bc-dbb804386fcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815738137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.815738137
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3157914496
Short name T139
Test name
Test status
Simulation time 71790829469 ps
CPU time 122.57 seconds
Started Feb 18 12:31:19 PM PST 24
Finished Feb 18 12:33:25 PM PST 24
Peak memory 190348 kb
Host smart-e7764332-d68d-4f8e-b2ca-01c384a2f761
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157914496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3157914496
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1347527435
Short name T251
Test name
Test status
Simulation time 50401528206 ps
CPU time 323.13 seconds
Started Feb 18 12:31:28 PM PST 24
Finished Feb 18 12:36:55 PM PST 24
Peak memory 190536 kb
Host smart-510bd7ef-827e-4144-a0fa-93e237d8daec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347527435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1347527435
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.2524973063
Short name T333
Test name
Test status
Simulation time 60806470181 ps
CPU time 284.67 seconds
Started Feb 18 12:31:17 PM PST 24
Finished Feb 18 12:36:05 PM PST 24
Peak memory 182356 kb
Host smart-6086b6f8-05f9-409e-9f85-8ae14f481598
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524973063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2524973063
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1843120167
Short name T435
Test name
Test status
Simulation time 377861135717 ps
CPU time 146.13 seconds
Started Feb 18 12:30:25 PM PST 24
Finished Feb 18 12:33:01 PM PST 24
Peak memory 182328 kb
Host smart-416dc467-3bc7-451c-a3b7-b03e0ce28986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843120167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1843120167
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.4290258562
Short name T299
Test name
Test status
Simulation time 306917319124 ps
CPU time 1675.98 seconds
Started Feb 18 12:30:38 PM PST 24
Finished Feb 18 12:58:39 PM PST 24
Peak memory 190552 kb
Host smart-2b67cd62-09c9-4c88-9c19-012bfe56fdb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290258562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.4290258562
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.2039158718
Short name T243
Test name
Test status
Simulation time 39992036337 ps
CPU time 15.8 seconds
Started Feb 18 12:30:28 PM PST 24
Finished Feb 18 12:30:54 PM PST 24
Peak memory 182296 kb
Host smart-0cac58b7-a20c-4800-ad4f-5fb477e90b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039158718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2039158718
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.2915055722
Short name T16
Test name
Test status
Simulation time 34559565 ps
CPU time 0.75 seconds
Started Feb 18 12:30:38 PM PST 24
Finished Feb 18 12:30:44 PM PST 24
Peak memory 212596 kb
Host smart-5ff27155-fd72-4c20-baa2-66596463537d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915055722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.2915055722
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.108836788
Short name T35
Test name
Test status
Simulation time 108284424728 ps
CPU time 481.78 seconds
Started Feb 18 12:30:29 PM PST 24
Finished Feb 18 12:38:41 PM PST 24
Peak memory 205212 kb
Host smart-d794125c-6dd3-4de0-8157-333c8f4e3301
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108836788 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.108836788
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.109659485
Short name T54
Test name
Test status
Simulation time 523771846566 ps
CPU time 292.48 seconds
Started Feb 18 12:30:48 PM PST 24
Finished Feb 18 12:35:43 PM PST 24
Peak memory 182316 kb
Host smart-6c6d71bd-d9a5-4790-849e-4ae59f45a96f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109659485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.rv_timer_cfg_update_on_fly.109659485
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.3799676705
Short name T430
Test name
Test status
Simulation time 197928673478 ps
CPU time 73.03 seconds
Started Feb 18 12:30:32 PM PST 24
Finished Feb 18 12:31:53 PM PST 24
Peak memory 182364 kb
Host smart-ce08e3cf-ca24-45bc-b558-b651c54c2370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799676705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3799676705
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.2676386018
Short name T381
Test name
Test status
Simulation time 109542177 ps
CPU time 0.77 seconds
Started Feb 18 12:30:30 PM PST 24
Finished Feb 18 12:30:40 PM PST 24
Peak memory 182176 kb
Host smart-3448358a-647d-48cf-9842-8a3d3cd46409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676386018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2676386018
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2172861290
Short name T375
Test name
Test status
Simulation time 200505547383 ps
CPU time 295.48 seconds
Started Feb 18 12:30:35 PM PST 24
Finished Feb 18 12:35:37 PM PST 24
Peak memory 182292 kb
Host smart-65046bd0-5275-4ed6-8660-02a551a11c9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172861290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2172861290
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3572127053
Short name T100
Test name
Test status
Simulation time 81206380765 ps
CPU time 152.02 seconds
Started Feb 18 12:30:23 PM PST 24
Finished Feb 18 12:33:04 PM PST 24
Peak memory 182280 kb
Host smart-df3cb32c-ed1c-4c34-97b4-073f2b9bb29f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572127053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.3572127053
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.2113167121
Short name T372
Test name
Test status
Simulation time 141966375822 ps
CPU time 46.15 seconds
Started Feb 18 12:30:43 PM PST 24
Finished Feb 18 12:31:33 PM PST 24
Peak memory 182352 kb
Host smart-dc2adcec-72e2-42af-a8eb-57b95d8f99d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113167121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2113167121
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.2567037827
Short name T45
Test name
Test status
Simulation time 89012488517 ps
CPU time 341.73 seconds
Started Feb 18 12:30:44 PM PST 24
Finished Feb 18 12:36:29 PM PST 24
Peak memory 182296 kb
Host smart-74cf7f40-5461-45ba-b4ac-74be2ac0a0b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567037827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2567037827
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.794869297
Short name T344
Test name
Test status
Simulation time 34119169658 ps
CPU time 76.01 seconds
Started Feb 18 12:30:42 PM PST 24
Finished Feb 18 12:32:02 PM PST 24
Peak memory 182272 kb
Host smart-c75b927b-8a82-45d5-8b31-bc353d48a8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794869297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.794869297
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1257978235
Short name T19
Test name
Test status
Simulation time 106481515138 ps
CPU time 49.37 seconds
Started Feb 18 12:30:25 PM PST 24
Finished Feb 18 12:31:25 PM PST 24
Peak memory 193768 kb
Host smart-0b069000-c1f9-459d-bb74-1cc8f2308221
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257978235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1257978235
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.4004256510
Short name T125
Test name
Test status
Simulation time 92781667973 ps
CPU time 339.93 seconds
Started Feb 18 12:30:54 PM PST 24
Finished Feb 18 12:36:36 PM PST 24
Peak memory 197020 kb
Host smart-d7583ec2-409f-4945-9df9-ac61682aa257
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004256510 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.4004256510
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.2044147319
Short name T284
Test name
Test status
Simulation time 154742933722 ps
CPU time 288.34 seconds
Started Feb 18 12:30:44 PM PST 24
Finished Feb 18 12:35:35 PM PST 24
Peak memory 182380 kb
Host smart-dd432a25-ef37-46b0-9195-baa753019fe5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044147319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.2044147319
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.232572476
Short name T407
Test name
Test status
Simulation time 570048000417 ps
CPU time 133.09 seconds
Started Feb 18 12:30:45 PM PST 24
Finished Feb 18 12:33:02 PM PST 24
Peak memory 182336 kb
Host smart-ce5744fd-92d1-4df9-ad23-2059f42157c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232572476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.232572476
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.603482674
Short name T134
Test name
Test status
Simulation time 223586319496 ps
CPU time 93.69 seconds
Started Feb 18 12:30:21 PM PST 24
Finished Feb 18 12:32:01 PM PST 24
Peak memory 190472 kb
Host smart-bf5868e9-7e83-49e4-843a-da7128e6831b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603482674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.603482674
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3964707289
Short name T220
Test name
Test status
Simulation time 612414143889 ps
CPU time 200.48 seconds
Started Feb 18 12:30:26 PM PST 24
Finished Feb 18 12:33:57 PM PST 24
Peak memory 190564 kb
Host smart-c622c393-000a-4c7b-8082-4a22917adb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964707289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3964707289
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.2660066316
Short name T128
Test name
Test status
Simulation time 361790883268 ps
CPU time 579.7 seconds
Started Feb 18 12:30:40 PM PST 24
Finished Feb 18 12:40:24 PM PST 24
Peak memory 208840 kb
Host smart-d1d47840-23d7-4db9-b6a7-1dc037d625be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660066316 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.2660066316
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.921594942
Short name T291
Test name
Test status
Simulation time 164376016509 ps
CPU time 249.46 seconds
Started Feb 18 12:30:52 PM PST 24
Finished Feb 18 12:35:04 PM PST 24
Peak memory 182256 kb
Host smart-ae75f2c7-f76e-4688-9a6e-ed0ceffbfe62
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921594942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.921594942
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.3229286431
Short name T428
Test name
Test status
Simulation time 34761751980 ps
CPU time 28.55 seconds
Started Feb 18 12:30:35 PM PST 24
Finished Feb 18 12:31:10 PM PST 24
Peak memory 182308 kb
Host smart-a6239c57-3b61-476e-82c3-54add2ddc907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229286431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3229286431
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.440107753
Short name T288
Test name
Test status
Simulation time 381057495657 ps
CPU time 211.48 seconds
Started Feb 18 12:30:44 PM PST 24
Finished Feb 18 12:34:19 PM PST 24
Peak memory 190512 kb
Host smart-12eb0d1f-2873-4005-855b-eb5e7fcebd76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440107753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.440107753
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.659072308
Short name T138
Test name
Test status
Simulation time 80748198208 ps
CPU time 224.64 seconds
Started Feb 18 12:30:54 PM PST 24
Finished Feb 18 12:34:41 PM PST 24
Peak memory 190528 kb
Host smart-f3e3820c-e3a5-4daa-a7f7-916d85776e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659072308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.659072308
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2513266420
Short name T272
Test name
Test status
Simulation time 361828808181 ps
CPU time 839.37 seconds
Started Feb 18 12:30:43 PM PST 24
Finished Feb 18 12:44:46 PM PST 24
Peak memory 194532 kb
Host smart-c321bc8d-c484-4709-8f92-8f32d63da29f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513266420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2513266420
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2744940346
Short name T105
Test name
Test status
Simulation time 283620082020 ps
CPU time 444.48 seconds
Started Feb 18 12:30:19 PM PST 24
Finished Feb 18 12:37:50 PM PST 24
Peak memory 182260 kb
Host smart-5702e5da-33d0-45e8-bdb6-07d180cfb677
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744940346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2744940346
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.673329575
Short name T119
Test name
Test status
Simulation time 113850565888 ps
CPU time 96.57 seconds
Started Feb 18 12:30:54 PM PST 24
Finished Feb 18 12:32:33 PM PST 24
Peak memory 182300 kb
Host smart-b38d7aee-0124-460f-9f7f-4d754f774ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673329575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.673329575
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.4062972484
Short name T467
Test name
Test status
Simulation time 23241226176 ps
CPU time 20.07 seconds
Started Feb 18 12:30:56 PM PST 24
Finished Feb 18 12:31:18 PM PST 24
Peak memory 182372 kb
Host smart-a850a225-22aa-4963-b45c-a4099fe415b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062972484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.4062972484
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.2873676634
Short name T195
Test name
Test status
Simulation time 1069336041950 ps
CPU time 971.02 seconds
Started Feb 18 12:30:46 PM PST 24
Finished Feb 18 12:47:00 PM PST 24
Peak memory 193556 kb
Host smart-b98c9561-77fd-4568-a0f4-18405b87e2e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873676634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.2873676634
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.273351614
Short name T160
Test name
Test status
Simulation time 42318547188 ps
CPU time 79.78 seconds
Started Feb 18 12:30:39 PM PST 24
Finished Feb 18 12:32:03 PM PST 24
Peak memory 182264 kb
Host smart-aee84d0d-0ada-477c-a3ce-a06449a07322
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273351614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.273351614
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.1515557195
Short name T392
Test name
Test status
Simulation time 28295085694 ps
CPU time 42.17 seconds
Started Feb 18 12:30:45 PM PST 24
Finished Feb 18 12:31:31 PM PST 24
Peak memory 182336 kb
Host smart-0c1b7a54-15a1-4a40-a0c4-efce9e9464c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515557195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1515557195
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.2706578750
Short name T469
Test name
Test status
Simulation time 159235814127 ps
CPU time 306.92 seconds
Started Feb 18 12:30:46 PM PST 24
Finished Feb 18 12:35:56 PM PST 24
Peak memory 190560 kb
Host smart-a295c505-db06-402c-aef5-c36261a8ec57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706578750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2706578750
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.2089467526
Short name T362
Test name
Test status
Simulation time 206193349832 ps
CPU time 1004.84 seconds
Started Feb 18 12:30:49 PM PST 24
Finished Feb 18 12:47:36 PM PST 24
Peak memory 193452 kb
Host smart-4aca2031-4e86-4543-bab6-9f596717e1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089467526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2089467526
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.344896423
Short name T388
Test name
Test status
Simulation time 40691713357 ps
CPU time 88.81 seconds
Started Feb 18 12:30:49 PM PST 24
Finished Feb 18 12:32:19 PM PST 24
Peak memory 196688 kb
Host smart-dfba641a-858d-4104-8714-ddc3620b52c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344896423 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.344896423
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3028350999
Short name T308
Test name
Test status
Simulation time 116385886478 ps
CPU time 194.85 seconds
Started Feb 18 12:30:46 PM PST 24
Finished Feb 18 12:34:04 PM PST 24
Peak memory 182344 kb
Host smart-11d90bf0-055c-4583-b16c-3f576d44e9f7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028350999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3028350999
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.264422771
Short name T384
Test name
Test status
Simulation time 261075029648 ps
CPU time 210.59 seconds
Started Feb 18 12:30:45 PM PST 24
Finished Feb 18 12:34:19 PM PST 24
Peak memory 182412 kb
Host smart-8968b33d-8f59-473f-8b1f-2882290744a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264422771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.264422771
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.4259417862
Short name T413
Test name
Test status
Simulation time 39123654422 ps
CPU time 101.59 seconds
Started Feb 18 12:30:47 PM PST 24
Finished Feb 18 12:32:31 PM PST 24
Peak memory 182328 kb
Host smart-57dd3921-ed93-47d0-a5a4-ece509782dd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259417862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.4259417862
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.4293019053
Short name T4
Test name
Test status
Simulation time 53519689882 ps
CPU time 53.99 seconds
Started Feb 18 12:31:37 PM PST 24
Finished Feb 18 12:32:36 PM PST 24
Peak memory 189808 kb
Host smart-0f88db66-9fed-4cbb-a9db-46afef2d4ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293019053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.4293019053
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.1750052037
Short name T33
Test name
Test status
Simulation time 61199258493 ps
CPU time 433.14 seconds
Started Feb 18 12:30:49 PM PST 24
Finished Feb 18 12:38:06 PM PST 24
Peak memory 205844 kb
Host smart-8ea41801-cce4-4cdc-9736-0b6faa626a25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750052037 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.1750052037
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3183242315
Short name T289
Test name
Test status
Simulation time 96887816563 ps
CPU time 76.48 seconds
Started Feb 18 12:30:45 PM PST 24
Finished Feb 18 12:32:04 PM PST 24
Peak memory 182420 kb
Host smart-7aafbfb3-28a2-43ed-82c7-c6cf87b2c963
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183242315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3183242315
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2771454371
Short name T414
Test name
Test status
Simulation time 40767166101 ps
CPU time 65.26 seconds
Started Feb 18 12:30:48 PM PST 24
Finished Feb 18 12:31:55 PM PST 24
Peak memory 182300 kb
Host smart-2b287c41-e000-4010-89a2-cbdbbc07181d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771454371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2771454371
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.3199089322
Short name T468
Test name
Test status
Simulation time 159753647003 ps
CPU time 86.62 seconds
Started Feb 18 12:30:53 PM PST 24
Finished Feb 18 12:32:22 PM PST 24
Peak memory 182272 kb
Host smart-3521a583-e988-49b7-a712-c8490b8c94c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199089322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3199089322
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.3556168554
Short name T463
Test name
Test status
Simulation time 18685229668 ps
CPU time 30.01 seconds
Started Feb 18 12:30:44 PM PST 24
Finished Feb 18 12:31:18 PM PST 24
Peak memory 182240 kb
Host smart-871d0881-61a2-49be-89e4-ec7491c35b98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556168554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3556168554
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.4135277607
Short name T259
Test name
Test status
Simulation time 12666335738 ps
CPU time 75.34 seconds
Started Feb 18 12:30:47 PM PST 24
Finished Feb 18 12:32:05 PM PST 24
Peak memory 182312 kb
Host smart-4cb5d8fc-114b-4eaf-b51c-48f647c6e730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135277607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.4135277607
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.253579897
Short name T11
Test name
Test status
Simulation time 152600207245 ps
CPU time 445.26 seconds
Started Feb 18 12:30:46 PM PST 24
Finished Feb 18 12:38:14 PM PST 24
Peak memory 197016 kb
Host smart-76b1bbe8-1c75-42f2-94e4-83c0a1899472
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253579897 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.253579897
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1793630009
Short name T26
Test name
Test status
Simulation time 189237396842 ps
CPU time 368.86 seconds
Started Feb 18 12:30:53 PM PST 24
Finished Feb 18 12:37:03 PM PST 24
Peak memory 182284 kb
Host smart-8f07d8f3-b196-4c4b-9ed4-551b360d8611
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793630009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1793630009
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.508793515
Short name T118
Test name
Test status
Simulation time 65879537503 ps
CPU time 92.23 seconds
Started Feb 18 12:30:56 PM PST 24
Finished Feb 18 12:32:30 PM PST 24
Peak memory 182304 kb
Host smart-6b8877ef-d840-437a-9c52-3ebe8b0b9651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508793515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.508793515
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.3559925997
Short name T446
Test name
Test status
Simulation time 152118181916 ps
CPU time 274.09 seconds
Started Feb 18 12:30:51 PM PST 24
Finished Feb 18 12:35:26 PM PST 24
Peak memory 190572 kb
Host smart-7fde73d0-59e1-413c-aa4b-b0c128a20954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559925997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3559925997
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.109079758
Short name T155
Test name
Test status
Simulation time 241988286439 ps
CPU time 323.95 seconds
Started Feb 18 12:30:41 PM PST 24
Finished Feb 18 12:36:09 PM PST 24
Peak memory 190584 kb
Host smart-b361a173-0db6-4d87-a2c8-d738aeb1827c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109079758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.109079758
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.3703181773
Short name T207
Test name
Test status
Simulation time 2067590220341 ps
CPU time 849.66 seconds
Started Feb 18 12:30:55 PM PST 24
Finished Feb 18 12:45:11 PM PST 24
Peak memory 190396 kb
Host smart-f0c332bd-1f58-4715-8464-95294650d385
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703181773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.3703181773
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.147199960
Short name T52
Test name
Test status
Simulation time 89155288272 ps
CPU time 653 seconds
Started Feb 18 12:30:46 PM PST 24
Finished Feb 18 12:41:42 PM PST 24
Peak memory 205848 kb
Host smart-46d94c5a-0e0e-4ed2-93dc-18a05aae6371
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147199960 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.147199960
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3365308288
Short name T242
Test name
Test status
Simulation time 83935608730 ps
CPU time 161.48 seconds
Started Feb 18 12:30:25 PM PST 24
Finished Feb 18 12:33:16 PM PST 24
Peak memory 182308 kb
Host smart-820a473e-ca6b-4eda-b7bb-6ae67f0015d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365308288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.3365308288
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1417229291
Short name T116
Test name
Test status
Simulation time 370650579720 ps
CPU time 172.13 seconds
Started Feb 18 12:30:28 PM PST 24
Finished Feb 18 12:33:30 PM PST 24
Peak memory 182352 kb
Host smart-58057fbe-c85c-41de-b0b2-8bd0a2661bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417229291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1417229291
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3775839600
Short name T297
Test name
Test status
Simulation time 103699407788 ps
CPU time 198.9 seconds
Started Feb 18 12:30:29 PM PST 24
Finished Feb 18 12:33:58 PM PST 24
Peak memory 182268 kb
Host smart-dac2aef7-cd2b-47c2-bf3b-9fb0575bb78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775839600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3775839600
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.346487474
Short name T15
Test name
Test status
Simulation time 162953261 ps
CPU time 0.82 seconds
Started Feb 18 12:30:30 PM PST 24
Finished Feb 18 12:30:40 PM PST 24
Peak memory 212752 kb
Host smart-d5bff30e-ab4a-4ef3-b146-3ea79ea48d44
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346487474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.346487474
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.1995910088
Short name T377
Test name
Test status
Simulation time 29506018 ps
CPU time 0.62 seconds
Started Feb 18 12:30:20 PM PST 24
Finished Feb 18 12:30:35 PM PST 24
Peak memory 182152 kb
Host smart-7bb6245b-85ae-4e92-ba0d-0e376e25fdf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995910088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
1995910088
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.974469380
Short name T48
Test name
Test status
Simulation time 130048194739 ps
CPU time 250.1 seconds
Started Feb 18 12:30:16 PM PST 24
Finished Feb 18 12:34:33 PM PST 24
Peak memory 205224 kb
Host smart-0912e97f-3c8c-4c65-88d7-b73a9c252c3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974469380 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.974469380
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2637059214
Short name T275
Test name
Test status
Simulation time 760963845713 ps
CPU time 1304.45 seconds
Started Feb 18 12:30:51 PM PST 24
Finished Feb 18 12:52:38 PM PST 24
Peak memory 182308 kb
Host smart-96e9357b-614b-4907-9638-6cb14d86d9a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637059214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2637059214
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3587455592
Short name T438
Test name
Test status
Simulation time 88304363598 ps
CPU time 118.69 seconds
Started Feb 18 12:36:19 PM PST 24
Finished Feb 18 12:38:25 PM PST 24
Peak memory 182336 kb
Host smart-fb4f9db4-1e47-4d6c-8fc5-a328ff0fd532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587455592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3587455592
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3605976563
Short name T292
Test name
Test status
Simulation time 143701541890 ps
CPU time 144.11 seconds
Started Feb 18 12:30:49 PM PST 24
Finished Feb 18 12:33:15 PM PST 24
Peak memory 190524 kb
Host smart-1827b23a-d2af-4db9-88cb-74519c418ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605976563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3605976563
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3786341535
Short name T282
Test name
Test status
Simulation time 137368460789 ps
CPU time 243.44 seconds
Started Feb 18 12:30:55 PM PST 24
Finished Feb 18 12:35:01 PM PST 24
Peak memory 182296 kb
Host smart-539c38f1-9a0f-4c52-8c56-78a13c062ac6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786341535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3786341535
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3216629426
Short name T412
Test name
Test status
Simulation time 238840529669 ps
CPU time 105.34 seconds
Started Feb 18 12:30:50 PM PST 24
Finished Feb 18 12:32:37 PM PST 24
Peak memory 182372 kb
Host smart-7f5d3d4b-e996-49b0-a3f2-e3a011e35caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216629426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3216629426
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.3404466363
Short name T405
Test name
Test status
Simulation time 15945068048 ps
CPU time 26.66 seconds
Started Feb 18 12:30:59 PM PST 24
Finished Feb 18 12:31:27 PM PST 24
Peak memory 182380 kb
Host smart-60e27a8a-53ad-46e5-95a2-ac4f59694c16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404466363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3404466363
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.608822195
Short name T454
Test name
Test status
Simulation time 28119524169 ps
CPU time 69.55 seconds
Started Feb 18 12:30:53 PM PST 24
Finished Feb 18 12:32:05 PM PST 24
Peak memory 190556 kb
Host smart-259541bf-f7dd-4c28-9ae0-c120a5ae45d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608822195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.608822195
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2930454752
Short name T459
Test name
Test status
Simulation time 31664345 ps
CPU time 0.54 seconds
Started Feb 18 12:31:18 PM PST 24
Finished Feb 18 12:31:22 PM PST 24
Peak memory 181760 kb
Host smart-7a7bc51a-ff80-45df-a547-59a0c21232b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930454752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2930454752
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.963558342
Short name T166
Test name
Test status
Simulation time 25567669554 ps
CPU time 45.8 seconds
Started Feb 18 12:31:47 PM PST 24
Finished Feb 18 12:32:34 PM PST 24
Peak memory 181948 kb
Host smart-a5bf1154-f54e-4861-ab87-740716c31107
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963558342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.rv_timer_cfg_update_on_fly.963558342
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.193177929
Short name T429
Test name
Test status
Simulation time 296964085387 ps
CPU time 118.42 seconds
Started Feb 18 12:31:48 PM PST 24
Finished Feb 18 12:33:47 PM PST 24
Peak memory 182072 kb
Host smart-08283121-4fe5-48c8-9c74-962b08f2060d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193177929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.193177929
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.3451866296
Short name T421
Test name
Test status
Simulation time 16657317350 ps
CPU time 28.22 seconds
Started Feb 18 12:30:57 PM PST 24
Finished Feb 18 12:31:27 PM PST 24
Peak memory 182372 kb
Host smart-b74d8497-f88c-4cc5-8617-d560db6d20d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451866296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.3451866296
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.2340271894
Short name T142
Test name
Test status
Simulation time 54510549750 ps
CPU time 92.9 seconds
Started Feb 18 12:31:01 PM PST 24
Finished Feb 18 12:32:36 PM PST 24
Peak memory 192684 kb
Host smart-a4b692ba-d52f-4a46-90da-3bf9c3237500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340271894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2340271894
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3659765317
Short name T101
Test name
Test status
Simulation time 158081632797 ps
CPU time 255.21 seconds
Started Feb 18 12:31:46 PM PST 24
Finished Feb 18 12:36:03 PM PST 24
Peak memory 182056 kb
Host smart-911e12bc-4b21-4b35-a053-174e4b42a6af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659765317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3659765317
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.289688721
Short name T364
Test name
Test status
Simulation time 243836495936 ps
CPU time 426.92 seconds
Started Feb 18 12:30:45 PM PST 24
Finished Feb 18 12:37:55 PM PST 24
Peak memory 182276 kb
Host smart-7ca72a68-b5bc-471b-908e-b99d28cfff5a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289688721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.289688721
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.355552272
Short name T65
Test name
Test status
Simulation time 370243394597 ps
CPU time 300.31 seconds
Started Feb 18 12:31:47 PM PST 24
Finished Feb 18 12:36:48 PM PST 24
Peak memory 182064 kb
Host smart-267f3e7f-428e-4f14-8e77-d692c1209d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355552272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.355552272
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.349346554
Short name T194
Test name
Test status
Simulation time 938675144708 ps
CPU time 690.87 seconds
Started Feb 18 12:30:54 PM PST 24
Finished Feb 18 12:42:27 PM PST 24
Peak memory 190544 kb
Host smart-fc9f71ad-4270-49ab-8fa3-43da081b9f87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349346554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.349346554
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.1250568619
Short name T269
Test name
Test status
Simulation time 94128508964 ps
CPU time 95.02 seconds
Started Feb 18 12:30:47 PM PST 24
Finished Feb 18 12:32:25 PM PST 24
Peak memory 182420 kb
Host smart-b36335fd-c733-4eb2-991f-22300d0a786c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250568619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1250568619
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.78707253
Short name T221
Test name
Test status
Simulation time 672411873676 ps
CPU time 547.69 seconds
Started Feb 18 12:30:51 PM PST 24
Finished Feb 18 12:40:00 PM PST 24
Peak memory 190532 kb
Host smart-3eddc508-9d5a-478b-b5d1-5cbe0af848fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78707253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.78707253
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.3113649016
Short name T461
Test name
Test status
Simulation time 11468522440 ps
CPU time 107.68 seconds
Started Feb 18 12:30:43 PM PST 24
Finished Feb 18 12:32:35 PM PST 24
Peak memory 194324 kb
Host smart-27dd7f4f-1a4a-4765-8aae-e1d657d9407b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113649016 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.3113649016
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2369936336
Short name T266
Test name
Test status
Simulation time 1827786983711 ps
CPU time 1601.9 seconds
Started Feb 18 12:30:57 PM PST 24
Finished Feb 18 12:57:42 PM PST 24
Peak memory 182320 kb
Host smart-3554b3ae-ab7b-4233-bcb3-26f5874e114a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369936336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2369936336
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.2331462143
Short name T448
Test name
Test status
Simulation time 39891844701 ps
CPU time 66.03 seconds
Started Feb 18 12:30:47 PM PST 24
Finished Feb 18 12:31:56 PM PST 24
Peak memory 182452 kb
Host smart-7d46f2f0-7551-401d-82d9-0c310ea6ab1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331462143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2331462143
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.174593886
Short name T434
Test name
Test status
Simulation time 43753966554 ps
CPU time 265.31 seconds
Started Feb 18 12:30:56 PM PST 24
Finished Feb 18 12:35:24 PM PST 24
Peak memory 182316 kb
Host smart-14261b2d-6b08-4f13-9fe4-e773e6b139f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174593886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.174593886
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.3482228375
Short name T200
Test name
Test status
Simulation time 52800944684 ps
CPU time 407.64 seconds
Started Feb 18 12:31:47 PM PST 24
Finished Feb 18 12:38:36 PM PST 24
Peak memory 196764 kb
Host smart-5cadc66d-5155-49a9-8122-784d2fe8ec27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482228375 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.3482228375
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2299151367
Short name T102
Test name
Test status
Simulation time 222579807323 ps
CPU time 368.04 seconds
Started Feb 18 12:30:54 PM PST 24
Finished Feb 18 12:37:05 PM PST 24
Peak memory 182320 kb
Host smart-35ab3a49-ac2d-452c-985b-f4065ca9b498
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299151367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2299151367
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.4258274424
Short name T444
Test name
Test status
Simulation time 590125065694 ps
CPU time 186.37 seconds
Started Feb 18 12:31:47 PM PST 24
Finished Feb 18 12:34:55 PM PST 24
Peak memory 182024 kb
Host smart-1be68b01-b088-42e2-b3d7-65c0191d47c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258274424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.4258274424
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.1631296236
Short name T340
Test name
Test status
Simulation time 16537226572 ps
CPU time 23.87 seconds
Started Feb 18 12:31:01 PM PST 24
Finished Feb 18 12:31:27 PM PST 24
Peak memory 182384 kb
Host smart-8ce8db63-b0c6-4b77-ad58-c3536951ffe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631296236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1631296236
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.3540343900
Short name T212
Test name
Test status
Simulation time 483498526745 ps
CPU time 230.46 seconds
Started Feb 18 12:31:47 PM PST 24
Finished Feb 18 12:35:38 PM PST 24
Peak memory 190260 kb
Host smart-a326d495-2056-4c27-ae56-44c8242fd487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540343900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3540343900
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2839123863
Short name T445
Test name
Test status
Simulation time 577796927832 ps
CPU time 312.95 seconds
Started Feb 18 12:31:00 PM PST 24
Finished Feb 18 12:36:14 PM PST 24
Peak memory 193080 kb
Host smart-ae04098c-09c1-4863-bfa4-948077080642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839123863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2839123863
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.3959248709
Short name T183
Test name
Test status
Simulation time 53480561781 ps
CPU time 48.23 seconds
Started Feb 18 12:30:56 PM PST 24
Finished Feb 18 12:31:47 PM PST 24
Peak memory 182300 kb
Host smart-73f4d0e7-ae98-4cf2-9c8a-c86cb2f0acdd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959248709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.3959248709
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3233042111
Short name T56
Test name
Test status
Simulation time 379504956686 ps
CPU time 171.44 seconds
Started Feb 18 12:30:41 PM PST 24
Finished Feb 18 12:33:36 PM PST 24
Peak memory 182308 kb
Host smart-826a3da0-a042-4e4a-89d1-fa9a869a4132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233042111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3233042111
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.3312127929
Short name T69
Test name
Test status
Simulation time 291376386746 ps
CPU time 250.93 seconds
Started Feb 18 12:30:46 PM PST 24
Finished Feb 18 12:35:00 PM PST 24
Peak memory 190560 kb
Host smart-5e8ce4c9-506d-4789-a9a3-55454e4df49f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312127929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3312127929
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3849527364
Short name T286
Test name
Test status
Simulation time 271184589835 ps
CPU time 110.14 seconds
Started Feb 18 12:30:51 PM PST 24
Finished Feb 18 12:32:43 PM PST 24
Peak memory 190564 kb
Host smart-de5dd8de-b60b-497a-a1a5-c9ef4d644f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849527364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3849527364
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.209201849
Short name T379
Test name
Test status
Simulation time 63574208 ps
CPU time 0.57 seconds
Started Feb 18 12:30:57 PM PST 24
Finished Feb 18 12:31:00 PM PST 24
Peak memory 182104 kb
Host smart-1cc86454-e172-4f45-8a11-29fa4087d73b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209201849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.
209201849
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2372138702
Short name T373
Test name
Test status
Simulation time 120425283891 ps
CPU time 140.31 seconds
Started Feb 18 12:30:58 PM PST 24
Finished Feb 18 12:33:20 PM PST 24
Peak memory 182316 kb
Host smart-7fa1ebcc-16c6-4dc2-a8cb-a8ee8189044d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372138702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2372138702
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.2709843919
Short name T332
Test name
Test status
Simulation time 48468390646 ps
CPU time 108.52 seconds
Started Feb 18 12:31:00 PM PST 24
Finished Feb 18 12:32:49 PM PST 24
Peak memory 190524 kb
Host smart-a43eb28b-aeaf-499e-9f0c-148326c0e511
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709843919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2709843919
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.4148281474
Short name T403
Test name
Test status
Simulation time 57376914 ps
CPU time 0.55 seconds
Started Feb 18 12:31:02 PM PST 24
Finished Feb 18 12:31:05 PM PST 24
Peak memory 182104 kb
Host smart-3465efa0-6bc3-481c-a246-b888f3899f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148281474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.4148281474
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2717489893
Short name T135
Test name
Test status
Simulation time 407070170040 ps
CPU time 673.1 seconds
Started Feb 18 12:30:56 PM PST 24
Finished Feb 18 12:42:12 PM PST 24
Peak memory 190504 kb
Host smart-8fe42422-3d14-4413-a774-e796f2bc5461
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717489893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2717489893
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.410781110
Short name T462
Test name
Test status
Simulation time 74837903658 ps
CPU time 724.66 seconds
Started Feb 18 12:30:46 PM PST 24
Finished Feb 18 12:42:53 PM PST 24
Peak memory 206500 kb
Host smart-5995ab68-958f-4216-a034-d9d2e09d4e67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410781110 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.410781110
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.2102834037
Short name T47
Test name
Test status
Simulation time 62433459009 ps
CPU time 100.88 seconds
Started Feb 18 12:30:51 PM PST 24
Finished Feb 18 12:32:33 PM PST 24
Peak memory 182348 kb
Host smart-389af089-4c8a-4859-a594-2a5fb0407860
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102834037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.2102834037
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.1537362855
Short name T424
Test name
Test status
Simulation time 33765500084 ps
CPU time 27.19 seconds
Started Feb 18 12:30:49 PM PST 24
Finished Feb 18 12:31:18 PM PST 24
Peak memory 182356 kb
Host smart-864c397d-9c97-4e96-977f-e1255dff79ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537362855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1537362855
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.3052941414
Short name T72
Test name
Test status
Simulation time 48863416122 ps
CPU time 41.96 seconds
Started Feb 18 12:30:52 PM PST 24
Finished Feb 18 12:31:36 PM PST 24
Peak memory 190568 kb
Host smart-a239d68a-0794-4386-ba0e-59116180e825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052941414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3052941414
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.950506953
Short name T55
Test name
Test status
Simulation time 28032799985 ps
CPU time 130.09 seconds
Started Feb 18 12:31:05 PM PST 24
Finished Feb 18 12:33:16 PM PST 24
Peak memory 190580 kb
Host smart-018aeadc-98ac-4162-b1bc-f5697617df27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950506953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.950506953
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.2300844627
Short name T248
Test name
Test status
Simulation time 5858451013382 ps
CPU time 1272.02 seconds
Started Feb 18 12:30:55 PM PST 24
Finished Feb 18 12:52:10 PM PST 24
Peak memory 195224 kb
Host smart-32116829-484d-4f95-b348-6ed93b725b8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300844627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.2300844627
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.190950762
Short name T37
Test name
Test status
Simulation time 237118438170 ps
CPU time 988.85 seconds
Started Feb 18 12:30:50 PM PST 24
Finished Feb 18 12:47:20 PM PST 24
Peak memory 211088 kb
Host smart-1eb18e64-9775-431d-8400-b01437f195bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190950762 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.190950762
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.1658331367
Short name T168
Test name
Test status
Simulation time 170463572406 ps
CPU time 323.47 seconds
Started Feb 18 12:30:56 PM PST 24
Finished Feb 18 12:36:22 PM PST 24
Peak memory 182324 kb
Host smart-8be88dfa-bac3-4908-ac4a-c355621e01bb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658331367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.1658331367
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.2004022705
Short name T458
Test name
Test status
Simulation time 268242686445 ps
CPU time 106.81 seconds
Started Feb 18 12:30:47 PM PST 24
Finished Feb 18 12:32:36 PM PST 24
Peak memory 182316 kb
Host smart-f7889b08-7ca9-4205-9cfc-9589d1d152d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004022705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.2004022705
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.2908189309
Short name T328
Test name
Test status
Simulation time 59917087352 ps
CPU time 37.91 seconds
Started Feb 18 12:31:12 PM PST 24
Finished Feb 18 12:31:52 PM PST 24
Peak memory 182240 kb
Host smart-f6bd3108-9f6c-4221-8e31-dc30355a68f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908189309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2908189309
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3133723266
Short name T401
Test name
Test status
Simulation time 10020659651 ps
CPU time 17.5 seconds
Started Feb 18 12:30:25 PM PST 24
Finished Feb 18 12:30:53 PM PST 24
Peak memory 182264 kb
Host smart-07e369b6-f70a-453b-9384-a9974fc34cb7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133723266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3133723266
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2186228677
Short name T404
Test name
Test status
Simulation time 342304710876 ps
CPU time 103.23 seconds
Started Feb 18 12:30:29 PM PST 24
Finished Feb 18 12:32:22 PM PST 24
Peak memory 182344 kb
Host smart-2e5dfc84-28ab-4f93-a585-5be7c5b1421f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186228677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2186228677
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.1666042464
Short name T366
Test name
Test status
Simulation time 173958011763 ps
CPU time 72.44 seconds
Started Feb 18 12:30:24 PM PST 24
Finished Feb 18 12:31:46 PM PST 24
Peak memory 190548 kb
Host smart-987fa825-14fc-4ef3-a877-676ab825c915
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666042464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.1666042464
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2860856017
Short name T90
Test name
Test status
Simulation time 18712257886 ps
CPU time 46.29 seconds
Started Feb 18 12:30:28 PM PST 24
Finished Feb 18 12:31:24 PM PST 24
Peak memory 182340 kb
Host smart-14f7aa63-5cb8-4191-9271-e1e31904c97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860856017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2860856017
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2731158081
Short name T17
Test name
Test status
Simulation time 289163151 ps
CPU time 0.99 seconds
Started Feb 18 12:30:30 PM PST 24
Finished Feb 18 12:30:41 PM PST 24
Peak memory 212564 kb
Host smart-1b3d4f76-3082-44d2-a801-1ec5eddf12d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731158081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2731158081
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.394785352
Short name T361
Test name
Test status
Simulation time 60496148089 ps
CPU time 270.18 seconds
Started Feb 18 12:30:22 PM PST 24
Finished Feb 18 12:35:00 PM PST 24
Peak memory 205240 kb
Host smart-adf6135b-b303-4d87-b308-84a22fcaf161
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394785352 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.394785352
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.2498351806
Short name T96
Test name
Test status
Simulation time 789918959147 ps
CPU time 387.2 seconds
Started Feb 18 12:31:48 PM PST 24
Finished Feb 18 12:38:16 PM PST 24
Peak memory 182028 kb
Host smart-928ab877-c3dc-46ea-9e87-ddc04a13db78
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498351806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.2498351806
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2990322289
Short name T7
Test name
Test status
Simulation time 355502889231 ps
CPU time 145.46 seconds
Started Feb 18 12:31:01 PM PST 24
Finished Feb 18 12:33:29 PM PST 24
Peak memory 182360 kb
Host smart-f313cd1e-04ba-4320-bbe3-50a086c10a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990322289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2990322289
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.276292632
Short name T170
Test name
Test status
Simulation time 428710654938 ps
CPU time 331.8 seconds
Started Feb 18 12:31:09 PM PST 24
Finished Feb 18 12:36:42 PM PST 24
Peak memory 190504 kb
Host smart-b273e991-2af8-4034-88d6-5cdee0b61b6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276292632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.276292632
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.2767717667
Short name T411
Test name
Test status
Simulation time 993932087 ps
CPU time 2.11 seconds
Started Feb 18 12:31:00 PM PST 24
Finished Feb 18 12:31:03 PM PST 24
Peak memory 182064 kb
Host smart-3185d3c2-b9b4-417c-8026-f739268ef7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767717667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.2767717667
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2200095467
Short name T409
Test name
Test status
Simulation time 276827855945 ps
CPU time 219.47 seconds
Started Feb 18 12:31:00 PM PST 24
Finished Feb 18 12:34:41 PM PST 24
Peak memory 182320 kb
Host smart-a9eb2703-227c-43a3-9b7b-08a56c8d6fe6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200095467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2200095467
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.1885589316
Short name T431
Test name
Test status
Simulation time 146773909283 ps
CPU time 262.37 seconds
Started Feb 18 12:30:49 PM PST 24
Finished Feb 18 12:35:13 PM PST 24
Peak memory 205288 kb
Host smart-5a075606-7121-4f3f-a75c-9af25f47d4ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885589316 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.1885589316
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3691994549
Short name T433
Test name
Test status
Simulation time 271759337065 ps
CPU time 162.35 seconds
Started Feb 18 12:31:09 PM PST 24
Finished Feb 18 12:33:52 PM PST 24
Peak memory 182320 kb
Host smart-561387d3-0697-4fae-b175-93443cf7475c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691994549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3691994549
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3768080673
Short name T457
Test name
Test status
Simulation time 290804555762 ps
CPU time 225.23 seconds
Started Feb 18 12:31:03 PM PST 24
Finished Feb 18 12:34:50 PM PST 24
Peak memory 182304 kb
Host smart-7f65be6b-1bef-4bf4-8f2b-27a9df7f24fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768080673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3768080673
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1407574561
Short name T172
Test name
Test status
Simulation time 135075059210 ps
CPU time 532.18 seconds
Started Feb 18 12:31:11 PM PST 24
Finished Feb 18 12:40:05 PM PST 24
Peak memory 190516 kb
Host smart-a0de04c9-a086-41d6-8636-c555203fc502
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407574561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1407574561
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2751689736
Short name T302
Test name
Test status
Simulation time 215544083405 ps
CPU time 124.85 seconds
Started Feb 18 12:30:47 PM PST 24
Finished Feb 18 12:32:54 PM PST 24
Peak memory 194076 kb
Host smart-bbc293b2-c44d-4833-bc98-f486a2a997ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751689736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2751689736
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.393313419
Short name T398
Test name
Test status
Simulation time 50987948644 ps
CPU time 832.76 seconds
Started Feb 18 12:30:51 PM PST 24
Finished Feb 18 12:44:46 PM PST 24
Peak memory 197016 kb
Host smart-26ba168c-bee2-4fc8-912d-c25d25fd2369
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393313419 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.393313419
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.818711352
Short name T232
Test name
Test status
Simulation time 203999986288 ps
CPU time 393.46 seconds
Started Feb 18 12:30:52 PM PST 24
Finished Feb 18 12:37:27 PM PST 24
Peak memory 182324 kb
Host smart-c433e615-dbb9-47ac-9e7d-22cd500fe70c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818711352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.818711352
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.618291148
Short name T410
Test name
Test status
Simulation time 58351410695 ps
CPU time 37.25 seconds
Started Feb 18 12:31:00 PM PST 24
Finished Feb 18 12:31:38 PM PST 24
Peak memory 182348 kb
Host smart-4a9a6a62-79fe-429d-a7c0-b8620e6432c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618291148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.618291148
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.962230726
Short name T27
Test name
Test status
Simulation time 769294825784 ps
CPU time 372.68 seconds
Started Feb 18 12:30:44 PM PST 24
Finished Feb 18 12:37:00 PM PST 24
Peak memory 190544 kb
Host smart-4fe148be-feff-4bc3-b930-aee43034b8b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962230726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.962230726
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1841785286
Short name T423
Test name
Test status
Simulation time 8246127877 ps
CPU time 7.41 seconds
Started Feb 18 12:30:48 PM PST 24
Finished Feb 18 12:30:57 PM PST 24
Peak memory 194152 kb
Host smart-f0b99d05-6798-4060-a9f2-7f70b6831dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841785286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1841785286
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.3283097972
Short name T2
Test name
Test status
Simulation time 539128272502 ps
CPU time 547.23 seconds
Started Feb 18 12:30:50 PM PST 24
Finished Feb 18 12:39:59 PM PST 24
Peak memory 194700 kb
Host smart-f83a3c6d-a57f-45c5-a2ce-9f099a61ac66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283097972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.3283097972
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.142368188
Short name T322
Test name
Test status
Simulation time 131146114768 ps
CPU time 101.55 seconds
Started Feb 18 12:31:47 PM PST 24
Finished Feb 18 12:33:30 PM PST 24
Peak memory 182024 kb
Host smart-759cce1d-4410-4541-bd2a-e790fdbe66f7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142368188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.rv_timer_cfg_update_on_fly.142368188
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.1728501532
Short name T432
Test name
Test status
Simulation time 454146647649 ps
CPU time 185.54 seconds
Started Feb 18 12:30:46 PM PST 24
Finished Feb 18 12:33:54 PM PST 24
Peak memory 182116 kb
Host smart-9d564d78-0baf-4dd6-841e-dafbe3e64012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728501532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1728501532
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.6694483
Short name T43
Test name
Test status
Simulation time 473239886566 ps
CPU time 241.14 seconds
Started Feb 18 12:31:01 PM PST 24
Finished Feb 18 12:35:05 PM PST 24
Peak memory 190580 kb
Host smart-84fe3127-eb08-4b8a-95d6-e9b656f1557a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6694483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.6694483
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.1647446225
Short name T204
Test name
Test status
Simulation time 221264722677 ps
CPU time 232.48 seconds
Started Feb 18 12:30:45 PM PST 24
Finished Feb 18 12:34:41 PM PST 24
Peak memory 190492 kb
Host smart-0e475867-6c2b-4d92-867a-e95e61907505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647446225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1647446225
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2304582733
Short name T41
Test name
Test status
Simulation time 788966154766 ps
CPU time 339.51 seconds
Started Feb 18 12:31:09 PM PST 24
Finished Feb 18 12:36:49 PM PST 24
Peak memory 182264 kb
Host smart-06d8641b-1df3-4423-9e87-e5dddc443d87
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304582733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2304582733
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.1660385345
Short name T420
Test name
Test status
Simulation time 154153539547 ps
CPU time 217.89 seconds
Started Feb 18 12:31:12 PM PST 24
Finished Feb 18 12:34:51 PM PST 24
Peak memory 182304 kb
Host smart-da185165-2cc9-4327-a885-6ee12b650d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660385345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1660385345
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.2065285997
Short name T108
Test name
Test status
Simulation time 37468007505 ps
CPU time 57.66 seconds
Started Feb 18 12:31:18 PM PST 24
Finished Feb 18 12:32:20 PM PST 24
Peak memory 190676 kb
Host smart-9d37ac55-2e06-4bd4-9cc5-e508a0925d46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065285997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2065285997
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.310236440
Short name T300
Test name
Test status
Simulation time 51379276763 ps
CPU time 269.14 seconds
Started Feb 18 12:31:00 PM PST 24
Finished Feb 18 12:35:30 PM PST 24
Peak memory 193916 kb
Host smart-b589b143-8a53-44f7-9848-f8381fa63478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310236440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.310236440
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.297310899
Short name T416
Test name
Test status
Simulation time 63244994 ps
CPU time 0.53 seconds
Started Feb 18 12:30:55 PM PST 24
Finished Feb 18 12:30:58 PM PST 24
Peak memory 181768 kb
Host smart-7b69becd-5143-47ab-9474-0b5f80571495
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297310899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
297310899
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.395717793
Short name T126
Test name
Test status
Simulation time 1033971974669 ps
CPU time 425.9 seconds
Started Feb 18 12:30:45 PM PST 24
Finished Feb 18 12:37:54 PM PST 24
Peak memory 205208 kb
Host smart-60854f55-1fa7-4c31-a17d-e85ff70d9f93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395717793 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.395717793
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3679943777
Short name T351
Test name
Test status
Simulation time 695087745652 ps
CPU time 221.52 seconds
Started Feb 18 12:30:56 PM PST 24
Finished Feb 18 12:34:41 PM PST 24
Peak memory 182312 kb
Host smart-3f949899-468a-4f61-aa08-8d388bed589d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679943777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3679943777
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.3473148944
Short name T426
Test name
Test status
Simulation time 201008238221 ps
CPU time 300.82 seconds
Started Feb 18 12:30:57 PM PST 24
Finished Feb 18 12:36:00 PM PST 24
Peak memory 182452 kb
Host smart-623a5b69-2e50-4b4f-b6df-1e50fdc6725e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473148944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3473148944
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.4168334629
Short name T10
Test name
Test status
Simulation time 69364599 ps
CPU time 0.74 seconds
Started Feb 18 12:31:06 PM PST 24
Finished Feb 18 12:31:08 PM PST 24
Peak memory 182124 kb
Host smart-082a1cd1-c832-488e-84cc-cf7e5cb5945e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168334629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.4168334629
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.2991048583
Short name T34
Test name
Test status
Simulation time 381343124375 ps
CPU time 865.81 seconds
Started Feb 18 12:30:56 PM PST 24
Finished Feb 18 12:45:25 PM PST 24
Peak memory 207996 kb
Host smart-4c0afc8f-7f15-4ee7-b06b-60f931810132
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991048583 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.2991048583
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3090426649
Short name T178
Test name
Test status
Simulation time 331984989954 ps
CPU time 244.01 seconds
Started Feb 18 12:31:13 PM PST 24
Finished Feb 18 12:35:18 PM PST 24
Peak memory 182276 kb
Host smart-a981d077-2bcb-4036-84d7-245a4e0dccdb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090426649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3090426649
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1385147484
Short name T451
Test name
Test status
Simulation time 94458445501 ps
CPU time 129.92 seconds
Started Feb 18 12:30:45 PM PST 24
Finished Feb 18 12:32:58 PM PST 24
Peak memory 182332 kb
Host smart-af6f5b72-e2d3-439b-a22d-e8b495aa673f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385147484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1385147484
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.3014571408
Short name T256
Test name
Test status
Simulation time 791088659175 ps
CPU time 1038.58 seconds
Started Feb 18 12:31:06 PM PST 24
Finished Feb 18 12:48:32 PM PST 24
Peak memory 190580 kb
Host smart-cc59c4fe-a530-4463-a45b-6bde32bc56de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014571408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3014571408
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.1626509409
Short name T419
Test name
Test status
Simulation time 3579311907 ps
CPU time 1.31 seconds
Started Feb 18 12:31:08 PM PST 24
Finished Feb 18 12:31:10 PM PST 24
Peak memory 192616 kb
Host smart-9e0f12cf-60fe-4785-a112-0157e8e537b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626509409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1626509409
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2283749565
Short name T378
Test name
Test status
Simulation time 104109383 ps
CPU time 0.55 seconds
Started Feb 18 12:30:55 PM PST 24
Finished Feb 18 12:30:58 PM PST 24
Peak memory 182144 kb
Host smart-5c43475d-5b6b-4a8e-86ac-347466bd53d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283749565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2283749565
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1592008948
Short name T197
Test name
Test status
Simulation time 349758893801 ps
CPU time 595.52 seconds
Started Feb 18 12:31:02 PM PST 24
Finished Feb 18 12:41:00 PM PST 24
Peak memory 182424 kb
Host smart-57ccba97-87b1-4973-bd56-eb9e231ed531
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592008948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1592008948
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.1803277925
Short name T439
Test name
Test status
Simulation time 299262387720 ps
CPU time 124 seconds
Started Feb 18 12:30:52 PM PST 24
Finished Feb 18 12:32:58 PM PST 24
Peak memory 182344 kb
Host smart-d7b24cbe-23fd-4af1-a064-2bcb0317623f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803277925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.1803277925
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.1109848928
Short name T425
Test name
Test status
Simulation time 46876557954 ps
CPU time 82.52 seconds
Started Feb 18 12:30:56 PM PST 24
Finished Feb 18 12:32:21 PM PST 24
Peak memory 182372 kb
Host smart-7104210b-5436-4092-9f88-5533eac481b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109848928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.1109848928
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.2158853855
Short name T62
Test name
Test status
Simulation time 131739943828 ps
CPU time 246.11 seconds
Started Feb 18 12:31:09 PM PST 24
Finished Feb 18 12:35:16 PM PST 24
Peak memory 194392 kb
Host smart-2a12ea5f-1c4e-4e7a-a234-5c30d2747896
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158853855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.2158853855
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.2925858281
Short name T230
Test name
Test status
Simulation time 285007698192 ps
CPU time 74.93 seconds
Started Feb 18 12:31:22 PM PST 24
Finished Feb 18 12:32:39 PM PST 24
Peak memory 182308 kb
Host smart-ba151f5e-5133-4e1c-ba57-5788643a7d3e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925858281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.2925858281
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.3610099975
Short name T60
Test name
Test status
Simulation time 75161718447 ps
CPU time 117.77 seconds
Started Feb 18 12:31:22 PM PST 24
Finished Feb 18 12:33:22 PM PST 24
Peak memory 182344 kb
Host smart-1b8298bd-0834-4b98-9bcd-82800783d4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610099975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3610099975
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.579980972
Short name T233
Test name
Test status
Simulation time 118640082521 ps
CPU time 88.11 seconds
Started Feb 18 12:31:13 PM PST 24
Finished Feb 18 12:32:44 PM PST 24
Peak memory 182316 kb
Host smart-3cadd6d1-2377-42c4-b6d0-15a5f1a4f38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579980972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.579980972
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3604165863
Short name T217
Test name
Test status
Simulation time 1127272014819 ps
CPU time 838.59 seconds
Started Feb 18 12:31:06 PM PST 24
Finished Feb 18 12:45:05 PM PST 24
Peak memory 190480 kb
Host smart-8c161eee-e971-4f55-9dda-d70e0172cb7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604165863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3604165863
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.2476999376
Short name T382
Test name
Test status
Simulation time 51469948659 ps
CPU time 413.4 seconds
Started Feb 18 12:31:14 PM PST 24
Finished Feb 18 12:38:10 PM PST 24
Peak memory 205232 kb
Host smart-4c1dec71-a50f-4deb-8a4b-112b4959b22f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476999376 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.2476999376
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3959614631
Short name T226
Test name
Test status
Simulation time 102362664255 ps
CPU time 54.27 seconds
Started Feb 18 12:31:18 PM PST 24
Finished Feb 18 12:32:16 PM PST 24
Peak memory 182300 kb
Host smart-e60b6405-10e2-4efc-8c18-cef43c4b46ce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959614631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3959614631
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.178779761
Short name T450
Test name
Test status
Simulation time 78250762659 ps
CPU time 125.98 seconds
Started Feb 18 12:31:13 PM PST 24
Finished Feb 18 12:33:21 PM PST 24
Peak memory 182408 kb
Host smart-0a2a0f8e-576f-43f1-991f-75c8382cb051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178779761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.178779761
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.427346235
Short name T337
Test name
Test status
Simulation time 123970551667 ps
CPU time 60.56 seconds
Started Feb 18 12:31:01 PM PST 24
Finished Feb 18 12:32:04 PM PST 24
Peak memory 182384 kb
Host smart-05ec3258-30ce-4eee-b3a7-008c35b46553
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427346235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.427346235
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.251857351
Short name T464
Test name
Test status
Simulation time 61360686753 ps
CPU time 155.86 seconds
Started Feb 18 12:30:57 PM PST 24
Finished Feb 18 12:33:36 PM PST 24
Peak memory 190484 kb
Host smart-01a85869-112c-48b8-9f3c-e721291a7148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251857351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.251857351
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1902162797
Short name T443
Test name
Test status
Simulation time 185466130051 ps
CPU time 168.28 seconds
Started Feb 18 12:30:28 PM PST 24
Finished Feb 18 12:33:27 PM PST 24
Peak memory 182268 kb
Host smart-d2f096d8-4b95-470e-9d48-61a2337486c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902162797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1902162797
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.2493243052
Short name T390
Test name
Test status
Simulation time 239268497517 ps
CPU time 211.85 seconds
Started Feb 18 12:30:40 PM PST 24
Finished Feb 18 12:34:16 PM PST 24
Peak memory 182352 kb
Host smart-344fcf19-7435-4ef2-aa7d-968f5957c3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493243052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2493243052
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.2345910416
Short name T203
Test name
Test status
Simulation time 188071364639 ps
CPU time 1222.52 seconds
Started Feb 18 12:30:26 PM PST 24
Finished Feb 18 12:50:59 PM PST 24
Peak memory 190636 kb
Host smart-ab1449c9-7de6-440f-b2a2-df4d85ede2e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345910416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2345910416
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2330735464
Short name T436
Test name
Test status
Simulation time 123500644 ps
CPU time 0.53 seconds
Started Feb 18 12:30:25 PM PST 24
Finished Feb 18 12:30:36 PM PST 24
Peak memory 182120 kb
Host smart-087ea8c9-d5c2-4571-a6cb-d36b3db87cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330735464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2330735464
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.511651142
Short name T247
Test name
Test status
Simulation time 77423276236 ps
CPU time 458.83 seconds
Started Feb 18 12:30:38 PM PST 24
Finished Feb 18 12:38:22 PM PST 24
Peak memory 190536 kb
Host smart-adbbd5a3-e9e3-4a1a-8bcb-f1cee1a905da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511651142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.511651142
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.143134405
Short name T53
Test name
Test status
Simulation time 187713838525 ps
CPU time 424.75 seconds
Started Feb 18 12:30:41 PM PST 24
Finished Feb 18 12:37:50 PM PST 24
Peak memory 205264 kb
Host smart-e09ad322-78f6-4db4-a321-31e2a5197d80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143134405 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.143134405
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.1007459188
Short name T137
Test name
Test status
Simulation time 130338612222 ps
CPU time 254.49 seconds
Started Feb 18 12:31:11 PM PST 24
Finished Feb 18 12:35:27 PM PST 24
Peak memory 190520 kb
Host smart-8538e204-1793-4965-9aba-37bf56df8cd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007459188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1007459188
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.541001392
Short name T225
Test name
Test status
Simulation time 757264711691 ps
CPU time 474.79 seconds
Started Feb 18 12:31:13 PM PST 24
Finished Feb 18 12:39:09 PM PST 24
Peak memory 190520 kb
Host smart-39188ec0-8f1a-42e4-adec-5f23e0c22ef6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541001392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.541001392
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.854531505
Short name T335
Test name
Test status
Simulation time 15754499037 ps
CPU time 98.06 seconds
Started Feb 18 12:31:10 PM PST 24
Finished Feb 18 12:32:49 PM PST 24
Peak memory 182336 kb
Host smart-85e81dd3-6534-4bcf-a092-4b37f85db5b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854531505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.854531505
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.2153319821
Short name T154
Test name
Test status
Simulation time 428063159149 ps
CPU time 377.09 seconds
Started Feb 18 12:31:14 PM PST 24
Finished Feb 18 12:37:33 PM PST 24
Peak memory 190476 kb
Host smart-e3dc7be6-b28c-462c-a791-effd43d40424
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153319821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2153319821
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.555346614
Short name T1
Test name
Test status
Simulation time 17624207770 ps
CPU time 30.16 seconds
Started Feb 18 12:31:11 PM PST 24
Finished Feb 18 12:31:42 PM PST 24
Peak memory 182280 kb
Host smart-c75dd8e9-8127-4cfe-8d6c-2003055df9ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555346614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.555346614
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.2590833148
Short name T313
Test name
Test status
Simulation time 576536285265 ps
CPU time 1653.24 seconds
Started Feb 18 12:31:12 PM PST 24
Finished Feb 18 12:58:47 PM PST 24
Peak memory 190540 kb
Host smart-b2710ede-8b1a-4dd9-b23f-566139ee762f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590833148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2590833148
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.1159817704
Short name T70
Test name
Test status
Simulation time 1239806156130 ps
CPU time 247.95 seconds
Started Feb 18 12:30:59 PM PST 24
Finished Feb 18 12:35:09 PM PST 24
Peak memory 190604 kb
Host smart-c86b4307-e199-4db0-8f08-6b2865adeb27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159817704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1159817704
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3965393245
Short name T151
Test name
Test status
Simulation time 258409508750 ps
CPU time 398.05 seconds
Started Feb 18 12:30:40 PM PST 24
Finished Feb 18 12:37:22 PM PST 24
Peak memory 182384 kb
Host smart-c221eabf-fe08-466c-96fd-ec30afdd15f3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965393245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.3965393245
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.1050787504
Short name T376
Test name
Test status
Simulation time 100218252552 ps
CPU time 146.68 seconds
Started Feb 18 12:30:20 PM PST 24
Finished Feb 18 12:32:53 PM PST 24
Peak memory 182232 kb
Host smart-3808f65d-1667-40a7-8b53-2ca10fbd0981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050787504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1050787504
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.1476439225
Short name T93
Test name
Test status
Simulation time 194915898894 ps
CPU time 435.74 seconds
Started Feb 18 12:30:22 PM PST 24
Finished Feb 18 12:37:45 PM PST 24
Peak memory 192732 kb
Host smart-1469142b-91f3-4727-9417-d7a836c2b1b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476439225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1476439225
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.269788053
Short name T349
Test name
Test status
Simulation time 153896265942 ps
CPU time 173.51 seconds
Started Feb 18 12:30:19 PM PST 24
Finished Feb 18 12:33:19 PM PST 24
Peak memory 194216 kb
Host smart-d48440a8-2346-4786-be97-514616f6f357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269788053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.269788053
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.152457415
Short name T296
Test name
Test status
Simulation time 20597803564 ps
CPU time 12.93 seconds
Started Feb 18 12:30:36 PM PST 24
Finished Feb 18 12:30:55 PM PST 24
Peak memory 182276 kb
Host smart-4e92b733-20f9-469c-a043-9e9ac8fc8e37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152457415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.152457415
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.4204972717
Short name T339
Test name
Test status
Simulation time 204362386941 ps
CPU time 134.82 seconds
Started Feb 18 12:31:13 PM PST 24
Finished Feb 18 12:33:30 PM PST 24
Peak memory 182368 kb
Host smart-f1a5db16-5563-445c-a272-5dbd8843e658
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204972717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.4204972717
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1961052275
Short name T370
Test name
Test status
Simulation time 116672347337 ps
CPU time 66.35 seconds
Started Feb 18 12:31:16 PM PST 24
Finished Feb 18 12:32:26 PM PST 24
Peak memory 182380 kb
Host smart-e6de6e4f-154a-40ac-a33c-9c03794e66d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961052275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1961052275
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.3436558452
Short name T71
Test name
Test status
Simulation time 20220842081 ps
CPU time 102.62 seconds
Started Feb 18 12:31:15 PM PST 24
Finished Feb 18 12:33:05 PM PST 24
Peak memory 190544 kb
Host smart-62529f1b-9fae-494e-9be8-508579e73bc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436558452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3436558452
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1615470364
Short name T252
Test name
Test status
Simulation time 72895459663 ps
CPU time 110.51 seconds
Started Feb 18 12:30:58 PM PST 24
Finished Feb 18 12:32:51 PM PST 24
Peak memory 182368 kb
Host smart-7c1daf1f-94ff-450d-a842-5896d4ed5f93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615470364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1615470364
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.283163736
Short name T57
Test name
Test status
Simulation time 184815975929 ps
CPU time 40.45 seconds
Started Feb 18 12:31:10 PM PST 24
Finished Feb 18 12:31:52 PM PST 24
Peak memory 182336 kb
Host smart-b7c2603a-e6e7-45a8-88ed-f703185fa237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283163736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.283163736
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.4252495468
Short name T264
Test name
Test status
Simulation time 182043107530 ps
CPU time 448.63 seconds
Started Feb 18 12:31:12 PM PST 24
Finished Feb 18 12:38:42 PM PST 24
Peak memory 194016 kb
Host smart-a77a2fcd-3c8d-4cba-97c7-69f821bab166
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252495468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.4252495468
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.1289528606
Short name T316
Test name
Test status
Simulation time 314357851176 ps
CPU time 148.91 seconds
Started Feb 18 12:31:10 PM PST 24
Finished Feb 18 12:33:41 PM PST 24
Peak memory 190492 kb
Host smart-03157814-6de4-4211-9771-e895ae862ae7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289528606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1289528606
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.318146442
Short name T147
Test name
Test status
Simulation time 1773091462008 ps
CPU time 1157.52 seconds
Started Feb 18 12:30:34 PM PST 24
Finished Feb 18 12:49:59 PM PST 24
Peak memory 182280 kb
Host smart-01e03bb5-69ce-4251-9498-a457c60440ce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318146442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.rv_timer_cfg_update_on_fly.318146442
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3629246539
Short name T394
Test name
Test status
Simulation time 75687549948 ps
CPU time 31.96 seconds
Started Feb 18 12:30:24 PM PST 24
Finished Feb 18 12:31:04 PM PST 24
Peak memory 182332 kb
Host smart-4c23f88a-25c7-424a-b19d-1d28ead42a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629246539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3629246539
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.3021990945
Short name T391
Test name
Test status
Simulation time 4948357998 ps
CPU time 9.46 seconds
Started Feb 18 12:30:38 PM PST 24
Finished Feb 18 12:30:53 PM PST 24
Peak memory 193396 kb
Host smart-d607d572-13bb-407c-83d6-1dbe3275a9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021990945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3021990945
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1590992265
Short name T260
Test name
Test status
Simulation time 77632402603 ps
CPU time 1697.23 seconds
Started Feb 18 12:30:31 PM PST 24
Finished Feb 18 12:58:57 PM PST 24
Peak memory 190564 kb
Host smart-96f933db-62bc-4348-9319-ea11cab4b336
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590992265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1590992265
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.3343206320
Short name T380
Test name
Test status
Simulation time 242298848806 ps
CPU time 448.06 seconds
Started Feb 18 12:30:42 PM PST 24
Finished Feb 18 12:38:14 PM PST 24
Peak memory 205256 kb
Host smart-88f156b8-2ca0-43dc-98ef-b7f8ef66afd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343206320 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.3343206320
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.rv_timer_random.2922299816
Short name T257
Test name
Test status
Simulation time 371916600131 ps
CPU time 216.57 seconds
Started Feb 18 12:31:12 PM PST 24
Finished Feb 18 12:34:50 PM PST 24
Peak memory 192804 kb
Host smart-5de4e516-503e-4ebd-a35a-fb01b57ab785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922299816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2922299816
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.1156600672
Short name T358
Test name
Test status
Simulation time 106432128715 ps
CPU time 204.57 seconds
Started Feb 18 12:31:01 PM PST 24
Finished Feb 18 12:34:28 PM PST 24
Peak memory 190576 kb
Host smart-6ebfb08f-1270-4685-9a0c-5823ae4baebe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156600672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1156600672
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3966880802
Short name T224
Test name
Test status
Simulation time 149461963951 ps
CPU time 347.74 seconds
Started Feb 18 12:31:03 PM PST 24
Finished Feb 18 12:36:53 PM PST 24
Peak memory 190576 kb
Host smart-72dc873a-5ddd-4b6a-a412-a5b25deed16e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966880802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3966880802
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3994113463
Short name T214
Test name
Test status
Simulation time 775730696700 ps
CPU time 163.55 seconds
Started Feb 18 12:30:55 PM PST 24
Finished Feb 18 12:33:41 PM PST 24
Peak memory 190512 kb
Host smart-0159c313-b316-461d-a5b5-9fd49fbc66b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994113463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3994113463
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.434072099
Short name T249
Test name
Test status
Simulation time 3701807557361 ps
CPU time 914.98 seconds
Started Feb 18 12:30:27 PM PST 24
Finished Feb 18 12:45:53 PM PST 24
Peak memory 182260 kb
Host smart-cd9eb6bf-113b-47ad-a9f3-c3ac6f8a03c4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434072099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.rv_timer_cfg_update_on_fly.434072099
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3878091327
Short name T466
Test name
Test status
Simulation time 64368381223 ps
CPU time 91.54 seconds
Started Feb 18 12:30:22 PM PST 24
Finished Feb 18 12:32:00 PM PST 24
Peak memory 182316 kb
Host smart-589c73ca-8cbf-457d-9dbb-b7bad69c90c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878091327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3878091327
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.2569593537
Short name T262
Test name
Test status
Simulation time 57637598361 ps
CPU time 131.92 seconds
Started Feb 18 12:30:28 PM PST 24
Finished Feb 18 12:32:50 PM PST 24
Peak memory 190512 kb
Host smart-ebdc3109-e2e5-4934-82dd-11130e7b50c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569593537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2569593537
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.3573572727
Short name T255
Test name
Test status
Simulation time 136825428599 ps
CPU time 206.84 seconds
Started Feb 18 12:30:18 PM PST 24
Finished Feb 18 12:33:51 PM PST 24
Peak memory 194268 kb
Host smart-aece86d0-975c-490b-8e38-5967e5c9391c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573572727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3573572727
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3507507303
Short name T63
Test name
Test status
Simulation time 25298172674 ps
CPU time 96.54 seconds
Started Feb 18 12:30:25 PM PST 24
Finished Feb 18 12:32:12 PM PST 24
Peak memory 194512 kb
Host smart-388ee453-abd8-4c91-9739-f3fcd061ab00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507507303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3507507303
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.1352580433
Short name T49
Test name
Test status
Simulation time 573600940098 ps
CPU time 1081.85 seconds
Started Feb 18 12:30:24 PM PST 24
Finished Feb 18 12:48:35 PM PST 24
Peak memory 212536 kb
Host smart-2d40fbf0-232a-4614-80d3-2b517746d2d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352580433 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.1352580433
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.3698065708
Short name T283
Test name
Test status
Simulation time 102390823034 ps
CPU time 749.97 seconds
Started Feb 18 12:31:19 PM PST 24
Finished Feb 18 12:43:53 PM PST 24
Peak memory 190488 kb
Host smart-15170cf8-5d5f-4521-b747-3efdb5a355f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698065708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3698065708
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1641465553
Short name T273
Test name
Test status
Simulation time 91243055435 ps
CPU time 44.88 seconds
Started Feb 18 12:31:10 PM PST 24
Finished Feb 18 12:31:57 PM PST 24
Peak memory 190528 kb
Host smart-94ad36fd-437e-4896-a08d-7b518c10277b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641465553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1641465553
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.555850600
Short name T149
Test name
Test status
Simulation time 1211987495387 ps
CPU time 458.02 seconds
Started Feb 18 12:31:08 PM PST 24
Finished Feb 18 12:38:48 PM PST 24
Peak memory 190708 kb
Host smart-08d2c93a-f5c4-4c1f-947a-898377e97a09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555850600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.555850600
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2836988740
Short name T305
Test name
Test status
Simulation time 208228422607 ps
CPU time 219.84 seconds
Started Feb 18 12:31:06 PM PST 24
Finished Feb 18 12:34:47 PM PST 24
Peak memory 190708 kb
Host smart-a70fb4c9-05c5-4b98-a8a0-8f86e0f54437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836988740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2836988740
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.760705241
Short name T311
Test name
Test status
Simulation time 341417505800 ps
CPU time 83.24 seconds
Started Feb 18 12:31:16 PM PST 24
Finished Feb 18 12:32:43 PM PST 24
Peak memory 190576 kb
Host smart-70437167-2fd5-417d-b11e-73f20e39196d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760705241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.760705241
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3189784368
Short name T228
Test name
Test status
Simulation time 77198483504 ps
CPU time 158.59 seconds
Started Feb 18 12:31:14 PM PST 24
Finished Feb 18 12:33:56 PM PST 24
Peak memory 190568 kb
Host smart-1d61587e-5df7-4497-bd45-1791010e4d1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189784368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3189784368
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.4113109951
Short name T369
Test name
Test status
Simulation time 86348991772 ps
CPU time 125.83 seconds
Started Feb 18 12:31:16 PM PST 24
Finished Feb 18 12:33:26 PM PST 24
Peak memory 193936 kb
Host smart-b3de2823-00d1-4b98-bed8-818e1cd1253c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113109951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.4113109951
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.1465294577
Short name T329
Test name
Test status
Simulation time 50861182751 ps
CPU time 84.59 seconds
Started Feb 18 12:31:10 PM PST 24
Finished Feb 18 12:32:36 PM PST 24
Peak memory 182328 kb
Host smart-b254ee75-d0db-436b-9e71-13bcae6b458a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465294577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.1465294577
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2582927916
Short name T268
Test name
Test status
Simulation time 129068914847 ps
CPU time 244.79 seconds
Started Feb 18 12:30:19 PM PST 24
Finished Feb 18 12:34:31 PM PST 24
Peak memory 182308 kb
Host smart-f4ef4bf9-8849-4b42-be37-5e4e2f52ff9c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582927916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2582927916
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.814310233
Short name T386
Test name
Test status
Simulation time 651509561351 ps
CPU time 313.05 seconds
Started Feb 18 12:30:44 PM PST 24
Finished Feb 18 12:36:01 PM PST 24
Peak memory 182328 kb
Host smart-7c4aac2e-be7b-4e15-8a79-8f873533b796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814310233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.814310233
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.101208314
Short name T213
Test name
Test status
Simulation time 185767243500 ps
CPU time 269.6 seconds
Started Feb 18 12:30:42 PM PST 24
Finished Feb 18 12:35:16 PM PST 24
Peak memory 192812 kb
Host smart-d1e8f745-9cb5-4312-9519-06bb6a848b35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101208314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.101208314
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.448718576
Short name T290
Test name
Test status
Simulation time 223967335265 ps
CPU time 139.08 seconds
Started Feb 18 12:30:21 PM PST 24
Finished Feb 18 12:32:47 PM PST 24
Peak memory 193872 kb
Host smart-a753d6ce-e0f1-4c7a-86b2-6f6f89828e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448718576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.448718576
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.140187789
Short name T449
Test name
Test status
Simulation time 5460524748 ps
CPU time 5.1 seconds
Started Feb 18 12:30:53 PM PST 24
Finished Feb 18 12:31:00 PM PST 24
Peak memory 182252 kb
Host smart-bbc3f510-0a61-4e27-8460-6b5b78c008f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140187789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.140187789
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/91.rv_timer_random.3008314532
Short name T350
Test name
Test status
Simulation time 255319396939 ps
CPU time 3096.17 seconds
Started Feb 18 12:31:13 PM PST 24
Finished Feb 18 01:22:52 PM PST 24
Peak memory 190484 kb
Host smart-c0309e7b-799b-470a-b5c6-0ee78ff69d8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008314532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3008314532
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1332344171
Short name T3
Test name
Test status
Simulation time 287868640428 ps
CPU time 80.99 seconds
Started Feb 18 12:31:21 PM PST 24
Finished Feb 18 12:32:45 PM PST 24
Peak memory 182384 kb
Host smart-f83848cc-d49a-406d-ac54-6cb6f5b6105d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332344171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1332344171
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3743740244
Short name T447
Test name
Test status
Simulation time 272989670 ps
CPU time 0.73 seconds
Started Feb 18 12:31:09 PM PST 24
Finished Feb 18 12:31:12 PM PST 24
Peak memory 182240 kb
Host smart-65a6dfcb-f68d-4483-9e2e-d521b173442d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743740244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3743740244
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.4114070600
Short name T121
Test name
Test status
Simulation time 46430827181 ps
CPU time 80.63 seconds
Started Feb 18 12:31:11 PM PST 24
Finished Feb 18 12:32:33 PM PST 24
Peak memory 182292 kb
Host smart-658dd68e-c7de-4709-b593-3959218a7c43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114070600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.4114070600
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.2633974211
Short name T341
Test name
Test status
Simulation time 119983479619 ps
CPU time 57.96 seconds
Started Feb 18 12:31:17 PM PST 24
Finished Feb 18 12:32:19 PM PST 24
Peak memory 182384 kb
Host smart-f9a2b1a5-49bc-4475-a298-cf04cab622bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633974211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2633974211
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2280540963
Short name T106
Test name
Test status
Simulation time 135906119228 ps
CPU time 647.84 seconds
Started Feb 18 12:31:19 PM PST 24
Finished Feb 18 12:42:10 PM PST 24
Peak memory 182328 kb
Host smart-d7073a60-986b-42e0-8b06-60c82c0c978a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280540963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2280540963
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3833003700
Short name T353
Test name
Test status
Simulation time 20250947275 ps
CPU time 30.71 seconds
Started Feb 18 12:31:31 PM PST 24
Finished Feb 18 12:32:07 PM PST 24
Peak memory 182360 kb
Host smart-990d5f99-5296-4a35-b0b0-e61748ad05bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833003700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3833003700
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.3633979410
Short name T152
Test name
Test status
Simulation time 104884953493 ps
CPU time 185.8 seconds
Started Feb 18 12:31:12 PM PST 24
Finished Feb 18 12:34:19 PM PST 24
Peak memory 190568 kb
Host smart-e2362abe-7aeb-4c5d-9d69-1d1ae1899e2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633979410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3633979410
Directory /workspace/99.rv_timer_random/latest
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