Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.59 99.36 98.73 100.00 100.00 100.00 99.43


Total test records in report: 582
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T504 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2464687831 Feb 21 12:34:17 PM PST 24 Feb 21 12:34:20 PM PST 24 13499584 ps
T505 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1408690142 Feb 21 12:34:36 PM PST 24 Feb 21 12:34:39 PM PST 24 38922907 ps
T506 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2469122326 Feb 21 12:35:35 PM PST 24 Feb 21 12:35:35 PM PST 24 59873935 ps
T507 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2949402857 Feb 21 12:34:44 PM PST 24 Feb 21 12:34:46 PM PST 24 34505815 ps
T508 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.711754478 Feb 21 12:34:14 PM PST 24 Feb 21 12:34:16 PM PST 24 14820495 ps
T509 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3125736163 Feb 21 12:34:36 PM PST 24 Feb 21 12:34:39 PM PST 24 27521678 ps
T510 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1882861828 Feb 21 12:34:45 PM PST 24 Feb 21 12:34:47 PM PST 24 19943650 ps
T511 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3772236543 Feb 21 12:34:18 PM PST 24 Feb 21 12:34:20 PM PST 24 60704003 ps
T512 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3820924694 Feb 21 12:34:38 PM PST 24 Feb 21 12:34:41 PM PST 24 37681178 ps
T513 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.242707405 Feb 21 12:34:16 PM PST 24 Feb 21 12:34:20 PM PST 24 170875733 ps
T514 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1519738218 Feb 21 12:34:22 PM PST 24 Feb 21 12:34:23 PM PST 24 60693122 ps
T515 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1386282320 Feb 21 12:34:41 PM PST 24 Feb 21 12:34:42 PM PST 24 93428279 ps
T516 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3065461019 Feb 21 12:34:43 PM PST 24 Feb 21 12:34:45 PM PST 24 15551745 ps
T517 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1984291479 Feb 21 12:34:27 PM PST 24 Feb 21 12:34:29 PM PST 24 143403446 ps
T518 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2482706407 Feb 21 12:34:41 PM PST 24 Feb 21 12:34:43 PM PST 24 351135297 ps
T519 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.254839997 Feb 21 12:34:21 PM PST 24 Feb 21 12:34:22 PM PST 24 35707639 ps
T520 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.259469755 Feb 21 12:34:31 PM PST 24 Feb 21 12:34:33 PM PST 24 16797490 ps
T521 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3766669998 Feb 21 12:34:32 PM PST 24 Feb 21 12:34:33 PM PST 24 14296790 ps
T522 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2051203564 Feb 21 12:34:53 PM PST 24 Feb 21 12:34:58 PM PST 24 23305148 ps
T523 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.264825409 Feb 21 12:34:33 PM PST 24 Feb 21 12:34:34 PM PST 24 120855165 ps
T524 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.912760351 Feb 21 12:34:40 PM PST 24 Feb 21 12:34:42 PM PST 24 29637598 ps
T525 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1652678921 Feb 21 12:34:32 PM PST 24 Feb 21 12:34:34 PM PST 24 540382499 ps
T526 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1263000558 Feb 21 12:34:24 PM PST 24 Feb 21 12:34:25 PM PST 24 29657269 ps
T527 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3628770766 Feb 21 12:34:16 PM PST 24 Feb 21 12:34:22 PM PST 24 520400457 ps
T528 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2374403037 Feb 21 12:34:14 PM PST 24 Feb 21 12:34:16 PM PST 24 25324940 ps
T529 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1211815003 Feb 21 12:34:15 PM PST 24 Feb 21 12:34:17 PM PST 24 26986712 ps
T530 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1539155424 Feb 21 12:34:23 PM PST 24 Feb 21 12:34:25 PM PST 24 40016873 ps
T531 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2126502271 Feb 21 12:34:34 PM PST 24 Feb 21 12:34:35 PM PST 24 36348446 ps
T532 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1896595511 Feb 21 12:34:44 PM PST 24 Feb 21 12:34:46 PM PST 24 98830652 ps
T533 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3296415330 Feb 21 12:34:18 PM PST 24 Feb 21 12:34:20 PM PST 24 14799040 ps
T534 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2862162328 Feb 21 12:34:46 PM PST 24 Feb 21 12:34:47 PM PST 24 74614524 ps
T535 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3260775071 Feb 21 12:34:53 PM PST 24 Feb 21 12:34:58 PM PST 24 65196176 ps
T536 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1808395564 Feb 21 12:34:44 PM PST 24 Feb 21 12:34:45 PM PST 24 13938341 ps
T537 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.4280255311 Feb 21 12:34:47 PM PST 24 Feb 21 12:34:49 PM PST 24 12176052 ps
T538 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1453239078 Feb 21 12:34:50 PM PST 24 Feb 21 12:34:57 PM PST 24 20083068 ps
T539 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2063255329 Feb 21 12:34:43 PM PST 24 Feb 21 12:34:45 PM PST 24 204466122 ps
T82 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1841642340 Feb 21 12:34:53 PM PST 24 Feb 21 12:34:59 PM PST 24 13664951 ps
T540 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2610807218 Feb 21 12:34:36 PM PST 24 Feb 21 12:34:39 PM PST 24 31100361 ps
T541 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1471507766 Feb 21 12:34:47 PM PST 24 Feb 21 12:34:53 PM PST 24 37261105 ps
T542 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1186423095 Feb 21 12:34:15 PM PST 24 Feb 21 12:34:18 PM PST 24 104109895 ps
T543 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2094569825 Feb 21 12:34:39 PM PST 24 Feb 21 12:34:42 PM PST 24 20803854 ps
T544 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3746538701 Feb 21 12:34:23 PM PST 24 Feb 21 12:34:25 PM PST 24 299278812 ps
T545 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3518638285 Feb 21 12:34:37 PM PST 24 Feb 21 12:34:38 PM PST 24 198849864 ps
T546 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.684961069 Feb 21 12:34:41 PM PST 24 Feb 21 12:34:42 PM PST 24 18471243 ps
T547 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2704213899 Feb 21 12:34:40 PM PST 24 Feb 21 12:34:43 PM PST 24 72145707 ps
T548 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1401132118 Feb 21 12:34:45 PM PST 24 Feb 21 12:34:47 PM PST 24 110905755 ps
T549 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1824836638 Feb 21 12:34:52 PM PST 24 Feb 21 12:34:58 PM PST 24 39126102 ps
T550 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3706692901 Feb 21 12:34:42 PM PST 24 Feb 21 12:34:43 PM PST 24 35985980 ps
T551 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1112930786 Feb 21 12:34:33 PM PST 24 Feb 21 12:34:34 PM PST 24 34119834 ps
T552 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1035486452 Feb 21 12:34:50 PM PST 24 Feb 21 12:34:57 PM PST 24 21207314 ps
T553 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3029647713 Feb 21 12:34:43 PM PST 24 Feb 21 12:34:44 PM PST 24 12634168 ps
T554 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2381806516 Feb 21 12:34:21 PM PST 24 Feb 21 12:34:22 PM PST 24 15884285 ps
T555 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3844074579 Feb 21 12:34:38 PM PST 24 Feb 21 12:34:42 PM PST 24 48568971 ps
T556 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.534726895 Feb 21 12:34:27 PM PST 24 Feb 21 12:34:28 PM PST 24 50101042 ps
T557 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3944060350 Feb 21 12:34:28 PM PST 24 Feb 21 12:34:29 PM PST 24 82672667 ps
T558 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1945087629 Feb 21 12:34:14 PM PST 24 Feb 21 12:34:25 PM PST 24 76044619 ps
T559 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3185298414 Feb 21 12:34:37 PM PST 24 Feb 21 12:34:39 PM PST 24 77801404 ps
T560 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3222443447 Feb 21 12:34:25 PM PST 24 Feb 21 12:34:26 PM PST 24 49827809 ps
T561 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.442657601 Feb 21 12:34:37 PM PST 24 Feb 21 12:34:39 PM PST 24 75436484 ps
T562 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2288681263 Feb 21 12:34:38 PM PST 24 Feb 21 12:34:47 PM PST 24 33530775 ps
T563 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.166091509 Feb 21 12:34:20 PM PST 24 Feb 21 12:34:22 PM PST 24 79849902 ps
T564 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3070416685 Feb 21 12:34:28 PM PST 24 Feb 21 12:34:30 PM PST 24 97530341 ps
T565 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.903616020 Feb 21 12:34:13 PM PST 24 Feb 21 12:34:15 PM PST 24 88408136 ps
T566 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1553436983 Feb 21 12:34:32 PM PST 24 Feb 21 12:34:34 PM PST 24 252431748 ps
T567 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3282271605 Feb 21 12:34:53 PM PST 24 Feb 21 12:34:58 PM PST 24 44057300 ps
T568 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3129482569 Feb 21 12:34:21 PM PST 24 Feb 21 12:34:23 PM PST 24 147791495 ps
T569 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1512742338 Feb 21 12:34:50 PM PST 24 Feb 21 12:34:58 PM PST 24 85238478 ps
T570 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3505647846 Feb 21 12:34:35 PM PST 24 Feb 21 12:34:36 PM PST 24 51341333 ps
T571 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3129057765 Feb 21 12:34:47 PM PST 24 Feb 21 12:34:53 PM PST 24 16754446 ps
T572 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1197296972 Feb 21 12:34:36 PM PST 24 Feb 21 12:34:39 PM PST 24 43909219 ps
T84 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1584848192 Feb 21 12:34:32 PM PST 24 Feb 21 12:34:34 PM PST 24 57819363 ps
T573 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2043031852 Feb 21 12:34:21 PM PST 24 Feb 21 12:34:22 PM PST 24 11824546 ps
T574 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3854219335 Feb 21 12:34:46 PM PST 24 Feb 21 12:34:49 PM PST 24 15686956 ps
T575 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3869658928 Feb 21 12:34:42 PM PST 24 Feb 21 12:34:44 PM PST 24 147543419 ps
T576 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2459128444 Feb 21 12:34:21 PM PST 24 Feb 21 12:34:22 PM PST 24 15501736 ps
T83 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1101914436 Feb 21 12:34:36 PM PST 24 Feb 21 12:34:40 PM PST 24 850942353 ps
T577 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2012441100 Feb 21 12:34:34 PM PST 24 Feb 21 12:34:35 PM PST 24 17053733 ps
T578 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2544370854 Feb 21 12:34:39 PM PST 24 Feb 21 12:34:42 PM PST 24 31281412 ps
T579 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1950209865 Feb 21 12:34:39 PM PST 24 Feb 21 12:34:42 PM PST 24 84663707 ps
T580 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2064907346 Feb 21 12:34:33 PM PST 24 Feb 21 12:34:45 PM PST 24 23122855 ps
T581 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.56303821 Feb 21 12:34:35 PM PST 24 Feb 21 12:34:36 PM PST 24 14866527 ps
T582 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.4160318140 Feb 21 12:34:27 PM PST 24 Feb 21 12:34:28 PM PST 24 132609756 ps

Test location /workspace/coverage/default/11.rv_timer_stress_all.1630466629
Short name T1
Test name
Test status
Simulation time 1967849662170 ps
CPU time 700.11 seconds
Started Feb 21 12:42:42 PM PST 24
Finished Feb 21 12:54:23 PM PST 24
Peak memory 190956 kb
Host smart-3e072716-e79f-428a-9441-4cb8aafdbcce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630466629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1630466629
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_random.1486890372
Short name T104
Test name
Test status
Simulation time 584488502461 ps
CPU time 646.49 seconds
Started Feb 21 12:43:00 PM PST 24
Finished Feb 21 12:53:47 PM PST 24
Peak memory 190940 kb
Host smart-2d2d0020-4cfb-4eda-b9f1-1696e2503ac2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486890372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1486890372
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.1766602968
Short name T15
Test name
Test status
Simulation time 60619926483 ps
CPU time 356.97 seconds
Started Feb 21 12:42:36 PM PST 24
Finished Feb 21 12:48:34 PM PST 24
Peak memory 197596 kb
Host smart-9ede0534-7f1a-4b0e-8fb3-887995adff08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766602968 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.1766602968
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1474184585
Short name T65
Test name
Test status
Simulation time 582461576477 ps
CPU time 2922.29 seconds
Started Feb 21 12:42:58 PM PST 24
Finished Feb 21 01:31:42 PM PST 24
Peak memory 194296 kb
Host smart-9b1cc744-1550-4bd4-be5c-a8e813183a83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474184585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1474184585
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.1058250572
Short name T48
Test name
Test status
Simulation time 3614337437389 ps
CPU time 2305.85 seconds
Started Feb 21 12:43:07 PM PST 24
Finished Feb 21 01:21:33 PM PST 24
Peak memory 190872 kb
Host smart-883caca4-0bda-4935-838a-ebcec922292d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058250572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.1058250572
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.3399561235
Short name T2
Test name
Test status
Simulation time 119026215 ps
CPU time 0.8 seconds
Started Feb 21 12:42:27 PM PST 24
Finished Feb 21 12:42:28 PM PST 24
Peak memory 213052 kb
Host smart-f4b087ef-5f1f-4a8a-8c67-ec8122874b93
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399561235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.3399561235
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3347652801
Short name T136
Test name
Test status
Simulation time 2318282045237 ps
CPU time 1880.89 seconds
Started Feb 21 12:42:48 PM PST 24
Finished Feb 21 01:14:14 PM PST 24
Peak memory 190868 kb
Host smart-97c0e5b7-23ab-4158-8ae5-8c5490fb34ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347652801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3347652801
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1642392598
Short name T169
Test name
Test status
Simulation time 1487261778315 ps
CPU time 1984.15 seconds
Started Feb 21 12:43:02 PM PST 24
Finished Feb 21 01:16:07 PM PST 24
Peak memory 190984 kb
Host smart-9f18052f-7439-4bed-af12-8eb6c49f18fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642392598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1642392598
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2663546194
Short name T51
Test name
Test status
Simulation time 768867324575 ps
CPU time 1560.96 seconds
Started Feb 21 12:43:09 PM PST 24
Finished Feb 21 01:09:10 PM PST 24
Peak memory 195276 kb
Host smart-e91fd3d1-8751-4bb2-be9d-70b89239dc8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663546194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2663546194
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2595439687
Short name T50
Test name
Test status
Simulation time 292531818871 ps
CPU time 1264.76 seconds
Started Feb 21 12:42:57 PM PST 24
Finished Feb 21 01:04:04 PM PST 24
Peak memory 190948 kb
Host smart-dc75d750-d5c1-468d-a355-4846288b390e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595439687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2595439687
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.285748371
Short name T135
Test name
Test status
Simulation time 4484433534761 ps
CPU time 5389.5 seconds
Started Feb 21 12:42:59 PM PST 24
Finished Feb 21 02:12:50 PM PST 24
Peak memory 195292 kb
Host smart-761ed07a-56b9-44a5-b0e2-d5d8f8450cde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285748371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.
285748371
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2664538442
Short name T21
Test name
Test status
Simulation time 2140837516 ps
CPU time 1.38 seconds
Started Feb 21 12:34:26 PM PST 24
Finished Feb 21 12:34:28 PM PST 24
Peak memory 183160 kb
Host smart-306e340d-eb05-41b1-99d2-31310442420a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664538442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2664538442
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1875869580
Short name T49
Test name
Test status
Simulation time 545333629786 ps
CPU time 1107.5 seconds
Started Feb 21 12:42:40 PM PST 24
Finished Feb 21 01:01:08 PM PST 24
Peak memory 191016 kb
Host smart-06194795-2735-43dc-acba-e518687e231e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875869580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1875869580
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3690267498
Short name T239
Test name
Test status
Simulation time 565979399633 ps
CPU time 1685.29 seconds
Started Feb 21 12:43:06 PM PST 24
Finished Feb 21 01:11:12 PM PST 24
Peak memory 190976 kb
Host smart-570104fb-0dc6-4f6a-bd12-a464863aa6e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690267498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3690267498
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.635854291
Short name T142
Test name
Test status
Simulation time 1438418982381 ps
CPU time 1196.86 seconds
Started Feb 21 12:43:08 PM PST 24
Finished Feb 21 01:03:05 PM PST 24
Peak memory 195692 kb
Host smart-e5b3efae-97d3-4133-9fc4-1b3d2c3f7804
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635854291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
635854291
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1398158025
Short name T53
Test name
Test status
Simulation time 432673756969 ps
CPU time 802.33 seconds
Started Feb 21 12:42:38 PM PST 24
Finished Feb 21 12:56:02 PM PST 24
Peak memory 190744 kb
Host smart-f1b9c720-903a-4899-a99d-9a95b3717879
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398158025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1398158025
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.637008620
Short name T173
Test name
Test status
Simulation time 1199657727628 ps
CPU time 3054.57 seconds
Started Feb 21 12:42:54 PM PST 24
Finished Feb 21 01:33:50 PM PST 24
Peak memory 190904 kb
Host smart-05e9e017-099b-45f7-9d1c-5bf8396f202c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637008620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.637008620
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.1589161722
Short name T148
Test name
Test status
Simulation time 282964381949 ps
CPU time 340.64 seconds
Started Feb 21 12:43:24 PM PST 24
Finished Feb 21 12:49:06 PM PST 24
Peak memory 194100 kb
Host smart-0891a2df-41ad-42f7-8312-5c08435239fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589161722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1589161722
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1647668115
Short name T183
Test name
Test status
Simulation time 709523505625 ps
CPU time 1554.21 seconds
Started Feb 21 12:43:01 PM PST 24
Finished Feb 21 01:08:56 PM PST 24
Peak memory 190912 kb
Host smart-99cced04-e6d9-405a-8b2a-dc4e06d6bb5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647668115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1647668115
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.236773753
Short name T268
Test name
Test status
Simulation time 1580592117381 ps
CPU time 832.3 seconds
Started Feb 21 12:42:55 PM PST 24
Finished Feb 21 12:56:48 PM PST 24
Peak memory 190324 kb
Host smart-e67721d8-903d-42d5-9d68-47a1864a983f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236773753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.
236773753
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/179.rv_timer_random.3259961064
Short name T139
Test name
Test status
Simulation time 978232674871 ps
CPU time 904.69 seconds
Started Feb 21 12:43:33 PM PST 24
Finished Feb 21 12:58:39 PM PST 24
Peak memory 190972 kb
Host smart-dd638531-01f3-4e97-bc73-e51d2379462d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259961064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3259961064
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3479835511
Short name T146
Test name
Test status
Simulation time 649851535783 ps
CPU time 807.01 seconds
Started Feb 21 12:43:16 PM PST 24
Finished Feb 21 12:56:43 PM PST 24
Peak memory 190948 kb
Host smart-0cecc97e-50e3-4d7f-9a7a-04168e8ebca0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479835511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3479835511
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.439009903
Short name T177
Test name
Test status
Simulation time 102036154214 ps
CPU time 171.77 seconds
Started Feb 21 12:43:31 PM PST 24
Finished Feb 21 12:46:23 PM PST 24
Peak memory 190896 kb
Host smart-235efecd-5a97-4cbe-b5f8-5447056078cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439009903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.439009903
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.1195613491
Short name T54
Test name
Test status
Simulation time 1049037071109 ps
CPU time 583.39 seconds
Started Feb 21 12:43:00 PM PST 24
Finished Feb 21 12:52:44 PM PST 24
Peak memory 190768 kb
Host smart-69fab702-264f-4ccc-bb8d-aa23fefadb3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195613491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.1195613491
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/68.rv_timer_random.748595028
Short name T214
Test name
Test status
Simulation time 862587941874 ps
CPU time 387.53 seconds
Started Feb 21 12:43:19 PM PST 24
Finished Feb 21 12:49:47 PM PST 24
Peak memory 190932 kb
Host smart-ec892db2-6b4f-4715-8f75-e1d1cb081cbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748595028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.748595028
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.1356513577
Short name T140
Test name
Test status
Simulation time 660849502115 ps
CPU time 1311.06 seconds
Started Feb 21 12:42:55 PM PST 24
Finished Feb 21 01:04:47 PM PST 24
Peak memory 195512 kb
Host smart-ee71468a-0641-4fe2-9094-27e19c68bf4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356513577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.1356513577
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_random.545839140
Short name T229
Test name
Test status
Simulation time 130253264064 ps
CPU time 273.68 seconds
Started Feb 21 12:42:59 PM PST 24
Finished Feb 21 12:47:33 PM PST 24
Peak memory 194120 kb
Host smart-7e8cf7da-2381-4fca-b12e-49a2fc59e05e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545839140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.545839140
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.607029783
Short name T108
Test name
Test status
Simulation time 175667719926 ps
CPU time 162.4 seconds
Started Feb 21 12:43:28 PM PST 24
Finished Feb 21 12:46:11 PM PST 24
Peak memory 194384 kb
Host smart-e6e323ba-f22a-4cf1-b52b-0ea066a0591a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607029783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.607029783
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.222663669
Short name T187
Test name
Test status
Simulation time 94681885868 ps
CPU time 149.24 seconds
Started Feb 21 12:43:17 PM PST 24
Finished Feb 21 12:45:47 PM PST 24
Peak memory 190856 kb
Host smart-852bb55d-bec2-42dd-aa6d-91618d1f2114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222663669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.222663669
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.1153983002
Short name T111
Test name
Test status
Simulation time 679815316344 ps
CPU time 390.08 seconds
Started Feb 21 12:43:43 PM PST 24
Finished Feb 21 12:50:16 PM PST 24
Peak memory 191008 kb
Host smart-1372fe24-a421-4a20-bdf1-a6c25f6c71c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153983002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1153983002
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.1252965317
Short name T225
Test name
Test status
Simulation time 299059167228 ps
CPU time 325 seconds
Started Feb 21 12:43:54 PM PST 24
Finished Feb 21 12:49:21 PM PST 24
Peak memory 191168 kb
Host smart-d028ce33-1861-4bf0-a28e-9332e952375f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252965317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1252965317
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1101914436
Short name T83
Test name
Test status
Simulation time 850942353 ps
CPU time 3.74 seconds
Started Feb 21 12:34:36 PM PST 24
Finished Feb 21 12:34:40 PM PST 24
Peak memory 190744 kb
Host smart-7385c8c1-ff72-4870-8223-777fb843c9b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101914436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.1101914436
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.94080025
Short name T264
Test name
Test status
Simulation time 474540541357 ps
CPU time 815.12 seconds
Started Feb 21 12:42:47 PM PST 24
Finished Feb 21 12:56:22 PM PST 24
Peak memory 182560 kb
Host smart-34ad5924-335a-4a22-abaa-39cdcc36938c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94080025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.rv_timer_cfg_update_on_fly.94080025
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/126.rv_timer_random.4009592588
Short name T150
Test name
Test status
Simulation time 210795661889 ps
CPU time 367.02 seconds
Started Feb 21 12:43:37 PM PST 24
Finished Feb 21 12:49:45 PM PST 24
Peak memory 190972 kb
Host smart-2c5f5eb6-de16-424d-8ee6-30ad5f89b162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009592588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.4009592588
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2773097399
Short name T161
Test name
Test status
Simulation time 321757064488 ps
CPU time 594.76 seconds
Started Feb 21 12:43:52 PM PST 24
Finished Feb 21 12:53:50 PM PST 24
Peak memory 190940 kb
Host smart-6548b1a7-d086-453a-b327-f59d1db87140
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773097399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2773097399
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.1434090729
Short name T246
Test name
Test status
Simulation time 374748838971 ps
CPU time 1220.91 seconds
Started Feb 21 12:43:16 PM PST 24
Finished Feb 21 01:03:38 PM PST 24
Peak memory 190928 kb
Host smart-df76795d-bb34-4093-a22f-bc90319c8329
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434090729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1434090729
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.925637624
Short name T132
Test name
Test status
Simulation time 351625104847 ps
CPU time 359.03 seconds
Started Feb 21 12:43:46 PM PST 24
Finished Feb 21 12:49:50 PM PST 24
Peak memory 194172 kb
Host smart-525dd839-4733-4e17-8a30-96e3aec9b1cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925637624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.925637624
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.1813575476
Short name T191
Test name
Test status
Simulation time 348726776451 ps
CPU time 381.59 seconds
Started Feb 21 12:43:47 PM PST 24
Finished Feb 21 12:50:13 PM PST 24
Peak memory 190944 kb
Host smart-683932db-0531-47b8-93c9-bd112977440e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813575476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1813575476
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.575618379
Short name T240
Test name
Test status
Simulation time 135069814658 ps
CPU time 206.33 seconds
Started Feb 21 12:44:01 PM PST 24
Finished Feb 21 12:47:27 PM PST 24
Peak memory 190972 kb
Host smart-c613cd54-141a-41ad-a6cb-da78e3d4ce08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575618379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.575618379
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.3106687005
Short name T131
Test name
Test status
Simulation time 118543203378 ps
CPU time 562.5 seconds
Started Feb 21 12:43:19 PM PST 24
Finished Feb 21 12:52:42 PM PST 24
Peak memory 190944 kb
Host smart-dc9a2962-cb71-4213-b26d-4de47a5bb541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106687005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3106687005
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2343110134
Short name T200
Test name
Test status
Simulation time 1012027892834 ps
CPU time 415.42 seconds
Started Feb 21 12:43:10 PM PST 24
Finished Feb 21 12:50:06 PM PST 24
Peak memory 190852 kb
Host smart-f1469b4f-112e-40f0-8f4b-3ff003b15f89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343110134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2343110134
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.665641778
Short name T171
Test name
Test status
Simulation time 194852901028 ps
CPU time 629.72 seconds
Started Feb 21 12:43:21 PM PST 24
Finished Feb 21 12:53:51 PM PST 24
Peak memory 190952 kb
Host smart-557590c3-3e0a-4e71-9c49-7da7530af7d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665641778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.665641778
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2369373592
Short name T325
Test name
Test status
Simulation time 438059924079 ps
CPU time 1177.47 seconds
Started Feb 21 12:43:03 PM PST 24
Finished Feb 21 01:02:41 PM PST 24
Peak memory 190980 kb
Host smart-ad6a5c3a-590f-4472-a1c6-4609633e3125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369373592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2369373592
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/77.rv_timer_random.4230262662
Short name T207
Test name
Test status
Simulation time 293680780828 ps
CPU time 274.6 seconds
Started Feb 21 12:43:12 PM PST 24
Finished Feb 21 12:47:47 PM PST 24
Peak memory 190916 kb
Host smart-ff37f9d5-b9e7-407a-9d17-6369883c352d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230262662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.4230262662
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/100.rv_timer_random.3292166207
Short name T164
Test name
Test status
Simulation time 75465439177 ps
CPU time 182.62 seconds
Started Feb 21 12:43:08 PM PST 24
Finished Feb 21 12:46:11 PM PST 24
Peak memory 190956 kb
Host smart-f2fcdc03-c7bd-4f52-9f39-41e847df8c87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292166207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3292166207
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.3237483491
Short name T278
Test name
Test status
Simulation time 210734954925 ps
CPU time 263.8 seconds
Started Feb 21 12:43:31 PM PST 24
Finished Feb 21 12:47:55 PM PST 24
Peak memory 190972 kb
Host smart-d1662a52-ec2f-4428-843d-1a347cba4ae4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237483491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3237483491
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.3994923829
Short name T147
Test name
Test status
Simulation time 460900127537 ps
CPU time 215.18 seconds
Started Feb 21 12:43:22 PM PST 24
Finished Feb 21 12:46:58 PM PST 24
Peak memory 190960 kb
Host smart-8fcb1aed-3c66-4d1d-8564-8d66ebac9e29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994923829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3994923829
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3450531733
Short name T158
Test name
Test status
Simulation time 528855579473 ps
CPU time 288.57 seconds
Started Feb 21 12:42:37 PM PST 24
Finished Feb 21 12:47:27 PM PST 24
Peak memory 182756 kb
Host smart-cc98bde2-8dcc-4f76-bdf1-971d7d649631
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450531733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.3450531733
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_random.474806353
Short name T154
Test name
Test status
Simulation time 146549921621 ps
CPU time 670.81 seconds
Started Feb 21 12:42:15 PM PST 24
Finished Feb 21 12:53:27 PM PST 24
Peak memory 190796 kb
Host smart-7d7e8666-9f7a-4ac2-985d-5e95b024a227
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474806353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.474806353
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random.2704017324
Short name T138
Test name
Test status
Simulation time 123111607240 ps
CPU time 439.57 seconds
Started Feb 21 12:42:38 PM PST 24
Finished Feb 21 12:49:59 PM PST 24
Peak memory 190816 kb
Host smart-36d1bf36-210b-4fd2-9c50-0b9978d679d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704017324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2704017324
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.3308088175
Short name T221
Test name
Test status
Simulation time 1350776726534 ps
CPU time 755.11 seconds
Started Feb 21 12:43:07 PM PST 24
Finished Feb 21 12:55:43 PM PST 24
Peak memory 194204 kb
Host smart-2fa5cdb3-573e-4c96-9791-7a68b6b61a47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308088175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.3308088175
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_random.2592601422
Short name T251
Test name
Test status
Simulation time 1166975946145 ps
CPU time 457.81 seconds
Started Feb 21 12:43:10 PM PST 24
Finished Feb 21 12:50:48 PM PST 24
Peak memory 190876 kb
Host smart-a91591b5-3e05-475d-b760-ccbca8b3cb35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592601422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2592601422
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3996052884
Short name T133
Test name
Test status
Simulation time 469430321786 ps
CPU time 212.92 seconds
Started Feb 21 12:43:04 PM PST 24
Finished Feb 21 12:46:37 PM PST 24
Peak memory 195300 kb
Host smart-1ffdbfca-d144-4ae0-8144-1c0598f1a7ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996052884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3996052884
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1006835595
Short name T41
Test name
Test status
Simulation time 103227877636 ps
CPU time 167.43 seconds
Started Feb 21 12:42:59 PM PST 24
Finished Feb 21 12:45:47 PM PST 24
Peak memory 182776 kb
Host smart-deff878c-aed4-4798-8362-631703e3482a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006835595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1006835595
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.708004242
Short name T73
Test name
Test status
Simulation time 39990889 ps
CPU time 0.62 seconds
Started Feb 21 12:34:10 PM PST 24
Finished Feb 21 12:34:11 PM PST 24
Peak memory 191624 kb
Host smart-08487cd9-509e-4b0e-b315-bc18fc67f963
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708004242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.708004242
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.550605517
Short name T91
Test name
Test status
Simulation time 119519052 ps
CPU time 1.4 seconds
Started Feb 21 12:34:47 PM PST 24
Finished Feb 21 12:34:50 PM PST 24
Peak memory 194828 kb
Host smart-288fc321-7b3f-4179-adb5-ee0937e0e626
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550605517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.550605517
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3410707560
Short name T355
Test name
Test status
Simulation time 133515978239 ps
CPU time 34.39 seconds
Started Feb 21 12:42:16 PM PST 24
Finished Feb 21 12:42:56 PM PST 24
Peak memory 191960 kb
Host smart-50be0ea7-592a-43cb-b82a-e8de5e448cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410707560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3410707560
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.1642574900
Short name T344
Test name
Test status
Simulation time 2461313044768 ps
CPU time 510.64 seconds
Started Feb 21 12:43:52 PM PST 24
Finished Feb 21 12:52:26 PM PST 24
Peak memory 191184 kb
Host smart-b7c41005-c1ef-4e74-84b4-971ce41791e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642574900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1642574900
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.3475242873
Short name T98
Test name
Test status
Simulation time 127883247227 ps
CPU time 246.9 seconds
Started Feb 21 12:43:23 PM PST 24
Finished Feb 21 12:47:30 PM PST 24
Peak memory 193408 kb
Host smart-6add8d2f-af4a-4c2b-953f-ebb9af5410bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475242873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3475242873
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.2157442523
Short name T259
Test name
Test status
Simulation time 371788780859 ps
CPU time 344.96 seconds
Started Feb 21 12:43:21 PM PST 24
Finished Feb 21 12:49:06 PM PST 24
Peak memory 190980 kb
Host smart-b91c1bf1-2cd7-4528-add6-23cb13202d74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157442523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2157442523
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.3315969099
Short name T292
Test name
Test status
Simulation time 117888430058 ps
CPU time 403.26 seconds
Started Feb 21 12:43:28 PM PST 24
Finished Feb 21 12:50:12 PM PST 24
Peak memory 190968 kb
Host smart-e96b7450-dbf8-4575-9674-5a0e762ae445
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315969099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3315969099
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.1899932448
Short name T245
Test name
Test status
Simulation time 125946742979 ps
CPU time 354.85 seconds
Started Feb 21 12:43:46 PM PST 24
Finished Feb 21 12:49:45 PM PST 24
Peak memory 190816 kb
Host smart-563962fc-f886-4c93-86f0-e2b47812845b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899932448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1899932448
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2035050809
Short name T237
Test name
Test status
Simulation time 1114860028537 ps
CPU time 511.34 seconds
Started Feb 21 12:42:26 PM PST 24
Finished Feb 21 12:50:58 PM PST 24
Peak memory 182784 kb
Host smart-8e8567f9-a6a1-44af-8a5f-73df642e1da3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035050809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2035050809
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1748427939
Short name T261
Test name
Test status
Simulation time 1128106316783 ps
CPU time 566.98 seconds
Started Feb 21 12:43:00 PM PST 24
Finished Feb 21 12:52:28 PM PST 24
Peak memory 182416 kb
Host smart-be3f31bb-71e0-42a3-8187-3d5a30607233
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748427939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1748427939
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2375544052
Short name T116
Test name
Test status
Simulation time 363188665475 ps
CPU time 604.82 seconds
Started Feb 21 12:43:06 PM PST 24
Finished Feb 21 12:53:12 PM PST 24
Peak memory 182764 kb
Host smart-3cc81e4a-29d2-4091-ad9f-11393107ba31
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375544052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.2375544052
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_random.1008694286
Short name T350
Test name
Test status
Simulation time 1775081977478 ps
CPU time 403.76 seconds
Started Feb 21 12:42:35 PM PST 24
Finished Feb 21 12:49:20 PM PST 24
Peak memory 190876 kb
Host smart-6f413b22-fefa-4a10-8ae4-760b4c27f868
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008694286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.1008694286
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random.2246761089
Short name T181
Test name
Test status
Simulation time 141891964716 ps
CPU time 250.5 seconds
Started Feb 21 12:43:17 PM PST 24
Finished Feb 21 12:47:28 PM PST 24
Peak memory 194344 kb
Host smart-809723e2-854c-466d-a911-04a4f07900a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246761089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2246761089
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.441836897
Short name T180
Test name
Test status
Simulation time 1051027677770 ps
CPU time 875.39 seconds
Started Feb 21 12:43:04 PM PST 24
Finished Feb 21 12:57:40 PM PST 24
Peak memory 190908 kb
Host smart-30060825-8f19-4adf-8fbf-6f2ae25b4f0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441836897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
441836897
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/91.rv_timer_random.4093424811
Short name T168
Test name
Test status
Simulation time 1441092417671 ps
CPU time 387.59 seconds
Started Feb 21 12:43:29 PM PST 24
Finished Feb 21 12:49:57 PM PST 24
Peak memory 190972 kb
Host smart-46c04a68-3d03-4995-aa9d-32bac3952ce7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093424811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.4093424811
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.967375023
Short name T227
Test name
Test status
Simulation time 159713691534 ps
CPU time 250.16 seconds
Started Feb 21 12:42:33 PM PST 24
Finished Feb 21 12:46:43 PM PST 24
Peak memory 182676 kb
Host smart-bab29369-e155-4ece-8652-ef17bcf3eb09
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967375023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.rv_timer_cfg_update_on_fly.967375023
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.543813802
Short name T343
Test name
Test status
Simulation time 1990996474082 ps
CPU time 474.4 seconds
Started Feb 21 12:42:32 PM PST 24
Finished Feb 21 12:50:27 PM PST 24
Peak memory 190996 kb
Host smart-fd86457e-bf13-485c-b003-53e166237938
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543813802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.543813802
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.495543535
Short name T277
Test name
Test status
Simulation time 966575160023 ps
CPU time 542.89 seconds
Started Feb 21 12:42:47 PM PST 24
Finished Feb 21 12:51:50 PM PST 24
Peak memory 182676 kb
Host smart-ff100adb-f6cb-42a4-99a6-8ba16c39dac8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495543535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rv_timer_cfg_update_on_fly.495543535
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_random.514847554
Short name T6
Test name
Test status
Simulation time 478708229011 ps
CPU time 488.19 seconds
Started Feb 21 12:42:37 PM PST 24
Finished Feb 21 12:50:46 PM PST 24
Peak memory 190796 kb
Host smart-c2d6bc23-cdf1-42f0-95ac-624703929129
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514847554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.514847554
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.3939453322
Short name T315
Test name
Test status
Simulation time 32378961685 ps
CPU time 79.63 seconds
Started Feb 21 12:43:32 PM PST 24
Finished Feb 21 12:44:52 PM PST 24
Peak memory 182764 kb
Host smart-9b1375e4-44c3-42da-976a-7cff72b2bd6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939453322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3939453322
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.794820778
Short name T241
Test name
Test status
Simulation time 225232287158 ps
CPU time 454.12 seconds
Started Feb 21 12:43:32 PM PST 24
Finished Feb 21 12:51:07 PM PST 24
Peak memory 194296 kb
Host smart-ff4032d2-2f5b-4be7-a7a4-8dab5817fbdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794820778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.794820778
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.3747300739
Short name T117
Test name
Test status
Simulation time 171672404863 ps
CPU time 625.26 seconds
Started Feb 21 12:43:56 PM PST 24
Finished Feb 21 12:54:22 PM PST 24
Peak memory 191184 kb
Host smart-796df498-9392-4481-aef0-efe61507789f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747300739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3747300739
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.31777244
Short name T314
Test name
Test status
Simulation time 53776654283 ps
CPU time 935.21 seconds
Started Feb 21 12:43:42 PM PST 24
Finished Feb 21 12:59:20 PM PST 24
Peak memory 182808 kb
Host smart-787d64bc-a6d7-4d0c-b196-515a54519f2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31777244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.31777244
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2433159275
Short name T322
Test name
Test status
Simulation time 37845590030 ps
CPU time 19.82 seconds
Started Feb 21 12:43:47 PM PST 24
Finished Feb 21 12:44:11 PM PST 24
Peak memory 182652 kb
Host smart-40140af7-0a64-423c-8891-2984a9dac949
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433159275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2433159275
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1134766322
Short name T342
Test name
Test status
Simulation time 15307522305 ps
CPU time 7.81 seconds
Started Feb 21 12:42:36 PM PST 24
Finished Feb 21 12:42:46 PM PST 24
Peak memory 182688 kb
Host smart-da7b8608-a285-4ea3-ba7a-4ff57cd30e61
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134766322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1134766322
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/130.rv_timer_random.2115969315
Short name T301
Test name
Test status
Simulation time 740475288204 ps
CPU time 463.04 seconds
Started Feb 21 12:43:09 PM PST 24
Finished Feb 21 12:50:52 PM PST 24
Peak memory 190852 kb
Host smart-268f84f3-990d-4cc3-83a2-dae5e43c0331
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115969315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2115969315
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.1379982163
Short name T339
Test name
Test status
Simulation time 267946337902 ps
CPU time 240.75 seconds
Started Feb 21 12:43:10 PM PST 24
Finished Feb 21 12:47:11 PM PST 24
Peak memory 190852 kb
Host smart-aad3ee33-1b90-453d-9ae9-6a45c7580f71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379982163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1379982163
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.2334909945
Short name T194
Test name
Test status
Simulation time 177566552095 ps
CPU time 459.37 seconds
Started Feb 21 12:43:25 PM PST 24
Finished Feb 21 12:51:05 PM PST 24
Peak memory 190932 kb
Host smart-0b97101a-e8c1-4d0d-9edf-3231a999411e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334909945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2334909945
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3490950113
Short name T220
Test name
Test status
Simulation time 1538731095152 ps
CPU time 766.37 seconds
Started Feb 21 12:43:29 PM PST 24
Finished Feb 21 12:56:16 PM PST 24
Peak memory 190968 kb
Host smart-7f4f58b5-ee06-4b2b-aa62-91df8f673813
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490950113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3490950113
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1598954693
Short name T231
Test name
Test status
Simulation time 213169311839 ps
CPU time 486.23 seconds
Started Feb 21 12:43:06 PM PST 24
Finished Feb 21 12:51:13 PM PST 24
Peak memory 193408 kb
Host smart-791d2553-288d-427e-9881-3238d289a8d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598954693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1598954693
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.9286679
Short name T199
Test name
Test status
Simulation time 153247987055 ps
CPU time 444.08 seconds
Started Feb 21 12:43:16 PM PST 24
Finished Feb 21 12:50:41 PM PST 24
Peak memory 190944 kb
Host smart-d46fe179-fa43-46ee-b23d-ca79454d729e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9286679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.9286679
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.3959392184
Short name T4
Test name
Test status
Simulation time 196909454906 ps
CPU time 76.54 seconds
Started Feb 21 12:43:20 PM PST 24
Finished Feb 21 12:44:37 PM PST 24
Peak memory 190948 kb
Host smart-5e9f9c80-9cbd-4f1b-bb03-27a695289b46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959392184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3959392184
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.91052796
Short name T285
Test name
Test status
Simulation time 51353536679 ps
CPU time 84.83 seconds
Started Feb 21 12:43:45 PM PST 24
Finished Feb 21 12:45:13 PM PST 24
Peak memory 190856 kb
Host smart-c26359ad-4bdc-46fc-a8d9-468f0f385cfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91052796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.91052796
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.4051844414
Short name T257
Test name
Test status
Simulation time 316815010726 ps
CPU time 442.34 seconds
Started Feb 21 12:43:17 PM PST 24
Finished Feb 21 12:50:40 PM PST 24
Peak memory 182756 kb
Host smart-ee2108c0-a12f-46cc-945b-c0a541ac5de6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051844414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.4051844414
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.69626749
Short name T275
Test name
Test status
Simulation time 525589290998 ps
CPU time 1710.21 seconds
Started Feb 21 12:42:45 PM PST 24
Finished Feb 21 01:11:16 PM PST 24
Peak memory 191000 kb
Host smart-f03975eb-b28a-42ac-8ac4-787a2c58dd94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69626749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.69626749
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1085116157
Short name T188
Test name
Test status
Simulation time 13408497597 ps
CPU time 22.93 seconds
Started Feb 21 12:42:40 PM PST 24
Finished Feb 21 12:43:08 PM PST 24
Peak memory 182796 kb
Host smart-b1a1a7b6-1700-4305-9221-37d67374b996
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085116157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.1085116157
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.4019762553
Short name T269
Test name
Test status
Simulation time 664023239803 ps
CPU time 612.85 seconds
Started Feb 21 12:43:00 PM PST 24
Finished Feb 21 12:53:14 PM PST 24
Peak memory 182800 kb
Host smart-b9c5caa0-d7c9-4b21-ad8a-38b4ccd9c184
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019762553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.4019762553
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.530047460
Short name T205
Test name
Test status
Simulation time 686143455032 ps
CPU time 584.97 seconds
Started Feb 21 12:43:06 PM PST 24
Finished Feb 21 12:52:52 PM PST 24
Peak memory 190940 kb
Host smart-98af2636-cea5-4e61-8bb0-3ba7fa5c2785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530047460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
530047460
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.827031574
Short name T233
Test name
Test status
Simulation time 422418605852 ps
CPU time 746.18 seconds
Started Feb 21 12:43:08 PM PST 24
Finished Feb 21 12:55:34 PM PST 24
Peak memory 182672 kb
Host smart-90274d22-ed33-4083-8067-e5924f1b5d85
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827031574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.827031574
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_random.2297764166
Short name T125
Test name
Test status
Simulation time 147635180687 ps
CPU time 618.26 seconds
Started Feb 21 12:42:54 PM PST 24
Finished Feb 21 12:53:14 PM PST 24
Peak memory 190956 kb
Host smart-e7a80e74-8471-4496-b972-7d17e5cb6254
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297764166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2297764166
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.134894095
Short name T335
Test name
Test status
Simulation time 123327224420 ps
CPU time 443.82 seconds
Started Feb 21 12:43:40 PM PST 24
Finished Feb 21 12:51:04 PM PST 24
Peak memory 193204 kb
Host smart-aeb28c0b-a09b-4aa9-a207-d41dc6e89689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134894095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.134894095
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.1745269114
Short name T255
Test name
Test status
Simulation time 631456688983 ps
CPU time 709.25 seconds
Started Feb 21 12:43:11 PM PST 24
Finished Feb 21 12:55:01 PM PST 24
Peak memory 190864 kb
Host smart-a3d43d26-8de7-4779-9de9-a2f2af888021
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745269114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1745269114
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2667377741
Short name T471
Test name
Test status
Simulation time 23414067 ps
CPU time 0.68 seconds
Started Feb 21 12:34:16 PM PST 24
Finished Feb 21 12:34:20 PM PST 24
Peak memory 191796 kb
Host smart-56113be7-6ea4-4fcd-b56c-055a516553c1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667377741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.2667377741
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3418768249
Short name T27
Test name
Test status
Simulation time 18251549 ps
CPU time 0.57 seconds
Started Feb 21 12:34:07 PM PST 24
Finished Feb 21 12:34:09 PM PST 24
Peak memory 182460 kb
Host smart-8a9357c8-a115-4cea-9974-63006eec20b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418768249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.3418768249
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3125736163
Short name T509
Test name
Test status
Simulation time 27521678 ps
CPU time 0.76 seconds
Started Feb 21 12:34:36 PM PST 24
Finished Feb 21 12:34:39 PM PST 24
Peak memory 195416 kb
Host smart-1947d963-cccd-45bb-8b59-f08409d971a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125736163 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3125736163
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3162312534
Short name T502
Test name
Test status
Simulation time 93315409 ps
CPU time 0.54 seconds
Started Feb 21 12:34:18 PM PST 24
Finished Feb 21 12:34:20 PM PST 24
Peak memory 181996 kb
Host smart-30ca6587-f071-4020-b43f-4089fbe8a45c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162312534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3162312534
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1022887975
Short name T453
Test name
Test status
Simulation time 50795461 ps
CPU time 0.56 seconds
Started Feb 21 12:34:27 PM PST 24
Finished Feb 21 12:34:33 PM PST 24
Peak memory 182216 kb
Host smart-9d60ebf4-2ffd-41ab-8745-2a8afe71acb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022887975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1022887975
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2954419888
Short name T480
Test name
Test status
Simulation time 172937244 ps
CPU time 1.73 seconds
Started Feb 21 12:34:14 PM PST 24
Finished Feb 21 12:34:20 PM PST 24
Peak memory 197176 kb
Host smart-66dd06cc-4d4d-4515-a665-1a37cc5fe752
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954419888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2954419888
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2927693565
Short name T494
Test name
Test status
Simulation time 94730064 ps
CPU time 1.29 seconds
Started Feb 21 12:34:18 PM PST 24
Finished Feb 21 12:34:20 PM PST 24
Peak memory 194756 kb
Host smart-a1aa943b-5326-4a20-9370-9ca874259068
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927693565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2927693565
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3623001568
Short name T495
Test name
Test status
Simulation time 121076216 ps
CPU time 0.84 seconds
Started Feb 21 12:34:23 PM PST 24
Finished Feb 21 12:34:25 PM PST 24
Peak memory 191508 kb
Host smart-3a6b6418-8649-472e-91cc-ac57d8fe74ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623001568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3623001568
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3542604501
Short name T74
Test name
Test status
Simulation time 350446710 ps
CPU time 3.15 seconds
Started Feb 21 12:34:14 PM PST 24
Finished Feb 21 12:34:18 PM PST 24
Peak memory 193108 kb
Host smart-829a620d-5ad4-45b9-bc35-1d9d8487099d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542604501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.3542604501
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2381806516
Short name T554
Test name
Test status
Simulation time 15884285 ps
CPU time 0.55 seconds
Started Feb 21 12:34:21 PM PST 24
Finished Feb 21 12:34:22 PM PST 24
Peak memory 182544 kb
Host smart-2057ce46-f4f5-4260-8c9c-4916e57364e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381806516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.2381806516
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.929772957
Short name T493
Test name
Test status
Simulation time 28543748 ps
CPU time 0.87 seconds
Started Feb 21 12:34:16 PM PST 24
Finished Feb 21 12:34:20 PM PST 24
Peak memory 196688 kb
Host smart-7a2e1250-4c22-4f72-a6e4-cc99b26e5975
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929772957 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.929772957
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3985534896
Short name T78
Test name
Test status
Simulation time 12499397 ps
CPU time 0.54 seconds
Started Feb 21 12:34:21 PM PST 24
Finished Feb 21 12:34:22 PM PST 24
Peak memory 182520 kb
Host smart-53e2149b-5c7a-4a00-b728-0d04d4af9ef2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985534896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3985534896
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3760506983
Short name T491
Test name
Test status
Simulation time 39839439 ps
CPU time 0.56 seconds
Started Feb 21 12:34:19 PM PST 24
Finished Feb 21 12:34:20 PM PST 24
Peak memory 182156 kb
Host smart-6dbb39af-3712-46ba-91fa-c4435bc664a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760506983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3760506983
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2769072861
Short name T72
Test name
Test status
Simulation time 138274344 ps
CPU time 0.73 seconds
Started Feb 21 12:34:17 PM PST 24
Finished Feb 21 12:34:20 PM PST 24
Peak memory 191372 kb
Host smart-d52dcb35-9d98-454d-95c4-8ddb1495e613
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769072861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2769072861
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3129482569
Short name T568
Test name
Test status
Simulation time 147791495 ps
CPU time 1.97 seconds
Started Feb 21 12:34:21 PM PST 24
Finished Feb 21 12:34:23 PM PST 24
Peak memory 197188 kb
Host smart-48c85b7d-021b-4200-8997-2aab85c9679f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129482569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3129482569
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2695757958
Short name T460
Test name
Test status
Simulation time 69021897 ps
CPU time 0.73 seconds
Started Feb 21 12:34:47 PM PST 24
Finished Feb 21 12:34:50 PM PST 24
Peak memory 194528 kb
Host smart-bcc58c30-c272-44d4-b816-045b86d7609f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695757958 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2695757958
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1844215629
Short name T77
Test name
Test status
Simulation time 14643289 ps
CPU time 0.58 seconds
Started Feb 21 12:34:47 PM PST 24
Finished Feb 21 12:34:49 PM PST 24
Peak memory 182404 kb
Host smart-b6b59e2e-4c8b-495d-aa78-df356e3b7f5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844215629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1844215629
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.119087263
Short name T486
Test name
Test status
Simulation time 190671487 ps
CPU time 0.54 seconds
Started Feb 21 12:34:37 PM PST 24
Finished Feb 21 12:34:38 PM PST 24
Peak memory 182052 kb
Host smart-003de1bd-aeab-417e-8e42-69f0463c4f62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119087263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.119087263
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4049784120
Short name T85
Test name
Test status
Simulation time 33287435 ps
CPU time 0.62 seconds
Started Feb 21 12:34:14 PM PST 24
Finished Feb 21 12:34:15 PM PST 24
Peak memory 191444 kb
Host smart-8cc88ae5-54c4-4a17-a97b-1094c9be43b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049784120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.4049784120
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.4065615638
Short name T463
Test name
Test status
Simulation time 109257716 ps
CPU time 1.26 seconds
Started Feb 21 12:34:52 PM PST 24
Finished Feb 21 12:34:59 PM PST 24
Peak memory 196988 kb
Host smart-cae24266-ac05-4d6d-8cc1-06ed4a876275
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065615638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.4065615638
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1652678921
Short name T525
Test name
Test status
Simulation time 540382499 ps
CPU time 1.29 seconds
Started Feb 21 12:34:32 PM PST 24
Finished Feb 21 12:34:34 PM PST 24
Peak memory 182760 kb
Host smart-84078171-2482-4906-8f72-1bb67efaa0e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652678921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1652678921
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1458232149
Short name T457
Test name
Test status
Simulation time 18839716 ps
CPU time 0.65 seconds
Started Feb 21 12:34:36 PM PST 24
Finished Feb 21 12:34:39 PM PST 24
Peak memory 193640 kb
Host smart-dcc3c177-9f0a-4ee7-902a-045178b6111a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458232149 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1458232149
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.4180272640
Short name T75
Test name
Test status
Simulation time 15408150 ps
CPU time 0.58 seconds
Started Feb 21 12:34:35 PM PST 24
Finished Feb 21 12:34:36 PM PST 24
Peak memory 182464 kb
Host smart-77a5ba1e-7ee1-41ad-9e3e-e4cef21d61c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180272640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.4180272640
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1197296972
Short name T572
Test name
Test status
Simulation time 43909219 ps
CPU time 0.57 seconds
Started Feb 21 12:34:36 PM PST 24
Finished Feb 21 12:34:39 PM PST 24
Peak memory 182176 kb
Host smart-7ef5a567-690a-4a55-8b46-15623c783127
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197296972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.1197296972
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.4131396753
Short name T88
Test name
Test status
Simulation time 75935797 ps
CPU time 0.59 seconds
Started Feb 21 12:34:41 PM PST 24
Finished Feb 21 12:34:42 PM PST 24
Peak memory 191652 kb
Host smart-de78fc2d-04fe-4081-af79-8af04c0339ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131396753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.4131396753
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1824836638
Short name T549
Test name
Test status
Simulation time 39126102 ps
CPU time 1.78 seconds
Started Feb 21 12:34:52 PM PST 24
Finished Feb 21 12:34:58 PM PST 24
Peak memory 196972 kb
Host smart-808d67ac-3668-400d-8316-3dfc3d735671
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824836638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1824836638
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3869658928
Short name T575
Test name
Test status
Simulation time 147543419 ps
CPU time 1.35 seconds
Started Feb 21 12:34:42 PM PST 24
Finished Feb 21 12:34:44 PM PST 24
Peak memory 194748 kb
Host smart-c45a1a6f-adef-45a0-b90d-b9ec852a9668
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869658928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3869658928
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2064907346
Short name T580
Test name
Test status
Simulation time 23122855 ps
CPU time 0.95 seconds
Started Feb 21 12:34:33 PM PST 24
Finished Feb 21 12:34:45 PM PST 24
Peak memory 196964 kb
Host smart-7d5c7cb6-ebc2-4151-9e42-1e5c85069496
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064907346 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2064907346
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1112930786
Short name T551
Test name
Test status
Simulation time 34119834 ps
CPU time 0.56 seconds
Started Feb 21 12:34:33 PM PST 24
Finished Feb 21 12:34:34 PM PST 24
Peak memory 182456 kb
Host smart-5fc11acd-7fce-4a5c-89ca-b62ee3088ee9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112930786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1112930786
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1808395564
Short name T536
Test name
Test status
Simulation time 13938341 ps
CPU time 0.54 seconds
Started Feb 21 12:34:44 PM PST 24
Finished Feb 21 12:34:45 PM PST 24
Peak memory 181600 kb
Host smart-271d945f-ccd1-4780-aadc-b8eae8977374
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808395564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1808395564
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3769594321
Short name T63
Test name
Test status
Simulation time 70034026 ps
CPU time 0.8 seconds
Started Feb 21 12:34:41 PM PST 24
Finished Feb 21 12:34:42 PM PST 24
Peak memory 192908 kb
Host smart-09b14a77-a98c-450e-a2b8-89adbd5a8ed4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769594321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3769594321
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.296443685
Short name T469
Test name
Test status
Simulation time 51008828 ps
CPU time 2.31 seconds
Started Feb 21 12:34:34 PM PST 24
Finished Feb 21 12:34:37 PM PST 24
Peak memory 197176 kb
Host smart-276b3779-dbf0-4534-a3d7-401fbf02ab84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296443685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.296443685
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3505719556
Short name T498
Test name
Test status
Simulation time 136587546 ps
CPU time 1.35 seconds
Started Feb 21 12:34:18 PM PST 24
Finished Feb 21 12:34:21 PM PST 24
Peak memory 194996 kb
Host smart-24286944-6a2e-455b-b9c0-c5008fbb07fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505719556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3505719556
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3048780542
Short name T466
Test name
Test status
Simulation time 110956772 ps
CPU time 0.62 seconds
Started Feb 21 12:34:21 PM PST 24
Finished Feb 21 12:34:22 PM PST 24
Peak memory 193500 kb
Host smart-a017486e-f567-421c-bb6c-fb46cb42fd62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048780542 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3048780542
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3065461019
Short name T516
Test name
Test status
Simulation time 15551745 ps
CPU time 0.58 seconds
Started Feb 21 12:34:43 PM PST 24
Finished Feb 21 12:34:45 PM PST 24
Peak memory 182420 kb
Host smart-da64f8f4-c5c4-4c46-9f3e-a9b16dd8c6ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065461019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3065461019
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2464687831
Short name T504
Test name
Test status
Simulation time 13499584 ps
CPU time 0.57 seconds
Started Feb 21 12:34:17 PM PST 24
Finished Feb 21 12:34:20 PM PST 24
Peak memory 182228 kb
Host smart-e0eebb7f-1ff7-4827-ae24-5513b707b2d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464687831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2464687831
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2482706407
Short name T518
Test name
Test status
Simulation time 351135297 ps
CPU time 0.76 seconds
Started Feb 21 12:34:41 PM PST 24
Finished Feb 21 12:34:43 PM PST 24
Peak memory 192964 kb
Host smart-6dd4cb73-2cbd-4894-8b23-0579a97de3ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482706407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2482706407
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3790592929
Short name T464
Test name
Test status
Simulation time 305332350 ps
CPU time 1.78 seconds
Started Feb 21 12:34:41 PM PST 24
Finished Feb 21 12:34:43 PM PST 24
Peak memory 197156 kb
Host smart-59f72af3-4391-4ddf-a35c-e305d1ca03c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790592929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3790592929
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3746538701
Short name T544
Test name
Test status
Simulation time 299278812 ps
CPU time 1.2 seconds
Started Feb 21 12:34:23 PM PST 24
Finished Feb 21 12:34:25 PM PST 24
Peak memory 194536 kb
Host smart-5fbfc050-6623-4a62-80de-c5b9bf04589d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746538701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3746538701
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3944060350
Short name T557
Test name
Test status
Simulation time 82672667 ps
CPU time 0.71 seconds
Started Feb 21 12:34:28 PM PST 24
Finished Feb 21 12:34:29 PM PST 24
Peak memory 194588 kb
Host smart-574c0d06-759c-4220-adeb-53649a04979b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944060350 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.3944060350
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2330481629
Short name T26
Test name
Test status
Simulation time 20241251 ps
CPU time 0.54 seconds
Started Feb 21 12:34:52 PM PST 24
Finished Feb 21 12:34:58 PM PST 24
Peak memory 182176 kb
Host smart-15530a8c-2cfd-4377-8c3f-2f548d772bce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330481629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2330481629
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1981540392
Short name T472
Test name
Test status
Simulation time 12669626 ps
CPU time 0.58 seconds
Started Feb 21 12:34:43 PM PST 24
Finished Feb 21 12:34:44 PM PST 24
Peak memory 182544 kb
Host smart-be231c1f-743c-498d-bd8d-04daf49aa591
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981540392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1981540392
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.264825409
Short name T523
Test name
Test status
Simulation time 120855165 ps
CPU time 0.68 seconds
Started Feb 21 12:34:33 PM PST 24
Finished Feb 21 12:34:34 PM PST 24
Peak memory 191232 kb
Host smart-3c5ddf81-a90a-47b0-96f4-e7b771d7b523
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264825409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.264825409
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2030972963
Short name T487
Test name
Test status
Simulation time 52221070 ps
CPU time 0.78 seconds
Started Feb 21 12:34:45 PM PST 24
Finished Feb 21 12:34:47 PM PST 24
Peak memory 190848 kb
Host smart-aa5e350d-aec7-4327-9d94-388844779647
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030972963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2030972963
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1945087629
Short name T558
Test name
Test status
Simulation time 76044619 ps
CPU time 0.99 seconds
Started Feb 21 12:34:14 PM PST 24
Finished Feb 21 12:34:25 PM PST 24
Peak memory 196932 kb
Host smart-a50d29e6-0e92-453d-8ec9-1ed46b144599
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945087629 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1945087629
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.689524670
Short name T81
Test name
Test status
Simulation time 16576929 ps
CPU time 0.57 seconds
Started Feb 21 12:34:18 PM PST 24
Finished Feb 21 12:34:20 PM PST 24
Peak memory 182472 kb
Host smart-b42b9dc4-8daf-4c85-b395-7aa6b54f145b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689524670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.689524670
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3222443447
Short name T560
Test name
Test status
Simulation time 49827809 ps
CPU time 0.53 seconds
Started Feb 21 12:34:25 PM PST 24
Finished Feb 21 12:34:26 PM PST 24
Peak memory 182224 kb
Host smart-5c948301-c7f6-4749-a47c-4669cc3f3c29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222443447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3222443447
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.903616020
Short name T565
Test name
Test status
Simulation time 88408136 ps
CPU time 0.71 seconds
Started Feb 21 12:34:13 PM PST 24
Finished Feb 21 12:34:15 PM PST 24
Peak memory 191264 kb
Host smart-7fca7012-68e1-4a56-9147-dc3877ea139f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903616020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.903616020
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1506467180
Short name T496
Test name
Test status
Simulation time 169308251 ps
CPU time 2.49 seconds
Started Feb 21 12:34:51 PM PST 24
Finished Feb 21 12:35:00 PM PST 24
Peak memory 197088 kb
Host smart-44bc6905-1054-4c0f-a0c3-6e85e87f7522
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506467180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1506467180
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2063255329
Short name T539
Test name
Test status
Simulation time 204466122 ps
CPU time 1.1 seconds
Started Feb 21 12:34:43 PM PST 24
Finished Feb 21 12:34:45 PM PST 24
Peak memory 182640 kb
Host smart-e64d835a-0732-4a40-9ba9-bb267e7a0e27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063255329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2063255329
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1937206533
Short name T492
Test name
Test status
Simulation time 178953746 ps
CPU time 0.81 seconds
Started Feb 21 12:34:25 PM PST 24
Finished Feb 21 12:34:27 PM PST 24
Peak memory 195220 kb
Host smart-c56896e0-c341-44bb-bd93-f93e54203752
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937206533 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.1937206533
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3719806650
Short name T462
Test name
Test status
Simulation time 36797994 ps
CPU time 0.56 seconds
Started Feb 21 12:34:56 PM PST 24
Finished Feb 21 12:34:59 PM PST 24
Peak memory 182548 kb
Host smart-5d97d01b-6f3d-4963-bbd6-832cef6d7739
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719806650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3719806650
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2043031852
Short name T573
Test name
Test status
Simulation time 11824546 ps
CPU time 0.54 seconds
Started Feb 21 12:34:21 PM PST 24
Finished Feb 21 12:34:22 PM PST 24
Peak memory 182304 kb
Host smart-a07a7c62-d6ad-4be2-801a-f19c014972ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043031852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2043031852
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1984291479
Short name T517
Test name
Test status
Simulation time 143403446 ps
CPU time 0.79 seconds
Started Feb 21 12:34:27 PM PST 24
Finished Feb 21 12:34:29 PM PST 24
Peak memory 193032 kb
Host smart-d650e45b-a614-4047-b899-10d7359a2cbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984291479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1984291479
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1401132118
Short name T548
Test name
Test status
Simulation time 110905755 ps
CPU time 0.9 seconds
Started Feb 21 12:34:45 PM PST 24
Finished Feb 21 12:34:47 PM PST 24
Peak memory 196584 kb
Host smart-3ac81e1e-d758-44ec-b7d5-3c3889f0102c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401132118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1401132118
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.686274062
Short name T22
Test name
Test status
Simulation time 1668739449 ps
CPU time 1.3 seconds
Started Feb 21 12:34:37 PM PST 24
Finished Feb 21 12:34:39 PM PST 24
Peak memory 194816 kb
Host smart-5851a9b3-fa4b-43f1-93f4-0038edf6d82a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686274062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.686274062
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1512742338
Short name T569
Test name
Test status
Simulation time 85238478 ps
CPU time 0.7 seconds
Started Feb 21 12:34:50 PM PST 24
Finished Feb 21 12:34:58 PM PST 24
Peak memory 194296 kb
Host smart-4d33fdc6-2d55-40c6-b1ff-cc670b9ab5c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512742338 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1512742338
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1035486452
Short name T552
Test name
Test status
Simulation time 21207314 ps
CPU time 0.57 seconds
Started Feb 21 12:34:50 PM PST 24
Finished Feb 21 12:34:57 PM PST 24
Peak memory 182404 kb
Host smart-a831a27a-0fdb-43f5-af32-a1577136858f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035486452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1035486452
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3185298414
Short name T559
Test name
Test status
Simulation time 77801404 ps
CPU time 0.53 seconds
Started Feb 21 12:34:37 PM PST 24
Finished Feb 21 12:34:39 PM PST 24
Peak memory 182320 kb
Host smart-9ce2ed78-2b4b-4717-84a5-b1e39dee727f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185298414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3185298414
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1950209865
Short name T579
Test name
Test status
Simulation time 84663707 ps
CPU time 0.62 seconds
Started Feb 21 12:34:39 PM PST 24
Finished Feb 21 12:34:42 PM PST 24
Peak memory 191656 kb
Host smart-717900ec-d458-41b2-8be1-9befcfb47c97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950209865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.1950209865
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1482760373
Short name T459
Test name
Test status
Simulation time 171612125 ps
CPU time 1.77 seconds
Started Feb 21 12:34:26 PM PST 24
Finished Feb 21 12:34:29 PM PST 24
Peak memory 197192 kb
Host smart-3239cd4f-1677-47fc-bf37-fd2a71d5a88d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482760373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1482760373
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3572710181
Short name T23
Test name
Test status
Simulation time 431937752 ps
CPU time 1.32 seconds
Started Feb 21 12:34:36 PM PST 24
Finished Feb 21 12:34:39 PM PST 24
Peak memory 194936 kb
Host smart-2c864493-e543-4978-840a-92ee968f6bb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572710181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3572710181
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.93203000
Short name T479
Test name
Test status
Simulation time 265547746 ps
CPU time 0.89 seconds
Started Feb 21 12:34:38 PM PST 24
Finished Feb 21 12:34:42 PM PST 24
Peak memory 196676 kb
Host smart-724777ed-1d92-43f9-a168-16942edb71e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93203000 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.93203000
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3854219335
Short name T574
Test name
Test status
Simulation time 15686956 ps
CPU time 0.61 seconds
Started Feb 21 12:34:46 PM PST 24
Finished Feb 21 12:34:49 PM PST 24
Peak memory 182404 kb
Host smart-4b138830-1081-4841-90f1-c27eea1937b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854219335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3854219335
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2288681263
Short name T562
Test name
Test status
Simulation time 33530775 ps
CPU time 0.54 seconds
Started Feb 21 12:34:38 PM PST 24
Finished Feb 21 12:34:47 PM PST 24
Peak memory 181696 kb
Host smart-cd586cf8-6d29-4ed4-a85e-f84d9af8c873
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288681263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2288681263
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1519738218
Short name T514
Test name
Test status
Simulation time 60693122 ps
CPU time 0.63 seconds
Started Feb 21 12:34:22 PM PST 24
Finished Feb 21 12:34:23 PM PST 24
Peak memory 191648 kb
Host smart-70d82dd4-83cb-4352-90ba-257adae663b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519738218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1519738218
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2472235570
Short name T474
Test name
Test status
Simulation time 129959263 ps
CPU time 2.32 seconds
Started Feb 21 12:34:46 PM PST 24
Finished Feb 21 12:34:58 PM PST 24
Peak memory 197144 kb
Host smart-5b59f205-98c6-4bfe-87e5-33eca3c729f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472235570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2472235570
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.442657601
Short name T561
Test name
Test status
Simulation time 75436484 ps
CPU time 1.1 seconds
Started Feb 21 12:34:37 PM PST 24
Finished Feb 21 12:34:39 PM PST 24
Peak memory 194776 kb
Host smart-85900398-20d8-4141-b81a-50d9c2beef40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442657601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_in
tg_err.442657601
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1386282320
Short name T515
Test name
Test status
Simulation time 93428279 ps
CPU time 0.79 seconds
Started Feb 21 12:34:41 PM PST 24
Finished Feb 21 12:34:42 PM PST 24
Peak memory 196144 kb
Host smart-db9884a3-0ab8-47a7-b7e5-89ecd5fabda1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386282320 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1386282320
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2012441100
Short name T577
Test name
Test status
Simulation time 17053733 ps
CPU time 0.56 seconds
Started Feb 21 12:34:34 PM PST 24
Finished Feb 21 12:34:35 PM PST 24
Peak memory 182460 kb
Host smart-ff80329b-16b6-4615-9518-8fbe26413e9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012441100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2012441100
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1478546893
Short name T455
Test name
Test status
Simulation time 21947525 ps
CPU time 0.5 seconds
Started Feb 21 12:34:35 PM PST 24
Finished Feb 21 12:34:36 PM PST 24
Peak memory 181696 kb
Host smart-f386cae9-8de0-4c4a-bdb6-773f541dc3a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478546893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1478546893
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3505647846
Short name T570
Test name
Test status
Simulation time 51341333 ps
CPU time 0.59 seconds
Started Feb 21 12:34:35 PM PST 24
Finished Feb 21 12:34:36 PM PST 24
Peak memory 190868 kb
Host smart-75805e02-16b5-4237-925c-d91a4b785ee1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505647846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3505647846
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.242707405
Short name T513
Test name
Test status
Simulation time 170875733 ps
CPU time 1.14 seconds
Started Feb 21 12:34:16 PM PST 24
Finished Feb 21 12:34:20 PM PST 24
Peak memory 196632 kb
Host smart-0dd8f346-97c8-4874-8e6f-060bfb00b90e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242707405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.242707405
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1632592079
Short name T92
Test name
Test status
Simulation time 83194175 ps
CPU time 1.09 seconds
Started Feb 21 12:34:46 PM PST 24
Finished Feb 21 12:34:49 PM PST 24
Peak memory 194408 kb
Host smart-a381f6c3-2d37-4502-94c5-480b64b3b41e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632592079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1632592079
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2949402857
Short name T507
Test name
Test status
Simulation time 34505815 ps
CPU time 0.79 seconds
Started Feb 21 12:34:44 PM PST 24
Finished Feb 21 12:34:46 PM PST 24
Peak memory 192008 kb
Host smart-e1a51bbb-9aaa-49db-bf00-8af7ee11160e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949402857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.2949402857
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3358192908
Short name T47
Test name
Test status
Simulation time 2093843031 ps
CPU time 2.76 seconds
Started Feb 21 12:34:25 PM PST 24
Finished Feb 21 12:34:28 PM PST 24
Peak memory 191828 kb
Host smart-7a6f855c-7ca3-4967-a159-5efa880f92b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358192908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.3358192908
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2488227188
Short name T76
Test name
Test status
Simulation time 25625975 ps
CPU time 0.62 seconds
Started Feb 21 12:34:38 PM PST 24
Finished Feb 21 12:34:42 PM PST 24
Peak memory 182440 kb
Host smart-c56cceda-1cb8-40e3-b677-7b6dd6a870ae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488227188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2488227188
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1539155424
Short name T530
Test name
Test status
Simulation time 40016873 ps
CPU time 0.88 seconds
Started Feb 21 12:34:23 PM PST 24
Finished Feb 21 12:34:25 PM PST 24
Peak memory 196068 kb
Host smart-f71f2327-f6c4-4df8-9c68-e0572c599816
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539155424 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1539155424
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.4160318140
Short name T582
Test name
Test status
Simulation time 132609756 ps
CPU time 0.52 seconds
Started Feb 21 12:34:27 PM PST 24
Finished Feb 21 12:34:28 PM PST 24
Peak memory 182136 kb
Host smart-f9c26cd0-99be-4b42-9a8f-004a14931ca2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160318140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.4160318140
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3151485139
Short name T490
Test name
Test status
Simulation time 22583954 ps
CPU time 0.56 seconds
Started Feb 21 12:34:17 PM PST 24
Finished Feb 21 12:34:20 PM PST 24
Peak memory 182372 kb
Host smart-08d0583e-d0e9-41da-bde3-7fadd99b3e99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151485139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3151485139
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3988217423
Short name T46
Test name
Test status
Simulation time 38878988 ps
CPU time 0.63 seconds
Started Feb 21 12:34:12 PM PST 24
Finished Feb 21 12:34:13 PM PST 24
Peak memory 191768 kb
Host smart-3b953637-ca77-46af-9e07-cd6abb216432
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988217423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3988217423
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3628770766
Short name T527
Test name
Test status
Simulation time 520400457 ps
CPU time 2.2 seconds
Started Feb 21 12:34:16 PM PST 24
Finished Feb 21 12:34:22 PM PST 24
Peak memory 197172 kb
Host smart-fe19d5bc-17a8-4a4a-b207-5e1d17f1a204
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628770766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.3628770766
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1599785663
Short name T477
Test name
Test status
Simulation time 846193708 ps
CPU time 1.32 seconds
Started Feb 21 12:34:43 PM PST 24
Finished Feb 21 12:34:44 PM PST 24
Peak memory 182640 kb
Host smart-9451b198-f553-4815-8255-7043880f11c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599785663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.1599785663
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3518638285
Short name T545
Test name
Test status
Simulation time 198849864 ps
CPU time 0.54 seconds
Started Feb 21 12:34:37 PM PST 24
Finished Feb 21 12:34:38 PM PST 24
Peak memory 182220 kb
Host smart-3c04b603-73c1-497d-b9b4-3c4508e780e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518638285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3518638285
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.56303821
Short name T581
Test name
Test status
Simulation time 14866527 ps
CPU time 0.57 seconds
Started Feb 21 12:34:35 PM PST 24
Finished Feb 21 12:34:36 PM PST 24
Peak memory 182196 kb
Host smart-221794f6-2baa-42a0-8bc6-e5c0fda74dc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56303821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.56303821
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1408690142
Short name T505
Test name
Test status
Simulation time 38922907 ps
CPU time 0.55 seconds
Started Feb 21 12:34:36 PM PST 24
Finished Feb 21 12:34:39 PM PST 24
Peak memory 181612 kb
Host smart-efaf4f28-a2b3-4434-b801-4295d236c0e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408690142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.1408690142
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3943427561
Short name T470
Test name
Test status
Simulation time 52915533 ps
CPU time 0.55 seconds
Started Feb 21 12:34:33 PM PST 24
Finished Feb 21 12:34:34 PM PST 24
Peak memory 182220 kb
Host smart-72b09dd3-8c9b-40b5-8812-ef0cfa47b40c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943427561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3943427561
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2595488838
Short name T468
Test name
Test status
Simulation time 22606572 ps
CPU time 0.56 seconds
Started Feb 21 12:34:42 PM PST 24
Finished Feb 21 12:34:43 PM PST 24
Peak memory 182172 kb
Host smart-39811a02-e473-4b47-9903-8260ffab60c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595488838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2595488838
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2912908789
Short name T451
Test name
Test status
Simulation time 43115005 ps
CPU time 0.56 seconds
Started Feb 21 12:34:20 PM PST 24
Finished Feb 21 12:34:22 PM PST 24
Peak memory 181732 kb
Host smart-9eee71c5-771d-45de-8945-6636e045db3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912908789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2912908789
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1102257279
Short name T475
Test name
Test status
Simulation time 12244257 ps
CPU time 0.54 seconds
Started Feb 21 12:34:44 PM PST 24
Finished Feb 21 12:34:45 PM PST 24
Peak memory 181780 kb
Host smart-09b6a16a-16a4-45c9-afe7-443772979665
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102257279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1102257279
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3772236543
Short name T511
Test name
Test status
Simulation time 60704003 ps
CPU time 0.54 seconds
Started Feb 21 12:34:18 PM PST 24
Finished Feb 21 12:34:20 PM PST 24
Peak memory 182208 kb
Host smart-693b1ed2-aa59-4d61-91b4-0153f1ce57c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772236543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3772236543
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2051203564
Short name T522
Test name
Test status
Simulation time 23305148 ps
CPU time 0.54 seconds
Started Feb 21 12:34:53 PM PST 24
Finished Feb 21 12:34:58 PM PST 24
Peak memory 182160 kb
Host smart-dbcc9243-ea0d-4786-8ce6-a3653f3dee24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051203564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2051203564
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3229777655
Short name T478
Test name
Test status
Simulation time 14540367 ps
CPU time 0.55 seconds
Started Feb 21 12:34:45 PM PST 24
Finished Feb 21 12:34:47 PM PST 24
Peak memory 182324 kb
Host smart-f18e1be9-9c44-4888-8c83-30ac2a4be9cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229777655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3229777655
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1074870889
Short name T80
Test name
Test status
Simulation time 28055139 ps
CPU time 0.69 seconds
Started Feb 21 12:34:50 PM PST 24
Finished Feb 21 12:34:57 PM PST 24
Peak memory 182400 kb
Host smart-bee4c440-27cd-4232-834b-b3d0d6fecf2f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074870889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.1074870889
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1807478545
Short name T452
Test name
Test status
Simulation time 104195680 ps
CPU time 1.65 seconds
Started Feb 21 12:34:31 PM PST 24
Finished Feb 21 12:34:34 PM PST 24
Peak memory 191768 kb
Host smart-0f10c1fb-7878-4d9e-a51f-351558be76b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807478545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.1807478545
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2610807218
Short name T540
Test name
Test status
Simulation time 31100361 ps
CPU time 0.58 seconds
Started Feb 21 12:34:36 PM PST 24
Finished Feb 21 12:34:39 PM PST 24
Peak memory 182564 kb
Host smart-cbb4115e-5003-42e3-86d5-0e30447181bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610807218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.2610807218
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.228031693
Short name T473
Test name
Test status
Simulation time 54802283 ps
CPU time 0.83 seconds
Started Feb 21 12:34:36 PM PST 24
Finished Feb 21 12:34:38 PM PST 24
Peak memory 196472 kb
Host smart-bea75965-96d4-4647-909f-89eb9e56b8e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228031693 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.228031693
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.4167321686
Short name T497
Test name
Test status
Simulation time 12194036 ps
CPU time 0.54 seconds
Started Feb 21 12:34:39 PM PST 24
Finished Feb 21 12:34:42 PM PST 24
Peak memory 182452 kb
Host smart-41c13458-9506-42b3-a456-dc6e152eab8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167321686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.4167321686
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.912760351
Short name T524
Test name
Test status
Simulation time 29637598 ps
CPU time 0.52 seconds
Started Feb 21 12:34:40 PM PST 24
Finished Feb 21 12:34:42 PM PST 24
Peak memory 182196 kb
Host smart-221ad2e6-75c7-4c9e-a0cf-23d5f0316893
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912760351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.912760351
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1211815003
Short name T529
Test name
Test status
Simulation time 26986712 ps
CPU time 0.73 seconds
Started Feb 21 12:34:15 PM PST 24
Finished Feb 21 12:34:17 PM PST 24
Peak memory 191856 kb
Host smart-cb04af3e-bdf1-4fa4-b77d-a23a55a66e96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211815003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1211815003
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3570053705
Short name T456
Test name
Test status
Simulation time 191682801 ps
CPU time 2.44 seconds
Started Feb 21 12:34:23 PM PST 24
Finished Feb 21 12:34:27 PM PST 24
Peak memory 196996 kb
Host smart-22981147-7b62-4fdf-a641-6b9c571eb214
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570053705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3570053705
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1305573873
Short name T482
Test name
Test status
Simulation time 253506330 ps
CPU time 1.07 seconds
Started Feb 21 12:34:36 PM PST 24
Finished Feb 21 12:34:39 PM PST 24
Peak memory 194536 kb
Host smart-3ac8ee0f-ad9f-41a2-973e-32ae3a437946
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305573873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.1305573873
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3029647713
Short name T553
Test name
Test status
Simulation time 12634168 ps
CPU time 0.55 seconds
Started Feb 21 12:34:43 PM PST 24
Finished Feb 21 12:34:44 PM PST 24
Peak memory 181600 kb
Host smart-b85e75fc-d0c7-42a7-83ff-e2aee51ff777
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029647713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3029647713
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.4100097342
Short name T488
Test name
Test status
Simulation time 44195964 ps
CPU time 0.52 seconds
Started Feb 21 12:34:50 PM PST 24
Finished Feb 21 12:34:57 PM PST 24
Peak memory 181512 kb
Host smart-4276eef6-7a7f-435d-b6b9-d125f959157f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100097342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.4100097342
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.4175740182
Short name T465
Test name
Test status
Simulation time 91041039 ps
CPU time 0.55 seconds
Started Feb 21 12:34:48 PM PST 24
Finished Feb 21 12:34:50 PM PST 24
Peak memory 182264 kb
Host smart-6f5fca93-1252-46cc-8f15-f177c1589cc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175740182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.4175740182
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.684961069
Short name T546
Test name
Test status
Simulation time 18471243 ps
CPU time 0.56 seconds
Started Feb 21 12:34:41 PM PST 24
Finished Feb 21 12:34:42 PM PST 24
Peak memory 182256 kb
Host smart-968fbd8f-1057-4bcd-a6dd-0e4711d7f7d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684961069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.684961069
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3820924694
Short name T512
Test name
Test status
Simulation time 37681178 ps
CPU time 0.57 seconds
Started Feb 21 12:34:38 PM PST 24
Finished Feb 21 12:34:41 PM PST 24
Peak memory 181864 kb
Host smart-26e076f8-8069-434f-9fc8-99c58daaf6c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820924694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3820924694
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2544370854
Short name T578
Test name
Test status
Simulation time 31281412 ps
CPU time 0.58 seconds
Started Feb 21 12:34:39 PM PST 24
Finished Feb 21 12:34:42 PM PST 24
Peak memory 182364 kb
Host smart-10b40a96-7837-4426-bad7-6369fa14c48a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544370854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2544370854
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1471507766
Short name T541
Test name
Test status
Simulation time 37261105 ps
CPU time 0.53 seconds
Started Feb 21 12:34:47 PM PST 24
Finished Feb 21 12:34:53 PM PST 24
Peak memory 182244 kb
Host smart-0852e475-c0e8-481f-9470-856c7821434e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471507766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1471507766
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2511483643
Short name T489
Test name
Test status
Simulation time 14295446 ps
CPU time 0.56 seconds
Started Feb 21 12:34:53 PM PST 24
Finished Feb 21 12:34:59 PM PST 24
Peak memory 182328 kb
Host smart-030d6b36-17e0-4f00-8b9a-af26529bb6ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511483643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2511483643
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2469122326
Short name T506
Test name
Test status
Simulation time 59873935 ps
CPU time 0.58 seconds
Started Feb 21 12:35:35 PM PST 24
Finished Feb 21 12:35:35 PM PST 24
Peak memory 182136 kb
Host smart-e2b5f23e-ae2a-46ec-8606-684a7e1542ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469122326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2469122326
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1453239078
Short name T538
Test name
Test status
Simulation time 20083068 ps
CPU time 0.53 seconds
Started Feb 21 12:34:50 PM PST 24
Finished Feb 21 12:34:57 PM PST 24
Peak memory 181664 kb
Host smart-2c03c545-7ae6-40ec-9ac2-c6f54c3bb828
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453239078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1453239078
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2198785395
Short name T79
Test name
Test status
Simulation time 15948092 ps
CPU time 0.69 seconds
Started Feb 21 12:34:40 PM PST 24
Finished Feb 21 12:34:42 PM PST 24
Peak memory 182568 kb
Host smart-1e941da0-094a-4d84-8b63-7767ee8ac4da
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198785395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2198785395
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1995860283
Short name T499
Test name
Test status
Simulation time 1612242363 ps
CPU time 3.7 seconds
Started Feb 21 12:34:20 PM PST 24
Finished Feb 21 12:34:25 PM PST 24
Peak memory 191920 kb
Host smart-7fd1a4cb-1b18-4aa8-9d48-24892051dfa9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995860283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.1995860283
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.254839997
Short name T519
Test name
Test status
Simulation time 35707639 ps
CPU time 0.54 seconds
Started Feb 21 12:34:21 PM PST 24
Finished Feb 21 12:34:22 PM PST 24
Peak memory 181928 kb
Host smart-c0ec0d27-a474-4ca8-acb5-50d0b2f9c0f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254839997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re
set.254839997
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3260775071
Short name T535
Test name
Test status
Simulation time 65196176 ps
CPU time 0.67 seconds
Started Feb 21 12:34:53 PM PST 24
Finished Feb 21 12:34:58 PM PST 24
Peak memory 194060 kb
Host smart-a15fc601-962d-4232-b30e-613246cfe5b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260775071 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3260775071
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1584848192
Short name T84
Test name
Test status
Simulation time 57819363 ps
CPU time 0.58 seconds
Started Feb 21 12:34:32 PM PST 24
Finished Feb 21 12:34:34 PM PST 24
Peak memory 182404 kb
Host smart-11568aa9-5d03-43dc-b5c5-75bab0864ce1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584848192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1584848192
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3706692901
Short name T550
Test name
Test status
Simulation time 35985980 ps
CPU time 0.52 seconds
Started Feb 21 12:34:42 PM PST 24
Finished Feb 21 12:34:43 PM PST 24
Peak memory 181856 kb
Host smart-43e36095-0b31-44e3-85c3-68046e8c7f58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706692901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3706692901
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.833183843
Short name T86
Test name
Test status
Simulation time 61689362 ps
CPU time 0.75 seconds
Started Feb 21 12:34:16 PM PST 24
Finished Feb 21 12:34:20 PM PST 24
Peak memory 192948 kb
Host smart-a29b5510-ea8c-4f89-8af5-00457cafe3ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833183843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.833183843
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3507266305
Short name T449
Test name
Test status
Simulation time 97999543 ps
CPU time 1.24 seconds
Started Feb 21 12:34:36 PM PST 24
Finished Feb 21 12:34:37 PM PST 24
Peak memory 197292 kb
Host smart-44fa05ef-bfd0-4812-b328-5c9f2f8968be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507266305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3507266305
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3844074579
Short name T555
Test name
Test status
Simulation time 48568971 ps
CPU time 0.82 seconds
Started Feb 21 12:34:38 PM PST 24
Finished Feb 21 12:34:42 PM PST 24
Peak memory 193176 kb
Host smart-d095d48b-1340-4dc6-8634-238733122268
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844074579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.3844074579
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1882861828
Short name T510
Test name
Test status
Simulation time 19943650 ps
CPU time 0.52 seconds
Started Feb 21 12:34:45 PM PST 24
Finished Feb 21 12:34:47 PM PST 24
Peak memory 181660 kb
Host smart-3f49917c-59f1-4c0e-8a34-c112c5cf2cdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882861828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1882861828
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2862162328
Short name T534
Test name
Test status
Simulation time 74614524 ps
CPU time 0.54 seconds
Started Feb 21 12:34:46 PM PST 24
Finished Feb 21 12:34:47 PM PST 24
Peak memory 182304 kb
Host smart-a1239938-8b77-4cc5-950f-bfb89d57c8f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862162328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2862162328
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3323154161
Short name T501
Test name
Test status
Simulation time 26923511 ps
CPU time 0.55 seconds
Started Feb 21 12:34:45 PM PST 24
Finished Feb 21 12:34:46 PM PST 24
Peak memory 182052 kb
Host smart-612140b9-a124-4365-82c5-83c021520e7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323154161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3323154161
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.259469755
Short name T520
Test name
Test status
Simulation time 16797490 ps
CPU time 0.63 seconds
Started Feb 21 12:34:31 PM PST 24
Finished Feb 21 12:34:33 PM PST 24
Peak memory 182224 kb
Host smart-46bb1c7d-e96a-4f81-aa5e-2e2ae561d886
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259469755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.259469755
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2174485067
Short name T485
Test name
Test status
Simulation time 18004260 ps
CPU time 0.56 seconds
Started Feb 21 12:34:50 PM PST 24
Finished Feb 21 12:34:57 PM PST 24
Peak memory 182196 kb
Host smart-d732e608-10dd-4b9b-b1c5-de7ecfbc3508
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174485067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2174485067
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2094569825
Short name T543
Test name
Test status
Simulation time 20803854 ps
CPU time 0.58 seconds
Started Feb 21 12:34:39 PM PST 24
Finished Feb 21 12:34:42 PM PST 24
Peak memory 182156 kb
Host smart-b41709aa-ae8e-4505-a12c-56347c0ea181
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094569825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2094569825
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.4264714238
Short name T448
Test name
Test status
Simulation time 81273597 ps
CPU time 0.53 seconds
Started Feb 21 12:34:48 PM PST 24
Finished Feb 21 12:34:56 PM PST 24
Peak memory 181752 kb
Host smart-8f4461fa-912b-4b44-81bd-6818766b9ade
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264714238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.4264714238
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2126502271
Short name T531
Test name
Test status
Simulation time 36348446 ps
CPU time 0.58 seconds
Started Feb 21 12:34:34 PM PST 24
Finished Feb 21 12:34:35 PM PST 24
Peak memory 182216 kb
Host smart-698e0555-7fc0-4cd9-b60b-764d0d0d977c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126502271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2126502271
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3129057765
Short name T571
Test name
Test status
Simulation time 16754446 ps
CPU time 0.54 seconds
Started Feb 21 12:34:47 PM PST 24
Finished Feb 21 12:34:53 PM PST 24
Peak memory 182220 kb
Host smart-da981669-26b0-4db3-b898-b396e4bf08b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129057765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3129057765
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.669393558
Short name T461
Test name
Test status
Simulation time 15033025 ps
CPU time 0.55 seconds
Started Feb 21 12:34:49 PM PST 24
Finished Feb 21 12:34:57 PM PST 24
Peak memory 182232 kb
Host smart-aafb8408-265d-40e3-86be-ac1eea041060
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669393558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.669393558
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3667518864
Short name T45
Test name
Test status
Simulation time 21134541 ps
CPU time 0.65 seconds
Started Feb 21 12:34:46 PM PST 24
Finished Feb 21 12:34:48 PM PST 24
Peak memory 194692 kb
Host smart-8cef639a-3cf0-4eaf-a608-bd82047ab62c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667518864 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.3667518864
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.534726895
Short name T556
Test name
Test status
Simulation time 50101042 ps
CPU time 0.57 seconds
Started Feb 21 12:34:27 PM PST 24
Finished Feb 21 12:34:28 PM PST 24
Peak memory 191628 kb
Host smart-c5add212-bdb4-4960-9379-6ae0c53979d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534726895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.534726895
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1263000558
Short name T526
Test name
Test status
Simulation time 29657269 ps
CPU time 0.6 seconds
Started Feb 21 12:34:24 PM PST 24
Finished Feb 21 12:34:25 PM PST 24
Peak memory 182288 kb
Host smart-ac105eb2-ba92-4dd4-9de8-70a5730cb9be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263000558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1263000558
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.166091509
Short name T563
Test name
Test status
Simulation time 79849902 ps
CPU time 0.75 seconds
Started Feb 21 12:34:20 PM PST 24
Finished Feb 21 12:34:22 PM PST 24
Peak memory 192376 kb
Host smart-7e4f6f6c-0f95-460e-90be-9256cb73ed62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166091509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_tim
er_same_csr_outstanding.166091509
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3013105842
Short name T500
Test name
Test status
Simulation time 259868064 ps
CPU time 2.2 seconds
Started Feb 21 12:34:44 PM PST 24
Finished Feb 21 12:34:47 PM PST 24
Peak memory 197124 kb
Host smart-0abce0d9-1268-4509-8f66-8cc74e8f6cfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013105842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3013105842
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1553436983
Short name T566
Test name
Test status
Simulation time 252431748 ps
CPU time 0.83 seconds
Started Feb 21 12:34:32 PM PST 24
Finished Feb 21 12:34:34 PM PST 24
Peak memory 182540 kb
Host smart-de1a62a0-6d8d-4bff-ab07-34f80a4a860a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553436983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1553436983
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3148148185
Short name T484
Test name
Test status
Simulation time 53700790 ps
CPU time 0.6 seconds
Started Feb 21 12:34:41 PM PST 24
Finished Feb 21 12:34:42 PM PST 24
Peak memory 192616 kb
Host smart-ef545e51-7748-48f3-842d-a3a517d2986c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148148185 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3148148185
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.4280255311
Short name T537
Test name
Test status
Simulation time 12176052 ps
CPU time 0.61 seconds
Started Feb 21 12:34:47 PM PST 24
Finished Feb 21 12:34:49 PM PST 24
Peak memory 182464 kb
Host smart-35b3023a-3542-4db7-85d8-aaed153bc633
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280255311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.4280255311
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1671822426
Short name T454
Test name
Test status
Simulation time 18262583 ps
CPU time 0.52 seconds
Started Feb 21 12:34:35 PM PST 24
Finished Feb 21 12:34:36 PM PST 24
Peak memory 182212 kb
Host smart-803a467e-dd88-4975-afb4-d60c5c3dd127
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671822426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1671822426
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.818298041
Short name T503
Test name
Test status
Simulation time 32644619 ps
CPU time 0.69 seconds
Started Feb 21 12:34:11 PM PST 24
Finished Feb 21 12:34:12 PM PST 24
Peak memory 191416 kb
Host smart-f9c2d208-2407-415f-81da-f1654f6dc5a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818298041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.818298041
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3822527627
Short name T481
Test name
Test status
Simulation time 427753509 ps
CPU time 2.14 seconds
Started Feb 21 12:34:17 PM PST 24
Finished Feb 21 12:34:21 PM PST 24
Peak memory 197200 kb
Host smart-51217980-21a4-4df3-a74b-200446d17a49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822527627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3822527627
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1433581069
Short name T90
Test name
Test status
Simulation time 147327982 ps
CPU time 1.01 seconds
Started Feb 21 12:34:37 PM PST 24
Finished Feb 21 12:34:39 PM PST 24
Peak memory 194236 kb
Host smart-a6aa6fbe-3809-4129-bd17-cda7345d6c4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433581069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.1433581069
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2374403037
Short name T528
Test name
Test status
Simulation time 25324940 ps
CPU time 0.74 seconds
Started Feb 21 12:34:14 PM PST 24
Finished Feb 21 12:34:16 PM PST 24
Peak memory 194628 kb
Host smart-6e197574-e6f2-481f-acac-02c49aa19c36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374403037 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2374403037
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2459128444
Short name T576
Test name
Test status
Simulation time 15501736 ps
CPU time 0.54 seconds
Started Feb 21 12:34:21 PM PST 24
Finished Feb 21 12:34:22 PM PST 24
Peak memory 182152 kb
Host smart-45e6e031-d621-4cd7-b318-d59320185e9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459128444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2459128444
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3296415330
Short name T533
Test name
Test status
Simulation time 14799040 ps
CPU time 0.55 seconds
Started Feb 21 12:34:18 PM PST 24
Finished Feb 21 12:34:20 PM PST 24
Peak memory 182212 kb
Host smart-26ad37e0-50a9-46a0-9631-11a07c113e1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296415330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3296415330
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2880103789
Short name T25
Test name
Test status
Simulation time 164335410 ps
CPU time 0.8 seconds
Started Feb 21 12:34:45 PM PST 24
Finished Feb 21 12:34:47 PM PST 24
Peak memory 192856 kb
Host smart-c6d7ce4b-4de2-4ab3-8de3-36aa1795b8bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880103789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2880103789
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1186423095
Short name T542
Test name
Test status
Simulation time 104109895 ps
CPU time 1.66 seconds
Started Feb 21 12:34:15 PM PST 24
Finished Feb 21 12:34:18 PM PST 24
Peak memory 190820 kb
Host smart-43a3108e-d452-4625-8c55-d8460bf4ea85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186423095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1186423095
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2027905923
Short name T476
Test name
Test status
Simulation time 46729657 ps
CPU time 0.8 seconds
Started Feb 21 12:34:17 PM PST 24
Finished Feb 21 12:34:20 PM PST 24
Peak memory 182752 kb
Host smart-942cc202-dcd0-430f-b915-b60a4543966f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027905923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.2027905923
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3917892893
Short name T450
Test name
Test status
Simulation time 149423491 ps
CPU time 0.74 seconds
Started Feb 21 12:34:27 PM PST 24
Finished Feb 21 12:34:29 PM PST 24
Peak memory 194780 kb
Host smart-dd4235f7-7132-4701-9887-d4a1e7b82d04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917892893 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3917892893
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.990940878
Short name T458
Test name
Test status
Simulation time 14976587 ps
CPU time 0.6 seconds
Started Feb 21 12:34:23 PM PST 24
Finished Feb 21 12:34:25 PM PST 24
Peak memory 182368 kb
Host smart-20476ef3-24ea-4b90-bc74-f6ec679f7280
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990940878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.990940878
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.711754478
Short name T508
Test name
Test status
Simulation time 14820495 ps
CPU time 0.59 seconds
Started Feb 21 12:34:14 PM PST 24
Finished Feb 21 12:34:16 PM PST 24
Peak memory 182252 kb
Host smart-0bdd49f9-8377-4c07-b403-a8072bcf5da7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711754478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.711754478
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3277375938
Short name T87
Test name
Test status
Simulation time 53111881 ps
CPU time 0.68 seconds
Started Feb 21 12:34:16 PM PST 24
Finished Feb 21 12:34:20 PM PST 24
Peak memory 192840 kb
Host smart-6ec5788a-7c05-495c-8372-db32ecfc78df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277375938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.3277375938
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2704213899
Short name T547
Test name
Test status
Simulation time 72145707 ps
CPU time 2.02 seconds
Started Feb 21 12:34:40 PM PST 24
Finished Feb 21 12:34:43 PM PST 24
Peak memory 197220 kb
Host smart-08d742f9-8858-4d34-94b0-df8621a92252
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704213899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2704213899
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3070416685
Short name T564
Test name
Test status
Simulation time 97530341 ps
CPU time 1.31 seconds
Started Feb 21 12:34:28 PM PST 24
Finished Feb 21 12:34:30 PM PST 24
Peak memory 182736 kb
Host smart-e7ab1421-c858-4802-95c1-e1d553523654
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070416685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.3070416685
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2901771536
Short name T483
Test name
Test status
Simulation time 30011009 ps
CPU time 0.83 seconds
Started Feb 21 12:34:39 PM PST 24
Finished Feb 21 12:34:42 PM PST 24
Peak memory 196312 kb
Host smart-28d553a1-1c5e-4d15-97c1-9a93b75c7c31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901771536 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2901771536
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1841642340
Short name T82
Test name
Test status
Simulation time 13664951 ps
CPU time 0.54 seconds
Started Feb 21 12:34:53 PM PST 24
Finished Feb 21 12:34:59 PM PST 24
Peak memory 181984 kb
Host smart-8e9eac4f-9275-4506-997a-436fd769fc8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841642340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1841642340
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3282271605
Short name T567
Test name
Test status
Simulation time 44057300 ps
CPU time 0.54 seconds
Started Feb 21 12:34:53 PM PST 24
Finished Feb 21 12:34:58 PM PST 24
Peak memory 181604 kb
Host smart-623704eb-3efe-4bb7-83f4-0c729ec9c3f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282271605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3282271605
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3766669998
Short name T521
Test name
Test status
Simulation time 14296790 ps
CPU time 0.65 seconds
Started Feb 21 12:34:32 PM PST 24
Finished Feb 21 12:34:33 PM PST 24
Peak memory 190924 kb
Host smart-ec1d04f9-ecce-4d5f-8187-a5e7a693d682
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766669998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.3766669998
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3612862254
Short name T467
Test name
Test status
Simulation time 44212140 ps
CPU time 1.29 seconds
Started Feb 21 12:34:41 PM PST 24
Finished Feb 21 12:34:43 PM PST 24
Peak memory 196528 kb
Host smart-3167b57e-ee47-4bd4-b697-f78e0f9a843a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612862254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3612862254
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1896595511
Short name T532
Test name
Test status
Simulation time 98830652 ps
CPU time 0.9 seconds
Started Feb 21 12:34:44 PM PST 24
Finished Feb 21 12:34:46 PM PST 24
Peak memory 192332 kb
Host smart-3ab0b449-7e00-4c09-8690-93ac2350a7f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896595511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1896595511
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.522394774
Short name T377
Test name
Test status
Simulation time 149340684906 ps
CPU time 242.39 seconds
Started Feb 21 12:42:32 PM PST 24
Finished Feb 21 12:46:35 PM PST 24
Peak memory 182760 kb
Host smart-d71d085a-d7ad-4cce-ad3d-d04271109765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522394774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.522394774
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.420654267
Short name T306
Test name
Test status
Simulation time 39249011216 ps
CPU time 168.16 seconds
Started Feb 21 12:42:42 PM PST 24
Finished Feb 21 12:45:31 PM PST 24
Peak memory 190960 kb
Host smart-17ab6084-b111-4674-b899-6fe675a1d30d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420654267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.420654267
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.4105863824
Short name T236
Test name
Test status
Simulation time 217808643929 ps
CPU time 124.2 seconds
Started Feb 21 12:42:31 PM PST 24
Finished Feb 21 12:44:36 PM PST 24
Peak memory 182748 kb
Host smart-0a91c0e5-602d-46fb-957b-e35f17f82ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105863824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.4105863824
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.3480761894
Short name T13
Test name
Test status
Simulation time 157946017825 ps
CPU time 275.63 seconds
Started Feb 21 12:42:16 PM PST 24
Finished Feb 21 12:46:52 PM PST 24
Peak memory 205656 kb
Host smart-85391456-3bc7-416c-ae1a-1df5b300ebfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480761894 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.3480761894
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2119332081
Short name T378
Test name
Test status
Simulation time 540560981102 ps
CPU time 107.97 seconds
Started Feb 21 12:42:49 PM PST 24
Finished Feb 21 12:44:38 PM PST 24
Peak memory 182600 kb
Host smart-04a3ce95-7ada-4b36-a2f3-18fd0b1c0d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119332081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2119332081
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.3569277554
Short name T18
Test name
Test status
Simulation time 82826464 ps
CPU time 0.9 seconds
Started Feb 21 12:42:32 PM PST 24
Finished Feb 21 12:42:33 PM PST 24
Peak memory 214024 kb
Host smart-e5a55404-fa98-487e-8a7a-da39144464fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569277554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3569277554
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3809327180
Short name T364
Test name
Test status
Simulation time 170381728825 ps
CPU time 240.82 seconds
Started Feb 21 12:42:24 PM PST 24
Finished Feb 21 12:46:26 PM PST 24
Peak memory 182792 kb
Host smart-ab532a83-a4a4-4cae-9ae4-e6489b6920a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809327180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3809327180
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.1885815462
Short name T127
Test name
Test status
Simulation time 31701035827 ps
CPU time 32.51 seconds
Started Feb 21 12:42:45 PM PST 24
Finished Feb 21 12:43:17 PM PST 24
Peak memory 182804 kb
Host smart-f41a78cb-ec4e-43dd-8225-283bb14b0cb0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885815462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.1885815462
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.1923719478
Short name T71
Test name
Test status
Simulation time 124533448378 ps
CPU time 156.35 seconds
Started Feb 21 12:42:17 PM PST 24
Finished Feb 21 12:44:54 PM PST 24
Peak memory 182720 kb
Host smart-703ffbc4-eca3-4e2b-814b-792f46fa4bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923719478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1923719478
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.1290557497
Short name T226
Test name
Test status
Simulation time 794740042368 ps
CPU time 628.29 seconds
Started Feb 21 12:42:40 PM PST 24
Finished Feb 21 12:53:09 PM PST 24
Peak memory 190748 kb
Host smart-26aa9673-dd17-4830-80e1-8cb0b20d0dbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290557497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1290557497
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1393746812
Short name T172
Test name
Test status
Simulation time 24203574334 ps
CPU time 284.96 seconds
Started Feb 21 12:42:16 PM PST 24
Finished Feb 21 12:47:01 PM PST 24
Peak memory 182652 kb
Host smart-fb5e0b5f-724f-472a-bc95-dbc81250f08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393746812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1393746812
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.685966155
Short name T363
Test name
Test status
Simulation time 20405179 ps
CPU time 0.52 seconds
Started Feb 21 12:42:36 PM PST 24
Finished Feb 21 12:42:37 PM PST 24
Peak memory 182064 kb
Host smart-02c711e8-8de3-4473-a722-437685bfc825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685966155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
685966155
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/103.rv_timer_random.2411676595
Short name T145
Test name
Test status
Simulation time 273334245093 ps
CPU time 280.48 seconds
Started Feb 21 12:43:38 PM PST 24
Finished Feb 21 12:48:19 PM PST 24
Peak memory 190968 kb
Host smart-35cd5a2e-5a6d-4b47-8c23-a18cfc2aef4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411676595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2411676595
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1353170462
Short name T242
Test name
Test status
Simulation time 790769914412 ps
CPU time 764.32 seconds
Started Feb 21 12:43:36 PM PST 24
Finished Feb 21 12:56:21 PM PST 24
Peak memory 190912 kb
Host smart-70463bc6-db66-4268-801a-ee191415986c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353170462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1353170462
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2429582177
Short name T195
Test name
Test status
Simulation time 822803209760 ps
CPU time 594.98 seconds
Started Feb 21 12:43:42 PM PST 24
Finished Feb 21 12:53:40 PM PST 24
Peak memory 190980 kb
Host smart-9b03d1df-7026-4ce4-8bd3-ce90b123c794
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429582177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2429582177
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.3327209749
Short name T252
Test name
Test status
Simulation time 112505641862 ps
CPU time 52.95 seconds
Started Feb 21 12:43:22 PM PST 24
Finished Feb 21 12:44:15 PM PST 24
Peak memory 182748 kb
Host smart-2a02e150-626f-46aa-94f6-890954b83d3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327209749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3327209749
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.3261045732
Short name T39
Test name
Test status
Simulation time 33438448836 ps
CPU time 112.44 seconds
Started Feb 21 12:43:34 PM PST 24
Finished Feb 21 12:45:27 PM PST 24
Peak memory 190976 kb
Host smart-ddfee46d-95d8-42b0-a549-f49e37d67aab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261045732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3261045732
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.909828427
Short name T124
Test name
Test status
Simulation time 432126148136 ps
CPU time 246.35 seconds
Started Feb 21 12:42:40 PM PST 24
Finished Feb 21 12:46:47 PM PST 24
Peak memory 182568 kb
Host smart-b74d2a00-da26-4b5c-93d7-b7e238086f89
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909828427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.rv_timer_cfg_update_on_fly.909828427
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.4027227708
Short name T357
Test name
Test status
Simulation time 630327462158 ps
CPU time 263.3 seconds
Started Feb 21 12:42:41 PM PST 24
Finished Feb 21 12:47:04 PM PST 24
Peak memory 182668 kb
Host smart-c56f3f5a-4ced-4a65-a40b-b7569008b400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027227708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.4027227708
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.808042180
Short name T338
Test name
Test status
Simulation time 398496446227 ps
CPU time 156.73 seconds
Started Feb 21 12:42:53 PM PST 24
Finished Feb 21 12:45:31 PM PST 24
Peak memory 190964 kb
Host smart-b1b0204d-1dbb-49e0-aff7-081c15e74d14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808042180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.808042180
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.3278281977
Short name T414
Test name
Test status
Simulation time 44292125 ps
CPU time 0.61 seconds
Started Feb 21 12:42:46 PM PST 24
Finished Feb 21 12:42:46 PM PST 24
Peak memory 182356 kb
Host smart-eaa95f5a-50b2-4df1-8e5d-3cf396a1e7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278281977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.3278281977
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.2949062311
Short name T212
Test name
Test status
Simulation time 946600183439 ps
CPU time 138.49 seconds
Started Feb 21 12:43:38 PM PST 24
Finished Feb 21 12:45:57 PM PST 24
Peak memory 190952 kb
Host smart-dfd81009-c506-44e2-a7a4-f88b6e1c5cdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949062311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2949062311
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.3543328442
Short name T348
Test name
Test status
Simulation time 82048771452 ps
CPU time 45.39 seconds
Started Feb 21 12:43:33 PM PST 24
Finished Feb 21 12:44:19 PM PST 24
Peak memory 182740 kb
Host smart-dda85ae3-cae2-4fe5-93fd-6e894e076757
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543328442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3543328442
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.1931410654
Short name T67
Test name
Test status
Simulation time 79820689298 ps
CPU time 594.08 seconds
Started Feb 21 12:43:41 PM PST 24
Finished Feb 21 12:53:36 PM PST 24
Peak memory 182624 kb
Host smart-0f10b7d1-1480-4429-ae46-c37fc737178d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931410654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1931410654
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1782458543
Short name T256
Test name
Test status
Simulation time 217671924129 ps
CPU time 364.61 seconds
Started Feb 21 12:43:16 PM PST 24
Finished Feb 21 12:49:21 PM PST 24
Peak memory 190872 kb
Host smart-a6a00201-27c1-48ec-aa0d-f28c604e5f82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782458543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1782458543
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.4238143742
Short name T155
Test name
Test status
Simulation time 692038102716 ps
CPU time 381.17 seconds
Started Feb 21 12:43:42 PM PST 24
Finished Feb 21 12:50:04 PM PST 24
Peak memory 193008 kb
Host smart-4c00f704-7239-4c96-b02d-f50049a11463
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238143742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.4238143742
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3891971464
Short name T358
Test name
Test status
Simulation time 75285173584 ps
CPU time 102.24 seconds
Started Feb 21 12:42:38 PM PST 24
Finished Feb 21 12:44:21 PM PST 24
Peak memory 182544 kb
Host smart-8c189f50-9c82-40fb-b350-9da522da2ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891971464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3891971464
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.3223145687
Short name T94
Test name
Test status
Simulation time 240159207811 ps
CPU time 278.06 seconds
Started Feb 21 12:42:33 PM PST 24
Finished Feb 21 12:47:12 PM PST 24
Peak memory 190948 kb
Host smart-8868ed66-afa6-468e-91a8-e938586c2210
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223145687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3223145687
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.3347916623
Short name T401
Test name
Test status
Simulation time 962065679 ps
CPU time 0.99 seconds
Started Feb 21 12:42:49 PM PST 24
Finished Feb 21 12:42:50 PM PST 24
Peak memory 182508 kb
Host smart-1d0cb020-38ff-4c4f-96e8-c923ded587f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347916623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.3347916623
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2071218527
Short name T406
Test name
Test status
Simulation time 256651733344 ps
CPU time 219.32 seconds
Started Feb 21 12:43:02 PM PST 24
Finished Feb 21 12:46:42 PM PST 24
Peak memory 182668 kb
Host smart-df21ab73-7da4-4787-a476-92606f330851
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071218527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2071218527
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/122.rv_timer_random.370123931
Short name T262
Test name
Test status
Simulation time 46513381181 ps
CPU time 77.01 seconds
Started Feb 21 12:43:25 PM PST 24
Finished Feb 21 12:44:43 PM PST 24
Peak memory 190956 kb
Host smart-79f8c686-aea6-4c26-a3bd-935ca4bee14f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370123931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.370123931
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1245975281
Short name T353
Test name
Test status
Simulation time 180206730925 ps
CPU time 588.46 seconds
Started Feb 21 12:43:48 PM PST 24
Finished Feb 21 12:53:41 PM PST 24
Peak memory 182652 kb
Host smart-b0a17b70-8029-4e4d-9e90-297472076dfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245975281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1245975281
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.2890709776
Short name T196
Test name
Test status
Simulation time 85474259433 ps
CPU time 71.92 seconds
Started Feb 21 12:43:12 PM PST 24
Finished Feb 21 12:44:26 PM PST 24
Peak memory 190876 kb
Host smart-f56ae9a2-fb8c-4fc8-9cac-93d207e97319
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890709776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2890709776
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1906113450
Short name T337
Test name
Test status
Simulation time 86517364482 ps
CPU time 270.88 seconds
Started Feb 21 12:43:11 PM PST 24
Finished Feb 21 12:47:42 PM PST 24
Peak memory 190944 kb
Host smart-d5a1f341-3acd-4dae-a444-bd7dcf2ce38f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906113450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1906113450
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.608502584
Short name T294
Test name
Test status
Simulation time 523137327941 ps
CPU time 217.69 seconds
Started Feb 21 12:43:05 PM PST 24
Finished Feb 21 12:46:43 PM PST 24
Peak memory 192920 kb
Host smart-7052f61a-3882-48e0-8620-acc5964b00e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608502584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.608502584
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.880308518
Short name T362
Test name
Test status
Simulation time 68166064852 ps
CPU time 107.63 seconds
Started Feb 21 12:42:54 PM PST 24
Finished Feb 21 12:44:43 PM PST 24
Peak memory 182660 kb
Host smart-0c0d3a81-6327-47ec-a154-a6bbd5fca48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880308518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.880308518
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.2620457380
Short name T37
Test name
Test status
Simulation time 557889990888 ps
CPU time 607.07 seconds
Started Feb 21 12:42:45 PM PST 24
Finished Feb 21 12:52:52 PM PST 24
Peak memory 190868 kb
Host smart-b54d81ef-22ca-4853-896e-17aec99b50dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620457380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2620457380
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.4031448765
Short name T58
Test name
Test status
Simulation time 23690690995 ps
CPU time 23.34 seconds
Started Feb 21 12:42:41 PM PST 24
Finished Feb 21 12:43:04 PM PST 24
Peak memory 182736 kb
Host smart-4d7a0c75-3407-4130-9694-fd918e815f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031448765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.4031448765
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3092655821
Short name T66
Test name
Test status
Simulation time 207735161476 ps
CPU time 1705.02 seconds
Started Feb 21 12:42:43 PM PST 24
Finished Feb 21 01:11:09 PM PST 24
Peak memory 190860 kb
Host smart-16e0d2a4-ce57-497b-a8d2-b0b2ab6d6518
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092655821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3092655821
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/134.rv_timer_random.3197502655
Short name T265
Test name
Test status
Simulation time 21807915166 ps
CPU time 14.52 seconds
Started Feb 21 12:43:13 PM PST 24
Finished Feb 21 12:43:29 PM PST 24
Peak memory 182584 kb
Host smart-61d72fa1-e8af-42c5-8db3-26d5a315dae4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197502655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3197502655
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.277893799
Short name T152
Test name
Test status
Simulation time 316025976537 ps
CPU time 700.13 seconds
Started Feb 21 12:43:21 PM PST 24
Finished Feb 21 12:55:06 PM PST 24
Peak memory 190948 kb
Host smart-989d1c0d-f1ad-402b-8083-9604cc7b43bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277893799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.277893799
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.4153964519
Short name T61
Test name
Test status
Simulation time 31333287737 ps
CPU time 17.11 seconds
Started Feb 21 12:43:18 PM PST 24
Finished Feb 21 12:43:36 PM PST 24
Peak memory 182772 kb
Host smart-3c3b0c26-8102-4b58-bae4-fac4599b083d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153964519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.4153964519
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.355646028
Short name T119
Test name
Test status
Simulation time 49167293984 ps
CPU time 85.02 seconds
Started Feb 21 12:42:36 PM PST 24
Finished Feb 21 12:44:02 PM PST 24
Peak memory 182680 kb
Host smart-7974f2dc-3acd-40d5-9554-7495627bb1ce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355646028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.355646028
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2712268585
Short name T392
Test name
Test status
Simulation time 93424585445 ps
CPU time 121.95 seconds
Started Feb 21 12:42:22 PM PST 24
Finished Feb 21 12:44:24 PM PST 24
Peak memory 182660 kb
Host smart-0bd5ae78-01da-4549-8f93-881cc3ef707e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712268585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2712268585
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.173948940
Short name T274
Test name
Test status
Simulation time 36412490587 ps
CPU time 44.74 seconds
Started Feb 21 12:42:38 PM PST 24
Finished Feb 21 12:43:23 PM PST 24
Peak memory 190944 kb
Host smart-7ec11ca4-e27c-42e3-861b-bef0f7f5bc51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173948940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.173948940
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.2642051840
Short name T247
Test name
Test status
Simulation time 278957949575 ps
CPU time 426.48 seconds
Started Feb 21 12:42:50 PM PST 24
Finished Feb 21 12:49:57 PM PST 24
Peak memory 190852 kb
Host smart-71abcfbb-e3a0-4a7a-9f97-7b4a6df7327e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642051840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2642051840
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/142.rv_timer_random.763429048
Short name T349
Test name
Test status
Simulation time 58635084903 ps
CPU time 98.37 seconds
Started Feb 21 12:43:02 PM PST 24
Finished Feb 21 12:44:41 PM PST 24
Peak memory 190948 kb
Host smart-3f46182d-9fe1-4e8f-9c2f-9716be838cb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763429048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.763429048
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3909123419
Short name T219
Test name
Test status
Simulation time 820812297605 ps
CPU time 968.92 seconds
Started Feb 21 12:43:16 PM PST 24
Finished Feb 21 12:59:26 PM PST 24
Peak memory 190968 kb
Host smart-faf7dd06-18da-42dd-872f-18401ce6cad7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909123419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3909123419
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1455556733
Short name T69
Test name
Test status
Simulation time 33752447072 ps
CPU time 59.79 seconds
Started Feb 21 12:43:13 PM PST 24
Finished Feb 21 12:44:14 PM PST 24
Peak memory 190968 kb
Host smart-33df3663-2cb2-405a-9f43-9614b577ee4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455556733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1455556733
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.2419672779
Short name T444
Test name
Test status
Simulation time 392062553759 ps
CPU time 894.63 seconds
Started Feb 21 12:43:18 PM PST 24
Finished Feb 21 12:58:13 PM PST 24
Peak memory 190972 kb
Host smart-80e1bebe-6538-4a1a-bf5f-6275139d7ac2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419672779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2419672779
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.1607860700
Short name T216
Test name
Test status
Simulation time 26395965332 ps
CPU time 149.88 seconds
Started Feb 21 12:43:39 PM PST 24
Finished Feb 21 12:46:10 PM PST 24
Peak memory 182612 kb
Host smart-6ae7732f-d5b0-4dda-997c-ff6d2fa35bbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607860700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1607860700
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.538629399
Short name T185
Test name
Test status
Simulation time 111149296298 ps
CPU time 249.1 seconds
Started Feb 21 12:43:14 PM PST 24
Finished Feb 21 12:47:24 PM PST 24
Peak memory 194340 kb
Host smart-9836caac-5f6f-445b-9d2e-173d02e554f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538629399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.538629399
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.898441344
Short name T102
Test name
Test status
Simulation time 203549837791 ps
CPU time 53.94 seconds
Started Feb 21 12:43:19 PM PST 24
Finished Feb 21 12:44:14 PM PST 24
Peak memory 190948 kb
Host smart-1e10547f-7247-4a96-9d85-195a9cd3c8e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898441344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.898441344
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2002626981
Short name T331
Test name
Test status
Simulation time 335574243210 ps
CPU time 184.26 seconds
Started Feb 21 12:42:36 PM PST 24
Finished Feb 21 12:45:41 PM PST 24
Peak memory 182760 kb
Host smart-2f774150-77f8-45fd-b6d2-2e190ed1a4d5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002626981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2002626981
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1552859780
Short name T361
Test name
Test status
Simulation time 37340440266 ps
CPU time 55.65 seconds
Started Feb 21 12:42:37 PM PST 24
Finished Feb 21 12:43:34 PM PST 24
Peak memory 182732 kb
Host smart-5e733a3d-82eb-4fd3-a8b8-a9e490565920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552859780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1552859780
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.2448941561
Short name T218
Test name
Test status
Simulation time 35736280357 ps
CPU time 52.31 seconds
Started Feb 21 12:42:39 PM PST 24
Finished Feb 21 12:43:32 PM PST 24
Peak memory 190920 kb
Host smart-97ce0e6c-3130-4c7d-a3d6-e618de9a6834
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448941561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2448941561
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.816192561
Short name T380
Test name
Test status
Simulation time 675852977 ps
CPU time 1.48 seconds
Started Feb 21 12:42:36 PM PST 24
Finished Feb 21 12:42:39 PM PST 24
Peak memory 182504 kb
Host smart-fe8f9da6-0501-4a3f-9877-063de6804409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816192561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.816192561
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.3605126374
Short name T14
Test name
Test status
Simulation time 16378402977 ps
CPU time 179.05 seconds
Started Feb 21 12:43:01 PM PST 24
Finished Feb 21 12:46:00 PM PST 24
Peak memory 197476 kb
Host smart-4f8b0fa3-5e85-4fad-8310-e6c88882f470
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605126374 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.3605126374
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.824330119
Short name T320
Test name
Test status
Simulation time 625881857577 ps
CPU time 772.55 seconds
Started Feb 21 12:43:12 PM PST 24
Finished Feb 21 12:56:06 PM PST 24
Peak memory 193108 kb
Host smart-91e93b10-b88c-431a-b72b-1def6fdc0eec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824330119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.824330119
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.1805898263
Short name T208
Test name
Test status
Simulation time 204667693723 ps
CPU time 254.09 seconds
Started Feb 21 12:43:34 PM PST 24
Finished Feb 21 12:47:48 PM PST 24
Peak memory 194464 kb
Host smart-6d25e9d1-60da-444a-ab38-e1b0889bd323
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805898263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1805898263
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.2478124359
Short name T93
Test name
Test status
Simulation time 287272903091 ps
CPU time 717.54 seconds
Started Feb 21 12:43:28 PM PST 24
Finished Feb 21 12:55:26 PM PST 24
Peak memory 194148 kb
Host smart-1c49f6cf-2d98-41a4-a65f-d0e752dbaac8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478124359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2478124359
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3922269080
Short name T295
Test name
Test status
Simulation time 23512605980 ps
CPU time 40.43 seconds
Started Feb 21 12:43:25 PM PST 24
Finished Feb 21 12:44:06 PM PST 24
Peak memory 192976 kb
Host smart-0e532431-ef9b-4af7-874a-d0fac8353715
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922269080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3922269080
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.4079559348
Short name T192
Test name
Test status
Simulation time 95951563188 ps
CPU time 826.74 seconds
Started Feb 21 12:43:48 PM PST 24
Finished Feb 21 12:57:39 PM PST 24
Peak memory 182748 kb
Host smart-f599a8a4-7985-4798-972c-0a071417b99b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079559348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.4079559348
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.597306827
Short name T201
Test name
Test status
Simulation time 49219248045 ps
CPU time 417.96 seconds
Started Feb 21 12:43:15 PM PST 24
Finished Feb 21 12:50:14 PM PST 24
Peak memory 190944 kb
Host smart-c3a29714-a0b8-4210-98fc-731de0250e45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597306827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.597306827
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.2913321666
Short name T273
Test name
Test status
Simulation time 42154620469 ps
CPU time 23.79 seconds
Started Feb 21 12:43:48 PM PST 24
Finished Feb 21 12:44:17 PM PST 24
Peak memory 182740 kb
Host smart-9acc925c-c59d-4ce9-95f2-f17f64cdef63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913321666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2913321666
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.1884014406
Short name T446
Test name
Test status
Simulation time 65818511984 ps
CPU time 87.92 seconds
Started Feb 21 12:42:56 PM PST 24
Finished Feb 21 12:44:25 PM PST 24
Peak memory 182656 kb
Host smart-03768817-32d3-4813-9515-e3de9cf5d45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884014406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1884014406
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.2499781938
Short name T308
Test name
Test status
Simulation time 377268586020 ps
CPU time 378.67 seconds
Started Feb 21 12:42:36 PM PST 24
Finished Feb 21 12:48:56 PM PST 24
Peak memory 182756 kb
Host smart-d78d5c40-eaae-40b8-bcdf-872712f581e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499781938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.2499781938
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.880055810
Short name T412
Test name
Test status
Simulation time 39184014338 ps
CPU time 25.98 seconds
Started Feb 21 12:42:37 PM PST 24
Finished Feb 21 12:43:04 PM PST 24
Peak memory 194068 kb
Host smart-6e9b8694-859d-401f-b9eb-1453ab5d3df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880055810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.880055810
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2811979136
Short name T52
Test name
Test status
Simulation time 373130644 ps
CPU time 0.67 seconds
Started Feb 21 12:42:37 PM PST 24
Finished Feb 21 12:42:39 PM PST 24
Peak memory 181768 kb
Host smart-b2fa5bf6-3331-401c-b401-0a162eec51e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811979136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2811979136
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.3580164464
Short name T436
Test name
Test status
Simulation time 51296331924 ps
CPU time 19.11 seconds
Started Feb 21 12:43:41 PM PST 24
Finished Feb 21 12:44:01 PM PST 24
Peak memory 182800 kb
Host smart-05f90536-d6de-4e6e-8ffc-0552e91c0242
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580164464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3580164464
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.1364850806
Short name T179
Test name
Test status
Simulation time 94358806355 ps
CPU time 385.35 seconds
Started Feb 21 12:43:41 PM PST 24
Finished Feb 21 12:50:07 PM PST 24
Peak memory 192972 kb
Host smart-d91b28a7-a0a0-4f2d-8574-2d1d97033fb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364850806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1364850806
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.648810695
Short name T215
Test name
Test status
Simulation time 551114430 ps
CPU time 0.73 seconds
Started Feb 21 12:43:42 PM PST 24
Finished Feb 21 12:43:45 PM PST 24
Peak memory 182328 kb
Host smart-1e770c48-10b6-47f3-ac14-a1312128e9f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648810695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.648810695
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.1763861491
Short name T163
Test name
Test status
Simulation time 419729244778 ps
CPU time 305.7 seconds
Started Feb 21 12:43:43 PM PST 24
Finished Feb 21 12:48:50 PM PST 24
Peak memory 191000 kb
Host smart-3083b6d0-f34b-4531-b650-646516a1eea8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763861491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1763861491
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3787268072
Short name T228
Test name
Test status
Simulation time 58973264653 ps
CPU time 100.63 seconds
Started Feb 21 12:43:38 PM PST 24
Finished Feb 21 12:45:19 PM PST 24
Peak memory 191184 kb
Host smart-04a983b2-8203-4084-b698-80b928fbb076
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787268072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3787268072
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2884745297
Short name T113
Test name
Test status
Simulation time 218160594714 ps
CPU time 182.55 seconds
Started Feb 21 12:43:43 PM PST 24
Finished Feb 21 12:46:48 PM PST 24
Peak memory 190972 kb
Host smart-a6d8fcd0-972a-48ca-886a-d149feffc22f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884745297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2884745297
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.728644206
Short name T283
Test name
Test status
Simulation time 255700671334 ps
CPU time 1166.16 seconds
Started Feb 21 12:43:28 PM PST 24
Finished Feb 21 01:02:54 PM PST 24
Peak memory 190932 kb
Host smart-45785e89-eece-4741-8a6a-b23c76c0a467
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728644206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.728644206
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3438008896
Short name T175
Test name
Test status
Simulation time 112065131919 ps
CPU time 434.73 seconds
Started Feb 21 12:43:37 PM PST 24
Finished Feb 21 12:50:52 PM PST 24
Peak memory 190956 kb
Host smart-18add812-a4ed-45b2-8f94-1df00cf9c396
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438008896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3438008896
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.31424481
Short name T101
Test name
Test status
Simulation time 237440220558 ps
CPU time 194.96 seconds
Started Feb 21 12:43:45 PM PST 24
Finished Feb 21 12:47:04 PM PST 24
Peak memory 190856 kb
Host smart-e3402309-aa18-4062-ae35-5bfd4a23af04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31424481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.31424481
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1108873013
Short name T281
Test name
Test status
Simulation time 89496670190 ps
CPU time 132.94 seconds
Started Feb 21 12:42:59 PM PST 24
Finished Feb 21 12:45:12 PM PST 24
Peak memory 182768 kb
Host smart-90fbcff9-d804-4c28-9bef-012bd3e7683d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108873013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1108873013
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.286472844
Short name T3
Test name
Test status
Simulation time 133250555903 ps
CPU time 185 seconds
Started Feb 21 12:42:45 PM PST 24
Finished Feb 21 12:45:50 PM PST 24
Peak memory 182652 kb
Host smart-a47e93ce-9b1e-473b-ba97-04ea269a800e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286472844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.286472844
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.152356108
Short name T313
Test name
Test status
Simulation time 8859636523 ps
CPU time 12.62 seconds
Started Feb 21 12:42:55 PM PST 24
Finished Feb 21 12:43:08 PM PST 24
Peak memory 182728 kb
Host smart-b24d742f-ae01-4330-8a9f-11750c59366a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152356108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.152356108
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3155178419
Short name T159
Test name
Test status
Simulation time 170409342430 ps
CPU time 60.1 seconds
Started Feb 21 12:42:45 PM PST 24
Finished Feb 21 12:43:45 PM PST 24
Peak memory 182764 kb
Host smart-100adaf7-f5b9-46ee-844a-c7ac321c387a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155178419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3155178419
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2958416697
Short name T206
Test name
Test status
Simulation time 656231916363 ps
CPU time 234.77 seconds
Started Feb 21 12:42:46 PM PST 24
Finished Feb 21 12:46:41 PM PST 24
Peak memory 190948 kb
Host smart-5e09bb7f-acb3-48ea-8fd1-b1bf4ee7460f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958416697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2958416697
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.2240203885
Short name T44
Test name
Test status
Simulation time 9119636411 ps
CPU time 64.55 seconds
Started Feb 21 12:42:36 PM PST 24
Finished Feb 21 12:43:42 PM PST 24
Peak memory 197532 kb
Host smart-64a41f96-588b-4ba9-8bc8-b14c32184197
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240203885 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.2240203885
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/171.rv_timer_random.1012256492
Short name T128
Test name
Test status
Simulation time 395557152538 ps
CPU time 267.92 seconds
Started Feb 21 12:43:54 PM PST 24
Finished Feb 21 12:48:24 PM PST 24
Peak memory 191164 kb
Host smart-2959c213-0e3c-4d0f-bcd5-c3d1578deb60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012256492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1012256492
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3732246844
Short name T443
Test name
Test status
Simulation time 67178918578 ps
CPU time 158.74 seconds
Started Feb 21 12:43:15 PM PST 24
Finished Feb 21 12:45:55 PM PST 24
Peak memory 190916 kb
Host smart-f826e08a-ceef-4f21-8fc9-cd72e6907743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732246844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3732246844
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.2462090023
Short name T9
Test name
Test status
Simulation time 144236122855 ps
CPU time 200.83 seconds
Started Feb 21 12:43:08 PM PST 24
Finished Feb 21 12:46:29 PM PST 24
Peak memory 190972 kb
Host smart-cd4a8c5c-ee1a-41cb-bbef-f004483406c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462090023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2462090023
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2652754949
Short name T162
Test name
Test status
Simulation time 109053715447 ps
CPU time 294.66 seconds
Started Feb 21 12:43:22 PM PST 24
Finished Feb 21 12:48:17 PM PST 24
Peak memory 190936 kb
Host smart-96031554-b84f-4890-a73a-04aa98d95a7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652754949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2652754949
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3090948616
Short name T223
Test name
Test status
Simulation time 498553544963 ps
CPU time 643.75 seconds
Started Feb 21 12:43:54 PM PST 24
Finished Feb 21 12:54:40 PM PST 24
Peak memory 191164 kb
Host smart-d2efd193-28f9-49b0-839e-c3a5da77da4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090948616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3090948616
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.3191160421
Short name T336
Test name
Test status
Simulation time 53293395881 ps
CPU time 115.67 seconds
Started Feb 21 12:43:12 PM PST 24
Finished Feb 21 12:45:09 PM PST 24
Peak memory 190876 kb
Host smart-bb156cde-61c9-4caf-8aa2-167bd9b98dfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191160421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3191160421
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.715518835
Short name T122
Test name
Test status
Simulation time 196117673078 ps
CPU time 409.97 seconds
Started Feb 21 12:43:05 PM PST 24
Finished Feb 21 12:49:55 PM PST 24
Peak memory 194320 kb
Host smart-e200f06c-e02e-4140-a89d-6c742b7be76a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715518835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.715518835
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2815224274
Short name T442
Test name
Test status
Simulation time 112326558868 ps
CPU time 175.22 seconds
Started Feb 21 12:42:38 PM PST 24
Finished Feb 21 12:45:34 PM PST 24
Peak memory 182572 kb
Host smart-09f5b4f5-65a4-408d-b201-21d88b9380d5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815224274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.2815224274
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.3776143736
Short name T420
Test name
Test status
Simulation time 300032404614 ps
CPU time 118.43 seconds
Started Feb 21 12:42:42 PM PST 24
Finished Feb 21 12:44:41 PM PST 24
Peak memory 182712 kb
Host smart-d4dd362b-57ab-4a6a-966a-6626f8b5768e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776143736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3776143736
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.505260886
Short name T165
Test name
Test status
Simulation time 393534426309 ps
CPU time 329.42 seconds
Started Feb 21 12:42:48 PM PST 24
Finished Feb 21 12:48:18 PM PST 24
Peak memory 193412 kb
Host smart-255a7545-cd3b-48f8-8340-2e5c133f93fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505260886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.505260886
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3181004778
Short name T70
Test name
Test status
Simulation time 403710431 ps
CPU time 1.64 seconds
Started Feb 21 12:43:00 PM PST 24
Finished Feb 21 12:43:02 PM PST 24
Peak memory 182420 kb
Host smart-7bd0f8ac-4c4b-447e-93ad-2f3670c177b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181004778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3181004778
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.4248401068
Short name T143
Test name
Test status
Simulation time 4221169382106 ps
CPU time 1165.09 seconds
Started Feb 21 12:43:00 PM PST 24
Finished Feb 21 01:02:25 PM PST 24
Peak memory 195276 kb
Host smart-cf9e774f-d6c7-4a06-be4d-30d37b33d094
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248401068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.4248401068
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.3129293217
Short name T235
Test name
Test status
Simulation time 377730868868 ps
CPU time 237.12 seconds
Started Feb 21 12:43:18 PM PST 24
Finished Feb 21 12:47:15 PM PST 24
Peak memory 190852 kb
Host smart-32c6b21a-caad-4afa-9452-c7cb72f1f02c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129293217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3129293217
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.1420350319
Short name T232
Test name
Test status
Simulation time 614571261890 ps
CPU time 415.91 seconds
Started Feb 21 12:43:09 PM PST 24
Finished Feb 21 12:50:06 PM PST 24
Peak memory 190972 kb
Host smart-907805cb-6d01-44bd-a33d-2a46729a6616
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420350319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1420350319
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.3201696614
Short name T302
Test name
Test status
Simulation time 121943084759 ps
CPU time 94.31 seconds
Started Feb 21 12:43:13 PM PST 24
Finished Feb 21 12:44:58 PM PST 24
Peak memory 190848 kb
Host smart-11c6d2b5-77fc-4182-b64d-99d9c132f1d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201696614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3201696614
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.2072499117
Short name T333
Test name
Test status
Simulation time 6593014165 ps
CPU time 6.73 seconds
Started Feb 21 12:43:28 PM PST 24
Finished Feb 21 12:43:36 PM PST 24
Peak memory 182460 kb
Host smart-65e757bf-8387-40fd-a203-943849f8cdac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072499117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2072499117
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1767635765
Short name T110
Test name
Test status
Simulation time 191413882847 ps
CPU time 125.92 seconds
Started Feb 21 12:43:10 PM PST 24
Finished Feb 21 12:45:17 PM PST 24
Peak memory 193160 kb
Host smart-03aadfa8-91e7-4336-9a8a-aab671460d05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767635765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1767635765
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1318902317
Short name T120
Test name
Test status
Simulation time 106593172456 ps
CPU time 75.16 seconds
Started Feb 21 12:43:16 PM PST 24
Finished Feb 21 12:44:32 PM PST 24
Peak memory 182744 kb
Host smart-a7c5723f-644d-4686-bf63-e0a964d22642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318902317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1318902317
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.2997343797
Short name T209
Test name
Test status
Simulation time 32922885593 ps
CPU time 64.93 seconds
Started Feb 21 12:43:30 PM PST 24
Finished Feb 21 12:44:35 PM PST 24
Peak memory 182744 kb
Host smart-f3192ed6-8ceb-463a-abdf-b2e78fd14786
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997343797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2997343797
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1577426477
Short name T428
Test name
Test status
Simulation time 5370546534 ps
CPU time 8.48 seconds
Started Feb 21 12:43:26 PM PST 24
Finished Feb 21 12:43:35 PM PST 24
Peak memory 182616 kb
Host smart-e9864a0f-f8ba-4bf7-b574-a56fcab187a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577426477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1577426477
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2899681168
Short name T182
Test name
Test status
Simulation time 63906821692 ps
CPU time 115.3 seconds
Started Feb 21 12:42:59 PM PST 24
Finished Feb 21 12:44:55 PM PST 24
Peak memory 182768 kb
Host smart-a601aa2a-fe76-47e5-ac6b-b1297e7c642e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899681168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2899681168
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1948228756
Short name T360
Test name
Test status
Simulation time 141823562745 ps
CPU time 109.57 seconds
Started Feb 21 12:42:53 PM PST 24
Finished Feb 21 12:44:43 PM PST 24
Peak memory 182740 kb
Host smart-052ada73-97bd-44aa-924f-b80b727373b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948228756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1948228756
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.948491213
Short name T328
Test name
Test status
Simulation time 39387308365 ps
CPU time 226.92 seconds
Started Feb 21 12:43:00 PM PST 24
Finished Feb 21 12:46:47 PM PST 24
Peak memory 190984 kb
Host smart-56f0636a-ea0a-4824-ad98-d8020209866a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948491213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.948491213
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.1510619517
Short name T204
Test name
Test status
Simulation time 159515465744 ps
CPU time 69.88 seconds
Started Feb 21 12:42:34 PM PST 24
Finished Feb 21 12:43:44 PM PST 24
Peak memory 190968 kb
Host smart-835d3797-d13b-450a-95bc-b8369a0db3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510619517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1510619517
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/192.rv_timer_random.4207905082
Short name T323
Test name
Test status
Simulation time 142932395828 ps
CPU time 628.65 seconds
Started Feb 21 12:43:17 PM PST 24
Finished Feb 21 12:53:46 PM PST 24
Peak memory 190944 kb
Host smart-a63d6c7f-d5c0-40d3-bde1-48ffd99a22cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207905082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.4207905082
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.2024877747
Short name T105
Test name
Test status
Simulation time 103411951986 ps
CPU time 304.13 seconds
Started Feb 21 12:43:34 PM PST 24
Finished Feb 21 12:48:39 PM PST 24
Peak memory 193384 kb
Host smart-833026ed-cba9-4070-8fc5-54e458da9653
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024877747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2024877747
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1377104862
Short name T296
Test name
Test status
Simulation time 237500000834 ps
CPU time 132.35 seconds
Started Feb 21 12:43:32 PM PST 24
Finished Feb 21 12:45:45 PM PST 24
Peak memory 190812 kb
Host smart-5fe15848-6f8f-47cf-8195-1a1816e59749
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377104862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1377104862
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1042638005
Short name T329
Test name
Test status
Simulation time 405561758436 ps
CPU time 452.62 seconds
Started Feb 21 12:43:14 PM PST 24
Finished Feb 21 12:50:48 PM PST 24
Peak memory 190856 kb
Host smart-598fc2a5-8b7a-4902-83c0-c2e172a5c477
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042638005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1042638005
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.51775249
Short name T106
Test name
Test status
Simulation time 86344815575 ps
CPU time 464 seconds
Started Feb 21 12:43:30 PM PST 24
Finished Feb 21 12:51:14 PM PST 24
Peak memory 194312 kb
Host smart-09514cae-0051-4b65-8305-b86d1478d1f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51775249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.51775249
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2759643914
Short name T112
Test name
Test status
Simulation time 159007044715 ps
CPU time 445.79 seconds
Started Feb 21 12:43:30 PM PST 24
Finished Feb 21 12:50:56 PM PST 24
Peak memory 192444 kb
Host smart-1ef8d342-7b6a-4848-beeb-40d3af17dd4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759643914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2759643914
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.184923424
Short name T317
Test name
Test status
Simulation time 40982177801 ps
CPU time 65.1 seconds
Started Feb 21 12:43:29 PM PST 24
Finished Feb 21 12:44:35 PM PST 24
Peak memory 182664 kb
Host smart-b74652ab-8a63-4064-9e24-1cef02ad4ced
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184923424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.184923424
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.3701959641
Short name T373
Test name
Test status
Simulation time 436185669077 ps
CPU time 188.41 seconds
Started Feb 21 12:42:33 PM PST 24
Finished Feb 21 12:45:42 PM PST 24
Peak memory 182720 kb
Host smart-d166d510-8803-4074-aecf-54c4b7f9da4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701959641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3701959641
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.484663073
Short name T290
Test name
Test status
Simulation time 153083445690 ps
CPU time 46.69 seconds
Started Feb 21 12:42:27 PM PST 24
Finished Feb 21 12:43:14 PM PST 24
Peak memory 190880 kb
Host smart-10c1cdb9-79a8-4a79-b1a1-518b88805142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484663073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.484663073
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3700870876
Short name T16
Test name
Test status
Simulation time 83323364 ps
CPU time 0.91 seconds
Started Feb 21 12:42:37 PM PST 24
Finished Feb 21 12:42:44 PM PST 24
Peak memory 214128 kb
Host smart-e75799d3-9232-4ab0-a451-22a9a578d1e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700870876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3700870876
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2868846748
Short name T434
Test name
Test status
Simulation time 2453639458510 ps
CPU time 1054.45 seconds
Started Feb 21 12:42:37 PM PST 24
Finished Feb 21 01:00:13 PM PST 24
Peak memory 190888 kb
Host smart-830d5d77-6dab-46ef-979e-32ba0e6f62a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868846748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2868846748
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.3402525567
Short name T28
Test name
Test status
Simulation time 528528729665 ps
CPU time 955.79 seconds
Started Feb 21 12:42:32 PM PST 24
Finished Feb 21 12:58:29 PM PST 24
Peak memory 211356 kb
Host smart-430f49f9-5059-459d-b589-1adc07e29e68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402525567 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.3402525567
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3204489565
Short name T109
Test name
Test status
Simulation time 378888834294 ps
CPU time 649.7 seconds
Started Feb 21 12:42:46 PM PST 24
Finished Feb 21 12:53:36 PM PST 24
Peak memory 182656 kb
Host smart-6a207e30-69b4-4553-8cbb-311d03eafbb6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204489565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.3204489565
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1421670808
Short name T64
Test name
Test status
Simulation time 48646060095 ps
CPU time 76.17 seconds
Started Feb 21 12:43:01 PM PST 24
Finished Feb 21 12:44:17 PM PST 24
Peak memory 182776 kb
Host smart-b6d53984-0725-4006-bbbf-903775eae0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421670808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1421670808
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.1711664658
Short name T437
Test name
Test status
Simulation time 237625378835 ps
CPU time 330.87 seconds
Started Feb 21 12:42:45 PM PST 24
Finished Feb 21 12:48:16 PM PST 24
Peak memory 190976 kb
Host smart-fc861e6b-969b-4d62-8c01-227692b2f689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711664658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1711664658
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.4190468899
Short name T174
Test name
Test status
Simulation time 67069519251 ps
CPU time 231.84 seconds
Started Feb 21 12:43:06 PM PST 24
Finished Feb 21 12:46:59 PM PST 24
Peak memory 190972 kb
Host smart-31dfda95-13ec-4169-88c8-6dce76618d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190468899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.4190468899
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2530656891
Short name T8
Test name
Test status
Simulation time 473619963525 ps
CPU time 232.31 seconds
Started Feb 21 12:42:36 PM PST 24
Finished Feb 21 12:46:29 PM PST 24
Peak memory 182660 kb
Host smart-cf251c3b-b03d-4425-a4f4-3e187ceed0c2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530656891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2530656891
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.828142797
Short name T365
Test name
Test status
Simulation time 100035104723 ps
CPU time 96.53 seconds
Started Feb 21 12:42:34 PM PST 24
Finished Feb 21 12:44:10 PM PST 24
Peak memory 182772 kb
Host smart-d7387e24-1ce0-4f8b-a5ee-f03d6eb6dc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828142797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.828142797
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.3281945309
Short name T40
Test name
Test status
Simulation time 107252021173 ps
CPU time 143.62 seconds
Started Feb 21 12:42:28 PM PST 24
Finished Feb 21 12:44:52 PM PST 24
Peak memory 190864 kb
Host smart-980c14d6-bae6-4cc9-b26d-594404462d1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281945309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3281945309
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.4206224275
Short name T319
Test name
Test status
Simulation time 421966240 ps
CPU time 4.88 seconds
Started Feb 21 12:42:53 PM PST 24
Finished Feb 21 12:42:59 PM PST 24
Peak memory 182696 kb
Host smart-ac3b32e7-96f4-40c0-b4eb-cd7de60dbd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206224275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.4206224275
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.930322220
Short name T30
Test name
Test status
Simulation time 127293636024 ps
CPU time 933 seconds
Started Feb 21 12:42:59 PM PST 24
Finished Feb 21 12:58:32 PM PST 24
Peak memory 208420 kb
Host smart-ebaaa6d8-bf3c-43cf-86c1-f2d95d563513
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930322220 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.930322220
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3871993122
Short name T385
Test name
Test status
Simulation time 27573642907 ps
CPU time 45.72 seconds
Started Feb 21 12:43:01 PM PST 24
Finished Feb 21 12:43:47 PM PST 24
Peak memory 182792 kb
Host smart-a7da0c48-2b77-446a-b9a0-eff477093039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871993122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3871993122
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.2041079966
Short name T130
Test name
Test status
Simulation time 199413288182 ps
CPU time 345.32 seconds
Started Feb 21 12:42:49 PM PST 24
Finished Feb 21 12:48:34 PM PST 24
Peak memory 190964 kb
Host smart-25f32614-87ec-4b26-ae26-9a95b0874f41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041079966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2041079966
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.4274385484
Short name T354
Test name
Test status
Simulation time 145538885 ps
CPU time 1.05 seconds
Started Feb 21 12:42:50 PM PST 24
Finished Feb 21 12:42:52 PM PST 24
Peak memory 190732 kb
Host smart-6e0a1e0f-c545-4b3d-b97d-ac718996eef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274385484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.4274385484
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.308459008
Short name T99
Test name
Test status
Simulation time 343052372893 ps
CPU time 510.73 seconds
Started Feb 21 12:42:36 PM PST 24
Finished Feb 21 12:51:08 PM PST 24
Peak memory 190992 kb
Host smart-6495f6f1-9c59-43a5-bbe4-5ed8728feca7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308459008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.
308459008
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1974600964
Short name T5
Test name
Test status
Simulation time 92012307149 ps
CPU time 23.29 seconds
Started Feb 21 12:42:36 PM PST 24
Finished Feb 21 12:43:01 PM PST 24
Peak memory 182692 kb
Host smart-9b18effa-597b-497d-be03-9b9c8346cbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974600964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1974600964
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.930657477
Short name T396
Test name
Test status
Simulation time 33179409 ps
CPU time 0.58 seconds
Started Feb 21 12:42:49 PM PST 24
Finished Feb 21 12:42:50 PM PST 24
Peak memory 182432 kb
Host smart-5ef97db1-2e07-42e8-b1f4-9c164da0f9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930657477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.930657477
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.4003415464
Short name T417
Test name
Test status
Simulation time 140687812466 ps
CPU time 163.62 seconds
Started Feb 21 12:42:32 PM PST 24
Finished Feb 21 12:45:16 PM PST 24
Peak memory 182760 kb
Host smart-690b0ea1-ce37-491a-9c4d-f7074212ebd2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003415464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.4003415464
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3776795257
Short name T376
Test name
Test status
Simulation time 169461453910 ps
CPU time 65.57 seconds
Started Feb 21 12:42:42 PM PST 24
Finished Feb 21 12:43:48 PM PST 24
Peak memory 182548 kb
Host smart-72f4887a-fa29-4ccd-bd63-83118edd4cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776795257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3776795257
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.3313080287
Short name T284
Test name
Test status
Simulation time 47083642710 ps
CPU time 256.95 seconds
Started Feb 21 12:42:43 PM PST 24
Finished Feb 21 12:47:00 PM PST 24
Peak memory 190892 kb
Host smart-f200008e-0fb1-4ad5-9822-3f133ea34c3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313080287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3313080287
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.457432766
Short name T312
Test name
Test status
Simulation time 806705230706 ps
CPU time 173.01 seconds
Started Feb 21 12:42:52 PM PST 24
Finished Feb 21 12:45:46 PM PST 24
Peak memory 190980 kb
Host smart-4c3c19f7-6cac-4666-9623-4faad57afa4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457432766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.457432766
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.258310936
Short name T352
Test name
Test status
Simulation time 130326805222 ps
CPU time 192.39 seconds
Started Feb 21 12:42:46 PM PST 24
Finished Feb 21 12:45:59 PM PST 24
Peak memory 190976 kb
Host smart-e8d81eab-22d5-4755-9b51-976e69174f66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258310936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
258310936
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.1013665068
Short name T33
Test name
Test status
Simulation time 35830951661 ps
CPU time 241.4 seconds
Started Feb 21 12:43:02 PM PST 24
Finished Feb 21 12:47:04 PM PST 24
Peak memory 205576 kb
Host smart-29ed0892-2917-4f77-b060-580948bca4f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013665068 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.1013665068
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2455054390
Short name T263
Test name
Test status
Simulation time 18903231844 ps
CPU time 16.83 seconds
Started Feb 21 12:43:01 PM PST 24
Finished Feb 21 12:43:18 PM PST 24
Peak memory 182788 kb
Host smart-231d6761-2116-488d-88fd-2c86ccfb7d38
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455054390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2455054390
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.493519194
Short name T369
Test name
Test status
Simulation time 13390742421 ps
CPU time 18.12 seconds
Started Feb 21 12:42:50 PM PST 24
Finished Feb 21 12:43:09 PM PST 24
Peak memory 182756 kb
Host smart-ba863b61-0b6c-4e9b-bfdd-3c101c714a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493519194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.493519194
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.3513235988
Short name T266
Test name
Test status
Simulation time 159220344080 ps
CPU time 615.82 seconds
Started Feb 21 12:42:37 PM PST 24
Finished Feb 21 12:52:54 PM PST 24
Peak memory 190960 kb
Host smart-01bf416c-4c1c-4de6-ae9d-ffcfd18e961a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513235988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3513235988
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.2856210149
Short name T62
Test name
Test status
Simulation time 376511794 ps
CPU time 1.16 seconds
Started Feb 21 12:42:42 PM PST 24
Finished Feb 21 12:42:43 PM PST 24
Peak memory 182380 kb
Host smart-be2015d6-826c-4ff8-9040-9f93098f165a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856210149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2856210149
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.310054367
Short name T371
Test name
Test status
Simulation time 1686425363361 ps
CPU time 1063.96 seconds
Started Feb 21 12:42:40 PM PST 24
Finished Feb 21 01:00:25 PM PST 24
Peak memory 190992 kb
Host smart-b34336e3-e0e4-4232-b315-57228c4cdbbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310054367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.
310054367
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2311854720
Short name T372
Test name
Test status
Simulation time 240886767682 ps
CPU time 177.19 seconds
Started Feb 21 12:42:59 PM PST 24
Finished Feb 21 12:45:57 PM PST 24
Peak memory 182756 kb
Host smart-fe45ea99-7fa6-4d3c-b97b-0f2f9b5388b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311854720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2311854720
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.535315846
Short name T279
Test name
Test status
Simulation time 131975991554 ps
CPU time 183.79 seconds
Started Feb 21 12:42:42 PM PST 24
Finished Feb 21 12:45:46 PM PST 24
Peak memory 194184 kb
Host smart-8f48f2ed-159f-4cb4-ad2a-05bb09aa8c98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535315846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.535315846
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3469616927
Short name T431
Test name
Test status
Simulation time 19591623 ps
CPU time 0.52 seconds
Started Feb 21 12:42:51 PM PST 24
Finished Feb 21 12:42:53 PM PST 24
Peak memory 182304 kb
Host smart-fd3ced14-4a5a-4220-bdd5-475c3be12ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469616927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3469616927
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3207581373
Short name T422
Test name
Test status
Simulation time 1049237546190 ps
CPU time 523.03 seconds
Started Feb 21 12:42:41 PM PST 24
Finished Feb 21 12:51:25 PM PST 24
Peak memory 194964 kb
Host smart-2e227f61-8464-4e89-b333-9a7568036437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207581373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3207581373
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2403174412
Short name T368
Test name
Test status
Simulation time 121464585682 ps
CPU time 172.36 seconds
Started Feb 21 12:43:04 PM PST 24
Finished Feb 21 12:45:56 PM PST 24
Peak memory 182772 kb
Host smart-dac3b80a-686d-4c9e-b1f8-3b9693722547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403174412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2403174412
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.2688108773
Short name T12
Test name
Test status
Simulation time 123052388428 ps
CPU time 306.66 seconds
Started Feb 21 12:43:02 PM PST 24
Finished Feb 21 12:48:09 PM PST 24
Peak memory 190968 kb
Host smart-6a868933-dfe3-4403-8f46-506680df9c32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688108773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2688108773
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3790570331
Short name T426
Test name
Test status
Simulation time 7182109910 ps
CPU time 11.47 seconds
Started Feb 21 12:42:44 PM PST 24
Finished Feb 21 12:42:56 PM PST 24
Peak memory 182764 kb
Host smart-f14f4881-1312-4e2e-a8b9-2129d1ece10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790570331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3790570331
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.1640918868
Short name T60
Test name
Test status
Simulation time 442030180824 ps
CPU time 205.02 seconds
Started Feb 21 12:42:55 PM PST 24
Finished Feb 21 12:46:21 PM PST 24
Peak memory 190952 kb
Host smart-6391256b-fc8b-450a-8b55-37956689c99c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640918868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.1640918868
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.2657080492
Short name T399
Test name
Test status
Simulation time 5808276803 ps
CPU time 62.61 seconds
Started Feb 21 12:42:58 PM PST 24
Finished Feb 21 12:44:02 PM PST 24
Peak memory 197460 kb
Host smart-c8b91e14-6f39-4aeb-ba5a-5b2d348eb362
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657080492 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.2657080492
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2882282203
Short name T439
Test name
Test status
Simulation time 694562443968 ps
CPU time 392.74 seconds
Started Feb 21 12:42:41 PM PST 24
Finished Feb 21 12:49:14 PM PST 24
Peak memory 182720 kb
Host smart-c73e287c-efac-4e07-8bd0-25b9427f2737
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882282203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2882282203
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.1026776703
Short name T402
Test name
Test status
Simulation time 8099514164 ps
CPU time 13.51 seconds
Started Feb 21 12:42:41 PM PST 24
Finished Feb 21 12:42:55 PM PST 24
Peak memory 182772 kb
Host smart-2edbe6d9-b349-4717-b1cc-74898526680c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026776703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1026776703
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1358781172
Short name T407
Test name
Test status
Simulation time 19228732234 ps
CPU time 18.04 seconds
Started Feb 21 12:42:58 PM PST 24
Finished Feb 21 12:43:17 PM PST 24
Peak memory 182692 kb
Host smart-d9bc9d5c-8083-4a16-9fe6-9a488e2eee09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358781172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1358781172
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.944816141
Short name T10
Test name
Test status
Simulation time 710607913362 ps
CPU time 1655.88 seconds
Started Feb 21 12:42:53 PM PST 24
Finished Feb 21 01:10:30 PM PST 24
Peak memory 193116 kb
Host smart-82380daa-9439-40c8-8648-cd35202dc2ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944816141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.
944816141
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1324719590
Short name T270
Test name
Test status
Simulation time 8507966021221 ps
CPU time 2107.17 seconds
Started Feb 21 12:42:56 PM PST 24
Finished Feb 21 01:18:04 PM PST 24
Peak memory 182768 kb
Host smart-96c68600-6bab-4341-8814-ad9e387d3100
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324719590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1324719590
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.19342761
Short name T432
Test name
Test status
Simulation time 182468306028 ps
CPU time 74.14 seconds
Started Feb 21 12:42:52 PM PST 24
Finished Feb 21 12:44:08 PM PST 24
Peak memory 182748 kb
Host smart-9ba0e6ed-ff41-4356-922f-b1c314dd59bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19342761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.19342761
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.2059496635
Short name T222
Test name
Test status
Simulation time 143695948320 ps
CPU time 886.69 seconds
Started Feb 21 12:42:52 PM PST 24
Finished Feb 21 12:57:40 PM PST 24
Peak memory 190992 kb
Host smart-b78f26fd-38f7-46f2-bc8f-2d2305e89561
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059496635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2059496635
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1464926469
Short name T210
Test name
Test status
Simulation time 284978556450 ps
CPU time 124.18 seconds
Started Feb 21 12:42:57 PM PST 24
Finished Feb 21 12:45:02 PM PST 24
Peak memory 190952 kb
Host smart-a9e765f7-401c-474b-887c-bcb25317d427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464926469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1464926469
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.3492367355
Short name T57
Test name
Test status
Simulation time 222430028736 ps
CPU time 306.31 seconds
Started Feb 21 12:42:48 PM PST 24
Finished Feb 21 12:47:55 PM PST 24
Peak memory 182800 kb
Host smart-e4053d3c-403c-4013-a7b8-bf02849eef6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492367355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.3492367355
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2786680957
Short name T254
Test name
Test status
Simulation time 396401807326 ps
CPU time 727.21 seconds
Started Feb 21 12:42:50 PM PST 24
Finished Feb 21 12:54:57 PM PST 24
Peak memory 182764 kb
Host smart-551fb3da-5847-45f2-b4a7-fbba519d5825
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786680957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2786680957
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2180512949
Short name T379
Test name
Test status
Simulation time 857895721872 ps
CPU time 160.22 seconds
Started Feb 21 12:42:21 PM PST 24
Finished Feb 21 12:45:02 PM PST 24
Peak memory 182752 kb
Host smart-962690bc-c79e-4d04-b8d7-75bd942651b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180512949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2180512949
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.3244061990
Short name T156
Test name
Test status
Simulation time 323909440429 ps
CPU time 169.97 seconds
Started Feb 21 12:42:19 PM PST 24
Finished Feb 21 12:45:09 PM PST 24
Peak memory 190948 kb
Host smart-172ac18f-7dda-4359-9182-b1c2ad6ae66c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244061990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3244061990
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.879871688
Short name T167
Test name
Test status
Simulation time 493465269504 ps
CPU time 238.29 seconds
Started Feb 21 12:42:29 PM PST 24
Finished Feb 21 12:46:27 PM PST 24
Peak memory 190876 kb
Host smart-41ee1bf8-7ff5-44b0-8edf-b2c966bb84a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879871688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.879871688
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3157021348
Short name T17
Test name
Test status
Simulation time 219977937 ps
CPU time 0.9 seconds
Started Feb 21 12:42:34 PM PST 24
Finished Feb 21 12:42:36 PM PST 24
Peak memory 213908 kb
Host smart-596dc949-c5a1-49db-b0cb-6acc98dc9e26
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157021348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3157021348
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2744350970
Short name T24
Test name
Test status
Simulation time 139509213455 ps
CPU time 235.97 seconds
Started Feb 21 12:42:43 PM PST 24
Finished Feb 21 12:46:39 PM PST 24
Peak memory 194644 kb
Host smart-9e80e0db-27c8-4198-afc5-08d5796122c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744350970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2744350970
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.1224618550
Short name T38
Test name
Test status
Simulation time 82305293262 ps
CPU time 46.72 seconds
Started Feb 21 12:42:40 PM PST 24
Finished Feb 21 12:43:27 PM PST 24
Peak memory 182748 kb
Host smart-3a4927cf-7980-4893-813d-326bfcfa3fa1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224618550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.1224618550
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1646821990
Short name T390
Test name
Test status
Simulation time 263041835294 ps
CPU time 97.56 seconds
Started Feb 21 12:42:56 PM PST 24
Finished Feb 21 12:44:35 PM PST 24
Peak memory 182724 kb
Host smart-a0c04e52-75ed-490f-b0e8-155f9a19613c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646821990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1646821990
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.3632840240
Short name T95
Test name
Test status
Simulation time 58651664131 ps
CPU time 154.74 seconds
Started Feb 21 12:42:56 PM PST 24
Finished Feb 21 12:45:32 PM PST 24
Peak memory 194220 kb
Host smart-ac41e84a-b38e-452a-80ac-0dc3e3ca20bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632840240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3632840240
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1731374445
Short name T397
Test name
Test status
Simulation time 118717898 ps
CPU time 0.51 seconds
Started Feb 21 12:43:00 PM PST 24
Finished Feb 21 12:43:01 PM PST 24
Peak memory 182356 kb
Host smart-724d7d71-1b04-4517-8e4e-2a9722796231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731374445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1731374445
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.3498154746
Short name T32
Test name
Test status
Simulation time 30036863236 ps
CPU time 244.71 seconds
Started Feb 21 12:42:58 PM PST 24
Finished Feb 21 12:47:04 PM PST 24
Peak memory 197512 kb
Host smart-527b64c5-d3e7-4f5b-9666-51827cce90ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498154746 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.3498154746
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3945985265
Short name T115
Test name
Test status
Simulation time 11069834264 ps
CPU time 17.76 seconds
Started Feb 21 12:43:00 PM PST 24
Finished Feb 21 12:43:18 PM PST 24
Peak memory 182776 kb
Host smart-b3732fba-c22a-4eeb-a1a5-271c475b7c5d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945985265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3945985265
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1142677976
Short name T393
Test name
Test status
Simulation time 271766354382 ps
CPU time 109.44 seconds
Started Feb 21 12:43:06 PM PST 24
Finished Feb 21 12:44:56 PM PST 24
Peak memory 182792 kb
Host smart-3e6ba6b5-ad70-46c9-88f7-08c6f9fbac4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142677976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1142677976
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.3512436328
Short name T293
Test name
Test status
Simulation time 201619315707 ps
CPU time 168 seconds
Started Feb 21 12:42:58 PM PST 24
Finished Feb 21 12:45:47 PM PST 24
Peak memory 194244 kb
Host smart-73397486-7cd5-4aff-a110-51974b312c45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512436328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3512436328
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.1645816916
Short name T386
Test name
Test status
Simulation time 5415027878 ps
CPU time 10.3 seconds
Started Feb 21 12:42:38 PM PST 24
Finished Feb 21 12:42:49 PM PST 24
Peak memory 182768 kb
Host smart-be5fcc7d-f359-4dd7-b612-6c9b95c672ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645816916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1645816916
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2146311102
Short name T249
Test name
Test status
Simulation time 429751145596 ps
CPU time 268.33 seconds
Started Feb 21 12:43:03 PM PST 24
Finished Feb 21 12:47:32 PM PST 24
Peak memory 182692 kb
Host smart-7a0c67de-2b80-4dd4-9526-3ecc7f2e96e0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146311102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2146311102
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.500375646
Short name T441
Test name
Test status
Simulation time 153603377071 ps
CPU time 60.05 seconds
Started Feb 21 12:42:59 PM PST 24
Finished Feb 21 12:43:59 PM PST 24
Peak memory 182772 kb
Host smart-adf59708-d5aa-481e-aa13-07a48f420dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500375646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.500375646
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.3643230997
Short name T408
Test name
Test status
Simulation time 4436065776 ps
CPU time 7.54 seconds
Started Feb 21 12:42:52 PM PST 24
Finished Feb 21 12:43:01 PM PST 24
Peak memory 182732 kb
Host smart-7dd9a973-a693-4e8c-b5b5-e8261f807279
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643230997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.3643230997
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.2555494653
Short name T326
Test name
Test status
Simulation time 141523563208 ps
CPU time 132.96 seconds
Started Feb 21 12:42:39 PM PST 24
Finished Feb 21 12:44:53 PM PST 24
Peak memory 182800 kb
Host smart-4b4b1e2f-c3a2-4ca4-972a-d2081cef473d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555494653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2555494653
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.1709995096
Short name T300
Test name
Test status
Simulation time 746054713241 ps
CPU time 305.36 seconds
Started Feb 21 12:43:06 PM PST 24
Finished Feb 21 12:48:11 PM PST 24
Peak memory 194408 kb
Host smart-525a592d-260a-4c01-bbda-d97e0048220d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709995096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.1709995096
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_random.2105424055
Short name T282
Test name
Test status
Simulation time 283058923321 ps
CPU time 1794.9 seconds
Started Feb 21 12:43:04 PM PST 24
Finished Feb 21 01:12:59 PM PST 24
Peak memory 190956 kb
Host smart-10e18398-c703-4f1f-9b75-c6ed222804ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105424055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2105424055
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.825385794
Short name T253
Test name
Test status
Simulation time 66537175947 ps
CPU time 36.67 seconds
Started Feb 21 12:43:01 PM PST 24
Finished Feb 21 12:43:38 PM PST 24
Peak memory 182736 kb
Host smart-e0393122-e682-420f-b3aa-904f4e6bb78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825385794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.825385794
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2317324465
Short name T310
Test name
Test status
Simulation time 26406065136 ps
CPU time 163.69 seconds
Started Feb 21 12:43:05 PM PST 24
Finished Feb 21 12:45:49 PM PST 24
Peak memory 190948 kb
Host smart-3ed75670-4464-4f25-b75a-28a331a4259c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317324465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2317324465
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.4115448214
Short name T248
Test name
Test status
Simulation time 757777043772 ps
CPU time 431.51 seconds
Started Feb 21 12:42:59 PM PST 24
Finished Feb 21 12:50:11 PM PST 24
Peak memory 182800 kb
Host smart-e47228de-2eac-4115-a633-e6fa5732b90d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115448214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.4115448214
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.1617154348
Short name T382
Test name
Test status
Simulation time 84275490154 ps
CPU time 106.79 seconds
Started Feb 21 12:43:02 PM PST 24
Finished Feb 21 12:44:50 PM PST 24
Peak memory 182620 kb
Host smart-c9388b3b-4858-482c-a7ec-c3df4c3672ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617154348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1617154348
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.3443011279
Short name T184
Test name
Test status
Simulation time 202060388345 ps
CPU time 418.3 seconds
Started Feb 21 12:43:04 PM PST 24
Finished Feb 21 12:50:03 PM PST 24
Peak memory 190920 kb
Host smart-bc7c785a-9125-43c9-89f8-12245a8413ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443011279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3443011279
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3008212857
Short name T178
Test name
Test status
Simulation time 20443605944 ps
CPU time 132.87 seconds
Started Feb 21 12:43:02 PM PST 24
Finished Feb 21 12:45:15 PM PST 24
Peak memory 182772 kb
Host smart-1425e507-f07c-455c-9a19-fa3aa6b0ea35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008212857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3008212857
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3646386058
Short name T234
Test name
Test status
Simulation time 1714157626551 ps
CPU time 1190.39 seconds
Started Feb 21 12:42:46 PM PST 24
Finished Feb 21 01:02:37 PM PST 24
Peak memory 191000 kb
Host smart-82e20aed-cd29-4367-b41a-7cd7a1b496f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646386058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3646386058
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3705832320
Short name T258
Test name
Test status
Simulation time 393619193095 ps
CPU time 706.69 seconds
Started Feb 21 12:43:04 PM PST 24
Finished Feb 21 12:54:51 PM PST 24
Peak memory 182756 kb
Host smart-f2549590-0996-4837-82e9-d9b824294210
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705832320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3705832320
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3151200071
Short name T421
Test name
Test status
Simulation time 567382202003 ps
CPU time 158.15 seconds
Started Feb 21 12:43:00 PM PST 24
Finished Feb 21 12:45:38 PM PST 24
Peak memory 182708 kb
Host smart-7b4d6255-0592-4424-ae13-d73a69be3a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151200071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3151200071
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.1719096541
Short name T193
Test name
Test status
Simulation time 752160337756 ps
CPU time 2021.74 seconds
Started Feb 21 12:43:06 PM PST 24
Finished Feb 21 01:16:48 PM PST 24
Peak memory 190744 kb
Host smart-9c6eaf87-82ec-4cdf-8878-486e38d231e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719096541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1719096541
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.4116762849
Short name T121
Test name
Test status
Simulation time 315704294695 ps
CPU time 494.12 seconds
Started Feb 21 12:43:02 PM PST 24
Finished Feb 21 12:51:16 PM PST 24
Peak memory 190976 kb
Host smart-e614f994-a02b-4234-b93b-e9588b7291c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116762849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.4116762849
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2496374382
Short name T224
Test name
Test status
Simulation time 220060369521 ps
CPU time 372.85 seconds
Started Feb 21 12:42:59 PM PST 24
Finished Feb 21 12:49:12 PM PST 24
Peak memory 182796 kb
Host smart-92e397f6-6a48-4ae9-a88a-3149bf6193d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496374382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2496374382
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.315085416
Short name T389
Test name
Test status
Simulation time 38411092865 ps
CPU time 14.36 seconds
Started Feb 21 12:43:02 PM PST 24
Finished Feb 21 12:43:17 PM PST 24
Peak memory 182620 kb
Host smart-a874bd04-68aa-43d7-bcd0-7b3902d96286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315085416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.315085416
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.536209349
Short name T238
Test name
Test status
Simulation time 46490276761 ps
CPU time 94.1 seconds
Started Feb 21 12:42:56 PM PST 24
Finished Feb 21 12:44:32 PM PST 24
Peak memory 194296 kb
Host smart-4ed92950-bbeb-4919-b5c7-c130dcac67ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536209349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.536209349
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3095203621
Short name T413
Test name
Test status
Simulation time 153920897689 ps
CPU time 118.04 seconds
Started Feb 21 12:43:08 PM PST 24
Finished Feb 21 12:45:06 PM PST 24
Peak memory 193616 kb
Host smart-993e2e9d-b2db-4cf3-b36a-20998f67c6fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095203621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3095203621
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1205170631
Short name T298
Test name
Test status
Simulation time 17060479609 ps
CPU time 17.5 seconds
Started Feb 21 12:42:58 PM PST 24
Finished Feb 21 12:43:17 PM PST 24
Peak memory 182776 kb
Host smart-8e382efb-965f-49e0-a63b-cb6d5f607a25
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205170631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1205170631
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.931028200
Short name T35
Test name
Test status
Simulation time 285671116823 ps
CPU time 193.14 seconds
Started Feb 21 12:43:00 PM PST 24
Finished Feb 21 12:46:14 PM PST 24
Peak memory 182752 kb
Host smart-b6a34ad8-a1b5-4dc1-beef-51b0dfcf518e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931028200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.931028200
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.3008718083
Short name T327
Test name
Test status
Simulation time 548448989988 ps
CPU time 315.94 seconds
Started Feb 21 12:42:59 PM PST 24
Finished Feb 21 12:48:15 PM PST 24
Peak memory 190956 kb
Host smart-a4bb49c1-b3f0-48d5-ae80-b5fff1fd91cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008718083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3008718083
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1855982136
Short name T411
Test name
Test status
Simulation time 41872924241 ps
CPU time 13.89 seconds
Started Feb 21 12:42:57 PM PST 24
Finished Feb 21 12:43:12 PM PST 24
Peak memory 194396 kb
Host smart-acbd5a16-84f1-49a8-8f1f-abf9ac1666bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855982136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1855982136
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.709439264
Short name T213
Test name
Test status
Simulation time 675268724929 ps
CPU time 1631.15 seconds
Started Feb 21 12:42:59 PM PST 24
Finished Feb 21 01:10:11 PM PST 24
Peak memory 194776 kb
Host smart-dfb93718-4864-4ded-a26e-85662a6a17b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709439264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.
709439264
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.663738147
Short name T29
Test name
Test status
Simulation time 463661489477 ps
CPU time 914.18 seconds
Started Feb 21 12:42:54 PM PST 24
Finished Feb 21 12:58:09 PM PST 24
Peak memory 211472 kb
Host smart-1ffcdd44-81f7-4944-b7da-0581e58e4af4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663738147 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.663738147
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1408056988
Short name T230
Test name
Test status
Simulation time 858287359530 ps
CPU time 463.08 seconds
Started Feb 21 12:43:00 PM PST 24
Finished Feb 21 12:50:43 PM PST 24
Peak memory 182784 kb
Host smart-21d8a7de-7074-403b-855a-2f5d71dba28d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408056988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1408056988
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.4018978357
Short name T433
Test name
Test status
Simulation time 269061339255 ps
CPU time 188.61 seconds
Started Feb 21 12:42:59 PM PST 24
Finished Feb 21 12:46:08 PM PST 24
Peak memory 182772 kb
Host smart-77ce59a0-331c-48a3-86a6-8965e416e8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018978357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.4018978357
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1117325612
Short name T403
Test name
Test status
Simulation time 163062805 ps
CPU time 0.57 seconds
Started Feb 21 12:42:57 PM PST 24
Finished Feb 21 12:42:58 PM PST 24
Peak memory 182544 kb
Host smart-a30d19db-3c7c-42da-adbb-7553458c9503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117325612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1117325612
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.478867692
Short name T157
Test name
Test status
Simulation time 1123843557106 ps
CPU time 603.95 seconds
Started Feb 21 12:42:52 PM PST 24
Finished Feb 21 12:52:58 PM PST 24
Peak memory 182660 kb
Host smart-d6a4694f-7600-4c24-a62a-a40a9b40ae08
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478867692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.rv_timer_cfg_update_on_fly.478867692
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.1768949700
Short name T404
Test name
Test status
Simulation time 132577635839 ps
CPU time 201.77 seconds
Started Feb 21 12:43:05 PM PST 24
Finished Feb 21 12:46:28 PM PST 24
Peak memory 182792 kb
Host smart-d304c7b3-1a3f-45bc-964b-d8ad4d797cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768949700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1768949700
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.3951653926
Short name T114
Test name
Test status
Simulation time 1200795255052 ps
CPU time 217.54 seconds
Started Feb 21 12:43:01 PM PST 24
Finished Feb 21 12:46:39 PM PST 24
Peak memory 190904 kb
Host smart-4f361844-6142-42ac-8a60-3d6939e2bd7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951653926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3951653926
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.2423997416
Short name T318
Test name
Test status
Simulation time 413369643181 ps
CPU time 146.7 seconds
Started Feb 21 12:43:00 PM PST 24
Finished Feb 21 12:45:28 PM PST 24
Peak memory 190848 kb
Host smart-eb154d9d-d9f7-47b6-a266-6a04bc467359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423997416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2423997416
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3053367973
Short name T418
Test name
Test status
Simulation time 18956788 ps
CPU time 0.53 seconds
Started Feb 21 12:43:13 PM PST 24
Finished Feb 21 12:43:15 PM PST 24
Peak memory 181660 kb
Host smart-65cd76dc-1354-475f-8d3f-31fe6ee6fb86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053367973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3053367973
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1649137954
Short name T36
Test name
Test status
Simulation time 350675938582 ps
CPU time 340.86 seconds
Started Feb 21 12:42:24 PM PST 24
Finished Feb 21 12:48:06 PM PST 24
Peak memory 182780 kb
Host smart-530077cd-6cd8-4f1c-8641-060ee74b528f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649137954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1649137954
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3350986213
Short name T381
Test name
Test status
Simulation time 44780171430 ps
CPU time 75.71 seconds
Started Feb 21 12:42:35 PM PST 24
Finished Feb 21 12:43:51 PM PST 24
Peak memory 182720 kb
Host smart-5af3d70e-a08d-4a46-80a6-812b6110909a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350986213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3350986213
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.32525265
Short name T391
Test name
Test status
Simulation time 107093985 ps
CPU time 0.76 seconds
Started Feb 21 12:42:36 PM PST 24
Finished Feb 21 12:42:38 PM PST 24
Peak memory 182584 kb
Host smart-819f6408-b23a-49c9-bc4a-6dc09272c869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32525265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.32525265
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.1016786128
Short name T19
Test name
Test status
Simulation time 502882616 ps
CPU time 0.83 seconds
Started Feb 21 12:42:53 PM PST 24
Finished Feb 21 12:42:55 PM PST 24
Peak memory 212840 kb
Host smart-8e996de2-156f-4b8d-b3d1-4f041bf1bada
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016786128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1016786128
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1358236517
Short name T11
Test name
Test status
Simulation time 79143712042 ps
CPU time 177.18 seconds
Started Feb 21 12:42:24 PM PST 24
Finished Feb 21 12:45:22 PM PST 24
Peak memory 190972 kb
Host smart-19906c63-41f3-474a-81a0-4fcd8ac797b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358236517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1358236517
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.586233736
Short name T419
Test name
Test status
Simulation time 1640106102517 ps
CPU time 841.58 seconds
Started Feb 21 12:43:14 PM PST 24
Finished Feb 21 12:57:16 PM PST 24
Peak memory 182772 kb
Host smart-4d25cd90-0813-49c7-ae0b-ddb19983c884
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586233736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.rv_timer_cfg_update_on_fly.586233736
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.854561735
Short name T387
Test name
Test status
Simulation time 387276689232 ps
CPU time 149.3 seconds
Started Feb 21 12:43:17 PM PST 24
Finished Feb 21 12:45:46 PM PST 24
Peak memory 182744 kb
Host smart-21df6d87-940e-408a-87fc-e271d52ec8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854561735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.854561735
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3724207412
Short name T244
Test name
Test status
Simulation time 16362393485 ps
CPU time 28.75 seconds
Started Feb 21 12:43:02 PM PST 24
Finished Feb 21 12:43:31 PM PST 24
Peak memory 182664 kb
Host smart-329f35f5-d0e5-4202-beb5-70a541945dca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724207412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3724207412
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.2181983165
Short name T96
Test name
Test status
Simulation time 25333555764 ps
CPU time 82.17 seconds
Started Feb 21 12:43:06 PM PST 24
Finished Feb 21 12:44:29 PM PST 24
Peak memory 190972 kb
Host smart-9f9023bd-3c51-4dc1-be7a-8c7932f46d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181983165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.2181983165
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.4177825987
Short name T107
Test name
Test status
Simulation time 609773946193 ps
CPU time 282.07 seconds
Started Feb 21 12:43:03 PM PST 24
Finished Feb 21 12:47:45 PM PST 24
Peak memory 182804 kb
Host smart-5dc886cd-1085-407a-bd35-eba293bf7bd9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177825987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.4177825987
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.1992435306
Short name T388
Test name
Test status
Simulation time 218440478252 ps
CPU time 62.26 seconds
Started Feb 21 12:43:08 PM PST 24
Finished Feb 21 12:44:11 PM PST 24
Peak memory 182724 kb
Host smart-b70e6c56-a254-432b-8739-48b8e77c4d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992435306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1992435306
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1277906971
Short name T20
Test name
Test status
Simulation time 82950357906 ps
CPU time 258.03 seconds
Started Feb 21 12:43:18 PM PST 24
Finished Feb 21 12:47:36 PM PST 24
Peak memory 190936 kb
Host smart-34b6c4da-def7-437f-8004-66e95ba6dfc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277906971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1277906971
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3314861906
Short name T394
Test name
Test status
Simulation time 45768204 ps
CPU time 0.62 seconds
Started Feb 21 12:43:07 PM PST 24
Finished Feb 21 12:43:14 PM PST 24
Peak memory 182412 kb
Host smart-92a1e7ab-b46f-4c12-a309-8ede74215599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314861906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3314861906
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1671754205
Short name T289
Test name
Test status
Simulation time 1226296630946 ps
CPU time 778.01 seconds
Started Feb 21 12:43:03 PM PST 24
Finished Feb 21 12:56:01 PM PST 24
Peak memory 182772 kb
Host smart-78dc070d-00c0-44f6-b1a4-638ac6223e2b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671754205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1671754205
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2040850910
Short name T384
Test name
Test status
Simulation time 858328771518 ps
CPU time 182.01 seconds
Started Feb 21 12:43:03 PM PST 24
Finished Feb 21 12:46:06 PM PST 24
Peak memory 182808 kb
Host smart-f86a9f78-564e-4bc7-986d-a49db8d97687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040850910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2040850910
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.3732544350
Short name T189
Test name
Test status
Simulation time 189885346163 ps
CPU time 497.99 seconds
Started Feb 21 12:43:08 PM PST 24
Finished Feb 21 12:51:26 PM PST 24
Peak memory 190936 kb
Host smart-3d15cc2c-0c0e-4cf0-82c9-998426c2ea40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732544350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.3732544350
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1087901937
Short name T370
Test name
Test status
Simulation time 205845757 ps
CPU time 0.88 seconds
Started Feb 21 12:43:01 PM PST 24
Finished Feb 21 12:43:02 PM PST 24
Peak memory 182528 kb
Host smart-b5ca3838-527f-41fc-a7e6-d1f33f0bf75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087901937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1087901937
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.742047272
Short name T34
Test name
Test status
Simulation time 42062132822 ps
CPU time 250.28 seconds
Started Feb 21 12:42:56 PM PST 24
Finished Feb 21 12:47:08 PM PST 24
Peak memory 197432 kb
Host smart-13df524f-dc67-4321-a0db-3fd3cbd0b3b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742047272 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.742047272
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.62197718
Short name T129
Test name
Test status
Simulation time 6323221370 ps
CPU time 6.65 seconds
Started Feb 21 12:43:00 PM PST 24
Finished Feb 21 12:43:07 PM PST 24
Peak memory 182736 kb
Host smart-87d98c02-ac09-43d0-925a-636405e456b2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62197718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.rv_timer_cfg_update_on_fly.62197718
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.374011211
Short name T43
Test name
Test status
Simulation time 73666063154 ps
CPU time 59.63 seconds
Started Feb 21 12:43:04 PM PST 24
Finished Feb 21 12:44:04 PM PST 24
Peak memory 182716 kb
Host smart-a19d05c7-851c-4cae-bfb8-729bb3c13edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374011211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.374011211
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.3906049779
Short name T427
Test name
Test status
Simulation time 48458054653 ps
CPU time 22.64 seconds
Started Feb 21 12:43:01 PM PST 24
Finished Feb 21 12:43:24 PM PST 24
Peak memory 182780 kb
Host smart-a1dcab47-4f5f-41de-8ff9-d6c2898982e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906049779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3906049779
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.382910585
Short name T68
Test name
Test status
Simulation time 963664762687 ps
CPU time 779.32 seconds
Started Feb 21 12:43:02 PM PST 24
Finished Feb 21 12:56:02 PM PST 24
Peak memory 190936 kb
Host smart-c550ba6e-d2f0-44c9-82b2-260ac4ddbe44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382910585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
382910585
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2306275671
Short name T305
Test name
Test status
Simulation time 11145327372 ps
CPU time 17.87 seconds
Started Feb 21 12:43:00 PM PST 24
Finished Feb 21 12:43:18 PM PST 24
Peak memory 182676 kb
Host smart-100eec59-04bf-45a9-aeba-4cde2c87ccd9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306275671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2306275671
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2987974649
Short name T375
Test name
Test status
Simulation time 201967554899 ps
CPU time 147.97 seconds
Started Feb 21 12:43:05 PM PST 24
Finished Feb 21 12:45:33 PM PST 24
Peak memory 182652 kb
Host smart-660abbd8-d037-417e-acd1-1be14bca2ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987974649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2987974649
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1418532000
Short name T149
Test name
Test status
Simulation time 102142567114 ps
CPU time 127.63 seconds
Started Feb 21 12:43:02 PM PST 24
Finished Feb 21 12:45:10 PM PST 24
Peak memory 190864 kb
Host smart-5ed389ea-d026-4140-93c8-0f475bcbf014
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418532000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1418532000
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3394043330
Short name T425
Test name
Test status
Simulation time 1088107913 ps
CPU time 2.39 seconds
Started Feb 21 12:43:11 PM PST 24
Finished Feb 21 12:43:14 PM PST 24
Peak memory 190856 kb
Host smart-3360b529-ea18-40ec-a56c-f9083ff522e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394043330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3394043330
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.945619031
Short name T153
Test name
Test status
Simulation time 317412188626 ps
CPU time 481.91 seconds
Started Feb 21 12:43:03 PM PST 24
Finished Feb 21 12:51:05 PM PST 24
Peak memory 190996 kb
Host smart-6133532b-d8b4-4e52-9a55-89fc5093b55c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945619031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
945619031
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1880063506
Short name T311
Test name
Test status
Simulation time 92295653496 ps
CPU time 41.41 seconds
Started Feb 21 12:43:14 PM PST 24
Finished Feb 21 12:43:57 PM PST 24
Peak memory 182800 kb
Host smart-2f05ef57-b311-4dbe-8662-435ced9f7d30
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880063506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1880063506
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1126093702
Short name T359
Test name
Test status
Simulation time 510690211994 ps
CPU time 196.75 seconds
Started Feb 21 12:43:04 PM PST 24
Finished Feb 21 12:46:21 PM PST 24
Peak memory 182596 kb
Host smart-be894ce1-dd10-4190-9243-21a79b61d1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126093702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1126093702
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.4003002746
Short name T303
Test name
Test status
Simulation time 159724459859 ps
CPU time 195.57 seconds
Started Feb 21 12:43:03 PM PST 24
Finished Feb 21 12:46:19 PM PST 24
Peak memory 190928 kb
Host smart-bd37061a-00a2-4f94-919f-b91cfb22a789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003002746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.4003002746
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2286404956
Short name T409
Test name
Test status
Simulation time 110473892449 ps
CPU time 56.88 seconds
Started Feb 21 12:43:06 PM PST 24
Finished Feb 21 12:44:04 PM PST 24
Peak memory 182768 kb
Host smart-14c4034e-55aa-44c1-8b16-944abe995424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286404956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2286404956
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.571062517
Short name T243
Test name
Test status
Simulation time 605010098293 ps
CPU time 347.35 seconds
Started Feb 21 12:43:08 PM PST 24
Finished Feb 21 12:48:56 PM PST 24
Peak memory 182748 kb
Host smart-10c3cb9f-e9cb-49d7-bd77-ab71c1ec57e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571062517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.571062517
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1743568781
Short name T416
Test name
Test status
Simulation time 55548094013 ps
CPU time 45.52 seconds
Started Feb 21 12:43:05 PM PST 24
Finished Feb 21 12:43:50 PM PST 24
Peak memory 182724 kb
Host smart-f7a510cb-3277-4736-9d6a-3c2a11b6f17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743568781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1743568781
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.1580863891
Short name T59
Test name
Test status
Simulation time 1035411879785 ps
CPU time 479.98 seconds
Started Feb 21 12:43:04 PM PST 24
Finished Feb 21 12:51:15 PM PST 24
Peak memory 190976 kb
Host smart-664706fa-f371-49fe-a823-3ee7bf23e6a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580863891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1580863891
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3547025165
Short name T341
Test name
Test status
Simulation time 29991504165 ps
CPU time 72.6 seconds
Started Feb 21 12:43:06 PM PST 24
Finished Feb 21 12:44:19 PM PST 24
Peak memory 190968 kb
Host smart-36067438-b4d3-4973-9f94-3ba9ca09e124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547025165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3547025165
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.4100457881
Short name T280
Test name
Test status
Simulation time 504217601575 ps
CPU time 289.76 seconds
Started Feb 21 12:43:02 PM PST 24
Finished Feb 21 12:47:53 PM PST 24
Peak memory 182776 kb
Host smart-24056f95-5051-4088-b243-121a7c2fdf1e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100457881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.4100457881
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.1809057657
Short name T356
Test name
Test status
Simulation time 432775453312 ps
CPU time 66.6 seconds
Started Feb 21 12:43:04 PM PST 24
Finished Feb 21 12:44:11 PM PST 24
Peak memory 182708 kb
Host smart-f6fb06da-f3dc-4ae3-b3d6-1c714fc6e5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809057657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.1809057657
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.4213081977
Short name T271
Test name
Test status
Simulation time 160270367404 ps
CPU time 1266.08 seconds
Started Feb 21 12:43:23 PM PST 24
Finished Feb 21 01:04:29 PM PST 24
Peak memory 190912 kb
Host smart-911b2094-6f63-4c23-9274-d581c70f222f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213081977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.4213081977
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2627168158
Short name T346
Test name
Test status
Simulation time 77939141918 ps
CPU time 335.87 seconds
Started Feb 21 12:43:04 PM PST 24
Finished Feb 21 12:48:41 PM PST 24
Peak memory 190968 kb
Host smart-3732ccce-6558-493a-bdea-6da028b41959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627168158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2627168158
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.29115328
Short name T291
Test name
Test status
Simulation time 601832788882 ps
CPU time 503.86 seconds
Started Feb 21 12:43:05 PM PST 24
Finished Feb 21 12:51:29 PM PST 24
Peak memory 182800 kb
Host smart-107cc72b-5ad0-43e2-b123-38c35b1bb601
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29115328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.rv_timer_cfg_update_on_fly.29115328
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.2214502222
Short name T367
Test name
Test status
Simulation time 85816114821 ps
CPU time 149.07 seconds
Started Feb 21 12:43:05 PM PST 24
Finished Feb 21 12:45:35 PM PST 24
Peak memory 182776 kb
Host smart-6dd9b3f5-3cdb-4774-9dde-581b8593cceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214502222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.2214502222
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.3912694417
Short name T307
Test name
Test status
Simulation time 5842340868 ps
CPU time 5.48 seconds
Started Feb 21 12:43:13 PM PST 24
Finished Feb 21 12:43:20 PM PST 24
Peak memory 182756 kb
Host smart-d8240ee2-a5a5-4201-805c-1417715a9ae3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912694417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3912694417
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3461625464
Short name T299
Test name
Test status
Simulation time 49668269604 ps
CPU time 100.29 seconds
Started Feb 21 12:43:55 PM PST 24
Finished Feb 21 12:45:36 PM PST 24
Peak memory 182752 kb
Host smart-41604a36-02e1-4c49-8a4f-c974e0d0b084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461625464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3461625464
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.1407601163
Short name T89
Test name
Test status
Simulation time 59276917795 ps
CPU time 562.56 seconds
Started Feb 21 12:43:28 PM PST 24
Finished Feb 21 12:52:51 PM PST 24
Peak memory 205548 kb
Host smart-98de3442-b32b-43b4-86f9-6013f94b228a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407601163 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.1407601163
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1733239954
Short name T445
Test name
Test status
Simulation time 479072001677 ps
CPU time 225.67 seconds
Started Feb 21 12:43:22 PM PST 24
Finished Feb 21 12:47:08 PM PST 24
Peak memory 182772 kb
Host smart-05017d8f-9d1a-469e-9f83-ee94a88ea053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733239954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1733239954
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.2266082685
Short name T345
Test name
Test status
Simulation time 23209586171 ps
CPU time 55.65 seconds
Started Feb 21 12:43:04 PM PST 24
Finished Feb 21 12:44:00 PM PST 24
Peak memory 182744 kb
Host smart-ae206894-fcfd-4808-b08e-64c0abec55e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266082685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2266082685
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.310734915
Short name T340
Test name
Test status
Simulation time 383964496458 ps
CPU time 214.7 seconds
Started Feb 21 12:42:45 PM PST 24
Finished Feb 21 12:46:20 PM PST 24
Peak memory 182684 kb
Host smart-16c9d7e0-a880-46d7-a76a-166322eddd6d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310734915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.rv_timer_cfg_update_on_fly.310734915
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.2112602057
Short name T383
Test name
Test status
Simulation time 85077356370 ps
CPU time 119.9 seconds
Started Feb 21 12:42:39 PM PST 24
Finished Feb 21 12:44:40 PM PST 24
Peak memory 182720 kb
Host smart-43c2b8fe-780f-4872-a57a-55634baa7bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112602057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2112602057
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.3930069797
Short name T260
Test name
Test status
Simulation time 230114729129 ps
CPU time 956.71 seconds
Started Feb 21 12:42:54 PM PST 24
Finished Feb 21 12:58:53 PM PST 24
Peak memory 190972 kb
Host smart-2ed2c594-a35e-467c-91fd-9aa5efc5775b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930069797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3930069797
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3047364161
Short name T366
Test name
Test status
Simulation time 620351156 ps
CPU time 0.81 seconds
Started Feb 21 12:42:38 PM PST 24
Finished Feb 21 12:42:40 PM PST 24
Peak memory 182320 kb
Host smart-78557974-b10b-4df4-a0b9-eb756687c143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047364161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3047364161
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.479104135
Short name T276
Test name
Test status
Simulation time 127933024810 ps
CPU time 116.51 seconds
Started Feb 21 12:43:34 PM PST 24
Finished Feb 21 12:45:36 PM PST 24
Peak memory 194336 kb
Host smart-cf82fcd5-16f9-485f-977d-ac207c606081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479104135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.479104135
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.4245277605
Short name T423
Test name
Test status
Simulation time 121241374712 ps
CPU time 33.22 seconds
Started Feb 21 12:43:06 PM PST 24
Finished Feb 21 12:43:40 PM PST 24
Peak memory 190976 kb
Host smart-b3635143-ab6f-490d-b2fe-d05c8cd746b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245277605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.4245277605
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.2133500327
Short name T211
Test name
Test status
Simulation time 181656096651 ps
CPU time 200.77 seconds
Started Feb 21 12:43:12 PM PST 24
Finished Feb 21 12:46:35 PM PST 24
Peak memory 194992 kb
Host smart-f31b5564-08ac-4c05-9ae8-261573ce09cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133500327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2133500327
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.2138028592
Short name T287
Test name
Test status
Simulation time 250250861855 ps
CPU time 137.76 seconds
Started Feb 21 12:43:12 PM PST 24
Finished Feb 21 12:45:31 PM PST 24
Peak memory 190864 kb
Host smart-028b9478-ffa4-49f2-9264-0a8c2d070d87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138028592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2138028592
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.1689142372
Short name T144
Test name
Test status
Simulation time 106305495061 ps
CPU time 118.41 seconds
Started Feb 21 12:43:15 PM PST 24
Finished Feb 21 12:45:15 PM PST 24
Peak memory 182648 kb
Host smart-0aac5eb7-919a-4ecd-98e8-9dc7a71c256a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689142372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1689142372
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.449161220
Short name T100
Test name
Test status
Simulation time 629437904456 ps
CPU time 612 seconds
Started Feb 21 12:43:20 PM PST 24
Finished Feb 21 12:53:32 PM PST 24
Peak memory 190992 kb
Host smart-8c041bb2-b2a8-41b5-af08-b230650a4c8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449161220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.449161220
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.2101761596
Short name T141
Test name
Test status
Simulation time 416223395181 ps
CPU time 363.19 seconds
Started Feb 21 12:43:12 PM PST 24
Finished Feb 21 12:49:17 PM PST 24
Peak memory 190852 kb
Host smart-f8e63c60-8cc8-41ef-bc53-721644adce08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101761596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2101761596
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2450393845
Short name T297
Test name
Test status
Simulation time 307601413759 ps
CPU time 1897.65 seconds
Started Feb 21 12:43:04 PM PST 24
Finished Feb 21 01:14:42 PM PST 24
Peak memory 190976 kb
Host smart-6e487d94-4308-47d7-a9d5-e42d0c3b96b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450393845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2450393845
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.2838123023
Short name T438
Test name
Test status
Simulation time 328053814678 ps
CPU time 297.48 seconds
Started Feb 21 12:42:49 PM PST 24
Finished Feb 21 12:47:47 PM PST 24
Peak memory 182720 kb
Host smart-a93456a9-8435-4992-be4e-18b778e21403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838123023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2838123023
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.2113252934
Short name T103
Test name
Test status
Simulation time 135184587297 ps
CPU time 646.07 seconds
Started Feb 21 12:42:44 PM PST 24
Finished Feb 21 12:53:30 PM PST 24
Peak memory 190848 kb
Host smart-59ef0cde-878d-4f3b-aaf1-7e225e794b7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113252934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2113252934
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.3403531996
Short name T447
Test name
Test status
Simulation time 15186135376 ps
CPU time 26.24 seconds
Started Feb 21 12:42:55 PM PST 24
Finished Feb 21 12:43:22 PM PST 24
Peak memory 190464 kb
Host smart-034b93c0-ae09-4652-9c80-1b161a9c9ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403531996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3403531996
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2957690759
Short name T410
Test name
Test status
Simulation time 212270265742 ps
CPU time 295.65 seconds
Started Feb 21 12:43:01 PM PST 24
Finished Feb 21 12:47:57 PM PST 24
Peak memory 194088 kb
Host smart-22e15c84-8a67-4cb8-b7e2-511582e1828a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957690759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2957690759
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.2869978013
Short name T321
Test name
Test status
Simulation time 31866760212 ps
CPU time 262.29 seconds
Started Feb 21 12:42:52 PM PST 24
Finished Feb 21 12:47:21 PM PST 24
Peak memory 205700 kb
Host smart-f5a4c48c-71e2-4aed-99b6-0c5ce292029c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869978013 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.2869978013
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.273807037
Short name T429
Test name
Test status
Simulation time 60829001073 ps
CPU time 106.01 seconds
Started Feb 21 12:43:05 PM PST 24
Finished Feb 21 12:44:51 PM PST 24
Peak memory 190908 kb
Host smart-c6d4ae00-e0e7-4c5b-ba26-0fb191435555
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273807037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.273807037
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.1015087045
Short name T398
Test name
Test status
Simulation time 133853232841 ps
CPU time 67.32 seconds
Started Feb 21 12:43:10 PM PST 24
Finished Feb 21 12:44:18 PM PST 24
Peak memory 182768 kb
Host smart-4ddcdb9e-5fe3-412a-aace-34975ec00a0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015087045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1015087045
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1006528425
Short name T374
Test name
Test status
Simulation time 49504436651 ps
CPU time 39.25 seconds
Started Feb 21 12:43:20 PM PST 24
Finished Feb 21 12:43:59 PM PST 24
Peak memory 182740 kb
Host smart-58c48ce3-b844-40a2-9dd7-895a33ac5bf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006528425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1006528425
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.659396121
Short name T330
Test name
Test status
Simulation time 85444164528 ps
CPU time 111.88 seconds
Started Feb 21 12:43:14 PM PST 24
Finished Feb 21 12:45:07 PM PST 24
Peak memory 182756 kb
Host smart-b2d1dbd1-f642-4831-8e24-0303098ce272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659396121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.659396121
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.45305888
Short name T134
Test name
Test status
Simulation time 446349925772 ps
CPU time 251.79 seconds
Started Feb 21 12:43:20 PM PST 24
Finished Feb 21 12:47:42 PM PST 24
Peak memory 190988 kb
Host smart-bbed1031-cac3-4bdd-9341-e89acb744c7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45305888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.45305888
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.871020415
Short name T176
Test name
Test status
Simulation time 270625258213 ps
CPU time 131.07 seconds
Started Feb 21 12:43:05 PM PST 24
Finished Feb 21 12:45:16 PM PST 24
Peak memory 190800 kb
Host smart-0387d2fb-7149-4d76-b415-677cdadb86cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871020415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.871020415
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.4059627622
Short name T198
Test name
Test status
Simulation time 137894286055 ps
CPU time 233.86 seconds
Started Feb 21 12:43:11 PM PST 24
Finished Feb 21 12:47:05 PM PST 24
Peak memory 190976 kb
Host smart-2b492d55-c354-4eff-b414-0c644af40c3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059627622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.4059627622
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.4088698762
Short name T166
Test name
Test status
Simulation time 1435954218150 ps
CPU time 387.39 seconds
Started Feb 21 12:43:04 PM PST 24
Finished Feb 21 12:49:31 PM PST 24
Peak memory 190976 kb
Host smart-6ee79664-84e1-41ea-bc24-8d884bb3dfae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088698762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.4088698762
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.2096581337
Short name T316
Test name
Test status
Simulation time 54677870181 ps
CPU time 54.09 seconds
Started Feb 21 12:43:16 PM PST 24
Finished Feb 21 12:44:11 PM PST 24
Peak memory 182748 kb
Host smart-6090c90d-53c7-4644-b01b-3ccde0fbed57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096581337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2096581337
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3683480681
Short name T170
Test name
Test status
Simulation time 12594567021 ps
CPU time 8.44 seconds
Started Feb 21 12:42:46 PM PST 24
Finished Feb 21 12:42:55 PM PST 24
Peak memory 182736 kb
Host smart-04b3a815-ba28-4fda-84ac-c82514abb082
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683480681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3683480681
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1048349219
Short name T435
Test name
Test status
Simulation time 83256066065 ps
CPU time 95.01 seconds
Started Feb 21 12:42:46 PM PST 24
Finished Feb 21 12:44:21 PM PST 24
Peak memory 182620 kb
Host smart-77ebd2cb-af78-42a0-90a1-4cf459664bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048349219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1048349219
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.2700815046
Short name T351
Test name
Test status
Simulation time 38580451753 ps
CPU time 252.72 seconds
Started Feb 21 12:42:41 PM PST 24
Finished Feb 21 12:46:54 PM PST 24
Peak memory 190952 kb
Host smart-5603bb06-5b16-4a0e-81a1-2b123d9cc58f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700815046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2700815046
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1882278667
Short name T304
Test name
Test status
Simulation time 194903824564 ps
CPU time 476.62 seconds
Started Feb 21 12:42:34 PM PST 24
Finished Feb 21 12:50:32 PM PST 24
Peak memory 190952 kb
Host smart-bef8b98f-b3ae-4310-b89c-1e59f639b820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882278667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1882278667
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.168398751
Short name T31
Test name
Test status
Simulation time 108796347299 ps
CPU time 287.5 seconds
Started Feb 21 12:42:46 PM PST 24
Finished Feb 21 12:47:33 PM PST 24
Peak memory 197520 kb
Host smart-594849a4-8c8c-48db-990e-24cc7853a664
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168398751 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.168398751
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.150154296
Short name T137
Test name
Test status
Simulation time 33450867853 ps
CPU time 75.31 seconds
Started Feb 21 12:43:06 PM PST 24
Finished Feb 21 12:44:22 PM PST 24
Peak memory 193424 kb
Host smart-adc80820-845e-4491-b62f-e7219023614f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150154296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.150154296
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3603896257
Short name T324
Test name
Test status
Simulation time 84022157871 ps
CPU time 74.14 seconds
Started Feb 21 12:43:09 PM PST 24
Finished Feb 21 12:44:23 PM PST 24
Peak memory 191184 kb
Host smart-a643e02f-3018-4bb7-8f74-9b6676ff073c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603896257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3603896257
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.1287250263
Short name T160
Test name
Test status
Simulation time 94002669534 ps
CPU time 140.78 seconds
Started Feb 21 12:43:13 PM PST 24
Finished Feb 21 12:45:35 PM PST 24
Peak memory 190872 kb
Host smart-6d755b19-ff80-47a8-a5be-d959a824fd40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287250263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1287250263
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3351639985
Short name T190
Test name
Test status
Simulation time 76264622728 ps
CPU time 125.2 seconds
Started Feb 21 12:43:07 PM PST 24
Finished Feb 21 12:45:12 PM PST 24
Peak memory 190880 kb
Host smart-28c92c10-309e-4389-b3bd-9f3e9b6b13be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351639985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3351639985
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3258047334
Short name T267
Test name
Test status
Simulation time 424490223764 ps
CPU time 848.5 seconds
Started Feb 21 12:43:09 PM PST 24
Finished Feb 21 12:57:18 PM PST 24
Peak memory 194372 kb
Host smart-1dbf89a5-ff48-4d20-93cb-1b7b1c455436
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258047334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3258047334
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3324876188
Short name T217
Test name
Test status
Simulation time 42723189253 ps
CPU time 50.97 seconds
Started Feb 21 12:43:49 PM PST 24
Finished Feb 21 12:44:44 PM PST 24
Peak memory 190976 kb
Host smart-362d9b9a-88a1-4a74-a2c6-697ca5a8e65d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324876188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3324876188
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2694134322
Short name T424
Test name
Test status
Simulation time 35003400857 ps
CPU time 49.24 seconds
Started Feb 21 12:43:08 PM PST 24
Finished Feb 21 12:43:57 PM PST 24
Peak memory 190932 kb
Host smart-1a37d32c-3523-4fec-acaf-a4419a3f3681
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694134322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2694134322
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3374211555
Short name T97
Test name
Test status
Simulation time 578610854778 ps
CPU time 1016.77 seconds
Started Feb 21 12:42:59 PM PST 24
Finished Feb 21 12:59:57 PM PST 24
Peak memory 182808 kb
Host smart-e3574ec2-7b70-40f5-bfd5-840b27d2d235
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374211555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3374211555
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.4031199136
Short name T395
Test name
Test status
Simulation time 137356703553 ps
CPU time 104.01 seconds
Started Feb 21 12:42:18 PM PST 24
Finished Feb 21 12:44:03 PM PST 24
Peak memory 182776 kb
Host smart-6110e98a-9c44-484f-969d-4a488663998f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031199136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.4031199136
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.2704855346
Short name T250
Test name
Test status
Simulation time 145181747703 ps
CPU time 175.05 seconds
Started Feb 21 12:42:30 PM PST 24
Finished Feb 21 12:45:25 PM PST 24
Peak memory 191920 kb
Host smart-2aea0e08-b6a5-4a4e-8dfd-ac020d4317e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704855346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2704855346
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.977910244
Short name T186
Test name
Test status
Simulation time 278142585705 ps
CPU time 171.35 seconds
Started Feb 21 12:42:32 PM PST 24
Finished Feb 21 12:45:24 PM PST 24
Peak memory 190944 kb
Host smart-01a1205b-4cbb-419b-8258-d1281c489bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977910244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.977910244
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.1596047803
Short name T286
Test name
Test status
Simulation time 648271429359 ps
CPU time 382.88 seconds
Started Feb 21 12:43:26 PM PST 24
Finished Feb 21 12:49:49 PM PST 24
Peak memory 190992 kb
Host smart-34357bbf-0741-46dc-9bd2-d8c2d5f79840
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596047803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.1596047803
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.2020482231
Short name T202
Test name
Test status
Simulation time 174418202612 ps
CPU time 180.57 seconds
Started Feb 21 12:43:27 PM PST 24
Finished Feb 21 12:46:28 PM PST 24
Peak memory 193084 kb
Host smart-a99da764-3849-46f1-b22d-f307283c4851
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020482231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2020482231
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.3672664113
Short name T203
Test name
Test status
Simulation time 171625035189 ps
CPU time 321.18 seconds
Started Feb 21 12:43:37 PM PST 24
Finished Feb 21 12:48:58 PM PST 24
Peak memory 190904 kb
Host smart-944f78e2-57e2-4ee7-9918-e8b82d8ed885
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672664113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3672664113
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.2274174590
Short name T151
Test name
Test status
Simulation time 239298035304 ps
CPU time 234.85 seconds
Started Feb 21 12:43:32 PM PST 24
Finished Feb 21 12:47:27 PM PST 24
Peak memory 194760 kb
Host smart-880747a1-b1a6-4206-b14f-a78af77b9af1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274174590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.2274174590
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.3693523897
Short name T430
Test name
Test status
Simulation time 19821457587 ps
CPU time 237.6 seconds
Started Feb 21 12:43:09 PM PST 24
Finished Feb 21 12:47:07 PM PST 24
Peak memory 190928 kb
Host smart-dc9e96b4-f05f-45b0-b236-abc9d640b14b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693523897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3693523897
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.2333259465
Short name T332
Test name
Test status
Simulation time 143525699538 ps
CPU time 51.42 seconds
Started Feb 21 12:43:12 PM PST 24
Finished Feb 21 12:44:05 PM PST 24
Peak memory 182608 kb
Host smart-24b2a82c-48c9-4f1c-a68a-5bb2659cae6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333259465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2333259465
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3443582499
Short name T309
Test name
Test status
Simulation time 79262411837 ps
CPU time 135.75 seconds
Started Feb 21 12:43:25 PM PST 24
Finished Feb 21 12:45:41 PM PST 24
Peak memory 194308 kb
Host smart-1d72c748-65e3-4314-b793-d2acd18c0feb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443582499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3443582499
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.715268396
Short name T415
Test name
Test status
Simulation time 502349798081 ps
CPU time 254.07 seconds
Started Feb 21 12:43:22 PM PST 24
Finished Feb 21 12:47:40 PM PST 24
Peak memory 190948 kb
Host smart-e7df512f-f78d-487d-95d4-3df373a8bd35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715268396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.715268396
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.70277681
Short name T272
Test name
Test status
Simulation time 4925890232 ps
CPU time 8.26 seconds
Started Feb 21 12:43:16 PM PST 24
Finished Feb 21 12:43:25 PM PST 24
Peak memory 182608 kb
Host smart-960607a9-e0e3-4b9c-afbb-de9c4ed992ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70277681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.70277681
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.3110429723
Short name T118
Test name
Test status
Simulation time 675751653448 ps
CPU time 353.38 seconds
Started Feb 21 12:42:36 PM PST 24
Finished Feb 21 12:48:31 PM PST 24
Peak memory 182700 kb
Host smart-1bdc5a85-6841-48be-987d-6c02a760d624
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110429723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.3110429723
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.3343642420
Short name T400
Test name
Test status
Simulation time 333308929365 ps
CPU time 141.4 seconds
Started Feb 21 12:42:57 PM PST 24
Finished Feb 21 12:45:19 PM PST 24
Peak memory 182616 kb
Host smart-9fd99f6c-46bf-4889-aa72-625c301837ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343642420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.3343642420
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.1823256394
Short name T126
Test name
Test status
Simulation time 574484160176 ps
CPU time 1243.86 seconds
Started Feb 21 12:42:12 PM PST 24
Finished Feb 21 01:02:58 PM PST 24
Peak memory 194120 kb
Host smart-c03e2c1e-85ea-4966-b9df-33c45befa64a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823256394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.1823256394
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3774521664
Short name T440
Test name
Test status
Simulation time 9292473612 ps
CPU time 5.28 seconds
Started Feb 21 12:42:34 PM PST 24
Finished Feb 21 12:42:41 PM PST 24
Peak memory 182756 kb
Host smart-13ec00b9-f461-4172-9239-0fc5cd292865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774521664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3774521664
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.2992422986
Short name T56
Test name
Test status
Simulation time 108529691360 ps
CPU time 430.39 seconds
Started Feb 21 12:42:32 PM PST 24
Finished Feb 21 12:49:43 PM PST 24
Peak memory 182588 kb
Host smart-0cbe185b-a4d4-430a-9eff-37818333ff60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992422986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
2992422986
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.946753624
Short name T7
Test name
Test status
Simulation time 77157048499 ps
CPU time 64.66 seconds
Started Feb 21 12:43:26 PM PST 24
Finished Feb 21 12:44:31 PM PST 24
Peak memory 182756 kb
Host smart-2a4ed867-1eb8-4aae-952a-205bddcd6db0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946753624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.946753624
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1493033854
Short name T55
Test name
Test status
Simulation time 168093429444 ps
CPU time 274.13 seconds
Started Feb 21 12:43:15 PM PST 24
Finished Feb 21 12:47:50 PM PST 24
Peak memory 190916 kb
Host smart-dbf0799b-dc12-4892-8a2b-431e0536f11e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493033854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1493033854
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3248972678
Short name T405
Test name
Test status
Simulation time 11868417427 ps
CPU time 77.33 seconds
Started Feb 21 12:43:24 PM PST 24
Finished Feb 21 12:44:41 PM PST 24
Peak memory 182744 kb
Host smart-db753318-6fb8-4d51-9cfb-609fa9218bfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248972678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3248972678
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.128479556
Short name T42
Test name
Test status
Simulation time 68413983740 ps
CPU time 129.75 seconds
Started Feb 21 12:43:18 PM PST 24
Finished Feb 21 12:45:28 PM PST 24
Peak memory 190940 kb
Host smart-511be875-4afc-4811-95e7-601cdd77d5bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128479556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.128479556
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3219693384
Short name T197
Test name
Test status
Simulation time 316838067346 ps
CPU time 674.02 seconds
Started Feb 21 12:43:26 PM PST 24
Finished Feb 21 12:54:41 PM PST 24
Peak memory 190860 kb
Host smart-3947ec4d-2cec-4fe2-bc59-f936cba31f70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219693384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3219693384
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.380147581
Short name T288
Test name
Test status
Simulation time 2746743679909 ps
CPU time 616.78 seconds
Started Feb 21 12:43:23 PM PST 24
Finished Feb 21 12:53:43 PM PST 24
Peak memory 190984 kb
Host smart-e8a797b6-62d6-4d83-a5da-833ccdf778da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380147581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.380147581
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1234686076
Short name T334
Test name
Test status
Simulation time 217159983097 ps
CPU time 462.67 seconds
Started Feb 21 12:43:15 PM PST 24
Finished Feb 21 12:50:59 PM PST 24
Peak memory 190920 kb
Host smart-745efd7d-a956-4a8c-81dc-6fc4d5159707
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234686076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1234686076
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3159802713
Short name T123
Test name
Test status
Simulation time 130963562088 ps
CPU time 233.97 seconds
Started Feb 21 12:43:36 PM PST 24
Finished Feb 21 12:47:31 PM PST 24
Peak memory 194312 kb
Host smart-40f560b3-bd54-4e5d-9034-a6bb3a229214
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159802713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3159802713
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.162828945
Short name T347
Test name
Test status
Simulation time 47472325759 ps
CPU time 62.19 seconds
Started Feb 21 12:43:40 PM PST 24
Finished Feb 21 12:44:43 PM PST 24
Peak memory 182644 kb
Host smart-90088e6c-1645-41cf-a144-39ebabcbe4a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162828945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.162828945
Directory /workspace/99.rv_timer_random/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%