Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.55 99.36 98.73 100.00 100.00 100.00 99.21


Total test records in report: 582
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T128 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2272217541 Feb 25 01:27:35 PM PST 24 Feb 25 01:27:37 PM PST 24 80914064 ps
T510 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1358804757 Feb 25 01:27:36 PM PST 24 Feb 25 01:27:37 PM PST 24 24100491 ps
T102 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.891870210 Feb 25 01:27:18 PM PST 24 Feb 25 01:27:19 PM PST 24 13639326 ps
T511 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.250267614 Feb 25 01:27:48 PM PST 24 Feb 25 01:27:49 PM PST 24 71866713 ps
T512 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2793094066 Feb 25 01:27:48 PM PST 24 Feb 25 01:27:49 PM PST 24 47684568 ps
T513 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.145742737 Feb 25 01:27:34 PM PST 24 Feb 25 01:27:35 PM PST 24 23161977 ps
T103 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2922542433 Feb 25 01:27:25 PM PST 24 Feb 25 01:27:27 PM PST 24 114846506 ps
T514 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.383734826 Feb 25 01:27:50 PM PST 24 Feb 25 01:27:51 PM PST 24 542320336 ps
T515 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.90676379 Feb 25 01:27:51 PM PST 24 Feb 25 01:27:51 PM PST 24 33296049 ps
T516 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.4229849589 Feb 25 01:27:15 PM PST 24 Feb 25 01:27:16 PM PST 24 189818783 ps
T517 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.970792951 Feb 25 01:27:19 PM PST 24 Feb 25 01:27:20 PM PST 24 20525290 ps
T104 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1258646448 Feb 25 01:27:06 PM PST 24 Feb 25 01:27:07 PM PST 24 59210414 ps
T518 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3726414273 Feb 25 01:27:30 PM PST 24 Feb 25 01:27:33 PM PST 24 532925461 ps
T519 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.4013565115 Feb 25 01:27:09 PM PST 24 Feb 25 01:27:10 PM PST 24 45158140 ps
T520 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.728615208 Feb 25 01:27:40 PM PST 24 Feb 25 01:27:42 PM PST 24 121754645 ps
T521 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1886599648 Feb 25 01:27:50 PM PST 24 Feb 25 01:27:51 PM PST 24 15375073 ps
T107 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2611454466 Feb 25 01:27:15 PM PST 24 Feb 25 01:27:16 PM PST 24 30474656 ps
T522 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3715074353 Feb 25 01:27:04 PM PST 24 Feb 25 01:27:05 PM PST 24 51317480 ps
T523 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.2326657418 Feb 25 01:27:30 PM PST 24 Feb 25 01:27:31 PM PST 24 43039132 ps
T524 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.299428244 Feb 25 01:27:35 PM PST 24 Feb 25 01:27:36 PM PST 24 95609022 ps
T525 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.608656485 Feb 25 01:27:48 PM PST 24 Feb 25 01:27:49 PM PST 24 15482750 ps
T526 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.4261389378 Feb 25 01:27:34 PM PST 24 Feb 25 01:27:36 PM PST 24 212322480 ps
T527 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2060418 Feb 25 01:27:48 PM PST 24 Feb 25 01:27:49 PM PST 24 50431987 ps
T528 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3088690283 Feb 25 01:27:38 PM PST 24 Feb 25 01:27:39 PM PST 24 51366603 ps
T529 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.89957727 Feb 25 01:27:33 PM PST 24 Feb 25 01:27:33 PM PST 24 109534530 ps
T530 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2114476264 Feb 25 01:27:19 PM PST 24 Feb 25 01:27:21 PM PST 24 237487886 ps
T531 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.4086743360 Feb 25 01:27:53 PM PST 24 Feb 25 01:27:54 PM PST 24 13743491 ps
T532 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3249039942 Feb 25 01:27:04 PM PST 24 Feb 25 01:27:07 PM PST 24 251313394 ps
T533 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.221165659 Feb 25 01:27:43 PM PST 24 Feb 25 01:27:44 PM PST 24 62051816 ps
T534 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1033947081 Feb 25 01:27:55 PM PST 24 Feb 25 01:27:57 PM PST 24 41100509 ps
T535 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1212161241 Feb 25 01:27:53 PM PST 24 Feb 25 01:27:54 PM PST 24 68158172 ps
T106 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.506335973 Feb 25 01:27:31 PM PST 24 Feb 25 01:27:32 PM PST 24 62740263 ps
T536 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.938223491 Feb 25 01:27:54 PM PST 24 Feb 25 01:27:56 PM PST 24 94155252 ps
T537 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1623081995 Feb 25 01:27:03 PM PST 24 Feb 25 01:27:04 PM PST 24 21081658 ps
T538 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1455566755 Feb 25 01:27:43 PM PST 24 Feb 25 01:27:43 PM PST 24 11641751 ps
T539 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3748803950 Feb 25 01:27:48 PM PST 24 Feb 25 01:27:49 PM PST 24 124910478 ps
T540 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2683958539 Feb 25 01:27:53 PM PST 24 Feb 25 01:27:54 PM PST 24 36071829 ps
T541 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3939634148 Feb 25 01:27:48 PM PST 24 Feb 25 01:27:49 PM PST 24 15177200 ps
T108 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1519302035 Feb 25 01:27:15 PM PST 24 Feb 25 01:27:16 PM PST 24 53620016 ps
T542 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2929750702 Feb 25 01:27:44 PM PST 24 Feb 25 01:27:45 PM PST 24 75188142 ps
T543 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.847205137 Feb 25 01:27:48 PM PST 24 Feb 25 01:27:49 PM PST 24 51408706 ps
T544 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3953179277 Feb 25 01:27:03 PM PST 24 Feb 25 01:27:06 PM PST 24 66867463 ps
T545 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3063034818 Feb 25 01:27:55 PM PST 24 Feb 25 01:27:57 PM PST 24 86081630 ps
T546 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3834821921 Feb 25 01:27:50 PM PST 24 Feb 25 01:27:51 PM PST 24 13359661 ps
T129 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1547970329 Feb 25 01:27:48 PM PST 24 Feb 25 01:27:50 PM PST 24 247679557 ps
T547 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.397325418 Feb 25 01:27:43 PM PST 24 Feb 25 01:27:44 PM PST 24 12856224 ps
T548 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2800460834 Feb 25 01:27:50 PM PST 24 Feb 25 01:27:51 PM PST 24 166179299 ps
T549 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.45625029 Feb 25 01:27:05 PM PST 24 Feb 25 01:27:07 PM PST 24 172369018 ps
T550 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1815215210 Feb 25 01:27:43 PM PST 24 Feb 25 01:27:43 PM PST 24 12326529 ps
T551 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2791578912 Feb 25 01:27:20 PM PST 24 Feb 25 01:27:21 PM PST 24 325801551 ps
T552 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1097556683 Feb 25 01:27:04 PM PST 24 Feb 25 01:27:04 PM PST 24 40040237 ps
T553 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1602648180 Feb 25 01:27:05 PM PST 24 Feb 25 01:27:06 PM PST 24 19367869 ps
T554 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3522163517 Feb 25 01:27:06 PM PST 24 Feb 25 01:27:06 PM PST 24 114333921 ps
T555 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.881982818 Feb 25 01:27:49 PM PST 24 Feb 25 01:27:51 PM PST 24 200034014 ps
T556 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3975143264 Feb 25 01:27:48 PM PST 24 Feb 25 01:27:51 PM PST 24 505780884 ps
T557 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2513321568 Feb 25 01:27:48 PM PST 24 Feb 25 01:27:49 PM PST 24 19828052 ps
T558 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3911851561 Feb 25 01:27:50 PM PST 24 Feb 25 01:27:51 PM PST 24 32119229 ps
T559 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.181455756 Feb 25 01:27:44 PM PST 24 Feb 25 01:27:45 PM PST 24 47315022 ps
T560 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3311118765 Feb 25 01:27:51 PM PST 24 Feb 25 01:27:51 PM PST 24 14495026 ps
T561 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1260818839 Feb 25 01:27:48 PM PST 24 Feb 25 01:27:49 PM PST 24 26866381 ps
T562 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3540553796 Feb 25 01:27:51 PM PST 24 Feb 25 01:27:52 PM PST 24 14979355 ps
T563 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3032630871 Feb 25 01:27:42 PM PST 24 Feb 25 01:27:43 PM PST 24 19864142 ps
T564 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1685623098 Feb 25 01:27:46 PM PST 24 Feb 25 01:27:49 PM PST 24 344007305 ps
T565 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.131830478 Feb 25 01:27:17 PM PST 24 Feb 25 01:27:17 PM PST 24 15343476 ps
T566 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3688224442 Feb 25 01:27:40 PM PST 24 Feb 25 01:27:40 PM PST 24 14201813 ps
T567 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1120170040 Feb 25 01:27:55 PM PST 24 Feb 25 01:27:56 PM PST 24 50795991 ps
T568 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1349600082 Feb 25 01:27:49 PM PST 24 Feb 25 01:27:50 PM PST 24 34297826 ps
T569 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2409265575 Feb 25 01:27:09 PM PST 24 Feb 25 01:27:11 PM PST 24 200834412 ps
T570 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.4030048216 Feb 25 01:27:53 PM PST 24 Feb 25 01:27:54 PM PST 24 32283537 ps
T571 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.4003916470 Feb 25 01:27:48 PM PST 24 Feb 25 01:27:49 PM PST 24 194568898 ps
T572 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.895179016 Feb 25 01:27:47 PM PST 24 Feb 25 01:27:48 PM PST 24 49115806 ps
T573 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.182202198 Feb 25 01:27:48 PM PST 24 Feb 25 01:27:49 PM PST 24 17470505 ps
T574 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3401512438 Feb 25 01:27:36 PM PST 24 Feb 25 01:27:39 PM PST 24 147931102 ps
T109 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1041780868 Feb 25 01:27:43 PM PST 24 Feb 25 01:27:43 PM PST 24 34761428 ps
T575 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.531658325 Feb 25 01:27:44 PM PST 24 Feb 25 01:27:46 PM PST 24 30293628 ps
T576 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1893964953 Feb 25 01:27:20 PM PST 24 Feb 25 01:27:22 PM PST 24 137793421 ps
T577 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1210869452 Feb 25 01:27:48 PM PST 24 Feb 25 01:27:50 PM PST 24 254556005 ps
T578 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.863889655 Feb 25 01:27:32 PM PST 24 Feb 25 01:27:33 PM PST 24 364126479 ps
T579 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.868550071 Feb 25 01:27:43 PM PST 24 Feb 25 01:27:43 PM PST 24 26029396 ps
T580 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.321674130 Feb 25 01:27:19 PM PST 24 Feb 25 01:27:20 PM PST 24 40261240 ps
T581 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.4082046198 Feb 25 01:27:52 PM PST 24 Feb 25 01:27:53 PM PST 24 67542390 ps
T582 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.219917033 Feb 25 01:27:43 PM PST 24 Feb 25 01:27:45 PM PST 24 206874338 ps

Test location /workspace/coverage/default/156.rv_timer_random.328718278
Short name T5
Test name
Test status
Simulation time 350419466686 ps
CPU time 332.38 seconds
Started Feb 25 01:48:49 PM PST 24
Finished Feb 25 01:54:22 PM PST 24
Peak memory 190956 kb
Host smart-a05b9b08-c747-49f0-9f33-a0aa9e37d74f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328718278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.328718278
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.3150725646
Short name T14
Test name
Test status
Simulation time 126679677753 ps
CPU time 612.67 seconds
Started Feb 25 01:47:21 PM PST 24
Finished Feb 25 01:57:35 PM PST 24
Peak memory 206388 kb
Host smart-a33b010b-e2d3-4056-aab1-3b602e5eeccd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150725646 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.3150725646
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2302680962
Short name T30
Test name
Test status
Simulation time 352201385 ps
CPU time 1.14 seconds
Started Feb 25 01:27:44 PM PST 24
Finished Feb 25 01:27:46 PM PST 24
Peak memory 182944 kb
Host smart-2eaa6e8e-40f9-4602-be0f-165541551b7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302680962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2302680962
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.1733454766
Short name T147
Test name
Test status
Simulation time 4817049407615 ps
CPU time 4376.71 seconds
Started Feb 25 01:47:28 PM PST 24
Finished Feb 25 03:00:27 PM PST 24
Peak memory 190988 kb
Host smart-1f1185ef-bcd7-4bea-a446-a4651b0a9541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733454766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.1733454766
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3119348914
Short name T59
Test name
Test status
Simulation time 2245584332851 ps
CPU time 2242.5 seconds
Started Feb 25 01:47:41 PM PST 24
Finished Feb 25 02:25:03 PM PST 24
Peak memory 190972 kb
Host smart-d18b91cf-3ce5-4814-b18d-939f30dde513
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119348914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3119348914
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.3827444764
Short name T163
Test name
Test status
Simulation time 1047260233657 ps
CPU time 2887.61 seconds
Started Feb 25 01:47:33 PM PST 24
Finished Feb 25 02:35:41 PM PST 24
Peak memory 195600 kb
Host smart-59943c94-e38e-4fa3-a838-2028ff572c34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827444764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.3827444764
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_random.1820832055
Short name T133
Test name
Test status
Simulation time 2428935360054 ps
CPU time 712.2 seconds
Started Feb 25 01:47:19 PM PST 24
Finished Feb 25 01:59:13 PM PST 24
Peak memory 190956 kb
Host smart-eeb4f2f0-7dfd-4ae4-ac4a-7b5be981fdda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820832055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1820832055
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3407352529
Short name T164
Test name
Test status
Simulation time 442710136032 ps
CPU time 1164.54 seconds
Started Feb 25 01:47:41 PM PST 24
Finished Feb 25 02:07:05 PM PST 24
Peak memory 190964 kb
Host smart-54ad097f-095f-45e5-bac5-9b0fb34c63f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407352529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3407352529
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.2150542513
Short name T142
Test name
Test status
Simulation time 408464014890 ps
CPU time 1030.03 seconds
Started Feb 25 01:47:16 PM PST 24
Finished Feb 25 02:04:26 PM PST 24
Peak memory 194924 kb
Host smart-8184f267-9306-4caf-ae59-8bf47bf10d45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150542513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
2150542513
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.201306441
Short name T215
Test name
Test status
Simulation time 3049901282523 ps
CPU time 2365.62 seconds
Started Feb 25 01:47:06 PM PST 24
Finished Feb 25 02:26:32 PM PST 24
Peak memory 190988 kb
Host smart-f783f2c8-7ea6-4dd5-a234-775cecd170e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201306441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.201306441
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3199676774
Short name T218
Test name
Test status
Simulation time 340217657514 ps
CPU time 1197.61 seconds
Started Feb 25 01:47:21 PM PST 24
Finished Feb 25 02:07:20 PM PST 24
Peak memory 190908 kb
Host smart-9a354e56-dc9d-43cb-9574-78e4a29cd171
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199676774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3199676774
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2304046321
Short name T191
Test name
Test status
Simulation time 1045829729585 ps
CPU time 2104.62 seconds
Started Feb 25 01:47:19 PM PST 24
Finished Feb 25 02:22:25 PM PST 24
Peak memory 190952 kb
Host smart-11e3eae4-6217-472c-a61a-50c51579b33a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304046321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2304046321
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.726932905
Short name T101
Test name
Test status
Simulation time 44452131 ps
CPU time 0.55 seconds
Started Feb 25 01:27:04 PM PST 24
Finished Feb 25 01:27:05 PM PST 24
Peak memory 191788 kb
Host smart-099e1884-a286-48f1-9dde-c76f326b5638
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726932905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re
set.726932905
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2518560546
Short name T16
Test name
Test status
Simulation time 148186337 ps
CPU time 0.73 seconds
Started Feb 25 01:47:03 PM PST 24
Finished Feb 25 01:47:04 PM PST 24
Peak memory 212788 kb
Host smart-1830f66b-5008-4507-adb4-452cbfe6a11d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518560546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2518560546
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2338315052
Short name T71
Test name
Test status
Simulation time 2163688667158 ps
CPU time 1593.58 seconds
Started Feb 25 01:47:08 PM PST 24
Finished Feb 25 02:13:43 PM PST 24
Peak memory 190988 kb
Host smart-b6fad212-7fb5-47ab-9880-1c14b54dd55d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338315052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2338315052
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2298625048
Short name T283
Test name
Test status
Simulation time 3129119001846 ps
CPU time 2196.15 seconds
Started Feb 25 01:47:24 PM PST 24
Finished Feb 25 02:24:02 PM PST 24
Peak memory 190876 kb
Host smart-f1cc4f46-7599-4c87-ab47-5030cfa3b7e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298625048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2298625048
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/193.rv_timer_random.2342540438
Short name T120
Test name
Test status
Simulation time 620190713770 ps
CPU time 303.4 seconds
Started Feb 25 01:49:08 PM PST 24
Finished Feb 25 01:54:12 PM PST 24
Peak memory 190928 kb
Host smart-9f88ce3e-7b08-4743-a1c7-600564dc6f28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342540438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2342540438
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.3750517774
Short name T49
Test name
Test status
Simulation time 229865659784 ps
CPU time 392.18 seconds
Started Feb 25 01:47:32 PM PST 24
Finished Feb 25 01:54:04 PM PST 24
Peak memory 190924 kb
Host smart-98280bfb-71cf-4d1c-979b-04b3695df37f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750517774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.3750517774
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/58.rv_timer_random.556310555
Short name T197
Test name
Test status
Simulation time 253763051717 ps
CPU time 270.19 seconds
Started Feb 25 01:47:55 PM PST 24
Finished Feb 25 01:52:25 PM PST 24
Peak memory 190952 kb
Host smart-1d6506d3-ad46-432d-b062-56b0025559f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556310555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.556310555
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.4232222396
Short name T2
Test name
Test status
Simulation time 854522937703 ps
CPU time 1358.9 seconds
Started Feb 25 01:48:51 PM PST 24
Finished Feb 25 02:11:31 PM PST 24
Peak memory 190972 kb
Host smart-66bad007-cf40-4afd-b360-6e8015b3cf10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232222396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.4232222396
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3583729068
Short name T70
Test name
Test status
Simulation time 666244623941 ps
CPU time 1286.65 seconds
Started Feb 25 01:47:22 PM PST 24
Finished Feb 25 02:08:50 PM PST 24
Peak memory 190956 kb
Host smart-ec2f81fe-2cfa-4f85-9150-af30c93209b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583729068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3583729068
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1801103329
Short name T252
Test name
Test status
Simulation time 1243661193123 ps
CPU time 2361.02 seconds
Started Feb 25 01:47:59 PM PST 24
Finished Feb 25 02:27:20 PM PST 24
Peak memory 195568 kb
Host smart-f8571a8b-16bb-4f0d-b8c4-f4ed2ea98794
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801103329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1801103329
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/115.rv_timer_random.103308480
Short name T192
Test name
Test status
Simulation time 130690245858 ps
CPU time 296.3 seconds
Started Feb 25 01:48:21 PM PST 24
Finished Feb 25 01:53:17 PM PST 24
Peak memory 190908 kb
Host smart-aeaa2f4f-796f-4c26-9fc3-ba3ef8954ff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103308480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.103308480
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.664487675
Short name T47
Test name
Test status
Simulation time 145450030400 ps
CPU time 704.28 seconds
Started Feb 25 01:48:17 PM PST 24
Finished Feb 25 02:00:01 PM PST 24
Peak memory 190952 kb
Host smart-8fe7b262-1eef-436e-867f-dd7c6cc0c990
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664487675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.664487675
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.2904943895
Short name T223
Test name
Test status
Simulation time 147460242122 ps
CPU time 609.3 seconds
Started Feb 25 01:48:26 PM PST 24
Finished Feb 25 01:58:36 PM PST 24
Peak memory 194164 kb
Host smart-c639b5ca-00c3-48a3-9f15-5661a0a1ec7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904943895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2904943895
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1130662965
Short name T289
Test name
Test status
Simulation time 700574595055 ps
CPU time 2721.86 seconds
Started Feb 25 01:47:03 PM PST 24
Finished Feb 25 02:32:25 PM PST 24
Peak memory 190948 kb
Host smart-1b73cc78-626c-4513-b9e6-cc22092f5dd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130662965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1130662965
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/118.rv_timer_random.1120473142
Short name T239
Test name
Test status
Simulation time 185141877249 ps
CPU time 803.85 seconds
Started Feb 25 01:48:25 PM PST 24
Finished Feb 25 02:01:49 PM PST 24
Peak memory 190964 kb
Host smart-7f400b4a-f65b-4298-a8d1-ebe67dffb429
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120473142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1120473142
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2348308749
Short name T187
Test name
Test status
Simulation time 466376092439 ps
CPU time 204.88 seconds
Started Feb 25 01:48:34 PM PST 24
Finished Feb 25 01:52:00 PM PST 24
Peak memory 194268 kb
Host smart-fd341c37-90e6-4e97-a272-34c675666ae7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348308749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2348308749
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.3671868457
Short name T208
Test name
Test status
Simulation time 1579621694560 ps
CPU time 2905.66 seconds
Started Feb 25 01:49:06 PM PST 24
Finished Feb 25 02:37:33 PM PST 24
Peak memory 190788 kb
Host smart-3e5e128d-e173-4c8c-b322-f5e7468cc1ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671868457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3671868457
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.394535161
Short name T140
Test name
Test status
Simulation time 755180272526 ps
CPU time 1410.87 seconds
Started Feb 25 01:47:58 PM PST 24
Finished Feb 25 02:11:30 PM PST 24
Peak memory 190948 kb
Host smart-708c2d35-beef-4ce6-b5f4-4b6309c0de60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394535161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.394535161
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.3126319766
Short name T231
Test name
Test status
Simulation time 856701605469 ps
CPU time 256.91 seconds
Started Feb 25 01:49:05 PM PST 24
Finished Feb 25 01:53:22 PM PST 24
Peak memory 191004 kb
Host smart-572f7d9f-fdf0-44da-8044-9ae5e16e3974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126319766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3126319766
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.144252181
Short name T325
Test name
Test status
Simulation time 117861338324 ps
CPU time 155.78 seconds
Started Feb 25 01:49:11 PM PST 24
Finished Feb 25 01:51:47 PM PST 24
Peak memory 195128 kb
Host smart-b5a87d63-8100-4ce3-91c2-ee1952990b3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144252181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.144252181
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.3750431794
Short name T148
Test name
Test status
Simulation time 96577954143 ps
CPU time 376.15 seconds
Started Feb 25 01:49:12 PM PST 24
Finished Feb 25 01:55:28 PM PST 24
Peak memory 190952 kb
Host smart-43d7f830-f200-48d5-be5b-503b6733eaaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750431794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3750431794
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random.3090010939
Short name T170
Test name
Test status
Simulation time 825262205144 ps
CPU time 493.98 seconds
Started Feb 25 01:47:25 PM PST 24
Finished Feb 25 01:55:41 PM PST 24
Peak memory 194096 kb
Host smart-1a587b4c-8f98-4040-9937-e5f75ac48254
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090010939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3090010939
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1706472690
Short name T69
Test name
Test status
Simulation time 322143114615 ps
CPU time 247.65 seconds
Started Feb 25 01:47:36 PM PST 24
Finished Feb 25 01:51:44 PM PST 24
Peak memory 190952 kb
Host smart-6f6bb3b8-d893-4756-95ab-be3efb60955a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706472690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1706472690
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/81.rv_timer_random.3810277118
Short name T138
Test name
Test status
Simulation time 385422725884 ps
CPU time 365.92 seconds
Started Feb 25 01:48:00 PM PST 24
Finished Feb 25 01:54:06 PM PST 24
Peak memory 190960 kb
Host smart-9c6fda8c-56b6-49b7-b527-ef260d493414
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810277118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.3810277118
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.922718889
Short name T53
Test name
Test status
Simulation time 27104482 ps
CPU time 0.65 seconds
Started Feb 25 01:27:44 PM PST 24
Finished Feb 25 01:27:45 PM PST 24
Peak memory 191756 kb
Host smart-18eefff4-b953-496f-8df1-2ea012aa1abd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922718889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_ti
mer_same_csr_outstanding.922718889
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/14.rv_timer_random.3332515087
Short name T183
Test name
Test status
Simulation time 178557903146 ps
CPU time 311.8 seconds
Started Feb 25 01:47:14 PM PST 24
Finished Feb 25 01:52:27 PM PST 24
Peak memory 190948 kb
Host smart-2812afb4-f89d-447c-a3b1-54385aea7c90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332515087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3332515087
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.507263799
Short name T209
Test name
Test status
Simulation time 683963550105 ps
CPU time 306.89 seconds
Started Feb 25 01:48:51 PM PST 24
Finished Feb 25 01:53:58 PM PST 24
Peak memory 194416 kb
Host smart-91d537f9-3523-4932-909e-c359d0b03335
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507263799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.507263799
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.2117100934
Short name T175
Test name
Test status
Simulation time 135050881448 ps
CPU time 652.36 seconds
Started Feb 25 01:47:20 PM PST 24
Finished Feb 25 01:58:13 PM PST 24
Peak memory 190948 kb
Host smart-646156e2-34f1-4362-8517-f1f216dcd16a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117100934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2117100934
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.3208430581
Short name T178
Test name
Test status
Simulation time 74354966197 ps
CPU time 243.63 seconds
Started Feb 25 01:47:50 PM PST 24
Finished Feb 25 01:51:53 PM PST 24
Peak memory 190948 kb
Host smart-b89c3d26-a006-4391-9b28-05a54ff2624c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208430581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3208430581
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/70.rv_timer_random.3715213539
Short name T190
Test name
Test status
Simulation time 599603789103 ps
CPU time 322.93 seconds
Started Feb 25 01:48:02 PM PST 24
Finished Feb 25 01:53:25 PM PST 24
Peak memory 194416 kb
Host smart-ac8a2d5b-a301-402b-9325-befa2be130dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715213539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3715213539
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random.974460705
Short name T249
Test name
Test status
Simulation time 386966004739 ps
CPU time 269.68 seconds
Started Feb 25 01:47:10 PM PST 24
Finished Feb 25 01:51:40 PM PST 24
Peak memory 190964 kb
Host smart-d0227a98-6c41-443e-bb6e-4863f1964fa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974460705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.974460705
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1188039641
Short name T358
Test name
Test status
Simulation time 514514720701 ps
CPU time 521.9 seconds
Started Feb 25 01:48:44 PM PST 24
Finished Feb 25 01:57:27 PM PST 24
Peak memory 190984 kb
Host smart-ea2edd18-7c07-4fba-9ff5-2f5385aafe47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188039641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1188039641
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.595210297
Short name T363
Test name
Test status
Simulation time 696493297868 ps
CPU time 2048.51 seconds
Started Feb 25 01:49:06 PM PST 24
Finished Feb 25 02:23:15 PM PST 24
Peak memory 190928 kb
Host smart-4d6c1964-219d-4021-974e-c55b40ab878f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595210297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.595210297
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.220873356
Short name T205
Test name
Test status
Simulation time 114557206591 ps
CPU time 172.94 seconds
Started Feb 25 01:49:14 PM PST 24
Finished Feb 25 01:52:07 PM PST 24
Peak memory 190912 kb
Host smart-75b623fb-ad15-4606-a118-3354b93c14ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220873356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.220873356
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random.172062237
Short name T13
Test name
Test status
Simulation time 112777817584 ps
CPU time 409.81 seconds
Started Feb 25 01:47:29 PM PST 24
Finished Feb 25 01:54:19 PM PST 24
Peak memory 190948 kb
Host smart-68168ba8-8e2d-4629-ac31-9352e04def25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172062237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.172062237
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3340897978
Short name T214
Test name
Test status
Simulation time 163548167719 ps
CPU time 326.15 seconds
Started Feb 25 01:48:08 PM PST 24
Finished Feb 25 01:53:34 PM PST 24
Peak memory 190892 kb
Host smart-55cfd444-29ad-476f-99a2-e21e45fc49ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340897978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3340897978
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.1845131134
Short name T157
Test name
Test status
Simulation time 587208210840 ps
CPU time 444.26 seconds
Started Feb 25 01:47:14 PM PST 24
Finished Feb 25 01:54:39 PM PST 24
Peak memory 190960 kb
Host smart-82afe9f3-5757-4da3-8104-2fd871cf49f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845131134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1845131134
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.2278653965
Short name T284
Test name
Test status
Simulation time 138691978513 ps
CPU time 365.52 seconds
Started Feb 25 01:48:21 PM PST 24
Finished Feb 25 01:54:27 PM PST 24
Peak memory 190924 kb
Host smart-cc4b2d6d-6136-4cef-aa18-365b5a0ba8be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278653965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2278653965
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.3752483873
Short name T4
Test name
Test status
Simulation time 159431055811 ps
CPU time 1575.43 seconds
Started Feb 25 01:48:24 PM PST 24
Finished Feb 25 02:14:40 PM PST 24
Peak memory 190904 kb
Host smart-f6d6470f-795a-4683-b56e-9a5a41dd295d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752483873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3752483873
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.2156952309
Short name T266
Test name
Test status
Simulation time 119550183536 ps
CPU time 193.94 seconds
Started Feb 25 01:48:25 PM PST 24
Finished Feb 25 01:51:39 PM PST 24
Peak memory 194404 kb
Host smart-bcb10741-75ab-4965-a32b-fa45a0491079
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156952309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2156952309
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/130.rv_timer_random.1861294681
Short name T276
Test name
Test status
Simulation time 353306057872 ps
CPU time 368.31 seconds
Started Feb 25 01:48:37 PM PST 24
Finished Feb 25 01:54:45 PM PST 24
Peak memory 190968 kb
Host smart-1af67e50-aabf-4f09-b0db-765d7f26b183
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861294681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1861294681
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3256247791
Short name T150
Test name
Test status
Simulation time 160844734368 ps
CPU time 656.5 seconds
Started Feb 25 01:48:45 PM PST 24
Finished Feb 25 01:59:42 PM PST 24
Peak memory 182752 kb
Host smart-7cad8690-810f-451a-9caf-2bf1e31e74e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256247791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3256247791
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random.2634755192
Short name T292
Test name
Test status
Simulation time 1122824999097 ps
CPU time 1042.58 seconds
Started Feb 25 01:47:18 PM PST 24
Finished Feb 25 02:04:41 PM PST 24
Peak memory 190952 kb
Host smart-bb6173a8-d1a4-48ff-a925-962ee4a00b40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634755192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2634755192
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random.537270076
Short name T229
Test name
Test status
Simulation time 180770472985 ps
CPU time 465.12 seconds
Started Feb 25 01:47:46 PM PST 24
Finished Feb 25 01:55:31 PM PST 24
Peak memory 194340 kb
Host smart-d156cd48-64ec-40a4-ba43-adf86db0b899
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537270076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.537270076
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.3823181998
Short name T326
Test name
Test status
Simulation time 634882504691 ps
CPU time 1092.82 seconds
Started Feb 25 01:48:08 PM PST 24
Finished Feb 25 02:06:21 PM PST 24
Peak memory 190892 kb
Host smart-b23f7963-5f48-4bd4-8e6d-616c85a70646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823181998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3823181998
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3353543979
Short name T303
Test name
Test status
Simulation time 836836340646 ps
CPU time 2863.8 seconds
Started Feb 25 01:47:25 PM PST 24
Finished Feb 25 02:35:10 PM PST 24
Peak memory 191008 kb
Host smart-1d3a366b-ef06-4991-a583-54faea8ef758
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353543979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3353543979
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_random.3077521060
Short name T241
Test name
Test status
Simulation time 248539142242 ps
CPU time 135.26 seconds
Started Feb 25 01:47:05 PM PST 24
Finished Feb 25 01:49:20 PM PST 24
Peak memory 190948 kb
Host smart-154cff30-869f-4b67-88fa-4ef4138101f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077521060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3077521060
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2143626790
Short name T151
Test name
Test status
Simulation time 274335567233 ps
CPU time 254.85 seconds
Started Feb 25 01:47:19 PM PST 24
Finished Feb 25 01:51:35 PM PST 24
Peak memory 182780 kb
Host smart-0879aa84-e007-4f71-99ab-58c1d8d87f88
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143626790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.2143626790
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/107.rv_timer_random.409700254
Short name T139
Test name
Test status
Simulation time 785431004808 ps
CPU time 760.53 seconds
Started Feb 25 01:48:17 PM PST 24
Finished Feb 25 02:00:58 PM PST 24
Peak memory 190968 kb
Host smart-517bcbfb-9022-41f4-ba2a-62cc4d166a85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409700254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.409700254
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.2488554736
Short name T77
Test name
Test status
Simulation time 262922326768 ps
CPU time 1852.77 seconds
Started Feb 25 01:48:24 PM PST 24
Finished Feb 25 02:19:18 PM PST 24
Peak memory 190792 kb
Host smart-4b3b2dea-4714-48b5-92b2-2100a6c78802
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488554736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2488554736
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.3054116689
Short name T58
Test name
Test status
Simulation time 527277193497 ps
CPU time 864.92 seconds
Started Feb 25 01:48:31 PM PST 24
Finished Feb 25 02:02:57 PM PST 24
Peak memory 190952 kb
Host smart-c620225e-17d5-4b84-9df8-17f7f97e5287
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054116689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3054116689
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1187103578
Short name T274
Test name
Test status
Simulation time 577524690696 ps
CPU time 1864.29 seconds
Started Feb 25 01:48:33 PM PST 24
Finished Feb 25 02:19:38 PM PST 24
Peak memory 190948 kb
Host smart-eae4dcfa-255f-4c19-bb51-b4be773541a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187103578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1187103578
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3685561881
Short name T155
Test name
Test status
Simulation time 41320957075 ps
CPU time 64.19 seconds
Started Feb 25 01:48:37 PM PST 24
Finished Feb 25 01:49:41 PM PST 24
Peak memory 192072 kb
Host smart-74ddd559-1a96-49dd-b465-55207f342861
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685561881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3685561881
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.3880293093
Short name T212
Test name
Test status
Simulation time 127959134578 ps
CPU time 571.12 seconds
Started Feb 25 01:48:52 PM PST 24
Finished Feb 25 01:58:23 PM PST 24
Peak memory 191080 kb
Host smart-5fce413b-4fe7-4b3d-ac9a-7298f217f65e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880293093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3880293093
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.588133815
Short name T207
Test name
Test status
Simulation time 90794026049 ps
CPU time 411.39 seconds
Started Feb 25 01:49:08 PM PST 24
Finished Feb 25 01:56:00 PM PST 24
Peak memory 190892 kb
Host smart-39798036-839b-44c5-887b-502f0714d351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588133815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.588133815
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random.2311759203
Short name T9
Test name
Test status
Simulation time 76042923169 ps
CPU time 104.53 seconds
Started Feb 25 01:47:24 PM PST 24
Finished Feb 25 01:49:10 PM PST 24
Peak memory 190948 kb
Host smart-edfe7404-1c83-4283-9601-0c82d5ecd8ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311759203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2311759203
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2687311522
Short name T244
Test name
Test status
Simulation time 157998490876 ps
CPU time 131.77 seconds
Started Feb 25 01:48:08 PM PST 24
Finished Feb 25 01:50:20 PM PST 24
Peak memory 182760 kb
Host smart-e9f6d449-ac5c-4560-b14d-0ab06f352e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687311522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2687311522
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/79.rv_timer_random.1106854689
Short name T267
Test name
Test status
Simulation time 93240103412 ps
CPU time 136.33 seconds
Started Feb 25 01:47:57 PM PST 24
Finished Feb 25 01:50:14 PM PST 24
Peak memory 190940 kb
Host smart-d18d70a6-46a7-401e-bd89-38d9d578fd21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106854689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1106854689
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.851879461
Short name T91
Test name
Test status
Simulation time 52968671181 ps
CPU time 214.42 seconds
Started Feb 25 01:47:04 PM PST 24
Finished Feb 25 01:50:39 PM PST 24
Peak memory 182768 kb
Host smart-1246f132-1c9b-4a41-8981-006268edd277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851879461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.851879461
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/82.rv_timer_random.3705517168
Short name T287
Test name
Test status
Simulation time 112082962951 ps
CPU time 194.13 seconds
Started Feb 25 01:48:02 PM PST 24
Finished Feb 25 01:51:17 PM PST 24
Peak memory 190952 kb
Host smart-3271887e-0f3b-4c1c-bc22-37cce261ffc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705517168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3705517168
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.556204424
Short name T365
Test name
Test status
Simulation time 107356311294 ps
CPU time 279.65 seconds
Started Feb 25 01:48:09 PM PST 24
Finished Feb 25 01:52:48 PM PST 24
Peak memory 190952 kb
Host smart-e3a27841-aeb9-4955-b4fb-f2e721544bf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556204424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.556204424
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2798827897
Short name T127
Test name
Test status
Simulation time 450997876 ps
CPU time 1.45 seconds
Started Feb 25 01:27:40 PM PST 24
Finished Feb 25 01:27:41 PM PST 24
Peak memory 194712 kb
Host smart-7f3d2bf4-10e8-4dda-85c6-774c8b53372c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798827897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2798827897
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2598345961
Short name T237
Test name
Test status
Simulation time 1443976680835 ps
CPU time 587.71 seconds
Started Feb 25 01:47:06 PM PST 24
Finished Feb 25 01:56:54 PM PST 24
Peak memory 182792 kb
Host smart-6727345d-c62e-467d-a61a-6912face99cc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598345961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2598345961
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/100.rv_timer_random.1166780146
Short name T225
Test name
Test status
Simulation time 191885071117 ps
CPU time 868.57 seconds
Started Feb 25 01:48:17 PM PST 24
Finished Feb 25 02:02:46 PM PST 24
Peak memory 190968 kb
Host smart-7d56fbbe-9ac8-468b-b465-c8130d5ccd3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166780146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1166780146
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.2482789665
Short name T304
Test name
Test status
Simulation time 1977937635 ps
CPU time 1.42 seconds
Started Feb 25 01:48:13 PM PST 24
Finished Feb 25 01:48:15 PM PST 24
Peak memory 182668 kb
Host smart-456adec1-b62d-4ed1-ae69-9f7139bddd89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482789665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2482789665
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.2815096606
Short name T230
Test name
Test status
Simulation time 177220795504 ps
CPU time 505.19 seconds
Started Feb 25 01:48:18 PM PST 24
Finished Feb 25 01:56:43 PM PST 24
Peak memory 190928 kb
Host smart-60542f86-a020-44b4-8f83-4b8737ad07a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815096606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2815096606
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.1801873989
Short name T323
Test name
Test status
Simulation time 746065568810 ps
CPU time 1083.96 seconds
Started Feb 25 01:48:24 PM PST 24
Finished Feb 25 02:06:29 PM PST 24
Peak memory 190960 kb
Host smart-1d68f9ae-f829-4411-94f4-d73f18f81c3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801873989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1801873989
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3516090243
Short name T156
Test name
Test status
Simulation time 45971171309 ps
CPU time 77.83 seconds
Started Feb 25 01:47:17 PM PST 24
Finished Feb 25 01:48:35 PM PST 24
Peak memory 182780 kb
Host smart-90de1823-048b-4770-a314-2a32258474c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516090243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.3516090243
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/138.rv_timer_random.2075040658
Short name T136
Test name
Test status
Simulation time 728310678450 ps
CPU time 224.91 seconds
Started Feb 25 01:48:37 PM PST 24
Finished Feb 25 01:52:22 PM PST 24
Peak memory 194436 kb
Host smart-92702a59-5554-4896-81e6-1bf47f22a050
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075040658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2075040658
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.2974736082
Short name T273
Test name
Test status
Simulation time 133551607576 ps
CPU time 595.8 seconds
Started Feb 25 01:48:45 PM PST 24
Finished Feb 25 01:58:41 PM PST 24
Peak memory 190980 kb
Host smart-9a39c762-d27e-4385-8968-16e84b2ea811
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974736082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2974736082
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/160.rv_timer_random.1580618906
Short name T228
Test name
Test status
Simulation time 66843721813 ps
CPU time 89.61 seconds
Started Feb 25 01:48:51 PM PST 24
Finished Feb 25 01:50:21 PM PST 24
Peak memory 190980 kb
Host smart-b9792073-c68e-4b72-acc8-c5901aa358aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580618906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1580618906
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.3479196396
Short name T173
Test name
Test status
Simulation time 523554168330 ps
CPU time 392.32 seconds
Started Feb 25 01:49:06 PM PST 24
Finished Feb 25 01:55:38 PM PST 24
Peak memory 190880 kb
Host smart-d68deab5-182a-43c2-bd57-95f06a693455
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479196396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3479196396
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.1777680059
Short name T143
Test name
Test status
Simulation time 324622066041 ps
CPU time 414.72 seconds
Started Feb 25 01:49:06 PM PST 24
Finished Feb 25 01:56:01 PM PST 24
Peak memory 190884 kb
Host smart-8aea1b8b-1313-435b-9edd-b5d555c9aede
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777680059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1777680059
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.1478358998
Short name T134
Test name
Test status
Simulation time 93464873743 ps
CPU time 703.45 seconds
Started Feb 25 01:49:05 PM PST 24
Finished Feb 25 02:00:49 PM PST 24
Peak memory 190964 kb
Host smart-021d363e-9c1c-4aca-89a7-28013c39f474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478358998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1478358998
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1315431176
Short name T176
Test name
Test status
Simulation time 398560371961 ps
CPU time 305.42 seconds
Started Feb 25 01:49:13 PM PST 24
Finished Feb 25 01:54:18 PM PST 24
Peak memory 190964 kb
Host smart-29367a78-196f-4929-a4cf-861da9c12e31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315431176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1315431176
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random.925176260
Short name T306
Test name
Test status
Simulation time 53991497708 ps
CPU time 27.91 seconds
Started Feb 25 01:47:19 PM PST 24
Finished Feb 25 01:47:47 PM PST 24
Peak memory 182760 kb
Host smart-ef17f34b-d2e5-4dfb-a7ad-946015a30615
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925176260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.925176260
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.86429761
Short name T67
Test name
Test status
Simulation time 748207724963 ps
CPU time 685.22 seconds
Started Feb 25 01:47:21 PM PST 24
Finished Feb 25 01:58:47 PM PST 24
Peak memory 191016 kb
Host smart-00dd0e5f-930a-44c7-b209-cf8c936729d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86429761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.86429761
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2420685657
Short name T219
Test name
Test status
Simulation time 2224334684277 ps
CPU time 552.71 seconds
Started Feb 25 01:47:16 PM PST 24
Finished Feb 25 01:56:29 PM PST 24
Peak memory 194224 kb
Host smart-e65d09e2-8162-4dc2-9ca8-5c91f58b7803
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420685657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2420685657
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.23163385
Short name T181
Test name
Test status
Simulation time 401063143901 ps
CPU time 403.37 seconds
Started Feb 25 01:47:31 PM PST 24
Finished Feb 25 01:54:15 PM PST 24
Peak memory 182792 kb
Host smart-99a158dc-3e93-4062-90cd-f3210bd6e621
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23163385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.rv_timer_cfg_update_on_fly.23163385
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_random.4071548492
Short name T344
Test name
Test status
Simulation time 240622769829 ps
CPU time 129.53 seconds
Started Feb 25 01:47:30 PM PST 24
Finished Feb 25 01:49:40 PM PST 24
Peak memory 190888 kb
Host smart-9777aea2-4306-445b-a974-d08bf6d68b22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071548492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.4071548492
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.4290455290
Short name T74
Test name
Test status
Simulation time 472219012513 ps
CPU time 1044.09 seconds
Started Feb 25 01:47:32 PM PST 24
Finished Feb 25 02:04:56 PM PST 24
Peak memory 194076 kb
Host smart-6181c1cb-b443-4b23-939f-a28914294c40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290455290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.4290455290
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.65498437
Short name T202
Test name
Test status
Simulation time 686575041807 ps
CPU time 1188.71 seconds
Started Feb 25 01:47:40 PM PST 24
Finished Feb 25 02:07:29 PM PST 24
Peak memory 190956 kb
Host smart-3586ba5c-2396-4b2a-a9af-1334ea4a93f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65498437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.65498437
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_random.3869130535
Short name T227
Test name
Test status
Simulation time 36235941295 ps
CPU time 79.64 seconds
Started Feb 25 01:47:12 PM PST 24
Finished Feb 25 01:48:32 PM PST 24
Peak memory 190904 kb
Host smart-44d9b2b8-e75b-4072-b508-e0bf480edb59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869130535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3869130535
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.2456823349
Short name T351
Test name
Test status
Simulation time 571605215309 ps
CPU time 388.11 seconds
Started Feb 25 01:48:09 PM PST 24
Finished Feb 25 01:54:37 PM PST 24
Peak memory 190952 kb
Host smart-7cd52679-ab61-4df0-8d64-2b96f50993b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456823349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2456823349
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.3943775399
Short name T23
Test name
Test status
Simulation time 604132240973 ps
CPU time 587.89 seconds
Started Feb 25 01:47:18 PM PST 24
Finished Feb 25 01:57:07 PM PST 24
Peak memory 182780 kb
Host smart-4536f4a0-7390-484c-980b-f5512e10dfbc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943775399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.3943775399
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2283459027
Short name T93
Test name
Test status
Simulation time 70453798 ps
CPU time 0.6 seconds
Started Feb 25 01:27:07 PM PST 24
Finished Feb 25 01:27:07 PM PST 24
Peak memory 182556 kb
Host smart-76f3bad7-8865-4a39-b54c-94c4e6592bd5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283459027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.2283459027
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3953179277
Short name T544
Test name
Test status
Simulation time 66867463 ps
CPU time 2.33 seconds
Started Feb 25 01:27:03 PM PST 24
Finished Feb 25 01:27:06 PM PST 24
Peak memory 191948 kb
Host smart-15517b8d-c41c-406f-985c-b9f1447d4ae7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953179277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3953179277
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.4242221223
Short name T498
Test name
Test status
Simulation time 19580508 ps
CPU time 0.61 seconds
Started Feb 25 01:27:03 PM PST 24
Finished Feb 25 01:27:04 PM PST 24
Peak memory 182520 kb
Host smart-d8446186-69e8-4bbf-b859-f51304d969ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242221223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.4242221223
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3091158853
Short name T509
Test name
Test status
Simulation time 31575208 ps
CPU time 0.64 seconds
Started Feb 25 01:27:07 PM PST 24
Finished Feb 25 01:27:08 PM PST 24
Peak memory 193372 kb
Host smart-bd019ff8-5b8d-44e7-939b-8a2c7b1f8368
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091158853 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3091158853
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1669613974
Short name T57
Test name
Test status
Simulation time 17996546 ps
CPU time 0.65 seconds
Started Feb 25 01:27:02 PM PST 24
Finished Feb 25 01:27:02 PM PST 24
Peak memory 182556 kb
Host smart-81e9bda3-6658-4c7a-865f-bdd352772f8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669613974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1669613974
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3982141856
Short name T493
Test name
Test status
Simulation time 14289888 ps
CPU time 0.54 seconds
Started Feb 25 01:27:07 PM PST 24
Finished Feb 25 01:27:08 PM PST 24
Peak memory 181748 kb
Host smart-97182340-fd92-42b8-b7a5-9e201b6a00d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982141856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3982141856
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1623081995
Short name T537
Test name
Test status
Simulation time 21081658 ps
CPU time 0.61 seconds
Started Feb 25 01:27:03 PM PST 24
Finished Feb 25 01:27:04 PM PST 24
Peak memory 190904 kb
Host smart-2c3ccf4a-e415-4e81-ab07-588f45640fea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623081995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1623081995
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1197991280
Short name T486
Test name
Test status
Simulation time 151584124 ps
CPU time 1.87 seconds
Started Feb 25 01:27:05 PM PST 24
Finished Feb 25 01:27:07 PM PST 24
Peak memory 197240 kb
Host smart-9b280aa1-075f-43e1-ab55-b6a3abab7a33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197991280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1197991280
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.4013565115
Short name T519
Test name
Test status
Simulation time 45158140 ps
CPU time 0.84 seconds
Started Feb 25 01:27:09 PM PST 24
Finished Feb 25 01:27:10 PM PST 24
Peak memory 182680 kb
Host smart-f0e7c998-5b63-4a1b-8ada-d0e3922f9b4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013565115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.4013565115
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1258646448
Short name T104
Test name
Test status
Simulation time 59210414 ps
CPU time 0.62 seconds
Started Feb 25 01:27:06 PM PST 24
Finished Feb 25 01:27:07 PM PST 24
Peak memory 182516 kb
Host smart-428cd658-73c5-409b-994f-1f9bb47b91ce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258646448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1258646448
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3249039942
Short name T532
Test name
Test status
Simulation time 251313394 ps
CPU time 2.52 seconds
Started Feb 25 01:27:04 PM PST 24
Finished Feb 25 01:27:07 PM PST 24
Peak memory 190860 kb
Host smart-cd6a23eb-e8cb-437b-8515-e7e8aaf3dc74
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249039942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.3249039942
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2153033293
Short name T472
Test name
Test status
Simulation time 18766695 ps
CPU time 0.8 seconds
Started Feb 25 01:27:04 PM PST 24
Finished Feb 25 01:27:05 PM PST 24
Peak memory 195720 kb
Host smart-2819917f-39b2-4c69-9e37-849e5683e2ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153033293 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2153033293
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3715074353
Short name T522
Test name
Test status
Simulation time 51317480 ps
CPU time 0.56 seconds
Started Feb 25 01:27:04 PM PST 24
Finished Feb 25 01:27:05 PM PST 24
Peak memory 182480 kb
Host smart-e7f74505-f381-4211-9547-a487a139d0e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715074353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3715074353
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1097556683
Short name T552
Test name
Test status
Simulation time 40040237 ps
CPU time 0.57 seconds
Started Feb 25 01:27:04 PM PST 24
Finished Feb 25 01:27:04 PM PST 24
Peak memory 182348 kb
Host smart-81a1c154-8659-412c-b019-d077930c52d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097556683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.1097556683
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3522163517
Short name T554
Test name
Test status
Simulation time 114333921 ps
CPU time 0.68 seconds
Started Feb 25 01:27:06 PM PST 24
Finished Feb 25 01:27:06 PM PST 24
Peak memory 191268 kb
Host smart-04986259-85e3-4e5a-8259-956717ec8986
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522163517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.3522163517
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.45625029
Short name T549
Test name
Test status
Simulation time 172369018 ps
CPU time 1.86 seconds
Started Feb 25 01:27:05 PM PST 24
Finished Feb 25 01:27:07 PM PST 24
Peak memory 197248 kb
Host smart-7b40535e-82f9-445a-94f5-8036b57baede
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45625029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.45625029
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.4220495485
Short name T507
Test name
Test status
Simulation time 157818045 ps
CPU time 1.07 seconds
Started Feb 25 01:27:04 PM PST 24
Finished Feb 25 01:27:05 PM PST 24
Peak memory 194424 kb
Host smart-fd194e62-520f-4852-bb81-2240f804044f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220495485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.4220495485
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1531023011
Short name T461
Test name
Test status
Simulation time 27108075 ps
CPU time 1.21 seconds
Started Feb 25 01:27:40 PM PST 24
Finished Feb 25 01:27:42 PM PST 24
Peak memory 197284 kb
Host smart-ddfdfd61-76e3-4380-b841-66b2c1af0032
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531023011 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.1531023011
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.181455756
Short name T559
Test name
Test status
Simulation time 47315022 ps
CPU time 0.56 seconds
Started Feb 25 01:27:44 PM PST 24
Finished Feb 25 01:27:45 PM PST 24
Peak memory 182568 kb
Host smart-cda00c34-3db0-4f9f-9f51-e6f70281a88c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181455756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.181455756
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3921934732
Short name T488
Test name
Test status
Simulation time 20624657 ps
CPU time 0.53 seconds
Started Feb 25 01:27:40 PM PST 24
Finished Feb 25 01:27:41 PM PST 24
Peak memory 181764 kb
Host smart-b1ab9d0c-7c84-4528-bcb8-65a6e00f3e77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921934732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3921934732
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.219917033
Short name T582
Test name
Test status
Simulation time 206874338 ps
CPU time 1.92 seconds
Started Feb 25 01:27:43 PM PST 24
Finished Feb 25 01:27:45 PM PST 24
Peak memory 197260 kb
Host smart-443090fa-dbe1-464e-8039-03361071c135
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219917033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.219917033
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3822551389
Short name T125
Test name
Test status
Simulation time 456379098 ps
CPU time 1.4 seconds
Started Feb 25 01:27:44 PM PST 24
Finished Feb 25 01:27:45 PM PST 24
Peak memory 194752 kb
Host smart-d7379c50-e4b3-4ced-bd75-6d96a30aea95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822551389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.3822551389
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2164217736
Short name T490
Test name
Test status
Simulation time 16995476 ps
CPU time 0.66 seconds
Started Feb 25 01:27:35 PM PST 24
Finished Feb 25 01:27:36 PM PST 24
Peak memory 193624 kb
Host smart-9b85e02d-0c7f-4366-9e53-c89a805dbc5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164217736 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2164217736
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.134361378
Short name T491
Test name
Test status
Simulation time 26096450 ps
CPU time 0.57 seconds
Started Feb 25 01:27:45 PM PST 24
Finished Feb 25 01:27:46 PM PST 24
Peak memory 182512 kb
Host smart-e5cc6f73-33a9-4e99-a333-58de0a9e768c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134361378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.134361378
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.397325418
Short name T547
Test name
Test status
Simulation time 12856224 ps
CPU time 0.55 seconds
Started Feb 25 01:27:43 PM PST 24
Finished Feb 25 01:27:44 PM PST 24
Peak memory 182312 kb
Host smart-4c04f214-0eaa-4e11-953a-3862ef99f81b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397325418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.397325418
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.868550071
Short name T579
Test name
Test status
Simulation time 26029396 ps
CPU time 0.62 seconds
Started Feb 25 01:27:43 PM PST 24
Finished Feb 25 01:27:43 PM PST 24
Peak memory 191708 kb
Host smart-7bbb17bd-b573-4d67-a53d-36b6c814780c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868550071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_ti
mer_same_csr_outstanding.868550071
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2114639178
Short name T52
Test name
Test status
Simulation time 530443024 ps
CPU time 2.03 seconds
Started Feb 25 01:27:45 PM PST 24
Finished Feb 25 01:27:48 PM PST 24
Peak memory 197264 kb
Host smart-6807ffca-b27a-403b-99f9-e908f6df5c44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114639178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2114639178
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.728615208
Short name T520
Test name
Test status
Simulation time 121754645 ps
CPU time 1.31 seconds
Started Feb 25 01:27:40 PM PST 24
Finished Feb 25 01:27:42 PM PST 24
Peak memory 182720 kb
Host smart-60c85408-12c0-47e2-ab2b-d88b2aa3c0f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728615208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.728615208
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3032630871
Short name T563
Test name
Test status
Simulation time 19864142 ps
CPU time 0.69 seconds
Started Feb 25 01:27:42 PM PST 24
Finished Feb 25 01:27:43 PM PST 24
Peak memory 193844 kb
Host smart-f452e539-e7c4-460d-a040-767e605c6ebb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032630871 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3032630871
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1815215210
Short name T550
Test name
Test status
Simulation time 12326529 ps
CPU time 0.61 seconds
Started Feb 25 01:27:43 PM PST 24
Finished Feb 25 01:27:43 PM PST 24
Peak memory 182556 kb
Host smart-b1e441f5-299a-43e1-a149-fc64ebba7650
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815215210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1815215210
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.262179673
Short name T475
Test name
Test status
Simulation time 143786012 ps
CPU time 0.55 seconds
Started Feb 25 01:27:37 PM PST 24
Finished Feb 25 01:27:38 PM PST 24
Peak memory 182364 kb
Host smart-09d5304b-00ac-4afa-a009-8b5189f305dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262179673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.262179673
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1469686221
Short name T110
Test name
Test status
Simulation time 126035772 ps
CPU time 0.75 seconds
Started Feb 25 01:27:40 PM PST 24
Finished Feb 25 01:27:42 PM PST 24
Peak memory 191432 kb
Host smart-ca7fdba4-8867-4e34-8fbb-f4b72125cc2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469686221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1469686221
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.531658325
Short name T575
Test name
Test status
Simulation time 30293628 ps
CPU time 1.61 seconds
Started Feb 25 01:27:44 PM PST 24
Finished Feb 25 01:27:46 PM PST 24
Peak memory 197088 kb
Host smart-c90a37d8-ae94-4d6b-82f4-9482c7c2e231
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531658325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.531658325
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2800460834
Short name T548
Test name
Test status
Simulation time 166179299 ps
CPU time 1.01 seconds
Started Feb 25 01:27:50 PM PST 24
Finished Feb 25 01:27:51 PM PST 24
Peak memory 196808 kb
Host smart-bb83a9c5-f99f-4889-bb71-3cc03fd68737
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800460834 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2800460834
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3688224442
Short name T566
Test name
Test status
Simulation time 14201813 ps
CPU time 0.62 seconds
Started Feb 25 01:27:40 PM PST 24
Finished Feb 25 01:27:40 PM PST 24
Peak memory 182556 kb
Host smart-6adefbc8-cd55-4ccf-8900-c1f74f8d14f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688224442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3688224442
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1455566755
Short name T538
Test name
Test status
Simulation time 11641751 ps
CPU time 0.53 seconds
Started Feb 25 01:27:43 PM PST 24
Finished Feb 25 01:27:43 PM PST 24
Peak memory 181704 kb
Host smart-f28c382d-9092-4a7c-ba20-6c9f2fa3c109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455566755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1455566755
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.997744355
Short name T34
Test name
Test status
Simulation time 20547784 ps
CPU time 0.77 seconds
Started Feb 25 01:27:46 PM PST 24
Finished Feb 25 01:27:47 PM PST 24
Peak memory 191492 kb
Host smart-f46a2d92-4905-4bcf-84dc-d568809ae527
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997744355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti
mer_same_csr_outstanding.997744355
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2929750702
Short name T542
Test name
Test status
Simulation time 75188142 ps
CPU time 1.14 seconds
Started Feb 25 01:27:44 PM PST 24
Finished Feb 25 01:27:45 PM PST 24
Peak memory 197016 kb
Host smart-5437878b-d82a-495a-9c44-90a4e39af027
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929750702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2929750702
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.895179016
Short name T572
Test name
Test status
Simulation time 49115806 ps
CPU time 1.17 seconds
Started Feb 25 01:27:47 PM PST 24
Finished Feb 25 01:27:48 PM PST 24
Peak memory 197248 kb
Host smart-1f212759-77a7-46fa-a11b-9f2e66125c7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895179016 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.895179016
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.608656485
Short name T525
Test name
Test status
Simulation time 15482750 ps
CPU time 0.57 seconds
Started Feb 25 01:27:48 PM PST 24
Finished Feb 25 01:27:49 PM PST 24
Peak memory 182568 kb
Host smart-92138e0f-f1dc-44a0-8ad8-4e13877f8b58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608656485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.608656485
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.943225729
Short name T457
Test name
Test status
Simulation time 19779075 ps
CPU time 0.58 seconds
Started Feb 25 01:27:46 PM PST 24
Finished Feb 25 01:27:47 PM PST 24
Peak memory 182324 kb
Host smart-a8cdf34b-c082-4dce-a73f-a74fc26b98aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943225729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.943225729
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1474337210
Short name T54
Test name
Test status
Simulation time 113715700 ps
CPU time 0.74 seconds
Started Feb 25 01:27:50 PM PST 24
Finished Feb 25 01:27:51 PM PST 24
Peak memory 192844 kb
Host smart-563efdc1-203c-4070-9a2f-b5fcae5c9f31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474337210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.1474337210
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3751949077
Short name T492
Test name
Test status
Simulation time 123130596 ps
CPU time 2.11 seconds
Started Feb 25 01:27:44 PM PST 24
Finished Feb 25 01:27:46 PM PST 24
Peak memory 197248 kb
Host smart-702188b4-bb5b-43bf-ba62-b21e145665d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751949077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3751949077
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.383734826
Short name T514
Test name
Test status
Simulation time 542320336 ps
CPU time 1.08 seconds
Started Feb 25 01:27:50 PM PST 24
Finished Feb 25 01:27:51 PM PST 24
Peak memory 182836 kb
Host smart-acbac8df-2ab2-4697-8d47-d22e5974640e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383734826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_in
tg_err.383734826
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2557861472
Short name T485
Test name
Test status
Simulation time 51265690 ps
CPU time 0.66 seconds
Started Feb 25 01:27:48 PM PST 24
Finished Feb 25 01:27:49 PM PST 24
Peak memory 193840 kb
Host smart-2e50947a-0467-4456-a654-a47ffaefdabc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557861472 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2557861472
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.606033849
Short name T95
Test name
Test status
Simulation time 22265731 ps
CPU time 0.54 seconds
Started Feb 25 01:27:46 PM PST 24
Finished Feb 25 01:27:46 PM PST 24
Peak memory 182148 kb
Host smart-33448fd2-0d55-4f68-806e-57dff15f2a63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606033849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.606033849
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.90676379
Short name T515
Test name
Test status
Simulation time 33296049 ps
CPU time 0.57 seconds
Started Feb 25 01:27:51 PM PST 24
Finished Feb 25 01:27:51 PM PST 24
Peak memory 182352 kb
Host smart-b57b1022-59c5-4c18-8789-caf375abd097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90676379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.90676379
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3837516226
Short name T56
Test name
Test status
Simulation time 147712665 ps
CPU time 0.7 seconds
Started Feb 25 01:27:46 PM PST 24
Finished Feb 25 01:27:47 PM PST 24
Peak memory 192304 kb
Host smart-42ab7a6e-a45f-4875-898c-5177f3639387
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837516226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3837516226
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2976009895
Short name T504
Test name
Test status
Simulation time 115689983 ps
CPU time 0.96 seconds
Started Feb 25 01:27:48 PM PST 24
Finished Feb 25 01:27:49 PM PST 24
Peak memory 196960 kb
Host smart-5f99436d-e909-4b88-8aa1-d12d9f2fed5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976009895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2976009895
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1210869452
Short name T577
Test name
Test status
Simulation time 254556005 ps
CPU time 1.13 seconds
Started Feb 25 01:27:48 PM PST 24
Finished Feb 25 01:27:50 PM PST 24
Peak memory 194904 kb
Host smart-2a394596-dd03-483f-af4d-e5e2aad8bba3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210869452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1210869452
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1806946452
Short name T474
Test name
Test status
Simulation time 13925218 ps
CPU time 0.64 seconds
Started Feb 25 01:27:48 PM PST 24
Finished Feb 25 01:27:48 PM PST 24
Peak memory 193528 kb
Host smart-8daed58d-d836-40fd-ae83-5cafddeaadf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806946452 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.1806946452
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3638951015
Short name T470
Test name
Test status
Simulation time 13615209 ps
CPU time 0.59 seconds
Started Feb 25 01:27:48 PM PST 24
Finished Feb 25 01:27:48 PM PST 24
Peak memory 182556 kb
Host smart-00a3abb2-090b-479b-90de-a04343641d35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638951015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3638951015
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3474055957
Short name T482
Test name
Test status
Simulation time 13447397 ps
CPU time 0.57 seconds
Started Feb 25 01:27:48 PM PST 24
Finished Feb 25 01:27:49 PM PST 24
Peak memory 182300 kb
Host smart-d77274ed-a5a7-48c1-a699-1aec1abcef3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474055957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3474055957
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2639009272
Short name T113
Test name
Test status
Simulation time 53957815 ps
CPU time 0.72 seconds
Started Feb 25 01:27:47 PM PST 24
Finished Feb 25 01:27:48 PM PST 24
Peak memory 191520 kb
Host smart-5fbcf80c-d9ca-484a-a615-52accdf32f09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639009272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2639009272
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2064438919
Short name T497
Test name
Test status
Simulation time 213792215 ps
CPU time 1.83 seconds
Started Feb 25 01:27:48 PM PST 24
Finished Feb 25 01:27:51 PM PST 24
Peak memory 197312 kb
Host smart-1d2463c6-491d-467f-9699-1784f65aab08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064438919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2064438919
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1547970329
Short name T129
Test name
Test status
Simulation time 247679557 ps
CPU time 1.4 seconds
Started Feb 25 01:27:48 PM PST 24
Finished Feb 25 01:27:50 PM PST 24
Peak memory 182948 kb
Host smart-94efa026-b062-401f-9d4d-5c0345e0cc45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547970329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.1547970329
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3911851561
Short name T558
Test name
Test status
Simulation time 32119229 ps
CPU time 0.67 seconds
Started Feb 25 01:27:50 PM PST 24
Finished Feb 25 01:27:51 PM PST 24
Peak memory 193984 kb
Host smart-4de424d4-43c7-4b3a-9f8a-d53eb7c10954
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911851561 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3911851561
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2793094066
Short name T512
Test name
Test status
Simulation time 47684568 ps
CPU time 0.57 seconds
Started Feb 25 01:27:48 PM PST 24
Finished Feb 25 01:27:49 PM PST 24
Peak memory 182556 kb
Host smart-83db407f-44d4-4afa-8140-a1d9a3691a64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793094066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2793094066
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2513321568
Short name T557
Test name
Test status
Simulation time 19828052 ps
CPU time 0.54 seconds
Started Feb 25 01:27:48 PM PST 24
Finished Feb 25 01:27:49 PM PST 24
Peak memory 181704 kb
Host smart-81df75f3-7493-40a4-9823-0450df52cc3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513321568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.2513321568
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.4201568967
Short name T112
Test name
Test status
Simulation time 123581347 ps
CPU time 0.73 seconds
Started Feb 25 01:27:48 PM PST 24
Finished Feb 25 01:27:48 PM PST 24
Peak memory 193052 kb
Host smart-813ab0fd-f9c3-47b6-a3ee-60d1c4c9137a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201568967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.4201568967
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1685623098
Short name T564
Test name
Test status
Simulation time 344007305 ps
CPU time 3 seconds
Started Feb 25 01:27:46 PM PST 24
Finished Feb 25 01:27:49 PM PST 24
Peak memory 197328 kb
Host smart-d99e4ef6-1d7b-405e-af67-b735d6c55dcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685623098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1685623098
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.881982818
Short name T555
Test name
Test status
Simulation time 200034014 ps
CPU time 1.12 seconds
Started Feb 25 01:27:49 PM PST 24
Finished Feb 25 01:27:51 PM PST 24
Peak memory 194532 kb
Host smart-c132576e-2045-4c47-acb0-83a74b42b0f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881982818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in
tg_err.881982818
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2877679324
Short name T471
Test name
Test status
Simulation time 104067103 ps
CPU time 0.84 seconds
Started Feb 25 01:27:48 PM PST 24
Finished Feb 25 01:27:50 PM PST 24
Peak memory 196280 kb
Host smart-af2932c3-b340-470b-b7e3-8b846f594f3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877679324 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.2877679324
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3777403009
Short name T98
Test name
Test status
Simulation time 11478860 ps
CPU time 0.57 seconds
Started Feb 25 01:27:51 PM PST 24
Finished Feb 25 01:27:51 PM PST 24
Peak memory 182360 kb
Host smart-db0d4bfa-9021-4983-b051-3c21c1c69222
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777403009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3777403009
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1886599648
Short name T521
Test name
Test status
Simulation time 15375073 ps
CPU time 0.56 seconds
Started Feb 25 01:27:50 PM PST 24
Finished Feb 25 01:27:51 PM PST 24
Peak memory 182344 kb
Host smart-b3fcf398-9090-48c4-a6eb-5afffce8aa50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886599648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1886599648
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3748803950
Short name T539
Test name
Test status
Simulation time 124910478 ps
CPU time 0.75 seconds
Started Feb 25 01:27:48 PM PST 24
Finished Feb 25 01:27:49 PM PST 24
Peak memory 191476 kb
Host smart-dd8d6185-e45a-4fcb-81a0-3d8ede227082
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748803950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.3748803950
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2911488864
Short name T477
Test name
Test status
Simulation time 96554126 ps
CPU time 1.32 seconds
Started Feb 25 01:27:49 PM PST 24
Finished Feb 25 01:27:50 PM PST 24
Peak memory 197248 kb
Host smart-934fa5d3-7269-4af1-bac3-aa2837e45624
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911488864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2911488864
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.195432157
Short name T484
Test name
Test status
Simulation time 70439799 ps
CPU time 1.12 seconds
Started Feb 25 01:27:49 PM PST 24
Finished Feb 25 01:27:51 PM PST 24
Peak memory 182984 kb
Host smart-b11c310c-68a1-4354-8b16-0e1fbfd2fae8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195432157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_in
tg_err.195432157
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1349600082
Short name T568
Test name
Test status
Simulation time 34297826 ps
CPU time 0.86 seconds
Started Feb 25 01:27:49 PM PST 24
Finished Feb 25 01:27:50 PM PST 24
Peak memory 196280 kb
Host smart-40aaf27d-ff0c-45df-979a-f0d1a98e3f7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349600082 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1349600082
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3311118765
Short name T560
Test name
Test status
Simulation time 14495026 ps
CPU time 0.55 seconds
Started Feb 25 01:27:51 PM PST 24
Finished Feb 25 01:27:51 PM PST 24
Peak memory 182008 kb
Host smart-4a469aaa-9666-40e1-b1e7-ab27d98b8c68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311118765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.3311118765
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.182202198
Short name T573
Test name
Test status
Simulation time 17470505 ps
CPU time 0.54 seconds
Started Feb 25 01:27:48 PM PST 24
Finished Feb 25 01:27:49 PM PST 24
Peak memory 181948 kb
Host smart-28abe746-012b-4399-94b7-8cc077b2c211
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182202198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.182202198
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.847205137
Short name T543
Test name
Test status
Simulation time 51408706 ps
CPU time 0.69 seconds
Started Feb 25 01:27:48 PM PST 24
Finished Feb 25 01:27:49 PM PST 24
Peak memory 191836 kb
Host smart-e116bc91-bfc5-4970-bce6-30be82d38e95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847205137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_ti
mer_same_csr_outstanding.847205137
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3975143264
Short name T556
Test name
Test status
Simulation time 505780884 ps
CPU time 2.9 seconds
Started Feb 25 01:27:48 PM PST 24
Finished Feb 25 01:27:51 PM PST 24
Peak memory 197276 kb
Host smart-9550048f-dbb7-42dd-86e7-d30b9af80ba7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975143264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3975143264
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.250267614
Short name T511
Test name
Test status
Simulation time 71866713 ps
CPU time 1.08 seconds
Started Feb 25 01:27:48 PM PST 24
Finished Feb 25 01:27:49 PM PST 24
Peak memory 194584 kb
Host smart-6c912d5d-1ac8-4405-b5b8-98fbf0b10160
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250267614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_in
tg_err.250267614
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2922542433
Short name T103
Test name
Test status
Simulation time 114846506 ps
CPU time 0.82 seconds
Started Feb 25 01:27:25 PM PST 24
Finished Feb 25 01:27:27 PM PST 24
Peak memory 182476 kb
Host smart-97f2371b-aa4d-4d14-916c-51c14ee4d3cc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922542433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.2922542433
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1289139060
Short name T92
Test name
Test status
Simulation time 119698375 ps
CPU time 2.4 seconds
Started Feb 25 01:27:18 PM PST 24
Finished Feb 25 01:27:21 PM PST 24
Peak memory 182760 kb
Host smart-b9ae12b8-6b1c-4e8a-a12f-f6925a6bc066
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289139060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1289139060
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2570080238
Short name T502
Test name
Test status
Simulation time 15581176 ps
CPU time 0.55 seconds
Started Feb 25 01:27:17 PM PST 24
Finished Feb 25 01:27:17 PM PST 24
Peak memory 181932 kb
Host smart-a80d36e0-f3ef-49cd-998a-ba017f1e0cce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570080238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2570080238
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3523279890
Short name T500
Test name
Test status
Simulation time 24683285 ps
CPU time 0.76 seconds
Started Feb 25 01:27:23 PM PST 24
Finished Feb 25 01:27:25 PM PST 24
Peak memory 195324 kb
Host smart-cefe245d-b496-49b6-96f0-46f3f03381e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523279890 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3523279890
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2384000061
Short name T99
Test name
Test status
Simulation time 15786370 ps
CPU time 0.57 seconds
Started Feb 25 01:27:18 PM PST 24
Finished Feb 25 01:27:19 PM PST 24
Peak memory 191792 kb
Host smart-4cceb124-1168-478e-94c8-1438b9e03e12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384000061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2384000061
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1602648180
Short name T553
Test name
Test status
Simulation time 19367869 ps
CPU time 0.53 seconds
Started Feb 25 01:27:05 PM PST 24
Finished Feb 25 01:27:06 PM PST 24
Peak memory 181708 kb
Host smart-01ad2293-2502-4352-bcc4-d1f6ca5985aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602648180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1602648180
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.4229849589
Short name T516
Test name
Test status
Simulation time 189818783 ps
CPU time 0.76 seconds
Started Feb 25 01:27:15 PM PST 24
Finished Feb 25 01:27:16 PM PST 24
Peak memory 193040 kb
Host smart-22a499fc-1be6-4180-92a4-1c366fc6990b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229849589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.4229849589
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2409265575
Short name T569
Test name
Test status
Simulation time 200834412 ps
CPU time 2.74 seconds
Started Feb 25 01:27:09 PM PST 24
Finished Feb 25 01:27:11 PM PST 24
Peak memory 197292 kb
Host smart-fdc8e768-1628-45db-a4f8-b4eb1ce9385e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409265575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2409265575
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3152037093
Short name T31
Test name
Test status
Simulation time 50495297 ps
CPU time 0.87 seconds
Started Feb 25 01:27:07 PM PST 24
Finished Feb 25 01:27:08 PM PST 24
Peak memory 182760 kb
Host smart-399d0679-8a63-42a1-9a50-f1b41c93d6bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152037093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.3152037093
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.4003916470
Short name T571
Test name
Test status
Simulation time 194568898 ps
CPU time 0.56 seconds
Started Feb 25 01:27:48 PM PST 24
Finished Feb 25 01:27:49 PM PST 24
Peak memory 181948 kb
Host smart-87e70496-24e6-4148-bd4c-c812c30ff82d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003916470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.4003916470
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3939634148
Short name T541
Test name
Test status
Simulation time 15177200 ps
CPU time 0.56 seconds
Started Feb 25 01:27:48 PM PST 24
Finished Feb 25 01:27:49 PM PST 24
Peak memory 182352 kb
Host smart-290a5cb6-18e6-49f8-af7d-dfe1e3e1d1f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939634148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3939634148
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2995712706
Short name T465
Test name
Test status
Simulation time 15774577 ps
CPU time 0.59 seconds
Started Feb 25 01:27:48 PM PST 24
Finished Feb 25 01:27:49 PM PST 24
Peak memory 182380 kb
Host smart-c1c1eb11-7b12-4617-b944-138601e4684b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995712706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2995712706
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3834023945
Short name T459
Test name
Test status
Simulation time 60061743 ps
CPU time 0.58 seconds
Started Feb 25 01:27:50 PM PST 24
Finished Feb 25 01:27:51 PM PST 24
Peak memory 182312 kb
Host smart-3ff69308-7f9a-4358-936a-c8006fe8488b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834023945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3834023945
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1112806602
Short name T508
Test name
Test status
Simulation time 32357586 ps
CPU time 0.58 seconds
Started Feb 25 01:27:51 PM PST 24
Finished Feb 25 01:27:51 PM PST 24
Peak memory 182356 kb
Host smart-669124a1-cbaa-4bd5-80f2-3acd6b6cc0ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112806602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1112806602
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1120170040
Short name T567
Test name
Test status
Simulation time 50795991 ps
CPU time 0.55 seconds
Started Feb 25 01:27:55 PM PST 24
Finished Feb 25 01:27:56 PM PST 24
Peak memory 182228 kb
Host smart-c306c2ec-e458-45de-8d78-cc566ee19176
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120170040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1120170040
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1585667262
Short name T469
Test name
Test status
Simulation time 41333646 ps
CPU time 0.57 seconds
Started Feb 25 01:27:51 PM PST 24
Finished Feb 25 01:27:51 PM PST 24
Peak memory 182348 kb
Host smart-12782dfb-32a6-40a1-bd75-c8dc89d2ebdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585667262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1585667262
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.755705422
Short name T468
Test name
Test status
Simulation time 86390843 ps
CPU time 0.55 seconds
Started Feb 25 01:27:48 PM PST 24
Finished Feb 25 01:27:49 PM PST 24
Peak memory 182296 kb
Host smart-d486c08e-2c3e-40c2-9688-fc5a0c6fc21c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755705422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.755705422
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1033947081
Short name T534
Test name
Test status
Simulation time 41100509 ps
CPU time 0.59 seconds
Started Feb 25 01:27:55 PM PST 24
Finished Feb 25 01:27:57 PM PST 24
Peak memory 182128 kb
Host smart-2d86d7fa-ee11-475a-b6c4-ce5171f9bc37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033947081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1033947081
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3880574343
Short name T478
Test name
Test status
Simulation time 97518486 ps
CPU time 0.53 seconds
Started Feb 25 01:27:55 PM PST 24
Finished Feb 25 01:27:57 PM PST 24
Peak memory 181696 kb
Host smart-ce221d3d-3c78-485f-813c-4637f2950f66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880574343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3880574343
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1519302035
Short name T108
Test name
Test status
Simulation time 53620016 ps
CPU time 0.72 seconds
Started Feb 25 01:27:15 PM PST 24
Finished Feb 25 01:27:16 PM PST 24
Peak memory 192256 kb
Host smart-105ebdfe-f136-4323-b969-2a0b3b02d978
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519302035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.1519302035
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2371465694
Short name T105
Test name
Test status
Simulation time 243162538 ps
CPU time 2.4 seconds
Started Feb 25 01:27:15 PM PST 24
Finished Feb 25 01:27:18 PM PST 24
Peak memory 193060 kb
Host smart-2d622d96-afaf-47e4-8826-37c335ba1e20
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371465694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2371465694
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.131830478
Short name T565
Test name
Test status
Simulation time 15343476 ps
CPU time 0.57 seconds
Started Feb 25 01:27:17 PM PST 24
Finished Feb 25 01:27:17 PM PST 24
Peak memory 182496 kb
Host smart-6a6d543f-44ab-42c2-8491-197454191a79
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131830478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_re
set.131830478
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.321674130
Short name T580
Test name
Test status
Simulation time 40261240 ps
CPU time 1.03 seconds
Started Feb 25 01:27:19 PM PST 24
Finished Feb 25 01:27:20 PM PST 24
Peak memory 196440 kb
Host smart-f6a91995-f399-46a5-ad3d-90970b12a132
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321674130 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.321674130
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.624726472
Short name T100
Test name
Test status
Simulation time 39976867 ps
CPU time 0.52 seconds
Started Feb 25 01:27:15 PM PST 24
Finished Feb 25 01:27:15 PM PST 24
Peak memory 182052 kb
Host smart-10b417e9-8a2a-4a06-bd6a-963fe0583d38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624726472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.624726472
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2888057623
Short name T458
Test name
Test status
Simulation time 14331489 ps
CPU time 0.55 seconds
Started Feb 25 01:27:16 PM PST 24
Finished Feb 25 01:27:16 PM PST 24
Peak memory 182288 kb
Host smart-ed75137c-8f27-40d6-a3e1-8c6a95cda789
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888057623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2888057623
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3767841351
Short name T114
Test name
Test status
Simulation time 53360768 ps
CPU time 0.61 seconds
Started Feb 25 01:27:17 PM PST 24
Finished Feb 25 01:27:19 PM PST 24
Peak memory 191156 kb
Host smart-4f842318-f2cd-4527-9a5b-2c2512768300
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767841351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3767841351
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2114476264
Short name T530
Test name
Test status
Simulation time 237487886 ps
CPU time 1.74 seconds
Started Feb 25 01:27:19 PM PST 24
Finished Feb 25 01:27:21 PM PST 24
Peak memory 197312 kb
Host smart-98e2d257-0d49-4be6-8c96-cdd6a311bbf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114476264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2114476264
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3960189131
Short name T487
Test name
Test status
Simulation time 102012799 ps
CPU time 1.11 seconds
Started Feb 25 01:27:16 PM PST 24
Finished Feb 25 01:27:18 PM PST 24
Peak memory 194700 kb
Host smart-4cd8b9c6-3ae6-4e12-9be6-986aff0ef097
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960189131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3960189131
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2526680134
Short name T464
Test name
Test status
Simulation time 33310289 ps
CPU time 0.54 seconds
Started Feb 25 01:27:49 PM PST 24
Finished Feb 25 01:27:50 PM PST 24
Peak memory 182264 kb
Host smart-df5512b0-3763-4ab8-a064-abcccb38fe41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526680134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2526680134
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3063034818
Short name T545
Test name
Test status
Simulation time 86081630 ps
CPU time 0.58 seconds
Started Feb 25 01:27:55 PM PST 24
Finished Feb 25 01:27:57 PM PST 24
Peak memory 182280 kb
Host smart-0b0f3279-f394-40d0-8477-7d3e5b63c6e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063034818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3063034818
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1260818839
Short name T561
Test name
Test status
Simulation time 26866381 ps
CPU time 0.52 seconds
Started Feb 25 01:27:48 PM PST 24
Finished Feb 25 01:27:49 PM PST 24
Peak memory 181744 kb
Host smart-67b58989-8a2c-477b-af5e-70e175cfab7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260818839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1260818839
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2060418
Short name T527
Test name
Test status
Simulation time 50431987 ps
CPU time 0.56 seconds
Started Feb 25 01:27:48 PM PST 24
Finished Feb 25 01:27:49 PM PST 24
Peak memory 182324 kb
Host smart-74442c13-5649-428d-ac73-3f5e97dc4695
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.2060418
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.4030048216
Short name T570
Test name
Test status
Simulation time 32283537 ps
CPU time 0.55 seconds
Started Feb 25 01:27:53 PM PST 24
Finished Feb 25 01:27:54 PM PST 24
Peak memory 181624 kb
Host smart-6a141912-985f-48c0-a9c2-df50ab9e4b3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030048216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.4030048216
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.871434892
Short name T499
Test name
Test status
Simulation time 13201620 ps
CPU time 0.55 seconds
Started Feb 25 01:27:49 PM PST 24
Finished Feb 25 01:27:50 PM PST 24
Peak memory 182248 kb
Host smart-00b6f557-0911-4298-b4bb-87d3ac74fcf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871434892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.871434892
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.4086743360
Short name T531
Test name
Test status
Simulation time 13743491 ps
CPU time 0.62 seconds
Started Feb 25 01:27:53 PM PST 24
Finished Feb 25 01:27:54 PM PST 24
Peak memory 182184 kb
Host smart-f3ade189-f0bd-4494-8f17-2767006d3a81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086743360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.4086743360
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1973561886
Short name T503
Test name
Test status
Simulation time 16003439 ps
CPU time 0.55 seconds
Started Feb 25 01:27:53 PM PST 24
Finished Feb 25 01:27:54 PM PST 24
Peak memory 182304 kb
Host smart-d56e016e-886a-4407-9ccb-861f9ebcb040
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973561886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1973561886
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1065525537
Short name T483
Test name
Test status
Simulation time 152458681 ps
CPU time 0.56 seconds
Started Feb 25 01:27:55 PM PST 24
Finished Feb 25 01:27:57 PM PST 24
Peak memory 182288 kb
Host smart-5c89461f-e27d-4fbd-ad44-3cef692a7740
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065525537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1065525537
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3540553796
Short name T562
Test name
Test status
Simulation time 14979355 ps
CPU time 0.56 seconds
Started Feb 25 01:27:51 PM PST 24
Finished Feb 25 01:27:52 PM PST 24
Peak memory 182328 kb
Host smart-4ac9e42f-3e40-4874-a90e-cd6a797b9bb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540553796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3540553796
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.506335973
Short name T106
Test name
Test status
Simulation time 62740263 ps
CPU time 0.81 seconds
Started Feb 25 01:27:31 PM PST 24
Finished Feb 25 01:27:32 PM PST 24
Peak memory 182564 kb
Host smart-3662c669-6b08-4210-80b7-217a5469b93a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506335973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alias
ing.506335973
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3151573815
Short name T94
Test name
Test status
Simulation time 89359793 ps
CPU time 3.18 seconds
Started Feb 25 01:27:20 PM PST 24
Finished Feb 25 01:27:23 PM PST 24
Peak memory 190840 kb
Host smart-b4c8b246-b571-4387-8a08-90a6af202622
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151573815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3151573815
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2611454466
Short name T107
Test name
Test status
Simulation time 30474656 ps
CPU time 0.56 seconds
Started Feb 25 01:27:15 PM PST 24
Finished Feb 25 01:27:16 PM PST 24
Peak memory 182516 kb
Host smart-1c4d7696-a6f5-4d3d-8e2d-4afd2c271215
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611454466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2611454466
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1358804757
Short name T510
Test name
Test status
Simulation time 24100491 ps
CPU time 0.8 seconds
Started Feb 25 01:27:36 PM PST 24
Finished Feb 25 01:27:37 PM PST 24
Peak memory 195128 kb
Host smart-5be970d4-bbd1-4ada-8c16-88a82c773fce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358804757 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1358804757
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.891870210
Short name T102
Test name
Test status
Simulation time 13639326 ps
CPU time 0.58 seconds
Started Feb 25 01:27:18 PM PST 24
Finished Feb 25 01:27:19 PM PST 24
Peak memory 182576 kb
Host smart-ee842282-0e32-438e-a12f-6e77f4aad198
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891870210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.891870210
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.970792951
Short name T517
Test name
Test status
Simulation time 20525290 ps
CPU time 0.58 seconds
Started Feb 25 01:27:19 PM PST 24
Finished Feb 25 01:27:20 PM PST 24
Peak memory 182200 kb
Host smart-6c21234e-a802-4037-9053-a013870d5982
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970792951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.970792951
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1777130824
Short name T495
Test name
Test status
Simulation time 19166890 ps
CPU time 0.7 seconds
Started Feb 25 01:27:40 PM PST 24
Finished Feb 25 01:27:41 PM PST 24
Peak memory 191420 kb
Host smart-7e02e69f-db59-4915-b3c3-1fc6f32a92f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777130824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.1777130824
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1893964953
Short name T576
Test name
Test status
Simulation time 137793421 ps
CPU time 2.49 seconds
Started Feb 25 01:27:20 PM PST 24
Finished Feb 25 01:27:22 PM PST 24
Peak memory 197196 kb
Host smart-968e5fe7-4ec8-4e70-8965-605ce6ac839c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893964953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1893964953
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2791578912
Short name T551
Test name
Test status
Simulation time 325801551 ps
CPU time 1.12 seconds
Started Feb 25 01:27:20 PM PST 24
Finished Feb 25 01:27:21 PM PST 24
Peak memory 194748 kb
Host smart-3651e62f-c043-4450-997a-3a61d9544ac9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791578912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2791578912
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.811936448
Short name T460
Test name
Test status
Simulation time 18948658 ps
CPU time 0.59 seconds
Started Feb 25 01:27:54 PM PST 24
Finished Feb 25 01:27:55 PM PST 24
Peak memory 182220 kb
Host smart-5c98b0d5-7317-4080-8d28-ef6272a3cd74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811936448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.811936448
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2710104599
Short name T466
Test name
Test status
Simulation time 40625309 ps
CPU time 0.62 seconds
Started Feb 25 01:27:53 PM PST 24
Finished Feb 25 01:27:54 PM PST 24
Peak memory 182224 kb
Host smart-0844b3b2-e94a-40e4-aaa2-266a4e078982
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710104599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2710104599
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1212161241
Short name T535
Test name
Test status
Simulation time 68158172 ps
CPU time 0.58 seconds
Started Feb 25 01:27:53 PM PST 24
Finished Feb 25 01:27:54 PM PST 24
Peak memory 182348 kb
Host smart-d707fcea-8d58-4228-908d-81d6f844abf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212161241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1212161241
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3317780029
Short name T505
Test name
Test status
Simulation time 47732471 ps
CPU time 0.54 seconds
Started Feb 25 01:27:52 PM PST 24
Finished Feb 25 01:27:53 PM PST 24
Peak memory 181692 kb
Host smart-f9e20935-0add-4c12-98a7-7f433ee3cd18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317780029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3317780029
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2683958539
Short name T540
Test name
Test status
Simulation time 36071829 ps
CPU time 0.55 seconds
Started Feb 25 01:27:53 PM PST 24
Finished Feb 25 01:27:54 PM PST 24
Peak memory 182304 kb
Host smart-cbd8db71-5f99-4ef1-b19d-6e76dc234d1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683958539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2683958539
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1301915341
Short name T473
Test name
Test status
Simulation time 11221839 ps
CPU time 0.54 seconds
Started Feb 25 01:27:52 PM PST 24
Finished Feb 25 01:27:53 PM PST 24
Peak memory 181908 kb
Host smart-5c6197d4-97bc-45f6-857b-ac0ae8222a6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301915341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1301915341
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3834821921
Short name T546
Test name
Test status
Simulation time 13359661 ps
CPU time 0.53 seconds
Started Feb 25 01:27:50 PM PST 24
Finished Feb 25 01:27:51 PM PST 24
Peak memory 181736 kb
Host smart-1540ef17-25b3-41da-bbcd-159020754c4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834821921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3834821921
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.4082046198
Short name T581
Test name
Test status
Simulation time 67542390 ps
CPU time 0.53 seconds
Started Feb 25 01:27:52 PM PST 24
Finished Feb 25 01:27:53 PM PST 24
Peak memory 182304 kb
Host smart-974716fb-4b20-42df-a2f1-ed362c35773f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082046198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.4082046198
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.938223491
Short name T536
Test name
Test status
Simulation time 94155252 ps
CPU time 0.58 seconds
Started Feb 25 01:27:54 PM PST 24
Finished Feb 25 01:27:56 PM PST 24
Peak memory 182252 kb
Host smart-fcf3d06f-d7d5-4413-9a4d-3ca78537ea28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938223491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.938223491
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2105679812
Short name T463
Test name
Test status
Simulation time 39497523 ps
CPU time 0.54 seconds
Started Feb 25 01:27:54 PM PST 24
Finished Feb 25 01:27:55 PM PST 24
Peak memory 181688 kb
Host smart-2e7b7442-2151-48b2-b2c3-7866fb26ee43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105679812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2105679812
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1359501734
Short name T55
Test name
Test status
Simulation time 31395342 ps
CPU time 0.81 seconds
Started Feb 25 01:27:35 PM PST 24
Finished Feb 25 01:27:36 PM PST 24
Peak memory 194932 kb
Host smart-0fede51e-55ab-4cf9-b0ac-0d82044f0121
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359501734 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1359501734
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.453531425
Short name T496
Test name
Test status
Simulation time 18481206 ps
CPU time 0.51 seconds
Started Feb 25 01:27:35 PM PST 24
Finished Feb 25 01:27:36 PM PST 24
Peak memory 182152 kb
Host smart-3a76f91d-631e-41bd-a9f9-3170d6010508
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453531425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.453531425
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.841859138
Short name T489
Test name
Test status
Simulation time 27936204 ps
CPU time 0.54 seconds
Started Feb 25 01:27:31 PM PST 24
Finished Feb 25 01:27:32 PM PST 24
Peak memory 182316 kb
Host smart-38466855-5ecb-43ce-aeb1-11d359bbdfd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841859138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.841859138
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1289224767
Short name T97
Test name
Test status
Simulation time 15511012 ps
CPU time 0.63 seconds
Started Feb 25 01:27:35 PM PST 24
Finished Feb 25 01:27:36 PM PST 24
Peak memory 191744 kb
Host smart-553d1b80-171f-432b-8068-afc019386466
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289224767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1289224767
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1600955247
Short name T476
Test name
Test status
Simulation time 80536980 ps
CPU time 0.84 seconds
Started Feb 25 01:27:34 PM PST 24
Finished Feb 25 01:27:35 PM PST 24
Peak memory 194864 kb
Host smart-750b556b-e082-4a4d-af0f-006bf81709d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600955247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1600955247
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2272217541
Short name T128
Test name
Test status
Simulation time 80914064 ps
CPU time 1.11 seconds
Started Feb 25 01:27:35 PM PST 24
Finished Feb 25 01:27:37 PM PST 24
Peak memory 194568 kb
Host smart-19d46dc8-eb29-4409-86d8-f613a94eda2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272217541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.2272217541
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1867380824
Short name T467
Test name
Test status
Simulation time 17708352 ps
CPU time 0.64 seconds
Started Feb 25 01:27:35 PM PST 24
Finished Feb 25 01:27:36 PM PST 24
Peak memory 193736 kb
Host smart-f4263fb7-2f36-437e-ab30-f9c280536432
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867380824 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1867380824
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.2326657418
Short name T523
Test name
Test status
Simulation time 43039132 ps
CPU time 0.57 seconds
Started Feb 25 01:27:30 PM PST 24
Finished Feb 25 01:27:31 PM PST 24
Peak memory 182552 kb
Host smart-e36eb36b-c4c5-4a69-b712-68214f037376
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326657418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.2326657418
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1233443102
Short name T480
Test name
Test status
Simulation time 13522356 ps
CPU time 0.57 seconds
Started Feb 25 01:27:30 PM PST 24
Finished Feb 25 01:27:31 PM PST 24
Peak memory 182324 kb
Host smart-d6effc01-f1d9-4fa3-9872-184687d73dfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233443102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1233443102
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.631708590
Short name T111
Test name
Test status
Simulation time 712218357 ps
CPU time 0.81 seconds
Started Feb 25 01:27:45 PM PST 24
Finished Feb 25 01:27:46 PM PST 24
Peak memory 193044 kb
Host smart-c486a9ce-ce67-432f-be7d-ce6100615bbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631708590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.631708590
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3726414273
Short name T518
Test name
Test status
Simulation time 532925461 ps
CPU time 2.48 seconds
Started Feb 25 01:27:30 PM PST 24
Finished Feb 25 01:27:33 PM PST 24
Peak memory 197304 kb
Host smart-561e89e4-00a4-4206-8e2b-0826ca8af22d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726414273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3726414273
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.4237683483
Short name T32
Test name
Test status
Simulation time 124838856 ps
CPU time 1.43 seconds
Started Feb 25 01:27:30 PM PST 24
Finished Feb 25 01:27:32 PM PST 24
Peak memory 182868 kb
Host smart-6d539283-421f-43dd-99ec-74309cd5aa5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237683483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.4237683483
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.329798461
Short name T33
Test name
Test status
Simulation time 152215248 ps
CPU time 0.87 seconds
Started Feb 25 01:27:32 PM PST 24
Finished Feb 25 01:27:33 PM PST 24
Peak memory 197036 kb
Host smart-b989af31-90fd-47f9-be99-218b833edd96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329798461 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.329798461
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1279793034
Short name T96
Test name
Test status
Simulation time 47671977 ps
CPU time 0.58 seconds
Started Feb 25 01:27:32 PM PST 24
Finished Feb 25 01:27:33 PM PST 24
Peak memory 182552 kb
Host smart-8b935766-1a76-421a-984f-81dc29031fbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279793034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1279793034
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3754085383
Short name T479
Test name
Test status
Simulation time 11666623 ps
CPU time 0.57 seconds
Started Feb 25 01:27:41 PM PST 24
Finished Feb 25 01:27:42 PM PST 24
Peak memory 182308 kb
Host smart-4fd95bb5-539c-4a04-9a24-15d946d06962
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754085383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3754085383
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.299428244
Short name T524
Test name
Test status
Simulation time 95609022 ps
CPU time 0.82 seconds
Started Feb 25 01:27:35 PM PST 24
Finished Feb 25 01:27:36 PM PST 24
Peak memory 192828 kb
Host smart-d9878ab3-96b1-4e06-bc81-f14382affd01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299428244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_tim
er_same_csr_outstanding.299428244
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.584603086
Short name T481
Test name
Test status
Simulation time 69732586 ps
CPU time 1.03 seconds
Started Feb 25 01:27:36 PM PST 24
Finished Feb 25 01:27:38 PM PST 24
Peak memory 195400 kb
Host smart-68d6e29e-8745-4efb-9701-a3697b000488
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584603086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.584603086
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2632775668
Short name T126
Test name
Test status
Simulation time 98123548 ps
CPU time 1.32 seconds
Started Feb 25 01:27:34 PM PST 24
Finished Feb 25 01:27:36 PM PST 24
Peak memory 183096 kb
Host smart-966f4523-98b5-48b5-9c7f-73cff65096a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632775668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.2632775668
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.863889655
Short name T578
Test name
Test status
Simulation time 364126479 ps
CPU time 0.78 seconds
Started Feb 25 01:27:32 PM PST 24
Finished Feb 25 01:27:33 PM PST 24
Peak memory 195044 kb
Host smart-ef6f05fb-0a68-4b45-a316-8e9e0faad221
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863889655 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.863889655
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3088690283
Short name T528
Test name
Test status
Simulation time 51366603 ps
CPU time 0.59 seconds
Started Feb 25 01:27:38 PM PST 24
Finished Feb 25 01:27:39 PM PST 24
Peak memory 182540 kb
Host smart-b3bf9b89-67b0-4b89-9faa-e76daafa481b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088690283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3088690283
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3957183882
Short name T506
Test name
Test status
Simulation time 11359591 ps
CPU time 0.51 seconds
Started Feb 25 01:27:39 PM PST 24
Finished Feb 25 01:27:40 PM PST 24
Peak memory 181752 kb
Host smart-624d32ab-1a09-4283-85c8-0084e1a6749b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957183882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3957183882
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.89957727
Short name T529
Test name
Test status
Simulation time 109534530 ps
CPU time 0.66 seconds
Started Feb 25 01:27:33 PM PST 24
Finished Feb 25 01:27:33 PM PST 24
Peak memory 192032 kb
Host smart-bf67d3ea-6510-4c3e-ab75-a6428ed66b48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89957727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_time
r_same_csr_outstanding.89957727
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3401512438
Short name T574
Test name
Test status
Simulation time 147931102 ps
CPU time 3.02 seconds
Started Feb 25 01:27:36 PM PST 24
Finished Feb 25 01:27:39 PM PST 24
Peak memory 197332 kb
Host smart-366f61e5-144f-437d-818e-297caa5aee2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401512438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3401512438
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.4261389378
Short name T526
Test name
Test status
Simulation time 212322480 ps
CPU time 1.36 seconds
Started Feb 25 01:27:34 PM PST 24
Finished Feb 25 01:27:36 PM PST 24
Peak memory 194876 kb
Host smart-39ba9eee-f837-414c-83c8-6d3de3273ad3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261389378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.4261389378
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.4084087587
Short name T494
Test name
Test status
Simulation time 77237790 ps
CPU time 0.74 seconds
Started Feb 25 01:27:43 PM PST 24
Finished Feb 25 01:27:44 PM PST 24
Peak memory 195200 kb
Host smart-fd35e1be-5b3f-4ea3-b366-5de68d1c0af7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084087587 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.4084087587
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1041780868
Short name T109
Test name
Test status
Simulation time 34761428 ps
CPU time 0.56 seconds
Started Feb 25 01:27:43 PM PST 24
Finished Feb 25 01:27:43 PM PST 24
Peak memory 182572 kb
Host smart-b6d7db76-b381-4332-8378-3701cb6e89f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041780868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1041780868
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1254821636
Short name T462
Test name
Test status
Simulation time 24623806 ps
CPU time 0.54 seconds
Started Feb 25 01:27:39 PM PST 24
Finished Feb 25 01:27:40 PM PST 24
Peak memory 182352 kb
Host smart-cd2bcd2f-acea-4353-b551-691cd0e790c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254821636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1254821636
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.221165659
Short name T533
Test name
Test status
Simulation time 62051816 ps
CPU time 0.62 seconds
Started Feb 25 01:27:43 PM PST 24
Finished Feb 25 01:27:44 PM PST 24
Peak memory 191788 kb
Host smart-b0092bdf-7b28-4206-8749-8e5bd83a5e28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221165659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_tim
er_same_csr_outstanding.221165659
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.145742737
Short name T513
Test name
Test status
Simulation time 23161977 ps
CPU time 1 seconds
Started Feb 25 01:27:34 PM PST 24
Finished Feb 25 01:27:35 PM PST 24
Peak memory 195372 kb
Host smart-a49e62cb-bbe3-44a0-9ed0-45428fc50952
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145742737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.145742737
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1582543231
Short name T501
Test name
Test status
Simulation time 152602051 ps
CPU time 0.83 seconds
Started Feb 25 01:27:42 PM PST 24
Finished Feb 25 01:27:43 PM PST 24
Peak memory 193048 kb
Host smart-e467a858-2abf-48b3-b8f4-a028630590de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582543231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1582543231
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1324727225
Short name T310
Test name
Test status
Simulation time 1659415901954 ps
CPU time 470.17 seconds
Started Feb 25 01:47:04 PM PST 24
Finished Feb 25 01:54:54 PM PST 24
Peak memory 182688 kb
Host smart-6a2e59bf-b1ae-40fd-a8ab-9e73ffa41b41
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324727225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1324727225
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.627297745
Short name T379
Test name
Test status
Simulation time 122914621346 ps
CPU time 206.43 seconds
Started Feb 25 01:46:58 PM PST 24
Finished Feb 25 01:50:25 PM PST 24
Peak memory 182752 kb
Host smart-9b872cb6-44fe-4851-abf0-38657f086452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627297745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.627297745
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.1210432076
Short name T425
Test name
Test status
Simulation time 32998080244 ps
CPU time 66.93 seconds
Started Feb 25 01:47:00 PM PST 24
Finished Feb 25 01:48:07 PM PST 24
Peak memory 190860 kb
Host smart-9cab5329-8117-4083-8ffe-072745f3558e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210432076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1210432076
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3283937218
Short name T75
Test name
Test status
Simulation time 109159650651 ps
CPU time 172.61 seconds
Started Feb 25 01:47:06 PM PST 24
Finished Feb 25 01:49:59 PM PST 24
Peak memory 190960 kb
Host smart-1c80788a-78af-4ada-8b3e-b651cacc76ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283937218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3283937218
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2027466356
Short name T382
Test name
Test status
Simulation time 173251134727 ps
CPU time 106.72 seconds
Started Feb 25 01:47:03 PM PST 24
Finished Feb 25 01:48:50 PM PST 24
Peak memory 182732 kb
Host smart-4469ba38-b8df-45a5-9e1b-10e47e384efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027466356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2027466356
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.3688636309
Short name T135
Test name
Test status
Simulation time 309440834022 ps
CPU time 143.02 seconds
Started Feb 25 01:47:02 PM PST 24
Finished Feb 25 01:49:25 PM PST 24
Peak memory 190952 kb
Host smart-cb882277-f809-4022-ba95-025a94cc612f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688636309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3688636309
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2269760980
Short name T260
Test name
Test status
Simulation time 31041546863 ps
CPU time 61.31 seconds
Started Feb 25 01:47:01 PM PST 24
Finished Feb 25 01:48:03 PM PST 24
Peak memory 190860 kb
Host smart-19001d83-7388-4935-9e52-6ed791c80757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269760980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2269760980
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.25842841
Short name T18
Test name
Test status
Simulation time 375189698 ps
CPU time 0.86 seconds
Started Feb 25 01:46:58 PM PST 24
Finished Feb 25 01:46:59 PM PST 24
Peak memory 212944 kb
Host smart-e389c846-6971-485e-89dc-db50cfa3c281
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25842841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.25842841
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.149038191
Short name T41
Test name
Test status
Simulation time 650395995985 ps
CPU time 561.26 seconds
Started Feb 25 01:47:05 PM PST 24
Finished Feb 25 01:56:28 PM PST 24
Peak memory 205700 kb
Host smart-2ce58da3-ca00-4ae5-9866-32c56fda95af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149038191 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.149038191
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.2535888848
Short name T416
Test name
Test status
Simulation time 289510262650 ps
CPU time 166.97 seconds
Started Feb 25 01:47:16 PM PST 24
Finished Feb 25 01:50:03 PM PST 24
Peak memory 182692 kb
Host smart-dc7bd159-3f57-4a03-a4d6-4e5e319e2e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535888848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2535888848
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.2380318420
Short name T141
Test name
Test status
Simulation time 51775068985 ps
CPU time 423.87 seconds
Started Feb 25 01:47:12 PM PST 24
Finished Feb 25 01:54:16 PM PST 24
Peak memory 190908 kb
Host smart-90ff821f-cdd6-4023-b28b-9262184518fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380318420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2380318420
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.3603486976
Short name T434
Test name
Test status
Simulation time 368405228722 ps
CPU time 304.77 seconds
Started Feb 25 01:47:19 PM PST 24
Finished Feb 25 01:52:25 PM PST 24
Peak memory 191984 kb
Host smart-bd9ed231-49e0-4a4d-84f0-caf410b82453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603486976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3603486976
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3014627226
Short name T257
Test name
Test status
Simulation time 24559415979 ps
CPU time 35.27 seconds
Started Feb 25 01:47:09 PM PST 24
Finished Feb 25 01:47:44 PM PST 24
Peak memory 182516 kb
Host smart-c2132014-5de5-4dde-aaee-1ed0db5c134b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014627226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3014627226
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/102.rv_timer_random.982964126
Short name T89
Test name
Test status
Simulation time 160436511447 ps
CPU time 138.57 seconds
Started Feb 25 01:48:15 PM PST 24
Finished Feb 25 01:50:34 PM PST 24
Peak memory 182748 kb
Host smart-3a17915c-e604-4c8b-ba91-4e8a0b253721
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982964126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.982964126
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.1732508839
Short name T130
Test name
Test status
Simulation time 12834502341 ps
CPU time 22.17 seconds
Started Feb 25 01:48:14 PM PST 24
Finished Feb 25 01:48:37 PM PST 24
Peak memory 182764 kb
Host smart-e940321e-0a7a-42fe-b548-1e1ad6ac860a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732508839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1732508839
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.87979058
Short name T409
Test name
Test status
Simulation time 41769415496 ps
CPU time 61.68 seconds
Started Feb 25 01:48:14 PM PST 24
Finished Feb 25 01:49:16 PM PST 24
Peak memory 182748 kb
Host smart-cb2695c3-ac54-4f5d-b1c7-565bb9cb2032
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87979058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.87979058
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2907815508
Short name T298
Test name
Test status
Simulation time 170263868175 ps
CPU time 1389.96 seconds
Started Feb 25 01:48:13 PM PST 24
Finished Feb 25 02:11:24 PM PST 24
Peak memory 190960 kb
Host smart-2b55657e-1db0-4453-8f99-04b3febbbbd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907815508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2907815508
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.721770799
Short name T350
Test name
Test status
Simulation time 89803363204 ps
CPU time 702.01 seconds
Started Feb 25 01:48:15 PM PST 24
Finished Feb 25 01:59:57 PM PST 24
Peak memory 190960 kb
Host smart-aca89a7e-db64-4b4d-9e27-00fc37555c01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721770799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.721770799
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.564156817
Short name T185
Test name
Test status
Simulation time 75278138569 ps
CPU time 256.77 seconds
Started Feb 25 01:48:14 PM PST 24
Finished Feb 25 01:52:31 PM PST 24
Peak memory 193112 kb
Host smart-0649d334-9d5b-4f44-90a0-28bb47e4cf54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564156817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.564156817
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.1978399830
Short name T357
Test name
Test status
Simulation time 80314543768 ps
CPU time 145.92 seconds
Started Feb 25 01:47:17 PM PST 24
Finished Feb 25 01:49:43 PM PST 24
Peak memory 182716 kb
Host smart-94eb3360-7cab-49da-ba5d-00f2932624e1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978399830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.1978399830
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.1311645280
Short name T413
Test name
Test status
Simulation time 397523751502 ps
CPU time 137.26 seconds
Started Feb 25 01:47:24 PM PST 24
Finished Feb 25 01:49:44 PM PST 24
Peak memory 182400 kb
Host smart-e2f53cf9-994e-4ae4-95ba-2d0b560f48dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311645280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1311645280
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.3838256526
Short name T403
Test name
Test status
Simulation time 688772166 ps
CPU time 1.68 seconds
Started Feb 25 01:47:14 PM PST 24
Finished Feb 25 01:47:16 PM PST 24
Peak memory 182320 kb
Host smart-3dae3173-20d2-4294-b60c-92a3d7dd9596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838256526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.3838256526
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.4274111470
Short name T66
Test name
Test status
Simulation time 581077312919 ps
CPU time 215.69 seconds
Started Feb 25 01:47:16 PM PST 24
Finished Feb 25 01:50:52 PM PST 24
Peak memory 191000 kb
Host smart-94775e61-e50b-4b00-8bda-dfd6b74e7f0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274111470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.4274111470
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/110.rv_timer_random.17095179
Short name T232
Test name
Test status
Simulation time 623671499811 ps
CPU time 243.04 seconds
Started Feb 25 01:48:21 PM PST 24
Finished Feb 25 01:52:24 PM PST 24
Peak memory 190908 kb
Host smart-52fc55ba-6e87-4f72-9a06-9eac9928036c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17095179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.17095179
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.2593936270
Short name T346
Test name
Test status
Simulation time 220783560788 ps
CPU time 126.82 seconds
Started Feb 25 01:48:14 PM PST 24
Finished Feb 25 01:50:21 PM PST 24
Peak memory 190948 kb
Host smart-9d38e95f-7596-4e31-97d7-95b93e2eda7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593936270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2593936270
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2352624662
Short name T1
Test name
Test status
Simulation time 119985333978 ps
CPU time 612.71 seconds
Started Feb 25 01:48:14 PM PST 24
Finished Feb 25 01:58:27 PM PST 24
Peak memory 182764 kb
Host smart-07f8dbc7-821d-44b9-8e32-b217e7794bf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352624662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2352624662
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.1099680757
Short name T321
Test name
Test status
Simulation time 64122522409 ps
CPU time 124.28 seconds
Started Feb 25 01:48:18 PM PST 24
Finished Feb 25 01:50:23 PM PST 24
Peak memory 182724 kb
Host smart-66bd9a4b-92c0-4802-a3f0-966def22740b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099680757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1099680757
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.1340922930
Short name T186
Test name
Test status
Simulation time 88204435198 ps
CPU time 427.5 seconds
Started Feb 25 01:48:23 PM PST 24
Finished Feb 25 01:55:31 PM PST 24
Peak memory 190972 kb
Host smart-8295cc45-bfa0-499b-8345-d2e2ece4d71a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340922930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1340922930
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3886554477
Short name T162
Test name
Test status
Simulation time 441480710125 ps
CPU time 256.9 seconds
Started Feb 25 01:47:10 PM PST 24
Finished Feb 25 01:51:27 PM PST 24
Peak memory 182732 kb
Host smart-fc44144e-6873-44b9-a4ee-15626f01a8bd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886554477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3886554477
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.2564479654
Short name T375
Test name
Test status
Simulation time 324135955978 ps
CPU time 148.81 seconds
Started Feb 25 01:47:09 PM PST 24
Finished Feb 25 01:49:38 PM PST 24
Peak memory 182760 kb
Host smart-cb233e12-a08b-4c2c-b54d-4c1f09ea24f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564479654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.2564479654
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.4062446938
Short name T426
Test name
Test status
Simulation time 77242871756 ps
CPU time 112.52 seconds
Started Feb 25 01:47:15 PM PST 24
Finished Feb 25 01:49:08 PM PST 24
Peak memory 193112 kb
Host smart-a8fbee33-c5f4-4bbc-afdf-06662693ada1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062446938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.4062446938
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2810619576
Short name T311
Test name
Test status
Simulation time 353981803075 ps
CPU time 138.78 seconds
Started Feb 25 01:47:16 PM PST 24
Finished Feb 25 01:49:35 PM PST 24
Peak memory 193168 kb
Host smart-0ca09d3c-61b3-4847-8ed1-d4c202706c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810619576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2810619576
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.317882701
Short name T145
Test name
Test status
Simulation time 312280330039 ps
CPU time 3237.52 seconds
Started Feb 25 01:47:07 PM PST 24
Finished Feb 25 02:41:05 PM PST 24
Peak memory 194452 kb
Host smart-fb329bd5-b56f-424f-b050-5e71d901b839
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317882701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.
317882701
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/121.rv_timer_random.1955588509
Short name T356
Test name
Test status
Simulation time 674942246893 ps
CPU time 879.23 seconds
Started Feb 25 01:48:25 PM PST 24
Finished Feb 25 02:03:05 PM PST 24
Peak memory 190880 kb
Host smart-b49d04d9-a3cd-4647-9422-936b1a2604e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955588509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1955588509
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.226695346
Short name T317
Test name
Test status
Simulation time 348350334726 ps
CPU time 1005.07 seconds
Started Feb 25 01:48:26 PM PST 24
Finished Feb 25 02:05:12 PM PST 24
Peak memory 190948 kb
Host smart-1c73c30e-e713-44c5-bb62-7590a328aa63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226695346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.226695346
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3763729600
Short name T226
Test name
Test status
Simulation time 117111277173 ps
CPU time 129.21 seconds
Started Feb 25 01:48:23 PM PST 24
Finished Feb 25 01:50:32 PM PST 24
Peak memory 190980 kb
Host smart-bf6dabf4-2050-448a-b6c5-20101206e9a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763729600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3763729600
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2603159183
Short name T28
Test name
Test status
Simulation time 683840582163 ps
CPU time 291.07 seconds
Started Feb 25 01:48:23 PM PST 24
Finished Feb 25 01:53:15 PM PST 24
Peak memory 190912 kb
Host smart-b706a2fb-f9f0-4720-95c2-35876495ed46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603159183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2603159183
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1636575570
Short name T255
Test name
Test status
Simulation time 118508378478 ps
CPU time 493.17 seconds
Started Feb 25 01:48:32 PM PST 24
Finished Feb 25 01:56:46 PM PST 24
Peak memory 194644 kb
Host smart-60eb85cd-6afe-4d36-b650-4d63a6dd091f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636575570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1636575570
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.3018940399
Short name T83
Test name
Test status
Simulation time 282456082227 ps
CPU time 141.14 seconds
Started Feb 25 01:48:34 PM PST 24
Finished Feb 25 01:50:55 PM PST 24
Peak memory 190924 kb
Host smart-795c8ddb-1210-483b-9ecd-d3ea94b3ed25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018940399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3018940399
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2953571980
Short name T404
Test name
Test status
Simulation time 529580258250 ps
CPU time 274.75 seconds
Started Feb 25 01:47:09 PM PST 24
Finished Feb 25 01:51:45 PM PST 24
Peak memory 182732 kb
Host smart-c382be54-e488-4df9-82e7-75a1e86116d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953571980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2953571980
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.663898463
Short name T65
Test name
Test status
Simulation time 8803932095 ps
CPU time 13.92 seconds
Started Feb 25 01:47:16 PM PST 24
Finished Feb 25 01:47:30 PM PST 24
Peak memory 182588 kb
Host smart-dfedd303-c389-4152-bf15-6a145103a7e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663898463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.663898463
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.660450716
Short name T386
Test name
Test status
Simulation time 22364018 ps
CPU time 0.55 seconds
Started Feb 25 01:47:18 PM PST 24
Finished Feb 25 01:47:19 PM PST 24
Peak memory 182456 kb
Host smart-78b0fbd4-a23e-4b7b-939e-1b4ce35cb4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660450716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.660450716
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/132.rv_timer_random.3794437934
Short name T10
Test name
Test status
Simulation time 102746116870 ps
CPU time 46.74 seconds
Started Feb 25 01:48:32 PM PST 24
Finished Feb 25 01:49:20 PM PST 24
Peak memory 182728 kb
Host smart-92188bab-cc3d-4e0b-9d63-a85088fad3f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794437934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3794437934
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3304372488
Short name T265
Test name
Test status
Simulation time 572086115557 ps
CPU time 278.32 seconds
Started Feb 25 01:48:32 PM PST 24
Finished Feb 25 01:53:11 PM PST 24
Peak memory 194468 kb
Host smart-066030be-2d9a-4f82-9fc8-7fe373231165
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304372488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3304372488
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.1892947026
Short name T216
Test name
Test status
Simulation time 337781384319 ps
CPU time 648.44 seconds
Started Feb 25 01:48:32 PM PST 24
Finished Feb 25 01:59:21 PM PST 24
Peak memory 190984 kb
Host smart-f26f59df-4995-417f-b18c-0fa2d7a87539
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892947026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1892947026
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2604282956
Short name T152
Test name
Test status
Simulation time 65155433110 ps
CPU time 382.84 seconds
Started Feb 25 01:48:33 PM PST 24
Finished Feb 25 01:54:56 PM PST 24
Peak memory 191004 kb
Host smart-92ec0576-2d27-415e-9a00-fc5f2937c6c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604282956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2604282956
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3873253157
Short name T250
Test name
Test status
Simulation time 4997332187 ps
CPU time 9.45 seconds
Started Feb 25 01:47:15 PM PST 24
Finished Feb 25 01:47:25 PM PST 24
Peak memory 182776 kb
Host smart-40a2d98c-4e03-4511-8aae-3cde4889d1b7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873253157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3873253157
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.162949911
Short name T436
Test name
Test status
Simulation time 341085209072 ps
CPU time 120.47 seconds
Started Feb 25 01:47:24 PM PST 24
Finished Feb 25 01:49:27 PM PST 24
Peak memory 182660 kb
Host smart-88e25be9-3a9f-4cc7-9c28-e7e5ce372c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162949911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.162949911
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.2115598357
Short name T353
Test name
Test status
Simulation time 57372902361 ps
CPU time 44.41 seconds
Started Feb 25 01:47:14 PM PST 24
Finished Feb 25 01:47:58 PM PST 24
Peak memory 190948 kb
Host smart-1d198cbf-9d95-4364-b1e8-50ac46de444a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115598357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2115598357
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.3648892564
Short name T446
Test name
Test status
Simulation time 176028437179 ps
CPU time 172.83 seconds
Started Feb 25 01:48:35 PM PST 24
Finished Feb 25 01:51:28 PM PST 24
Peak memory 190952 kb
Host smart-102b0ccc-c34c-4260-8601-79ed464db9af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648892564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3648892564
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.1949307273
Short name T196
Test name
Test status
Simulation time 324053326383 ps
CPU time 527.87 seconds
Started Feb 25 01:48:37 PM PST 24
Finished Feb 25 01:57:25 PM PST 24
Peak memory 190968 kb
Host smart-b33477df-db8e-4b22-b1dd-166cf1dd299a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949307273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1949307273
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.2730490093
Short name T243
Test name
Test status
Simulation time 256610819734 ps
CPU time 422.34 seconds
Started Feb 25 01:48:45 PM PST 24
Finished Feb 25 01:55:48 PM PST 24
Peak memory 190984 kb
Host smart-ccce9f60-5a25-4736-a817-57ce47fc123a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730490093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2730490093
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.4099010268
Short name T258
Test name
Test status
Simulation time 198441753653 ps
CPU time 2311.45 seconds
Started Feb 25 01:48:45 PM PST 24
Finished Feb 25 02:27:17 PM PST 24
Peak memory 190968 kb
Host smart-78d69117-a697-4adf-b62f-dbf48cb6c001
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099010268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.4099010268
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2863377152
Short name T294
Test name
Test status
Simulation time 327850963733 ps
CPU time 747.72 seconds
Started Feb 25 01:48:43 PM PST 24
Finished Feb 25 02:01:11 PM PST 24
Peak memory 190864 kb
Host smart-b0918eef-0622-40db-95c9-65a23aa5e991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863377152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2863377152
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.2360901522
Short name T117
Test name
Test status
Simulation time 132477485801 ps
CPU time 861.32 seconds
Started Feb 25 01:48:45 PM PST 24
Finished Feb 25 02:03:07 PM PST 24
Peak memory 190952 kb
Host smart-3d0719f4-d9e4-4d25-90cc-eada0ad75b64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360901522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2360901522
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.4057797363
Short name T184
Test name
Test status
Simulation time 78428000152 ps
CPU time 125.48 seconds
Started Feb 25 01:48:43 PM PST 24
Finished Feb 25 01:50:49 PM PST 24
Peak memory 193208 kb
Host smart-a61186a9-8b70-4b7b-a255-e270eb01fb9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057797363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.4057797363
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.3500511184
Short name T122
Test name
Test status
Simulation time 926384899727 ps
CPU time 464 seconds
Started Feb 25 01:47:24 PM PST 24
Finished Feb 25 01:55:10 PM PST 24
Peak memory 182676 kb
Host smart-5341037f-5b86-4cbd-81a8-70050bef482b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500511184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.3500511184
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1935905285
Short name T85
Test name
Test status
Simulation time 177468778318 ps
CPU time 74.43 seconds
Started Feb 25 01:47:21 PM PST 24
Finished Feb 25 01:48:37 PM PST 24
Peak memory 182692 kb
Host smart-e8f6f1c6-7557-4012-b1b1-570f2b168926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935905285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1935905285
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.760278561
Short name T132
Test name
Test status
Simulation time 55636008395 ps
CPU time 350.85 seconds
Started Feb 25 01:47:17 PM PST 24
Finished Feb 25 01:53:08 PM PST 24
Peak memory 190912 kb
Host smart-d689b4d5-d917-4286-9049-ec3ba3b994d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760278561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.760278561
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.2995120611
Short name T87
Test name
Test status
Simulation time 29716600499 ps
CPU time 1007.12 seconds
Started Feb 25 01:47:33 PM PST 24
Finished Feb 25 02:04:20 PM PST 24
Peak memory 182684 kb
Host smart-c01e5e4d-94e9-49f5-86fb-a5786592d38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995120611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.2995120611
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1155726580
Short name T238
Test name
Test status
Simulation time 565216154982 ps
CPU time 1030.61 seconds
Started Feb 25 01:47:21 PM PST 24
Finished Feb 25 02:04:33 PM PST 24
Peak memory 195184 kb
Host smart-669d2a1c-e9b7-4c1f-a73a-ce67ae36eea9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155726580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1155726580
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.3708752531
Short name T37
Test name
Test status
Simulation time 94674870630 ps
CPU time 214.67 seconds
Started Feb 25 01:47:23 PM PST 24
Finished Feb 25 01:50:58 PM PST 24
Peak memory 209716 kb
Host smart-6d809cfe-fe41-4483-b53a-70c529d657ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708752531 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.3708752531
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.485092110
Short name T359
Test name
Test status
Simulation time 33857543367 ps
CPU time 29.08 seconds
Started Feb 25 01:48:51 PM PST 24
Finished Feb 25 01:49:20 PM PST 24
Peak memory 182672 kb
Host smart-6277d04c-50af-4c2b-9e94-384f888fd2e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485092110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.485092110
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.1315571362
Short name T331
Test name
Test status
Simulation time 236335040064 ps
CPU time 121.79 seconds
Started Feb 25 01:48:52 PM PST 24
Finished Feb 25 01:50:54 PM PST 24
Peak memory 194812 kb
Host smart-e7f53e9e-3032-40ac-a681-b5db44c23eac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315571362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1315571362
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.132348469
Short name T275
Test name
Test status
Simulation time 28772991751 ps
CPU time 77.9 seconds
Started Feb 25 01:48:51 PM PST 24
Finished Feb 25 01:50:10 PM PST 24
Peak memory 190948 kb
Host smart-145b3009-7fc9-4a8e-8ca2-113cbdbdd083
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132348469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.132348469
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.3119338227
Short name T364
Test name
Test status
Simulation time 117474271036 ps
CPU time 261.45 seconds
Started Feb 25 01:48:49 PM PST 24
Finished Feb 25 01:53:11 PM PST 24
Peak memory 182656 kb
Host smart-ccfb0d07-d1e5-4ca9-9f8f-5ec2d7e930af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119338227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3119338227
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3864832760
Short name T338
Test name
Test status
Simulation time 774260451671 ps
CPU time 236.29 seconds
Started Feb 25 01:48:49 PM PST 24
Finished Feb 25 01:52:46 PM PST 24
Peak memory 190964 kb
Host smart-775014ab-3c0d-45f2-8793-76d426d97480
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864832760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3864832760
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.1159319831
Short name T26
Test name
Test status
Simulation time 280891500556 ps
CPU time 211.68 seconds
Started Feb 25 01:48:52 PM PST 24
Finished Feb 25 01:52:24 PM PST 24
Peak memory 190968 kb
Host smart-afe207c5-5572-4f22-9564-b1a1c81377b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159319831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1159319831
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.675651988
Short name T324
Test name
Test status
Simulation time 39864870861 ps
CPU time 87.52 seconds
Started Feb 25 01:48:53 PM PST 24
Finished Feb 25 01:50:21 PM PST 24
Peak memory 193088 kb
Host smart-6facb9bc-ae94-43f2-8511-281172b74ce7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675651988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.675651988
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.1703663326
Short name T84
Test name
Test status
Simulation time 175575953331 ps
CPU time 604.75 seconds
Started Feb 25 01:48:50 PM PST 24
Finished Feb 25 01:58:55 PM PST 24
Peak memory 190948 kb
Host smart-b36ffdf4-b149-4633-bafe-a17e6b696087
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703663326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1703663326
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2762491321
Short name T302
Test name
Test status
Simulation time 2397438835912 ps
CPU time 1264.69 seconds
Started Feb 25 01:47:19 PM PST 24
Finished Feb 25 02:08:25 PM PST 24
Peak memory 182676 kb
Host smart-543e4a85-6506-4b95-a384-56b06e6473a5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762491321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2762491321
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.3742260711
Short name T383
Test name
Test status
Simulation time 469462821138 ps
CPU time 196.6 seconds
Started Feb 25 01:47:33 PM PST 24
Finished Feb 25 01:50:50 PM PST 24
Peak memory 182708 kb
Host smart-75692697-3a7c-4e93-924b-7ee6c9e03864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742260711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3742260711
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.4065877730
Short name T60
Test name
Test status
Simulation time 64871633419 ps
CPU time 177.04 seconds
Started Feb 25 01:47:31 PM PST 24
Finished Feb 25 01:50:28 PM PST 24
Peak memory 182708 kb
Host smart-1d60e023-7e6b-4c2c-8b01-c931b82ffffd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065877730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.4065877730
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.822559987
Short name T444
Test name
Test status
Simulation time 8749342523 ps
CPU time 12 seconds
Started Feb 25 01:47:17 PM PST 24
Finished Feb 25 01:47:29 PM PST 24
Peak memory 182580 kb
Host smart-a3aa14ca-0f75-48f6-b8b7-dc4a5963eda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822559987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.822559987
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3800698150
Short name T449
Test name
Test status
Simulation time 449870882132 ps
CPU time 378.36 seconds
Started Feb 25 01:47:23 PM PST 24
Finished Feb 25 01:53:42 PM PST 24
Peak memory 195240 kb
Host smart-1ec0509e-5d86-43a5-8947-c859e7e175a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800698150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3800698150
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/161.rv_timer_random.2848802667
Short name T400
Test name
Test status
Simulation time 73897050208 ps
CPU time 132.99 seconds
Started Feb 25 01:48:51 PM PST 24
Finished Feb 25 01:51:04 PM PST 24
Peak memory 190980 kb
Host smart-62e48791-277c-41d6-a86e-ec3ae14591fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848802667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2848802667
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.464285890
Short name T194
Test name
Test status
Simulation time 71431568119 ps
CPU time 30.68 seconds
Started Feb 25 01:48:54 PM PST 24
Finished Feb 25 01:49:25 PM PST 24
Peak memory 190964 kb
Host smart-c8c21b96-a722-42b2-9c0a-242d62f51467
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464285890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.464285890
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.1100206337
Short name T167
Test name
Test status
Simulation time 156825098137 ps
CPU time 117.86 seconds
Started Feb 25 01:48:51 PM PST 24
Finished Feb 25 01:50:50 PM PST 24
Peak memory 190972 kb
Host smart-4a1c556d-623e-4006-aba1-7bbee75198d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100206337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1100206337
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.1856638586
Short name T165
Test name
Test status
Simulation time 25079584672 ps
CPU time 39.54 seconds
Started Feb 25 01:48:54 PM PST 24
Finished Feb 25 01:49:34 PM PST 24
Peak memory 182784 kb
Host smart-0a9ae627-e49d-420d-9c37-7dc40fc8a4e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856638586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1856638586
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.3893766869
Short name T158
Test name
Test status
Simulation time 156491372347 ps
CPU time 928.68 seconds
Started Feb 25 01:49:05 PM PST 24
Finished Feb 25 02:04:34 PM PST 24
Peak memory 182792 kb
Host smart-bf2af0f4-3b29-4cea-b74b-b57c12ca37c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893766869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3893766869
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3753135840
Short name T313
Test name
Test status
Simulation time 54154503731 ps
CPU time 142.99 seconds
Started Feb 25 01:49:07 PM PST 24
Finished Feb 25 01:51:30 PM PST 24
Peak memory 190980 kb
Host smart-265cd71e-6284-4c06-9177-1a3dafb4bc4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753135840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3753135840
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3947856500
Short name T121
Test name
Test status
Simulation time 2549093473 ps
CPU time 3.07 seconds
Started Feb 25 01:47:21 PM PST 24
Finished Feb 25 01:47:25 PM PST 24
Peak memory 182772 kb
Host smart-9fd02e73-8538-4ac4-a645-3fce8c08fa54
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947856500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3947856500
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.2133370228
Short name T414
Test name
Test status
Simulation time 136512910446 ps
CPU time 179.65 seconds
Started Feb 25 01:47:21 PM PST 24
Finished Feb 25 01:50:22 PM PST 24
Peak memory 182688 kb
Host smart-c029a235-e988-404f-97d6-ed97cab522e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133370228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2133370228
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.2631318158
Short name T172
Test name
Test status
Simulation time 89719677871 ps
CPU time 144.15 seconds
Started Feb 25 01:47:19 PM PST 24
Finished Feb 25 01:49:44 PM PST 24
Peak memory 190952 kb
Host smart-c0c60753-3184-467b-9a32-f33303493272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631318158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2631318158
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3898885652
Short name T46
Test name
Test status
Simulation time 46060967034 ps
CPU time 764.95 seconds
Started Feb 25 01:47:19 PM PST 24
Finished Feb 25 02:00:05 PM PST 24
Peak memory 182468 kb
Host smart-bc1733a8-9f3a-45d0-92ab-28f6c2567afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898885652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3898885652
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.481271499
Short name T366
Test name
Test status
Simulation time 2513821391049 ps
CPU time 774.89 seconds
Started Feb 25 01:47:19 PM PST 24
Finished Feb 25 02:00:16 PM PST 24
Peak memory 190864 kb
Host smart-8a0b464d-4e97-4516-bfbb-3d57466636ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481271499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.
481271499
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/173.rv_timer_random.545680589
Short name T78
Test name
Test status
Simulation time 12425788120 ps
CPU time 16.58 seconds
Started Feb 25 01:49:05 PM PST 24
Finished Feb 25 01:49:21 PM PST 24
Peak memory 182428 kb
Host smart-5180d327-9b86-47c2-89bd-0d7bf77c1373
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545680589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.545680589
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.975138882
Short name T253
Test name
Test status
Simulation time 116095645689 ps
CPU time 101.08 seconds
Started Feb 25 01:49:05 PM PST 24
Finished Feb 25 01:50:46 PM PST 24
Peak memory 190948 kb
Host smart-28752cb0-eeab-4b3f-aa5c-52c2e27cbeae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975138882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.975138882
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.492923938
Short name T295
Test name
Test status
Simulation time 185190827913 ps
CPU time 92.37 seconds
Started Feb 25 01:49:07 PM PST 24
Finished Feb 25 01:50:40 PM PST 24
Peak memory 182752 kb
Host smart-bc32eeb6-8250-4484-8564-db582736833a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492923938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.492923938
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.480235445
Short name T437
Test name
Test status
Simulation time 134182253011 ps
CPU time 248.42 seconds
Started Feb 25 01:49:06 PM PST 24
Finished Feb 25 01:53:14 PM PST 24
Peak memory 194096 kb
Host smart-0b20762b-9b27-47c4-909b-1b38d6c5164a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480235445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.480235445
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.386443407
Short name T221
Test name
Test status
Simulation time 312008470409 ps
CPU time 229.84 seconds
Started Feb 25 01:49:07 PM PST 24
Finished Feb 25 01:52:57 PM PST 24
Peak memory 190776 kb
Host smart-32cd7722-d7d3-46f1-8caa-66f249bddadd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386443407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.386443407
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2341968557
Short name T8
Test name
Test status
Simulation time 1909776648963 ps
CPU time 1139.27 seconds
Started Feb 25 01:47:25 PM PST 24
Finished Feb 25 02:06:26 PM PST 24
Peak memory 182792 kb
Host smart-76aa290c-8e0d-4ca4-88e7-af9fd60958d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341968557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.2341968557
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.3850843647
Short name T451
Test name
Test status
Simulation time 587117896808 ps
CPU time 226.73 seconds
Started Feb 25 01:47:18 PM PST 24
Finished Feb 25 01:51:06 PM PST 24
Peak memory 182756 kb
Host smart-e896cae0-d4c9-45ec-897d-e4e54a66d4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850843647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3850843647
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3402348355
Short name T433
Test name
Test status
Simulation time 93720058 ps
CPU time 0.67 seconds
Started Feb 25 01:47:18 PM PST 24
Finished Feb 25 01:47:20 PM PST 24
Peak memory 182516 kb
Host smart-0dca7b85-5604-4b2d-9038-4dc5e15978be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402348355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3402348355
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3408264208
Short name T116
Test name
Test status
Simulation time 164327120175 ps
CPU time 129.24 seconds
Started Feb 25 01:47:25 PM PST 24
Finished Feb 25 01:49:36 PM PST 24
Peak memory 182816 kb
Host smart-f723b043-47cc-4378-8f24-a3908a9942f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408264208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3408264208
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.886383637
Short name T281
Test name
Test status
Simulation time 1116098531016 ps
CPU time 797 seconds
Started Feb 25 01:49:07 PM PST 24
Finished Feb 25 02:02:24 PM PST 24
Peak memory 190948 kb
Host smart-b45b1f01-cf59-4b6b-bcdf-eff9c177276f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886383637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.886383637
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.2636192155
Short name T397
Test name
Test status
Simulation time 7151335668 ps
CPU time 12.13 seconds
Started Feb 25 01:49:05 PM PST 24
Finished Feb 25 01:49:18 PM PST 24
Peak memory 182696 kb
Host smart-e080825d-5870-4003-83e9-6c6cd80af345
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636192155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2636192155
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.3766297407
Short name T242
Test name
Test status
Simulation time 83738997227 ps
CPU time 1343.72 seconds
Started Feb 25 01:49:05 PM PST 24
Finished Feb 25 02:11:29 PM PST 24
Peak memory 190924 kb
Host smart-acc18949-f5b1-461f-97de-06bad14ddd53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766297407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3766297407
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3657528329
Short name T118
Test name
Test status
Simulation time 49833838753 ps
CPU time 388.45 seconds
Started Feb 25 01:49:05 PM PST 24
Finished Feb 25 01:55:34 PM PST 24
Peak memory 190964 kb
Host smart-03b49309-313e-4e60-99fe-550ae95949e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657528329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3657528329
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1076728608
Short name T82
Test name
Test status
Simulation time 38390785317 ps
CPU time 224.92 seconds
Started Feb 25 01:49:12 PM PST 24
Finished Feb 25 01:52:58 PM PST 24
Peak memory 182776 kb
Host smart-f32c18e8-f8ea-4283-ac17-18a9936b4b0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076728608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1076728608
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1279402936
Short name T360
Test name
Test status
Simulation time 796409454077 ps
CPU time 995.29 seconds
Started Feb 25 01:49:13 PM PST 24
Finished Feb 25 02:05:49 PM PST 24
Peak memory 190852 kb
Host smart-0026e609-df16-4dee-b6b1-8d2aa15fcabe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279402936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1279402936
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3100387889
Short name T240
Test name
Test status
Simulation time 651106081420 ps
CPU time 1832.47 seconds
Started Feb 25 01:49:12 PM PST 24
Finished Feb 25 02:19:44 PM PST 24
Peak memory 193128 kb
Host smart-1a616659-6090-4293-816d-8050047c4d70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100387889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3100387889
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.357656662
Short name T115
Test name
Test status
Simulation time 30661812036 ps
CPU time 49.59 seconds
Started Feb 25 01:47:24 PM PST 24
Finished Feb 25 01:48:16 PM PST 24
Peak memory 182776 kb
Host smart-76752282-9fa3-4b18-9c0c-bcf434a1b929
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357656662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.357656662
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.4179889017
Short name T422
Test name
Test status
Simulation time 104579561762 ps
CPU time 147.95 seconds
Started Feb 25 01:47:23 PM PST 24
Finished Feb 25 01:49:53 PM PST 24
Peak memory 182668 kb
Host smart-7b2b99d6-1ac6-4cb8-92ed-a9b12e84e631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179889017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.4179889017
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.2554988815
Short name T330
Test name
Test status
Simulation time 458671561503 ps
CPU time 1869.96 seconds
Started Feb 25 01:47:19 PM PST 24
Finished Feb 25 02:18:30 PM PST 24
Peak memory 182744 kb
Host smart-728133cd-46ea-467b-b8f3-2adb0de75d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554988815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2554988815
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/191.rv_timer_random.2537422048
Short name T48
Test name
Test status
Simulation time 297900384552 ps
CPU time 213.93 seconds
Started Feb 25 01:49:13 PM PST 24
Finished Feb 25 01:52:47 PM PST 24
Peak memory 193404 kb
Host smart-e05ba73a-948b-4a9f-b1ed-fec2faf56f8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537422048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.2537422048
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.2268033815
Short name T21
Test name
Test status
Simulation time 2732045563504 ps
CPU time 822.38 seconds
Started Feb 25 01:49:10 PM PST 24
Finished Feb 25 02:02:53 PM PST 24
Peak memory 190928 kb
Host smart-70f936a3-72bf-442d-874b-d4ede53ee749
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268033815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2268033815
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3022756754
Short name T347
Test name
Test status
Simulation time 180713966008 ps
CPU time 316.01 seconds
Started Feb 25 01:49:10 PM PST 24
Finished Feb 25 01:54:26 PM PST 24
Peak memory 190928 kb
Host smart-44b5ae69-8eec-48fc-b994-4e522b4e578c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022756754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3022756754
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.4016383020
Short name T262
Test name
Test status
Simulation time 448293456852 ps
CPU time 816.46 seconds
Started Feb 25 01:49:12 PM PST 24
Finished Feb 25 02:02:48 PM PST 24
Peak memory 190972 kb
Host smart-d34aa16d-dff9-4187-8f93-8fe6a8b6ddb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016383020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.4016383020
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.4024998270
Short name T453
Test name
Test status
Simulation time 81074700464 ps
CPU time 226.22 seconds
Started Feb 25 01:49:09 PM PST 24
Finished Feb 25 01:52:55 PM PST 24
Peak memory 190968 kb
Host smart-25a86f1f-977a-4db9-a4e7-cab2a947abab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024998270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.4024998270
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.3246435440
Short name T198
Test name
Test status
Simulation time 278294048921 ps
CPU time 1160.83 seconds
Started Feb 25 01:49:17 PM PST 24
Finished Feb 25 02:08:38 PM PST 24
Peak memory 190928 kb
Host smart-8b019fcf-d3c9-4385-b7ed-f20dfab8b2ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246435440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3246435440
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3946136385
Short name T220
Test name
Test status
Simulation time 323642951886 ps
CPU time 191.67 seconds
Started Feb 25 01:49:12 PM PST 24
Finished Feb 25 01:52:24 PM PST 24
Peak memory 193276 kb
Host smart-5be37990-d9f9-41d2-b1d0-5588fe62d525
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946136385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3946136385
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3453022031
Short name T201
Test name
Test status
Simulation time 1490130172839 ps
CPU time 1293.94 seconds
Started Feb 25 01:46:56 PM PST 24
Finished Feb 25 02:08:30 PM PST 24
Peak memory 182792 kb
Host smart-5e1add7e-0b95-4b2d-9193-4e27e6142636
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453022031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3453022031
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.848854663
Short name T387
Test name
Test status
Simulation time 44096617412 ps
CPU time 71.88 seconds
Started Feb 25 01:46:59 PM PST 24
Finished Feb 25 01:48:11 PM PST 24
Peak memory 182768 kb
Host smart-4118bbfa-eb18-4021-a0d5-f4ed632e2b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848854663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.848854663
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3015493889
Short name T211
Test name
Test status
Simulation time 590223169855 ps
CPU time 339.21 seconds
Started Feb 25 01:46:59 PM PST 24
Finished Feb 25 01:52:39 PM PST 24
Peak memory 190960 kb
Host smart-c3d25d9d-d174-43c9-a5d6-ef5597613152
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015493889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3015493889
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.760500822
Short name T320
Test name
Test status
Simulation time 44420877667 ps
CPU time 78.65 seconds
Started Feb 25 01:47:03 PM PST 24
Finished Feb 25 01:48:22 PM PST 24
Peak memory 190912 kb
Host smart-d533ed66-ad84-45ea-acf6-62058a49c9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760500822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.760500822
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.4128055203
Short name T17
Test name
Test status
Simulation time 469891345 ps
CPU time 0.93 seconds
Started Feb 25 01:47:05 PM PST 24
Finished Feb 25 01:47:06 PM PST 24
Peak memory 214028 kb
Host smart-fdcc8237-69cc-474f-bc01-cbf1b151280e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128055203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.4128055203
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2988058595
Short name T377
Test name
Test status
Simulation time 487929363758 ps
CPU time 240.62 seconds
Started Feb 25 01:47:05 PM PST 24
Finished Feb 25 01:51:06 PM PST 24
Peak memory 195268 kb
Host smart-aeb2e5c3-b8c7-43fd-82fd-9e6514cbbad3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988058595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2988058595
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.4201375474
Short name T318
Test name
Test status
Simulation time 127232910410 ps
CPU time 203.26 seconds
Started Feb 25 01:47:24 PM PST 24
Finished Feb 25 01:50:49 PM PST 24
Peak memory 182640 kb
Host smart-5cb4e802-6c83-4c55-9f4e-6a825cf89808
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201375474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.4201375474
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.3494501855
Short name T119
Test name
Test status
Simulation time 20928890385 ps
CPU time 16.97 seconds
Started Feb 25 01:47:19 PM PST 24
Finished Feb 25 01:47:37 PM PST 24
Peak memory 182760 kb
Host smart-a6edcfdf-a2a3-487e-bfb3-55a4881cab10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494501855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3494501855
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3997102083
Short name T179
Test name
Test status
Simulation time 489720711145 ps
CPU time 306.38 seconds
Started Feb 25 01:47:24 PM PST 24
Finished Feb 25 01:52:32 PM PST 24
Peak memory 190856 kb
Host smart-9d8feea1-e3b1-45d1-9082-3f0564304cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997102083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3997102083
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2825319785
Short name T361
Test name
Test status
Simulation time 26500014307 ps
CPU time 23.95 seconds
Started Feb 25 01:47:31 PM PST 24
Finished Feb 25 01:47:55 PM PST 24
Peak memory 182736 kb
Host smart-c7e1dc2f-ae7b-45c3-b415-1acca11c6858
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825319785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2825319785
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.4216513423
Short name T427
Test name
Test status
Simulation time 306978073894 ps
CPU time 70.95 seconds
Started Feb 25 01:47:33 PM PST 24
Finished Feb 25 01:48:44 PM PST 24
Peak memory 182704 kb
Host smart-6f5fb4ec-3f8f-4f75-809c-dfd964f22b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216513423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.4216513423
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.1186382809
Short name T329
Test name
Test status
Simulation time 286271766203 ps
CPU time 274.72 seconds
Started Feb 25 01:47:20 PM PST 24
Finished Feb 25 01:51:57 PM PST 24
Peak memory 190968 kb
Host smart-8d56edce-4f94-415c-a1f5-8d993d054f28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186382809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1186382809
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.557472502
Short name T63
Test name
Test status
Simulation time 23085348325 ps
CPU time 43.3 seconds
Started Feb 25 01:47:21 PM PST 24
Finished Feb 25 01:48:05 PM PST 24
Peak memory 194228 kb
Host smart-1f737227-c7a3-4622-b2bc-207db293dc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557472502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.557472502
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3104831303
Short name T280
Test name
Test status
Simulation time 1051421546827 ps
CPU time 592.41 seconds
Started Feb 25 01:47:23 PM PST 24
Finished Feb 25 01:57:18 PM PST 24
Peak memory 182776 kb
Host smart-38a8a55f-151b-4ba3-99cf-6a176a00fa63
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104831303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3104831303
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3906938695
Short name T421
Test name
Test status
Simulation time 168842350510 ps
CPU time 237.46 seconds
Started Feb 25 01:47:23 PM PST 24
Finished Feb 25 01:51:23 PM PST 24
Peak memory 182752 kb
Host smart-4505a27e-3958-4681-8daf-9e1061a1765e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906938695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3906938695
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.594824267
Short name T343
Test name
Test status
Simulation time 91853065268 ps
CPU time 63.85 seconds
Started Feb 25 01:47:18 PM PST 24
Finished Feb 25 01:48:22 PM PST 24
Peak memory 182760 kb
Host smart-0fd0926e-d248-4f64-a323-2f9196323600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594824267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.594824267
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.675900609
Short name T159
Test name
Test status
Simulation time 7629359083 ps
CPU time 5.15 seconds
Started Feb 25 01:47:24 PM PST 24
Finished Feb 25 01:47:31 PM PST 24
Peak memory 182772 kb
Host smart-699fa8ff-2c9c-42c7-9271-c2f88ef1e25b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675900609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.675900609
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.3277595974
Short name T391
Test name
Test status
Simulation time 373261609427 ps
CPU time 150.87 seconds
Started Feb 25 01:47:17 PM PST 24
Finished Feb 25 01:49:48 PM PST 24
Peak memory 182752 kb
Host smart-c36275b3-4b47-4f40-a303-aeae26e71924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277595974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3277595974
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1883443034
Short name T3
Test name
Test status
Simulation time 366810683433 ps
CPU time 1691.26 seconds
Started Feb 25 01:47:24 PM PST 24
Finished Feb 25 02:15:37 PM PST 24
Peak memory 190768 kb
Host smart-82f85655-a9dd-4194-a926-be90e16dcfcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883443034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1883443034
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.51174035
Short name T368
Test name
Test status
Simulation time 181893035 ps
CPU time 1.47 seconds
Started Feb 25 01:47:31 PM PST 24
Finished Feb 25 01:47:32 PM PST 24
Peak memory 182672 kb
Host smart-a2474819-2b4b-41d2-9463-92247dc86c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51174035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.51174035
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2750401236
Short name T68
Test name
Test status
Simulation time 23015082 ps
CPU time 0.56 seconds
Started Feb 25 01:47:24 PM PST 24
Finished Feb 25 01:47:26 PM PST 24
Peak memory 182332 kb
Host smart-c40721a6-e29e-4ce2-a576-0791f1921735
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750401236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2750401236
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2080769656
Short name T296
Test name
Test status
Simulation time 388644864694 ps
CPU time 325.68 seconds
Started Feb 25 01:47:16 PM PST 24
Finished Feb 25 01:52:42 PM PST 24
Peak memory 182884 kb
Host smart-5797293a-a848-4c6c-9101-38198b9e0cf3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080769656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2080769656
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.1784693331
Short name T384
Test name
Test status
Simulation time 33169639197 ps
CPU time 45.63 seconds
Started Feb 25 01:47:32 PM PST 24
Finished Feb 25 01:48:18 PM PST 24
Peak memory 182572 kb
Host smart-34ce6a86-fe1e-4605-a665-d30facdb1d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784693331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.1784693331
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.3433889706
Short name T269
Test name
Test status
Simulation time 64893905327 ps
CPU time 104.33 seconds
Started Feb 25 01:47:24 PM PST 24
Finished Feb 25 01:49:11 PM PST 24
Peak memory 190604 kb
Host smart-1267582a-6add-47b4-b75a-720f8d042642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433889706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3433889706
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1380682050
Short name T405
Test name
Test status
Simulation time 212131075 ps
CPU time 0.61 seconds
Started Feb 25 01:47:24 PM PST 24
Finished Feb 25 01:47:27 PM PST 24
Peak memory 182436 kb
Host smart-dd3935b5-d11e-4de1-a375-2a6b963eb98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380682050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1380682050
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.3831224164
Short name T305
Test name
Test status
Simulation time 344717137763 ps
CPU time 575.68 seconds
Started Feb 25 01:47:34 PM PST 24
Finished Feb 25 01:57:10 PM PST 24
Peak memory 182596 kb
Host smart-b6fa34aa-ba12-418d-ba45-03f6181f6291
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831224164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.3831224164
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.2298002737
Short name T424
Test name
Test status
Simulation time 225585625333 ps
CPU time 180.74 seconds
Started Feb 25 01:47:20 PM PST 24
Finished Feb 25 01:50:22 PM PST 24
Peak memory 182756 kb
Host smart-033ca1a2-cf26-4dd2-bee5-14104a050c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298002737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2298002737
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.1148682227
Short name T161
Test name
Test status
Simulation time 5835443466 ps
CPU time 209.05 seconds
Started Feb 25 01:47:34 PM PST 24
Finished Feb 25 01:51:03 PM PST 24
Peak memory 182592 kb
Host smart-ada054a9-0dc7-4b1c-902e-042da951ebed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148682227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1148682227
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.2627751615
Short name T438
Test name
Test status
Simulation time 994535110 ps
CPU time 1.06 seconds
Started Feb 25 01:47:20 PM PST 24
Finished Feb 25 01:47:23 PM PST 24
Peak memory 182528 kb
Host smart-d0ae24c8-ec7e-4c4d-b8fc-3e7e538a3eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627751615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2627751615
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2759281611
Short name T456
Test name
Test status
Simulation time 1261891633324 ps
CPU time 1374.52 seconds
Started Feb 25 01:47:19 PM PST 24
Finished Feb 25 02:10:15 PM PST 24
Peak memory 194076 kb
Host smart-14d5002b-a47d-4bd7-81d4-5a98bd76fe5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759281611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2759281611
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.449009044
Short name T193
Test name
Test status
Simulation time 53770305191 ps
CPU time 93.67 seconds
Started Feb 25 01:47:24 PM PST 24
Finished Feb 25 01:48:59 PM PST 24
Peak memory 182652 kb
Host smart-5edf629b-d684-4cd2-9906-2581939be410
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449009044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.449009044
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2589680081
Short name T372
Test name
Test status
Simulation time 49890613727 ps
CPU time 66.36 seconds
Started Feb 25 01:47:15 PM PST 24
Finished Feb 25 01:48:21 PM PST 24
Peak memory 182700 kb
Host smart-a5dee711-0582-4a82-b22d-25237b9e606f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589680081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2589680081
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.2166163420
Short name T88
Test name
Test status
Simulation time 34210248481 ps
CPU time 356.14 seconds
Started Feb 25 01:47:25 PM PST 24
Finished Feb 25 01:53:23 PM PST 24
Peak memory 182752 kb
Host smart-d573410a-8a34-4d58-a40b-897cb7f5ba69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166163420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2166163420
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3657626919
Short name T29
Test name
Test status
Simulation time 32994486573 ps
CPU time 64.53 seconds
Started Feb 25 01:47:22 PM PST 24
Finished Feb 25 01:48:27 PM PST 24
Peak memory 194728 kb
Host smart-eb9885a6-d48c-4d45-a43c-f91788e62a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657626919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3657626919
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1841468558
Short name T195
Test name
Test status
Simulation time 393487340877 ps
CPU time 309.5 seconds
Started Feb 25 01:47:18 PM PST 24
Finished Feb 25 01:52:28 PM PST 24
Peak memory 190988 kb
Host smart-51e6ed0b-deab-418a-a682-4a3ac159e857
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841468558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1841468558
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.3914642147
Short name T42
Test name
Test status
Simulation time 52094919896 ps
CPU time 606.35 seconds
Started Feb 25 01:47:20 PM PST 24
Finished Feb 25 01:57:28 PM PST 24
Peak memory 205720 kb
Host smart-273dea7d-a3da-41ac-ac5c-298d25d3bca7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914642147 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.3914642147
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3360212559
Short name T301
Test name
Test status
Simulation time 962652024356 ps
CPU time 685.37 seconds
Started Feb 25 01:47:16 PM PST 24
Finished Feb 25 01:58:42 PM PST 24
Peak memory 182748 kb
Host smart-47975c5d-351c-4c6e-9ff5-4c605ee5bb37
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360212559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3360212559
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.3599096850
Short name T399
Test name
Test status
Simulation time 235561990697 ps
CPU time 141.67 seconds
Started Feb 25 01:47:34 PM PST 24
Finished Feb 25 01:49:56 PM PST 24
Peak memory 182572 kb
Host smart-0e006fe8-bbf1-4fc9-ba87-2a9aaed97962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599096850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3599096850
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.4104384021
Short name T79
Test name
Test status
Simulation time 365118505 ps
CPU time 0.88 seconds
Started Feb 25 01:47:19 PM PST 24
Finished Feb 25 01:47:22 PM PST 24
Peak memory 191136 kb
Host smart-c10a2893-b539-4a6f-b51b-22b410f66136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104384021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.4104384021
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.2480716366
Short name T81
Test name
Test status
Simulation time 243181524911 ps
CPU time 93.75 seconds
Started Feb 25 01:47:23 PM PST 24
Finished Feb 25 01:48:57 PM PST 24
Peak memory 182708 kb
Host smart-b2f65bb7-91ff-47b1-82a3-9f7546a2c7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480716366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2480716366
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.3451173900
Short name T342
Test name
Test status
Simulation time 256861385432 ps
CPU time 125.34 seconds
Started Feb 25 01:47:34 PM PST 24
Finished Feb 25 01:49:40 PM PST 24
Peak memory 194308 kb
Host smart-2732c593-d907-4e2f-92a1-54e9ed171ebd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451173900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3451173900
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.4204356425
Short name T168
Test name
Test status
Simulation time 337918212491 ps
CPU time 194.45 seconds
Started Feb 25 01:47:27 PM PST 24
Finished Feb 25 01:50:43 PM PST 24
Peak memory 190960 kb
Host smart-39a3cfbe-ca76-4443-bc61-e4a825b83db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204356425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.4204356425
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.303542558
Short name T160
Test name
Test status
Simulation time 351713434120 ps
CPU time 1270.83 seconds
Started Feb 25 01:47:30 PM PST 24
Finished Feb 25 02:08:41 PM PST 24
Peak memory 191012 kb
Host smart-17aac3b5-7504-4140-af0f-e8ed41dcdbcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303542558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.
303542558
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3779648059
Short name T188
Test name
Test status
Simulation time 86252983241 ps
CPU time 77.25 seconds
Started Feb 25 01:47:28 PM PST 24
Finished Feb 25 01:48:47 PM PST 24
Peak memory 182780 kb
Host smart-15bc942e-be5f-4412-b934-1bd31f63081f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779648059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.3779648059
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.3309793403
Short name T447
Test name
Test status
Simulation time 107995294928 ps
CPU time 165.73 seconds
Started Feb 25 01:47:28 PM PST 24
Finished Feb 25 01:50:15 PM PST 24
Peak memory 182760 kb
Host smart-6a3a70bc-5be4-448e-b92c-8582f8a21669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309793403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.3309793403
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.354476248
Short name T440
Test name
Test status
Simulation time 32514764755 ps
CPU time 377.26 seconds
Started Feb 25 01:47:27 PM PST 24
Finished Feb 25 01:53:46 PM PST 24
Peak memory 182692 kb
Host smart-6a2b146f-e841-48f9-935b-68279fded168
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354476248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.354476248
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2615257031
Short name T374
Test name
Test status
Simulation time 75096339 ps
CPU time 0.54 seconds
Started Feb 25 01:47:31 PM PST 24
Finished Feb 25 01:47:32 PM PST 24
Peak memory 182440 kb
Host smart-a89bbeb8-922d-4302-8ca9-41a902abb4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615257031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2615257031
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.1190428649
Short name T166
Test name
Test status
Simulation time 2383983272720 ps
CPU time 930.67 seconds
Started Feb 25 01:47:09 PM PST 24
Finished Feb 25 02:02:40 PM PST 24
Peak memory 182776 kb
Host smart-3e28f071-a795-4c8f-81ee-b1e23017f304
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190428649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.1190428649
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1410162840
Short name T430
Test name
Test status
Simulation time 526644374229 ps
CPU time 391.12 seconds
Started Feb 25 01:46:57 PM PST 24
Finished Feb 25 01:53:28 PM PST 24
Peak memory 182768 kb
Host smart-c958f928-3895-4aff-8630-3a01ce7d31c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410162840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1410162840
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.201912724
Short name T200
Test name
Test status
Simulation time 420706219172 ps
CPU time 872.97 seconds
Started Feb 25 01:47:06 PM PST 24
Finished Feb 25 02:01:39 PM PST 24
Peak memory 191000 kb
Host smart-652b867a-bad6-428e-b475-d2425dee69ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201912724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.201912724
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3157289176
Short name T333
Test name
Test status
Simulation time 104620493107 ps
CPU time 46.59 seconds
Started Feb 25 01:47:01 PM PST 24
Finished Feb 25 01:47:48 PM PST 24
Peak memory 182504 kb
Host smart-0365449b-0375-4112-9aa6-ec7c1e604bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157289176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3157289176
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3255860125
Short name T19
Test name
Test status
Simulation time 63567040 ps
CPU time 0.75 seconds
Started Feb 25 01:47:11 PM PST 24
Finished Feb 25 01:47:11 PM PST 24
Peak memory 212936 kb
Host smart-d2131366-f410-4f3e-a29f-76794022175d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255860125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3255860125
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3495107549
Short name T337
Test name
Test status
Simulation time 49751920214 ps
CPU time 29.59 seconds
Started Feb 25 01:47:27 PM PST 24
Finished Feb 25 01:47:59 PM PST 24
Peak memory 182780 kb
Host smart-b7f92d26-59e9-460a-82df-b733d60ef517
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495107549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3495107549
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3851699806
Short name T76
Test name
Test status
Simulation time 617898811603 ps
CPU time 242.74 seconds
Started Feb 25 01:47:30 PM PST 24
Finished Feb 25 01:51:33 PM PST 24
Peak memory 182752 kb
Host smart-5f78ebcc-5b33-464d-9fa0-0e7d377a65de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851699806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3851699806
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.726458459
Short name T300
Test name
Test status
Simulation time 96603627967 ps
CPU time 93.14 seconds
Started Feb 25 01:47:28 PM PST 24
Finished Feb 25 01:49:02 PM PST 24
Peak memory 190948 kb
Host smart-80cd64ea-3b31-4215-becc-9dc87e0f9d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726458459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.726458459
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.483942239
Short name T408
Test name
Test status
Simulation time 35518825 ps
CPU time 0.57 seconds
Started Feb 25 01:47:28 PM PST 24
Finished Feb 25 01:47:30 PM PST 24
Peak memory 182456 kb
Host smart-ebd195dd-5cc1-4f8e-8e83-f0f9b04f9e11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483942239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
483942239
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.1898435828
Short name T15
Test name
Test status
Simulation time 91368284168 ps
CPU time 902.76 seconds
Started Feb 25 01:47:30 PM PST 24
Finished Feb 25 02:02:33 PM PST 24
Peak memory 210636 kb
Host smart-7260457a-1681-41cf-94b9-48f109224c72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898435828 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.1898435828
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2586538411
Short name T307
Test name
Test status
Simulation time 217779576751 ps
CPU time 358.77 seconds
Started Feb 25 01:47:32 PM PST 24
Finished Feb 25 01:53:31 PM PST 24
Peak memory 182764 kb
Host smart-69e2c00b-a58a-4efc-b7cf-8fad3cd932b1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586538411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2586538411
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1073598560
Short name T381
Test name
Test status
Simulation time 103427966972 ps
CPU time 69.12 seconds
Started Feb 25 01:47:28 PM PST 24
Finished Feb 25 01:48:38 PM PST 24
Peak memory 182752 kb
Host smart-b45f4f34-3742-4537-87a7-94fe87c020f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073598560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1073598560
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.1250266947
Short name T43
Test name
Test status
Simulation time 127550890 ps
CPU time 1.01 seconds
Started Feb 25 01:47:29 PM PST 24
Finished Feb 25 01:47:31 PM PST 24
Peak memory 191964 kb
Host smart-f43f62b2-6c2c-40d3-9bc6-48e59b320275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250266947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1250266947
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1848326801
Short name T270
Test name
Test status
Simulation time 333614940794 ps
CPU time 421.89 seconds
Started Feb 25 01:47:31 PM PST 24
Finished Feb 25 01:54:33 PM PST 24
Peak memory 182772 kb
Host smart-75f24a9b-28ec-4d15-aa6b-e5e572e7e674
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848326801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.1848326801
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.159695090
Short name T419
Test name
Test status
Simulation time 167438311243 ps
CPU time 63.01 seconds
Started Feb 25 01:47:32 PM PST 24
Finished Feb 25 01:48:35 PM PST 24
Peak memory 182768 kb
Host smart-d56a1378-a7fb-4386-ab78-6704ac4a0c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159695090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.159695090
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.4225741137
Short name T452
Test name
Test status
Simulation time 13624194328 ps
CPU time 282.18 seconds
Started Feb 25 01:47:32 PM PST 24
Finished Feb 25 01:52:14 PM PST 24
Peak memory 182708 kb
Host smart-8b8093d5-7a18-459a-a434-748cb079368f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225741137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.4225741137
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3697950413
Short name T395
Test name
Test status
Simulation time 20174118 ps
CPU time 0.62 seconds
Started Feb 25 01:47:25 PM PST 24
Finished Feb 25 01:47:27 PM PST 24
Peak memory 182460 kb
Host smart-bf18b476-2905-4257-b2a6-3b8bad5598be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697950413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3697950413
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.2963811151
Short name T38
Test name
Test status
Simulation time 44920775684 ps
CPU time 346.07 seconds
Started Feb 25 01:47:30 PM PST 24
Finished Feb 25 01:53:16 PM PST 24
Peak memory 205712 kb
Host smart-f12f414e-3c67-4546-a40d-9c053c68d257
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963811151 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.2963811151
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2431546312
Short name T248
Test name
Test status
Simulation time 1800730651026 ps
CPU time 912.72 seconds
Started Feb 25 01:47:32 PM PST 24
Finished Feb 25 02:02:45 PM PST 24
Peak memory 182768 kb
Host smart-18c15284-2505-4a26-a4bb-f1ceb51f0e93
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431546312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2431546312
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3087427854
Short name T428
Test name
Test status
Simulation time 139013303185 ps
CPU time 124.4 seconds
Started Feb 25 01:47:30 PM PST 24
Finished Feb 25 01:49:35 PM PST 24
Peak memory 182748 kb
Host smart-a4fbd3d1-bf0b-40d1-ba87-f85b55e5df4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087427854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3087427854
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.2497591445
Short name T355
Test name
Test status
Simulation time 48888471471 ps
CPU time 337.53 seconds
Started Feb 25 01:47:28 PM PST 24
Finished Feb 25 01:53:07 PM PST 24
Peak memory 182668 kb
Host smart-c3a82c8c-0e2f-41b4-bcbf-95b7eeee6587
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497591445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2497591445
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2644817071
Short name T435
Test name
Test status
Simulation time 5863320972 ps
CPU time 12.78 seconds
Started Feb 25 01:47:31 PM PST 24
Finished Feb 25 01:47:44 PM PST 24
Peak memory 190948 kb
Host smart-3745af26-8f21-4233-9c23-630c31d77d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644817071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2644817071
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3339056111
Short name T171
Test name
Test status
Simulation time 552415079655 ps
CPU time 1134.77 seconds
Started Feb 25 01:47:27 PM PST 24
Finished Feb 25 02:06:24 PM PST 24
Peak memory 190972 kb
Host smart-1f0f139f-9449-4233-a379-6f7cd1f310f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339056111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3339056111
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1355276020
Short name T154
Test name
Test status
Simulation time 424861372474 ps
CPU time 776.61 seconds
Started Feb 25 01:47:34 PM PST 24
Finished Feb 25 02:00:31 PM PST 24
Peak memory 182596 kb
Host smart-da2ef73c-987a-452f-81f1-8cc4b29096f0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355276020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.1355276020
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3559168140
Short name T389
Test name
Test status
Simulation time 517344373281 ps
CPU time 212.16 seconds
Started Feb 25 01:47:28 PM PST 24
Finished Feb 25 01:51:02 PM PST 24
Peak memory 182748 kb
Host smart-067b7012-a219-4e70-98be-0dc86241e837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559168140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3559168140
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.1386348268
Short name T251
Test name
Test status
Simulation time 2004579156664 ps
CPU time 910.68 seconds
Started Feb 25 01:47:30 PM PST 24
Finished Feb 25 02:02:41 PM PST 24
Peak memory 194508 kb
Host smart-1651923e-0c6e-43f0-822f-5617c37a1377
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386348268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1386348268
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3610108598
Short name T349
Test name
Test status
Simulation time 173384373633 ps
CPU time 1773.9 seconds
Started Feb 25 01:47:32 PM PST 24
Finished Feb 25 02:17:06 PM PST 24
Peak memory 193780 kb
Host smart-a8b944b7-70f9-4967-a65b-4b75383af5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610108598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3610108598
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2885465204
Short name T247
Test name
Test status
Simulation time 44262064660 ps
CPU time 25.37 seconds
Started Feb 25 01:47:29 PM PST 24
Finished Feb 25 01:47:55 PM PST 24
Peak memory 182768 kb
Host smart-20cb7445-5700-415e-8375-b5a54ba47940
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885465204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2885465204
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3823998925
Short name T385
Test name
Test status
Simulation time 285508350596 ps
CPU time 57.46 seconds
Started Feb 25 01:47:31 PM PST 24
Finished Feb 25 01:48:29 PM PST 24
Peak memory 182752 kb
Host smart-fa960e76-dfb6-4bc7-a9f1-a9d5a64d4c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823998925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3823998925
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.3190437266
Short name T144
Test name
Test status
Simulation time 125304077420 ps
CPU time 433.04 seconds
Started Feb 25 01:47:29 PM PST 24
Finished Feb 25 01:54:43 PM PST 24
Peak memory 190940 kb
Host smart-0ed7365a-eae7-4565-9665-87803925b6c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190437266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3190437266
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.3279799688
Short name T396
Test name
Test status
Simulation time 32643150830 ps
CPU time 15.12 seconds
Started Feb 25 01:47:26 PM PST 24
Finished Feb 25 01:47:43 PM PST 24
Peak memory 182748 kb
Host smart-e01b7467-9dbe-4032-92f3-030df751bf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279799688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3279799688
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1714338509
Short name T406
Test name
Test status
Simulation time 659786928907 ps
CPU time 513.54 seconds
Started Feb 25 01:47:28 PM PST 24
Finished Feb 25 01:56:03 PM PST 24
Peak memory 191000 kb
Host smart-0d6d096a-c026-48ab-92da-66ce58b2cc66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714338509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1714338509
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.3220019667
Short name T11
Test name
Test status
Simulation time 14908793730 ps
CPU time 73.51 seconds
Started Feb 25 01:47:30 PM PST 24
Finished Feb 25 01:48:44 PM PST 24
Peak memory 194584 kb
Host smart-f0996c2c-66b8-4b3b-b3f9-31eb6f7988a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220019667 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.3220019667
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1957828771
Short name T316
Test name
Test status
Simulation time 394177460891 ps
CPU time 583.44 seconds
Started Feb 25 01:47:32 PM PST 24
Finished Feb 25 01:57:15 PM PST 24
Peak memory 181860 kb
Host smart-bbd6dc5b-85c5-40e0-876d-a780cd3cf2e1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957828771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1957828771
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.2300748896
Short name T369
Test name
Test status
Simulation time 262689188089 ps
CPU time 112.48 seconds
Started Feb 25 01:47:27 PM PST 24
Finished Feb 25 01:49:21 PM PST 24
Peak memory 182752 kb
Host smart-97bc497b-da90-401f-98c2-33d9aaeba328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300748896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2300748896
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.1485235539
Short name T80
Test name
Test status
Simulation time 178451782007 ps
CPU time 84.64 seconds
Started Feb 25 01:47:27 PM PST 24
Finished Feb 25 01:48:54 PM PST 24
Peak memory 182744 kb
Host smart-3f057a96-c177-41da-97b8-49b9b260b3db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485235539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1485235539
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2433584919
Short name T73
Test name
Test status
Simulation time 415636079959 ps
CPU time 318.81 seconds
Started Feb 25 01:47:35 PM PST 24
Finished Feb 25 01:52:54 PM PST 24
Peak memory 190964 kb
Host smart-bb88da25-2072-442f-baef-5bfb4a7a8d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433584919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2433584919
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.799295147
Short name T64
Test name
Test status
Simulation time 15499402577 ps
CPU time 29.39 seconds
Started Feb 25 01:47:43 PM PST 24
Finished Feb 25 01:48:13 PM PST 24
Peak memory 182764 kb
Host smart-c6413639-110e-41bc-8d46-26178fd22d99
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799295147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.799295147
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.257316647
Short name T393
Test name
Test status
Simulation time 122704977706 ps
CPU time 49.72 seconds
Started Feb 25 01:47:41 PM PST 24
Finished Feb 25 01:48:30 PM PST 24
Peak memory 181604 kb
Host smart-57d9d688-a4e9-474c-aa6c-3bdcbbf78f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257316647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.257316647
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.3699440895
Short name T439
Test name
Test status
Simulation time 4740997632 ps
CPU time 5.14 seconds
Started Feb 25 01:47:39 PM PST 24
Finished Feb 25 01:47:44 PM PST 24
Peak memory 190980 kb
Host smart-cade8c81-54bf-43c7-99a4-0658a05e7b29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699440895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3699440895
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.4119037293
Short name T448
Test name
Test status
Simulation time 24264836900 ps
CPU time 39.3 seconds
Started Feb 25 01:47:43 PM PST 24
Finished Feb 25 01:48:23 PM PST 24
Peak memory 190860 kb
Host smart-13174da4-df36-42a4-b1de-c40caf058816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119037293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.4119037293
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3017009065
Short name T455
Test name
Test status
Simulation time 466758040949 ps
CPU time 194.44 seconds
Started Feb 25 01:47:40 PM PST 24
Finished Feb 25 01:50:54 PM PST 24
Peak memory 182772 kb
Host smart-1a4ce8f7-0c32-4192-9c2e-5535599cb3a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017009065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3017009065
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2933587306
Short name T401
Test name
Test status
Simulation time 183705810445 ps
CPU time 69.33 seconds
Started Feb 25 01:47:36 PM PST 24
Finished Feb 25 01:48:45 PM PST 24
Peak memory 182692 kb
Host smart-81cd2ec0-94e9-4772-a1b6-e04a32402181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933587306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2933587306
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2446904824
Short name T288
Test name
Test status
Simulation time 122770323951 ps
CPU time 192.31 seconds
Started Feb 25 01:47:39 PM PST 24
Finished Feb 25 01:50:52 PM PST 24
Peak memory 190960 kb
Host smart-cdf75e79-81f3-48e5-a08f-d33118fe7d9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446904824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2446904824
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.515155278
Short name T277
Test name
Test status
Simulation time 51693550915 ps
CPU time 94.71 seconds
Started Feb 25 01:47:48 PM PST 24
Finished Feb 25 01:49:22 PM PST 24
Peak memory 194352 kb
Host smart-96ab2414-3255-4dce-a625-4f95d6b3c3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515155278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.515155278
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.2026782512
Short name T39
Test name
Test status
Simulation time 10738907193 ps
CPU time 61.86 seconds
Started Feb 25 01:47:40 PM PST 24
Finished Feb 25 01:48:42 PM PST 24
Peak memory 197384 kb
Host smart-eea99dbe-5419-43eb-94b5-bad6dfd0fc40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026782512 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.2026782512
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2370360102
Short name T174
Test name
Test status
Simulation time 14445899388 ps
CPU time 26.33 seconds
Started Feb 25 01:47:41 PM PST 24
Finished Feb 25 01:48:07 PM PST 24
Peak memory 182768 kb
Host smart-0fb2b26a-bbc1-4dd2-932f-d87adf1c57cb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370360102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2370360102
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.2931937730
Short name T373
Test name
Test status
Simulation time 58493067387 ps
CPU time 45.51 seconds
Started Feb 25 01:47:41 PM PST 24
Finished Feb 25 01:48:26 PM PST 24
Peak memory 181620 kb
Host smart-5a7ffdaa-bbcf-4c7d-a01e-a264bedd7d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931937730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.2931937730
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.3164703500
Short name T442
Test name
Test status
Simulation time 164463116978 ps
CPU time 73.71 seconds
Started Feb 25 01:47:39 PM PST 24
Finished Feb 25 01:48:53 PM PST 24
Peak memory 182748 kb
Host smart-2cc65bc8-f463-4c57-ab50-1cf2da03ac65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164703500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3164703500
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.2273513766
Short name T417
Test name
Test status
Simulation time 4149897946 ps
CPU time 8.97 seconds
Started Feb 25 01:47:42 PM PST 24
Finished Feb 25 01:47:51 PM PST 24
Peak memory 182740 kb
Host smart-f05cef3f-3cab-4c06-b14c-7ff6fe60eb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273513766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2273513766
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.4087025783
Short name T35
Test name
Test status
Simulation time 68215447546 ps
CPU time 60.6 seconds
Started Feb 25 01:47:38 PM PST 24
Finished Feb 25 01:48:39 PM PST 24
Peak memory 190916 kb
Host smart-34f0c314-d859-4af5-91cf-6d205b05ea29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087025783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.4087025783
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1329029771
Short name T291
Test name
Test status
Simulation time 356294555468 ps
CPU time 643.57 seconds
Started Feb 25 01:47:11 PM PST 24
Finished Feb 25 01:57:54 PM PST 24
Peak memory 182724 kb
Host smart-2d59fece-60a5-4736-b155-95c14762b8b5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329029771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1329029771
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.364020315
Short name T398
Test name
Test status
Simulation time 85547157594 ps
CPU time 31.53 seconds
Started Feb 25 01:47:00 PM PST 24
Finished Feb 25 01:47:31 PM PST 24
Peak memory 182760 kb
Host smart-6551602f-b0e5-4b2c-a739-9b78c508cfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364020315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.364020315
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.453350157
Short name T420
Test name
Test status
Simulation time 36428132663 ps
CPU time 63.19 seconds
Started Feb 25 01:47:02 PM PST 24
Finished Feb 25 01:48:05 PM PST 24
Peak memory 182752 kb
Host smart-7416a036-c754-4a9d-983c-b598c739a62d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453350157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.453350157
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1358270381
Short name T407
Test name
Test status
Simulation time 394851380 ps
CPU time 0.57 seconds
Started Feb 25 01:47:21 PM PST 24
Finished Feb 25 01:47:23 PM PST 24
Peak memory 181916 kb
Host smart-cad281a0-a468-4ed0-941d-65a1dccbbf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358270381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1358270381
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.154557308
Short name T20
Test name
Test status
Simulation time 1631914768 ps
CPU time 1.11 seconds
Started Feb 25 01:47:10 PM PST 24
Finished Feb 25 01:47:11 PM PST 24
Peak memory 212852 kb
Host smart-a793005c-49f4-42b4-8146-b29f0649a9a2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154557308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.154557308
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.2891991470
Short name T72
Test name
Test status
Simulation time 519096583933 ps
CPU time 210.8 seconds
Started Feb 25 01:47:09 PM PST 24
Finished Feb 25 01:50:40 PM PST 24
Peak memory 195244 kb
Host smart-d3b33fe8-8713-4dc7-afc0-712a77271e01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891991470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
2891991470
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.3590304020
Short name T51
Test name
Test status
Simulation time 27506585927 ps
CPU time 183.84 seconds
Started Feb 25 01:47:09 PM PST 24
Finished Feb 25 01:50:14 PM PST 24
Peak memory 197504 kb
Host smart-56aee38b-4366-4436-aca9-4558b50c4e40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590304020 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.3590304020
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3365975393
Short name T334
Test name
Test status
Simulation time 581603201152 ps
CPU time 285.09 seconds
Started Feb 25 01:47:43 PM PST 24
Finished Feb 25 01:52:28 PM PST 24
Peak memory 182772 kb
Host smart-a1f66c5e-ed53-41e2-8444-d9027ae10c85
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365975393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3365975393
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2269851797
Short name T415
Test name
Test status
Simulation time 211236451199 ps
CPU time 45.81 seconds
Started Feb 25 01:47:39 PM PST 24
Finished Feb 25 01:48:25 PM PST 24
Peak memory 182804 kb
Host smart-247d9834-ed6c-4d6d-b5ba-e827bab6347f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269851797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2269851797
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.1718308786
Short name T180
Test name
Test status
Simulation time 986280684230 ps
CPU time 472.13 seconds
Started Feb 25 01:48:01 PM PST 24
Finished Feb 25 01:55:54 PM PST 24
Peak memory 190940 kb
Host smart-6152ae03-8a00-4ccf-b5aa-e66455a926cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718308786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1718308786
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.2098428533
Short name T7
Test name
Test status
Simulation time 146511668577 ps
CPU time 495.81 seconds
Started Feb 25 01:48:01 PM PST 24
Finished Feb 25 01:56:17 PM PST 24
Peak memory 190940 kb
Host smart-c8f33421-d92e-4fb5-9614-07e9756bbe60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098428533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.2098428533
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2441551267
Short name T169
Test name
Test status
Simulation time 1338472769618 ps
CPU time 594.8 seconds
Started Feb 25 01:47:37 PM PST 24
Finished Feb 25 01:57:32 PM PST 24
Peak memory 182764 kb
Host smart-54aa9b86-f195-4040-b26d-fb8c07146da4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441551267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2441551267
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.299869196
Short name T124
Test name
Test status
Simulation time 52147929243 ps
CPU time 296.7 seconds
Started Feb 25 01:47:32 PM PST 24
Finished Feb 25 01:52:29 PM PST 24
Peak memory 197476 kb
Host smart-fb6e3c1c-4ec6-4528-9acd-62329e2f40e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299869196 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.299869196
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1064406316
Short name T299
Test name
Test status
Simulation time 1012539863797 ps
CPU time 296.37 seconds
Started Feb 25 01:47:43 PM PST 24
Finished Feb 25 01:52:40 PM PST 24
Peak memory 182776 kb
Host smart-01318221-3171-44d1-837d-a9ce69349c1c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064406316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1064406316
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.652682211
Short name T371
Test name
Test status
Simulation time 393773996057 ps
CPU time 267.23 seconds
Started Feb 25 01:47:38 PM PST 24
Finished Feb 25 01:52:05 PM PST 24
Peak memory 182712 kb
Host smart-50942e40-9b7a-4ba8-a632-e155d5f7135e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652682211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.652682211
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.243524716
Short name T206
Test name
Test status
Simulation time 157327928596 ps
CPU time 119.14 seconds
Started Feb 25 01:47:49 PM PST 24
Finished Feb 25 01:49:48 PM PST 24
Peak memory 190776 kb
Host smart-d8261755-7903-4a4e-a84d-b1a65770deac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243524716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.243524716
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3341794959
Short name T12
Test name
Test status
Simulation time 42502171 ps
CPU time 0.61 seconds
Started Feb 25 01:47:45 PM PST 24
Finished Feb 25 01:47:46 PM PST 24
Peak memory 182420 kb
Host smart-41e003ca-35e5-4495-88e1-458c833b47fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341794959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3341794959
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.623487920
Short name T348
Test name
Test status
Simulation time 695405526855 ps
CPU time 613.01 seconds
Started Feb 25 01:48:01 PM PST 24
Finished Feb 25 01:58:15 PM PST 24
Peak memory 182740 kb
Host smart-ef4fa435-d63b-416d-a60f-e9ab3a8aca0e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623487920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.623487920
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2573403555
Short name T392
Test name
Test status
Simulation time 109260642380 ps
CPU time 155.67 seconds
Started Feb 25 01:47:46 PM PST 24
Finished Feb 25 01:50:22 PM PST 24
Peak memory 182752 kb
Host smart-da9334a4-1765-4ff2-a3cd-2578465504ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573403555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2573403555
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.369687096
Short name T44
Test name
Test status
Simulation time 52321564354 ps
CPU time 91.92 seconds
Started Feb 25 01:47:38 PM PST 24
Finished Feb 25 01:49:10 PM PST 24
Peak memory 190976 kb
Host smart-34307db5-1443-4f5e-8a2f-3138b653079f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369687096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.369687096
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2299090482
Short name T423
Test name
Test status
Simulation time 16948806721 ps
CPU time 28.55 seconds
Started Feb 25 01:47:42 PM PST 24
Finished Feb 25 01:48:10 PM PST 24
Peak memory 190952 kb
Host smart-62a93779-16ec-4989-98f5-5788cdd72f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299090482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2299090482
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1710302161
Short name T354
Test name
Test status
Simulation time 102460092311 ps
CPU time 158.74 seconds
Started Feb 25 01:47:39 PM PST 24
Finished Feb 25 01:50:18 PM PST 24
Peak memory 190960 kb
Host smart-32ac2a5c-8814-4f56-b2b8-ee8839ac0690
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710302161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1710302161
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.4284817667
Short name T217
Test name
Test status
Simulation time 262763144460 ps
CPU time 464.9 seconds
Started Feb 25 01:47:42 PM PST 24
Finished Feb 25 01:55:27 PM PST 24
Peak memory 182784 kb
Host smart-74c4df6a-157a-49e6-889f-079764a3a940
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284817667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.4284817667
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.4089105070
Short name T25
Test name
Test status
Simulation time 107643785835 ps
CPU time 173.91 seconds
Started Feb 25 01:47:46 PM PST 24
Finished Feb 25 01:50:40 PM PST 24
Peak memory 182752 kb
Host smart-85e456f3-0870-4135-b9d1-879437412b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089105070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.4089105070
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.2049289473
Short name T45
Test name
Test status
Simulation time 41943498825 ps
CPU time 69.77 seconds
Started Feb 25 01:47:46 PM PST 24
Finished Feb 25 01:48:56 PM PST 24
Peak memory 190948 kb
Host smart-0ba1c33c-d594-494b-ab4c-ee343464e985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049289473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2049289473
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.4153239834
Short name T376
Test name
Test status
Simulation time 844461706575 ps
CPU time 403.8 seconds
Started Feb 25 01:48:01 PM PST 24
Finished Feb 25 01:54:46 PM PST 24
Peak memory 190948 kb
Host smart-1b92ec4f-4b88-463e-a34c-f01a8b0008c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153239834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.4153239834
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.4213698435
Short name T272
Test name
Test status
Simulation time 677659896179 ps
CPU time 1228.84 seconds
Started Feb 25 01:47:40 PM PST 24
Finished Feb 25 02:08:09 PM PST 24
Peak memory 182696 kb
Host smart-a244dc88-d645-4fa8-85c5-d031d7f9a905
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213698435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.4213698435
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.1064362266
Short name T450
Test name
Test status
Simulation time 410617653905 ps
CPU time 88.47 seconds
Started Feb 25 01:48:00 PM PST 24
Finished Feb 25 01:49:30 PM PST 24
Peak memory 182740 kb
Host smart-01b1907a-14cc-4922-9cb8-44321e1c7b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064362266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1064362266
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1865092935
Short name T235
Test name
Test status
Simulation time 1861465459271 ps
CPU time 300.47 seconds
Started Feb 25 01:47:39 PM PST 24
Finished Feb 25 01:52:40 PM PST 24
Peak memory 190972 kb
Host smart-60ed4f20-00d3-41e3-a29a-6553eb2dfe51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865092935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1865092935
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3768116727
Short name T315
Test name
Test status
Simulation time 150806396144 ps
CPU time 1164.37 seconds
Started Feb 25 01:48:01 PM PST 24
Finished Feb 25 02:07:26 PM PST 24
Peak memory 182728 kb
Host smart-ec72d05e-9845-4171-aa55-87575dffcf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768116727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3768116727
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1720106922
Short name T380
Test name
Test status
Simulation time 225169188785 ps
CPU time 192.51 seconds
Started Feb 25 01:47:42 PM PST 24
Finished Feb 25 01:50:55 PM PST 24
Peak memory 190972 kb
Host smart-4ab36cc0-b2a5-4c6c-9537-7d5feeb9e4a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720106922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1720106922
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.4077513553
Short name T224
Test name
Test status
Simulation time 75859909825 ps
CPU time 145.41 seconds
Started Feb 25 01:47:41 PM PST 24
Finished Feb 25 01:50:06 PM PST 24
Peak memory 182784 kb
Host smart-130f646b-b3d3-4a5f-9707-986f5a469919
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077513553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.4077513553
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2098103487
Short name T402
Test name
Test status
Simulation time 68982565005 ps
CPU time 49.75 seconds
Started Feb 25 01:47:42 PM PST 24
Finished Feb 25 01:48:31 PM PST 24
Peak memory 182756 kb
Host smart-94914796-d498-40c7-aab6-90ec73ba2a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098103487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2098103487
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.2950612311
Short name T189
Test name
Test status
Simulation time 335052865901 ps
CPU time 1325.6 seconds
Started Feb 25 01:47:46 PM PST 24
Finished Feb 25 02:09:52 PM PST 24
Peak memory 190956 kb
Host smart-0323f39c-1f83-4d14-814a-f2cd94bb9f17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950612311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2950612311
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2719684878
Short name T340
Test name
Test status
Simulation time 45051515577 ps
CPU time 77.36 seconds
Started Feb 25 01:47:41 PM PST 24
Finished Feb 25 01:48:58 PM PST 24
Peak memory 182744 kb
Host smart-eb0cb0e5-907c-45ec-896b-771a448550ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719684878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2719684878
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2469597595
Short name T352
Test name
Test status
Simulation time 1160574795005 ps
CPU time 1043.3 seconds
Started Feb 25 01:47:46 PM PST 24
Finished Feb 25 02:05:09 PM PST 24
Peak memory 190952 kb
Host smart-a25de568-9e01-4ecb-bdd3-80fbc7f0f11d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469597595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2469597595
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.775842632
Short name T199
Test name
Test status
Simulation time 619509413733 ps
CPU time 362.56 seconds
Started Feb 25 01:47:50 PM PST 24
Finished Feb 25 01:53:53 PM PST 24
Peak memory 182776 kb
Host smart-579abce7-14f7-483d-83e5-925b1a3ee331
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775842632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.775842632
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.4163344889
Short name T412
Test name
Test status
Simulation time 99327713152 ps
CPU time 152.68 seconds
Started Feb 25 01:47:42 PM PST 24
Finished Feb 25 01:50:15 PM PST 24
Peak memory 182756 kb
Host smart-4e0046d6-b9ee-4611-8728-efafa2ea92cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163344889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.4163344889
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.1182020200
Short name T319
Test name
Test status
Simulation time 108603287681 ps
CPU time 450.29 seconds
Started Feb 25 01:47:41 PM PST 24
Finished Feb 25 01:55:11 PM PST 24
Peak memory 190960 kb
Host smart-e5d96366-32bc-435e-ba8f-3997f068322c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182020200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1182020200
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3591709227
Short name T378
Test name
Test status
Simulation time 654952936463 ps
CPU time 221.82 seconds
Started Feb 25 01:47:57 PM PST 24
Finished Feb 25 01:51:39 PM PST 24
Peak memory 190940 kb
Host smart-63c03d95-0b0c-472d-967f-bcd693154774
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591709227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3591709227
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2081530550
Short name T362
Test name
Test status
Simulation time 16404446498 ps
CPU time 20.75 seconds
Started Feb 25 01:47:53 PM PST 24
Finished Feb 25 01:48:14 PM PST 24
Peak memory 182784 kb
Host smart-f43a0f84-3ecc-429b-a911-003c82b7714f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081530550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2081530550
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.1460610927
Short name T27
Test name
Test status
Simulation time 262023794519 ps
CPU time 80.67 seconds
Started Feb 25 01:47:50 PM PST 24
Finished Feb 25 01:49:11 PM PST 24
Peak memory 182732 kb
Host smart-073252fa-ee3f-4b44-81fd-2da6e32cfe7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460610927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.1460610927
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.4166301914
Short name T222
Test name
Test status
Simulation time 417814856380 ps
CPU time 407.7 seconds
Started Feb 25 01:47:49 PM PST 24
Finished Feb 25 01:54:37 PM PST 24
Peak memory 190948 kb
Host smart-1815c006-f0a9-4169-abbe-8fca76478cd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166301914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.4166301914
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2741961993
Short name T246
Test name
Test status
Simulation time 129557790276 ps
CPU time 294.19 seconds
Started Feb 25 01:47:57 PM PST 24
Finished Feb 25 01:52:51 PM PST 24
Peak memory 190956 kb
Host smart-a0e6a35a-aaf7-4a6f-aa25-5645d9b78ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741961993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2741961993
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3610120037
Short name T339
Test name
Test status
Simulation time 415188687872 ps
CPU time 520.55 seconds
Started Feb 25 01:48:08 PM PST 24
Finished Feb 25 01:56:49 PM PST 24
Peak memory 190936 kb
Host smart-faa2f889-02e0-48bd-af78-f62a62fdd6aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610120037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3610120037
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3364467121
Short name T285
Test name
Test status
Simulation time 11660097511 ps
CPU time 20.4 seconds
Started Feb 25 01:47:49 PM PST 24
Finished Feb 25 01:48:10 PM PST 24
Peak memory 182760 kb
Host smart-1d2a93a4-7a5c-492c-85e1-3f8ecdd9d5c0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364467121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3364467121
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1700785106
Short name T123
Test name
Test status
Simulation time 103091556720 ps
CPU time 151.59 seconds
Started Feb 25 01:47:52 PM PST 24
Finished Feb 25 01:50:24 PM PST 24
Peak memory 182784 kb
Host smart-5f712a55-7ca1-4628-8f06-e8ceb3cf36ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700785106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1700785106
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.3930909178
Short name T259
Test name
Test status
Simulation time 170796030440 ps
CPU time 652.2 seconds
Started Feb 25 01:47:59 PM PST 24
Finished Feb 25 01:58:51 PM PST 24
Peak memory 190948 kb
Host smart-eaf120d4-7fb5-4e77-bba5-485d0860d280
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930909178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3930909178
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3082300868
Short name T210
Test name
Test status
Simulation time 51456563193 ps
CPU time 93.77 seconds
Started Feb 25 01:47:52 PM PST 24
Finished Feb 25 01:49:26 PM PST 24
Peak memory 190896 kb
Host smart-bad31598-a3dd-4b78-8201-dfcc9378b6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082300868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3082300868
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.4163160834
Short name T40
Test name
Test status
Simulation time 21411623239 ps
CPU time 171.61 seconds
Started Feb 25 01:47:59 PM PST 24
Finished Feb 25 01:50:51 PM PST 24
Peak memory 197508 kb
Host smart-40193d13-194b-48f7-9dbb-f50a2f992d1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163160834 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.4163160834
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3073825156
Short name T61
Test name
Test status
Simulation time 68710584672 ps
CPU time 122.39 seconds
Started Feb 25 01:48:08 PM PST 24
Finished Feb 25 01:50:11 PM PST 24
Peak memory 182700 kb
Host smart-7fe78eab-0090-4581-a1f4-ce80b8c660d1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073825156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3073825156
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3589103915
Short name T394
Test name
Test status
Simulation time 114862100579 ps
CPU time 195.66 seconds
Started Feb 25 01:47:48 PM PST 24
Finished Feb 25 01:51:04 PM PST 24
Peak memory 182756 kb
Host smart-0662d1d3-be26-4b79-ab65-4488364c2a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589103915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3589103915
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.1052508522
Short name T431
Test name
Test status
Simulation time 50261627621 ps
CPU time 79.25 seconds
Started Feb 25 01:47:51 PM PST 24
Finished Feb 25 01:49:10 PM PST 24
Peak memory 182760 kb
Host smart-46d4e6a9-b7df-493a-b18b-14e5bfd114d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052508522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1052508522
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3522391824
Short name T335
Test name
Test status
Simulation time 35369140573 ps
CPU time 44.36 seconds
Started Feb 25 01:48:08 PM PST 24
Finished Feb 25 01:48:53 PM PST 24
Peak memory 182760 kb
Host smart-5a26de24-9913-4f25-8057-6cd982886418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522391824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3522391824
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.2493595486
Short name T322
Test name
Test status
Simulation time 692232365614 ps
CPU time 634.15 seconds
Started Feb 25 01:48:08 PM PST 24
Finished Feb 25 01:58:42 PM PST 24
Peak memory 191008 kb
Host smart-57590b69-ded3-4985-8166-c08aa81aa83b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493595486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.2493595486
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.182761653
Short name T432
Test name
Test status
Simulation time 10476449255 ps
CPU time 18.3 seconds
Started Feb 25 01:47:17 PM PST 24
Finished Feb 25 01:47:35 PM PST 24
Peak memory 182764 kb
Host smart-4fb6bde0-d09f-49d3-b2bf-fdf54a54fb00
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182761653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.rv_timer_cfg_update_on_fly.182761653
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1772728020
Short name T390
Test name
Test status
Simulation time 578339442558 ps
CPU time 214.99 seconds
Started Feb 25 01:47:13 PM PST 24
Finished Feb 25 01:50:49 PM PST 24
Peak memory 182756 kb
Host smart-3c90f893-e1c1-4343-a333-b7e02ac6530f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772728020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1772728020
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.610001673
Short name T234
Test name
Test status
Simulation time 882938091836 ps
CPU time 298.74 seconds
Started Feb 25 01:47:18 PM PST 24
Finished Feb 25 01:52:17 PM PST 24
Peak memory 190952 kb
Host smart-e7e27148-4c7b-43f3-b00e-df12358ff230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610001673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.610001673
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.686089461
Short name T282
Test name
Test status
Simulation time 83703847269 ps
CPU time 152.54 seconds
Started Feb 25 01:47:16 PM PST 24
Finished Feb 25 01:49:48 PM PST 24
Peak memory 182764 kb
Host smart-93191afd-9e76-46da-ab5b-2e9895809ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686089461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.686089461
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1532220022
Short name T429
Test name
Test status
Simulation time 390101762360 ps
CPU time 270.75 seconds
Started Feb 25 01:47:16 PM PST 24
Finished Feb 25 01:51:47 PM PST 24
Peak memory 182748 kb
Host smart-87e2f813-c158-4901-9c37-73beb05223f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532220022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1532220022
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.3244255179
Short name T153
Test name
Test status
Simulation time 1274622037030 ps
CPU time 1064.73 seconds
Started Feb 25 01:47:55 PM PST 24
Finished Feb 25 02:05:40 PM PST 24
Peak memory 194080 kb
Host smart-fd8c335d-8d7d-4170-8f8d-ee0ea874bdca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244255179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3244255179
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.2608659190
Short name T131
Test name
Test status
Simulation time 262211817083 ps
CPU time 354.46 seconds
Started Feb 25 01:47:52 PM PST 24
Finished Feb 25 01:53:47 PM PST 24
Peak memory 193640 kb
Host smart-b8730389-9cc3-445e-9568-c1659be02362
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608659190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2608659190
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.900792387
Short name T50
Test name
Test status
Simulation time 166126591252 ps
CPU time 751.44 seconds
Started Feb 25 01:47:50 PM PST 24
Finished Feb 25 02:00:22 PM PST 24
Peak memory 190968 kb
Host smart-c38cdc3d-a763-4152-9860-cf775e4384e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900792387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.900792387
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.2896680483
Short name T345
Test name
Test status
Simulation time 179820106354 ps
CPU time 176.36 seconds
Started Feb 25 01:47:51 PM PST 24
Finished Feb 25 01:50:48 PM PST 24
Peak memory 190960 kb
Host smart-c795c480-cba3-47bd-9ed7-3ed7d25fa459
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896680483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2896680483
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.352341355
Short name T213
Test name
Test status
Simulation time 242141521914 ps
CPU time 393.33 seconds
Started Feb 25 01:47:51 PM PST 24
Finished Feb 25 01:54:24 PM PST 24
Peak memory 190912 kb
Host smart-91c66a4c-d8a7-4aed-bfc4-61b99ac3e181
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352341355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.352341355
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.4078482541
Short name T146
Test name
Test status
Simulation time 130526363291 ps
CPU time 368.86 seconds
Started Feb 25 01:48:02 PM PST 24
Finished Feb 25 01:54:11 PM PST 24
Peak memory 190896 kb
Host smart-e5692f92-21c5-4fca-877a-7dd6cbab6a23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078482541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.4078482541
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.4111988227
Short name T149
Test name
Test status
Simulation time 215748884253 ps
CPU time 203.78 seconds
Started Feb 25 01:47:54 PM PST 24
Finished Feb 25 01:51:18 PM PST 24
Peak memory 190952 kb
Host smart-1628700a-4bf9-4dc6-841b-12930636343d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111988227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.4111988227
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3666740282
Short name T236
Test name
Test status
Simulation time 409921802090 ps
CPU time 353.69 seconds
Started Feb 25 01:47:20 PM PST 24
Finished Feb 25 01:53:15 PM PST 24
Peak memory 182760 kb
Host smart-823cabc9-41ba-42d4-9990-99b5c59e059d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666740282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.3666740282
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.4217712666
Short name T370
Test name
Test status
Simulation time 160345685834 ps
CPU time 245.66 seconds
Started Feb 25 01:47:09 PM PST 24
Finished Feb 25 01:51:15 PM PST 24
Peak memory 182752 kb
Host smart-78f4ed88-7dd9-4b97-8826-658a8eaa8791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217712666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.4217712666
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2701839378
Short name T327
Test name
Test status
Simulation time 61323839661 ps
CPU time 175.8 seconds
Started Feb 25 01:47:15 PM PST 24
Finished Feb 25 01:50:11 PM PST 24
Peak memory 182740 kb
Host smart-a5681481-294b-48c7-b2d2-66e1495a5c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701839378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2701839378
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.2819116386
Short name T204
Test name
Test status
Simulation time 11812169164 ps
CPU time 266.37 seconds
Started Feb 25 01:48:02 PM PST 24
Finished Feb 25 01:52:29 PM PST 24
Peak memory 190892 kb
Host smart-61d8406b-905f-4365-9550-e1dfdd099b6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819116386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2819116386
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.3831867928
Short name T24
Test name
Test status
Simulation time 336728199070 ps
CPU time 410.98 seconds
Started Feb 25 01:47:51 PM PST 24
Finished Feb 25 01:54:42 PM PST 24
Peak memory 190948 kb
Host smart-547cdc7c-6aaa-4748-a22d-d3f81c517462
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831867928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3831867928
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.683859565
Short name T203
Test name
Test status
Simulation time 108263481299 ps
CPU time 91.52 seconds
Started Feb 25 01:47:58 PM PST 24
Finished Feb 25 01:49:30 PM PST 24
Peak memory 190952 kb
Host smart-caeedda1-3aca-4601-9d64-82f2d9444ec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683859565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.683859565
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.3353370901
Short name T332
Test name
Test status
Simulation time 358304122554 ps
CPU time 226.63 seconds
Started Feb 25 01:47:49 PM PST 24
Finished Feb 25 01:51:36 PM PST 24
Peak memory 190948 kb
Host smart-c3d84e22-965f-4a77-9485-19c08a558a27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353370901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3353370901
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.2598349549
Short name T263
Test name
Test status
Simulation time 145714966038 ps
CPU time 171.75 seconds
Started Feb 25 01:47:52 PM PST 24
Finished Feb 25 01:50:44 PM PST 24
Peak memory 190908 kb
Host smart-a7b76767-d4f2-477f-931e-501c63036c31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598349549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2598349549
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.308159064
Short name T6
Test name
Test status
Simulation time 127466223118 ps
CPU time 259.59 seconds
Started Feb 25 01:47:49 PM PST 24
Finished Feb 25 01:52:09 PM PST 24
Peak memory 190948 kb
Host smart-fc4173bd-66fd-440c-8cd1-03c83cbdafbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308159064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.308159064
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.2732578618
Short name T411
Test name
Test status
Simulation time 76168245774 ps
CPU time 46.49 seconds
Started Feb 25 01:48:02 PM PST 24
Finished Feb 25 01:48:49 PM PST 24
Peak memory 182704 kb
Host smart-78fe9d7e-4c94-479c-a9c1-53709379708a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732578618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2732578618
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.739992354
Short name T86
Test name
Test status
Simulation time 61775565983 ps
CPU time 82.44 seconds
Started Feb 25 01:48:01 PM PST 24
Finished Feb 25 01:49:24 PM PST 24
Peak memory 190896 kb
Host smart-47596784-a504-4980-a4be-0737c1f1921f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739992354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.739992354
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.477769142
Short name T245
Test name
Test status
Simulation time 146824342674 ps
CPU time 334.76 seconds
Started Feb 25 01:48:08 PM PST 24
Finished Feb 25 01:53:43 PM PST 24
Peak memory 190964 kb
Host smart-ae36d35c-f99f-4369-9f6c-94b1b3162a95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477769142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.477769142
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3865973122
Short name T314
Test name
Test status
Simulation time 4368399206 ps
CPU time 7.55 seconds
Started Feb 25 01:47:15 PM PST 24
Finished Feb 25 01:47:23 PM PST 24
Peak memory 182784 kb
Host smart-f8911a92-2e44-41d9-bce2-6c8e7785c0bc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865973122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3865973122
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3096728979
Short name T388
Test name
Test status
Simulation time 441182872901 ps
CPU time 87 seconds
Started Feb 25 01:47:15 PM PST 24
Finished Feb 25 01:48:42 PM PST 24
Peak memory 182752 kb
Host smart-2dcf10a8-f0f5-42a4-8dc1-437d781be5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096728979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3096728979
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.4292142397
Short name T328
Test name
Test status
Simulation time 369919405220 ps
CPU time 1784.03 seconds
Started Feb 25 01:47:14 PM PST 24
Finished Feb 25 02:16:58 PM PST 24
Peak memory 190956 kb
Host smart-618fd990-0636-4342-9662-a2eb3c9b1165
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292142397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.4292142397
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.139370285
Short name T443
Test name
Test status
Simulation time 3423958598 ps
CPU time 5.94 seconds
Started Feb 25 01:47:18 PM PST 24
Finished Feb 25 01:47:24 PM PST 24
Peak memory 182772 kb
Host smart-080b677c-01b3-4817-9620-4dcadd2994d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139370285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.139370285
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1179898052
Short name T336
Test name
Test status
Simulation time 463414046704 ps
CPU time 502.37 seconds
Started Feb 25 01:47:16 PM PST 24
Finished Feb 25 01:55:38 PM PST 24
Peak memory 190940 kb
Host smart-b286573b-1289-4470-ab3e-56ab1592cc96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179898052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1179898052
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/71.rv_timer_random.2328267578
Short name T367
Test name
Test status
Simulation time 83854925995 ps
CPU time 1047.79 seconds
Started Feb 25 01:47:56 PM PST 24
Finished Feb 25 02:05:24 PM PST 24
Peak memory 190960 kb
Host smart-0471f047-7ee4-4199-83c2-9006b3136d63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328267578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2328267578
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.2128923311
Short name T309
Test name
Test status
Simulation time 168842574478 ps
CPU time 1678.42 seconds
Started Feb 25 01:48:02 PM PST 24
Finished Feb 25 02:16:01 PM PST 24
Peak memory 190908 kb
Host smart-ca62e990-0f67-4021-b188-62243f119fc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128923311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2128923311
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.461270025
Short name T297
Test name
Test status
Simulation time 241186785015 ps
CPU time 482.29 seconds
Started Feb 25 01:47:58 PM PST 24
Finished Feb 25 01:56:00 PM PST 24
Peak memory 190968 kb
Host smart-964dacac-0a06-4342-a150-bd5909823d55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461270025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.461270025
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1144355979
Short name T62
Test name
Test status
Simulation time 287989010360 ps
CPU time 279.29 seconds
Started Feb 25 01:47:54 PM PST 24
Finished Feb 25 01:52:34 PM PST 24
Peak memory 190944 kb
Host smart-c655fbcf-5d28-4f67-bcb3-72f4a992110f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144355979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1144355979
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3961607489
Short name T290
Test name
Test status
Simulation time 316732991980 ps
CPU time 215.35 seconds
Started Feb 25 01:47:54 PM PST 24
Finished Feb 25 01:51:30 PM PST 24
Peak memory 190892 kb
Host smart-87adc283-82a7-46af-a934-a0983503e61c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961607489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3961607489
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3946932275
Short name T445
Test name
Test status
Simulation time 424097427102 ps
CPU time 347.58 seconds
Started Feb 25 01:48:02 PM PST 24
Finished Feb 25 01:53:50 PM PST 24
Peak memory 190952 kb
Host smart-dc6dc29e-2563-4e7f-8f4a-f943542e6247
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946932275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3946932275
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.18114725
Short name T286
Test name
Test status
Simulation time 330084462566 ps
CPU time 929.24 seconds
Started Feb 25 01:48:03 PM PST 24
Finished Feb 25 02:03:33 PM PST 24
Peak memory 190956 kb
Host smart-9acddb64-1350-466a-8e7e-7e13a1674943
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18114725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.18114725
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.4042159522
Short name T261
Test name
Test status
Simulation time 95891769585 ps
CPU time 167.08 seconds
Started Feb 25 01:47:15 PM PST 24
Finished Feb 25 01:50:03 PM PST 24
Peak memory 182772 kb
Host smart-f80c500a-5478-4271-a11d-f787bd9205c2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042159522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.4042159522
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3956404101
Short name T454
Test name
Test status
Simulation time 176667704964 ps
CPU time 133.58 seconds
Started Feb 25 01:47:16 PM PST 24
Finished Feb 25 01:49:29 PM PST 24
Peak memory 182752 kb
Host smart-bae4515d-c534-439f-bdd8-8b5040684762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956404101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3956404101
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2797503924
Short name T441
Test name
Test status
Simulation time 187810801780 ps
CPU time 1902.52 seconds
Started Feb 25 01:47:09 PM PST 24
Finished Feb 25 02:18:52 PM PST 24
Peak memory 190972 kb
Host smart-6187297d-d198-46d4-bb89-9b24282ed88f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797503924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2797503924
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.7961046
Short name T312
Test name
Test status
Simulation time 194044650743 ps
CPU time 95.01 seconds
Started Feb 25 01:48:02 PM PST 24
Finished Feb 25 01:49:37 PM PST 24
Peak memory 190968 kb
Host smart-5a9577fe-9123-4d79-be0a-ffc39dd5ac8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7961046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.7961046
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.979976340
Short name T278
Test name
Test status
Simulation time 305920867877 ps
CPU time 151.42 seconds
Started Feb 25 01:48:10 PM PST 24
Finished Feb 25 01:50:41 PM PST 24
Peak memory 190952 kb
Host smart-799943ee-47a7-4613-b1d7-baf92debe6fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979976340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.979976340
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2141186568
Short name T271
Test name
Test status
Simulation time 2079169178860 ps
CPU time 406.12 seconds
Started Feb 25 01:48:08 PM PST 24
Finished Feb 25 01:54:54 PM PST 24
Peak memory 190944 kb
Host smart-c96bf5b2-dc02-4c6c-8542-99fe22763be5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141186568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2141186568
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2553898752
Short name T182
Test name
Test status
Simulation time 37723118917 ps
CPU time 81.77 seconds
Started Feb 25 01:48:09 PM PST 24
Finished Feb 25 01:49:30 PM PST 24
Peak memory 190952 kb
Host smart-756b8d72-ca28-4ba5-a72d-cca0941ced8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553898752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2553898752
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.98348409
Short name T137
Test name
Test status
Simulation time 162467310536 ps
CPU time 290.49 seconds
Started Feb 25 01:48:09 PM PST 24
Finished Feb 25 01:53:00 PM PST 24
Peak memory 190960 kb
Host smart-ab571a1b-b180-43dc-ad2d-c43f92020a85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98348409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.98348409
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.475625490
Short name T341
Test name
Test status
Simulation time 330060239706 ps
CPU time 238.81 seconds
Started Feb 25 01:48:23 PM PST 24
Finished Feb 25 01:52:23 PM PST 24
Peak memory 190964 kb
Host smart-f8b5ee09-a7b1-40fc-92e3-448f3fa0a14e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475625490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.475625490
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.1048586979
Short name T177
Test name
Test status
Simulation time 617683636506 ps
CPU time 475.12 seconds
Started Feb 25 01:48:10 PM PST 24
Finished Feb 25 01:56:06 PM PST 24
Peak memory 190960 kb
Host smart-f29f3450-eb22-4ac3-a561-d3e7f9e2eeb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048586979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.1048586979
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1338518776
Short name T410
Test name
Test status
Simulation time 142687988795 ps
CPU time 188.41 seconds
Started Feb 25 01:47:08 PM PST 24
Finished Feb 25 01:50:16 PM PST 24
Peak memory 182748 kb
Host smart-306fbbba-646e-43cd-84b1-8e0700ced057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338518776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1338518776
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.790694397
Short name T254
Test name
Test status
Simulation time 394834512335 ps
CPU time 378 seconds
Started Feb 25 01:47:19 PM PST 24
Finished Feb 25 01:53:38 PM PST 24
Peak memory 194484 kb
Host smart-d299804b-7bf3-488d-916f-a5b217f8522c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790694397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.790694397
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3112466696
Short name T22
Test name
Test status
Simulation time 1141094542 ps
CPU time 2.51 seconds
Started Feb 25 01:47:16 PM PST 24
Finished Feb 25 01:47:19 PM PST 24
Peak memory 190908 kb
Host smart-1149f373-a5e2-4f05-b834-bedf330aec21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112466696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3112466696
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.1801846797
Short name T36
Test name
Test status
Simulation time 24901245764 ps
CPU time 211.87 seconds
Started Feb 25 01:47:14 PM PST 24
Finished Feb 25 01:50:47 PM PST 24
Peak memory 205708 kb
Host smart-7e9ebea3-7fff-4064-88bf-ab3721600956
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801846797 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.1801846797
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.340360159
Short name T264
Test name
Test status
Simulation time 22075037703 ps
CPU time 35.94 seconds
Started Feb 25 01:48:09 PM PST 24
Finished Feb 25 01:48:45 PM PST 24
Peak memory 182496 kb
Host smart-27c2c706-67bd-4d40-ac9b-414e7836f00f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340360159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.340360159
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.2453657136
Short name T308
Test name
Test status
Simulation time 97116964858 ps
CPU time 91.95 seconds
Started Feb 25 01:48:14 PM PST 24
Finished Feb 25 01:49:46 PM PST 24
Peak memory 190952 kb
Host smart-031e0e11-be8d-41c0-a070-86c5a0d104f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453657136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2453657136
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3045924492
Short name T233
Test name
Test status
Simulation time 487954945159 ps
CPU time 393.03 seconds
Started Feb 25 01:48:09 PM PST 24
Finished Feb 25 01:54:42 PM PST 24
Peak memory 193112 kb
Host smart-3ca4aaf1-5637-4ce6-9f96-0d25fbd754c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045924492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3045924492
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.540944731
Short name T256
Test name
Test status
Simulation time 85570015001 ps
CPU time 168.28 seconds
Started Feb 25 01:48:10 PM PST 24
Finished Feb 25 01:50:58 PM PST 24
Peak memory 192084 kb
Host smart-102132ec-9f51-438a-b060-a2cf97fece05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540944731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.540944731
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1336390502
Short name T293
Test name
Test status
Simulation time 343345387841 ps
CPU time 141.26 seconds
Started Feb 25 01:48:09 PM PST 24
Finished Feb 25 01:50:30 PM PST 24
Peak memory 190904 kb
Host smart-3edc0e6b-9b39-4b96-b5a0-0e895517818b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336390502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1336390502
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.1733552708
Short name T90
Test name
Test status
Simulation time 529536330599 ps
CPU time 1172.31 seconds
Started Feb 25 01:48:08 PM PST 24
Finished Feb 25 02:07:41 PM PST 24
Peak memory 190952 kb
Host smart-15a37753-6ff9-4ff2-8928-677a673f921a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733552708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1733552708
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2352521372
Short name T279
Test name
Test status
Simulation time 43598508395 ps
CPU time 79.3 seconds
Started Feb 25 01:48:08 PM PST 24
Finished Feb 25 01:49:28 PM PST 24
Peak memory 190948 kb
Host smart-f1480709-5c85-428b-b695-2f5463fc6542
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352521372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2352521372
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1819777898
Short name T418
Test name
Test status
Simulation time 257409001465 ps
CPU time 144.36 seconds
Started Feb 25 01:48:10 PM PST 24
Finished Feb 25 01:50:34 PM PST 24
Peak memory 190872 kb
Host smart-1d54e9d3-40dd-49cd-9b6a-27d3d629c457
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819777898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1819777898
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.3171823126
Short name T268
Test name
Test status
Simulation time 137029849216 ps
CPU time 271.07 seconds
Started Feb 25 01:48:13 PM PST 24
Finished Feb 25 01:52:44 PM PST 24
Peak memory 190964 kb
Host smart-944671bb-ec1b-4b98-8650-8aaf41d06663
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171823126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3171823126
Directory /workspace/99.rv_timer_random/latest
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