Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.57 99.36 98.73 100.00 100.00 100.00 99.32


Total test records in report: 577
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T506 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1251309344 Feb 29 12:52:29 PM PST 24 Feb 29 12:52:31 PM PST 24 487675851 ps
T507 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.534197263 Feb 29 12:52:30 PM PST 24 Feb 29 12:52:30 PM PST 24 35048214 ps
T87 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.545899153 Feb 29 12:52:26 PM PST 24 Feb 29 12:52:31 PM PST 24 1361233708 ps
T508 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3231127970 Feb 29 12:52:41 PM PST 24 Feb 29 12:52:43 PM PST 24 654124581 ps
T509 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1073832256 Feb 29 12:52:31 PM PST 24 Feb 29 12:52:32 PM PST 24 28947393 ps
T510 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2478185635 Feb 29 12:52:36 PM PST 24 Feb 29 12:52:38 PM PST 24 858189605 ps
T511 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.597714131 Feb 29 12:52:52 PM PST 24 Feb 29 12:52:53 PM PST 24 15297415 ps
T512 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3168134059 Feb 29 12:52:46 PM PST 24 Feb 29 12:52:47 PM PST 24 13715704 ps
T513 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.243365089 Feb 29 12:52:52 PM PST 24 Feb 29 12:52:53 PM PST 24 19746337 ps
T514 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1212055023 Feb 29 12:52:24 PM PST 24 Feb 29 12:52:25 PM PST 24 93368212 ps
T515 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.382952320 Feb 29 12:52:30 PM PST 24 Feb 29 12:52:31 PM PST 24 68927593 ps
T88 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2242038406 Feb 29 12:52:43 PM PST 24 Feb 29 12:52:45 PM PST 24 12461322 ps
T516 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1321486160 Feb 29 12:52:44 PM PST 24 Feb 29 12:52:45 PM PST 24 41635523 ps
T517 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2744753905 Feb 29 12:52:36 PM PST 24 Feb 29 12:52:37 PM PST 24 11723640 ps
T518 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1051285920 Feb 29 12:52:44 PM PST 24 Feb 29 12:52:47 PM PST 24 83097284 ps
T519 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1282361675 Feb 29 12:52:50 PM PST 24 Feb 29 12:52:51 PM PST 24 28686597 ps
T520 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1793448482 Feb 29 12:52:33 PM PST 24 Feb 29 12:52:34 PM PST 24 42160106 ps
T521 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2672038052 Feb 29 12:52:28 PM PST 24 Feb 29 12:52:31 PM PST 24 361457492 ps
T522 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3468338814 Feb 29 12:52:46 PM PST 24 Feb 29 12:52:47 PM PST 24 11960792 ps
T523 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3986272113 Feb 29 12:52:31 PM PST 24 Feb 29 12:52:31 PM PST 24 59434625 ps
T524 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1188669021 Feb 29 12:52:46 PM PST 24 Feb 29 12:52:47 PM PST 24 16324343 ps
T525 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3311449593 Feb 29 12:52:40 PM PST 24 Feb 29 12:52:45 PM PST 24 50222432 ps
T526 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2194179131 Feb 29 12:52:44 PM PST 24 Feb 29 12:52:46 PM PST 24 102382416 ps
T527 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2334689042 Feb 29 12:52:19 PM PST 24 Feb 29 12:52:21 PM PST 24 50484921 ps
T528 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.4244679032 Feb 29 12:52:44 PM PST 24 Feb 29 12:52:45 PM PST 24 137287381 ps
T529 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1716338366 Feb 29 12:52:33 PM PST 24 Feb 29 12:52:35 PM PST 24 56914294 ps
T530 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.42081939 Feb 29 12:52:22 PM PST 24 Feb 29 12:52:23 PM PST 24 43518139 ps
T531 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1514236915 Feb 29 12:52:24 PM PST 24 Feb 29 12:52:26 PM PST 24 124169691 ps
T532 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.4225041194 Feb 29 12:52:40 PM PST 24 Feb 29 12:52:40 PM PST 24 15647625 ps
T533 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.491958687 Feb 29 12:52:28 PM PST 24 Feb 29 12:52:30 PM PST 24 44840367 ps
T534 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2034356170 Feb 29 12:52:43 PM PST 24 Feb 29 12:52:45 PM PST 24 76990866 ps
T535 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1064561457 Feb 29 12:52:44 PM PST 24 Feb 29 12:52:45 PM PST 24 76324754 ps
T89 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.181842933 Feb 29 12:52:45 PM PST 24 Feb 29 12:52:46 PM PST 24 50776433 ps
T536 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2548685709 Feb 29 12:52:32 PM PST 24 Feb 29 12:52:34 PM PST 24 530020249 ps
T537 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3021730496 Feb 29 12:52:43 PM PST 24 Feb 29 12:52:45 PM PST 24 84726234 ps
T538 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.973900399 Feb 29 12:52:28 PM PST 24 Feb 29 12:52:29 PM PST 24 23056919 ps
T539 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1289269575 Feb 29 12:52:28 PM PST 24 Feb 29 12:52:30 PM PST 24 18748278 ps
T540 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.563720927 Feb 29 12:52:56 PM PST 24 Feb 29 12:52:58 PM PST 24 54833479 ps
T541 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2341080358 Feb 29 12:52:19 PM PST 24 Feb 29 12:52:20 PM PST 24 13119462 ps
T542 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1817463181 Feb 29 12:52:19 PM PST 24 Feb 29 12:52:21 PM PST 24 117115962 ps
T543 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3272823269 Feb 29 12:52:39 PM PST 24 Feb 29 12:52:41 PM PST 24 300786371 ps
T544 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2075312584 Feb 29 12:52:21 PM PST 24 Feb 29 12:52:22 PM PST 24 12703244 ps
T545 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3198861907 Feb 29 12:52:45 PM PST 24 Feb 29 12:52:47 PM PST 24 212657152 ps
T90 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2326556736 Feb 29 12:52:50 PM PST 24 Feb 29 12:52:50 PM PST 24 66567409 ps
T546 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2183096249 Feb 29 12:52:30 PM PST 24 Feb 29 12:52:31 PM PST 24 217810163 ps
T547 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2693553404 Feb 29 12:53:02 PM PST 24 Feb 29 12:53:03 PM PST 24 95113806 ps
T548 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2161396118 Feb 29 12:52:47 PM PST 24 Feb 29 12:52:48 PM PST 24 63982687 ps
T549 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2510779690 Feb 29 12:52:47 PM PST 24 Feb 29 12:52:48 PM PST 24 21268547 ps
T550 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.4046885937 Feb 29 12:52:35 PM PST 24 Feb 29 12:52:36 PM PST 24 81525080 ps
T551 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.40340736 Feb 29 12:52:44 PM PST 24 Feb 29 12:52:46 PM PST 24 61216265 ps
T552 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1329764806 Feb 29 12:52:56 PM PST 24 Feb 29 12:52:58 PM PST 24 51163843 ps
T553 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.4050438556 Feb 29 12:52:36 PM PST 24 Feb 29 12:52:37 PM PST 24 143332660 ps
T554 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1425257283 Feb 29 12:52:38 PM PST 24 Feb 29 12:52:39 PM PST 24 48438046 ps
T555 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1205667129 Feb 29 12:52:43 PM PST 24 Feb 29 12:52:49 PM PST 24 36515820 ps
T556 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3739597584 Feb 29 12:52:26 PM PST 24 Feb 29 12:52:28 PM PST 24 37196584 ps
T557 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3589959995 Feb 29 12:52:52 PM PST 24 Feb 29 12:52:53 PM PST 24 40660771 ps
T558 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3110616780 Feb 29 12:52:22 PM PST 24 Feb 29 12:52:24 PM PST 24 104880272 ps
T559 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3249242917 Feb 29 12:52:25 PM PST 24 Feb 29 12:52:26 PM PST 24 16815911 ps
T560 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.746271747 Feb 29 12:52:20 PM PST 24 Feb 29 12:52:21 PM PST 24 88206531 ps
T561 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3429646768 Feb 29 12:53:12 PM PST 24 Feb 29 12:53:13 PM PST 24 48086499 ps
T562 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2181724387 Feb 29 12:52:45 PM PST 24 Feb 29 12:52:46 PM PST 24 42279973 ps
T563 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.245787700 Feb 29 12:52:33 PM PST 24 Feb 29 12:52:34 PM PST 24 49274557 ps
T564 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2343477 Feb 29 12:52:24 PM PST 24 Feb 29 12:52:25 PM PST 24 170759058 ps
T565 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.673062321 Feb 29 12:52:39 PM PST 24 Feb 29 12:52:40 PM PST 24 21253490 ps
T566 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1467408082 Feb 29 12:52:26 PM PST 24 Feb 29 12:52:27 PM PST 24 33368670 ps
T567 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3603168480 Feb 29 12:52:46 PM PST 24 Feb 29 12:52:47 PM PST 24 12332022 ps
T568 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3663391040 Feb 29 12:52:50 PM PST 24 Feb 29 12:52:51 PM PST 24 41091716 ps
T569 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2800143944 Feb 29 12:52:51 PM PST 24 Feb 29 12:52:51 PM PST 24 14408275 ps
T570 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.722272594 Feb 29 12:52:38 PM PST 24 Feb 29 12:52:39 PM PST 24 15687071 ps
T91 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1934480587 Feb 29 12:52:31 PM PST 24 Feb 29 12:52:32 PM PST 24 13868161 ps
T571 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3289662814 Feb 29 12:52:32 PM PST 24 Feb 29 12:52:33 PM PST 24 32081483 ps
T572 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3780284265 Feb 29 12:52:33 PM PST 24 Feb 29 12:52:34 PM PST 24 13437108 ps
T573 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3487047848 Feb 29 12:52:41 PM PST 24 Feb 29 12:52:48 PM PST 24 67166620 ps
T574 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.101641926 Feb 29 12:52:23 PM PST 24 Feb 29 12:52:26 PM PST 24 248053608 ps
T575 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.4123454549 Feb 29 12:52:27 PM PST 24 Feb 29 12:52:29 PM PST 24 444991764 ps
T576 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2535813592 Feb 29 12:52:41 PM PST 24 Feb 29 12:52:43 PM PST 24 68617387 ps
T577 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1725271529 Feb 29 12:52:39 PM PST 24 Feb 29 12:52:41 PM PST 24 115085032 ps

Test location /workspace/coverage/default/5.rv_timer_stress_all.2316195255
Short name T2
Test name
Test status
Simulation time 798698787788 ps
CPU time 806.82 seconds
Started Feb 29 01:00:46 PM PST 24
Finished Feb 29 01:14:13 PM PST 24
Peak memory 190980 kb
Host smart-48e5ac42-d223-4902-9157-26d35a15fa38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316195255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
2316195255
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.1343469621
Short name T37
Test name
Test status
Simulation time 132064129685 ps
CPU time 485.95 seconds
Started Feb 29 01:01:23 PM PST 24
Finished Feb 29 01:09:29 PM PST 24
Peak memory 205748 kb
Host smart-3c1b9128-0efb-48bb-9b1f-511a13e81e47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343469621 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.1343469621
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.231190416
Short name T30
Test name
Test status
Simulation time 77324376 ps
CPU time 1.08 seconds
Started Feb 29 12:52:25 PM PST 24
Finished Feb 29 12:52:26 PM PST 24
Peak memory 194520 kb
Host smart-cb63f4fd-ac4a-44fe-a8fa-5ed584ad6fe2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231190416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.231190416
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1758698106
Short name T155
Test name
Test status
Simulation time 703237618000 ps
CPU time 1409.64 seconds
Started Feb 29 01:01:31 PM PST 24
Finished Feb 29 01:25:01 PM PST 24
Peak memory 190968 kb
Host smart-8ed92014-15a2-4a0a-835e-da4de983662b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758698106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1758698106
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2077074776
Short name T139
Test name
Test status
Simulation time 1493503462554 ps
CPU time 2995.71 seconds
Started Feb 29 01:00:50 PM PST 24
Finished Feb 29 01:50:46 PM PST 24
Peak memory 195168 kb
Host smart-a402b45f-02c7-439d-9930-e6e2b0fedd93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077074776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2077074776
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.146306280
Short name T150
Test name
Test status
Simulation time 2950940534228 ps
CPU time 2296.33 seconds
Started Feb 29 01:00:58 PM PST 24
Finished Feb 29 01:39:15 PM PST 24
Peak memory 195784 kb
Host smart-8ea85c45-1242-48bc-954a-e07a54f14786
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146306280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.
146306280
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3486599532
Short name T102
Test name
Test status
Simulation time 2339010227901 ps
CPU time 2352.8 seconds
Started Feb 29 01:00:50 PM PST 24
Finished Feb 29 01:40:04 PM PST 24
Peak memory 195560 kb
Host smart-e5190d67-46c0-40d4-b3d2-5b3b838b40ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486599532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3486599532
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.91874681
Short name T148
Test name
Test status
Simulation time 2757747585142 ps
CPU time 2533.04 seconds
Started Feb 29 01:01:18 PM PST 24
Finished Feb 29 01:43:32 PM PST 24
Peak memory 191124 kb
Host smart-cad87218-85fe-49a8-84b4-f1aa35f24938
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91874681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.91874681
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/84.rv_timer_random.4010965889
Short name T7
Test name
Test status
Simulation time 1135218699939 ps
CPU time 983.98 seconds
Started Feb 29 01:01:38 PM PST 24
Finished Feb 29 01:18:02 PM PST 24
Peak memory 194860 kb
Host smart-883a2181-c087-4457-bd64-c08be3cc0b7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010965889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.4010965889
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.3102324200
Short name T261
Test name
Test status
Simulation time 627167230016 ps
CPU time 2006.01 seconds
Started Feb 29 01:01:23 PM PST 24
Finished Feb 29 01:34:50 PM PST 24
Peak memory 190996 kb
Host smart-edfe004a-ae8e-483c-8f1d-2372a61f5ffe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102324200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.3102324200
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.4032697385
Short name T52
Test name
Test status
Simulation time 40537370 ps
CPU time 0.56 seconds
Started Feb 29 12:52:21 PM PST 24
Finished Feb 29 12:52:22 PM PST 24
Peak memory 182308 kb
Host smart-1ece42cc-c17d-4a8b-be25-5ca583cc3101
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032697385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.4032697385
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2679782220
Short name T216
Test name
Test status
Simulation time 532574011341 ps
CPU time 1253.16 seconds
Started Feb 29 01:01:35 PM PST 24
Finished Feb 29 01:22:29 PM PST 24
Peak memory 190952 kb
Host smart-bdc7c6d4-fb70-4e49-8efe-82aea2bf76a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679782220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2679782220
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.1431741335
Short name T113
Test name
Test status
Simulation time 576732413319 ps
CPU time 1043.91 seconds
Started Feb 29 01:00:58 PM PST 24
Finished Feb 29 01:18:23 PM PST 24
Peak memory 191012 kb
Host smart-006f27d9-daf4-43bb-946e-8136b29c5894
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431741335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.1431741335
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1750076342
Short name T20
Test name
Test status
Simulation time 41565279 ps
CPU time 0.79 seconds
Started Feb 29 01:00:39 PM PST 24
Finished Feb 29 01:00:40 PM PST 24
Peak memory 212844 kb
Host smart-8ef27414-35e6-48ba-9e70-fbd73521e05c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750076342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1750076342
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/125.rv_timer_random.1225984918
Short name T117
Test name
Test status
Simulation time 114532500807 ps
CPU time 200.8 seconds
Started Feb 29 01:01:34 PM PST 24
Finished Feb 29 01:04:55 PM PST 24
Peak memory 193056 kb
Host smart-8a12a678-7e08-45d2-b669-c0fc481d91ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225984918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1225984918
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3250864845
Short name T64
Test name
Test status
Simulation time 125192064832 ps
CPU time 308.22 seconds
Started Feb 29 01:01:34 PM PST 24
Finished Feb 29 01:06:43 PM PST 24
Peak memory 190488 kb
Host smart-40605215-18ff-4ea7-951b-7d9d96c9ae4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250864845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3250864845
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.4062379273
Short name T174
Test name
Test status
Simulation time 1016045097747 ps
CPU time 694.7 seconds
Started Feb 29 01:00:46 PM PST 24
Finished Feb 29 01:12:21 PM PST 24
Peak memory 195380 kb
Host smart-e2032131-b304-4c76-9dea-b2607daa2f7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062379273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
4062379273
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.3890119020
Short name T12
Test name
Test status
Simulation time 239781848967 ps
CPU time 369.67 seconds
Started Feb 29 01:00:50 PM PST 24
Finished Feb 29 01:07:00 PM PST 24
Peak memory 195428 kb
Host smart-fa0eefe5-1e30-4e98-b6f1-d73e8ce91854
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890119020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.3890119020
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.2821032436
Short name T295
Test name
Test status
Simulation time 453105556296 ps
CPU time 1448.39 seconds
Started Feb 29 01:01:21 PM PST 24
Finished Feb 29 01:25:29 PM PST 24
Peak memory 190912 kb
Host smart-7fdd86d8-55a8-4e17-aed7-615c4681d472
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821032436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.2821032436
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/129.rv_timer_random.135655847
Short name T10
Test name
Test status
Simulation time 442885570645 ps
CPU time 397.99 seconds
Started Feb 29 01:01:40 PM PST 24
Finished Feb 29 01:08:19 PM PST 24
Peak memory 190904 kb
Host smart-bbc21b7d-59c5-4cdc-817a-2271a7f03d3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135655847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.135655847
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1385918725
Short name T233
Test name
Test status
Simulation time 207588975569 ps
CPU time 341.61 seconds
Started Feb 29 01:01:43 PM PST 24
Finished Feb 29 01:07:25 PM PST 24
Peak memory 190908 kb
Host smart-67ff2309-b5e5-42a9-867c-78a3e5008ec6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385918725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1385918725
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.4053987590
Short name T211
Test name
Test status
Simulation time 863130884003 ps
CPU time 1045.83 seconds
Started Feb 29 01:01:03 PM PST 24
Finished Feb 29 01:18:29 PM PST 24
Peak memory 190996 kb
Host smart-60e1c8ce-957a-4ddc-990e-b6356d01351e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053987590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.4053987590
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/91.rv_timer_random.2363079822
Short name T315
Test name
Test status
Simulation time 164411493122 ps
CPU time 2210.55 seconds
Started Feb 29 01:01:38 PM PST 24
Finished Feb 29 01:38:28 PM PST 24
Peak memory 190932 kb
Host smart-5a10a1db-1901-41c7-b909-c06095212b53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363079822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2363079822
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.3480735084
Short name T203
Test name
Test status
Simulation time 1066607523732 ps
CPU time 1190.64 seconds
Started Feb 29 01:01:44 PM PST 24
Finished Feb 29 01:21:35 PM PST 24
Peak memory 193164 kb
Host smart-130cb6a5-e4e4-444e-a8a8-7f7f439c9689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480735084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3480735084
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1935166142
Short name T59
Test name
Test status
Simulation time 382358886427 ps
CPU time 657.11 seconds
Started Feb 29 01:01:35 PM PST 24
Finished Feb 29 01:12:33 PM PST 24
Peak memory 190920 kb
Host smart-9c5a51c9-5770-47f9-8bd1-1485e249818e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935166142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1935166142
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/157.rv_timer_random.1149360227
Short name T340
Test name
Test status
Simulation time 193795935290 ps
CPU time 275.53 seconds
Started Feb 29 01:01:51 PM PST 24
Finished Feb 29 01:06:27 PM PST 24
Peak memory 190940 kb
Host smart-0db9db25-12a4-4c1d-8896-7d14fdfa8c86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149360227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1149360227
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.4168780631
Short name T100
Test name
Test status
Simulation time 1194990665315 ps
CPU time 932.27 seconds
Started Feb 29 01:01:51 PM PST 24
Finished Feb 29 01:17:23 PM PST 24
Peak memory 190916 kb
Host smart-399bbe86-317a-407d-96f3-362204b321ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168780631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.4168780631
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.544842719
Short name T171
Test name
Test status
Simulation time 295405447838 ps
CPU time 301.19 seconds
Started Feb 29 01:00:49 PM PST 24
Finished Feb 29 01:05:51 PM PST 24
Peak memory 182740 kb
Host smart-5d6ae6b7-3476-4430-b855-5f8cef9017d9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544842719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.rv_timer_cfg_update_on_fly.544842719
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/184.rv_timer_random.2627635416
Short name T156
Test name
Test status
Simulation time 323845122096 ps
CPU time 768.9 seconds
Started Feb 29 01:02:00 PM PST 24
Finished Feb 29 01:14:49 PM PST 24
Peak memory 190952 kb
Host smart-b5fc96ee-7da0-41b0-ade4-70fb153d313f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627635416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2627635416
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random.895293701
Short name T133
Test name
Test status
Simulation time 549048419824 ps
CPU time 214.29 seconds
Started Feb 29 01:01:35 PM PST 24
Finished Feb 29 01:05:10 PM PST 24
Peak memory 190408 kb
Host smart-3ee9789e-95f1-4ffb-92c4-0d503f27ecc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895293701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.895293701
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random.25480640
Short name T180
Test name
Test status
Simulation time 81234036668 ps
CPU time 311.67 seconds
Started Feb 29 01:00:41 PM PST 24
Finished Feb 29 01:05:53 PM PST 24
Peak memory 190936 kb
Host smart-8c9595cc-15cb-4025-9ea8-0bcc28bcd9d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25480640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.25480640
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3600718768
Short name T190
Test name
Test status
Simulation time 138562632168 ps
CPU time 264.91 seconds
Started Feb 29 01:01:34 PM PST 24
Finished Feb 29 01:05:59 PM PST 24
Peak memory 190928 kb
Host smart-e28d57e3-5210-4f3f-a031-e3a22ad4cb85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600718768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3600718768
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1921953000
Short name T85
Test name
Test status
Simulation time 21979420 ps
CPU time 0.55 seconds
Started Feb 29 12:52:39 PM PST 24
Finished Feb 29 12:52:40 PM PST 24
Peak memory 182424 kb
Host smart-55b421ac-863e-4bf5-a65f-622ca0fc87ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921953000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1921953000
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/151.rv_timer_random.987926404
Short name T290
Test name
Test status
Simulation time 561284296305 ps
CPU time 1133.74 seconds
Started Feb 29 01:01:43 PM PST 24
Finished Feb 29 01:20:37 PM PST 24
Peak memory 190920 kb
Host smart-6e7947bf-cc52-4bc5-bfcf-08a080d96002
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987926404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.987926404
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.4023490139
Short name T222
Test name
Test status
Simulation time 107791562274 ps
CPU time 392.75 seconds
Started Feb 29 01:00:48 PM PST 24
Finished Feb 29 01:07:21 PM PST 24
Peak memory 190920 kb
Host smart-ba840cb7-248c-4312-bb90-bb333cf35b3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023490139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.4023490139
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.1409756133
Short name T230
Test name
Test status
Simulation time 736813258959 ps
CPU time 624.95 seconds
Started Feb 29 01:01:51 PM PST 24
Finished Feb 29 01:12:16 PM PST 24
Peak memory 190928 kb
Host smart-ccc38872-d76a-4512-8bae-65fc398ee67c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409756133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1409756133
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.989150125
Short name T317
Test name
Test status
Simulation time 3580545807274 ps
CPU time 1183.21 seconds
Started Feb 29 01:01:13 PM PST 24
Finished Feb 29 01:20:57 PM PST 24
Peak memory 182744 kb
Host smart-1ff0da88-bf6a-4a28-86e1-231b380ec424
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989150125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.989150125
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_random.2726222876
Short name T151
Test name
Test status
Simulation time 109411434527 ps
CPU time 490.62 seconds
Started Feb 29 01:01:23 PM PST 24
Finished Feb 29 01:09:35 PM PST 24
Peak memory 190940 kb
Host smart-3a08c530-516a-4907-99f7-5b7b4b8c5014
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726222876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2726222876
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random.459355796
Short name T200
Test name
Test status
Simulation time 673033747719 ps
CPU time 894.82 seconds
Started Feb 29 01:01:35 PM PST 24
Finished Feb 29 01:16:30 PM PST 24
Peak memory 190880 kb
Host smart-848e8cfa-3812-4959-b121-e4a5924d1f26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459355796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.459355796
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.529716073
Short name T126
Test name
Test status
Simulation time 591755011682 ps
CPU time 993.55 seconds
Started Feb 29 01:00:48 PM PST 24
Finished Feb 29 01:17:22 PM PST 24
Peak memory 190968 kb
Host smart-0c75f6b1-7563-4f68-8c52-6261f0d8955c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529716073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.529716073
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/101.rv_timer_random.445719294
Short name T255
Test name
Test status
Simulation time 691380594873 ps
CPU time 346.24 seconds
Started Feb 29 01:01:45 PM PST 24
Finished Feb 29 01:07:31 PM PST 24
Peak memory 190840 kb
Host smart-0b34fb60-bca4-4d99-b1d9-b4e8a07bfe6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445719294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.445719294
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3876684976
Short name T197
Test name
Test status
Simulation time 241044778151 ps
CPU time 246.38 seconds
Started Feb 29 01:00:50 PM PST 24
Finished Feb 29 01:04:57 PM PST 24
Peak memory 182784 kb
Host smart-a3832445-b2c6-43f6-b628-e19f857878d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876684976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3876684976
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/121.rv_timer_random.3297828297
Short name T299
Test name
Test status
Simulation time 692541597876 ps
CPU time 283.99 seconds
Started Feb 29 01:01:39 PM PST 24
Finished Feb 29 01:06:23 PM PST 24
Peak memory 190872 kb
Host smart-dd58dfce-1320-4db3-83dd-46e99ec4de02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297828297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3297828297
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2898916576
Short name T236
Test name
Test status
Simulation time 278126875712 ps
CPU time 194.61 seconds
Started Feb 29 01:01:46 PM PST 24
Finished Feb 29 01:05:01 PM PST 24
Peak memory 193032 kb
Host smart-cf80ccb3-f6e7-4251-ae07-959e556741fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898916576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2898916576
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random.3212664915
Short name T162
Test name
Test status
Simulation time 525412338041 ps
CPU time 480.44 seconds
Started Feb 29 01:01:14 PM PST 24
Finished Feb 29 01:09:15 PM PST 24
Peak memory 190748 kb
Host smart-b6cdeef5-1b81-4518-a169-1027f573a7cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212664915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3212664915
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3705996435
Short name T276
Test name
Test status
Simulation time 442962412925 ps
CPU time 678.99 seconds
Started Feb 29 01:01:21 PM PST 24
Finished Feb 29 01:12:40 PM PST 24
Peak memory 190920 kb
Host smart-2f362f52-2d44-4104-865d-34eed60870e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705996435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3705996435
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_random.4071543621
Short name T141
Test name
Test status
Simulation time 92182002328 ps
CPU time 128 seconds
Started Feb 29 01:01:23 PM PST 24
Finished Feb 29 01:03:32 PM PST 24
Peak memory 182720 kb
Host smart-fc55dcb0-c894-4d93-bea4-5b18ec5cc51e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071543621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.4071543621
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.2616454384
Short name T262
Test name
Test status
Simulation time 123673613060 ps
CPU time 233.03 seconds
Started Feb 29 01:00:58 PM PST 24
Finished Feb 29 01:04:51 PM PST 24
Peak memory 194904 kb
Host smart-02ff4913-fd8e-4071-a302-85a76d793b9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616454384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.2616454384
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.4166283032
Short name T109
Test name
Test status
Simulation time 138152607335 ps
CPU time 384.29 seconds
Started Feb 29 01:02:01 PM PST 24
Finished Feb 29 01:08:25 PM PST 24
Peak memory 193864 kb
Host smart-d83c98b3-a559-4ef4-a7e2-291d1ab8dcbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166283032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.4166283032
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random.4018325079
Short name T280
Test name
Test status
Simulation time 109833067572 ps
CPU time 306.16 seconds
Started Feb 29 01:01:01 PM PST 24
Finished Feb 29 01:06:08 PM PST 24
Peak memory 190924 kb
Host smart-aa98e360-293c-411d-9bd5-52e630da41ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018325079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.4018325079
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random.3279126681
Short name T333
Test name
Test status
Simulation time 90017166218 ps
CPU time 1031.82 seconds
Started Feb 29 01:00:58 PM PST 24
Finished Feb 29 01:18:10 PM PST 24
Peak memory 190928 kb
Host smart-6dae4ec5-6035-4e64-9a9d-6152a4bf4193
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279126681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3279126681
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.579823842
Short name T293
Test name
Test status
Simulation time 31644242050 ps
CPU time 18.22 seconds
Started Feb 29 01:01:21 PM PST 24
Finished Feb 29 01:01:39 PM PST 24
Peak memory 182748 kb
Host smart-90d7a20f-7ae7-4943-b7b6-4f4e24f7e8c8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579823842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.rv_timer_cfg_update_on_fly.579823842
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_random.3155254259
Short name T205
Test name
Test status
Simulation time 141080067311 ps
CPU time 1573.06 seconds
Started Feb 29 01:01:32 PM PST 24
Finished Feb 29 01:27:46 PM PST 24
Peak memory 190888 kb
Host smart-a2a7bf52-3472-43de-b442-1645db0ca852
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155254259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3155254259
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/80.rv_timer_random.2651387313
Short name T348
Test name
Test status
Simulation time 268395258141 ps
CPU time 1103.88 seconds
Started Feb 29 01:01:37 PM PST 24
Finished Feb 29 01:20:01 PM PST 24
Peak memory 190788 kb
Host smart-161c532a-d1fb-4de8-864a-7225c600314d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651387313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2651387313
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1826661285
Short name T165
Test name
Test status
Simulation time 72439328000 ps
CPU time 108.04 seconds
Started Feb 29 01:00:44 PM PST 24
Finished Feb 29 01:02:33 PM PST 24
Peak memory 190920 kb
Host smart-38f30e86-4860-41b3-8454-49f2770027ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826661285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1826661285
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/118.rv_timer_random.3792774818
Short name T195
Test name
Test status
Simulation time 313168856599 ps
CPU time 229.51 seconds
Started Feb 29 01:01:33 PM PST 24
Finished Feb 29 01:05:23 PM PST 24
Peak memory 190908 kb
Host smart-2b9c0cf5-0ce9-403b-b642-5ceef74ece45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792774818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3792774818
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/130.rv_timer_random.1664730098
Short name T5
Test name
Test status
Simulation time 344350568381 ps
CPU time 195.64 seconds
Started Feb 29 01:01:36 PM PST 24
Finished Feb 29 01:04:52 PM PST 24
Peak memory 190812 kb
Host smart-45dbd290-f69d-4993-b6eb-3894e9b5766c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664730098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1664730098
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1160483854
Short name T131
Test name
Test status
Simulation time 93261117927 ps
CPU time 71.72 seconds
Started Feb 29 01:00:47 PM PST 24
Finished Feb 29 01:01:59 PM PST 24
Peak memory 190856 kb
Host smart-a1315346-2acd-44ab-81df-ddaacbe98a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160483854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1160483854
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/158.rv_timer_random.215218504
Short name T120
Test name
Test status
Simulation time 494990856404 ps
CPU time 252.35 seconds
Started Feb 29 01:01:37 PM PST 24
Finished Feb 29 01:05:49 PM PST 24
Peak memory 190916 kb
Host smart-79653455-f8a9-4210-828f-2b60408a7c95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215218504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.215218504
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3475349586
Short name T43
Test name
Test status
Simulation time 870798479869 ps
CPU time 558.33 seconds
Started Feb 29 01:01:59 PM PST 24
Finished Feb 29 01:11:17 PM PST 24
Peak memory 190944 kb
Host smart-ac4c63bb-b6f0-4472-8bcc-44bd021700ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475349586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3475349586
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.4004818976
Short name T248
Test name
Test status
Simulation time 707547003328 ps
CPU time 608.53 seconds
Started Feb 29 01:01:59 PM PST 24
Finished Feb 29 01:12:07 PM PST 24
Peak memory 190864 kb
Host smart-4139138c-ef8a-4870-8d74-c0b050fe5f7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004818976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.4004818976
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.3792611041
Short name T249
Test name
Test status
Simulation time 321283690336 ps
CPU time 445.91 seconds
Started Feb 29 01:00:46 PM PST 24
Finished Feb 29 01:08:12 PM PST 24
Peak memory 190972 kb
Host smart-3362c18b-d57d-42de-842c-c571c2fe5552
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792611041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
3792611041
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_random.3773773535
Short name T294
Test name
Test status
Simulation time 87031233907 ps
CPU time 135.55 seconds
Started Feb 29 01:01:14 PM PST 24
Finished Feb 29 01:03:30 PM PST 24
Peak memory 192060 kb
Host smart-6de12cc3-6c2b-4a77-bcf9-313250523c9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773773535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.3773773535
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.861690648
Short name T185
Test name
Test status
Simulation time 484262147938 ps
CPU time 775.34 seconds
Started Feb 29 01:01:19 PM PST 24
Finished Feb 29 01:14:14 PM PST 24
Peak memory 182792 kb
Host smart-4cb5dad5-293a-4789-9a19-41612f6303cb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861690648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.rv_timer_cfg_update_on_fly.861690648
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3186180548
Short name T284
Test name
Test status
Simulation time 316007326079 ps
CPU time 155.51 seconds
Started Feb 29 01:01:22 PM PST 24
Finished Feb 29 01:03:57 PM PST 24
Peak memory 182776 kb
Host smart-83c176ea-6c71-4c7d-839b-a23e2ddc66b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186180548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3186180548
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1618959773
Short name T287
Test name
Test status
Simulation time 147968324650 ps
CPU time 2121.56 seconds
Started Feb 29 01:01:27 PM PST 24
Finished Feb 29 01:36:49 PM PST 24
Peak memory 190976 kb
Host smart-df558589-5553-450a-a355-1f64325f7b64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618959773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1618959773
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1566917416
Short name T63
Test name
Test status
Simulation time 632201650086 ps
CPU time 538.99 seconds
Started Feb 29 01:01:31 PM PST 24
Finished Feb 29 01:10:30 PM PST 24
Peak memory 190912 kb
Host smart-7b909b79-f747-488b-8ea3-e1de6e0e3478
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566917416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1566917416
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/78.rv_timer_random.1080476865
Short name T9
Test name
Test status
Simulation time 83598862317 ps
CPU time 325.35 seconds
Started Feb 29 01:01:42 PM PST 24
Finished Feb 29 01:07:08 PM PST 24
Peak memory 190956 kb
Host smart-f41a1815-7e1d-4dd8-8ff6-9ddc1548b1cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080476865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1080476865
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.3594046494
Short name T114
Test name
Test status
Simulation time 132305389200 ps
CPU time 164.93 seconds
Started Feb 29 01:00:45 PM PST 24
Finished Feb 29 01:03:30 PM PST 24
Peak memory 190932 kb
Host smart-8dcea3be-084e-44f0-a21d-51a42651863d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594046494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3594046494
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2173389454
Short name T60
Test name
Test status
Simulation time 396826421599 ps
CPU time 1192.51 seconds
Started Feb 29 01:00:47 PM PST 24
Finished Feb 29 01:20:40 PM PST 24
Peak memory 194792 kb
Host smart-09697d90-8d80-4373-9b05-61be5af3c466
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173389454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2173389454
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.1356469033
Short name T79
Test name
Test status
Simulation time 43489580890 ps
CPU time 70.19 seconds
Started Feb 29 01:00:49 PM PST 24
Finished Feb 29 01:01:59 PM PST 24
Peak memory 190940 kb
Host smart-58f75dcb-c256-4f07-8875-59050e96dda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356469033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1356469033
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/105.rv_timer_random.3669097908
Short name T227
Test name
Test status
Simulation time 550529244069 ps
CPU time 435.25 seconds
Started Feb 29 01:01:35 PM PST 24
Finished Feb 29 01:08:51 PM PST 24
Peak memory 193120 kb
Host smart-d7054a5d-6e94-4755-9d80-c47eada086a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669097908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3669097908
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.2857328866
Short name T210
Test name
Test status
Simulation time 174561205758 ps
CPU time 422.43 seconds
Started Feb 29 01:01:35 PM PST 24
Finished Feb 29 01:08:38 PM PST 24
Peak memory 191008 kb
Host smart-ab1f2ff3-67d7-476c-9da0-1db66390812b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857328866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2857328866
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.1095496296
Short name T74
Test name
Test status
Simulation time 682143169923 ps
CPU time 2008.57 seconds
Started Feb 29 01:01:44 PM PST 24
Finished Feb 29 01:35:13 PM PST 24
Peak memory 190836 kb
Host smart-7ab16eb3-2112-4d67-9260-7991e145d4f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095496296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1095496296
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.3993875800
Short name T272
Test name
Test status
Simulation time 262453610875 ps
CPU time 263.39 seconds
Started Feb 29 01:01:32 PM PST 24
Finished Feb 29 01:05:56 PM PST 24
Peak memory 193880 kb
Host smart-3745957b-552d-4250-a851-ae393b8017eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993875800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3993875800
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.3726117202
Short name T300
Test name
Test status
Simulation time 388651507117 ps
CPU time 261.05 seconds
Started Feb 29 01:01:31 PM PST 24
Finished Feb 29 01:05:53 PM PST 24
Peak memory 190932 kb
Host smart-c7ec0ed1-467b-4450-8b02-89744a5d3c48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726117202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3726117202
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.1482931311
Short name T192
Test name
Test status
Simulation time 187560226370 ps
CPU time 1044.69 seconds
Started Feb 29 01:01:25 PM PST 24
Finished Feb 29 01:18:50 PM PST 24
Peak memory 190932 kb
Host smart-f5817817-efaf-4ffb-a008-6c4d03ac3446
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482931311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1482931311
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1165025610
Short name T187
Test name
Test status
Simulation time 261890847280 ps
CPU time 460.9 seconds
Started Feb 29 01:00:52 PM PST 24
Finished Feb 29 01:08:33 PM PST 24
Peak memory 182752 kb
Host smart-c460eb75-0f76-4c79-9d97-801a91459935
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165025610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1165025610
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/131.rv_timer_random.1906879807
Short name T332
Test name
Test status
Simulation time 53301751131 ps
CPU time 141.43 seconds
Started Feb 29 01:01:36 PM PST 24
Finished Feb 29 01:03:58 PM PST 24
Peak memory 182612 kb
Host smart-4260e149-789d-4218-9d5c-1bc1ef7763d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906879807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1906879807
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3950327182
Short name T258
Test name
Test status
Simulation time 377588853601 ps
CPU time 212.12 seconds
Started Feb 29 01:00:48 PM PST 24
Finished Feb 29 01:04:20 PM PST 24
Peak memory 182596 kb
Host smart-ac75256a-3e61-4ef0-bf0c-62d14916f4dd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950327182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3950327182
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_random.259931161
Short name T127
Test name
Test status
Simulation time 129354324424 ps
CPU time 572.3 seconds
Started Feb 29 01:00:46 PM PST 24
Finished Feb 29 01:10:19 PM PST 24
Peak memory 190928 kb
Host smart-03e66132-b7da-4e8e-8cec-699ac879a201
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259931161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.259931161
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.4258304208
Short name T273
Test name
Test status
Simulation time 118601678162 ps
CPU time 127.23 seconds
Started Feb 29 01:01:45 PM PST 24
Finished Feb 29 01:03:52 PM PST 24
Peak memory 194188 kb
Host smart-152b3ea3-5cfd-4144-a9b4-c28b97820dde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258304208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.4258304208
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.218656716
Short name T217
Test name
Test status
Simulation time 100057817873 ps
CPU time 97.78 seconds
Started Feb 29 01:00:48 PM PST 24
Finished Feb 29 01:02:26 PM PST 24
Peak memory 190908 kb
Host smart-f4a5db86-d4cd-497b-919e-764ecd65cd9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218656716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.218656716
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.2258155767
Short name T199
Test name
Test status
Simulation time 116217597901 ps
CPU time 1792.86 seconds
Started Feb 29 01:01:51 PM PST 24
Finished Feb 29 01:31:44 PM PST 24
Peak memory 190932 kb
Host smart-f16feca4-7b5a-49d1-a629-1a5ae1d55449
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258155767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2258155767
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.4198541712
Short name T99
Test name
Test status
Simulation time 532314285749 ps
CPU time 571.49 seconds
Started Feb 29 01:01:51 PM PST 24
Finished Feb 29 01:11:22 PM PST 24
Peak memory 190908 kb
Host smart-e8fec392-a411-49b6-968b-221b476fe3f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198541712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.4198541712
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.4169859606
Short name T208
Test name
Test status
Simulation time 110454821012 ps
CPU time 775.32 seconds
Started Feb 29 01:01:47 PM PST 24
Finished Feb 29 01:14:42 PM PST 24
Peak memory 193104 kb
Host smart-e22f5ca9-4daa-48f4-a675-6317dc423ada
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169859606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.4169859606
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.144631292
Short name T119
Test name
Test status
Simulation time 860783067467 ps
CPU time 653.65 seconds
Started Feb 29 01:01:46 PM PST 24
Finished Feb 29 01:12:40 PM PST 24
Peak memory 190928 kb
Host smart-8ab22e33-0224-4c90-aa5f-5ddaa4aea7d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144631292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.144631292
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.2216561483
Short name T158
Test name
Test status
Simulation time 153311128152 ps
CPU time 525.15 seconds
Started Feb 29 01:01:48 PM PST 24
Finished Feb 29 01:10:34 PM PST 24
Peak memory 190932 kb
Host smart-d1234c5e-7634-4c8d-a8f9-97a9bb470548
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216561483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2216561483
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.1121014100
Short name T242
Test name
Test status
Simulation time 330711390083 ps
CPU time 314.03 seconds
Started Feb 29 01:02:00 PM PST 24
Finished Feb 29 01:07:14 PM PST 24
Peak memory 190940 kb
Host smart-b843a573-33f4-4f10-9e07-4a2e5ce97848
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121014100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1121014100
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2158375223
Short name T46
Test name
Test status
Simulation time 65268585184 ps
CPU time 123.83 seconds
Started Feb 29 01:02:09 PM PST 24
Finished Feb 29 01:04:13 PM PST 24
Peak memory 190952 kb
Host smart-1287e879-55c3-4f93-963d-d781e1f2db95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158375223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2158375223
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1758324263
Short name T136
Test name
Test status
Simulation time 162572149790 ps
CPU time 350.14 seconds
Started Feb 29 01:01:59 PM PST 24
Finished Feb 29 01:07:50 PM PST 24
Peak memory 190944 kb
Host smart-8a803ee7-f3d4-4376-b1bb-e2ee8666110a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758324263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1758324263
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.722913146
Short name T166
Test name
Test status
Simulation time 198723169469 ps
CPU time 287.64 seconds
Started Feb 29 01:02:00 PM PST 24
Finished Feb 29 01:06:48 PM PST 24
Peak memory 190976 kb
Host smart-21e71910-e3f1-4a24-bf6f-45d84543ae64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722913146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.722913146
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.2824966658
Short name T160
Test name
Test status
Simulation time 138303629319 ps
CPU time 467.42 seconds
Started Feb 29 01:02:13 PM PST 24
Finished Feb 29 01:10:01 PM PST 24
Peak memory 182644 kb
Host smart-d283d333-dc4e-46bf-a93c-58d1b4f3eacd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824966658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2824966658
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.481441665
Short name T350
Test name
Test status
Simulation time 93350264608 ps
CPU time 81.14 seconds
Started Feb 29 01:00:56 PM PST 24
Finished Feb 29 01:02:18 PM PST 24
Peak memory 190848 kb
Host smart-edbc3b49-a715-4f0b-9d85-5650e3f47122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481441665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.481441665
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2239004714
Short name T157
Test name
Test status
Simulation time 618951381789 ps
CPU time 144.22 seconds
Started Feb 29 01:01:14 PM PST 24
Finished Feb 29 01:03:39 PM PST 24
Peak memory 182712 kb
Host smart-b4b80fb1-80d2-494f-8d12-8d00f23e5c50
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239004714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2239004714
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2297911720
Short name T219
Test name
Test status
Simulation time 126602736068 ps
CPU time 219.2 seconds
Started Feb 29 01:01:18 PM PST 24
Finished Feb 29 01:04:58 PM PST 24
Peak memory 190952 kb
Host smart-7771cda5-9660-42a2-af82-acfd0b858ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297911720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2297911720
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1324510816
Short name T302
Test name
Test status
Simulation time 311284986338 ps
CPU time 523.54 seconds
Started Feb 29 01:01:20 PM PST 24
Finished Feb 29 01:10:04 PM PST 24
Peak memory 191184 kb
Host smart-e89736de-2fe5-4f51-b9f5-97cdc9550f42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324510816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1324510816
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_random.662765399
Short name T314
Test name
Test status
Simulation time 350852531632 ps
CPU time 481.4 seconds
Started Feb 29 01:01:21 PM PST 24
Finished Feb 29 01:09:22 PM PST 24
Peak memory 190972 kb
Host smart-aa36709b-7059-46f8-a349-ff7f9a8dd2d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662765399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.662765399
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1756737444
Short name T331
Test name
Test status
Simulation time 1011576923182 ps
CPU time 587.47 seconds
Started Feb 29 01:01:25 PM PST 24
Finished Feb 29 01:11:13 PM PST 24
Peak memory 182740 kb
Host smart-68da30fd-7c8b-4722-86c4-84c6fde31e9c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756737444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1756737444
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/88.rv_timer_random.1075461270
Short name T323
Test name
Test status
Simulation time 426025130742 ps
CPU time 88.39 seconds
Started Feb 29 01:01:38 PM PST 24
Finished Feb 29 01:03:06 PM PST 24
Peak memory 190932 kb
Host smart-212f74f3-d34c-4f13-a725-8994325b4780
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075461270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1075461270
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3392599906
Short name T335
Test name
Test status
Simulation time 376227415419 ps
CPU time 581.53 seconds
Started Feb 29 01:00:49 PM PST 24
Finished Feb 29 01:10:31 PM PST 24
Peak memory 195108 kb
Host smart-2a628dd1-417f-4074-b509-00e2ba5225a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392599906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3392599906
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.819782413
Short name T84
Test name
Test status
Simulation time 117607750 ps
CPU time 0.8 seconds
Started Feb 29 12:52:10 PM PST 24
Finished Feb 29 12:52:11 PM PST 24
Peak memory 192292 kb
Host smart-948f5c2f-9fcf-4a9b-aea5-0ca4e8dbca17
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819782413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alias
ing.819782413
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.957303197
Short name T502
Test name
Test status
Simulation time 91949891 ps
CPU time 3.19 seconds
Started Feb 29 12:52:13 PM PST 24
Finished Feb 29 12:52:16 PM PST 24
Peak memory 190796 kb
Host smart-4ada80df-dc5e-494f-9e4b-3af662e3d6ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957303197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.957303197
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.4130718957
Short name T86
Test name
Test status
Simulation time 61128616 ps
CPU time 0.56 seconds
Started Feb 29 12:52:24 PM PST 24
Finished Feb 29 12:52:25 PM PST 24
Peak memory 182496 kb
Host smart-cff1934c-c48b-4626-a07c-1c7b4bbd5fcd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130718957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.4130718957
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.42081939
Short name T530
Test name
Test status
Simulation time 43518139 ps
CPU time 1.01 seconds
Started Feb 29 12:52:22 PM PST 24
Finished Feb 29 12:52:23 PM PST 24
Peak memory 197068 kb
Host smart-8f8190b8-3c77-4da1-ab65-b4f8dc54813f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42081939 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.42081939
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3986272113
Short name T523
Test name
Test status
Simulation time 59434625 ps
CPU time 0.57 seconds
Started Feb 29 12:52:31 PM PST 24
Finished Feb 29 12:52:31 PM PST 24
Peak memory 182344 kb
Host smart-f7814dd6-ee76-4aea-afbb-09d3603a1812
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986272113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3986272113
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3349498977
Short name T92
Test name
Test status
Simulation time 60113241 ps
CPU time 0.59 seconds
Started Feb 29 12:52:20 PM PST 24
Finished Feb 29 12:52:21 PM PST 24
Peak memory 191516 kb
Host smart-1def1288-c68a-46fe-a2a9-5585305750f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349498977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.3349498977
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1514236915
Short name T531
Test name
Test status
Simulation time 124169691 ps
CPU time 1.29 seconds
Started Feb 29 12:52:24 PM PST 24
Finished Feb 29 12:52:26 PM PST 24
Peak memory 196360 kb
Host smart-a411253f-aa68-4db4-acf4-bb68ad23bd9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514236915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1514236915
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1817463181
Short name T542
Test name
Test status
Simulation time 117115962 ps
CPU time 1.15 seconds
Started Feb 29 12:52:19 PM PST 24
Finished Feb 29 12:52:21 PM PST 24
Peak memory 194840 kb
Host smart-f1a06d0f-6492-4ed6-b4bf-a82e18b19598
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817463181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1817463181
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3810354350
Short name T476
Test name
Test status
Simulation time 365000220 ps
CPU time 0.62 seconds
Started Feb 29 12:52:22 PM PST 24
Finished Feb 29 12:52:23 PM PST 24
Peak memory 191736 kb
Host smart-c10367f1-7765-40c1-85e3-67fca8d54f72
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810354350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3810354350
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3110616780
Short name T558
Test name
Test status
Simulation time 104880272 ps
CPU time 1.59 seconds
Started Feb 29 12:52:22 PM PST 24
Finished Feb 29 12:52:24 PM PST 24
Peak memory 192312 kb
Host smart-d50da8af-b2c4-45c1-9b0c-07311b614d70
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110616780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.3110616780
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2341080358
Short name T541
Test name
Test status
Simulation time 13119462 ps
CPU time 0.53 seconds
Started Feb 29 12:52:19 PM PST 24
Finished Feb 29 12:52:20 PM PST 24
Peak memory 181884 kb
Host smart-051198ae-66d3-470e-828a-15fe5e9e04c2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341080358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.2341080358
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2334689042
Short name T527
Test name
Test status
Simulation time 50484921 ps
CPU time 0.68 seconds
Started Feb 29 12:52:19 PM PST 24
Finished Feb 29 12:52:21 PM PST 24
Peak memory 193856 kb
Host smart-7dec487c-caf4-4398-aa66-6fb2e1161fba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334689042 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2334689042
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1289269575
Short name T539
Test name
Test status
Simulation time 18748278 ps
CPU time 0.57 seconds
Started Feb 29 12:52:28 PM PST 24
Finished Feb 29 12:52:30 PM PST 24
Peak memory 182508 kb
Host smart-dcf0310d-86d2-474b-9cd5-40017ce0bdf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289269575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1289269575
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.540286318
Short name T457
Test name
Test status
Simulation time 34209821 ps
CPU time 0.54 seconds
Started Feb 29 12:52:33 PM PST 24
Finished Feb 29 12:52:34 PM PST 24
Peak memory 182248 kb
Host smart-bb2dc86b-3945-4a53-a284-6d3ae7ba1504
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540286318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.540286318
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2075312584
Short name T544
Test name
Test status
Simulation time 12703244 ps
CPU time 0.61 seconds
Started Feb 29 12:52:21 PM PST 24
Finished Feb 29 12:52:22 PM PST 24
Peak memory 191576 kb
Host smart-4fca4eab-19f0-4ed2-9850-ce8414332436
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075312584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2075312584
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.786336339
Short name T503
Test name
Test status
Simulation time 110429798 ps
CPU time 0.9 seconds
Started Feb 29 12:52:14 PM PST 24
Finished Feb 29 12:52:15 PM PST 24
Peak memory 194852 kb
Host smart-ea26a7d3-8642-4b49-b2a7-a24bd9b1703c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786336339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.786336339
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3149489250
Short name T481
Test name
Test status
Simulation time 33086751 ps
CPU time 0.92 seconds
Started Feb 29 12:52:37 PM PST 24
Finished Feb 29 12:52:38 PM PST 24
Peak memory 197352 kb
Host smart-28b7622f-de7d-4db1-812d-63601602454f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149489250 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3149489250
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.181842933
Short name T89
Test name
Test status
Simulation time 50776433 ps
CPU time 0.62 seconds
Started Feb 29 12:52:45 PM PST 24
Finished Feb 29 12:52:46 PM PST 24
Peak memory 182520 kb
Host smart-ea9f7b3b-c0ee-4489-b907-7077fd36cf14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181842933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.181842933
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1535945760
Short name T494
Test name
Test status
Simulation time 16116153 ps
CPU time 0.56 seconds
Started Feb 29 12:52:52 PM PST 24
Finished Feb 29 12:52:52 PM PST 24
Peak memory 182240 kb
Host smart-bfd8a7f4-b1f2-4044-bf89-c42d640fe8ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535945760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1535945760
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3631844394
Short name T53
Test name
Test status
Simulation time 23478615 ps
CPU time 0.61 seconds
Started Feb 29 12:52:57 PM PST 24
Finished Feb 29 12:52:58 PM PST 24
Peak memory 191776 kb
Host smart-3daa3f43-8090-44db-b234-d6b1121ed9c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631844394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3631844394
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3272823269
Short name T543
Test name
Test status
Simulation time 300786371 ps
CPU time 1.45 seconds
Started Feb 29 12:52:39 PM PST 24
Finished Feb 29 12:52:41 PM PST 24
Peak memory 197064 kb
Host smart-27ddf55f-19c5-499c-b26f-ad3d9c9768b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272823269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3272823269
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3953170081
Short name T475
Test name
Test status
Simulation time 80913222 ps
CPU time 0.79 seconds
Started Feb 29 12:52:37 PM PST 24
Finished Feb 29 12:52:38 PM PST 24
Peak memory 182844 kb
Host smart-fb297ae1-3fc7-42f9-8d51-008b293366c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953170081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.3953170081
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1607829621
Short name T456
Test name
Test status
Simulation time 32415683 ps
CPU time 0.65 seconds
Started Feb 29 12:52:34 PM PST 24
Finished Feb 29 12:52:35 PM PST 24
Peak memory 193724 kb
Host smart-168dc541-6c78-4fb3-879c-8b553444d081
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607829621 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1607829621
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1188489862
Short name T72
Test name
Test status
Simulation time 16524139 ps
CPU time 0.57 seconds
Started Feb 29 12:52:42 PM PST 24
Finished Feb 29 12:52:42 PM PST 24
Peak memory 182564 kb
Host smart-bdb8294f-f361-4900-8203-182886828906
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188489862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1188489862
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3547468406
Short name T453
Test name
Test status
Simulation time 12657659 ps
CPU time 0.52 seconds
Started Feb 29 12:52:42 PM PST 24
Finished Feb 29 12:52:43 PM PST 24
Peak memory 181624 kb
Host smart-427f0931-8571-4c00-8fe5-5b9339a26236
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547468406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3547468406
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1356389075
Short name T499
Test name
Test status
Simulation time 93997692 ps
CPU time 0.78 seconds
Started Feb 29 12:52:44 PM PST 24
Finished Feb 29 12:52:45 PM PST 24
Peak memory 191232 kb
Host smart-7aaf9865-598c-43fa-94ba-7f7d88b4ba41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356389075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.1356389075
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2535813592
Short name T576
Test name
Test status
Simulation time 68617387 ps
CPU time 1.6 seconds
Started Feb 29 12:52:41 PM PST 24
Finished Feb 29 12:52:43 PM PST 24
Peak memory 197260 kb
Host smart-e72fc810-acf5-41d8-9588-a91030a3da36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535813592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2535813592
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.382952320
Short name T515
Test name
Test status
Simulation time 68927593 ps
CPU time 1.04 seconds
Started Feb 29 12:52:30 PM PST 24
Finished Feb 29 12:52:31 PM PST 24
Peak memory 194656 kb
Host smart-66f9ecb7-7932-42ee-b9a6-a157c732c5f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382952320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.382952320
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3487047848
Short name T573
Test name
Test status
Simulation time 67166620 ps
CPU time 1.56 seconds
Started Feb 29 12:52:41 PM PST 24
Finished Feb 29 12:52:48 PM PST 24
Peak memory 197216 kb
Host smart-9bc3b370-7f2a-495f-b320-d8ecae7c0a65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487047848 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3487047848
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.785658116
Short name T55
Test name
Test status
Simulation time 45811616 ps
CPU time 0.55 seconds
Started Feb 29 12:52:53 PM PST 24
Finished Feb 29 12:52:53 PM PST 24
Peak memory 182508 kb
Host smart-67910452-45cb-4794-a5f1-e356ee814921
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785658116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.785658116
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.243365089
Short name T513
Test name
Test status
Simulation time 19746337 ps
CPU time 0.55 seconds
Started Feb 29 12:52:52 PM PST 24
Finished Feb 29 12:52:53 PM PST 24
Peak memory 182232 kb
Host smart-b8f62d3b-42ce-4000-ae4a-d80bb1c9ddba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243365089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.243365089
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.4139437718
Short name T95
Test name
Test status
Simulation time 14190125 ps
CPU time 0.63 seconds
Started Feb 29 12:52:43 PM PST 24
Finished Feb 29 12:52:54 PM PST 24
Peak memory 191732 kb
Host smart-1f861f16-f705-424c-9213-6a0eef86220f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139437718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.4139437718
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3401064930
Short name T464
Test name
Test status
Simulation time 561607191 ps
CPU time 2.5 seconds
Started Feb 29 12:52:58 PM PST 24
Finished Feb 29 12:53:00 PM PST 24
Peak memory 197172 kb
Host smart-7f554a3c-1f6a-4c88-a84e-6ed877bf9520
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401064930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.3401064930
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.4244679032
Short name T528
Test name
Test status
Simulation time 137287381 ps
CPU time 1.13 seconds
Started Feb 29 12:52:44 PM PST 24
Finished Feb 29 12:52:45 PM PST 24
Peak memory 194656 kb
Host smart-45dc5ae2-9210-4506-bb12-248ddd0df55d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244679032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.4244679032
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1716338366
Short name T529
Test name
Test status
Simulation time 56914294 ps
CPU time 1.42 seconds
Started Feb 29 12:52:33 PM PST 24
Finished Feb 29 12:52:35 PM PST 24
Peak memory 197144 kb
Host smart-bee7e8c0-ce4e-4f67-aebd-bcda2da0f5f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716338366 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.1716338366
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3468338814
Short name T522
Test name
Test status
Simulation time 11960792 ps
CPU time 0.55 seconds
Started Feb 29 12:52:46 PM PST 24
Finished Feb 29 12:52:47 PM PST 24
Peak memory 182320 kb
Host smart-bfc405fa-e83c-4988-81f1-3c5b2e40b9c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468338814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3468338814
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3022662896
Short name T451
Test name
Test status
Simulation time 17160047 ps
CPU time 0.55 seconds
Started Feb 29 12:52:44 PM PST 24
Finished Feb 29 12:52:45 PM PST 24
Peak memory 182216 kb
Host smart-04630517-68d5-4472-b993-c8c3831f4f6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022662896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3022662896
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1634671976
Short name T82
Test name
Test status
Simulation time 62950474 ps
CPU time 0.76 seconds
Started Feb 29 12:52:37 PM PST 24
Finished Feb 29 12:52:38 PM PST 24
Peak memory 192692 kb
Host smart-e68dc29b-40f6-4ba1-ab80-dec2688d43ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634671976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1634671976
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.4124245560
Short name T484
Test name
Test status
Simulation time 128002204 ps
CPU time 1.6 seconds
Started Feb 29 12:52:38 PM PST 24
Finished Feb 29 12:52:41 PM PST 24
Peak memory 197208 kb
Host smart-825571e5-b870-4622-b404-55f4825a98dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124245560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.4124245560
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2183096249
Short name T546
Test name
Test status
Simulation time 217810163 ps
CPU time 0.8 seconds
Started Feb 29 12:52:30 PM PST 24
Finished Feb 29 12:52:31 PM PST 24
Peak memory 192864 kb
Host smart-72ecb1ea-427d-4415-8ff0-e1ebf769494a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183096249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2183096249
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.451437700
Short name T35
Test name
Test status
Simulation time 56990984 ps
CPU time 0.79 seconds
Started Feb 29 12:52:30 PM PST 24
Finished Feb 29 12:52:32 PM PST 24
Peak memory 195688 kb
Host smart-e85734db-40cd-427d-be93-061f35fb27da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451437700 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.451437700
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2242038406
Short name T88
Test name
Test status
Simulation time 12461322 ps
CPU time 0.56 seconds
Started Feb 29 12:52:43 PM PST 24
Finished Feb 29 12:52:45 PM PST 24
Peak memory 182452 kb
Host smart-de8a2e97-3ae0-40d9-9160-b692e7e476ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242038406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2242038406
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2227202435
Short name T461
Test name
Test status
Simulation time 25253434 ps
CPU time 0.56 seconds
Started Feb 29 12:52:45 PM PST 24
Finished Feb 29 12:52:46 PM PST 24
Peak memory 182300 kb
Host smart-9fce58c9-5c72-420e-b4dd-73e04e063772
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227202435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2227202435
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1990673852
Short name T83
Test name
Test status
Simulation time 38602662 ps
CPU time 0.61 seconds
Started Feb 29 12:52:33 PM PST 24
Finished Feb 29 12:52:34 PM PST 24
Peak memory 191668 kb
Host smart-f0b85c01-94b2-480a-87c5-da23420d824a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990673852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.1990673852
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3918391996
Short name T449
Test name
Test status
Simulation time 548621629 ps
CPU time 2.62 seconds
Started Feb 29 12:52:38 PM PST 24
Finished Feb 29 12:52:41 PM PST 24
Peak memory 197212 kb
Host smart-5a6024ce-0a07-459e-8f72-a3409c41f9f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918391996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3918391996
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.4123454549
Short name T575
Test name
Test status
Simulation time 444991764 ps
CPU time 1.07 seconds
Started Feb 29 12:52:27 PM PST 24
Finished Feb 29 12:52:29 PM PST 24
Peak memory 194320 kb
Host smart-0d240194-09f7-49db-93e8-5d685d719f55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123454549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.4123454549
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1539576671
Short name T465
Test name
Test status
Simulation time 446551608 ps
CPU time 0.72 seconds
Started Feb 29 12:52:37 PM PST 24
Finished Feb 29 12:52:38 PM PST 24
Peak memory 194596 kb
Host smart-821de64e-2be5-449e-a771-79d8c5831f2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539576671 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1539576671
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2696577955
Short name T468
Test name
Test status
Simulation time 29270979 ps
CPU time 0.66 seconds
Started Feb 29 12:52:38 PM PST 24
Finished Feb 29 12:52:40 PM PST 24
Peak memory 182456 kb
Host smart-78d8bf33-584b-482a-8b2a-dd595da29cdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696577955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2696577955
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2751044503
Short name T446
Test name
Test status
Simulation time 89531273 ps
CPU time 0.56 seconds
Started Feb 29 12:52:53 PM PST 24
Finished Feb 29 12:52:54 PM PST 24
Peak memory 182244 kb
Host smart-2f17f5a5-079f-42b2-98a7-eb28cf4a892e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751044503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2751044503
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2161396118
Short name T548
Test name
Test status
Simulation time 63982687 ps
CPU time 0.61 seconds
Started Feb 29 12:52:47 PM PST 24
Finished Feb 29 12:52:48 PM PST 24
Peak memory 190952 kb
Host smart-137b2136-9c6d-432d-97a4-970a95eb4204
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161396118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2161396118
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2478185635
Short name T510
Test name
Test status
Simulation time 858189605 ps
CPU time 1.41 seconds
Started Feb 29 12:52:36 PM PST 24
Finished Feb 29 12:52:38 PM PST 24
Peak memory 197240 kb
Host smart-44ff9ae6-e244-41b4-9c34-2d812f7c05f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478185635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2478185635
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1425257283
Short name T554
Test name
Test status
Simulation time 48438046 ps
CPU time 0.82 seconds
Started Feb 29 12:52:38 PM PST 24
Finished Feb 29 12:52:39 PM PST 24
Peak memory 193072 kb
Host smart-657766fa-e944-4ff1-b5ee-c268cf79ba08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425257283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1425257283
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1628969905
Short name T489
Test name
Test status
Simulation time 227669440 ps
CPU time 0.74 seconds
Started Feb 29 12:52:46 PM PST 24
Finished Feb 29 12:52:47 PM PST 24
Peak memory 194644 kb
Host smart-816de2cd-f168-4014-bd03-2827f3835b7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628969905 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.1628969905
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.4118417363
Short name T470
Test name
Test status
Simulation time 48075533 ps
CPU time 0.54 seconds
Started Feb 29 12:52:45 PM PST 24
Finished Feb 29 12:52:46 PM PST 24
Peak memory 182468 kb
Host smart-9cdc9808-edb4-4f9a-af8b-9270fbdd83e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118417363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.4118417363
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3129745550
Short name T447
Test name
Test status
Simulation time 146982506 ps
CPU time 0.56 seconds
Started Feb 29 12:52:50 PM PST 24
Finished Feb 29 12:52:51 PM PST 24
Peak memory 181708 kb
Host smart-7fc24435-adee-4f4d-862a-dc1b5211fa98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129745550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3129745550
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3021730496
Short name T537
Test name
Test status
Simulation time 84726234 ps
CPU time 0.62 seconds
Started Feb 29 12:52:43 PM PST 24
Finished Feb 29 12:52:45 PM PST 24
Peak memory 191688 kb
Host smart-8ffe7200-9ed3-4edf-95b1-50cdaf868d3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021730496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.3021730496
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3231127970
Short name T508
Test name
Test status
Simulation time 654124581 ps
CPU time 2.1 seconds
Started Feb 29 12:52:41 PM PST 24
Finished Feb 29 12:52:43 PM PST 24
Peak memory 197224 kb
Host smart-bcac7ccf-50e2-403d-9932-09d467f975a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231127970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3231127970
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3311449593
Short name T525
Test name
Test status
Simulation time 50222432 ps
CPU time 0.84 seconds
Started Feb 29 12:52:40 PM PST 24
Finished Feb 29 12:52:45 PM PST 24
Peak memory 193388 kb
Host smart-a44939db-d667-4806-b1ce-0e64f56dc1d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311449593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3311449593
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2693553404
Short name T547
Test name
Test status
Simulation time 95113806 ps
CPU time 0.69 seconds
Started Feb 29 12:53:02 PM PST 24
Finished Feb 29 12:53:03 PM PST 24
Peak memory 195068 kb
Host smart-9e518657-2a77-4062-9315-3687e89cd6fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693553404 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2693553404
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1934480587
Short name T91
Test name
Test status
Simulation time 13868161 ps
CPU time 0.55 seconds
Started Feb 29 12:52:31 PM PST 24
Finished Feb 29 12:52:32 PM PST 24
Peak memory 182056 kb
Host smart-81635e70-5398-4009-8a21-3022b8022558
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934480587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1934480587
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1994624133
Short name T445
Test name
Test status
Simulation time 20426522 ps
CPU time 0.57 seconds
Started Feb 29 12:52:45 PM PST 24
Finished Feb 29 12:52:46 PM PST 24
Peak memory 182192 kb
Host smart-08063233-5943-46b0-bf41-ee2054c8cc6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994624133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1994624133
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1282361675
Short name T519
Test name
Test status
Simulation time 28686597 ps
CPU time 0.72 seconds
Started Feb 29 12:52:50 PM PST 24
Finished Feb 29 12:52:51 PM PST 24
Peak memory 191776 kb
Host smart-405da4a8-8533-4754-8c9f-36d1dbd80f45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282361675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.1282361675
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1051285920
Short name T518
Test name
Test status
Simulation time 83097284 ps
CPU time 2.24 seconds
Started Feb 29 12:52:44 PM PST 24
Finished Feb 29 12:52:47 PM PST 24
Peak memory 197240 kb
Host smart-3dadfc4c-707e-4c3b-b1c9-5abe6144239a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051285920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1051285920
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2548685709
Short name T536
Test name
Test status
Simulation time 530020249 ps
CPU time 1.32 seconds
Started Feb 29 12:52:32 PM PST 24
Finished Feb 29 12:52:34 PM PST 24
Peak memory 194828 kb
Host smart-370f5f5f-341a-4513-ab5b-d62fa04a2768
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548685709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2548685709
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.40340736
Short name T551
Test name
Test status
Simulation time 61216265 ps
CPU time 0.6 seconds
Started Feb 29 12:52:44 PM PST 24
Finished Feb 29 12:52:46 PM PST 24
Peak memory 192840 kb
Host smart-c2534295-2f23-4bdd-89a6-6c750da9d6d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40340736 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.40340736
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3589959995
Short name T557
Test name
Test status
Simulation time 40660771 ps
CPU time 0.61 seconds
Started Feb 29 12:52:52 PM PST 24
Finished Feb 29 12:52:53 PM PST 24
Peak memory 191780 kb
Host smart-44c8a7fe-69df-4abf-8f25-f497b2d16e00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589959995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3589959995
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3396117160
Short name T455
Test name
Test status
Simulation time 154656441 ps
CPU time 0.55 seconds
Started Feb 29 12:52:42 PM PST 24
Finished Feb 29 12:52:43 PM PST 24
Peak memory 182176 kb
Host smart-17b0fa31-db39-49f1-894c-4c3c048d7f22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396117160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3396117160
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1205667129
Short name T555
Test name
Test status
Simulation time 36515820 ps
CPU time 0.76 seconds
Started Feb 29 12:52:43 PM PST 24
Finished Feb 29 12:52:49 PM PST 24
Peak memory 192764 kb
Host smart-1719d0cb-60c9-4a34-8b3b-27b0b312c37d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205667129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1205667129
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.193672151
Short name T498
Test name
Test status
Simulation time 51092318 ps
CPU time 2.36 seconds
Started Feb 29 12:52:30 PM PST 24
Finished Feb 29 12:52:33 PM PST 24
Peak memory 197212 kb
Host smart-9263bea7-62b6-4b10-9893-069f8ff9a454
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193672151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.193672151
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1725271529
Short name T577
Test name
Test status
Simulation time 115085032 ps
CPU time 1.12 seconds
Started Feb 29 12:52:39 PM PST 24
Finished Feb 29 12:52:41 PM PST 24
Peak memory 182708 kb
Host smart-15c4eb2f-2ff8-4e64-82a0-5210f8d3ee18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725271529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1725271529
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.4046885937
Short name T550
Test name
Test status
Simulation time 81525080 ps
CPU time 0.74 seconds
Started Feb 29 12:52:35 PM PST 24
Finished Feb 29 12:52:36 PM PST 24
Peak memory 194908 kb
Host smart-feb2e2ee-0eb9-44dc-94f3-441ab13b1d6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046885937 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.4046885937
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1321486160
Short name T516
Test name
Test status
Simulation time 41635523 ps
CPU time 0.52 seconds
Started Feb 29 12:52:44 PM PST 24
Finished Feb 29 12:52:45 PM PST 24
Peak memory 182072 kb
Host smart-3b98c268-e859-4e0b-8163-ef096dcc86a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321486160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1321486160
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.593494486
Short name T491
Test name
Test status
Simulation time 31695904 ps
CPU time 0.55 seconds
Started Feb 29 12:52:29 PM PST 24
Finished Feb 29 12:52:30 PM PST 24
Peak memory 182240 kb
Host smart-900c11b0-0bc9-4567-b2a9-fc5e4c5e5238
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593494486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.593494486
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1268436606
Short name T94
Test name
Test status
Simulation time 21517065 ps
CPU time 0.63 seconds
Started Feb 29 12:52:46 PM PST 24
Finished Feb 29 12:52:48 PM PST 24
Peak memory 191700 kb
Host smart-6848c313-a36f-4f59-a0dc-7a1546327a0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268436606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.1268436606
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.4198909924
Short name T483
Test name
Test status
Simulation time 136443695 ps
CPU time 1.63 seconds
Started Feb 29 12:52:30 PM PST 24
Finished Feb 29 12:52:32 PM PST 24
Peak memory 197152 kb
Host smart-9805195f-d1e4-415e-9d7a-a8218d6ce796
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198909924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.4198909924
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1839756119
Short name T98
Test name
Test status
Simulation time 85841151 ps
CPU time 1.06 seconds
Started Feb 29 12:52:46 PM PST 24
Finished Feb 29 12:52:48 PM PST 24
Peak memory 194596 kb
Host smart-5519baca-d944-4375-9505-20b1c3f94cf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839756119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1839756119
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1332829586
Short name T96
Test name
Test status
Simulation time 27674470 ps
CPU time 0.75 seconds
Started Feb 29 12:52:23 PM PST 24
Finished Feb 29 12:52:24 PM PST 24
Peak memory 182404 kb
Host smart-d5f88f0c-bf09-443c-b9e1-e83243f185b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332829586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1332829586
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.545899153
Short name T87
Test name
Test status
Simulation time 1361233708 ps
CPU time 3.13 seconds
Started Feb 29 12:52:26 PM PST 24
Finished Feb 29 12:52:31 PM PST 24
Peak memory 193324 kb
Host smart-ddfa5ce3-7d63-465f-a61e-f8d1c13847f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545899153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_b
ash.545899153
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.722272594
Short name T570
Test name
Test status
Simulation time 15687071 ps
CPU time 0.53 seconds
Started Feb 29 12:52:38 PM PST 24
Finished Feb 29 12:52:39 PM PST 24
Peak memory 182480 kb
Host smart-942347d2-52ec-4579-a6a7-21e2c3434961
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722272594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.722272594
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.4050438556
Short name T553
Test name
Test status
Simulation time 143332660 ps
CPU time 0.78 seconds
Started Feb 29 12:52:36 PM PST 24
Finished Feb 29 12:52:37 PM PST 24
Peak memory 195160 kb
Host smart-fef32a84-70ba-4596-9628-17b90586480a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050438556 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.4050438556
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.856269887
Short name T34
Test name
Test status
Simulation time 12494852 ps
CPU time 0.58 seconds
Started Feb 29 12:52:25 PM PST 24
Finished Feb 29 12:52:26 PM PST 24
Peak memory 182068 kb
Host smart-66e6b78d-d5b1-421c-b57a-7b29b8641e27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856269887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.856269887
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.853974536
Short name T458
Test name
Test status
Simulation time 14983498 ps
CPU time 0.55 seconds
Started Feb 29 12:52:31 PM PST 24
Finished Feb 29 12:52:32 PM PST 24
Peak memory 181692 kb
Host smart-b955bdee-cac7-4932-ad87-067a837dae0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853974536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.853974536
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2975391260
Short name T93
Test name
Test status
Simulation time 19044859 ps
CPU time 0.6 seconds
Started Feb 29 12:52:35 PM PST 24
Finished Feb 29 12:52:36 PM PST 24
Peak memory 190996 kb
Host smart-650e5b1b-5e63-4988-bb6c-595c44cd8219
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975391260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2975391260
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.663550556
Short name T452
Test name
Test status
Simulation time 112950502 ps
CPU time 1.48 seconds
Started Feb 29 12:52:22 PM PST 24
Finished Feb 29 12:52:23 PM PST 24
Peak memory 197004 kb
Host smart-7fa3aa35-3af2-4e9d-a7f9-2b2b3f8fd76b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663550556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.663550556
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.746271747
Short name T560
Test name
Test status
Simulation time 88206531 ps
CPU time 0.79 seconds
Started Feb 29 12:52:20 PM PST 24
Finished Feb 29 12:52:21 PM PST 24
Peak memory 193144 kb
Host smart-2d4ef5f3-7c16-4c16-9c6c-504f3b98a1f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746271747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_int
g_err.746271747
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.502405470
Short name T495
Test name
Test status
Simulation time 17358451 ps
CPU time 0.55 seconds
Started Feb 29 12:52:43 PM PST 24
Finished Feb 29 12:52:44 PM PST 24
Peak memory 182248 kb
Host smart-6b6cd004-219e-48ed-9572-cac519d3d0ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502405470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.502405470
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3663391040
Short name T568
Test name
Test status
Simulation time 41091716 ps
CPU time 0.52 seconds
Started Feb 29 12:52:50 PM PST 24
Finished Feb 29 12:52:51 PM PST 24
Peak memory 181696 kb
Host smart-93af553f-2a94-4e6d-b004-5c56a2135eae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663391040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3663391040
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1460204590
Short name T485
Test name
Test status
Simulation time 18981134 ps
CPU time 0.6 seconds
Started Feb 29 12:52:51 PM PST 24
Finished Feb 29 12:52:51 PM PST 24
Peak memory 182232 kb
Host smart-3bdcbfce-d55c-4c08-967d-5ba829e00cb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460204590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.1460204590
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3204027934
Short name T463
Test name
Test status
Simulation time 44152652 ps
CPU time 0.54 seconds
Started Feb 29 12:52:44 PM PST 24
Finished Feb 29 12:52:46 PM PST 24
Peak memory 182212 kb
Host smart-c08edee8-1603-49e9-bcc9-769f43dc8a51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204027934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3204027934
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.4225041194
Short name T532
Test name
Test status
Simulation time 15647625 ps
CPU time 0.52 seconds
Started Feb 29 12:52:40 PM PST 24
Finished Feb 29 12:52:40 PM PST 24
Peak memory 181672 kb
Host smart-1bb8b61c-9a00-4383-aa93-5bb935239057
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225041194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.4225041194
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.245787700
Short name T563
Test name
Test status
Simulation time 49274557 ps
CPU time 0.54 seconds
Started Feb 29 12:52:33 PM PST 24
Finished Feb 29 12:52:34 PM PST 24
Peak memory 182292 kb
Host smart-ef39a063-62d4-4a9e-8c01-e5265ce82603
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245787700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.245787700
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3780284265
Short name T572
Test name
Test status
Simulation time 13437108 ps
CPU time 0.54 seconds
Started Feb 29 12:52:33 PM PST 24
Finished Feb 29 12:52:34 PM PST 24
Peak memory 182236 kb
Host smart-cc1a2b5f-1725-455c-a5cf-c5af69fafbd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780284265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.3780284265
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1064561457
Short name T535
Test name
Test status
Simulation time 76324754 ps
CPU time 0.51 seconds
Started Feb 29 12:52:44 PM PST 24
Finished Feb 29 12:52:45 PM PST 24
Peak memory 181688 kb
Host smart-b3ed42d5-58f8-4bb5-adc9-b4437586f4a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064561457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1064561457
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2776954289
Short name T466
Test name
Test status
Simulation time 103085567 ps
CPU time 0.56 seconds
Started Feb 29 12:52:50 PM PST 24
Finished Feb 29 12:52:51 PM PST 24
Peak memory 181696 kb
Host smart-77107251-5457-47a9-97f4-9a9b19502098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776954289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2776954289
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.981870060
Short name T454
Test name
Test status
Simulation time 26484695 ps
CPU time 0.52 seconds
Started Feb 29 12:52:39 PM PST 24
Finished Feb 29 12:52:40 PM PST 24
Peak memory 181584 kb
Host smart-3b133101-8d87-4336-98cf-963046d6ed4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981870060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.981870060
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3249242917
Short name T559
Test name
Test status
Simulation time 16815911 ps
CPU time 0.61 seconds
Started Feb 29 12:52:25 PM PST 24
Finished Feb 29 12:52:26 PM PST 24
Peak memory 182524 kb
Host smart-a592c5cf-88bb-4825-ae68-f946f4fba09f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249242917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3249242917
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.101641926
Short name T574
Test name
Test status
Simulation time 248053608 ps
CPU time 2.23 seconds
Started Feb 29 12:52:23 PM PST 24
Finished Feb 29 12:52:26 PM PST 24
Peak memory 190800 kb
Host smart-ae12b62d-a086-42c9-8033-06c6e962c06f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101641926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.101641926
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2114415148
Short name T482
Test name
Test status
Simulation time 20383911 ps
CPU time 0.6 seconds
Started Feb 29 12:52:25 PM PST 24
Finished Feb 29 12:52:26 PM PST 24
Peak memory 191728 kb
Host smart-cd2812e3-be31-4dd6-812d-88f0443c278f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114415148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.2114415148
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.973900399
Short name T538
Test name
Test status
Simulation time 23056919 ps
CPU time 0.83 seconds
Started Feb 29 12:52:28 PM PST 24
Finished Feb 29 12:52:29 PM PST 24
Peak memory 196684 kb
Host smart-4b7985c0-2f23-4f23-842a-d15762791729
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973900399 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.973900399
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3615114669
Short name T478
Test name
Test status
Simulation time 13771393 ps
CPU time 0.57 seconds
Started Feb 29 12:52:23 PM PST 24
Finished Feb 29 12:52:24 PM PST 24
Peak memory 182508 kb
Host smart-dcbea55b-f7b3-4dad-b5a3-d0b0c1ae686e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615114669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3615114669
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.4097192562
Short name T490
Test name
Test status
Simulation time 13050914 ps
CPU time 0.53 seconds
Started Feb 29 12:52:28 PM PST 24
Finished Feb 29 12:52:30 PM PST 24
Peak memory 181720 kb
Host smart-130b9d04-4d3e-43f4-81b8-1ab403a6c7d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097192562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.4097192562
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.126319458
Short name T81
Test name
Test status
Simulation time 58320825 ps
CPU time 0.7 seconds
Started Feb 29 12:52:37 PM PST 24
Finished Feb 29 12:52:38 PM PST 24
Peak memory 192740 kb
Host smart-717fca81-50c7-4d3b-bcbf-29dffe1d6e4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126319458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_tim
er_same_csr_outstanding.126319458
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.996427028
Short name T505
Test name
Test status
Simulation time 39559760 ps
CPU time 1.72 seconds
Started Feb 29 12:52:59 PM PST 24
Finished Feb 29 12:53:01 PM PST 24
Peak memory 197088 kb
Host smart-7c5cadf6-3ff1-48f7-9737-caaa0d70d41a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996427028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.996427028
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.4056726202
Short name T32
Test name
Test status
Simulation time 369819766 ps
CPU time 1.3 seconds
Started Feb 29 12:52:27 PM PST 24
Finished Feb 29 12:52:29 PM PST 24
Peak memory 182864 kb
Host smart-17b1070d-dbd6-4383-92fd-ba77b2aa356e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056726202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.4056726202
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1048382503
Short name T496
Test name
Test status
Simulation time 25772141 ps
CPU time 0.52 seconds
Started Feb 29 12:52:41 PM PST 24
Finished Feb 29 12:52:42 PM PST 24
Peak memory 181680 kb
Host smart-d1f309a3-a607-46c0-a7b7-463b43f6e89e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048382503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1048382503
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2034356170
Short name T534
Test name
Test status
Simulation time 76990866 ps
CPU time 0.55 seconds
Started Feb 29 12:52:43 PM PST 24
Finished Feb 29 12:52:45 PM PST 24
Peak memory 182232 kb
Host smart-73402ce8-c86a-4fea-b6b5-e5d1f43ad61c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034356170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2034356170
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2510779690
Short name T549
Test name
Test status
Simulation time 21268547 ps
CPU time 0.54 seconds
Started Feb 29 12:52:47 PM PST 24
Finished Feb 29 12:52:48 PM PST 24
Peak memory 181896 kb
Host smart-a92f8bbd-7f42-4e54-813d-740eecffc4b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510779690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.2510779690
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1329764806
Short name T552
Test name
Test status
Simulation time 51163843 ps
CPU time 0.55 seconds
Started Feb 29 12:52:56 PM PST 24
Finished Feb 29 12:52:58 PM PST 24
Peak memory 182248 kb
Host smart-b09e54f1-d769-4124-b016-a4aa1a750480
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329764806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1329764806
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2086411159
Short name T467
Test name
Test status
Simulation time 17369669 ps
CPU time 0.56 seconds
Started Feb 29 12:52:48 PM PST 24
Finished Feb 29 12:52:49 PM PST 24
Peak memory 181764 kb
Host smart-8b8c1ee1-764d-49b9-af61-cabdab76e29c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086411159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2086411159
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.563720927
Short name T540
Test name
Test status
Simulation time 54833479 ps
CPU time 0.55 seconds
Started Feb 29 12:52:56 PM PST 24
Finished Feb 29 12:52:58 PM PST 24
Peak memory 182248 kb
Host smart-a6290204-3b40-4c7a-be63-aa5f5eecc270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563720927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.563720927
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2053236886
Short name T492
Test name
Test status
Simulation time 13773139 ps
CPU time 0.51 seconds
Started Feb 29 12:53:11 PM PST 24
Finished Feb 29 12:53:12 PM PST 24
Peak memory 181760 kb
Host smart-87706878-b33b-4ea2-bd12-c9202b8fc83e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053236886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2053236886
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.751976213
Short name T460
Test name
Test status
Simulation time 16312668 ps
CPU time 0.56 seconds
Started Feb 29 12:52:51 PM PST 24
Finished Feb 29 12:52:52 PM PST 24
Peak memory 182228 kb
Host smart-51d0f03e-4820-47c0-b217-029bc39e913c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751976213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.751976213
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.4116497983
Short name T474
Test name
Test status
Simulation time 12841294 ps
CPU time 0.56 seconds
Started Feb 29 12:52:48 PM PST 24
Finished Feb 29 12:52:49 PM PST 24
Peak memory 181732 kb
Host smart-039509a8-e243-4ec6-82da-40780e25167d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116497983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.4116497983
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2181724387
Short name T562
Test name
Test status
Simulation time 42279973 ps
CPU time 0.6 seconds
Started Feb 29 12:52:45 PM PST 24
Finished Feb 29 12:52:46 PM PST 24
Peak memory 182308 kb
Host smart-848b0a58-fd91-4001-891f-7a823aea338e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181724387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2181724387
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2460417803
Short name T488
Test name
Test status
Simulation time 165630502 ps
CPU time 0.73 seconds
Started Feb 29 12:52:33 PM PST 24
Finished Feb 29 12:52:34 PM PST 24
Peak memory 182528 kb
Host smart-055c8a2f-e5e4-4e84-a0f4-6651d57157a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460417803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2460417803
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1251309344
Short name T506
Test name
Test status
Simulation time 487675851 ps
CPU time 1.6 seconds
Started Feb 29 12:52:29 PM PST 24
Finished Feb 29 12:52:31 PM PST 24
Peak memory 191796 kb
Host smart-db943a3f-6091-492c-b6fb-254c2593e8d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251309344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.1251309344
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.316149234
Short name T56
Test name
Test status
Simulation time 16971185 ps
CPU time 0.56 seconds
Started Feb 29 12:52:22 PM PST 24
Finished Feb 29 12:52:23 PM PST 24
Peak memory 182484 kb
Host smart-9a2bf6e2-96e9-4fb5-a27e-08bac7568788
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316149234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re
set.316149234
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1166127879
Short name T479
Test name
Test status
Simulation time 130239124 ps
CPU time 0.83 seconds
Started Feb 29 12:52:35 PM PST 24
Finished Feb 29 12:52:36 PM PST 24
Peak memory 196320 kb
Host smart-88e0eeba-a373-435b-bf7b-b4f117d9e441
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166127879 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1166127879
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3739597584
Short name T556
Test name
Test status
Simulation time 37196584 ps
CPU time 0.53 seconds
Started Feb 29 12:52:26 PM PST 24
Finished Feb 29 12:52:28 PM PST 24
Peak memory 181976 kb
Host smart-b4f744de-261d-499e-92af-0446994c5396
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739597584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3739597584
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.534197263
Short name T507
Test name
Test status
Simulation time 35048214 ps
CPU time 0.54 seconds
Started Feb 29 12:52:30 PM PST 24
Finished Feb 29 12:52:30 PM PST 24
Peak memory 182284 kb
Host smart-053be0ef-c325-43f6-a452-33013d2dcb2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534197263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.534197263
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3289662814
Short name T571
Test name
Test status
Simulation time 32081483 ps
CPU time 0.73 seconds
Started Feb 29 12:52:32 PM PST 24
Finished Feb 29 12:52:33 PM PST 24
Peak memory 191644 kb
Host smart-a289050c-5b4f-48e8-b255-3d21e6b70d59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289662814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.3289662814
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3265858735
Short name T42
Test name
Test status
Simulation time 115628192 ps
CPU time 1.22 seconds
Started Feb 29 12:52:29 PM PST 24
Finished Feb 29 12:52:30 PM PST 24
Peak memory 196976 kb
Host smart-0d99cb84-d223-4e0d-8580-7fd9daad1286
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265858735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3265858735
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2920029837
Short name T472
Test name
Test status
Simulation time 87837199 ps
CPU time 1.11 seconds
Started Feb 29 12:52:26 PM PST 24
Finished Feb 29 12:52:28 PM PST 24
Peak memory 182624 kb
Host smart-7cbad061-d243-4b06-933f-ebdebdca875c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920029837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2920029837
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2566767187
Short name T504
Test name
Test status
Simulation time 102229443 ps
CPU time 0.56 seconds
Started Feb 29 12:53:00 PM PST 24
Finished Feb 29 12:53:01 PM PST 24
Peak memory 182164 kb
Host smart-4cc19e87-b219-47a8-b4ad-933898c8fec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566767187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2566767187
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3603168480
Short name T567
Test name
Test status
Simulation time 12332022 ps
CPU time 0.54 seconds
Started Feb 29 12:52:46 PM PST 24
Finished Feb 29 12:52:47 PM PST 24
Peak memory 182276 kb
Host smart-04c7a445-42fb-4104-9ca8-d27c542f2db5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603168480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3603168480
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1385996758
Short name T500
Test name
Test status
Simulation time 40818432 ps
CPU time 0.62 seconds
Started Feb 29 12:52:41 PM PST 24
Finished Feb 29 12:52:42 PM PST 24
Peak memory 182320 kb
Host smart-a5204398-681f-426e-8c3b-0d77760c14a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385996758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1385996758
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2194179131
Short name T526
Test name
Test status
Simulation time 102382416 ps
CPU time 0.6 seconds
Started Feb 29 12:52:44 PM PST 24
Finished Feb 29 12:52:46 PM PST 24
Peak memory 182512 kb
Host smart-ff2b1cef-2e72-4bec-8bb5-f6d72283bcd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194179131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2194179131
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1188669021
Short name T524
Test name
Test status
Simulation time 16324343 ps
CPU time 0.54 seconds
Started Feb 29 12:52:46 PM PST 24
Finished Feb 29 12:52:47 PM PST 24
Peak memory 182292 kb
Host smart-4b4d9f05-e7ed-40bc-8e0c-1d9225e8b64e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188669021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1188669021
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3429646768
Short name T561
Test name
Test status
Simulation time 48086499 ps
CPU time 0.51 seconds
Started Feb 29 12:53:12 PM PST 24
Finished Feb 29 12:53:13 PM PST 24
Peak memory 181904 kb
Host smart-b0f80c31-0cb4-49fb-87e3-92fc1e1bc790
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429646768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3429646768
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3168134059
Short name T512
Test name
Test status
Simulation time 13715704 ps
CPU time 0.54 seconds
Started Feb 29 12:52:46 PM PST 24
Finished Feb 29 12:52:47 PM PST 24
Peak memory 181696 kb
Host smart-affba3e9-6693-4473-a3e8-ccfd12c636f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168134059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3168134059
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1351022166
Short name T473
Test name
Test status
Simulation time 15549408 ps
CPU time 0.56 seconds
Started Feb 29 12:52:46 PM PST 24
Finished Feb 29 12:52:47 PM PST 24
Peak memory 182208 kb
Host smart-c7bff571-1416-47eb-8e1e-d47d11c00f0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351022166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1351022166
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2800143944
Short name T569
Test name
Test status
Simulation time 14408275 ps
CPU time 0.51 seconds
Started Feb 29 12:52:51 PM PST 24
Finished Feb 29 12:52:51 PM PST 24
Peak memory 181572 kb
Host smart-879c7c29-a7ab-40d5-9c70-b5435555590c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800143944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.2800143944
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3827792882
Short name T480
Test name
Test status
Simulation time 24147189 ps
CPU time 0.54 seconds
Started Feb 29 12:52:50 PM PST 24
Finished Feb 29 12:52:50 PM PST 24
Peak memory 181604 kb
Host smart-fddd547e-8df8-4057-a7d3-8b38d00ea5ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827792882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3827792882
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1788409828
Short name T462
Test name
Test status
Simulation time 51066347 ps
CPU time 0.77 seconds
Started Feb 29 12:52:33 PM PST 24
Finished Feb 29 12:52:34 PM PST 24
Peak memory 194764 kb
Host smart-a24f7832-e0bc-43ed-8dab-78a9540ce596
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788409828 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1788409828
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.428840057
Short name T54
Test name
Test status
Simulation time 13271752 ps
CPU time 0.55 seconds
Started Feb 29 12:52:25 PM PST 24
Finished Feb 29 12:52:26 PM PST 24
Peak memory 182104 kb
Host smart-4ffe63cb-b0e3-425e-926b-2605fd43d50d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428840057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.428840057
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.4196069188
Short name T450
Test name
Test status
Simulation time 70809629 ps
CPU time 0.55 seconds
Started Feb 29 12:52:26 PM PST 24
Finished Feb 29 12:52:27 PM PST 24
Peak memory 182316 kb
Host smart-557653ec-70bc-488b-9685-39674841ce21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196069188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.4196069188
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2344288364
Short name T33
Test name
Test status
Simulation time 83193159 ps
CPU time 0.65 seconds
Started Feb 29 12:52:43 PM PST 24
Finished Feb 29 12:52:45 PM PST 24
Peak memory 191932 kb
Host smart-c7510442-63df-4d45-a3ab-3150934de933
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344288364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2344288364
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1817546536
Short name T486
Test name
Test status
Simulation time 398311060 ps
CPU time 3.13 seconds
Started Feb 29 12:52:24 PM PST 24
Finished Feb 29 12:52:27 PM PST 24
Peak memory 197228 kb
Host smart-6fe77563-b93e-48a5-ac7b-f757002fbbe8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817546536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1817546536
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.491958687
Short name T533
Test name
Test status
Simulation time 44840367 ps
CPU time 0.8 seconds
Started Feb 29 12:52:28 PM PST 24
Finished Feb 29 12:52:30 PM PST 24
Peak memory 182824 kb
Host smart-642755a0-f6dc-44c2-acd1-cf1c9e56b92e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491958687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int
g_err.491958687
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3998486648
Short name T459
Test name
Test status
Simulation time 16877942 ps
CPU time 0.59 seconds
Started Feb 29 12:52:27 PM PST 24
Finished Feb 29 12:52:28 PM PST 24
Peak memory 192228 kb
Host smart-31eb5ec5-46c0-4d66-abea-c334eba09062
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998486648 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3998486648
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.4208989238
Short name T477
Test name
Test status
Simulation time 13903696 ps
CPU time 0.56 seconds
Started Feb 29 12:52:26 PM PST 24
Finished Feb 29 12:52:28 PM PST 24
Peak memory 182384 kb
Host smart-604a8258-1ac2-4491-b99b-91f581f5c8dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208989238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.4208989238
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1467408082
Short name T566
Test name
Test status
Simulation time 33368670 ps
CPU time 0.55 seconds
Started Feb 29 12:52:26 PM PST 24
Finished Feb 29 12:52:27 PM PST 24
Peak memory 182312 kb
Host smart-9723dea2-4161-4a13-a1f2-b1f2e1bf2977
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467408082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1467408082
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2343477
Short name T564
Test name
Test status
Simulation time 170759058 ps
CPU time 0.58 seconds
Started Feb 29 12:52:24 PM PST 24
Finished Feb 29 12:52:25 PM PST 24
Peak memory 191612 kb
Host smart-f220467f-41ad-42c8-b5b6-a2dd19156efb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_t
imer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer
_same_csr_outstanding.2343477
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.504493293
Short name T497
Test name
Test status
Simulation time 232829556 ps
CPU time 2.15 seconds
Started Feb 29 12:52:23 PM PST 24
Finished Feb 29 12:52:25 PM PST 24
Peak memory 197248 kb
Host smart-8c96b392-0619-40d0-8077-338a789e3238
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504493293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.504493293
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1326333868
Short name T31
Test name
Test status
Simulation time 124822764 ps
CPU time 1.36 seconds
Started Feb 29 12:52:26 PM PST 24
Finished Feb 29 12:52:29 PM PST 24
Peak memory 182980 kb
Host smart-06436dd6-ee95-450d-b43f-bd976fb4f4c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326333868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.1326333868
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1706779629
Short name T471
Test name
Test status
Simulation time 23392487 ps
CPU time 0.73 seconds
Started Feb 29 12:52:25 PM PST 24
Finished Feb 29 12:52:26 PM PST 24
Peak memory 194684 kb
Host smart-cc9f1702-7509-49cc-85b3-a6fb3472bd88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706779629 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1706779629
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2326556736
Short name T90
Test name
Test status
Simulation time 66567409 ps
CPU time 0.54 seconds
Started Feb 29 12:52:50 PM PST 24
Finished Feb 29 12:52:50 PM PST 24
Peak memory 182112 kb
Host smart-a256d4a7-4ad9-49a2-aa34-e714a28f6f0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326556736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2326556736
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1126223087
Short name T493
Test name
Test status
Simulation time 11712563 ps
CPU time 0.59 seconds
Started Feb 29 12:52:41 PM PST 24
Finished Feb 29 12:52:41 PM PST 24
Peak memory 182292 kb
Host smart-b5d3c6d6-c670-48dd-b573-90c912a7b206
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126223087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1126223087
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1512671610
Short name T501
Test name
Test status
Simulation time 136065417 ps
CPU time 0.84 seconds
Started Feb 29 12:52:20 PM PST 24
Finished Feb 29 12:52:21 PM PST 24
Peak memory 191364 kb
Host smart-845f94b8-435a-4858-bb39-325c3c5e41f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512671610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1512671610
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1206588469
Short name T448
Test name
Test status
Simulation time 23526080 ps
CPU time 1.23 seconds
Started Feb 29 12:52:27 PM PST 24
Finished Feb 29 12:52:33 PM PST 24
Peak memory 197244 kb
Host smart-a54c75ec-7cc9-416a-b155-1246f995e709
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206588469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1206588469
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3823857767
Short name T487
Test name
Test status
Simulation time 348847313 ps
CPU time 1.28 seconds
Started Feb 29 12:52:26 PM PST 24
Finished Feb 29 12:52:28 PM PST 24
Peak memory 194888 kb
Host smart-00598d9a-a6e2-4436-848f-1b937e563d00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823857767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3823857767
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3433328990
Short name T73
Test name
Test status
Simulation time 24132394 ps
CPU time 0.83 seconds
Started Feb 29 12:52:32 PM PST 24
Finished Feb 29 12:52:33 PM PST 24
Peak memory 195516 kb
Host smart-509e86cd-474a-4073-9c6e-10b856040b2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433328990 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3433328990
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1793448482
Short name T520
Test name
Test status
Simulation time 42160106 ps
CPU time 0.53 seconds
Started Feb 29 12:52:33 PM PST 24
Finished Feb 29 12:52:34 PM PST 24
Peak memory 181916 kb
Host smart-21487ec2-6be6-450b-bc60-aa74021a295e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793448482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1793448482
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.673062321
Short name T565
Test name
Test status
Simulation time 21253490 ps
CPU time 0.59 seconds
Started Feb 29 12:52:39 PM PST 24
Finished Feb 29 12:52:40 PM PST 24
Peak memory 191320 kb
Host smart-69cbdaeb-7309-4d24-8272-4ef253444c41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673062321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim
er_same_csr_outstanding.673062321
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1212055023
Short name T514
Test name
Test status
Simulation time 93368212 ps
CPU time 0.95 seconds
Started Feb 29 12:52:24 PM PST 24
Finished Feb 29 12:52:25 PM PST 24
Peak memory 196600 kb
Host smart-0c4b8220-8b57-457f-8cee-d629dcbdc98e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212055023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1212055023
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2165822840
Short name T97
Test name
Test status
Simulation time 53453689 ps
CPU time 0.81 seconds
Started Feb 29 12:52:25 PM PST 24
Finished Feb 29 12:52:27 PM PST 24
Peak memory 182796 kb
Host smart-3cdf5dc2-3a0e-46a1-a9b0-f6665ba7a744
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165822840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2165822840
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1283551478
Short name T469
Test name
Test status
Simulation time 58920275 ps
CPU time 0.83 seconds
Started Feb 29 12:52:39 PM PST 24
Finished Feb 29 12:52:40 PM PST 24
Peak memory 196560 kb
Host smart-ee834a00-1325-4123-9016-1954c10c40f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283551478 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1283551478
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.597714131
Short name T511
Test name
Test status
Simulation time 15297415 ps
CPU time 0.61 seconds
Started Feb 29 12:52:52 PM PST 24
Finished Feb 29 12:52:53 PM PST 24
Peak memory 182480 kb
Host smart-04dea077-684b-472d-ba4b-cea5753f85c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597714131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.597714131
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2744753905
Short name T517
Test name
Test status
Simulation time 11723640 ps
CPU time 0.52 seconds
Started Feb 29 12:52:36 PM PST 24
Finished Feb 29 12:52:37 PM PST 24
Peak memory 181896 kb
Host smart-de8903e0-9016-43ac-bc5d-01bd7cb17cdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744753905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2744753905
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1073832256
Short name T509
Test name
Test status
Simulation time 28947393 ps
CPU time 0.75 seconds
Started Feb 29 12:52:31 PM PST 24
Finished Feb 29 12:52:32 PM PST 24
Peak memory 192984 kb
Host smart-bb888fd7-4de4-486b-979f-fe0ccf6184bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073832256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1073832256
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2672038052
Short name T521
Test name
Test status
Simulation time 361457492 ps
CPU time 2.02 seconds
Started Feb 29 12:52:28 PM PST 24
Finished Feb 29 12:52:31 PM PST 24
Peak memory 197232 kb
Host smart-a3f34a93-de3f-4fe1-b659-0d40724a1da5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672038052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2672038052
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3198861907
Short name T545
Test name
Test status
Simulation time 212657152 ps
CPU time 1.24 seconds
Started Feb 29 12:52:45 PM PST 24
Finished Feb 29 12:52:47 PM PST 24
Peak memory 194684 kb
Host smart-0934587f-d2df-49e3-a06d-23f8d57af991
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198861907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3198861907
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1894402313
Short name T269
Test name
Test status
Simulation time 284939645372 ps
CPU time 511.77 seconds
Started Feb 29 01:00:44 PM PST 24
Finished Feb 29 01:09:16 PM PST 24
Peak memory 182756 kb
Host smart-31a5273a-0581-4a3d-91f8-f2268472289e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894402313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1894402313
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3748678754
Short name T385
Test name
Test status
Simulation time 46398452572 ps
CPU time 69.58 seconds
Started Feb 29 01:00:43 PM PST 24
Finished Feb 29 01:01:53 PM PST 24
Peak memory 182724 kb
Host smart-552fdbda-137f-42aa-9130-64194cfbe4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748678754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3748678754
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.933517723
Short name T415
Test name
Test status
Simulation time 378038025 ps
CPU time 0.9 seconds
Started Feb 29 01:00:45 PM PST 24
Finished Feb 29 01:00:46 PM PST 24
Peak memory 182572 kb
Host smart-0e9def99-0102-46bc-b5bc-6b8f35ee7b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933517723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.933517723
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1442339601
Short name T288
Test name
Test status
Simulation time 1834544430349 ps
CPU time 1028.48 seconds
Started Feb 29 01:00:46 PM PST 24
Finished Feb 29 01:17:55 PM PST 24
Peak memory 182768 kb
Host smart-32504084-0bf0-483c-af51-4e1b1931929e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442339601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1442339601
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2387126242
Short name T399
Test name
Test status
Simulation time 226810345317 ps
CPU time 321.56 seconds
Started Feb 29 01:00:42 PM PST 24
Finished Feb 29 01:06:04 PM PST 24
Peak memory 182728 kb
Host smart-d0939acb-2b6c-44f6-856b-1d2d9b36371f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387126242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2387126242
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.2784553273
Short name T285
Test name
Test status
Simulation time 266858775068 ps
CPU time 85.23 seconds
Started Feb 29 01:00:44 PM PST 24
Finished Feb 29 01:02:10 PM PST 24
Peak memory 182700 kb
Host smart-b5b7453b-3fd7-47c4-8e22-49d7b4bce63d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784553273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2784553273
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.671005200
Short name T19
Test name
Test status
Simulation time 50345184 ps
CPU time 0.74 seconds
Started Feb 29 01:00:46 PM PST 24
Finished Feb 29 01:00:47 PM PST 24
Peak memory 212956 kb
Host smart-8bc214b2-dc6f-4cdc-b6d0-d90483f2d442
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671005200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.671005200
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2781827873
Short name T21
Test name
Test status
Simulation time 5479344134 ps
CPU time 10.63 seconds
Started Feb 29 01:00:44 PM PST 24
Finished Feb 29 01:00:55 PM PST 24
Peak memory 182712 kb
Host smart-f8eded87-55c4-4857-a149-898feab60926
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781827873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.2781827873
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.4086230585
Short name T377
Test name
Test status
Simulation time 88911650231 ps
CPU time 16.37 seconds
Started Feb 29 01:00:50 PM PST 24
Finished Feb 29 01:01:07 PM PST 24
Peak memory 182716 kb
Host smart-2db439fa-1d0f-48c7-b694-ea594a574ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086230585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.4086230585
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.3103826924
Short name T220
Test name
Test status
Simulation time 116889612665 ps
CPU time 337.66 seconds
Started Feb 29 01:00:50 PM PST 24
Finished Feb 29 01:06:28 PM PST 24
Peak memory 193064 kb
Host smart-623c6ee6-c0f8-49e5-8757-dd26ad8cac39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103826924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3103826924
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/100.rv_timer_random.3717733426
Short name T319
Test name
Test status
Simulation time 166752235090 ps
CPU time 1000.14 seconds
Started Feb 29 01:01:37 PM PST 24
Finished Feb 29 01:18:18 PM PST 24
Peak memory 190988 kb
Host smart-551ffc9d-b4de-4c41-a72e-b4056aff4f06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717733426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3717733426
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.3055444992
Short name T177
Test name
Test status
Simulation time 119820980479 ps
CPU time 186.62 seconds
Started Feb 29 01:01:29 PM PST 24
Finished Feb 29 01:04:37 PM PST 24
Peak memory 193792 kb
Host smart-276de993-179a-4777-88d4-880dd29bbe65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055444992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3055444992
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.4008186
Short name T138
Test name
Test status
Simulation time 602767701200 ps
CPU time 1206.64 seconds
Started Feb 29 01:01:37 PM PST 24
Finished Feb 29 01:21:44 PM PST 24
Peak memory 190972 kb
Host smart-731bd908-f6de-406b-a81b-db9ced12a32f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.4008186
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.2971087784
Short name T409
Test name
Test status
Simulation time 177771595784 ps
CPU time 96.54 seconds
Started Feb 29 01:01:45 PM PST 24
Finished Feb 29 01:03:22 PM PST 24
Peak memory 182636 kb
Host smart-5a856a71-bbb1-4f29-8a91-bf066d0e94a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971087784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2971087784
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.1339353107
Short name T292
Test name
Test status
Simulation time 99657258697 ps
CPU time 162.34 seconds
Started Feb 29 01:01:45 PM PST 24
Finished Feb 29 01:04:27 PM PST 24
Peak memory 190856 kb
Host smart-5326f175-5800-491e-8816-3e79671da4ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339353107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1339353107
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.3144356379
Short name T403
Test name
Test status
Simulation time 48655767213 ps
CPU time 68.58 seconds
Started Feb 29 01:01:35 PM PST 24
Finished Feb 29 01:02:44 PM PST 24
Peak memory 182632 kb
Host smart-73a5f3ee-a96e-4075-9912-60f3d74b23c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144356379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3144356379
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.1039028623
Short name T28
Test name
Test status
Simulation time 90247533582 ps
CPU time 41.06 seconds
Started Feb 29 01:00:50 PM PST 24
Finished Feb 29 01:01:31 PM PST 24
Peak memory 182780 kb
Host smart-50d5b342-05ff-4fb5-a16e-bb9e91007af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039028623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1039028623
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.2548543546
Short name T152
Test name
Test status
Simulation time 402412830510 ps
CPU time 1061.02 seconds
Started Feb 29 01:00:43 PM PST 24
Finished Feb 29 01:18:25 PM PST 24
Peak memory 190912 kb
Host smart-deef516a-4715-4fc5-b06d-d5100da55f97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548543546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2548543546
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1467121570
Short name T433
Test name
Test status
Simulation time 49323538466 ps
CPU time 536.12 seconds
Started Feb 29 01:00:50 PM PST 24
Finished Feb 29 01:09:47 PM PST 24
Peak memory 190940 kb
Host smart-22b5f6cc-bfb8-4818-abe1-2960450c9e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467121570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1467121570
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.3566474242
Short name T80
Test name
Test status
Simulation time 3825295897859 ps
CPU time 2145.97 seconds
Started Feb 29 01:00:50 PM PST 24
Finished Feb 29 01:36:37 PM PST 24
Peak memory 193748 kb
Host smart-992ab7a6-6611-45cd-bcf8-98067af368c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566474242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.3566474242
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.850249145
Short name T41
Test name
Test status
Simulation time 84187792072 ps
CPU time 278.63 seconds
Started Feb 29 01:00:43 PM PST 24
Finished Feb 29 01:05:22 PM PST 24
Peak memory 205660 kb
Host smart-3d01103d-a437-4afc-b535-0162f0ead1ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850249145 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.850249145
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.rv_timer_random.883946766
Short name T193
Test name
Test status
Simulation time 560825806198 ps
CPU time 866.06 seconds
Started Feb 29 01:01:33 PM PST 24
Finished Feb 29 01:15:59 PM PST 24
Peak memory 191008 kb
Host smart-bf83645f-fdff-4dbd-83fc-89672c32594c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883946766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.883946766
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.89817864
Short name T135
Test name
Test status
Simulation time 64206366503 ps
CPU time 107.89 seconds
Started Feb 29 01:01:34 PM PST 24
Finished Feb 29 01:03:22 PM PST 24
Peak memory 191008 kb
Host smart-d3fc6dfd-7a1e-4dea-88c4-fde7a288f9ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89817864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.89817864
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3035439860
Short name T191
Test name
Test status
Simulation time 234442582146 ps
CPU time 753.35 seconds
Started Feb 29 01:01:33 PM PST 24
Finished Feb 29 01:14:07 PM PST 24
Peak memory 190908 kb
Host smart-4d11f048-8ea4-484c-a101-83139abf69f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035439860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3035439860
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1617741177
Short name T342
Test name
Test status
Simulation time 68121621033 ps
CPU time 80.3 seconds
Started Feb 29 01:01:34 PM PST 24
Finished Feb 29 01:02:54 PM PST 24
Peak memory 182804 kb
Host smart-e78405d5-8c52-428a-9d0e-a8987c632201
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617741177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1617741177
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.3237903567
Short name T178
Test name
Test status
Simulation time 362730057135 ps
CPU time 548.5 seconds
Started Feb 29 01:01:34 PM PST 24
Finished Feb 29 01:10:43 PM PST 24
Peak memory 190908 kb
Host smart-090ae1b8-f432-4506-b540-b4927d1fe4f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237903567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3237903567
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3203166028
Short name T410
Test name
Test status
Simulation time 303305329321 ps
CPU time 180.32 seconds
Started Feb 29 01:00:44 PM PST 24
Finished Feb 29 01:03:44 PM PST 24
Peak memory 182708 kb
Host smart-97bfd674-2bcf-4f68-92ed-f097c9e49253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203166028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3203166028
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.941802541
Short name T274
Test name
Test status
Simulation time 298456353820 ps
CPU time 400.93 seconds
Started Feb 29 01:00:49 PM PST 24
Finished Feb 29 01:07:31 PM PST 24
Peak memory 190928 kb
Host smart-70d4b245-246d-420c-9786-5f7dbb7a729d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941802541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.941802541
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2146016959
Short name T417
Test name
Test status
Simulation time 4326090217 ps
CPU time 44.4 seconds
Started Feb 29 01:00:47 PM PST 24
Finished Feb 29 01:01:31 PM PST 24
Peak memory 182712 kb
Host smart-e730a0da-e686-4f77-888f-4de771678d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146016959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2146016959
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.4173521410
Short name T68
Test name
Test status
Simulation time 341476110875 ps
CPU time 581.78 seconds
Started Feb 29 01:01:38 PM PST 24
Finished Feb 29 01:11:20 PM PST 24
Peak memory 190872 kb
Host smart-4a3a9f89-da26-4b81-9090-c2e280241e5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173521410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.4173521410
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.1086858018
Short name T394
Test name
Test status
Simulation time 19518947817 ps
CPU time 28.18 seconds
Started Feb 29 01:01:39 PM PST 24
Finished Feb 29 01:02:07 PM PST 24
Peak memory 182496 kb
Host smart-6cd519cb-4b5a-4961-85f5-1bff627ce178
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086858018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.1086858018
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.381319239
Short name T194
Test name
Test status
Simulation time 80281163673 ps
CPU time 344.43 seconds
Started Feb 29 01:01:34 PM PST 24
Finished Feb 29 01:07:19 PM PST 24
Peak memory 190892 kb
Host smart-aed72ece-c345-41e7-87b8-73b6de97c7c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381319239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.381319239
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.4178617431
Short name T183
Test name
Test status
Simulation time 231382503687 ps
CPU time 226.36 seconds
Started Feb 29 01:01:33 PM PST 24
Finished Feb 29 01:05:20 PM PST 24
Peak memory 193068 kb
Host smart-00f7eea1-7ad5-4106-99a7-615e7e67cac5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178617431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.4178617431
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3306242651
Short name T326
Test name
Test status
Simulation time 115106725365 ps
CPU time 908.27 seconds
Started Feb 29 01:01:40 PM PST 24
Finished Feb 29 01:16:48 PM PST 24
Peak memory 182688 kb
Host smart-1ec33e73-59e3-4106-9de9-bc65d23a9e1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306242651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3306242651
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.532567627
Short name T229
Test name
Test status
Simulation time 25888310280 ps
CPU time 28.59 seconds
Started Feb 29 01:01:37 PM PST 24
Finished Feb 29 01:02:06 PM PST 24
Peak memory 190792 kb
Host smart-d96055ad-d7ed-42a9-b58c-bfe987254a9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532567627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.532567627
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.4074232056
Short name T297
Test name
Test status
Simulation time 759591325809 ps
CPU time 459.21 seconds
Started Feb 29 01:00:45 PM PST 24
Finished Feb 29 01:08:24 PM PST 24
Peak memory 182736 kb
Host smart-12bc5d88-5020-4449-9114-c184b3c48cf0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074232056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.4074232056
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1618763898
Short name T362
Test name
Test status
Simulation time 120212286028 ps
CPU time 173.09 seconds
Started Feb 29 01:00:51 PM PST 24
Finished Feb 29 01:03:44 PM PST 24
Peak memory 182716 kb
Host smart-60814ba7-8546-46af-9ef8-57d53bf1e4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618763898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1618763898
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.1305758293
Short name T241
Test name
Test status
Simulation time 53123155059 ps
CPU time 102.84 seconds
Started Feb 29 01:00:45 PM PST 24
Finished Feb 29 01:02:28 PM PST 24
Peak memory 190932 kb
Host smart-5edf8eef-c5d9-4c2e-ac1d-008d2c5af2e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305758293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.1305758293
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2108957300
Short name T371
Test name
Test status
Simulation time 28471704 ps
CPU time 0.54 seconds
Started Feb 29 01:00:46 PM PST 24
Finished Feb 29 01:00:47 PM PST 24
Peak memory 182472 kb
Host smart-dcae7dfa-6878-42e9-b7e0-40920a9138f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108957300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2108957300
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.4172345865
Short name T202
Test name
Test status
Simulation time 227775186215 ps
CPU time 231.13 seconds
Started Feb 29 01:00:46 PM PST 24
Finished Feb 29 01:04:37 PM PST 24
Peak memory 190836 kb
Host smart-6622ba07-b79d-40e3-ba4f-fb4f7be32e34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172345865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.4172345865
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.1460720768
Short name T36
Test name
Test status
Simulation time 68156503633 ps
CPU time 657 seconds
Started Feb 29 01:00:46 PM PST 24
Finished Feb 29 01:11:43 PM PST 24
Peak memory 205664 kb
Host smart-3d54d450-d143-49c4-93c4-b01a32b19431
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460720768 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.1460720768
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/132.rv_timer_random.3589697553
Short name T144
Test name
Test status
Simulation time 141431177740 ps
CPU time 216.47 seconds
Started Feb 29 01:01:44 PM PST 24
Finished Feb 29 01:05:21 PM PST 24
Peak memory 193044 kb
Host smart-deca35f7-d8dc-4d73-ae9b-9ab9a3a71651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589697553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3589697553
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.1721209919
Short name T232
Test name
Test status
Simulation time 96963180894 ps
CPU time 98.91 seconds
Started Feb 29 01:01:34 PM PST 24
Finished Feb 29 01:03:13 PM PST 24
Peak memory 190956 kb
Host smart-1787c540-f562-4d7c-ba56-b846b8d6dc5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721209919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1721209919
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3470977464
Short name T142
Test name
Test status
Simulation time 325251400136 ps
CPU time 791.5 seconds
Started Feb 29 01:01:44 PM PST 24
Finished Feb 29 01:14:55 PM PST 24
Peak memory 190944 kb
Host smart-52644dfe-e85f-402e-860e-73ed32150912
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470977464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3470977464
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1462198045
Short name T173
Test name
Test status
Simulation time 347611583724 ps
CPU time 341.2 seconds
Started Feb 29 01:01:45 PM PST 24
Finished Feb 29 01:07:26 PM PST 24
Peak memory 190856 kb
Host smart-1630b68e-f97f-4e4f-b9c1-85f735fe60ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462198045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1462198045
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3920428681
Short name T163
Test name
Test status
Simulation time 113616900856 ps
CPU time 153.77 seconds
Started Feb 29 01:01:43 PM PST 24
Finished Feb 29 01:04:17 PM PST 24
Peak memory 190940 kb
Host smart-1953f21a-47bc-471e-bf38-54a2bb831b45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920428681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3920428681
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3837000228
Short name T402
Test name
Test status
Simulation time 37811552976 ps
CPU time 56.65 seconds
Started Feb 29 01:01:41 PM PST 24
Finished Feb 29 01:02:38 PM PST 24
Peak memory 182704 kb
Host smart-8c98cec7-d97b-41a9-987f-f6c349b2f37d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837000228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3837000228
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1783122145
Short name T143
Test name
Test status
Simulation time 26471405634 ps
CPU time 40.04 seconds
Started Feb 29 01:01:44 PM PST 24
Finished Feb 29 01:02:24 PM PST 24
Peak memory 193672 kb
Host smart-d53b0d04-c7b7-484a-8c2e-d21ea1f25381
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783122145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1783122145
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2003645246
Short name T392
Test name
Test status
Simulation time 199094460678 ps
CPU time 240.45 seconds
Started Feb 29 01:01:34 PM PST 24
Finished Feb 29 01:05:34 PM PST 24
Peak memory 190908 kb
Host smart-adcef532-d893-4090-8db8-a76451658cba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003645246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2003645246
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.1395338233
Short name T376
Test name
Test status
Simulation time 67844916239 ps
CPU time 66.7 seconds
Started Feb 29 01:00:48 PM PST 24
Finished Feb 29 01:01:55 PM PST 24
Peak memory 182564 kb
Host smart-f34c7741-5e54-40e2-9408-c3a4fa2d8ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395338233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.1395338233
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.1144141254
Short name T380
Test name
Test status
Simulation time 140189624 ps
CPU time 1.35 seconds
Started Feb 29 01:00:46 PM PST 24
Finished Feb 29 01:00:48 PM PST 24
Peak memory 182640 kb
Host smart-c66f5da4-0133-41b3-9147-c9400ce1aab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144141254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1144141254
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.3095576604
Short name T329
Test name
Test status
Simulation time 181866037863 ps
CPU time 296.59 seconds
Started Feb 29 01:01:36 PM PST 24
Finished Feb 29 01:06:33 PM PST 24
Peak memory 190860 kb
Host smart-9589fd6e-8e0a-458e-87ad-9ffbe5b48c89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095576604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3095576604
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.1432551380
Short name T344
Test name
Test status
Simulation time 664988003935 ps
CPU time 269.51 seconds
Started Feb 29 01:01:36 PM PST 24
Finished Feb 29 01:06:06 PM PST 24
Peak memory 190940 kb
Host smart-903daca2-255c-4e1d-9b3a-58cc4f63e0e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432551380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1432551380
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.1923536871
Short name T23
Test name
Test status
Simulation time 70120049234 ps
CPU time 470.05 seconds
Started Feb 29 01:01:46 PM PST 24
Finished Feb 29 01:09:36 PM PST 24
Peak memory 190852 kb
Host smart-2b51e985-d928-4ea6-a398-2202bb570bfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923536871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1923536871
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.2457285137
Short name T325
Test name
Test status
Simulation time 40228424566 ps
CPU time 71.61 seconds
Started Feb 29 01:01:43 PM PST 24
Finished Feb 29 01:02:55 PM PST 24
Peak memory 190936 kb
Host smart-046946d8-b07e-4b0a-88b7-c4ad3059a769
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457285137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2457285137
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.2153879618
Short name T328
Test name
Test status
Simulation time 68105951767 ps
CPU time 58.31 seconds
Started Feb 29 01:01:43 PM PST 24
Finished Feb 29 01:02:42 PM PST 24
Peak memory 190948 kb
Host smart-314deba8-02e4-4b38-bad9-b522dc433fcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153879618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2153879618
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1659583510
Short name T207
Test name
Test status
Simulation time 45334933815 ps
CPU time 80.4 seconds
Started Feb 29 01:01:44 PM PST 24
Finished Feb 29 01:03:04 PM PST 24
Peak memory 192980 kb
Host smart-4187bbe9-ad24-4803-a80c-786e5de7e59b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659583510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1659583510
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3663390656
Short name T318
Test name
Test status
Simulation time 104972972766 ps
CPU time 55 seconds
Started Feb 29 01:01:52 PM PST 24
Finished Feb 29 01:02:47 PM PST 24
Peak memory 182736 kb
Host smart-6031237e-9dfe-4fff-af59-1df478daaaab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663390656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3663390656
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3860669652
Short name T71
Test name
Test status
Simulation time 594549991144 ps
CPU time 291.81 seconds
Started Feb 29 01:01:37 PM PST 24
Finished Feb 29 01:06:29 PM PST 24
Peak memory 190912 kb
Host smart-84805b07-8491-4e46-972d-51f95fa203c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860669652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3860669652
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.4119574904
Short name T378
Test name
Test status
Simulation time 11717388556 ps
CPU time 22.34 seconds
Started Feb 29 01:00:49 PM PST 24
Finished Feb 29 01:01:11 PM PST 24
Peak memory 182740 kb
Host smart-23f85c01-27c0-44b6-a55a-743224510552
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119574904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.4119574904
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.667978177
Short name T360
Test name
Test status
Simulation time 287716545067 ps
CPU time 203.85 seconds
Started Feb 29 01:00:46 PM PST 24
Finished Feb 29 01:04:10 PM PST 24
Peak memory 182736 kb
Host smart-db7c56d8-f3b7-49ea-93fe-f13060cea447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667978177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.667978177
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.4017140198
Short name T436
Test name
Test status
Simulation time 85112389 ps
CPU time 0.66 seconds
Started Feb 29 01:00:45 PM PST 24
Finished Feb 29 01:00:46 PM PST 24
Peak memory 182500 kb
Host smart-49f4ccd2-be02-4fc0-829d-dfa5b30decba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017140198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.4017140198
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.2799912301
Short name T169
Test name
Test status
Simulation time 300316370880 ps
CPU time 912.07 seconds
Started Feb 29 01:01:36 PM PST 24
Finished Feb 29 01:16:48 PM PST 24
Peak memory 190932 kb
Host smart-bb28ae07-4284-44b9-8429-990cc2721d8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799912301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.2799912301
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.1055974556
Short name T291
Test name
Test status
Simulation time 682812639982 ps
CPU time 534.56 seconds
Started Feb 29 01:01:45 PM PST 24
Finished Feb 29 01:10:40 PM PST 24
Peak memory 190856 kb
Host smart-5b013731-851f-4c49-bb2e-9b8915c8b9f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055974556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1055974556
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.4007501679
Short name T312
Test name
Test status
Simulation time 97690737275 ps
CPU time 30.94 seconds
Started Feb 29 01:01:44 PM PST 24
Finished Feb 29 01:02:15 PM PST 24
Peak memory 182548 kb
Host smart-1662a4f2-572f-4cfa-aa9c-eb500a151291
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007501679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.4007501679
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1246474714
Short name T4
Test name
Test status
Simulation time 35755297840 ps
CPU time 35.28 seconds
Started Feb 29 01:01:51 PM PST 24
Finished Feb 29 01:02:26 PM PST 24
Peak memory 182736 kb
Host smart-6298a243-7b88-4e02-a066-933df9b184a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246474714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1246474714
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.791153073
Short name T240
Test name
Test status
Simulation time 87104842058 ps
CPU time 237.49 seconds
Started Feb 29 01:01:45 PM PST 24
Finished Feb 29 01:05:42 PM PST 24
Peak memory 193380 kb
Host smart-f4a9ba25-0930-46f2-917f-5d453b26169f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791153073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.791153073
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2667754103
Short name T128
Test name
Test status
Simulation time 61569269431 ps
CPU time 107.85 seconds
Started Feb 29 01:00:49 PM PST 24
Finished Feb 29 01:02:38 PM PST 24
Peak memory 182744 kb
Host smart-fa2fc186-7bdc-457b-a391-d8fe6b00d6ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667754103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2667754103
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.3507620444
Short name T429
Test name
Test status
Simulation time 143830012062 ps
CPU time 233.14 seconds
Started Feb 29 01:00:49 PM PST 24
Finished Feb 29 01:04:42 PM PST 24
Peak memory 182656 kb
Host smart-581921ff-827b-458e-976b-512f1559086a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507620444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3507620444
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.3704417369
Short name T45
Test name
Test status
Simulation time 296033923183 ps
CPU time 348.95 seconds
Started Feb 29 01:00:48 PM PST 24
Finished Feb 29 01:06:37 PM PST 24
Peak memory 190912 kb
Host smart-b4943b58-3ced-4ee3-8026-cef20d2c42c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704417369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3704417369
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.3365032373
Short name T44
Test name
Test status
Simulation time 28990836870 ps
CPU time 1085.73 seconds
Started Feb 29 01:00:49 PM PST 24
Finished Feb 29 01:18:55 PM PST 24
Peak memory 182700 kb
Host smart-a5da34d7-1417-472f-bf88-42665dc182db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365032373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.3365032373
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1216394367
Short name T430
Test name
Test status
Simulation time 255461919999 ps
CPU time 534.67 seconds
Started Feb 29 01:00:49 PM PST 24
Finished Feb 29 01:09:43 PM PST 24
Peak memory 190936 kb
Host smart-871b55af-77f7-439a-bc57-8798ba558e1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216394367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1216394367
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.2887056693
Short name T407
Test name
Test status
Simulation time 51747577704 ps
CPU time 71.75 seconds
Started Feb 29 01:01:51 PM PST 24
Finished Feb 29 01:03:03 PM PST 24
Peak memory 182532 kb
Host smart-cf01b4fe-03cc-4719-95b8-12ceb72b98e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887056693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.2887056693
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.2321466102
Short name T281
Test name
Test status
Simulation time 120802891383 ps
CPU time 227.14 seconds
Started Feb 29 01:01:53 PM PST 24
Finished Feb 29 01:05:40 PM PST 24
Peak memory 190920 kb
Host smart-c67586f8-7418-4835-baee-66720541f682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321466102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2321466102
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2666005982
Short name T416
Test name
Test status
Simulation time 10967666356 ps
CPU time 5.88 seconds
Started Feb 29 01:01:44 PM PST 24
Finished Feb 29 01:01:50 PM PST 24
Peak memory 182748 kb
Host smart-b8c23e77-2b58-49fc-972e-6f3f932f878a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666005982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2666005982
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.1370126223
Short name T311
Test name
Test status
Simulation time 112505670967 ps
CPU time 319.09 seconds
Started Feb 29 01:01:44 PM PST 24
Finished Feb 29 01:07:03 PM PST 24
Peak memory 190928 kb
Host smart-05ee53bb-80d4-42a6-a251-c1277a8d73c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370126223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1370126223
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.1672379812
Short name T25
Test name
Test status
Simulation time 105732438715 ps
CPU time 356.38 seconds
Started Feb 29 01:01:47 PM PST 24
Finished Feb 29 01:07:43 PM PST 24
Peak memory 190992 kb
Host smart-fc4881b3-57c7-48c4-b2a9-f4841ddbf915
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672379812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1672379812
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.1344409555
Short name T70
Test name
Test status
Simulation time 446056156786 ps
CPU time 107.34 seconds
Started Feb 29 01:01:52 PM PST 24
Finished Feb 29 01:03:39 PM PST 24
Peak memory 190936 kb
Host smart-cfd9cf69-b2e1-4b9c-bdb4-f2bb9e3277f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344409555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1344409555
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.4158023677
Short name T260
Test name
Test status
Simulation time 173114779532 ps
CPU time 270.23 seconds
Started Feb 29 01:01:55 PM PST 24
Finished Feb 29 01:06:26 PM PST 24
Peak memory 190868 kb
Host smart-0818e36a-253e-4fd5-8d2e-4591105ade27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158023677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.4158023677
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.4143960083
Short name T388
Test name
Test status
Simulation time 105510930139 ps
CPU time 164.91 seconds
Started Feb 29 01:00:48 PM PST 24
Finished Feb 29 01:03:33 PM PST 24
Peak memory 182724 kb
Host smart-a2862727-1087-475d-bf95-62630ef797db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143960083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.4143960083
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.4208157109
Short name T277
Test name
Test status
Simulation time 51988367749 ps
CPU time 89.24 seconds
Started Feb 29 01:00:49 PM PST 24
Finished Feb 29 01:02:18 PM PST 24
Peak memory 193324 kb
Host smart-93fe9bd8-a4f1-4a86-a1c0-7f3ac324aa4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208157109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.4208157109
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.4241014400
Short name T387
Test name
Test status
Simulation time 164262564380 ps
CPU time 145.88 seconds
Started Feb 29 01:01:49 PM PST 24
Finished Feb 29 01:04:15 PM PST 24
Peak memory 182728 kb
Host smart-67b00f0b-a000-49b5-b2f7-306930336544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241014400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.4241014400
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.627791671
Short name T107
Test name
Test status
Simulation time 164233680164 ps
CPU time 438.55 seconds
Started Feb 29 01:01:47 PM PST 24
Finished Feb 29 01:09:06 PM PST 24
Peak memory 194376 kb
Host smart-18041e79-65f0-4352-bfa3-4c3db52e49c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627791671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.627791671
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.853837116
Short name T110
Test name
Test status
Simulation time 74657003011 ps
CPU time 560.04 seconds
Started Feb 29 01:01:49 PM PST 24
Finished Feb 29 01:11:09 PM PST 24
Peak memory 190916 kb
Host smart-56ab2815-3c45-4b49-9c04-cec5a0ed7c26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853837116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.853837116
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.64227100
Short name T252
Test name
Test status
Simulation time 148533708449 ps
CPU time 347.05 seconds
Started Feb 29 01:01:50 PM PST 24
Finished Feb 29 01:07:37 PM PST 24
Peak memory 190944 kb
Host smart-4bc66206-c197-4cec-9633-ad50e9c9bf85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64227100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.64227100
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.344259958
Short name T336
Test name
Test status
Simulation time 175031753972 ps
CPU time 50.47 seconds
Started Feb 29 01:01:48 PM PST 24
Finished Feb 29 01:02:38 PM PST 24
Peak memory 182712 kb
Host smart-af707022-f780-405c-ba7b-aa2f8d0bd5e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344259958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.344259958
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3639667714
Short name T279
Test name
Test status
Simulation time 584157840395 ps
CPU time 180.76 seconds
Started Feb 29 01:01:47 PM PST 24
Finished Feb 29 01:04:48 PM PST 24
Peak memory 190948 kb
Host smart-82c2280e-fe85-4694-89a4-461474db40fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639667714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3639667714
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.4212535857
Short name T307
Test name
Test status
Simulation time 2333364230 ps
CPU time 1.51 seconds
Started Feb 29 01:01:47 PM PST 24
Finished Feb 29 01:01:49 PM PST 24
Peak memory 182588 kb
Host smart-6f6c891b-ae43-48f5-a1f5-316695e4ed18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212535857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.4212535857
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3892772858
Short name T265
Test name
Test status
Simulation time 901916968716 ps
CPU time 797.48 seconds
Started Feb 29 01:00:50 PM PST 24
Finished Feb 29 01:14:08 PM PST 24
Peak memory 182708 kb
Host smart-9ab6820f-0483-4de8-8725-06a8b1a9aeba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892772858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3892772858
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1644415817
Short name T361
Test name
Test status
Simulation time 329557826707 ps
CPU time 127.59 seconds
Started Feb 29 01:00:50 PM PST 24
Finished Feb 29 01:02:58 PM PST 24
Peak memory 182728 kb
Host smart-31bef1b1-5f9b-4554-8eea-c2ccd47e18c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644415817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1644415817
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.3384444438
Short name T161
Test name
Test status
Simulation time 142956628059 ps
CPU time 69.98 seconds
Started Feb 29 01:00:50 PM PST 24
Finished Feb 29 01:02:00 PM PST 24
Peak memory 190928 kb
Host smart-2fd04f4f-8ce4-4bb2-bae6-cbae5e675741
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384444438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3384444438
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.4029817734
Short name T125
Test name
Test status
Simulation time 142320531730 ps
CPU time 109.81 seconds
Started Feb 29 01:00:56 PM PST 24
Finished Feb 29 01:02:46 PM PST 24
Peak memory 190828 kb
Host smart-c0f08374-81d7-4182-b07b-dd239f6b7fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029817734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.4029817734
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.206738825
Short name T40
Test name
Test status
Simulation time 174144716194 ps
CPU time 702.95 seconds
Started Feb 29 01:00:58 PM PST 24
Finished Feb 29 01:12:42 PM PST 24
Peak memory 205668 kb
Host smart-c49b56ed-6b58-4a8a-8989-5b9a788c253e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206738825 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.206738825
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.rv_timer_random.2265410889
Short name T196
Test name
Test status
Simulation time 128004843613 ps
CPU time 119.46 seconds
Started Feb 29 01:02:00 PM PST 24
Finished Feb 29 01:04:00 PM PST 24
Peak memory 190928 kb
Host smart-f3dac539-33bc-479a-b126-9564b87e6fb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265410889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2265410889
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.17092507
Short name T181
Test name
Test status
Simulation time 76969534870 ps
CPU time 161.15 seconds
Started Feb 29 01:02:08 PM PST 24
Finished Feb 29 01:04:50 PM PST 24
Peak memory 190924 kb
Host smart-96a60a3d-8890-4719-833f-8fca4d37251e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17092507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.17092507
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.3711907098
Short name T214
Test name
Test status
Simulation time 45367628990 ps
CPU time 37.29 seconds
Started Feb 29 01:02:01 PM PST 24
Finished Feb 29 01:02:38 PM PST 24
Peak memory 193380 kb
Host smart-2986fdbe-6531-40f5-9647-0db43a3d6e1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711907098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3711907098
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.233497961
Short name T298
Test name
Test status
Simulation time 54537162867 ps
CPU time 99.35 seconds
Started Feb 29 01:02:00 PM PST 24
Finished Feb 29 01:03:39 PM PST 24
Peak memory 190924 kb
Host smart-2daf818c-00db-463c-bf9a-498a9a22963c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233497961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.233497961
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.2298275217
Short name T137
Test name
Test status
Simulation time 101925835409 ps
CPU time 174.57 seconds
Started Feb 29 01:02:00 PM PST 24
Finished Feb 29 01:04:54 PM PST 24
Peak memory 193428 kb
Host smart-bf325cd8-81db-4eef-8644-508a91b960e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298275217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2298275217
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.4262571688
Short name T198
Test name
Test status
Simulation time 4874257186 ps
CPU time 8.43 seconds
Started Feb 29 01:01:00 PM PST 24
Finished Feb 29 01:01:09 PM PST 24
Peak memory 182756 kb
Host smart-59872652-2cbc-4245-acc4-a385dd121d32
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262571688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.4262571688
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.2606780050
Short name T357
Test name
Test status
Simulation time 453996561050 ps
CPU time 188.64 seconds
Started Feb 29 01:00:57 PM PST 24
Finished Feb 29 01:04:06 PM PST 24
Peak memory 182692 kb
Host smart-6b5da025-4140-41db-977a-7fc5afeec5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606780050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2606780050
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.1012348740
Short name T215
Test name
Test status
Simulation time 110136174276 ps
CPU time 193.48 seconds
Started Feb 29 01:01:02 PM PST 24
Finished Feb 29 01:04:15 PM PST 24
Peak memory 190912 kb
Host smart-8d787cb8-edf9-49e1-afda-ccc3d10c4f70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012348740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1012348740
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.138696576
Short name T359
Test name
Test status
Simulation time 725517619 ps
CPU time 0.78 seconds
Started Feb 29 01:01:01 PM PST 24
Finished Feb 29 01:01:03 PM PST 24
Peak memory 182496 kb
Host smart-d6deabbe-e868-48ed-a553-4e0bb5cbdb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138696576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.138696576
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.97442920
Short name T355
Test name
Test status
Simulation time 174167522920 ps
CPU time 246.57 seconds
Started Feb 29 01:00:58 PM PST 24
Finished Feb 29 01:05:05 PM PST 24
Peak memory 190948 kb
Host smart-d69e2201-fc13-4f83-8c07-87d54429b6b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97442920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.97442920
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.892704599
Short name T15
Test name
Test status
Simulation time 44198559525 ps
CPU time 334.4 seconds
Started Feb 29 01:01:00 PM PST 24
Finished Feb 29 01:06:35 PM PST 24
Peak memory 205728 kb
Host smart-8c3cddcc-28b4-4c1a-865a-c6f3c16c85af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892704599 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.892704599
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.2571039379
Short name T324
Test name
Test status
Simulation time 47216418798 ps
CPU time 72.08 seconds
Started Feb 29 01:01:59 PM PST 24
Finished Feb 29 01:03:11 PM PST 24
Peak memory 182396 kb
Host smart-b670da61-98b3-449c-8419-644272772d4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571039379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2571039379
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.543652829
Short name T132
Test name
Test status
Simulation time 416236933932 ps
CPU time 235.64 seconds
Started Feb 29 01:02:00 PM PST 24
Finished Feb 29 01:05:56 PM PST 24
Peak memory 190912 kb
Host smart-8a5ee499-7078-48d2-85b3-f6d186890034
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543652829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.543652829
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.556603748
Short name T327
Test name
Test status
Simulation time 6878367320 ps
CPU time 12.74 seconds
Started Feb 29 01:01:59 PM PST 24
Finished Feb 29 01:02:12 PM PST 24
Peak memory 190956 kb
Host smart-9e49071b-b44c-4764-8761-9028b24cf49b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556603748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.556603748
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.2172226215
Short name T256
Test name
Test status
Simulation time 190846130091 ps
CPU time 1016.22 seconds
Started Feb 29 01:01:58 PM PST 24
Finished Feb 29 01:18:54 PM PST 24
Peak memory 190928 kb
Host smart-9d491fe4-c9d4-4c1d-a2e5-42088e613109
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172226215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2172226215
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.1083913286
Short name T189
Test name
Test status
Simulation time 737088315680 ps
CPU time 1335.59 seconds
Started Feb 29 01:02:00 PM PST 24
Finished Feb 29 01:24:15 PM PST 24
Peak memory 194144 kb
Host smart-ac23210f-3bf4-4ab8-81a3-6743ca01602a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083913286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1083913286
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.710243396
Short name T373
Test name
Test status
Simulation time 105979620508 ps
CPU time 85.51 seconds
Started Feb 29 01:02:00 PM PST 24
Finished Feb 29 01:03:26 PM PST 24
Peak memory 190936 kb
Host smart-adc0e698-3a49-4ea1-83d2-6bccd8ff002c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710243396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.710243396
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1779229543
Short name T3
Test name
Test status
Simulation time 434672788092 ps
CPU time 789.69 seconds
Started Feb 29 01:00:49 PM PST 24
Finished Feb 29 01:14:00 PM PST 24
Peak memory 182764 kb
Host smart-dab0c327-5f24-4614-874b-9b3c4c231cb5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779229543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1779229543
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1002146486
Short name T413
Test name
Test status
Simulation time 87482915065 ps
CPU time 122.75 seconds
Started Feb 29 01:00:42 PM PST 24
Finished Feb 29 01:02:44 PM PST 24
Peak memory 182716 kb
Host smart-ee28f939-9daf-4be1-a466-21a0bb3df55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002146486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1002146486
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.810891002
Short name T47
Test name
Test status
Simulation time 342471933596 ps
CPU time 187.53 seconds
Started Feb 29 01:00:45 PM PST 24
Finished Feb 29 01:03:52 PM PST 24
Peak memory 190928 kb
Host smart-96bad707-aaca-4c90-b39c-9f8f9cb1d0b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810891002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.810891002
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1848268296
Short name T442
Test name
Test status
Simulation time 27937117149 ps
CPU time 19.19 seconds
Started Feb 29 01:00:47 PM PST 24
Finished Feb 29 01:01:06 PM PST 24
Peak memory 182596 kb
Host smart-c23bf2a1-4cd8-4255-bb6b-d00b402aca26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848268296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1848268296
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.1598670651
Short name T16
Test name
Test status
Simulation time 113148596 ps
CPU time 0.8 seconds
Started Feb 29 01:00:46 PM PST 24
Finished Feb 29 01:00:48 PM PST 24
Peak memory 212924 kb
Host smart-178a800d-de04-4fdc-9d13-080bee04e96c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598670651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1598670651
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2460701578
Short name T149
Test name
Test status
Simulation time 795294770137 ps
CPU time 780.91 seconds
Started Feb 29 01:00:59 PM PST 24
Finished Feb 29 01:14:01 PM PST 24
Peak memory 182952 kb
Host smart-e5ff4d2f-671b-4eeb-99f7-e1e72e4e27c7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460701578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2460701578
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.2820124179
Short name T354
Test name
Test status
Simulation time 82528502100 ps
CPU time 111.08 seconds
Started Feb 29 01:00:57 PM PST 24
Finished Feb 29 01:02:48 PM PST 24
Peak memory 182724 kb
Host smart-9c014621-04c7-4659-b279-3fb8650a3207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820124179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.2820124179
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.1602901977
Short name T347
Test name
Test status
Simulation time 100072202239 ps
CPU time 120.72 seconds
Started Feb 29 01:00:56 PM PST 24
Finished Feb 29 01:02:58 PM PST 24
Peak memory 182784 kb
Host smart-6c6534b0-34f8-400d-ad18-eb2f312d0a22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602901977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1602901977
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.1601075668
Short name T201
Test name
Test status
Simulation time 136897240778 ps
CPU time 126.66 seconds
Started Feb 29 01:00:59 PM PST 24
Finished Feb 29 01:03:06 PM PST 24
Peak memory 194100 kb
Host smart-d77e4238-235b-4393-b477-0ed62eb3f8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601075668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.1601075668
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.4237742137
Short name T105
Test name
Test status
Simulation time 326510401456 ps
CPU time 550.31 seconds
Started Feb 29 01:00:59 PM PST 24
Finished Feb 29 01:10:10 PM PST 24
Peak memory 182760 kb
Host smart-34e9ad0d-bfb1-4501-9aca-6e202d800a9e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237742137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.4237742137
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.2992659662
Short name T379
Test name
Test status
Simulation time 152364799096 ps
CPU time 64.5 seconds
Started Feb 29 01:01:03 PM PST 24
Finished Feb 29 01:02:08 PM PST 24
Peak memory 182780 kb
Host smart-ec043d23-565e-4db7-a855-63117bfe4f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992659662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2992659662
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.4224401480
Short name T164
Test name
Test status
Simulation time 121287920166 ps
CPU time 123.98 seconds
Started Feb 29 01:01:02 PM PST 24
Finished Feb 29 01:03:06 PM PST 24
Peak memory 190928 kb
Host smart-2a25fe03-d343-4451-a3ed-f7175758c3d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224401480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.4224401480
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.844041838
Short name T330
Test name
Test status
Simulation time 45881525278 ps
CPU time 85.17 seconds
Started Feb 29 01:01:01 PM PST 24
Finished Feb 29 01:02:26 PM PST 24
Peak memory 182644 kb
Host smart-23d097a1-b31a-4f1a-b5a9-65bce4279cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844041838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.844041838
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.3664509893
Short name T103
Test name
Test status
Simulation time 2246255445458 ps
CPU time 527.05 seconds
Started Feb 29 01:00:58 PM PST 24
Finished Feb 29 01:09:46 PM PST 24
Peak memory 190980 kb
Host smart-ebf15307-385b-494b-bbd3-2fba2c1adf7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664509893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.3664509893
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1342869930
Short name T212
Test name
Test status
Simulation time 27025902776 ps
CPU time 47.94 seconds
Started Feb 29 01:01:01 PM PST 24
Finished Feb 29 01:01:49 PM PST 24
Peak memory 182756 kb
Host smart-11935451-6134-4e23-bd7f-a422a00c4da5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342869930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1342869930
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.2907577590
Short name T367
Test name
Test status
Simulation time 39286020236 ps
CPU time 66.82 seconds
Started Feb 29 01:00:58 PM PST 24
Finished Feb 29 01:02:05 PM PST 24
Peak memory 182740 kb
Host smart-8a817fc9-a5e5-4059-85ac-ef802e5ea525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907577590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.2907577590
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.2846937933
Short name T75
Test name
Test status
Simulation time 332543000291 ps
CPU time 181.09 seconds
Started Feb 29 01:01:04 PM PST 24
Finished Feb 29 01:04:05 PM PST 24
Peak memory 193644 kb
Host smart-e6c40df4-a227-4aa2-aa6b-f1267951cb8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846937933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2846937933
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.770970268
Short name T118
Test name
Test status
Simulation time 1977319775277 ps
CPU time 3025.87 seconds
Started Feb 29 01:00:59 PM PST 24
Finished Feb 29 01:51:25 PM PST 24
Peak memory 190948 kb
Host smart-b6d99c51-1e5f-41fe-8c94-33df1dfa99d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770970268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.
770970268
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.4188469595
Short name T397
Test name
Test status
Simulation time 101338732952 ps
CPU time 172.9 seconds
Started Feb 29 01:01:03 PM PST 24
Finished Feb 29 01:03:57 PM PST 24
Peak memory 182780 kb
Host smart-3b0f47bf-de92-4dd0-9dc7-228f9944a83e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188469595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.4188469595
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1366476066
Short name T76
Test name
Test status
Simulation time 35762013010 ps
CPU time 42.21 seconds
Started Feb 29 01:01:04 PM PST 24
Finished Feb 29 01:01:47 PM PST 24
Peak memory 182712 kb
Host smart-2bc07daf-9a14-4e06-8bd2-7c4bd5a5b53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366476066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1366476066
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.2154448824
Short name T309
Test name
Test status
Simulation time 34272904910 ps
CPU time 24.78 seconds
Started Feb 29 01:01:00 PM PST 24
Finished Feb 29 01:01:25 PM PST 24
Peak memory 182704 kb
Host smart-018c0a8e-828e-4665-b569-1da5abd57c39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154448824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2154448824
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.673525283
Short name T186
Test name
Test status
Simulation time 9000954052 ps
CPU time 13.75 seconds
Started Feb 29 01:01:00 PM PST 24
Finished Feb 29 01:01:14 PM PST 24
Peak memory 192024 kb
Host smart-d23d20d3-a8e2-4679-ae50-cbb3e0aa6d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673525283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.673525283
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.869352955
Short name T346
Test name
Test status
Simulation time 10592690549 ps
CPU time 17.7 seconds
Started Feb 29 01:00:57 PM PST 24
Finished Feb 29 01:01:16 PM PST 24
Peak memory 182720 kb
Host smart-3c0554a2-dd84-4b58-9eeb-91271606102b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869352955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.rv_timer_cfg_update_on_fly.869352955
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_random.3790682452
Short name T381
Test name
Test status
Simulation time 45501978766 ps
CPU time 122.49 seconds
Started Feb 29 01:00:56 PM PST 24
Finished Feb 29 01:02:59 PM PST 24
Peak memory 182728 kb
Host smart-2f158be3-47fd-4573-9cd3-85f3b010c984
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790682452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3790682452
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.958129884
Short name T375
Test name
Test status
Simulation time 110827170 ps
CPU time 0.68 seconds
Started Feb 29 01:00:56 PM PST 24
Finished Feb 29 01:00:57 PM PST 24
Peak memory 182456 kb
Host smart-805da0d4-0c83-4b08-a3a2-77132c0fce09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958129884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.958129884
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.3975319190
Short name T426
Test name
Test status
Simulation time 134960435664 ps
CPU time 197.14 seconds
Started Feb 29 01:00:58 PM PST 24
Finished Feb 29 01:04:15 PM PST 24
Peak memory 182820 kb
Host smart-a7d65bd2-2046-47cb-a667-a0e52d6a2f00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975319190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.3975319190
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.1405109920
Short name T14
Test name
Test status
Simulation time 30143925301 ps
CPU time 244.51 seconds
Started Feb 29 01:01:00 PM PST 24
Finished Feb 29 01:05:05 PM PST 24
Peak memory 197492 kb
Host smart-4b5c4ea0-f582-490b-acdb-571e846c4851
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405109920 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.1405109920
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.825290765
Short name T247
Test name
Test status
Simulation time 94835348464 ps
CPU time 142.81 seconds
Started Feb 29 01:00:58 PM PST 24
Finished Feb 29 01:03:21 PM PST 24
Peak memory 182776 kb
Host smart-c658da3a-42be-456e-8e81-58dd7c033413
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825290765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.825290765
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.553168394
Short name T431
Test name
Test status
Simulation time 11658561954 ps
CPU time 17.58 seconds
Started Feb 29 01:00:57 PM PST 24
Finished Feb 29 01:01:16 PM PST 24
Peak memory 182652 kb
Host smart-3ae803e2-454a-4195-b614-0d7459a51511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553168394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.553168394
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.921255109
Short name T349
Test name
Test status
Simulation time 79883495457 ps
CPU time 336.49 seconds
Started Feb 29 01:00:55 PM PST 24
Finished Feb 29 01:06:32 PM PST 24
Peak memory 192968 kb
Host smart-96da0272-d44a-446e-a68f-c926af6f14b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921255109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.921255109
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3602313895
Short name T372
Test name
Test status
Simulation time 317492444825 ps
CPU time 291.1 seconds
Started Feb 29 01:00:57 PM PST 24
Finished Feb 29 01:05:49 PM PST 24
Peak memory 182804 kb
Host smart-a1d92416-aab5-44ea-9b74-79ca228a50cd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602313895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3602313895
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.152714045
Short name T389
Test name
Test status
Simulation time 194723431795 ps
CPU time 319.59 seconds
Started Feb 29 01:01:01 PM PST 24
Finished Feb 29 01:06:21 PM PST 24
Peak memory 182732 kb
Host smart-6b3a462d-58b2-4033-b2d5-2bbdd6db9099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152714045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.152714045
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2898213970
Short name T268
Test name
Test status
Simulation time 151290309006 ps
CPU time 649.06 seconds
Started Feb 29 01:01:13 PM PST 24
Finished Feb 29 01:12:03 PM PST 24
Peak memory 190928 kb
Host smart-4d0002b7-9f64-4bad-9ed7-7e4f2fae5f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898213970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2898213970
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.2285376255
Short name T270
Test name
Test status
Simulation time 181081437660 ps
CPU time 651.18 seconds
Started Feb 29 01:01:14 PM PST 24
Finished Feb 29 01:12:06 PM PST 24
Peak memory 190968 kb
Host smart-9e312d87-75b1-47ed-a433-d255118bd888
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285376255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.2285376255
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1990917012
Short name T358
Test name
Test status
Simulation time 65472799088 ps
CPU time 50.8 seconds
Started Feb 29 01:01:15 PM PST 24
Finished Feb 29 01:02:07 PM PST 24
Peak memory 182612 kb
Host smart-e97a0210-503d-4d45-ad06-a3e0d43e8dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990917012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1990917012
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.1193514193
Short name T310
Test name
Test status
Simulation time 35680633415 ps
CPU time 50.78 seconds
Started Feb 29 01:01:18 PM PST 24
Finished Feb 29 01:02:09 PM PST 24
Peak memory 190852 kb
Host smart-d31f6713-5bb6-4439-b652-c7e5db1fef9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193514193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1193514193
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2163381224
Short name T170
Test name
Test status
Simulation time 236249705748 ps
CPU time 388.59 seconds
Started Feb 29 01:01:12 PM PST 24
Finished Feb 29 01:07:42 PM PST 24
Peak memory 182764 kb
Host smart-ed178f26-781d-4cfc-b9e9-9b76e6f704bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163381224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2163381224
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3290699799
Short name T275
Test name
Test status
Simulation time 527545891912 ps
CPU time 324.23 seconds
Started Feb 29 01:01:15 PM PST 24
Finished Feb 29 01:06:41 PM PST 24
Peak memory 182796 kb
Host smart-63a6d253-485e-4196-90f3-1bc2d547fb75
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290699799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.3290699799
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.3180559813
Short name T29
Test name
Test status
Simulation time 37728984891 ps
CPU time 24.15 seconds
Started Feb 29 01:01:16 PM PST 24
Finished Feb 29 01:01:41 PM PST 24
Peak memory 182724 kb
Host smart-2916a8af-4c89-4a0f-b57d-65d74493ce98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180559813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3180559813
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.1434220105
Short name T406
Test name
Test status
Simulation time 71028250283 ps
CPU time 56.78 seconds
Started Feb 29 01:01:21 PM PST 24
Finished Feb 29 01:02:18 PM PST 24
Peak memory 193136 kb
Host smart-c43366f6-4dd4-46f3-a510-b23f9a8c22d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434220105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1434220105
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2377339890
Short name T49
Test name
Test status
Simulation time 475337217 ps
CPU time 0.92 seconds
Started Feb 29 01:01:14 PM PST 24
Finished Feb 29 01:01:15 PM PST 24
Peak memory 190912 kb
Host smart-71726498-6dcb-4748-a6c7-afde83b8cd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377339890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2377339890
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.3568222521
Short name T122
Test name
Test status
Simulation time 178098070315 ps
CPU time 327.02 seconds
Started Feb 29 01:01:13 PM PST 24
Finished Feb 29 01:06:41 PM PST 24
Peak memory 194716 kb
Host smart-3954e219-5026-4eeb-ab94-110a31b56376
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568222521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.3568222521
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2726746857
Short name T213
Test name
Test status
Simulation time 82592758510 ps
CPU time 141.45 seconds
Started Feb 29 01:01:18 PM PST 24
Finished Feb 29 01:03:40 PM PST 24
Peak memory 182784 kb
Host smart-e69fa720-a58c-4455-aa26-1b3f1cb3ac74
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726746857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.2726746857
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.1033643849
Short name T65
Test name
Test status
Simulation time 27702058037 ps
CPU time 10.74 seconds
Started Feb 29 01:01:19 PM PST 24
Finished Feb 29 01:01:30 PM PST 24
Peak memory 182948 kb
Host smart-d785aa44-c1e2-4d4c-abab-2aad02100b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033643849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1033643849
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.3292015316
Short name T282
Test name
Test status
Simulation time 691012992933 ps
CPU time 192 seconds
Started Feb 29 01:01:14 PM PST 24
Finished Feb 29 01:04:27 PM PST 24
Peak memory 190976 kb
Host smart-6031d5b9-782b-451c-9dbe-894d89db0fae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292015316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3292015316
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.361214660
Short name T414
Test name
Test status
Simulation time 950630410 ps
CPU time 1.12 seconds
Started Feb 29 01:01:23 PM PST 24
Finished Feb 29 01:01:25 PM PST 24
Peak memory 191308 kb
Host smart-91899aad-ab6d-4296-9774-8aadf48e0b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361214660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.361214660
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1714196314
Short name T11
Test name
Test status
Simulation time 400961793494 ps
CPU time 2199.87 seconds
Started Feb 29 01:01:21 PM PST 24
Finished Feb 29 01:38:01 PM PST 24
Peak memory 190936 kb
Host smart-8fcc5403-a029-4ab9-a953-1216e95fd008
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714196314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1714196314
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.1080015063
Short name T420
Test name
Test status
Simulation time 3536735664 ps
CPU time 7.01 seconds
Started Feb 29 01:00:40 PM PST 24
Finished Feb 29 01:00:47 PM PST 24
Peak memory 182740 kb
Host smart-21cb48eb-9675-4474-b987-2edbaae67e0e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080015063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.1080015063
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.886022098
Short name T393
Test name
Test status
Simulation time 441107423812 ps
CPU time 169.01 seconds
Started Feb 29 01:00:43 PM PST 24
Finished Feb 29 01:03:32 PM PST 24
Peak memory 182740 kb
Host smart-d5013ce5-15bf-4d23-9200-1b6f2c0fa243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886022098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.886022098
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.1865025764
Short name T267
Test name
Test status
Simulation time 194189206225 ps
CPU time 173.33 seconds
Started Feb 29 01:00:45 PM PST 24
Finished Feb 29 01:03:38 PM PST 24
Peak memory 193376 kb
Host smart-96c6d696-5a64-4b74-9202-2f92ad1f0175
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865025764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1865025764
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2320063866
Short name T221
Test name
Test status
Simulation time 104805197220 ps
CPU time 527.86 seconds
Started Feb 29 01:00:46 PM PST 24
Finished Feb 29 01:09:34 PM PST 24
Peak memory 182648 kb
Host smart-53f1d63b-1b99-4568-8f09-e0160837ef87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320063866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2320063866
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2092021305
Short name T17
Test name
Test status
Simulation time 952109760 ps
CPU time 0.92 seconds
Started Feb 29 01:00:48 PM PST 24
Finished Feb 29 01:00:49 PM PST 24
Peak memory 213952 kb
Host smart-fecca5dc-9bcd-46dc-b947-6331d90fc9d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092021305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2092021305
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.621740615
Short name T440
Test name
Test status
Simulation time 35032136 ps
CPU time 0.64 seconds
Started Feb 29 01:00:42 PM PST 24
Finished Feb 29 01:00:43 PM PST 24
Peak memory 182496 kb
Host smart-4ab489c0-1559-4e9e-b2d8-1edc67ba5fc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621740615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.621740615
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3160157981
Short name T77
Test name
Test status
Simulation time 186825798856 ps
CPU time 71.33 seconds
Started Feb 29 01:01:14 PM PST 24
Finished Feb 29 01:02:27 PM PST 24
Peak memory 182612 kb
Host smart-8d67fdfb-68f1-4a0f-82bb-9cf728c8f9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160157981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3160157981
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.3611329638
Short name T251
Test name
Test status
Simulation time 26825069854 ps
CPU time 55.76 seconds
Started Feb 29 01:01:16 PM PST 24
Finished Feb 29 01:02:13 PM PST 24
Peak memory 182728 kb
Host smart-c2c4a255-f6f3-4c71-bafa-bf4378475f80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611329638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3611329638
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3933827748
Short name T432
Test name
Test status
Simulation time 24071468847 ps
CPU time 37.72 seconds
Started Feb 29 01:01:16 PM PST 24
Finished Feb 29 01:01:55 PM PST 24
Peak memory 182748 kb
Host smart-416d2718-7d5a-4e0e-93be-31f2e5bee379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933827748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3933827748
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1512021500
Short name T391
Test name
Test status
Simulation time 69635926443 ps
CPU time 110.36 seconds
Started Feb 29 01:01:17 PM PST 24
Finished Feb 29 01:03:08 PM PST 24
Peak memory 182692 kb
Host smart-9e5d5fa2-7fe6-49c8-8a12-e8e950c36c8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512021500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1512021500
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3412685580
Short name T228
Test name
Test status
Simulation time 233003342080 ps
CPU time 238.6 seconds
Started Feb 29 01:01:21 PM PST 24
Finished Feb 29 01:05:20 PM PST 24
Peak memory 182792 kb
Host smart-9ec063f0-4186-44be-b3ec-ebaa4dd9bf11
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412685580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3412685580
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1704100245
Short name T363
Test name
Test status
Simulation time 84282750994 ps
CPU time 74.92 seconds
Started Feb 29 01:01:18 PM PST 24
Finished Feb 29 01:02:33 PM PST 24
Peak memory 182728 kb
Host smart-2737939a-838d-465e-8cfe-e1bb6233e940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704100245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1704100245
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.4144417221
Short name T313
Test name
Test status
Simulation time 87821694585 ps
CPU time 144.84 seconds
Started Feb 29 01:01:14 PM PST 24
Finished Feb 29 01:03:41 PM PST 24
Peak memory 192904 kb
Host smart-031def57-b162-430a-a9fc-69cabdb7340b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144417221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.4144417221
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2528487005
Short name T383
Test name
Test status
Simulation time 215212181 ps
CPU time 0.7 seconds
Started Feb 29 01:01:18 PM PST 24
Finished Feb 29 01:01:19 PM PST 24
Peak memory 182492 kb
Host smart-fbb011bd-3822-4d4e-8402-f7664742f959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528487005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2528487005
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2674138252
Short name T434
Test name
Test status
Simulation time 1888846155797 ps
CPU time 418.84 seconds
Started Feb 29 01:01:17 PM PST 24
Finished Feb 29 01:08:17 PM PST 24
Peak memory 182756 kb
Host smart-2fd34711-3c71-4045-b0a8-1f3f1d2a7c67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674138252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2674138252
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2677268585
Short name T145
Test name
Test status
Simulation time 865961158270 ps
CPU time 523.16 seconds
Started Feb 29 01:01:15 PM PST 24
Finished Feb 29 01:10:00 PM PST 24
Peak memory 182668 kb
Host smart-08e318bc-0fc1-442d-9d60-35180a023ced
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677268585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2677268585
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.708568814
Short name T423
Test name
Test status
Simulation time 166488179832 ps
CPU time 267.98 seconds
Started Feb 29 01:01:17 PM PST 24
Finished Feb 29 01:05:46 PM PST 24
Peak memory 182708 kb
Host smart-2bafa9ba-4087-424b-9e29-6bf1b62022c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708568814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.708568814
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1558010119
Short name T425
Test name
Test status
Simulation time 1292248097 ps
CPU time 1.02 seconds
Started Feb 29 01:01:16 PM PST 24
Finished Feb 29 01:01:19 PM PST 24
Peak memory 190832 kb
Host smart-6ad9c3c7-09ab-443d-8b94-a6f485c833c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558010119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1558010119
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3033936875
Short name T66
Test name
Test status
Simulation time 473373378744 ps
CPU time 1537.22 seconds
Started Feb 29 01:01:24 PM PST 24
Finished Feb 29 01:27:01 PM PST 24
Peak memory 195296 kb
Host smart-303f9748-2b91-471c-b63e-37f03b90875d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033936875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3033936875
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1963307432
Short name T263
Test name
Test status
Simulation time 16150298405 ps
CPU time 26.5 seconds
Started Feb 29 01:01:17 PM PST 24
Finished Feb 29 01:01:45 PM PST 24
Peak memory 182952 kb
Host smart-4fbafab9-01bf-4f7e-9db3-9e89c0189682
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963307432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.1963307432
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.4068002712
Short name T395
Test name
Test status
Simulation time 77585352035 ps
CPU time 34.43 seconds
Started Feb 29 01:01:14 PM PST 24
Finished Feb 29 01:01:49 PM PST 24
Peak memory 182740 kb
Host smart-d16d05ac-a956-48f0-bdf0-a37b7039c417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068002712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.4068002712
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.2421928029
Short name T182
Test name
Test status
Simulation time 81316949042 ps
CPU time 623.55 seconds
Started Feb 29 01:01:16 PM PST 24
Finished Feb 29 01:11:41 PM PST 24
Peak memory 190920 kb
Host smart-28f046e3-fdd4-4afa-bad2-357a0954f7b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421928029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2421928029
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2133887656
Short name T239
Test name
Test status
Simulation time 125401179329 ps
CPU time 208.22 seconds
Started Feb 29 01:01:17 PM PST 24
Finished Feb 29 01:04:46 PM PST 24
Peak memory 190924 kb
Host smart-9c070092-0d0f-4395-a753-ec4c3bad5d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133887656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2133887656
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.1670298814
Short name T341
Test name
Test status
Simulation time 502076914635 ps
CPU time 214.6 seconds
Started Feb 29 01:01:16 PM PST 24
Finished Feb 29 01:04:52 PM PST 24
Peak memory 194320 kb
Host smart-a5a822b5-613f-4b2f-b977-c1fb16321f25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670298814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.1670298814
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.141719736
Short name T384
Test name
Test status
Simulation time 37191153492 ps
CPU time 49.32 seconds
Started Feb 29 01:01:18 PM PST 24
Finished Feb 29 01:02:08 PM PST 24
Peak memory 182728 kb
Host smart-81a20472-8863-4cfc-9858-e359be21fc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141719736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.141719736
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2306646302
Short name T418
Test name
Test status
Simulation time 113183808699 ps
CPU time 203.14 seconds
Started Feb 29 01:01:17 PM PST 24
Finished Feb 29 01:04:41 PM PST 24
Peak memory 182744 kb
Host smart-220a875f-35c8-43b5-b6b5-26ee8b00bb3a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306646302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2306646302
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3487158906
Short name T366
Test name
Test status
Simulation time 164416948873 ps
CPU time 250.9 seconds
Started Feb 29 01:01:18 PM PST 24
Finished Feb 29 01:05:29 PM PST 24
Peak memory 182724 kb
Host smart-35c85caa-1493-4443-a32e-68d63de607ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487158906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3487158906
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.3327157254
Short name T184
Test name
Test status
Simulation time 276875605680 ps
CPU time 293.66 seconds
Started Feb 29 01:01:17 PM PST 24
Finished Feb 29 01:06:12 PM PST 24
Peak memory 190924 kb
Host smart-dc9b902d-0cbf-4ecb-8a77-dd22f435f654
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327157254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3327157254
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.3373658359
Short name T129
Test name
Test status
Simulation time 33147609808 ps
CPU time 228.31 seconds
Started Feb 29 01:01:19 PM PST 24
Finished Feb 29 01:05:07 PM PST 24
Peak memory 182712 kb
Host smart-1244d51f-1bae-4cc8-8d8c-78a4a7c7a093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373658359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3373658359
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1560391907
Short name T286
Test name
Test status
Simulation time 271525110388 ps
CPU time 488.9 seconds
Started Feb 29 01:01:19 PM PST 24
Finished Feb 29 01:09:29 PM PST 24
Peak memory 182808 kb
Host smart-f8c48435-717c-40e6-a6cc-dbd4edb2dce8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560391907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1560391907
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1191581063
Short name T140
Test name
Test status
Simulation time 166093240806 ps
CPU time 290.8 seconds
Started Feb 29 01:01:16 PM PST 24
Finished Feb 29 01:06:08 PM PST 24
Peak memory 182712 kb
Host smart-a7defe97-4550-42d0-8963-9324f74ee6d4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191581063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1191581063
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.4049159183
Short name T390
Test name
Test status
Simulation time 601305390428 ps
CPU time 318.17 seconds
Started Feb 29 01:01:15 PM PST 24
Finished Feb 29 01:06:35 PM PST 24
Peak memory 182744 kb
Host smart-0fae7145-81b4-43d2-b0c1-53ef1cf8fa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049159183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.4049159183
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.3612046154
Short name T305
Test name
Test status
Simulation time 250290366202 ps
CPU time 219.77 seconds
Started Feb 29 01:01:21 PM PST 24
Finished Feb 29 01:05:01 PM PST 24
Peak memory 190928 kb
Host smart-dc1ae490-58cd-4b3c-9e8e-fb004581fd19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612046154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3612046154
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3842494649
Short name T306
Test name
Test status
Simulation time 23955185987 ps
CPU time 44.53 seconds
Started Feb 29 01:01:20 PM PST 24
Finished Feb 29 01:02:04 PM PST 24
Peak memory 193904 kb
Host smart-c11f4029-713f-4c40-95fe-4209ee4d34b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842494649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3842494649
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.3822703441
Short name T39
Test name
Test status
Simulation time 18115036223 ps
CPU time 194.63 seconds
Started Feb 29 01:01:19 PM PST 24
Finished Feb 29 01:04:34 PM PST 24
Peak memory 197348 kb
Host smart-257eeac2-e6b0-423b-9508-e610db323546
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822703441 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.3822703441
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1812006846
Short name T121
Test name
Test status
Simulation time 174055206836 ps
CPU time 313.39 seconds
Started Feb 29 01:01:20 PM PST 24
Finished Feb 29 01:06:34 PM PST 24
Peak memory 182716 kb
Host smart-9eae483a-e1f1-474c-abed-a88feaf5f50c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812006846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1812006846
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2970123237
Short name T356
Test name
Test status
Simulation time 63938625203 ps
CPU time 98.5 seconds
Started Feb 29 01:01:18 PM PST 24
Finished Feb 29 01:02:57 PM PST 24
Peak memory 182632 kb
Host smart-f766a166-6673-4f72-8ffd-fec916601178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970123237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2970123237
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.2435180888
Short name T209
Test name
Test status
Simulation time 1489765308067 ps
CPU time 1484.95 seconds
Started Feb 29 01:01:21 PM PST 24
Finished Feb 29 01:26:06 PM PST 24
Peak memory 190920 kb
Host smart-5f656398-1881-46b1-a81f-9a2d110ac424
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435180888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2435180888
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.696724864
Short name T238
Test name
Test status
Simulation time 20466939587 ps
CPU time 43.86 seconds
Started Feb 29 01:01:21 PM PST 24
Finished Feb 29 01:02:05 PM PST 24
Peak memory 182712 kb
Host smart-c9dd43ad-2f87-4acd-9971-07f7a0c1d46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696724864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.696724864
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2501529714
Short name T1
Test name
Test status
Simulation time 31522295852 ps
CPU time 13.56 seconds
Started Feb 29 01:01:18 PM PST 24
Finished Feb 29 01:01:32 PM PST 24
Peak memory 182728 kb
Host smart-685ad45a-92a8-403a-bc93-478e617edc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501529714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2501529714
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.4280619558
Short name T218
Test name
Test status
Simulation time 816376634563 ps
CPU time 735.78 seconds
Started Feb 29 01:01:19 PM PST 24
Finished Feb 29 01:13:35 PM PST 24
Peak memory 190856 kb
Host smart-aa38ca06-b738-47f4-81d0-3da58a76561f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280619558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.4280619558
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2763883025
Short name T322
Test name
Test status
Simulation time 192776537312 ps
CPU time 102.39 seconds
Started Feb 29 01:01:24 PM PST 24
Finished Feb 29 01:03:07 PM PST 24
Peak memory 190924 kb
Host smart-b8c879fa-f14a-4cc1-aed5-e4ac7c5c294b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763883025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2763883025
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2054297320
Short name T188
Test name
Test status
Simulation time 179050564061 ps
CPU time 315.3 seconds
Started Feb 29 01:01:23 PM PST 24
Finished Feb 29 01:06:39 PM PST 24
Peak memory 182752 kb
Host smart-8c74eadc-5633-4cc1-88dd-9dc7eca38ff3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054297320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2054297320
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.210499918
Short name T365
Test name
Test status
Simulation time 148528809030 ps
CPU time 76.85 seconds
Started Feb 29 01:01:23 PM PST 24
Finished Feb 29 01:02:41 PM PST 24
Peak memory 182728 kb
Host smart-b4b53f29-0756-486d-85e8-1e9ef7c19219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210499918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.210499918
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.4096885790
Short name T67
Test name
Test status
Simulation time 79688574 ps
CPU time 0.57 seconds
Started Feb 29 01:01:24 PM PST 24
Finished Feb 29 01:01:25 PM PST 24
Peak memory 182356 kb
Host smart-939aadd3-e9a6-4076-9a8f-c15136438e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096885790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.4096885790
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.85743060
Short name T24
Test name
Test status
Simulation time 632059838511 ps
CPU time 307.61 seconds
Started Feb 29 01:00:48 PM PST 24
Finished Feb 29 01:05:56 PM PST 24
Peak memory 182768 kb
Host smart-210b73ce-21fc-4965-abd3-eb06a32442cf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85743060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
rv_timer_cfg_update_on_fly.85743060
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.569630904
Short name T401
Test name
Test status
Simulation time 194252062729 ps
CPU time 157.96 seconds
Started Feb 29 01:00:46 PM PST 24
Finished Feb 29 01:03:24 PM PST 24
Peak memory 182608 kb
Host smart-59602afa-c337-49f7-903c-f5d0534bd49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569630904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.569630904
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.132723545
Short name T386
Test name
Test status
Simulation time 134148015681 ps
CPU time 127.22 seconds
Started Feb 29 01:00:43 PM PST 24
Finished Feb 29 01:02:50 PM PST 24
Peak memory 190976 kb
Host smart-977a1d52-3850-40d8-8f75-3555042a30cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132723545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.132723545
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2724736011
Short name T50
Test name
Test status
Simulation time 915075574 ps
CPU time 1.79 seconds
Started Feb 29 01:00:43 PM PST 24
Finished Feb 29 01:00:45 PM PST 24
Peak memory 182400 kb
Host smart-4e96ff33-5c83-48fd-8c4c-76a18c17766b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724736011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2724736011
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.3310865421
Short name T18
Test name
Test status
Simulation time 64378515 ps
CPU time 0.88 seconds
Started Feb 29 01:00:46 PM PST 24
Finished Feb 29 01:00:48 PM PST 24
Peak memory 212896 kb
Host smart-48f8236f-f3e5-408d-85d2-9e674298a136
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310865421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3310865421
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.712813962
Short name T237
Test name
Test status
Simulation time 263051084 ps
CPU time 0.96 seconds
Started Feb 29 01:01:16 PM PST 24
Finished Feb 29 01:01:18 PM PST 24
Peak memory 182500 kb
Host smart-6f501c57-6662-4cce-a4b5-4707c33e1b0e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712813962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.rv_timer_cfg_update_on_fly.712813962
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.73016803
Short name T438
Test name
Test status
Simulation time 115721163088 ps
CPU time 201.88 seconds
Started Feb 29 01:01:17 PM PST 24
Finished Feb 29 01:04:40 PM PST 24
Peak memory 182728 kb
Host smart-62e16cc3-a2f3-477a-924d-256778c5e1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73016803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.73016803
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.1162142102
Short name T266
Test name
Test status
Simulation time 692350183937 ps
CPU time 342.05 seconds
Started Feb 29 01:01:18 PM PST 24
Finished Feb 29 01:07:01 PM PST 24
Peak memory 190848 kb
Host smart-f1d5a159-5cfc-493e-94f7-6685a71e717f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162142102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1162142102
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.3055232478
Short name T421
Test name
Test status
Simulation time 43610375632 ps
CPU time 72.27 seconds
Started Feb 29 01:01:16 PM PST 24
Finished Feb 29 01:02:30 PM PST 24
Peak memory 190936 kb
Host smart-cbd9fb14-1fcc-41c6-9ece-174bcfcbd218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055232478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3055232478
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.105169626
Short name T38
Test name
Test status
Simulation time 75278787742 ps
CPU time 447.71 seconds
Started Feb 29 01:01:16 PM PST 24
Finished Feb 29 01:08:45 PM PST 24
Peak memory 206484 kb
Host smart-1b3f384d-7f98-40dc-acb6-338ab78b3736
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105169626 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.105169626
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3081557429
Short name T179
Test name
Test status
Simulation time 282013866312 ps
CPU time 290.48 seconds
Started Feb 29 01:01:15 PM PST 24
Finished Feb 29 01:06:07 PM PST 24
Peak memory 182776 kb
Host smart-9fc55999-3c61-4400-8cf0-b65f34d7bbb7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081557429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3081557429
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.1456472070
Short name T396
Test name
Test status
Simulation time 107545858511 ps
CPU time 178.41 seconds
Started Feb 29 01:01:16 PM PST 24
Finished Feb 29 01:04:16 PM PST 24
Peak memory 182728 kb
Host smart-c5877f57-72fb-4f44-9e99-215f06aba53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456472070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1456472070
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1758367619
Short name T283
Test name
Test status
Simulation time 1140626255771 ps
CPU time 424.03 seconds
Started Feb 29 01:01:24 PM PST 24
Finished Feb 29 01:08:28 PM PST 24
Peak memory 190852 kb
Host smart-cf7e1ad1-156e-4371-8361-8076c354c0e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758367619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1758367619
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3364337186
Short name T304
Test name
Test status
Simulation time 34706835418 ps
CPU time 61.69 seconds
Started Feb 29 01:01:23 PM PST 24
Finished Feb 29 01:02:26 PM PST 24
Peak memory 190932 kb
Host smart-e60ee3ce-46b6-48e5-9ef6-c09c96b618bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364337186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3364337186
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2004365870
Short name T253
Test name
Test status
Simulation time 112812208084 ps
CPU time 142.42 seconds
Started Feb 29 01:01:24 PM PST 24
Finished Feb 29 01:03:46 PM PST 24
Peak memory 190992 kb
Host smart-af332e6c-c03c-4741-b2ce-2ed106c9b089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004365870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2004365870
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2459785572
Short name T443
Test name
Test status
Simulation time 106391668317 ps
CPU time 75.76 seconds
Started Feb 29 01:01:33 PM PST 24
Finished Feb 29 01:02:49 PM PST 24
Peak memory 182732 kb
Host smart-8c9a7e9f-3d15-4806-8c25-13d595a284f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459785572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2459785572
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2149399677
Short name T316
Test name
Test status
Simulation time 219513897755 ps
CPU time 1840.14 seconds
Started Feb 29 01:01:26 PM PST 24
Finished Feb 29 01:32:07 PM PST 24
Peak memory 182760 kb
Host smart-f0b85427-274d-4b97-9ac6-cada26deb5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149399677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2149399677
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1942973525
Short name T235
Test name
Test status
Simulation time 7445506915 ps
CPU time 12.06 seconds
Started Feb 29 01:01:28 PM PST 24
Finished Feb 29 01:01:40 PM PST 24
Peak memory 182748 kb
Host smart-ef75df4a-aaa9-4fd7-96e0-c59dd9d53007
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942973525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1942973525
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.2386610504
Short name T404
Test name
Test status
Simulation time 589112655465 ps
CPU time 218.01 seconds
Started Feb 29 01:01:29 PM PST 24
Finished Feb 29 01:05:08 PM PST 24
Peak memory 182720 kb
Host smart-13aed213-8119-4e04-995f-976c0695fa02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386610504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2386610504
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.2011518850
Short name T26
Test name
Test status
Simulation time 24670476763 ps
CPU time 40.74 seconds
Started Feb 29 01:01:32 PM PST 24
Finished Feb 29 01:02:13 PM PST 24
Peak memory 182712 kb
Host smart-1d28369a-cc76-4940-8177-85f62850f563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011518850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2011518850
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.121622340
Short name T419
Test name
Test status
Simulation time 12237017276 ps
CPU time 23.79 seconds
Started Feb 29 01:01:31 PM PST 24
Finished Feb 29 01:01:54 PM PST 24
Peak memory 182712 kb
Host smart-f0a3905b-a5ab-401c-95c1-c6e05e3e2375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121622340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.121622340
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2472658680
Short name T61
Test name
Test status
Simulation time 505432156054 ps
CPU time 225.04 seconds
Started Feb 29 01:01:35 PM PST 24
Finished Feb 29 01:05:21 PM PST 24
Peak memory 182700 kb
Host smart-8fd08195-237c-4689-93a1-f485058a53d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472658680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2472658680
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.775790217
Short name T334
Test name
Test status
Simulation time 182241720121 ps
CPU time 304.7 seconds
Started Feb 29 01:01:29 PM PST 24
Finished Feb 29 01:06:35 PM PST 24
Peak memory 182912 kb
Host smart-589aef30-c8b4-4bc0-b732-d4425ee508b7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775790217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.rv_timer_cfg_update_on_fly.775790217
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2164188924
Short name T8
Test name
Test status
Simulation time 69227148328 ps
CPU time 115.41 seconds
Started Feb 29 01:01:25 PM PST 24
Finished Feb 29 01:03:21 PM PST 24
Peak memory 182724 kb
Host smart-62bef456-8b94-4f30-ab03-0dcbf0aed59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164188924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2164188924
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.3594224235
Short name T146
Test name
Test status
Simulation time 134332941108 ps
CPU time 111.38 seconds
Started Feb 29 01:01:32 PM PST 24
Finished Feb 29 01:03:23 PM PST 24
Peak memory 190924 kb
Host smart-b48883e0-f89a-47e5-8820-0388dba98e54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594224235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3594224235
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.94676243
Short name T345
Test name
Test status
Simulation time 49496228213 ps
CPU time 104.86 seconds
Started Feb 29 01:01:34 PM PST 24
Finished Feb 29 01:03:19 PM PST 24
Peak memory 182732 kb
Host smart-c850b651-0515-44a6-bdbc-09cf6e21cdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94676243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.94676243
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.4090188218
Short name T301
Test name
Test status
Simulation time 94411169031 ps
CPU time 160.21 seconds
Started Feb 29 01:01:27 PM PST 24
Finished Feb 29 01:04:07 PM PST 24
Peak memory 182632 kb
Host smart-b91a0143-6e4c-460e-9490-6325fc988fbf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090188218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.4090188218
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.887453647
Short name T369
Test name
Test status
Simulation time 79114896508 ps
CPU time 135.42 seconds
Started Feb 29 01:01:26 PM PST 24
Finished Feb 29 01:03:42 PM PST 24
Peak memory 182740 kb
Host smart-1d363b58-b2ff-41e6-a779-5104b82c5a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887453647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.887453647
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2529934528
Short name T259
Test name
Test status
Simulation time 25578181666 ps
CPU time 281.61 seconds
Started Feb 29 01:01:26 PM PST 24
Finished Feb 29 01:06:08 PM PST 24
Peak memory 182612 kb
Host smart-98ff6a9b-9c96-4f9f-b67d-d59ab84a9570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529934528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2529934528
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.162354626
Short name T58
Test name
Test status
Simulation time 1213654038951 ps
CPU time 490.81 seconds
Started Feb 29 01:01:31 PM PST 24
Finished Feb 29 01:09:42 PM PST 24
Peak memory 195172 kb
Host smart-3d9d2b15-bbb0-44f7-9263-5ccade9eccfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162354626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.
162354626
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2906956952
Short name T243
Test name
Test status
Simulation time 286818503738 ps
CPU time 259.34 seconds
Started Feb 29 01:01:30 PM PST 24
Finished Feb 29 01:05:50 PM PST 24
Peak memory 182736 kb
Host smart-3bb5d22f-6664-40f6-9e75-8bf6f6c31095
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906956952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.2906956952
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.2535431753
Short name T398
Test name
Test status
Simulation time 499199133078 ps
CPU time 220.66 seconds
Started Feb 29 01:01:24 PM PST 24
Finished Feb 29 01:05:05 PM PST 24
Peak memory 182544 kb
Host smart-d419b76d-f808-4218-a8b5-b92363aae551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535431753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2535431753
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.689530620
Short name T234
Test name
Test status
Simulation time 148169926685 ps
CPU time 231.02 seconds
Started Feb 29 01:01:31 PM PST 24
Finished Feb 29 01:05:22 PM PST 24
Peak memory 190916 kb
Host smart-76a9515f-ae7d-4132-8892-b1b1964c06e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689530620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.689530620
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.569695354
Short name T351
Test name
Test status
Simulation time 205923359042 ps
CPU time 458.01 seconds
Started Feb 29 01:01:32 PM PST 24
Finished Feb 29 01:09:11 PM PST 24
Peak memory 190884 kb
Host smart-561e22cb-0d5a-43f1-9f82-f6c1f4c1a2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569695354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.569695354
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.616485687
Short name T422
Test name
Test status
Simulation time 26184661662 ps
CPU time 44.2 seconds
Started Feb 29 01:01:23 PM PST 24
Finished Feb 29 01:02:07 PM PST 24
Peak memory 182736 kb
Host smart-ed9f9a2d-5b1a-4657-9ada-7d5529b20460
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616485687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.rv_timer_cfg_update_on_fly.616485687
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2129202075
Short name T364
Test name
Test status
Simulation time 45345930926 ps
CPU time 65.78 seconds
Started Feb 29 01:01:30 PM PST 24
Finished Feb 29 01:02:36 PM PST 24
Peak memory 182704 kb
Host smart-11aa049d-5598-4e1c-a9ed-8f26e6ba0c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129202075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2129202075
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.1102255293
Short name T116
Test name
Test status
Simulation time 2052857738 ps
CPU time 4.96 seconds
Started Feb 29 01:01:29 PM PST 24
Finished Feb 29 01:01:34 PM PST 24
Peak memory 182652 kb
Host smart-1ee2410a-b54f-4692-a03b-d9c9836d80e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102255293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1102255293
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.250010704
Short name T104
Test name
Test status
Simulation time 61982226714 ps
CPU time 36.54 seconds
Started Feb 29 01:01:25 PM PST 24
Finished Feb 29 01:02:02 PM PST 24
Peak memory 182736 kb
Host smart-aba19ccc-c790-474f-91cd-ce6fae86c02b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250010704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.250010704
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1383395756
Short name T370
Test name
Test status
Simulation time 311055064985 ps
CPU time 151.21 seconds
Started Feb 29 01:01:27 PM PST 24
Finished Feb 29 01:03:58 PM PST 24
Peak memory 182724 kb
Host smart-5728fc82-246b-447b-bf9b-51b06ed60035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383395756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1383395756
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2032267281
Short name T167
Test name
Test status
Simulation time 74011671734 ps
CPU time 130.86 seconds
Started Feb 29 01:01:32 PM PST 24
Finished Feb 29 01:03:43 PM PST 24
Peak memory 182708 kb
Host smart-e7c54926-0d43-4c54-b6ef-df98ba060fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032267281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2032267281
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3944036260
Short name T244
Test name
Test status
Simulation time 87805021312 ps
CPU time 158.63 seconds
Started Feb 29 01:01:23 PM PST 24
Finished Feb 29 01:04:02 PM PST 24
Peak memory 182752 kb
Host smart-728057d1-896a-4cc7-ac73-2c1042c8f037
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944036260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3944036260
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1107611658
Short name T435
Test name
Test status
Simulation time 482502778391 ps
CPU time 223.72 seconds
Started Feb 29 01:01:28 PM PST 24
Finished Feb 29 01:05:12 PM PST 24
Peak memory 182720 kb
Host smart-12f564ef-8b12-455c-b141-ecc2812ddb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107611658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1107611658
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.2116902191
Short name T69
Test name
Test status
Simulation time 925127975817 ps
CPU time 540.86 seconds
Started Feb 29 01:01:26 PM PST 24
Finished Feb 29 01:10:27 PM PST 24
Peak memory 190920 kb
Host smart-3ecbb9e0-e4d0-4887-a6b3-a1537d265f19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116902191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2116902191
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.57487183
Short name T308
Test name
Test status
Simulation time 276202319655 ps
CPU time 66.38 seconds
Started Feb 29 01:01:30 PM PST 24
Finished Feb 29 01:02:37 PM PST 24
Peak memory 182932 kb
Host smart-7ae3577d-098e-4ac9-a5d3-1be40ab2dd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57487183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.57487183
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.4251256183
Short name T153
Test name
Test status
Simulation time 324988140027 ps
CPU time 732.07 seconds
Started Feb 29 01:01:31 PM PST 24
Finished Feb 29 01:13:44 PM PST 24
Peak memory 190968 kb
Host smart-e63b9fa3-7b37-4fd0-bb8d-9959da90485d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251256183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.4251256183
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3830599893
Short name T27
Test name
Test status
Simulation time 89701159174 ps
CPU time 147.14 seconds
Started Feb 29 01:00:46 PM PST 24
Finished Feb 29 01:03:13 PM PST 24
Peak memory 182760 kb
Host smart-879fb861-61c9-46b9-b2c1-ac4c5bbcfb3a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830599893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3830599893
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3119140971
Short name T412
Test name
Test status
Simulation time 26704542936 ps
CPU time 36.01 seconds
Started Feb 29 01:00:45 PM PST 24
Finished Feb 29 01:01:21 PM PST 24
Peak memory 182732 kb
Host smart-fd91cb2d-3a98-4bdc-a34e-950722313ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119140971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3119140971
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.916740057
Short name T352
Test name
Test status
Simulation time 289881139244 ps
CPU time 54.86 seconds
Started Feb 29 01:00:48 PM PST 24
Finished Feb 29 01:01:43 PM PST 24
Peak memory 193928 kb
Host smart-462eabac-e874-43fc-8dd9-304826f28897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916740057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.916740057
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.1041403047
Short name T154
Test name
Test status
Simulation time 108163977996 ps
CPU time 196.18 seconds
Started Feb 29 01:01:33 PM PST 24
Finished Feb 29 01:04:49 PM PST 24
Peak memory 182688 kb
Host smart-41e73206-190e-4c8d-8b20-2febafaad008
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041403047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1041403047
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.1246362735
Short name T134
Test name
Test status
Simulation time 205320463402 ps
CPU time 94.32 seconds
Started Feb 29 01:01:27 PM PST 24
Finished Feb 29 01:03:01 PM PST 24
Peak memory 182648 kb
Host smart-670e61ff-c3a7-4ff3-b892-c238aeb81c30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246362735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1246362735
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.450934536
Short name T278
Test name
Test status
Simulation time 121497355399 ps
CPU time 216.79 seconds
Started Feb 29 01:01:31 PM PST 24
Finished Feb 29 01:05:08 PM PST 24
Peak memory 190852 kb
Host smart-14bcfa8f-56d3-4f10-8bc2-807aadd3ed69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450934536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.450934536
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.127415390
Short name T320
Test name
Test status
Simulation time 290546625875 ps
CPU time 568.97 seconds
Started Feb 29 01:01:31 PM PST 24
Finished Feb 29 01:11:01 PM PST 24
Peak memory 191108 kb
Host smart-010ab889-28a9-4cab-bff6-3af2e38515c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127415390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.127415390
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.1842507123
Short name T22
Test name
Test status
Simulation time 160066952423 ps
CPU time 413.74 seconds
Started Feb 29 01:01:30 PM PST 24
Finished Feb 29 01:08:24 PM PST 24
Peak memory 190912 kb
Host smart-e3aa224d-6911-4e90-b474-0d5a45625af9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842507123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1842507123
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.214269520
Short name T437
Test name
Test status
Simulation time 179715527489 ps
CPU time 156.89 seconds
Started Feb 29 01:01:30 PM PST 24
Finished Feb 29 01:04:07 PM PST 24
Peak memory 190852 kb
Host smart-88bc878c-cb7b-4d91-8c83-2f35586376c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214269520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.214269520
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.1920155256
Short name T338
Test name
Test status
Simulation time 128696029062 ps
CPU time 54.74 seconds
Started Feb 29 01:01:23 PM PST 24
Finished Feb 29 01:02:19 PM PST 24
Peak memory 182732 kb
Host smart-8419eee4-f514-4d19-afbc-1134e43ef94a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920155256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.1920155256
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.3424946454
Short name T444
Test name
Test status
Simulation time 162923828702 ps
CPU time 40.11 seconds
Started Feb 29 01:01:32 PM PST 24
Finished Feb 29 01:02:12 PM PST 24
Peak memory 191108 kb
Host smart-0fc6d44f-14d5-4df5-9241-6bc820745a4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424946454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3424946454
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.44387907
Short name T250
Test name
Test status
Simulation time 60535453012 ps
CPU time 941.79 seconds
Started Feb 29 01:01:35 PM PST 24
Finished Feb 29 01:17:17 PM PST 24
Peak memory 190992 kb
Host smart-9ae630e7-3f08-4c97-ae6c-71789e7930c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44387907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.44387907
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1803684177
Short name T147
Test name
Test status
Simulation time 10407641165 ps
CPU time 19.84 seconds
Started Feb 29 01:00:47 PM PST 24
Finished Feb 29 01:01:07 PM PST 24
Peak memory 182804 kb
Host smart-730ad5e9-65ff-4385-8bf1-1688ea6b085a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803684177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1803684177
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.3229776950
Short name T353
Test name
Test status
Simulation time 199503560011 ps
CPU time 310.87 seconds
Started Feb 29 01:00:47 PM PST 24
Finished Feb 29 01:05:58 PM PST 24
Peak memory 182612 kb
Host smart-084b1903-5f74-45e9-af6b-c237df824d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229776950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3229776950
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.171871210
Short name T101
Test name
Test status
Simulation time 309299605064 ps
CPU time 245.74 seconds
Started Feb 29 01:00:47 PM PST 24
Finished Feb 29 01:04:53 PM PST 24
Peak memory 190936 kb
Host smart-fb2b4ca7-e8f3-4d36-9d3a-35596e11a6ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171871210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.171871210
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1717827377
Short name T223
Test name
Test status
Simulation time 57783007601 ps
CPU time 51.44 seconds
Started Feb 29 01:00:49 PM PST 24
Finished Feb 29 01:01:41 PM PST 24
Peak memory 194368 kb
Host smart-3cc05452-febd-4fb4-9518-7b673b7e9714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717827377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1717827377
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1856751038
Short name T111
Test name
Test status
Simulation time 1669870027095 ps
CPU time 1562.58 seconds
Started Feb 29 01:00:48 PM PST 24
Finished Feb 29 01:26:51 PM PST 24
Peak memory 190948 kb
Host smart-e2b49713-dfad-4af8-92aa-7e235cd0f1b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856751038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1856751038
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.3249230858
Short name T108
Test name
Test status
Simulation time 527478852130 ps
CPU time 824.39 seconds
Started Feb 29 01:01:33 PM PST 24
Finished Feb 29 01:15:17 PM PST 24
Peak memory 190888 kb
Host smart-d9fca7b3-4ebf-4a87-92cf-5803f2043ed7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249230858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3249230858
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.3567111266
Short name T172
Test name
Test status
Simulation time 44496167342 ps
CPU time 72.55 seconds
Started Feb 29 01:01:33 PM PST 24
Finished Feb 29 01:02:46 PM PST 24
Peak memory 182796 kb
Host smart-dbfca467-2a83-4495-a292-ce050ea2f39f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567111266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3567111266
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.757451944
Short name T51
Test name
Test status
Simulation time 25116602977 ps
CPU time 37.95 seconds
Started Feb 29 01:01:33 PM PST 24
Finished Feb 29 01:02:11 PM PST 24
Peak memory 182544 kb
Host smart-8be73e4d-ad16-4f67-8b25-4d4eab95b3b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757451944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.757451944
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.934280965
Short name T257
Test name
Test status
Simulation time 70625410948 ps
CPU time 127.28 seconds
Started Feb 29 01:01:39 PM PST 24
Finished Feb 29 01:03:47 PM PST 24
Peak memory 190872 kb
Host smart-83b0bb0a-ba7c-453e-8fe8-a302480d4336
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934280965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.934280965
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.3246541573
Short name T343
Test name
Test status
Simulation time 46708972165 ps
CPU time 80.79 seconds
Started Feb 29 01:01:37 PM PST 24
Finished Feb 29 01:02:58 PM PST 24
Peak memory 190872 kb
Host smart-06fc3668-a909-45a8-9721-c50ea6d3bd79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246541573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3246541573
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1168134615
Short name T231
Test name
Test status
Simulation time 1978763169041 ps
CPU time 866.94 seconds
Started Feb 29 01:01:33 PM PST 24
Finished Feb 29 01:16:00 PM PST 24
Peak memory 190888 kb
Host smart-0a4720d9-b143-4c58-9607-b1981751a866
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168134615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1168134615
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1975594686
Short name T112
Test name
Test status
Simulation time 773258237319 ps
CPU time 658.84 seconds
Started Feb 29 01:01:32 PM PST 24
Finished Feb 29 01:12:31 PM PST 24
Peak memory 190912 kb
Host smart-cbd27d81-0776-455e-9545-db136c281cf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975594686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1975594686
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.2815057288
Short name T296
Test name
Test status
Simulation time 159876469568 ps
CPU time 140.02 seconds
Started Feb 29 01:01:31 PM PST 24
Finished Feb 29 01:03:51 PM PST 24
Peak memory 194268 kb
Host smart-c8e860f2-e558-46f3-89b1-6b78416e69f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815057288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2815057288
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.4264893157
Short name T321
Test name
Test status
Simulation time 56857647930 ps
CPU time 87.08 seconds
Started Feb 29 01:01:39 PM PST 24
Finished Feb 29 01:03:07 PM PST 24
Peak memory 182660 kb
Host smart-83ead688-3781-4e85-9c66-1da11b839b82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264893157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.4264893157
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.2020238677
Short name T224
Test name
Test status
Simulation time 203841358827 ps
CPU time 178.64 seconds
Started Feb 29 01:01:31 PM PST 24
Finished Feb 29 01:04:30 PM PST 24
Peak memory 194664 kb
Host smart-fb8d3146-20d2-4dc9-a6ed-89e024cd9651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020238677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2020238677
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.2389937275
Short name T264
Test name
Test status
Simulation time 3872598578438 ps
CPU time 903.68 seconds
Started Feb 29 01:00:42 PM PST 24
Finished Feb 29 01:15:46 PM PST 24
Peak memory 182572 kb
Host smart-4526d039-82fd-48fc-90c8-fcf36c98087a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389937275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.2389937275
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3218641670
Short name T408
Test name
Test status
Simulation time 254867288426 ps
CPU time 117.45 seconds
Started Feb 29 01:00:46 PM PST 24
Finished Feb 29 01:02:43 PM PST 24
Peak memory 182736 kb
Host smart-be2ff776-b9db-472b-8f48-d27a9f8a67ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218641670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3218641670
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.1045858529
Short name T78
Test name
Test status
Simulation time 160384192475 ps
CPU time 159.43 seconds
Started Feb 29 01:00:46 PM PST 24
Finished Feb 29 01:03:26 PM PST 24
Peak memory 190928 kb
Host smart-7d49e3da-004f-4bfa-955e-1f01b63bd0e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045858529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1045858529
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.3892337288
Short name T374
Test name
Test status
Simulation time 96629155 ps
CPU time 0.66 seconds
Started Feb 29 01:00:50 PM PST 24
Finished Feb 29 01:00:51 PM PST 24
Peak memory 182148 kb
Host smart-7ec6f941-99b3-4d88-aaec-841795f97a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892337288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3892337288
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1009898860
Short name T57
Test name
Test status
Simulation time 176921997883 ps
CPU time 123.82 seconds
Started Feb 29 01:00:50 PM PST 24
Finished Feb 29 01:02:54 PM PST 24
Peak memory 190984 kb
Host smart-99adb072-4a44-4327-b86f-05d178c7d163
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009898860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1009898860
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.2738068207
Short name T13
Test name
Test status
Simulation time 34029492189 ps
CPU time 264.56 seconds
Started Feb 29 01:00:50 PM PST 24
Finished Feb 29 01:05:15 PM PST 24
Peak memory 197344 kb
Host smart-aac7011e-a07b-418b-bea0-bc7482fe714b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738068207 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.2738068207
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.3495953047
Short name T289
Test name
Test status
Simulation time 47724702744 ps
CPU time 111.53 seconds
Started Feb 29 01:01:32 PM PST 24
Finished Feb 29 01:03:24 PM PST 24
Peak memory 193796 kb
Host smart-4caed89c-0256-419c-839a-2c9815a2341f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495953047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3495953047
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.4263024368
Short name T428
Test name
Test status
Simulation time 166057868441 ps
CPU time 908.58 seconds
Started Feb 29 01:01:34 PM PST 24
Finished Feb 29 01:16:43 PM PST 24
Peak memory 193752 kb
Host smart-d21f8a6e-ab50-41b0-8bc9-07517b303a1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263024368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.4263024368
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.421101145
Short name T225
Test name
Test status
Simulation time 103526144044 ps
CPU time 461.65 seconds
Started Feb 29 01:01:35 PM PST 24
Finished Feb 29 01:09:16 PM PST 24
Peak memory 194308 kb
Host smart-bfa6e0e9-67b0-4676-a2d7-8de37fa09a72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421101145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.421101145
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.4104813110
Short name T106
Test name
Test status
Simulation time 90523022469 ps
CPU time 260.43 seconds
Started Feb 29 01:01:39 PM PST 24
Finished Feb 29 01:06:00 PM PST 24
Peak memory 190860 kb
Host smart-cc2194e4-bbbe-4377-8da0-593234248ce8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104813110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.4104813110
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.202369926
Short name T271
Test name
Test status
Simulation time 217101553576 ps
CPU time 87.45 seconds
Started Feb 29 01:01:37 PM PST 24
Finished Feb 29 01:03:05 PM PST 24
Peak memory 182596 kb
Host smart-625a2cbd-f5a2-4600-a2d5-b2820fadee1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202369926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.202369926
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.1799463701
Short name T115
Test name
Test status
Simulation time 129664507234 ps
CPU time 53.81 seconds
Started Feb 29 01:01:36 PM PST 24
Finished Feb 29 01:02:31 PM PST 24
Peak memory 193060 kb
Host smart-f93dd0b7-9f95-4151-9090-7b8b59041c52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799463701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1799463701
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.2780309307
Short name T168
Test name
Test status
Simulation time 443267602041 ps
CPU time 189.14 seconds
Started Feb 29 01:01:36 PM PST 24
Finished Feb 29 01:04:46 PM PST 24
Peak memory 182588 kb
Host smart-ab0f3dcd-c7f9-482e-a17c-e09f73c04e0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780309307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.2780309307
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.4042314522
Short name T400
Test name
Test status
Simulation time 2397447074 ps
CPU time 4.24 seconds
Started Feb 29 01:01:29 PM PST 24
Finished Feb 29 01:01:34 PM PST 24
Peak memory 182548 kb
Host smart-b876c50c-51d6-422d-b713-29bec716e260
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042314522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.4042314522
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.1856901151
Short name T441
Test name
Test status
Simulation time 463113580405 ps
CPU time 522.65 seconds
Started Feb 29 01:01:30 PM PST 24
Finished Feb 29 01:10:13 PM PST 24
Peak memory 193172 kb
Host smart-930817ab-ab37-497f-9094-9c1f7d6ddcf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856901151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1856901151
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.772180075
Short name T245
Test name
Test status
Simulation time 277079148915 ps
CPU time 501.62 seconds
Started Feb 29 01:00:42 PM PST 24
Finished Feb 29 01:09:03 PM PST 24
Peak memory 182536 kb
Host smart-a8a6e91f-4880-41f5-8be7-ce22c66aa8b4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772180075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.rv_timer_cfg_update_on_fly.772180075
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3744902817
Short name T368
Test name
Test status
Simulation time 585634870593 ps
CPU time 251.42 seconds
Started Feb 29 01:00:49 PM PST 24
Finished Feb 29 01:05:01 PM PST 24
Peak memory 182740 kb
Host smart-3687761f-5123-4617-9bfc-07b660161096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744902817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3744902817
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.513345239
Short name T206
Test name
Test status
Simulation time 88528379650 ps
CPU time 191.31 seconds
Started Feb 29 01:00:42 PM PST 24
Finished Feb 29 01:03:54 PM PST 24
Peak memory 190952 kb
Host smart-e00e2618-1fe8-4a59-b8ff-7c91979a3dcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513345239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.513345239
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.3549533721
Short name T382
Test name
Test status
Simulation time 147371614 ps
CPU time 0.75 seconds
Started Feb 29 01:00:50 PM PST 24
Finished Feb 29 01:00:51 PM PST 24
Peak memory 182476 kb
Host smart-97d7d20d-fa79-4c88-a53a-99f7a2d3e88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549533721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3549533721
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.1214959925
Short name T62
Test name
Test status
Simulation time 121499398710 ps
CPU time 423.79 seconds
Started Feb 29 01:00:49 PM PST 24
Finished Feb 29 01:07:53 PM PST 24
Peak memory 194352 kb
Host smart-8475cf6f-c85c-4fe4-9a8b-d94b5529ddd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214959925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
1214959925
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/81.rv_timer_random.4023803960
Short name T123
Test name
Test status
Simulation time 50736007014 ps
CPU time 104.43 seconds
Started Feb 29 01:01:33 PM PST 24
Finished Feb 29 01:03:18 PM PST 24
Peak memory 190904 kb
Host smart-122736f8-7924-4a09-99a4-896563456e13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023803960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.4023803960
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.3179302352
Short name T130
Test name
Test status
Simulation time 148589970337 ps
CPU time 100.92 seconds
Started Feb 29 01:01:37 PM PST 24
Finished Feb 29 01:03:19 PM PST 24
Peak memory 190812 kb
Host smart-ff8c1b4d-34de-4cb4-b5c7-e768271b0c9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179302352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3179302352
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.2295582182
Short name T254
Test name
Test status
Simulation time 34809033732 ps
CPU time 836.3 seconds
Started Feb 29 01:01:38 PM PST 24
Finished Feb 29 01:15:35 PM PST 24
Peak memory 193672 kb
Host smart-b149f7c4-cb46-49c6-a051-83edca414eb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295582182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.2295582182
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.4015512392
Short name T246
Test name
Test status
Simulation time 360216473683 ps
CPU time 207.08 seconds
Started Feb 29 01:01:38 PM PST 24
Finished Feb 29 01:05:05 PM PST 24
Peak memory 190928 kb
Host smart-ec62b464-dc91-4354-8b98-9ccfa1b506ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015512392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.4015512392
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.256669260
Short name T175
Test name
Test status
Simulation time 357737465306 ps
CPU time 216.26 seconds
Started Feb 29 01:01:38 PM PST 24
Finished Feb 29 01:05:15 PM PST 24
Peak memory 190932 kb
Host smart-7585d658-0b03-48bc-b9a5-ea72fa45c735
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256669260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.256669260
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.4268605691
Short name T337
Test name
Test status
Simulation time 35096326254 ps
CPU time 20.92 seconds
Started Feb 29 01:01:37 PM PST 24
Finished Feb 29 01:01:58 PM PST 24
Peak memory 182736 kb
Host smart-f19b7fdd-bf87-4edd-8082-1b72a63620b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268605691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.4268605691
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.3260932167
Short name T48
Test name
Test status
Simulation time 177774404744 ps
CPU time 1834.57 seconds
Started Feb 29 01:01:40 PM PST 24
Finished Feb 29 01:32:15 PM PST 24
Peak memory 190900 kb
Host smart-8de3e170-d3fe-43f3-a7f7-839e13937eac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260932167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3260932167
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2517082765
Short name T176
Test name
Test status
Simulation time 58796365607 ps
CPU time 97.64 seconds
Started Feb 29 01:00:44 PM PST 24
Finished Feb 29 01:02:22 PM PST 24
Peak memory 182780 kb
Host smart-1ae915a2-72f0-4383-8d1d-959464dcf586
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517082765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2517082765
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.2088986012
Short name T424
Test name
Test status
Simulation time 127357422468 ps
CPU time 55.76 seconds
Started Feb 29 01:00:43 PM PST 24
Finished Feb 29 01:01:38 PM PST 24
Peak memory 182740 kb
Host smart-e8602695-af47-4ef6-9f6f-20be3536e5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088986012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2088986012
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.505746442
Short name T6
Test name
Test status
Simulation time 287159149081 ps
CPU time 206.79 seconds
Started Feb 29 01:00:48 PM PST 24
Finished Feb 29 01:04:15 PM PST 24
Peak memory 190856 kb
Host smart-463057ca-0a9d-4aa2-8171-41503e620d51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505746442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.505746442
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.4211320306
Short name T405
Test name
Test status
Simulation time 209141022 ps
CPU time 0.63 seconds
Started Feb 29 01:00:45 PM PST 24
Finished Feb 29 01:00:45 PM PST 24
Peak memory 182532 kb
Host smart-5bf0ea92-682b-49bc-b25d-95ee55a1b9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211320306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.4211320306
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.2476353931
Short name T204
Test name
Test status
Simulation time 476262018518 ps
CPU time 190.65 seconds
Started Feb 29 01:01:35 PM PST 24
Finished Feb 29 01:04:46 PM PST 24
Peak memory 190900 kb
Host smart-bc8aac3e-42c0-455e-9314-68d199f2d014
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476353931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2476353931
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1657874647
Short name T124
Test name
Test status
Simulation time 54402653015 ps
CPU time 84.64 seconds
Started Feb 29 01:01:37 PM PST 24
Finished Feb 29 01:03:02 PM PST 24
Peak memory 190976 kb
Host smart-d4f02348-73cc-4bd1-aff3-8a297705349c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657874647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1657874647
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.1121141529
Short name T439
Test name
Test status
Simulation time 160579806801 ps
CPU time 66.95 seconds
Started Feb 29 01:01:38 PM PST 24
Finished Feb 29 01:02:45 PM PST 24
Peak memory 182732 kb
Host smart-9b6a8de4-1256-49c6-bb06-62a17efbcfca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121141529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1121141529
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3698162140
Short name T411
Test name
Test status
Simulation time 195925422240 ps
CPU time 212.48 seconds
Started Feb 29 01:01:37 PM PST 24
Finished Feb 29 01:05:10 PM PST 24
Peak memory 190932 kb
Host smart-879c5844-9945-437f-b7d7-9637840a80c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698162140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3698162140
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.653666841
Short name T159
Test name
Test status
Simulation time 1125538625680 ps
CPU time 726.98 seconds
Started Feb 29 01:01:37 PM PST 24
Finished Feb 29 01:13:45 PM PST 24
Peak memory 193056 kb
Host smart-756d8be0-6735-4a4b-98a0-c6a35796df69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653666841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.653666841
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.2968750310
Short name T226
Test name
Test status
Simulation time 269904369975 ps
CPU time 73.16 seconds
Started Feb 29 01:01:41 PM PST 24
Finished Feb 29 01:02:54 PM PST 24
Peak memory 182720 kb
Host smart-f060cc10-18e0-4dff-a595-df58118d7a48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968750310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2968750310
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1235179824
Short name T303
Test name
Test status
Simulation time 332395741672 ps
CPU time 381.02 seconds
Started Feb 29 01:01:40 PM PST 24
Finished Feb 29 01:08:02 PM PST 24
Peak memory 194112 kb
Host smart-894fa725-95dd-4250-b2b6-3eab0f7598ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235179824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1235179824
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.370500136
Short name T427
Test name
Test status
Simulation time 129997289755 ps
CPU time 117.88 seconds
Started Feb 29 01:01:36 PM PST 24
Finished Feb 29 01:03:35 PM PST 24
Peak memory 190988 kb
Host smart-236287b1-6f1c-4234-8345-25bd2ddc4869
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370500136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.370500136
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.4287721377
Short name T339
Test name
Test status
Simulation time 94057054330 ps
CPU time 469.39 seconds
Started Feb 29 01:01:45 PM PST 24
Finished Feb 29 01:09:34 PM PST 24
Peak memory 182632 kb
Host smart-3435bf6f-1449-4e93-a73e-5f4b9d69734a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287721377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.4287721377
Directory /workspace/99.rv_timer_random/latest
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