| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.59 | 99.36 | 98.73 | 100.00 | 100.00 | 100.00 | 99.43 |
| T504 | /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.555699341 | Mar 03 12:33:34 PM PST 24 | Mar 03 12:33:35 PM PST 24 | 45715750 ps | ||
| T505 | /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2522555187 | Mar 03 12:33:28 PM PST 24 | Mar 03 12:33:30 PM PST 24 | 154460633 ps | ||
| T506 | /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.256732316 | Mar 03 12:33:27 PM PST 24 | Mar 03 12:33:29 PM PST 24 | 376085516 ps | ||
| T507 | /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.218868752 | Mar 03 12:33:17 PM PST 24 | Mar 03 12:33:22 PM PST 24 | 1108604912 ps | ||
| T508 | /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1309303632 | Mar 03 12:33:18 PM PST 24 | Mar 03 12:33:19 PM PST 24 | 43023313 ps | ||
| T509 | /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1215327698 | Mar 03 12:33:15 PM PST 24 | Mar 03 12:33:16 PM PST 24 | 29954298 ps | ||
| T510 | /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3038286872 | Mar 03 12:33:35 PM PST 24 | Mar 03 12:33:36 PM PST 24 | 16451830 ps | ||
| T511 | /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.635135692 | Mar 03 12:33:18 PM PST 24 | Mar 03 12:33:19 PM PST 24 | 264235565 ps | ||
| T512 | /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2130284619 | Mar 03 12:33:17 PM PST 24 | Mar 03 12:33:18 PM PST 24 | 19955409 ps | ||
| T513 | /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2936303683 | Mar 03 12:33:37 PM PST 24 | Mar 03 12:33:39 PM PST 24 | 275360333 ps | ||
| T514 | /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3275425756 | Mar 03 12:33:19 PM PST 24 | Mar 03 12:33:21 PM PST 24 | 202863095 ps | ||
| T515 | /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.401708837 | Mar 03 12:33:23 PM PST 24 | Mar 03 12:33:24 PM PST 24 | 71508796 ps | ||
| T516 | /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3620027393 | Mar 03 12:33:19 PM PST 24 | Mar 03 12:33:20 PM PST 24 | 12210994 ps | ||
| T517 | /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.158993242 | Mar 03 12:33:29 PM PST 24 | Mar 03 12:33:30 PM PST 24 | 20717497 ps | ||
| T518 | /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1756035341 | Mar 03 12:33:12 PM PST 24 | Mar 03 12:33:13 PM PST 24 | 37110888 ps | ||
| T519 | /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1803171964 | Mar 03 12:33:19 PM PST 24 | Mar 03 12:33:20 PM PST 24 | 23491488 ps | ||
| T520 | /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.153854461 | Mar 03 12:33:19 PM PST 24 | Mar 03 12:33:20 PM PST 24 | 23436495 ps | ||
| T521 | /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3976568954 | Mar 03 12:33:42 PM PST 24 | Mar 03 12:33:43 PM PST 24 | 19304769 ps | ||
| T522 | /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1129871908 | Mar 03 12:33:19 PM PST 24 | Mar 03 12:33:21 PM PST 24 | 125275235 ps | ||
| T523 | /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.955170278 | Mar 03 12:34:45 PM PST 24 | Mar 03 12:34:47 PM PST 24 | 26691059 ps | ||
| T524 | /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3109897658 | Mar 03 12:33:15 PM PST 24 | Mar 03 12:33:16 PM PST 24 | 24238679 ps | ||
| T525 | /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2670556620 | Mar 03 12:33:44 PM PST 24 | Mar 03 12:33:45 PM PST 24 | 17021580 ps | ||
| T526 | /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.251005651 | Mar 03 12:33:17 PM PST 24 | Mar 03 12:33:18 PM PST 24 | 14779973 ps | ||
| T527 | /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3428023253 | Mar 03 12:33:36 PM PST 24 | Mar 03 12:33:38 PM PST 24 | 973216189 ps | ||
| T528 | /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.564572866 | Mar 03 12:33:14 PM PST 24 | Mar 03 12:33:20 PM PST 24 | 24802652 ps | ||
| T529 | /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3145514079 | Mar 03 12:33:18 PM PST 24 | Mar 03 12:33:19 PM PST 24 | 32759165 ps | ||
| T530 | /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.727725654 | Mar 03 12:33:14 PM PST 24 | Mar 03 12:33:18 PM PST 24 | 1838802120 ps | ||
| T531 | /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.160406086 | Mar 03 12:33:18 PM PST 24 | Mar 03 12:33:19 PM PST 24 | 24305270 ps | ||
| T532 | /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1061509793 | Mar 03 12:33:19 PM PST 24 | Mar 03 12:33:20 PM PST 24 | 82787076 ps | ||
| T533 | /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1149878256 | Mar 03 12:33:19 PM PST 24 | Mar 03 12:33:20 PM PST 24 | 54900836 ps | ||
| T534 | /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.119345966 | Mar 03 12:33:39 PM PST 24 | Mar 03 12:33:40 PM PST 24 | 39189760 ps | ||
| T535 | /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2612585933 | Mar 03 12:33:27 PM PST 24 | Mar 03 12:33:28 PM PST 24 | 28903300 ps | ||
| T536 | /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.4226713441 | Mar 03 12:33:36 PM PST 24 | Mar 03 12:33:37 PM PST 24 | 29295111 ps | ||
| T537 | /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.804307796 | Mar 03 12:33:26 PM PST 24 | Mar 03 12:33:33 PM PST 24 | 232987131 ps | ||
| T538 | /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.80876878 | Mar 03 12:33:19 PM PST 24 | Mar 03 12:33:20 PM PST 24 | 39237476 ps | ||
| T539 | /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.621491975 | Mar 03 12:33:29 PM PST 24 | Mar 03 12:33:30 PM PST 24 | 25315259 ps | ||
| T540 | /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.82080082 | Mar 03 12:33:18 PM PST 24 | Mar 03 12:33:19 PM PST 24 | 12407551 ps | ||
| T541 | /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1889174588 | Mar 03 12:33:56 PM PST 24 | Mar 03 12:33:56 PM PST 24 | 32801949 ps | ||
| T542 | /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.759929648 | Mar 03 12:33:19 PM PST 24 | Mar 03 12:33:19 PM PST 24 | 32143116 ps | ||
| T543 | /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.708362897 | Mar 03 12:33:20 PM PST 24 | Mar 03 12:33:21 PM PST 24 | 31133086 ps | ||
| T92 | /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1325415723 | Mar 03 12:33:16 PM PST 24 | Mar 03 12:33:17 PM PST 24 | 14099733 ps | ||
| T544 | /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2022694143 | Mar 03 12:33:19 PM PST 24 | Mar 03 12:33:19 PM PST 24 | 38587874 ps | ||
| T545 | /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.212101445 | Mar 03 12:33:31 PM PST 24 | Mar 03 12:33:33 PM PST 24 | 28021518 ps | ||
| T546 | /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.94025565 | Mar 03 12:33:35 PM PST 24 | Mar 03 12:33:36 PM PST 24 | 41965084 ps | ||
| T93 | /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.179957442 | Mar 03 12:33:17 PM PST 24 | Mar 03 12:33:23 PM PST 24 | 28847896 ps | ||
| T547 | /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.4041746179 | Mar 03 12:33:17 PM PST 24 | Mar 03 12:33:19 PM PST 24 | 57270457 ps | ||
| T548 | /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2886335992 | Mar 03 12:33:17 PM PST 24 | Mar 03 12:33:19 PM PST 24 | 215578281 ps | ||
| T549 | /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2343387608 | Mar 03 12:33:24 PM PST 24 | Mar 03 12:33:25 PM PST 24 | 60369149 ps | ||
| T550 | /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2230412585 | Mar 03 12:33:19 PM PST 24 | Mar 03 12:33:20 PM PST 24 | 28489989 ps | ||
| T551 | /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.195824491 | Mar 03 12:33:14 PM PST 24 | Mar 03 12:33:15 PM PST 24 | 26656245 ps | ||
| T552 | /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1153693185 | Mar 03 12:33:18 PM PST 24 | Mar 03 12:33:20 PM PST 24 | 41961012 ps | ||
| T553 | /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1035765288 | Mar 03 12:33:46 PM PST 24 | Mar 03 12:33:47 PM PST 24 | 17900086 ps | ||
| T554 | /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1697116866 | Mar 03 12:33:42 PM PST 24 | Mar 03 12:33:44 PM PST 24 | 447042422 ps | ||
| T555 | /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1644655697 | Mar 03 12:33:50 PM PST 24 | Mar 03 12:33:51 PM PST 24 | 42388192 ps | ||
| T556 | /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1560103880 | Mar 03 12:33:17 PM PST 24 | Mar 03 12:33:18 PM PST 24 | 25636162 ps | ||
| T557 | /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3382219707 | Mar 03 12:33:12 PM PST 24 | Mar 03 12:33:13 PM PST 24 | 59514706 ps | ||
| T94 | /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2935158475 | Mar 03 12:33:37 PM PST 24 | Mar 03 12:33:38 PM PST 24 | 15675672 ps | ||
| T558 | /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.4076912835 | Mar 03 12:33:17 PM PST 24 | Mar 03 12:33:19 PM PST 24 | 159637771 ps | ||
| T559 | /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.667537725 | Mar 03 12:33:19 PM PST 24 | Mar 03 12:33:20 PM PST 24 | 13895175 ps | ||
| T560 | /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1005718669 | Mar 03 12:33:23 PM PST 24 | Mar 03 12:33:25 PM PST 24 | 110384647 ps | ||
| T561 | /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.4061881116 | Mar 03 12:33:22 PM PST 24 | Mar 03 12:33:23 PM PST 24 | 46601392 ps | ||
| T562 | /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.307467932 | Mar 03 12:33:19 PM PST 24 | Mar 03 12:33:20 PM PST 24 | 13663427 ps | ||
| T563 | /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.63474295 | Mar 03 12:34:50 PM PST 24 | Mar 03 12:34:51 PM PST 24 | 34822522 ps | ||
| T564 | /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2024623551 | Mar 03 12:33:19 PM PST 24 | Mar 03 12:33:21 PM PST 24 | 185024013 ps | ||
| T565 | /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3613845694 | Mar 03 12:33:13 PM PST 24 | Mar 03 12:33:14 PM PST 24 | 85527243 ps | ||
| T566 | /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1510347486 | Mar 03 12:33:32 PM PST 24 | Mar 03 12:33:33 PM PST 24 | 62802992 ps | ||
| T567 | /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.860100647 | Mar 03 12:33:18 PM PST 24 | Mar 03 12:33:24 PM PST 24 | 61626560 ps | ||
| T568 | /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1746601112 | Mar 03 12:33:22 PM PST 24 | Mar 03 12:33:23 PM PST 24 | 13297257 ps | ||
| T569 | /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.374800678 | Mar 03 12:33:32 PM PST 24 | Mar 03 12:33:33 PM PST 24 | 28605528 ps | ||
| T570 | /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2786844559 | Mar 03 12:33:39 PM PST 24 | Mar 03 12:33:40 PM PST 24 | 26445515 ps | ||
| T571 | /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.992237209 | Mar 03 12:33:17 PM PST 24 | Mar 03 12:33:17 PM PST 24 | 20778973 ps | ||
| T572 | /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2941572747 | Mar 03 12:33:38 PM PST 24 | Mar 03 12:33:40 PM PST 24 | 11233833 ps | ||
| T573 | /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.582048092 | Mar 03 12:33:18 PM PST 24 | Mar 03 12:33:24 PM PST 24 | 20147548 ps |
| Test location | /workspace/coverage/default/23.rv_timer_stress_all.3021653110 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 681008527118 ps |
| CPU time | 1888.6 seconds |
| Started | Mar 03 04:09:44 PM PST 24 |
| Finished | Mar 03 04:41:13 PM PST 24 |
| Peak memory | 191440 kb |
| Host | smart-2779312e-996b-485a-aed1-8b238ff21810 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021653110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all .3021653110 |
| Directory | /workspace/23.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.3333448794 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 26260802481 ps |
| CPU time | 107.43 seconds |
| Started | Mar 03 04:08:22 PM PST 24 |
| Finished | Mar 03 04:10:10 PM PST 24 |
| Peak memory | 197884 kb |
| Host | smart-df34b77e-e067-4317-8aea-88f18949b390 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333448794 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.3333448794 |
| Directory | /workspace/12.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1571515437 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 336511098 ps |
| CPU time | 1.08 seconds |
| Started | Mar 03 12:33:26 PM PST 24 |
| Finished | Mar 03 12:33:27 PM PST 24 |
| Peak memory | 194804 kb |
| Host | smart-73a708bd-403a-47fb-b659-8d407bb86e88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571515437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in tg_err.1571515437 |
| Directory | /workspace/3.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/10.rv_timer_stress_all.351032181 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 2430251042053 ps |
| CPU time | 2199.51 seconds |
| Started | Mar 03 04:08:07 PM PST 24 |
| Finished | Mar 03 04:44:47 PM PST 24 |
| Peak memory | 191356 kb |
| Host | smart-096ae01d-b31d-44ef-bd07-a83db79a64fe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351032181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all. 351032181 |
| Directory | /workspace/10.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/4.rv_timer_stress_all.1094589851 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 628712227078 ps |
| CPU time | 888.38 seconds |
| Started | Mar 03 04:07:44 PM PST 24 |
| Finished | Mar 03 04:22:33 PM PST 24 |
| Peak memory | 191392 kb |
| Host | smart-1eff42e4-0fe3-4bd5-b849-7cde54a43c8c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094589851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all. 1094589851 |
| Directory | /workspace/4.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/11.rv_timer_stress_all.4014554216 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 2795878659674 ps |
| CPU time | 2982.39 seconds |
| Started | Mar 03 04:08:19 PM PST 24 |
| Finished | Mar 03 04:58:02 PM PST 24 |
| Peak memory | 191316 kb |
| Host | smart-f265bea7-75d6-4938-8e1d-d92263f80c6e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014554216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all .4014554216 |
| Directory | /workspace/11.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/134.rv_timer_random.1387231891 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 313866985039 ps |
| CPU time | 290.04 seconds |
| Started | Mar 03 04:14:10 PM PST 24 |
| Finished | Mar 03 04:19:01 PM PST 24 |
| Peak memory | 191364 kb |
| Host | smart-0f37b1a2-c21d-4450-b957-4f7f09ccae89 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387231891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1387231891 |
| Directory | /workspace/134.rv_timer_random/latest |
| Test location | /workspace/coverage/default/30.rv_timer_stress_all.3812800948 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 2000709739405 ps |
| CPU time | 1005.67 seconds |
| Started | Mar 03 04:10:38 PM PST 24 |
| Finished | Mar 03 04:27:24 PM PST 24 |
| Peak memory | 195272 kb |
| Host | smart-eca2ab6c-ea0e-49e3-8966-458b8e464986 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812800948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all .3812800948 |
| Directory | /workspace/30.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1438569412 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 43537167 ps |
| CPU time | 0.61 seconds |
| Started | Mar 03 12:33:39 PM PST 24 |
| Finished | Mar 03 12:33:40 PM PST 24 |
| Peak memory | 182620 kb |
| Host | smart-643c5925-26ac-4cd5-988a-de84fc3048e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438569412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r eset.1438569412 |
| Directory | /workspace/1.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/47.rv_timer_stress_all.2142829378 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 1051799045360 ps |
| CPU time | 939.18 seconds |
| Started | Mar 03 04:12:40 PM PST 24 |
| Finished | Mar 03 04:28:20 PM PST 24 |
| Peak memory | 191304 kb |
| Host | smart-8e179ac2-4799-43a2-a4e6-3bb0722441e4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142829378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all .2142829378 |
| Directory | /workspace/47.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/16.rv_timer_stress_all.2946598626 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1840152074183 ps |
| CPU time | 1994.61 seconds |
| Started | Mar 03 04:08:43 PM PST 24 |
| Finished | Mar 03 04:41:58 PM PST 24 |
| Peak memory | 191396 kb |
| Host | smart-773efec6-aca1-40b0-849e-eacca96d78f5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946598626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all .2946598626 |
| Directory | /workspace/16.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/26.rv_timer_stress_all.1475385628 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 2255304161702 ps |
| CPU time | 1191.03 seconds |
| Started | Mar 03 04:10:08 PM PST 24 |
| Finished | Mar 03 04:29:59 PM PST 24 |
| Peak memory | 191400 kb |
| Host | smart-6eb4d712-f283-44ea-b703-37627d7bd3ce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475385628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all .1475385628 |
| Directory | /workspace/26.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/197.rv_timer_random.2209352642 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1253092152389 ps |
| CPU time | 338.39 seconds |
| Started | Mar 03 04:15:03 PM PST 24 |
| Finished | Mar 03 04:20:42 PM PST 24 |
| Peak memory | 191288 kb |
| Host | smart-bd5af7b6-43e1-477f-8c94-9372fc702b44 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209352642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2209352642 |
| Directory | /workspace/197.rv_timer_random/latest |
| Test location | /workspace/coverage/default/0.rv_timer_sec_cm.3155195140 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 259512568 ps |
| CPU time | 1.17 seconds |
| Started | Mar 03 04:07:27 PM PST 24 |
| Finished | Mar 03 04:07:28 PM PST 24 |
| Peak memory | 214372 kb |
| Host | smart-8333eb52-151c-4380-89b7-49e525f650ad |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155195140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.3155195140 |
| Directory | /workspace/0.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/45.rv_timer_stress_all.174756565 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1377275057361 ps |
| CPU time | 1583.85 seconds |
| Started | Mar 03 04:12:27 PM PST 24 |
| Finished | Mar 03 04:38:51 PM PST 24 |
| Peak memory | 191464 kb |
| Host | smart-e6772d8c-657f-463d-a753-a85b9a6e291a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174756565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all. 174756565 |
| Directory | /workspace/45.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/20.rv_timer_stress_all.2445178106 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 1035024407281 ps |
| CPU time | 842.31 seconds |
| Started | Mar 03 04:09:19 PM PST 24 |
| Finished | Mar 03 04:23:22 PM PST 24 |
| Peak memory | 195176 kb |
| Host | smart-92832740-4be8-446a-a316-585b51bc5939 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445178106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all .2445178106 |
| Directory | /workspace/20.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/28.rv_timer_stress_all.679563562 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 594855205674 ps |
| CPU time | 1583.09 seconds |
| Started | Mar 03 04:10:22 PM PST 24 |
| Finished | Mar 03 04:36:46 PM PST 24 |
| Peak memory | 191380 kb |
| Host | smart-91dbf424-c92d-465f-b43e-53e473a01ea0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679563562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all. 679563562 |
| Directory | /workspace/28.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/13.rv_timer_stress_all.2369555856 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 1466246994753 ps |
| CPU time | 2375.2 seconds |
| Started | Mar 03 04:08:22 PM PST 24 |
| Finished | Mar 03 04:47:58 PM PST 24 |
| Peak memory | 191420 kb |
| Host | smart-c85b0243-1d89-4dfc-8879-ba2d47a72642 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369555856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all .2369555856 |
| Directory | /workspace/13.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/21.rv_timer_stress_all.1387828596 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 575447317100 ps |
| CPU time | 1168.25 seconds |
| Started | Mar 03 04:09:26 PM PST 24 |
| Finished | Mar 03 04:28:55 PM PST 24 |
| Peak memory | 196044 kb |
| Host | smart-92412212-cb48-411d-beaa-d8d8c4b2c404 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387828596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all .1387828596 |
| Directory | /workspace/21.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/138.rv_timer_random.1018544314 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 160135873216 ps |
| CPU time | 266.73 seconds |
| Started | Mar 03 04:14:17 PM PST 24 |
| Finished | Mar 03 04:18:45 PM PST 24 |
| Peak memory | 191360 kb |
| Host | smart-da7c12ce-2f30-48f5-b291-7f24f2d2b66e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018544314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1018544314 |
| Directory | /workspace/138.rv_timer_random/latest |
| Test location | /workspace/coverage/default/169.rv_timer_random.1701848940 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 578034661740 ps |
| CPU time | 205.03 seconds |
| Started | Mar 03 04:14:35 PM PST 24 |
| Finished | Mar 03 04:18:01 PM PST 24 |
| Peak memory | 191372 kb |
| Host | smart-2d8c70b0-bf3f-4a3c-9718-24889d9e17a2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701848940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1701848940 |
| Directory | /workspace/169.rv_timer_random/latest |
| Test location | /workspace/coverage/default/144.rv_timer_random.620695892 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 690739767508 ps |
| CPU time | 511.34 seconds |
| Started | Mar 03 04:14:16 PM PST 24 |
| Finished | Mar 03 04:22:48 PM PST 24 |
| Peak memory | 193820 kb |
| Host | smart-62703040-5ebf-4190-b37b-fc021224b785 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620695892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.620695892 |
| Directory | /workspace/144.rv_timer_random/latest |
| Test location | /workspace/coverage/default/153.rv_timer_random.3407245321 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 885485526896 ps |
| CPU time | 376.79 seconds |
| Started | Mar 03 04:14:24 PM PST 24 |
| Finished | Mar 03 04:20:42 PM PST 24 |
| Peak memory | 194920 kb |
| Host | smart-2df3b599-9ba0-4fc9-a5c1-26211364c3ea |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407245321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3407245321 |
| Directory | /workspace/153.rv_timer_random/latest |
| Test location | /workspace/coverage/default/16.rv_timer_random.3903785280 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 90476012227 ps |
| CPU time | 185.58 seconds |
| Started | Mar 03 04:08:38 PM PST 24 |
| Finished | Mar 03 04:11:45 PM PST 24 |
| Peak memory | 191392 kb |
| Host | smart-a0de126d-ac72-44b8-a17a-b814be54e513 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903785280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3903785280 |
| Directory | /workspace/16.rv_timer_random/latest |
| Test location | /workspace/coverage/default/17.rv_timer_stress_all.2364629688 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 625956903638 ps |
| CPU time | 2458.3 seconds |
| Started | Mar 03 04:08:50 PM PST 24 |
| Finished | Mar 03 04:49:49 PM PST 24 |
| Peak memory | 191380 kb |
| Host | smart-01894292-9b89-4cbd-9b2d-ab8f63f5a73b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364629688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all .2364629688 |
| Directory | /workspace/17.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/49.rv_timer_stress_all.493404395 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1430343612274 ps |
| CPU time | 649.94 seconds |
| Started | Mar 03 04:12:45 PM PST 24 |
| Finished | Mar 03 04:23:35 PM PST 24 |
| Peak memory | 195952 kb |
| Host | smart-896df279-51e7-412c-af8f-2f10a7a8b5fb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493404395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all. 493404395 |
| Directory | /workspace/49.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/167.rv_timer_random.456538158 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 243939983222 ps |
| CPU time | 703.3 seconds |
| Started | Mar 03 04:14:36 PM PST 24 |
| Finished | Mar 03 04:26:20 PM PST 24 |
| Peak memory | 191412 kb |
| Host | smart-9380e1e5-788c-4387-8aff-697716f0c608 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456538158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.456538158 |
| Directory | /workspace/167.rv_timer_random/latest |
| Test location | /workspace/coverage/default/31.rv_timer_stress_all.43219478 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 367684662174 ps |
| CPU time | 361.76 seconds |
| Started | Mar 03 04:10:44 PM PST 24 |
| Finished | Mar 03 04:16:46 PM PST 24 |
| Peak memory | 195992 kb |
| Host | smart-cfdcfd4c-7022-4ace-8c54-5ac6df15e9cd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43219478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_ all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.43219478 |
| Directory | /workspace/31.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/55.rv_timer_random.4287633014 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 215617366549 ps |
| CPU time | 351.69 seconds |
| Started | Mar 03 04:12:52 PM PST 24 |
| Finished | Mar 03 04:18:44 PM PST 24 |
| Peak memory | 193540 kb |
| Host | smart-332333ec-6f84-4d77-b66e-dc390f04e2b1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287633014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.4287633014 |
| Directory | /workspace/55.rv_timer_random/latest |
| Test location | /workspace/coverage/default/24.rv_timer_stress_all.529874590 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1938586015525 ps |
| CPU time | 987.54 seconds |
| Started | Mar 03 04:09:50 PM PST 24 |
| Finished | Mar 03 04:26:18 PM PST 24 |
| Peak memory | 196328 kb |
| Host | smart-7be38543-8ac4-4801-95e9-869137a0396b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529874590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all. 529874590 |
| Directory | /workspace/24.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/38.rv_timer_random.3746359517 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 696779528852 ps |
| CPU time | 1076.88 seconds |
| Started | Mar 03 04:11:29 PM PST 24 |
| Finished | Mar 03 04:29:26 PM PST 24 |
| Peak memory | 191392 kb |
| Host | smart-ace46226-3bc0-4c8c-84c5-993b8746b027 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746359517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3746359517 |
| Directory | /workspace/38.rv_timer_random/latest |
| Test location | /workspace/coverage/default/94.rv_timer_random.637131275 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 635036627841 ps |
| CPU time | 369.34 seconds |
| Started | Mar 03 04:13:35 PM PST 24 |
| Finished | Mar 03 04:19:45 PM PST 24 |
| Peak memory | 191376 kb |
| Host | smart-82e6338b-fe4b-4eaa-9d53-598fabd363aa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637131275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.637131275 |
| Directory | /workspace/94.rv_timer_random/latest |
| Test location | /workspace/coverage/default/1.rv_timer_stress_all.2526922428 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 2256596600941 ps |
| CPU time | 1349.16 seconds |
| Started | Mar 03 04:07:43 PM PST 24 |
| Finished | Mar 03 04:30:12 PM PST 24 |
| Peak memory | 195940 kb |
| Host | smart-381730d5-0720-4a1b-8968-363511ab9cc1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526922428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all. 2526922428 |
| Directory | /workspace/1.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/100.rv_timer_random.541312391 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 180474277637 ps |
| CPU time | 787.89 seconds |
| Started | Mar 03 04:13:39 PM PST 24 |
| Finished | Mar 03 04:26:47 PM PST 24 |
| Peak memory | 191396 kb |
| Host | smart-310a2686-6999-481d-aadd-81a93394b8c6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541312391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.541312391 |
| Directory | /workspace/100.rv_timer_random/latest |
| Test location | /workspace/coverage/default/136.rv_timer_random.684387156 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 217818195821 ps |
| CPU time | 331.25 seconds |
| Started | Mar 03 04:14:11 PM PST 24 |
| Finished | Mar 03 04:19:42 PM PST 24 |
| Peak memory | 191396 kb |
| Host | smart-bcb655cd-b3fd-4d06-a905-bd7d5a23a2a3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684387156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.684387156 |
| Directory | /workspace/136.rv_timer_random/latest |
| Test location | /workspace/coverage/default/155.rv_timer_random.146051641 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 342703084579 ps |
| CPU time | 365.17 seconds |
| Started | Mar 03 04:14:24 PM PST 24 |
| Finished | Mar 03 04:20:30 PM PST 24 |
| Peak memory | 194732 kb |
| Host | smart-f7850400-9b2c-4413-a772-b9b5b44eb61f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146051641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.146051641 |
| Directory | /workspace/155.rv_timer_random/latest |
| Test location | /workspace/coverage/default/199.rv_timer_random.2341775004 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 155997265358 ps |
| CPU time | 299.53 seconds |
| Started | Mar 03 04:15:08 PM PST 24 |
| Finished | Mar 03 04:20:08 PM PST 24 |
| Peak memory | 191356 kb |
| Host | smart-e4d72978-3189-46ec-b37e-d1571a0fa6bf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341775004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2341775004 |
| Directory | /workspace/199.rv_timer_random/latest |
| Test location | /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2786927442 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 239506376244 ps |
| CPU time | 228.9 seconds |
| Started | Mar 03 04:09:21 PM PST 24 |
| Finished | Mar 03 04:13:10 PM PST 24 |
| Peak memory | 183128 kb |
| Host | smart-2c96fc7e-41b9-4a77-93bc-d5d0c1f3726f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786927442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_cfg_update_on_fly.2786927442 |
| Directory | /workspace/21.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/44.rv_timer_stress_all.653958755 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 874404296242 ps |
| CPU time | 540.58 seconds |
| Started | Mar 03 04:12:17 PM PST 24 |
| Finished | Mar 03 04:21:18 PM PST 24 |
| Peak memory | 191380 kb |
| Host | smart-7d08f508-d2c3-4d86-8c19-0cb4438df3e2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653958755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all. 653958755 |
| Directory | /workspace/44.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1091216516 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 453533858817 ps |
| CPU time | 863.94 seconds |
| Started | Mar 03 04:07:47 PM PST 24 |
| Finished | Mar 03 04:22:11 PM PST 24 |
| Peak memory | 183168 kb |
| Host | smart-3fc50bf8-9386-4662-a090-eb980867706b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091216516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_cfg_update_on_fly.1091216516 |
| Directory | /workspace/5.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/78.rv_timer_random.2897137106 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 583313801270 ps |
| CPU time | 2299.5 seconds |
| Started | Mar 03 04:13:15 PM PST 24 |
| Finished | Mar 03 04:51:35 PM PST 24 |
| Peak memory | 194944 kb |
| Host | smart-ef9d16e2-85c6-4b2c-b338-3508b26e97c5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897137106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2897137106 |
| Directory | /workspace/78.rv_timer_random/latest |
| Test location | /workspace/coverage/default/187.rv_timer_random.893257227 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 201641770532 ps |
| CPU time | 192.79 seconds |
| Started | Mar 03 04:14:57 PM PST 24 |
| Finished | Mar 03 04:18:10 PM PST 24 |
| Peak memory | 191368 kb |
| Host | smart-1c8f7798-e67e-4c7d-aea8-3dab15ea560f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893257227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.893257227 |
| Directory | /workspace/187.rv_timer_random/latest |
| Test location | /workspace/coverage/default/52.rv_timer_random.2891502761 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 443747767028 ps |
| CPU time | 378.6 seconds |
| Started | Mar 03 04:12:53 PM PST 24 |
| Finished | Mar 03 04:19:12 PM PST 24 |
| Peak memory | 191360 kb |
| Host | smart-cee5fd21-34f6-4c8a-90be-3528d9aa483d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891502761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2891502761 |
| Directory | /workspace/52.rv_timer_random/latest |
| Test location | /workspace/coverage/default/70.rv_timer_random.3264288146 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 87681444347 ps |
| CPU time | 186.62 seconds |
| Started | Mar 03 04:13:12 PM PST 24 |
| Finished | Mar 03 04:16:19 PM PST 24 |
| Peak memory | 191360 kb |
| Host | smart-30b9f509-f415-43eb-b361-79fdc26205c4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264288146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3264288146 |
| Directory | /workspace/70.rv_timer_random/latest |
| Test location | /workspace/coverage/default/0.rv_timer_random.1227666319 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 536231867900 ps |
| CPU time | 211.33 seconds |
| Started | Mar 03 04:07:16 PM PST 24 |
| Finished | Mar 03 04:10:48 PM PST 24 |
| Peak memory | 191388 kb |
| Host | smart-e4d9a055-6c1e-417a-89b7-b15dd285f280 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227666319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1227666319 |
| Directory | /workspace/0.rv_timer_random/latest |
| Test location | /workspace/coverage/default/117.rv_timer_random.1155755565 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 520845226172 ps |
| CPU time | 988.16 seconds |
| Started | Mar 03 04:13:51 PM PST 24 |
| Finished | Mar 03 04:30:20 PM PST 24 |
| Peak memory | 191592 kb |
| Host | smart-46dda9b0-1b8b-4885-b982-e02cb76bae3f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155755565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1155755565 |
| Directory | /workspace/117.rv_timer_random/latest |
| Test location | /workspace/coverage/default/121.rv_timer_random.1520809329 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 75375564406 ps |
| CPU time | 146.76 seconds |
| Started | Mar 03 04:13:51 PM PST 24 |
| Finished | Mar 03 04:16:18 PM PST 24 |
| Peak memory | 191396 kb |
| Host | smart-5c3e3adf-3f53-45c5-b459-2890d68cf7fc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520809329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1520809329 |
| Directory | /workspace/121.rv_timer_random/latest |
| Test location | /workspace/coverage/default/13.rv_timer_random_reset.3421943201 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 20787268406 ps |
| CPU time | 83.7 seconds |
| Started | Mar 03 04:08:19 PM PST 24 |
| Finished | Mar 03 04:09:43 PM PST 24 |
| Peak memory | 191396 kb |
| Host | smart-a83a8180-edd3-4246-ba58-f0029a7c9c06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3421943201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3421943201 |
| Directory | /workspace/13.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.1542012578 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 480509312160 ps |
| CPU time | 762.03 seconds |
| Started | Mar 03 04:08:25 PM PST 24 |
| Finished | Mar 03 04:21:08 PM PST 24 |
| Peak memory | 183152 kb |
| Host | smart-043f83a6-13c4-4574-b0c1-00e14a3ae972 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542012578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.1542012578 |
| Directory | /workspace/14.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/152.rv_timer_random.3966342736 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 91482231753 ps |
| CPU time | 180.8 seconds |
| Started | Mar 03 04:14:31 PM PST 24 |
| Finished | Mar 03 04:17:32 PM PST 24 |
| Peak memory | 194636 kb |
| Host | smart-e360a622-f916-4d84-8d3a-0d9c920e27a5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966342736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3966342736 |
| Directory | /workspace/152.rv_timer_random/latest |
| Test location | /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2019047472 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 161550457660 ps |
| CPU time | 85.99 seconds |
| Started | Mar 03 04:08:36 PM PST 24 |
| Finished | Mar 03 04:10:02 PM PST 24 |
| Peak memory | 183212 kb |
| Host | smart-8efab395-1c9c-4811-b182-ea8fe50b0c9a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019047472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.2019047472 |
| Directory | /workspace/16.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/166.rv_timer_random.2483785479 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 134246692442 ps |
| CPU time | 809.48 seconds |
| Started | Mar 03 04:14:35 PM PST 24 |
| Finished | Mar 03 04:28:05 PM PST 24 |
| Peak memory | 191332 kb |
| Host | smart-7a9fa0c1-3923-4784-a742-f236e40cd6cc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483785479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2483785479 |
| Directory | /workspace/166.rv_timer_random/latest |
| Test location | /workspace/coverage/default/182.rv_timer_random.864600021 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 155955162095 ps |
| CPU time | 859.68 seconds |
| Started | Mar 03 04:14:51 PM PST 24 |
| Finished | Mar 03 04:29:11 PM PST 24 |
| Peak memory | 191572 kb |
| Host | smart-7acf3303-af05-4ccb-9ae3-441dab54a24d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864600021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.864600021 |
| Directory | /workspace/182.rv_timer_random/latest |
| Test location | /workspace/coverage/default/190.rv_timer_random.1673734254 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 167849895723 ps |
| CPU time | 585.27 seconds |
| Started | Mar 03 04:14:59 PM PST 24 |
| Finished | Mar 03 04:24:45 PM PST 24 |
| Peak memory | 191448 kb |
| Host | smart-d2fe9daa-3125-48e9-9f46-66603a580c2f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673734254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1673734254 |
| Directory | /workspace/190.rv_timer_random/latest |
| Test location | /workspace/coverage/default/31.rv_timer_random.1227851332 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 103894399673 ps |
| CPU time | 176.26 seconds |
| Started | Mar 03 04:10:41 PM PST 24 |
| Finished | Mar 03 04:13:37 PM PST 24 |
| Peak memory | 194512 kb |
| Host | smart-57b2c78a-1545-441e-933b-99f5dfd99325 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227851332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1227851332 |
| Directory | /workspace/31.rv_timer_random/latest |
| Test location | /workspace/coverage/default/46.rv_timer_random.1512262063 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 86728556583 ps |
| CPU time | 190.51 seconds |
| Started | Mar 03 04:12:22 PM PST 24 |
| Finished | Mar 03 04:15:33 PM PST 24 |
| Peak memory | 191388 kb |
| Host | smart-d6e0471b-a19f-437d-a1fa-24bd262290f1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512262063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1512262063 |
| Directory | /workspace/46.rv_timer_random/latest |
| Test location | /workspace/coverage/default/69.rv_timer_random.2257771021 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 380361092746 ps |
| CPU time | 387.84 seconds |
| Started | Mar 03 04:13:09 PM PST 24 |
| Finished | Mar 03 04:19:37 PM PST 24 |
| Peak memory | 191380 kb |
| Host | smart-83ad3a03-08ac-478b-b45e-169f579699d4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257771021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2257771021 |
| Directory | /workspace/69.rv_timer_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1261494173 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 12248666 ps |
| CPU time | 0.58 seconds |
| Started | Mar 03 12:33:11 PM PST 24 |
| Finished | Mar 03 12:33:12 PM PST 24 |
| Peak memory | 182712 kb |
| Host | smart-dc966621-137b-4750-ba53-50565f7db69b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261494173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1261494173 |
| Directory | /workspace/0.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/default/103.rv_timer_random.949283575 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 389213000544 ps |
| CPU time | 94.48 seconds |
| Started | Mar 03 04:13:40 PM PST 24 |
| Finished | Mar 03 04:15:15 PM PST 24 |
| Peak memory | 191376 kb |
| Host | smart-d72517eb-1c7d-4db6-a5d2-1dc93e8bc565 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949283575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.949283575 |
| Directory | /workspace/103.rv_timer_random/latest |
| Test location | /workspace/coverage/default/106.rv_timer_random.2636905570 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 440484216128 ps |
| CPU time | 203.7 seconds |
| Started | Mar 03 04:13:41 PM PST 24 |
| Finished | Mar 03 04:17:04 PM PST 24 |
| Peak memory | 194732 kb |
| Host | smart-8508be48-aa74-4647-969f-2eca62bcef61 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636905570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2636905570 |
| Directory | /workspace/106.rv_timer_random/latest |
| Test location | /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.1901388402 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 170897210207 ps |
| CPU time | 307.53 seconds |
| Started | Mar 03 04:08:03 PM PST 24 |
| Finished | Mar 03 04:13:11 PM PST 24 |
| Peak memory | 183200 kb |
| Host | smart-0c00b238-6670-4d3c-87ac-2e67135c26bb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901388402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.1901388402 |
| Directory | /workspace/11.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/110.rv_timer_random.1820406345 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 338401716018 ps |
| CPU time | 645.55 seconds |
| Started | Mar 03 04:13:45 PM PST 24 |
| Finished | Mar 03 04:24:31 PM PST 24 |
| Peak memory | 191312 kb |
| Host | smart-e270b31b-3bfc-4481-977f-7cbec97cb70c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820406345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1820406345 |
| Directory | /workspace/110.rv_timer_random/latest |
| Test location | /workspace/coverage/default/119.rv_timer_random.2369936227 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 416368398270 ps |
| CPU time | 652.79 seconds |
| Started | Mar 03 04:13:51 PM PST 24 |
| Finished | Mar 03 04:24:44 PM PST 24 |
| Peak memory | 191388 kb |
| Host | smart-352bc500-9364-40f4-8844-f1aed71c2edb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369936227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2369936227 |
| Directory | /workspace/119.rv_timer_random/latest |
| Test location | /workspace/coverage/default/133.rv_timer_random.1481493242 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1074728768863 ps |
| CPU time | 292.56 seconds |
| Started | Mar 03 04:14:10 PM PST 24 |
| Finished | Mar 03 04:19:03 PM PST 24 |
| Peak memory | 194256 kb |
| Host | smart-7d5a9556-43ec-4764-a848-41a3447dacad |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481493242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1481493242 |
| Directory | /workspace/133.rv_timer_random/latest |
| Test location | /workspace/coverage/default/160.rv_timer_random.749637038 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 200345076735 ps |
| CPU time | 253.04 seconds |
| Started | Mar 03 04:14:24 PM PST 24 |
| Finished | Mar 03 04:18:39 PM PST 24 |
| Peak memory | 191348 kb |
| Host | smart-0b9515fb-9350-4256-9984-1b21612b57e5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749637038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.749637038 |
| Directory | /workspace/160.rv_timer_random/latest |
| Test location | /workspace/coverage/default/162.rv_timer_random.22170968 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 158863901594 ps |
| CPU time | 1489.5 seconds |
| Started | Mar 03 04:14:29 PM PST 24 |
| Finished | Mar 03 04:39:19 PM PST 24 |
| Peak memory | 193724 kb |
| Host | smart-44de8e4a-241a-4712-9f8d-00138772f9b6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22170968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.22170968 |
| Directory | /workspace/162.rv_timer_random/latest |
| Test location | /workspace/coverage/default/164.rv_timer_random.1676663345 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 165192729026 ps |
| CPU time | 167.17 seconds |
| Started | Mar 03 04:14:28 PM PST 24 |
| Finished | Mar 03 04:17:16 PM PST 24 |
| Peak memory | 194828 kb |
| Host | smart-6ca305d6-90ec-4484-9f62-39d059312a3d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676663345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1676663345 |
| Directory | /workspace/164.rv_timer_random/latest |
| Test location | /workspace/coverage/default/17.rv_timer_random.684062443 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 365189918677 ps |
| CPU time | 750.77 seconds |
| Started | Mar 03 04:08:43 PM PST 24 |
| Finished | Mar 03 04:21:14 PM PST 24 |
| Peak memory | 191392 kb |
| Host | smart-8b4ebf38-13fe-4679-955d-335fde7fc3dd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684062443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.684062443 |
| Directory | /workspace/17.rv_timer_random/latest |
| Test location | /workspace/coverage/default/18.rv_timer_random_reset.4039329881 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 245864842948 ps |
| CPU time | 643.48 seconds |
| Started | Mar 03 04:08:54 PM PST 24 |
| Finished | Mar 03 04:19:38 PM PST 24 |
| Peak memory | 191384 kb |
| Host | smart-91ab0bf3-bc09-4682-9c2d-160b2ecaf223 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4039329881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.4039329881 |
| Directory | /workspace/18.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/2.rv_timer_random.4207939107 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 2188964351708 ps |
| CPU time | 1467.33 seconds |
| Started | Mar 03 04:07:41 PM PST 24 |
| Finished | Mar 03 04:32:09 PM PST 24 |
| Peak memory | 191364 kb |
| Host | smart-b5f5f3b5-7def-4662-a954-af2f3ba9d141 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207939107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.4207939107 |
| Directory | /workspace/2.rv_timer_random/latest |
| Test location | /workspace/coverage/default/33.rv_timer_random.1639445226 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 533610861669 ps |
| CPU time | 282.09 seconds |
| Started | Mar 03 04:10:51 PM PST 24 |
| Finished | Mar 03 04:15:33 PM PST 24 |
| Peak memory | 191392 kb |
| Host | smart-1dd41b08-2f87-49f7-aa12-9d02be105fbd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639445226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1639445226 |
| Directory | /workspace/33.rv_timer_random/latest |
| Test location | /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1360621199 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 371660152454 ps |
| CPU time | 640.66 seconds |
| Started | Mar 03 04:11:04 PM PST 24 |
| Finished | Mar 03 04:21:45 PM PST 24 |
| Peak memory | 183208 kb |
| Host | smart-5079cf0a-14d2-4a5f-81ea-200c96e94ce2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360621199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.1360621199 |
| Directory | /workspace/34.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/37.rv_timer_stress_all.2246022521 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 796694534088 ps |
| CPU time | 383.38 seconds |
| Started | Mar 03 04:11:28 PM PST 24 |
| Finished | Mar 03 04:17:52 PM PST 24 |
| Peak memory | 191384 kb |
| Host | smart-0748c343-b0b2-4c82-a47c-08fb063f87f9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246022521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all .2246022521 |
| Directory | /workspace/37.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/49.rv_timer_random.2644009420 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 120817668183 ps |
| CPU time | 358.9 seconds |
| Started | Mar 03 04:12:40 PM PST 24 |
| Finished | Mar 03 04:18:40 PM PST 24 |
| Peak memory | 191380 kb |
| Host | smart-b3bb0322-5dfd-4462-acdb-d960022849dc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644009420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2644009420 |
| Directory | /workspace/49.rv_timer_random/latest |
| Test location | /workspace/coverage/default/79.rv_timer_random.3996471842 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 216421161840 ps |
| CPU time | 943.11 seconds |
| Started | Mar 03 04:13:16 PM PST 24 |
| Finished | Mar 03 04:28:59 PM PST 24 |
| Peak memory | 191392 kb |
| Host | smart-31c71ddd-6608-4378-8c75-86bd3f70600d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996471842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3996471842 |
| Directory | /workspace/79.rv_timer_random/latest |
| Test location | /workspace/coverage/default/85.rv_timer_random.2790368137 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 172611795504 ps |
| CPU time | 412.14 seconds |
| Started | Mar 03 04:13:22 PM PST 24 |
| Finished | Mar 03 04:20:15 PM PST 24 |
| Peak memory | 191400 kb |
| Host | smart-c606b18b-ed54-4945-93f0-9d4121a3b61f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790368137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2790368137 |
| Directory | /workspace/85.rv_timer_random/latest |
| Test location | /workspace/coverage/default/92.rv_timer_random.2511939086 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 70457973613 ps |
| CPU time | 126.25 seconds |
| Started | Mar 03 04:13:36 PM PST 24 |
| Finished | Mar 03 04:15:42 PM PST 24 |
| Peak memory | 193528 kb |
| Host | smart-e2e8ef7d-b63a-4a42-af3e-5175ceb55c79 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511939086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2511939086 |
| Directory | /workspace/92.rv_timer_random/latest |
| Test location | /workspace/coverage/default/105.rv_timer_random.851760304 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 117810110112 ps |
| CPU time | 206.46 seconds |
| Started | Mar 03 04:13:40 PM PST 24 |
| Finished | Mar 03 04:17:07 PM PST 24 |
| Peak memory | 191420 kb |
| Host | smart-766372d9-b80d-462d-8c40-d3d538186d1c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851760304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.851760304 |
| Directory | /workspace/105.rv_timer_random/latest |
| Test location | /workspace/coverage/default/124.rv_timer_random.1657507697 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 89398697904 ps |
| CPU time | 145.27 seconds |
| Started | Mar 03 04:13:57 PM PST 24 |
| Finished | Mar 03 04:16:23 PM PST 24 |
| Peak memory | 193608 kb |
| Host | smart-fe753b57-00e8-4c11-a319-77c7e9c60ae4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657507697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1657507697 |
| Directory | /workspace/124.rv_timer_random/latest |
| Test location | /workspace/coverage/default/127.rv_timer_random.2010132994 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 113070667599 ps |
| CPU time | 227.12 seconds |
| Started | Mar 03 04:13:58 PM PST 24 |
| Finished | Mar 03 04:17:45 PM PST 24 |
| Peak memory | 191384 kb |
| Host | smart-b96122ac-0923-434f-a495-d2f22ce16a48 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010132994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2010132994 |
| Directory | /workspace/127.rv_timer_random/latest |
| Test location | /workspace/coverage/default/135.rv_timer_random.1012618118 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 35677087733 ps |
| CPU time | 64.19 seconds |
| Started | Mar 03 04:14:11 PM PST 24 |
| Finished | Mar 03 04:15:15 PM PST 24 |
| Peak memory | 183192 kb |
| Host | smart-83c66bc0-dbf7-4d8b-ba47-34b23b1c9784 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012618118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1012618118 |
| Directory | /workspace/135.rv_timer_random/latest |
| Test location | /workspace/coverage/default/14.rv_timer_random.2166637928 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 47566242727 ps |
| CPU time | 51.06 seconds |
| Started | Mar 03 04:08:24 PM PST 24 |
| Finished | Mar 03 04:09:15 PM PST 24 |
| Peak memory | 183172 kb |
| Host | smart-579a18ec-7ba5-4cf5-969c-f3fbfcb43854 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166637928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2166637928 |
| Directory | /workspace/14.rv_timer_random/latest |
| Test location | /workspace/coverage/default/14.rv_timer_random_reset.3743882405 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 81805355848 ps |
| CPU time | 41.42 seconds |
| Started | Mar 03 04:08:23 PM PST 24 |
| Finished | Mar 03 04:09:05 PM PST 24 |
| Peak memory | 191376 kb |
| Host | smart-43e40abd-db7a-4a51-a6f7-9a88b92bdb62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3743882405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3743882405 |
| Directory | /workspace/14.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/157.rv_timer_random.4190082754 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 383322534401 ps |
| CPU time | 301.38 seconds |
| Started | Mar 03 04:14:24 PM PST 24 |
| Finished | Mar 03 04:19:27 PM PST 24 |
| Peak memory | 194808 kb |
| Host | smart-1c6bbcf5-dbc1-4bf3-9099-ae554c28cd00 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190082754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.4190082754 |
| Directory | /workspace/157.rv_timer_random/latest |
| Test location | /workspace/coverage/default/184.rv_timer_random.677110649 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 96772728145 ps |
| CPU time | 83.63 seconds |
| Started | Mar 03 04:14:54 PM PST 24 |
| Finished | Mar 03 04:16:18 PM PST 24 |
| Peak memory | 183188 kb |
| Host | smart-7fc2e0d7-84df-4f4f-9fbc-46b81d8e7720 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677110649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.677110649 |
| Directory | /workspace/184.rv_timer_random/latest |
| Test location | /workspace/coverage/default/19.rv_timer_random_reset.4144712910 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 54425164463 ps |
| CPU time | 98.39 seconds |
| Started | Mar 03 04:09:05 PM PST 24 |
| Finished | Mar 03 04:10:45 PM PST 24 |
| Peak memory | 183180 kb |
| Host | smart-2040395b-be09-40b4-8701-3806ea22d2ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4144712910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.4144712910 |
| Directory | /workspace/19.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/194.rv_timer_random.4039202835 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 84084630781 ps |
| CPU time | 321.58 seconds |
| Started | Mar 03 04:15:07 PM PST 24 |
| Finished | Mar 03 04:20:29 PM PST 24 |
| Peak memory | 191392 kb |
| Host | smart-c4e28878-bf51-4d55-85fc-e917f8e126a1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039202835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.4039202835 |
| Directory | /workspace/194.rv_timer_random/latest |
| Test location | /workspace/coverage/default/21.rv_timer_random.9934138 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 83826818631 ps |
| CPU time | 150.8 seconds |
| Started | Mar 03 04:09:22 PM PST 24 |
| Finished | Mar 03 04:11:53 PM PST 24 |
| Peak memory | 194704 kb |
| Host | smart-efed0dfe-b610-4ee9-9bad-c06fd72a4655 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9934138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.9934138 |
| Directory | /workspace/21.rv_timer_random/latest |
| Test location | /workspace/coverage/default/28.rv_timer_random.3835816383 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 355310356105 ps |
| CPU time | 1163.12 seconds |
| Started | Mar 03 04:10:14 PM PST 24 |
| Finished | Mar 03 04:29:39 PM PST 24 |
| Peak memory | 191300 kb |
| Host | smart-fb8cb596-a1f9-48af-94c9-cfc554b7fd0a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835816383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3835816383 |
| Directory | /workspace/28.rv_timer_random/latest |
| Test location | /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.1246529241 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 1009129388656 ps |
| CPU time | 604.72 seconds |
| Started | Mar 03 04:10:34 PM PST 24 |
| Finished | Mar 03 04:20:39 PM PST 24 |
| Peak memory | 183196 kb |
| Host | smart-0b980998-6983-4f1e-bc4f-6fbacb5979d9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246529241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.1246529241 |
| Directory | /workspace/30.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/38.rv_timer_stress_all.4177655125 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 265816182898 ps |
| CPU time | 499.81 seconds |
| Started | Mar 03 04:11:37 PM PST 24 |
| Finished | Mar 03 04:19:57 PM PST 24 |
| Peak memory | 195120 kb |
| Host | smart-a7a9fb1e-fe05-43cd-84f2-e41bf54e13b6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177655125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all .4177655125 |
| Directory | /workspace/38.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1410129044 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 419077783798 ps |
| CPU time | 401.67 seconds |
| Started | Mar 03 04:12:40 PM PST 24 |
| Finished | Mar 03 04:19:22 PM PST 24 |
| Peak memory | 183208 kb |
| Host | smart-f0edec47-94bd-46b9-90be-6233be82cc10 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410129044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_cfg_update_on_fly.1410129044 |
| Directory | /workspace/48.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/68.rv_timer_random.2317876594 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 98621113768 ps |
| CPU time | 200.89 seconds |
| Started | Mar 03 04:13:10 PM PST 24 |
| Finished | Mar 03 04:16:31 PM PST 24 |
| Peak memory | 191368 kb |
| Host | smart-52daec81-83ba-4283-91e6-b5c8cd8b3460 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317876594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2317876594 |
| Directory | /workspace/68.rv_timer_random/latest |
| Test location | /workspace/coverage/default/88.rv_timer_random.3484036022 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 534201785089 ps |
| CPU time | 630.42 seconds |
| Started | Mar 03 04:13:22 PM PST 24 |
| Finished | Mar 03 04:23:53 PM PST 24 |
| Peak memory | 191396 kb |
| Host | smart-310d5b6e-073f-44cf-99f8-4e54a5dbfb32 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484036022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3484036022 |
| Directory | /workspace/88.rv_timer_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.568044269 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 13542457 ps |
| CPU time | 0.63 seconds |
| Started | Mar 03 12:33:37 PM PST 24 |
| Finished | Mar 03 12:33:38 PM PST 24 |
| Peak memory | 182548 kb |
| Host | smart-1127823d-dba7-4c43-b814-2181efd51ffc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568044269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alias ing.568044269 |
| Directory | /workspace/0.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.218868752 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 1108604912 ps |
| CPU time | 2.62 seconds |
| Started | Mar 03 12:33:17 PM PST 24 |
| Finished | Mar 03 12:33:22 PM PST 24 |
| Peak memory | 191988 kb |
| Host | smart-8fe12e9b-0d76-4154-9a2a-d3ef794377e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218868752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b ash.218868752 |
| Directory | /workspace/0.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1904895826 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 32950277 ps |
| CPU time | 0.57 seconds |
| Started | Mar 03 12:33:33 PM PST 24 |
| Finished | Mar 03 12:33:34 PM PST 24 |
| Peak memory | 182720 kb |
| Host | smart-d9a26cd5-e39b-4bf5-bc91-dee41e917179 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904895826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r eset.1904895826 |
| Directory | /workspace/0.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.872476281 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 306482614 ps |
| CPU time | 1.44 seconds |
| Started | Mar 03 12:33:32 PM PST 24 |
| Finished | Mar 03 12:33:38 PM PST 24 |
| Peak memory | 197612 kb |
| Host | smart-273bafe0-8da4-4fb2-ac68-53152eaea603 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872476281 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.872476281 |
| Directory | /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2087233381 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 42446538 ps |
| CPU time | 0.53 seconds |
| Started | Mar 03 12:33:17 PM PST 24 |
| Finished | Mar 03 12:33:18 PM PST 24 |
| Peak memory | 182424 kb |
| Host | smart-1979b864-39ef-4285-9fd5-78ab07719160 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087233381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2087233381 |
| Directory | /workspace/0.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.58154268 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 24198322 ps |
| CPU time | 0.73 seconds |
| Started | Mar 03 12:33:12 PM PST 24 |
| Finished | Mar 03 12:33:13 PM PST 24 |
| Peak memory | 192196 kb |
| Host | smart-ba2dc3ae-9394-4dc9-9ec6-f3caf8570f31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58154268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_time r_same_csr_outstanding.58154268 |
| Directory | /workspace/0.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2295142580 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 131790820 ps |
| CPU time | 1.66 seconds |
| Started | Mar 03 12:33:17 PM PST 24 |
| Finished | Mar 03 12:33:19 PM PST 24 |
| Peak memory | 197564 kb |
| Host | smart-a0fd338c-7da3-409d-bac3-1878f92cde6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295142580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2295142580 |
| Directory | /workspace/0.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.511147909 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 212068991 ps |
| CPU time | 0.8 seconds |
| Started | Mar 03 12:33:27 PM PST 24 |
| Finished | Mar 03 12:33:28 PM PST 24 |
| Peak memory | 193120 kb |
| Host | smart-e4a28992-e862-425e-ba3d-75663b9e9635 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511147909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_int g_err.511147909 |
| Directory | /workspace/0.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3970088398 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 263717812 ps |
| CPU time | 0.78 seconds |
| Started | Mar 03 12:33:18 PM PST 24 |
| Finished | Mar 03 12:33:19 PM PST 24 |
| Peak memory | 182620 kb |
| Host | smart-6ecb17f3-2014-4773-accd-ad7d87c0a2f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970088398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia sing.3970088398 |
| Directory | /workspace/1.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1693218953 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 564802345 ps |
| CPU time | 2.69 seconds |
| Started | Mar 03 12:33:22 PM PST 24 |
| Finished | Mar 03 12:33:25 PM PST 24 |
| Peak memory | 182792 kb |
| Host | smart-fbbd780a-f653-4c59-a12a-fa9c21ffea47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693218953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_ bash.1693218953 |
| Directory | /workspace/1.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.621491975 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 25315259 ps |
| CPU time | 0.71 seconds |
| Started | Mar 03 12:33:29 PM PST 24 |
| Finished | Mar 03 12:33:30 PM PST 24 |
| Peak memory | 194828 kb |
| Host | smart-5a80de26-5b54-4591-b816-a773d8940bb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621491975 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.621491975 |
| Directory | /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.708362897 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 31133086 ps |
| CPU time | 0.61 seconds |
| Started | Mar 03 12:33:20 PM PST 24 |
| Finished | Mar 03 12:33:21 PM PST 24 |
| Peak memory | 182584 kb |
| Host | smart-fb03b2bb-234b-47b5-b15e-923fa7b38e33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708362897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.708362897 |
| Directory | /workspace/1.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3678510666 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 15718734 ps |
| CPU time | 0.54 seconds |
| Started | Mar 03 12:33:21 PM PST 24 |
| Finished | Mar 03 12:33:22 PM PST 24 |
| Peak memory | 181592 kb |
| Host | smart-bf4c1df4-9f10-412a-8f13-353b4f18d3d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678510666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3678510666 |
| Directory | /workspace/1.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3613845694 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 85527243 ps |
| CPU time | 0.83 seconds |
| Started | Mar 03 12:33:13 PM PST 24 |
| Finished | Mar 03 12:33:14 PM PST 24 |
| Peak memory | 191564 kb |
| Host | smart-23be5eaf-d72e-4efa-ad7c-e409f95c322b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613845694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti mer_same_csr_outstanding.3613845694 |
| Directory | /workspace/1.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3586340297 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 97850661 ps |
| CPU time | 1.23 seconds |
| Started | Mar 03 12:33:22 PM PST 24 |
| Finished | Mar 03 12:33:24 PM PST 24 |
| Peak memory | 197556 kb |
| Host | smart-e8109d45-3184-4e69-8b74-b5d86894934d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586340297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3586340297 |
| Directory | /workspace/1.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.804307796 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 232987131 ps |
| CPU time | 1.36 seconds |
| Started | Mar 03 12:33:26 PM PST 24 |
| Finished | Mar 03 12:33:33 PM PST 24 |
| Peak memory | 195272 kb |
| Host | smart-f391215d-2ab2-41f3-8bd1-5f5e54888d8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804307796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int g_err.804307796 |
| Directory | /workspace/1.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.711424821 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 68566500 ps |
| CPU time | 0.93 seconds |
| Started | Mar 03 12:33:49 PM PST 24 |
| Finished | Mar 03 12:33:51 PM PST 24 |
| Peak memory | 196784 kb |
| Host | smart-ae370c6d-a1da-45c9-b0a9-6e31d4927e80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711424821 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.711424821 |
| Directory | /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1035765288 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 17900086 ps |
| CPU time | 0.61 seconds |
| Started | Mar 03 12:33:46 PM PST 24 |
| Finished | Mar 03 12:33:47 PM PST 24 |
| Peak memory | 182608 kb |
| Host | smart-93e8caec-9b9e-490d-af39-54d8179ee5c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035765288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1035765288 |
| Directory | /workspace/10.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3145514079 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 32759165 ps |
| CPU time | 0.55 seconds |
| Started | Mar 03 12:33:18 PM PST 24 |
| Finished | Mar 03 12:33:19 PM PST 24 |
| Peak memory | 182372 kb |
| Host | smart-7eb22f68-6c4f-4bc6-a6e3-4d38deb43927 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145514079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3145514079 |
| Directory | /workspace/10.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.70561837 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 57716590 ps |
| CPU time | 0.73 seconds |
| Started | Mar 03 12:33:36 PM PST 24 |
| Finished | Mar 03 12:33:39 PM PST 24 |
| Peak memory | 192964 kb |
| Host | smart-fc5fd8c6-5681-4e9d-a80e-3669588cf382 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70561837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_tim er_same_csr_outstanding.70561837 |
| Directory | /workspace/10.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2522555187 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 154460633 ps |
| CPU time | 2.21 seconds |
| Started | Mar 03 12:33:28 PM PST 24 |
| Finished | Mar 03 12:33:30 PM PST 24 |
| Peak memory | 197528 kb |
| Host | smart-f04ef82a-7936-461b-8c13-131025987c13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522555187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.2522555187 |
| Directory | /workspace/10.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3428023253 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 973216189 ps |
| CPU time | 1.55 seconds |
| Started | Mar 03 12:33:36 PM PST 24 |
| Finished | Mar 03 12:33:38 PM PST 24 |
| Peak memory | 194728 kb |
| Host | smart-eb49bdf3-caec-4d98-88da-96ac61f4f6b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428023253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i ntg_err.3428023253 |
| Directory | /workspace/10.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1756035341 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 37110888 ps |
| CPU time | 0.94 seconds |
| Started | Mar 03 12:33:12 PM PST 24 |
| Finished | Mar 03 12:33:13 PM PST 24 |
| Peak memory | 197296 kb |
| Host | smart-b8040d2c-640f-4929-ae3b-b6fbf727298a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756035341 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1756035341 |
| Directory | /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2935158475 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 15675672 ps |
| CPU time | 0.59 seconds |
| Started | Mar 03 12:33:37 PM PST 24 |
| Finished | Mar 03 12:33:38 PM PST 24 |
| Peak memory | 182608 kb |
| Host | smart-6f8fbbd7-f180-4d9c-88a5-0eeca18facd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935158475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2935158475 |
| Directory | /workspace/11.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.374800678 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 28605528 ps |
| CPU time | 0.52 seconds |
| Started | Mar 03 12:33:32 PM PST 24 |
| Finished | Mar 03 12:33:33 PM PST 24 |
| Peak memory | 182436 kb |
| Host | smart-3f2a247c-43aa-4af4-b16e-ecc61f04ccde |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374800678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.374800678 |
| Directory | /workspace/11.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.4263925737 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 19372250 ps |
| CPU time | 0.72 seconds |
| Started | Mar 03 12:33:21 PM PST 24 |
| Finished | Mar 03 12:33:23 PM PST 24 |
| Peak memory | 192940 kb |
| Host | smart-c5302758-d2d5-4fdb-91a6-d4435b7001b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263925737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t imer_same_csr_outstanding.4263925737 |
| Directory | /workspace/11.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1312327810 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 41283466 ps |
| CPU time | 1.92 seconds |
| Started | Mar 03 12:33:21 PM PST 24 |
| Finished | Mar 03 12:33:24 PM PST 24 |
| Peak memory | 197456 kb |
| Host | smart-df4f69c6-2498-4f81-8d3c-e0d833e9b689 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312327810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1312327810 |
| Directory | /workspace/11.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1736104523 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 168710725 ps |
| CPU time | 1.29 seconds |
| Started | Mar 03 12:33:21 PM PST 24 |
| Finished | Mar 03 12:33:22 PM PST 24 |
| Peak memory | 194936 kb |
| Host | smart-11255e62-705b-4fcf-b723-18d10d5a5d80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736104523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i ntg_err.1736104523 |
| Directory | /workspace/11.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3101886487 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 57916022 ps |
| CPU time | 0.96 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:20 PM PST 24 |
| Peak memory | 195152 kb |
| Host | smart-274e74b6-b1bb-4e33-a2c9-219a92376e24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101886487 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3101886487 |
| Directory | /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.119345966 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 39189760 ps |
| CPU time | 0.54 seconds |
| Started | Mar 03 12:33:39 PM PST 24 |
| Finished | Mar 03 12:33:40 PM PST 24 |
| Peak memory | 182604 kb |
| Host | smart-49b19d10-bf80-49eb-b93f-9938a7ee3054 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119345966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.119345966 |
| Directory | /workspace/12.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1309303632 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 43023313 ps |
| CPU time | 0.56 seconds |
| Started | Mar 03 12:33:18 PM PST 24 |
| Finished | Mar 03 12:33:19 PM PST 24 |
| Peak memory | 182448 kb |
| Host | smart-6c216848-d49c-4aa6-a87f-d0bfdd160d1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309303632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1309303632 |
| Directory | /workspace/12.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.777376924 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 18188432 ps |
| CPU time | 0.61 seconds |
| Started | Mar 03 12:33:36 PM PST 24 |
| Finished | Mar 03 12:33:39 PM PST 24 |
| Peak memory | 191800 kb |
| Host | smart-76b82778-636e-4c61-9e13-6c8e4386ca60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777376924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_ti mer_same_csr_outstanding.777376924 |
| Directory | /workspace/12.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.256732316 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 376085516 ps |
| CPU time | 1.84 seconds |
| Started | Mar 03 12:33:27 PM PST 24 |
| Finished | Mar 03 12:33:29 PM PST 24 |
| Peak memory | 196572 kb |
| Host | smart-c0d9ec7c-ef7f-4ab4-81d6-87421fca306b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256732316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.256732316 |
| Directory | /workspace/12.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.4105386391 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 450597706 ps |
| CPU time | 1.35 seconds |
| Started | Mar 03 12:33:45 PM PST 24 |
| Finished | Mar 03 12:33:46 PM PST 24 |
| Peak memory | 195280 kb |
| Host | smart-d7207e57-f11c-41de-9bd7-facc6a9d383d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105386391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i ntg_err.4105386391 |
| Directory | /workspace/12.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1129871908 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 125275235 ps |
| CPU time | 1.44 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:21 PM PST 24 |
| Peak memory | 195484 kb |
| Host | smart-e5fe1d04-4436-43d9-a283-cfd700a747aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129871908 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.1129871908 |
| Directory | /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2420018327 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 17826521 ps |
| CPU time | 0.55 seconds |
| Started | Mar 03 12:33:36 PM PST 24 |
| Finished | Mar 03 12:33:37 PM PST 24 |
| Peak memory | 182224 kb |
| Host | smart-48eab234-6513-4d56-addb-d6a2d1d5a102 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420018327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2420018327 |
| Directory | /workspace/13.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1505024203 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 111807072 ps |
| CPU time | 0.53 seconds |
| Started | Mar 03 12:33:39 PM PST 24 |
| Finished | Mar 03 12:33:40 PM PST 24 |
| Peak memory | 182208 kb |
| Host | smart-b6d4bc58-3b6d-4cdc-8275-65953e77f17c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505024203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1505024203 |
| Directory | /workspace/13.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.4129527765 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 20674200 ps |
| CPU time | 0.64 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:20 PM PST 24 |
| Peak memory | 192220 kb |
| Host | smart-5346c724-23b6-4aa7-bea8-7fbe2fff4979 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129527765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t imer_same_csr_outstanding.4129527765 |
| Directory | /workspace/13.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.543683786 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 123825785 ps |
| CPU time | 2.48 seconds |
| Started | Mar 03 12:33:52 PM PST 24 |
| Finished | Mar 03 12:33:55 PM PST 24 |
| Peak memory | 197360 kb |
| Host | smart-557b2f8e-418c-4525-9bb8-60129457a8f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543683786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.543683786 |
| Directory | /workspace/13.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2936303683 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 275360333 ps |
| CPU time | 1.14 seconds |
| Started | Mar 03 12:33:37 PM PST 24 |
| Finished | Mar 03 12:33:39 PM PST 24 |
| Peak memory | 194760 kb |
| Host | smart-7b8ae21e-265a-4d11-9515-c144bc8dfbcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936303683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i ntg_err.2936303683 |
| Directory | /workspace/13.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.4135515663 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 26160239 ps |
| CPU time | 0.77 seconds |
| Started | Mar 03 12:33:33 PM PST 24 |
| Finished | Mar 03 12:33:34 PM PST 24 |
| Peak memory | 195336 kb |
| Host | smart-5c7a02b7-58e6-4c88-a33a-015fd8e3b148 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135515663 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.4135515663 |
| Directory | /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2941572747 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 11233833 ps |
| CPU time | 0.57 seconds |
| Started | Mar 03 12:33:38 PM PST 24 |
| Finished | Mar 03 12:33:40 PM PST 24 |
| Peak memory | 182468 kb |
| Host | smart-0c553f05-f72f-4695-ad2f-b3c0af6ae37d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941572747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2941572747 |
| Directory | /workspace/14.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2670556620 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 17021580 ps |
| CPU time | 0.56 seconds |
| Started | Mar 03 12:33:44 PM PST 24 |
| Finished | Mar 03 12:33:45 PM PST 24 |
| Peak memory | 182088 kb |
| Host | smart-59c25d24-087b-40e1-b40d-8f9632f6da51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670556620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2670556620 |
| Directory | /workspace/14.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3943863479 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 71155289 ps |
| CPU time | 0.75 seconds |
| Started | Mar 03 12:33:25 PM PST 24 |
| Finished | Mar 03 12:33:26 PM PST 24 |
| Peak memory | 191924 kb |
| Host | smart-2a3f621a-8a01-430b-9486-cb22bc8ac036 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943863479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t imer_same_csr_outstanding.3943863479 |
| Directory | /workspace/14.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.800088038 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 259459873 ps |
| CPU time | 1.89 seconds |
| Started | Mar 03 12:34:01 PM PST 24 |
| Finished | Mar 03 12:34:03 PM PST 24 |
| Peak memory | 197348 kb |
| Host | smart-819f07bc-088b-46a2-ae2c-3cecdf94d2ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800088038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.800088038 |
| Directory | /workspace/14.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.4257982152 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 143816972 ps |
| CPU time | 1.01 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:21 PM PST 24 |
| Peak memory | 194396 kb |
| Host | smart-b049ce31-90e4-4364-a55a-556634331097 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257982152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i ntg_err.4257982152 |
| Directory | /workspace/14.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2483220893 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 23535127 ps |
| CPU time | 0.66 seconds |
| Started | Mar 03 12:33:29 PM PST 24 |
| Finished | Mar 03 12:33:30 PM PST 24 |
| Peak memory | 194248 kb |
| Host | smart-d6dfd381-5ef7-41f6-8455-3438fe590cc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483220893 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2483220893 |
| Directory | /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2230412585 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 28489989 ps |
| CPU time | 0.59 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:20 PM PST 24 |
| Peak memory | 182172 kb |
| Host | smart-148695aa-8ccd-4775-8e30-871f15d7de9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230412585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2230412585 |
| Directory | /workspace/15.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.382704380 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 27871424 ps |
| CPU time | 0.62 seconds |
| Started | Mar 03 12:33:17 PM PST 24 |
| Finished | Mar 03 12:33:19 PM PST 24 |
| Peak memory | 181232 kb |
| Host | smart-e5bb7836-d20f-430f-9612-adb727677174 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382704380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.382704380 |
| Directory | /workspace/15.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2343387608 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 60369149 ps |
| CPU time | 0.66 seconds |
| Started | Mar 03 12:33:24 PM PST 24 |
| Finished | Mar 03 12:33:25 PM PST 24 |
| Peak memory | 191532 kb |
| Host | smart-5ec754f3-0e0f-4d76-8bf8-45eebbb9eff6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343387608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t imer_same_csr_outstanding.2343387608 |
| Directory | /workspace/15.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.212101445 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 28021518 ps |
| CPU time | 1.3 seconds |
| Started | Mar 03 12:33:31 PM PST 24 |
| Finished | Mar 03 12:33:33 PM PST 24 |
| Peak memory | 197480 kb |
| Host | smart-bdaeb820-ea1d-4439-82a3-ba857da0ee59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212101445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.212101445 |
| Directory | /workspace/15.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.338318497 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 336067934 ps |
| CPU time | 1.05 seconds |
| Started | Mar 03 12:33:42 PM PST 24 |
| Finished | Mar 03 12:33:44 PM PST 24 |
| Peak memory | 194808 kb |
| Host | smart-7ff173e3-1386-4a30-95a8-9117d2667416 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338318497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_in tg_err.338318497 |
| Directory | /workspace/15.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2449850303 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 89366407 ps |
| CPU time | 0.72 seconds |
| Started | Mar 03 12:33:52 PM PST 24 |
| Finished | Mar 03 12:33:53 PM PST 24 |
| Peak memory | 194260 kb |
| Host | smart-b533e636-295f-4876-bf84-fdb32b2554f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449850303 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2449850303 |
| Directory | /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1333688071 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 91037042 ps |
| CPU time | 0.56 seconds |
| Started | Mar 03 12:33:18 PM PST 24 |
| Finished | Mar 03 12:33:19 PM PST 24 |
| Peak memory | 182640 kb |
| Host | smart-7a304cb0-1013-4b7d-84b0-ebdf05f3e4e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333688071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1333688071 |
| Directory | /workspace/16.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.667537725 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 13895175 ps |
| CPU time | 0.56 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:20 PM PST 24 |
| Peak memory | 181644 kb |
| Host | smart-3d5fa373-7e69-4c8c-b228-0a0d701bc240 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667537725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.667537725 |
| Directory | /workspace/16.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2797378060 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 85211540 ps |
| CPU time | 0.69 seconds |
| Started | Mar 03 12:33:44 PM PST 24 |
| Finished | Mar 03 12:33:45 PM PST 24 |
| Peak memory | 191300 kb |
| Host | smart-625ac0d4-4b61-4f9f-bdaa-e904dd6861d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797378060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t imer_same_csr_outstanding.2797378060 |
| Directory | /workspace/16.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2757077839 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 44027693 ps |
| CPU time | 1.13 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:21 PM PST 24 |
| Peak memory | 196756 kb |
| Host | smart-7341546c-e06b-42ac-8889-e070d897e597 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757077839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2757077839 |
| Directory | /workspace/16.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.4253312493 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 123930771 ps |
| CPU time | 1.08 seconds |
| Started | Mar 03 12:33:39 PM PST 24 |
| Finished | Mar 03 12:33:41 PM PST 24 |
| Peak memory | 182904 kb |
| Host | smart-070c9d2b-c539-418b-8a28-63112a82cea5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253312493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i ntg_err.4253312493 |
| Directory | /workspace/16.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1005718669 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 110384647 ps |
| CPU time | 1.52 seconds |
| Started | Mar 03 12:33:23 PM PST 24 |
| Finished | Mar 03 12:33:25 PM PST 24 |
| Peak memory | 197432 kb |
| Host | smart-e85204d4-2d2d-4dc3-b388-8144bd011aee |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005718669 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1005718669 |
| Directory | /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3929548860 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 19131673 ps |
| CPU time | 0.52 seconds |
| Started | Mar 03 12:33:20 PM PST 24 |
| Finished | Mar 03 12:33:21 PM PST 24 |
| Peak memory | 182156 kb |
| Host | smart-a246e2f2-890d-4104-8d6c-e1182401361d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929548860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.3929548860 |
| Directory | /workspace/17.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.4111160993 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 43826278 ps |
| CPU time | 0.56 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:20 PM PST 24 |
| Peak memory | 182092 kb |
| Host | smart-3b634e9e-b346-4ac8-b5ac-0394a85ae002 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111160993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.4111160993 |
| Directory | /workspace/17.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.635135692 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 264235565 ps |
| CPU time | 0.76 seconds |
| Started | Mar 03 12:33:18 PM PST 24 |
| Finished | Mar 03 12:33:19 PM PST 24 |
| Peak memory | 190728 kb |
| Host | smart-07ee09ee-a71d-462b-9ef1-77d250dc53f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635135692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti mer_same_csr_outstanding.635135692 |
| Directory | /workspace/17.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3444135011 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 56831576 ps |
| CPU time | 2.56 seconds |
| Started | Mar 03 12:33:33 PM PST 24 |
| Finished | Mar 03 12:33:36 PM PST 24 |
| Peak memory | 197368 kb |
| Host | smart-a02f0ba9-645c-4511-987c-6a4b899d2eab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444135011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3444135011 |
| Directory | /workspace/17.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1367360479 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 285151778 ps |
| CPU time | 0.92 seconds |
| Started | Mar 03 12:34:48 PM PST 24 |
| Finished | Mar 03 12:34:49 PM PST 24 |
| Peak memory | 193484 kb |
| Host | smart-94ceafdb-b53f-4d7c-a59b-b5e7d6f5cea9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367360479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i ntg_err.1367360479 |
| Directory | /workspace/17.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1149878256 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 54900836 ps |
| CPU time | 0.75 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:20 PM PST 24 |
| Peak memory | 195380 kb |
| Host | smart-4b1a9480-d3e0-4a70-939c-0454dfcc3f1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149878256 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1149878256 |
| Directory | /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3191462798 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 38619899 ps |
| CPU time | 0.53 seconds |
| Started | Mar 03 12:33:39 PM PST 24 |
| Finished | Mar 03 12:33:40 PM PST 24 |
| Peak memory | 182604 kb |
| Host | smart-89b53bc8-23e9-48b2-b17c-935b4c482dfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191462798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3191462798 |
| Directory | /workspace/18.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.4226713441 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 29295111 ps |
| CPU time | 0.55 seconds |
| Started | Mar 03 12:33:36 PM PST 24 |
| Finished | Mar 03 12:33:37 PM PST 24 |
| Peak memory | 182400 kb |
| Host | smart-d69eb883-1099-43a7-b686-ae4ef0464a2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226713441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.4226713441 |
| Directory | /workspace/18.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1710190695 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 59714819 ps |
| CPU time | 0.61 seconds |
| Started | Mar 03 12:33:40 PM PST 24 |
| Finished | Mar 03 12:33:41 PM PST 24 |
| Peak memory | 191264 kb |
| Host | smart-508dd3ed-6c30-498e-b265-d12af1b446ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710190695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t imer_same_csr_outstanding.1710190695 |
| Directory | /workspace/18.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2024623551 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 185024013 ps |
| CPU time | 1.79 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:21 PM PST 24 |
| Peak memory | 197168 kb |
| Host | smart-f6ea6496-5de8-44ca-ad23-ec673fd6e6d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024623551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2024623551 |
| Directory | /workspace/18.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1697116866 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 447042422 ps |
| CPU time | 1.41 seconds |
| Started | Mar 03 12:33:42 PM PST 24 |
| Finished | Mar 03 12:33:44 PM PST 24 |
| Peak memory | 195020 kb |
| Host | smart-d682733c-f5c7-4766-b536-00beff058b94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697116866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i ntg_err.1697116866 |
| Directory | /workspace/18.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3309751183 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 119377392 ps |
| CPU time | 0.83 seconds |
| Started | Mar 03 12:33:28 PM PST 24 |
| Finished | Mar 03 12:33:29 PM PST 24 |
| Peak memory | 196236 kb |
| Host | smart-083eebf1-8697-4578-a6d0-5bc4237b3c7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309751183 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3309751183 |
| Directory | /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.153854461 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 23436495 ps |
| CPU time | 0.58 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:20 PM PST 24 |
| Peak memory | 191504 kb |
| Host | smart-1d71fc3a-9922-4ae0-9c9a-804733b62f9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153854461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.153854461 |
| Directory | /workspace/19.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3620027393 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 12210994 ps |
| CPU time | 0.58 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:20 PM PST 24 |
| Peak memory | 179556 kb |
| Host | smart-bae8b836-61ff-4af7-a367-b4194a0a07c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620027393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3620027393 |
| Directory | /workspace/19.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2198172731 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 19235540 ps |
| CPU time | 0.58 seconds |
| Started | Mar 03 12:34:48 PM PST 24 |
| Finished | Mar 03 12:34:49 PM PST 24 |
| Peak memory | 190924 kb |
| Host | smart-454a8e1e-9dd0-4635-9b6c-37e9269357e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198172731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t imer_same_csr_outstanding.2198172731 |
| Directory | /workspace/19.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3432479786 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 227166729 ps |
| CPU time | 2.87 seconds |
| Started | Mar 03 12:33:10 PM PST 24 |
| Finished | Mar 03 12:33:13 PM PST 24 |
| Peak memory | 197488 kb |
| Host | smart-8d3dd73b-3357-40f0-ac60-65691ae65648 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432479786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3432479786 |
| Directory | /workspace/19.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.3145215437 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 236492380 ps |
| CPU time | 1.06 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:20 PM PST 24 |
| Peak memory | 180840 kb |
| Host | smart-0619e7e2-0523-4008-81a2-111cbf0ab583 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145215437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i ntg_err.3145215437 |
| Directory | /workspace/19.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.992237209 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 20778973 ps |
| CPU time | 0.61 seconds |
| Started | Mar 03 12:33:17 PM PST 24 |
| Finished | Mar 03 12:33:17 PM PST 24 |
| Peak memory | 191760 kb |
| Host | smart-b9ef420d-e179-4fdd-a2df-076bb093001c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992237209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alias ing.992237209 |
| Directory | /workspace/2.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.727725654 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 1838802120 ps |
| CPU time | 3.41 seconds |
| Started | Mar 03 12:33:14 PM PST 24 |
| Finished | Mar 03 12:33:18 PM PST 24 |
| Peak memory | 193292 kb |
| Host | smart-8c0ec1c1-8720-47e7-9367-bc515c69484a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727725654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_b ash.727725654 |
| Directory | /workspace/2.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.937607481 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 32702442 ps |
| CPU time | 0.54 seconds |
| Started | Mar 03 12:33:15 PM PST 24 |
| Finished | Mar 03 12:33:21 PM PST 24 |
| Peak memory | 182536 kb |
| Host | smart-1eb64b60-2c2c-4c78-a143-80661112748c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937607481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re set.937607481 |
| Directory | /workspace/2.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3109897658 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 24238679 ps |
| CPU time | 0.72 seconds |
| Started | Mar 03 12:33:15 PM PST 24 |
| Finished | Mar 03 12:33:16 PM PST 24 |
| Peak memory | 195044 kb |
| Host | smart-e21cbb37-8ffd-4232-afba-7adf02ae30b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109897658 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3109897658 |
| Directory | /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1746601112 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 13297257 ps |
| CPU time | 0.52 seconds |
| Started | Mar 03 12:33:22 PM PST 24 |
| Finished | Mar 03 12:33:23 PM PST 24 |
| Peak memory | 182224 kb |
| Host | smart-8a5f4858-dbed-48fc-b871-4f3c91f5e7d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746601112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1746601112 |
| Directory | /workspace/2.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.790527845 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 14049062 ps |
| CPU time | 0.52 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:20 PM PST 24 |
| Peak memory | 181568 kb |
| Host | smart-655b3780-f3f1-4706-a15d-72ee86aceeca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790527845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.790527845 |
| Directory | /workspace/2.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.279338057 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 118336439 ps |
| CPU time | 0.77 seconds |
| Started | Mar 03 12:33:17 PM PST 24 |
| Finished | Mar 03 12:33:18 PM PST 24 |
| Peak memory | 191716 kb |
| Host | smart-ac0dbbc1-12cb-4962-ad70-9357c752a987 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279338057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_tim er_same_csr_outstanding.279338057 |
| Directory | /workspace/2.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1615347895 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 350386491 ps |
| CPU time | 1.47 seconds |
| Started | Mar 03 12:33:15 PM PST 24 |
| Finished | Mar 03 12:33:17 PM PST 24 |
| Peak memory | 196912 kb |
| Host | smart-51c11c32-7ca0-4dc3-b648-6a0ad4d06306 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615347895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1615347895 |
| Directory | /workspace/2.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.889853098 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 165449046 ps |
| CPU time | 1.38 seconds |
| Started | Mar 03 12:33:23 PM PST 24 |
| Finished | Mar 03 12:33:25 PM PST 24 |
| Peak memory | 195104 kb |
| Host | smart-fe5385fa-4961-4990-8c79-6d0d6e05e608 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889853098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_int g_err.889853098 |
| Directory | /workspace/2.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3038286872 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 16451830 ps |
| CPU time | 0.54 seconds |
| Started | Mar 03 12:33:35 PM PST 24 |
| Finished | Mar 03 12:33:36 PM PST 24 |
| Peak memory | 182272 kb |
| Host | smart-bef3373a-e1c9-4f16-a791-c69d27ce78a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038286872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3038286872 |
| Directory | /workspace/20.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3746438558 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 28047829 ps |
| CPU time | 0.54 seconds |
| Started | Mar 03 12:33:40 PM PST 24 |
| Finished | Mar 03 12:33:41 PM PST 24 |
| Peak memory | 181620 kb |
| Host | smart-333dff18-6589-47f0-af2e-c5b0fb9d664c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746438558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3746438558 |
| Directory | /workspace/21.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1922342674 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 13405211 ps |
| CPU time | 0.54 seconds |
| Started | Mar 03 12:33:43 PM PST 24 |
| Finished | Mar 03 12:33:43 PM PST 24 |
| Peak memory | 181620 kb |
| Host | smart-c44a1da7-70d8-49a4-8d41-29ba1a564ec3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922342674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.1922342674 |
| Directory | /workspace/22.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1540736976 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 12947282 ps |
| CPU time | 0.54 seconds |
| Started | Mar 03 12:33:18 PM PST 24 |
| Finished | Mar 03 12:33:19 PM PST 24 |
| Peak memory | 182068 kb |
| Host | smart-2dbd5ecd-88fc-4a05-9c7c-2d038102b8ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540736976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1540736976 |
| Directory | /workspace/23.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3128554605 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 13153173 ps |
| CPU time | 0.56 seconds |
| Started | Mar 03 12:33:17 PM PST 24 |
| Finished | Mar 03 12:33:19 PM PST 24 |
| Peak memory | 180812 kb |
| Host | smart-3a1ef100-3229-45b3-a6e7-6794d6d6079d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128554605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3128554605 |
| Directory | /workspace/24.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.49655061 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 35466000 ps |
| CPU time | 0.54 seconds |
| Started | Mar 03 12:33:40 PM PST 24 |
| Finished | Mar 03 12:33:41 PM PST 24 |
| Peak memory | 182384 kb |
| Host | smart-d91cc942-7e50-4a5f-9e1f-c18c82cd8791 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49655061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.49655061 |
| Directory | /workspace/25.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1510347486 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 62802992 ps |
| CPU time | 0.55 seconds |
| Started | Mar 03 12:33:32 PM PST 24 |
| Finished | Mar 03 12:33:33 PM PST 24 |
| Peak memory | 182268 kb |
| Host | smart-da6768f8-f1ea-4290-a411-074351f17212 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510347486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1510347486 |
| Directory | /workspace/26.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.94025565 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 41965084 ps |
| CPU time | 0.51 seconds |
| Started | Mar 03 12:33:35 PM PST 24 |
| Finished | Mar 03 12:33:36 PM PST 24 |
| Peak memory | 181604 kb |
| Host | smart-dadc2cec-702f-4821-9715-094d4b43293f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94025565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.94025565 |
| Directory | /workspace/27.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.955170278 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 26691059 ps |
| CPU time | 0.54 seconds |
| Started | Mar 03 12:34:45 PM PST 24 |
| Finished | Mar 03 12:34:47 PM PST 24 |
| Peak memory | 182408 kb |
| Host | smart-11844b58-976a-491b-af43-3ac9d548ef1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955170278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.955170278 |
| Directory | /workspace/28.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.195824491 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 26656245 ps |
| CPU time | 0.56 seconds |
| Started | Mar 03 12:33:14 PM PST 24 |
| Finished | Mar 03 12:33:15 PM PST 24 |
| Peak memory | 181588 kb |
| Host | smart-d8325595-047f-41d8-ba30-87093ac78ea8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195824491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.195824491 |
| Directory | /workspace/29.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1031447020 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 72367557 ps |
| CPU time | 0.67 seconds |
| Started | Mar 03 12:33:22 PM PST 24 |
| Finished | Mar 03 12:33:23 PM PST 24 |
| Peak memory | 182648 kb |
| Host | smart-d20056e4-e540-47d4-a17c-295572d54f24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031447020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia sing.1031447020 |
| Directory | /workspace/3.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2949643852 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 40650378 ps |
| CPU time | 1.46 seconds |
| Started | Mar 03 12:33:26 PM PST 24 |
| Finished | Mar 03 12:33:27 PM PST 24 |
| Peak memory | 190896 kb |
| Host | smart-eaeae4a6-7ddb-4d48-b6f6-b3b676ffbb7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949643852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_ bash.2949643852 |
| Directory | /workspace/3.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.179957442 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 28847896 ps |
| CPU time | 0.58 seconds |
| Started | Mar 03 12:33:17 PM PST 24 |
| Finished | Mar 03 12:33:23 PM PST 24 |
| Peak memory | 182588 kb |
| Host | smart-ffc360d7-04f3-4eb8-8385-0fd5c43416d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179957442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_re set.179957442 |
| Directory | /workspace/3.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1803171964 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 23491488 ps |
| CPU time | 0.69 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:20 PM PST 24 |
| Peak memory | 194588 kb |
| Host | smart-ad1d2793-efee-48bc-8014-85059ffdc071 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803171964 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1803171964 |
| Directory | /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1325415723 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 14099733 ps |
| CPU time | 0.58 seconds |
| Started | Mar 03 12:33:16 PM PST 24 |
| Finished | Mar 03 12:33:17 PM PST 24 |
| Peak memory | 182236 kb |
| Host | smart-29c27c71-3212-4081-80da-4de49d86ee62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325415723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1325415723 |
| Directory | /workspace/3.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.985550938 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 15019301 ps |
| CPU time | 0.55 seconds |
| Started | Mar 03 12:33:28 PM PST 24 |
| Finished | Mar 03 12:33:29 PM PST 24 |
| Peak memory | 182288 kb |
| Host | smart-a3d85085-815f-4342-8646-add821ceb00d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985550938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.985550938 |
| Directory | /workspace/3.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3558483001 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 82134036 ps |
| CPU time | 0.84 seconds |
| Started | Mar 03 12:33:40 PM PST 24 |
| Finished | Mar 03 12:33:41 PM PST 24 |
| Peak memory | 194240 kb |
| Host | smart-b965c613-7cbd-4814-8984-434dd0f74655 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558483001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti mer_same_csr_outstanding.3558483001 |
| Directory | /workspace/3.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1386103078 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 390641474 ps |
| CPU time | 1.92 seconds |
| Started | Mar 03 12:33:17 PM PST 24 |
| Finished | Mar 03 12:33:20 PM PST 24 |
| Peak memory | 197436 kb |
| Host | smart-aaab0ec9-6dca-4004-bcbe-4c7854286102 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386103078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1386103078 |
| Directory | /workspace/3.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.564572866 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 24802652 ps |
| CPU time | 0.55 seconds |
| Started | Mar 03 12:33:14 PM PST 24 |
| Finished | Mar 03 12:33:20 PM PST 24 |
| Peak memory | 182364 kb |
| Host | smart-f0528cef-3b18-4bcf-adff-c5dd764b0297 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564572866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.564572866 |
| Directory | /workspace/30.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.86553514 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 34106309 ps |
| CPU time | 0.5 seconds |
| Started | Mar 03 12:33:16 PM PST 24 |
| Finished | Mar 03 12:33:17 PM PST 24 |
| Peak memory | 181624 kb |
| Host | smart-17a40c76-b2ee-4505-a01c-d12f08963bc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86553514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.86553514 |
| Directory | /workspace/31.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1644655697 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 42388192 ps |
| CPU time | 0.57 seconds |
| Started | Mar 03 12:33:50 PM PST 24 |
| Finished | Mar 03 12:33:51 PM PST 24 |
| Peak memory | 182300 kb |
| Host | smart-ca120842-9197-43d5-b146-32f1f21b7245 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644655697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1644655697 |
| Directory | /workspace/32.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2022694143 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 38587874 ps |
| CPU time | 0.53 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:19 PM PST 24 |
| Peak memory | 181616 kb |
| Host | smart-3f1f314f-9803-4ffb-b34a-5174544728a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022694143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.2022694143 |
| Directory | /workspace/33.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.582048092 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 20147548 ps |
| CPU time | 0.5 seconds |
| Started | Mar 03 12:33:18 PM PST 24 |
| Finished | Mar 03 12:33:24 PM PST 24 |
| Peak memory | 182004 kb |
| Host | smart-bb1c7be8-7d98-4744-baa5-9d2346dc9348 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582048092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.582048092 |
| Directory | /workspace/34.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.63474295 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 34822522 ps |
| CPU time | 0.5 seconds |
| Started | Mar 03 12:34:50 PM PST 24 |
| Finished | Mar 03 12:34:51 PM PST 24 |
| Peak memory | 181528 kb |
| Host | smart-29efa48e-08f0-4d32-aef6-0ef5001cf813 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63474295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.63474295 |
| Directory | /workspace/35.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1889174588 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 32801949 ps |
| CPU time | 0.54 seconds |
| Started | Mar 03 12:33:56 PM PST 24 |
| Finished | Mar 03 12:33:56 PM PST 24 |
| Peak memory | 182140 kb |
| Host | smart-b3c4392c-f3a0-4da8-a6ea-07b4ad6670cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889174588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1889174588 |
| Directory | /workspace/36.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2526794521 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 59946529 ps |
| CPU time | 0.53 seconds |
| Started | Mar 03 12:33:13 PM PST 24 |
| Finished | Mar 03 12:33:14 PM PST 24 |
| Peak memory | 182376 kb |
| Host | smart-68a8bb42-5558-4f89-982b-e34ca085b39b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526794521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2526794521 |
| Directory | /workspace/37.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3936376575 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 55183074 ps |
| CPU time | 0.56 seconds |
| Started | Mar 03 12:33:46 PM PST 24 |
| Finished | Mar 03 12:33:46 PM PST 24 |
| Peak memory | 182348 kb |
| Host | smart-b2679b00-53a1-4f7d-a2ac-ed59f05ab0d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936376575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3936376575 |
| Directory | /workspace/38.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2260626572 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 13508297 ps |
| CPU time | 0.56 seconds |
| Started | Mar 03 12:33:37 PM PST 24 |
| Finished | Mar 03 12:33:37 PM PST 24 |
| Peak memory | 182372 kb |
| Host | smart-ff42607b-1973-45fe-a0a1-432e863b342a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260626572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2260626572 |
| Directory | /workspace/39.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.4061881116 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 46601392 ps |
| CPU time | 0.71 seconds |
| Started | Mar 03 12:33:22 PM PST 24 |
| Finished | Mar 03 12:33:23 PM PST 24 |
| Peak memory | 192324 kb |
| Host | smart-04ca0bd3-1319-4bde-9618-7b8f96f09aac |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061881116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia sing.4061881116 |
| Directory | /workspace/4.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3275425756 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 202863095 ps |
| CPU time | 1.52 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:21 PM PST 24 |
| Peak memory | 192356 kb |
| Host | smart-a8747cdd-8cb6-4ba8-a64b-1763e52d4d72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275425756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_ bash.3275425756 |
| Directory | /workspace/4.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.4210558122 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 62948498 ps |
| CPU time | 0.55 seconds |
| Started | Mar 03 12:33:25 PM PST 24 |
| Finished | Mar 03 12:33:26 PM PST 24 |
| Peak memory | 182596 kb |
| Host | smart-54fee135-4400-416b-88ab-b2a534c97101 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210558122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r eset.4210558122 |
| Directory | /workspace/4.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.860100647 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 61626560 ps |
| CPU time | 1.44 seconds |
| Started | Mar 03 12:33:18 PM PST 24 |
| Finished | Mar 03 12:33:24 PM PST 24 |
| Peak memory | 197512 kb |
| Host | smart-186347ee-af85-4285-befc-b3ca00d1f0d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860100647 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.860100647 |
| Directory | /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2931549461 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 15986595 ps |
| CPU time | 0.61 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:20 PM PST 24 |
| Peak memory | 182952 kb |
| Host | smart-d09e7431-d20b-4d8b-af71-130c05ad94ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931549461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2931549461 |
| Directory | /workspace/4.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.759929648 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 32143116 ps |
| CPU time | 0.58 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:19 PM PST 24 |
| Peak memory | 182796 kb |
| Host | smart-07c666c6-7937-47bd-b2c7-52d0b409b082 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759929648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.759929648 |
| Directory | /workspace/4.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2786844559 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 26445515 ps |
| CPU time | 0.62 seconds |
| Started | Mar 03 12:33:39 PM PST 24 |
| Finished | Mar 03 12:33:40 PM PST 24 |
| Peak memory | 191568 kb |
| Host | smart-dd32b94e-f914-4be7-b066-be7b21ea7552 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786844559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti mer_same_csr_outstanding.2786844559 |
| Directory | /workspace/4.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1153693185 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 41961012 ps |
| CPU time | 2.01 seconds |
| Started | Mar 03 12:33:18 PM PST 24 |
| Finished | Mar 03 12:33:20 PM PST 24 |
| Peak memory | 197452 kb |
| Host | smart-ae837788-6430-46ac-89f7-72d660dc3169 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153693185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1153693185 |
| Directory | /workspace/4.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.555699341 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 45715750 ps |
| CPU time | 0.9 seconds |
| Started | Mar 03 12:33:34 PM PST 24 |
| Finished | Mar 03 12:33:35 PM PST 24 |
| Peak memory | 193256 kb |
| Host | smart-8529f679-a101-488a-b972-e984447d707c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555699341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_int g_err.555699341 |
| Directory | /workspace/4.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1784451026 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 41592394 ps |
| CPU time | 0.53 seconds |
| Started | Mar 03 12:34:50 PM PST 24 |
| Finished | Mar 03 12:34:51 PM PST 24 |
| Peak memory | 182312 kb |
| Host | smart-0be96331-5529-46a1-a349-1d9b09857f0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784451026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1784451026 |
| Directory | /workspace/40.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2344599045 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 13573006 ps |
| CPU time | 0.57 seconds |
| Started | Mar 03 12:33:26 PM PST 24 |
| Finished | Mar 03 12:33:27 PM PST 24 |
| Peak memory | 182504 kb |
| Host | smart-9e74529f-e9b4-419d-8c54-e06ee9c14f81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344599045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2344599045 |
| Directory | /workspace/41.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1467984487 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 17726236 ps |
| CPU time | 0.52 seconds |
| Started | Mar 03 12:33:37 PM PST 24 |
| Finished | Mar 03 12:33:37 PM PST 24 |
| Peak memory | 181996 kb |
| Host | smart-61ea0959-e156-4e89-84f9-87da0cf00c2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467984487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1467984487 |
| Directory | /workspace/42.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.80876878 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 39237476 ps |
| CPU time | 0.54 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:20 PM PST 24 |
| Peak memory | 182420 kb |
| Host | smart-4c4d1f3e-ad92-4890-bdb3-29fdd10caae0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80876878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.80876878 |
| Directory | /workspace/43.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.41173557 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 14055530 ps |
| CPU time | 0.52 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:20 PM PST 24 |
| Peak memory | 181600 kb |
| Host | smart-02d36d6c-4670-442f-9c09-2b31c2c4ae06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41173557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.41173557 |
| Directory | /workspace/44.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1174591368 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 13190351 ps |
| CPU time | 0.55 seconds |
| Started | Mar 03 12:37:26 PM PST 24 |
| Finished | Mar 03 12:37:27 PM PST 24 |
| Peak memory | 182308 kb |
| Host | smart-8e17db1a-5199-4ab3-b08f-a7a7bdf6dad5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174591368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1174591368 |
| Directory | /workspace/45.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3703519473 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 42320719 ps |
| CPU time | 0.54 seconds |
| Started | Mar 03 12:33:21 PM PST 24 |
| Finished | Mar 03 12:33:22 PM PST 24 |
| Peak memory | 181640 kb |
| Host | smart-90ccda79-197b-4b7e-8cf0-bc4aac886580 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703519473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3703519473 |
| Directory | /workspace/46.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3475474106 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 25937421 ps |
| CPU time | 0.55 seconds |
| Started | Mar 03 12:33:16 PM PST 24 |
| Finished | Mar 03 12:33:17 PM PST 24 |
| Peak memory | 182428 kb |
| Host | smart-7055c200-49a0-4c5d-860e-5f295e940536 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475474106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3475474106 |
| Directory | /workspace/47.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1061509793 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 82787076 ps |
| CPU time | 0.52 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:20 PM PST 24 |
| Peak memory | 181940 kb |
| Host | smart-a7de376a-9ab1-4c83-8131-8e791661bf98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061509793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1061509793 |
| Directory | /workspace/48.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.82080082 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 12407551 ps |
| CPU time | 0.53 seconds |
| Started | Mar 03 12:33:18 PM PST 24 |
| Finished | Mar 03 12:33:19 PM PST 24 |
| Peak memory | 182484 kb |
| Host | smart-8fedcd03-f637-4390-b7e5-f63aaa8032bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82080082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.82080082 |
| Directory | /workspace/49.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2612585933 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 28903300 ps |
| CPU time | 0.78 seconds |
| Started | Mar 03 12:33:27 PM PST 24 |
| Finished | Mar 03 12:33:28 PM PST 24 |
| Peak memory | 194676 kb |
| Host | smart-049ce8ed-1c06-4703-8400-fd31f3eef236 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612585933 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2612585933 |
| Directory | /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1560103880 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 25636162 ps |
| CPU time | 0.58 seconds |
| Started | Mar 03 12:33:17 PM PST 24 |
| Finished | Mar 03 12:33:18 PM PST 24 |
| Peak memory | 182608 kb |
| Host | smart-391ce52b-b570-46f5-a490-30a0e57301c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560103880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1560103880 |
| Directory | /workspace/5.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1492021259 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 103270820 ps |
| CPU time | 0.54 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:20 PM PST 24 |
| Peak memory | 181624 kb |
| Host | smart-d376eeeb-dbe5-4a14-a85f-54536d737364 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492021259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1492021259 |
| Directory | /workspace/5.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.4041746179 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 57270457 ps |
| CPU time | 0.82 seconds |
| Started | Mar 03 12:33:17 PM PST 24 |
| Finished | Mar 03 12:33:19 PM PST 24 |
| Peak memory | 193200 kb |
| Host | smart-dae411af-d60a-4fa7-951d-e32966c7b457 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041746179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti mer_same_csr_outstanding.4041746179 |
| Directory | /workspace/5.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.160406086 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 24305270 ps |
| CPU time | 1.03 seconds |
| Started | Mar 03 12:33:18 PM PST 24 |
| Finished | Mar 03 12:33:19 PM PST 24 |
| Peak memory | 191064 kb |
| Host | smart-2e792b3e-39bc-402b-826e-911568f17043 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160406086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.160406086 |
| Directory | /workspace/5.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2354622769 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 233024104 ps |
| CPU time | 1.33 seconds |
| Started | Mar 03 12:33:14 PM PST 24 |
| Finished | Mar 03 12:33:16 PM PST 24 |
| Peak memory | 194976 kb |
| Host | smart-ffb309dd-8dd4-4f57-962b-f5d113d5eba4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354622769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in tg_err.2354622769 |
| Directory | /workspace/5.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.407144397 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 128097351 ps |
| CPU time | 0.89 seconds |
| Started | Mar 03 12:33:39 PM PST 24 |
| Finished | Mar 03 12:33:40 PM PST 24 |
| Peak memory | 197032 kb |
| Host | smart-b3fd43f3-dc67-4039-bea9-f04134a57cdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407144397 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.407144397 |
| Directory | /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.158993242 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 20717497 ps |
| CPU time | 0.55 seconds |
| Started | Mar 03 12:33:29 PM PST 24 |
| Finished | Mar 03 12:33:30 PM PST 24 |
| Peak memory | 182576 kb |
| Host | smart-c7435005-f66c-4fa7-bf84-2b687b9142bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158993242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.158993242 |
| Directory | /workspace/6.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.251005651 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 14779973 ps |
| CPU time | 0.53 seconds |
| Started | Mar 03 12:33:17 PM PST 24 |
| Finished | Mar 03 12:33:18 PM PST 24 |
| Peak memory | 182388 kb |
| Host | smart-0ae7ef49-7230-42dd-b801-8e28cb7c07f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251005651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.251005651 |
| Directory | /workspace/6.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2130284619 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 19955409 ps |
| CPU time | 0.61 seconds |
| Started | Mar 03 12:33:17 PM PST 24 |
| Finished | Mar 03 12:33:18 PM PST 24 |
| Peak memory | 191880 kb |
| Host | smart-7e9833cc-b9ff-48d4-94b0-08f2281a5fde |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130284619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti mer_same_csr_outstanding.2130284619 |
| Directory | /workspace/6.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.377129184 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 697014535 ps |
| CPU time | 2.02 seconds |
| Started | Mar 03 12:33:27 PM PST 24 |
| Finished | Mar 03 12:33:30 PM PST 24 |
| Peak memory | 197356 kb |
| Host | smart-2d12c636-6fed-44c1-9eac-51ce8560c64c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377129184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.377129184 |
| Directory | /workspace/6.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.4076912835 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 159637771 ps |
| CPU time | 1.06 seconds |
| Started | Mar 03 12:33:17 PM PST 24 |
| Finished | Mar 03 12:33:19 PM PST 24 |
| Peak memory | 183192 kb |
| Host | smart-8ba9c6ed-443a-469b-a821-72b4ec13a052 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076912835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in tg_err.4076912835 |
| Directory | /workspace/6.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3382219707 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 59514706 ps |
| CPU time | 0.66 seconds |
| Started | Mar 03 12:33:12 PM PST 24 |
| Finished | Mar 03 12:33:13 PM PST 24 |
| Peak memory | 192980 kb |
| Host | smart-f4487182-ab98-4163-a45b-694e6e43c6dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382219707 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3382219707 |
| Directory | /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1507323524 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 11010480 ps |
| CPU time | 0.54 seconds |
| Started | Mar 03 12:33:24 PM PST 24 |
| Finished | Mar 03 12:33:25 PM PST 24 |
| Peak memory | 182576 kb |
| Host | smart-982b84cd-02b9-4cc7-b2e5-dfdb8a32e4b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507323524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1507323524 |
| Directory | /workspace/7.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.307467932 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 13663427 ps |
| CPU time | 0.54 seconds |
| Started | Mar 03 12:33:19 PM PST 24 |
| Finished | Mar 03 12:33:20 PM PST 24 |
| Peak memory | 182348 kb |
| Host | smart-a5ae5591-e885-4382-9078-04afc702e2cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307467932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.307467932 |
| Directory | /workspace/7.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.401708837 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 71508796 ps |
| CPU time | 0.76 seconds |
| Started | Mar 03 12:33:23 PM PST 24 |
| Finished | Mar 03 12:33:24 PM PST 24 |
| Peak memory | 191552 kb |
| Host | smart-040404d8-4d01-49da-845c-f3b65d0796da |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401708837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_tim er_same_csr_outstanding.401708837 |
| Directory | /workspace/7.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2033759087 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 148507723 ps |
| CPU time | 1.03 seconds |
| Started | Mar 03 12:33:32 PM PST 24 |
| Finished | Mar 03 12:33:33 PM PST 24 |
| Peak memory | 196992 kb |
| Host | smart-2291b58c-f003-4b1a-9a65-bcb9eb5f5b07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033759087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2033759087 |
| Directory | /workspace/7.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2886335992 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 215578281 ps |
| CPU time | 1.3 seconds |
| Started | Mar 03 12:33:17 PM PST 24 |
| Finished | Mar 03 12:33:19 PM PST 24 |
| Peak memory | 183184 kb |
| Host | smart-b206fc80-96da-436e-b425-4b855852d543 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886335992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in tg_err.2886335992 |
| Directory | /workspace/7.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.937975666 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 57632699 ps |
| CPU time | 0.83 seconds |
| Started | Mar 03 12:33:18 PM PST 24 |
| Finished | Mar 03 12:33:21 PM PST 24 |
| Peak memory | 195732 kb |
| Host | smart-64cd0d34-5c37-40b1-b534-775d62f43c60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937975666 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.937975666 |
| Directory | /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1979766167 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 22668931 ps |
| CPU time | 0.55 seconds |
| Started | Mar 03 12:33:08 PM PST 24 |
| Finished | Mar 03 12:33:09 PM PST 24 |
| Peak memory | 182528 kb |
| Host | smart-f70ffeb9-3ef3-409f-afd9-6cae98f84079 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979766167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1979766167 |
| Directory | /workspace/8.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1312731157 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 120795322 ps |
| CPU time | 0.53 seconds |
| Started | Mar 03 12:33:15 PM PST 24 |
| Finished | Mar 03 12:33:16 PM PST 24 |
| Peak memory | 182364 kb |
| Host | smart-fd8fe66f-6c0e-47fb-bb2f-8533efbe8801 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312731157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1312731157 |
| Directory | /workspace/8.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2818660781 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 108309228 ps |
| CPU time | 0.81 seconds |
| Started | Mar 03 12:33:13 PM PST 24 |
| Finished | Mar 03 12:33:14 PM PST 24 |
| Peak memory | 191564 kb |
| Host | smart-8b88d1cd-bf52-4b07-8fc6-e63532e8513a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818660781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti mer_same_csr_outstanding.2818660781 |
| Directory | /workspace/8.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.4042406759 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 223183077 ps |
| CPU time | 1.32 seconds |
| Started | Mar 03 12:33:18 PM PST 24 |
| Finished | Mar 03 12:33:20 PM PST 24 |
| Peak memory | 196744 kb |
| Host | smart-d8693bde-b5d3-4f7f-8dea-3705dd606789 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042406759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.4042406759 |
| Directory | /workspace/8.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.912580031 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 92256126 ps |
| CPU time | 1.08 seconds |
| Started | Mar 03 12:33:20 PM PST 24 |
| Finished | Mar 03 12:33:21 PM PST 24 |
| Peak memory | 183036 kb |
| Host | smart-81260d99-97e1-471e-98e0-939fdebe4063 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912580031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int g_err.912580031 |
| Directory | /workspace/8.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.4219296081 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 30876588 ps |
| CPU time | 0.64 seconds |
| Started | Mar 03 12:33:43 PM PST 24 |
| Finished | Mar 03 12:33:44 PM PST 24 |
| Peak memory | 194048 kb |
| Host | smart-37038a6e-6ba7-4633-8442-4f132326938a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219296081 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.4219296081 |
| Directory | /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.103880219 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 13227818 ps |
| CPU time | 0.58 seconds |
| Started | Mar 03 12:33:21 PM PST 24 |
| Finished | Mar 03 12:33:22 PM PST 24 |
| Peak memory | 182532 kb |
| Host | smart-b9b86d61-90f7-468f-9453-987428e239fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103880219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.103880219 |
| Directory | /workspace/9.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1095625938 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 14187303 ps |
| CPU time | 0.56 seconds |
| Started | Mar 03 12:33:38 PM PST 24 |
| Finished | Mar 03 12:33:39 PM PST 24 |
| Peak memory | 181604 kb |
| Host | smart-6870a99c-5918-45b5-870d-ed087f79eb56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095625938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1095625938 |
| Directory | /workspace/9.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3976568954 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 19304769 ps |
| CPU time | 0.82 seconds |
| Started | Mar 03 12:33:42 PM PST 24 |
| Finished | Mar 03 12:33:43 PM PST 24 |
| Peak memory | 190856 kb |
| Host | smart-ffac5a65-38f7-40c3-972f-29017b76e0de |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976568954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti mer_same_csr_outstanding.3976568954 |
| Directory | /workspace/9.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1215327698 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 29954298 ps |
| CPU time | 0.92 seconds |
| Started | Mar 03 12:33:15 PM PST 24 |
| Finished | Mar 03 12:33:16 PM PST 24 |
| Peak memory | 194448 kb |
| Host | smart-c36a5397-927a-450a-acbe-124fdd932937 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215327698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1215327698 |
| Directory | /workspace/9.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2468193591 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 369629292 ps |
| CPU time | 1.37 seconds |
| Started | Mar 03 12:33:41 PM PST 24 |
| Finished | Mar 03 12:33:43 PM PST 24 |
| Peak memory | 182988 kb |
| Host | smart-a73e2570-d881-4997-b0ee-52ed28026c5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468193591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in tg_err.2468193591 |
| Directory | /workspace/9.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3011133904 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 41324513472 ps |
| CPU time | 33.77 seconds |
| Started | Mar 03 04:07:25 PM PST 24 |
| Finished | Mar 03 04:07:59 PM PST 24 |
| Peak memory | 183200 kb |
| Host | smart-8adea783-db52-41c8-8d71-a710b90c4cc5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011133904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_cfg_update_on_fly.3011133904 |
| Directory | /workspace/0.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/0.rv_timer_disabled.2437020516 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 91131681820 ps |
| CPU time | 78.55 seconds |
| Started | Mar 03 04:07:21 PM PST 24 |
| Finished | Mar 03 04:08:40 PM PST 24 |
| Peak memory | 183104 kb |
| Host | smart-8d054d00-dbfe-4ad8-b76e-9702b6ad5e7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2437020516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2437020516 |
| Directory | /workspace/0.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/0.rv_timer_random_reset.939493306 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 3446645269 ps |
| CPU time | 3.41 seconds |
| Started | Mar 03 04:07:19 PM PST 24 |
| Finished | Mar 03 04:07:22 PM PST 24 |
| Peak memory | 183016 kb |
| Host | smart-b63d7162-f1af-4ef4-b993-18246d5823ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=939493306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.939493306 |
| Directory | /workspace/0.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/0.rv_timer_stress_all.1697235878 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 504360028472 ps |
| CPU time | 823.37 seconds |
| Started | Mar 03 04:07:27 PM PST 24 |
| Finished | Mar 03 04:21:11 PM PST 24 |
| Peak memory | 191364 kb |
| Host | smart-779ff995-9c23-4aab-aef9-3d9ec3e1d56d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697235878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all. 1697235878 |
| Directory | /workspace/0.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.956120010 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 2742446439149 ps |
| CPU time | 890.63 seconds |
| Started | Mar 03 04:07:30 PM PST 24 |
| Finished | Mar 03 04:22:21 PM PST 24 |
| Peak memory | 183220 kb |
| Host | smart-9b294a12-7d07-441e-9586-6f7a9def170e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956120010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .rv_timer_cfg_update_on_fly.956120010 |
| Directory | /workspace/1.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/1.rv_timer_disabled.123183671 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 131838562311 ps |
| CPU time | 205.05 seconds |
| Started | Mar 03 04:07:26 PM PST 24 |
| Finished | Mar 03 04:10:51 PM PST 24 |
| Peak memory | 183180 kb |
| Host | smart-6781553e-d6b4-4ff6-b3eb-977f7cce6c08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=123183671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.123183671 |
| Directory | /workspace/1.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/1.rv_timer_random.3865399246 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 273084988573 ps |
| CPU time | 275.03 seconds |
| Started | Mar 03 04:07:29 PM PST 24 |
| Finished | Mar 03 04:12:04 PM PST 24 |
| Peak memory | 191300 kb |
| Host | smart-e42c5ce9-830d-4aff-aa92-08db34353eb7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865399246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3865399246 |
| Directory | /workspace/1.rv_timer_random/latest |
| Test location | /workspace/coverage/default/1.rv_timer_random_reset.4087207149 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 22104593 ps |
| CPU time | 0.76 seconds |
| Started | Mar 03 04:07:38 PM PST 24 |
| Finished | Mar 03 04:07:39 PM PST 24 |
| Peak memory | 182732 kb |
| Host | smart-5b6c9c85-be23-442d-a7af-b54638c7a4dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4087207149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.4087207149 |
| Directory | /workspace/1.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/1.rv_timer_sec_cm.4167169474 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 101083108 ps |
| CPU time | 1.03 seconds |
| Started | Mar 03 04:07:38 PM PST 24 |
| Finished | Mar 03 04:07:39 PM PST 24 |
| Peak memory | 214680 kb |
| Host | smart-718110b3-cb21-424e-9113-bdb6fe1b00f9 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167169474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.4167169474 |
| Directory | /workspace/1.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.1859327050 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 4669799440 ps |
| CPU time | 9.08 seconds |
| Started | Mar 03 04:07:55 PM PST 24 |
| Finished | Mar 03 04:08:05 PM PST 24 |
| Peak memory | 183168 kb |
| Host | smart-b9bc17d7-c531-4ca2-a5bd-7ec075641012 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859327050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_cfg_update_on_fly.1859327050 |
| Directory | /workspace/10.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/10.rv_timer_disabled.970919309 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 41310504285 ps |
| CPU time | 62.77 seconds |
| Started | Mar 03 04:08:01 PM PST 24 |
| Finished | Mar 03 04:09:04 PM PST 24 |
| Peak memory | 183152 kb |
| Host | smart-34012c02-737e-408f-837a-475c1a373cf7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=970919309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.970919309 |
| Directory | /workspace/10.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/10.rv_timer_random.2349504079 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 326328766592 ps |
| CPU time | 192.34 seconds |
| Started | Mar 03 04:08:00 PM PST 24 |
| Finished | Mar 03 04:11:13 PM PST 24 |
| Peak memory | 191344 kb |
| Host | smart-6a450879-106d-413c-9645-73574b269aaa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349504079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2349504079 |
| Directory | /workspace/10.rv_timer_random/latest |
| Test location | /workspace/coverage/default/10.rv_timer_random_reset.1536946146 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 108978052112 ps |
| CPU time | 1414.13 seconds |
| Started | Mar 03 04:08:03 PM PST 24 |
| Finished | Mar 03 04:31:38 PM PST 24 |
| Peak memory | 183164 kb |
| Host | smart-19d52379-9865-43b1-b0ed-5c0475068f0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1536946146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1536946146 |
| Directory | /workspace/10.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.329707277 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 32604582560 ps |
| CPU time | 274.27 seconds |
| Started | Mar 03 04:08:03 PM PST 24 |
| Finished | Mar 03 04:12:38 PM PST 24 |
| Peak memory | 206128 kb |
| Host | smart-8d21b5c6-d3f5-46f9-bef4-bf28564e49dd |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329707277 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.329707277 |
| Directory | /workspace/10.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/101.rv_timer_random.4155240832 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 96630306044 ps |
| CPU time | 278.71 seconds |
| Started | Mar 03 04:13:41 PM PST 24 |
| Finished | Mar 03 04:18:20 PM PST 24 |
| Peak memory | 191360 kb |
| Host | smart-5b172b95-02cd-412f-8992-0826a7197d52 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155240832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.4155240832 |
| Directory | /workspace/101.rv_timer_random/latest |
| Test location | /workspace/coverage/default/102.rv_timer_random.1586660005 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 26620228256 ps |
| CPU time | 29.57 seconds |
| Started | Mar 03 04:13:39 PM PST 24 |
| Finished | Mar 03 04:14:08 PM PST 24 |
| Peak memory | 183200 kb |
| Host | smart-d9ffa87b-7ccf-414f-b811-916772d98d1f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586660005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1586660005 |
| Directory | /workspace/102.rv_timer_random/latest |
| Test location | /workspace/coverage/default/104.rv_timer_random.3779941736 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 91582663241 ps |
| CPU time | 710.2 seconds |
| Started | Mar 03 04:13:40 PM PST 24 |
| Finished | Mar 03 04:25:31 PM PST 24 |
| Peak memory | 191344 kb |
| Host | smart-ec38393d-3377-4c96-a78d-63ad58f3c1d3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779941736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3779941736 |
| Directory | /workspace/104.rv_timer_random/latest |
| Test location | /workspace/coverage/default/107.rv_timer_random.2633967869 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 108700955673 ps |
| CPU time | 165 seconds |
| Started | Mar 03 04:13:41 PM PST 24 |
| Finished | Mar 03 04:16:26 PM PST 24 |
| Peak memory | 191352 kb |
| Host | smart-f99c31e9-e3ba-4b10-ac58-b98785f82f15 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633967869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2633967869 |
| Directory | /workspace/107.rv_timer_random/latest |
| Test location | /workspace/coverage/default/108.rv_timer_random.809802322 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 131553988403 ps |
| CPU time | 79.41 seconds |
| Started | Mar 03 04:13:46 PM PST 24 |
| Finished | Mar 03 04:15:06 PM PST 24 |
| Peak memory | 183168 kb |
| Host | smart-f4d929d4-4719-4d52-82b1-a4e29db3ec50 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809802322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.809802322 |
| Directory | /workspace/108.rv_timer_random/latest |
| Test location | /workspace/coverage/default/109.rv_timer_random.2713445460 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 379226882784 ps |
| CPU time | 600.59 seconds |
| Started | Mar 03 04:13:45 PM PST 24 |
| Finished | Mar 03 04:23:46 PM PST 24 |
| Peak memory | 191376 kb |
| Host | smart-1f77037e-0c8c-454c-8cde-1c34e7423fd9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713445460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2713445460 |
| Directory | /workspace/109.rv_timer_random/latest |
| Test location | /workspace/coverage/default/11.rv_timer_disabled.3067008146 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 38367896963 ps |
| CPU time | 67.59 seconds |
| Started | Mar 03 04:08:05 PM PST 24 |
| Finished | Mar 03 04:09:12 PM PST 24 |
| Peak memory | 183184 kb |
| Host | smart-09294580-2218-4703-bc38-023190a5f049 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3067008146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.3067008146 |
| Directory | /workspace/11.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/11.rv_timer_random.2090628035 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 3336745518 ps |
| CPU time | 5.51 seconds |
| Started | Mar 03 04:08:00 PM PST 24 |
| Finished | Mar 03 04:08:05 PM PST 24 |
| Peak memory | 183176 kb |
| Host | smart-7258a09b-192c-4d28-a5aa-67cf4ff29ec7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090628035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2090628035 |
| Directory | /workspace/11.rv_timer_random/latest |
| Test location | /workspace/coverage/default/11.rv_timer_random_reset.2653122484 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 143991118053 ps |
| CPU time | 77.97 seconds |
| Started | Mar 03 04:08:10 PM PST 24 |
| Finished | Mar 03 04:09:28 PM PST 24 |
| Peak memory | 195080 kb |
| Host | smart-5f27e36f-7c2b-4343-b5b6-1e3b191161b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2653122484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2653122484 |
| Directory | /workspace/11.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/111.rv_timer_random.356953415 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 144257299126 ps |
| CPU time | 144.89 seconds |
| Started | Mar 03 04:13:45 PM PST 24 |
| Finished | Mar 03 04:16:10 PM PST 24 |
| Peak memory | 191368 kb |
| Host | smart-e2044f54-e801-4c21-b72b-5fdf5d6648ed |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356953415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.356953415 |
| Directory | /workspace/111.rv_timer_random/latest |
| Test location | /workspace/coverage/default/112.rv_timer_random.3367511282 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 164048160588 ps |
| CPU time | 435.7 seconds |
| Started | Mar 03 04:13:46 PM PST 24 |
| Finished | Mar 03 04:21:01 PM PST 24 |
| Peak memory | 183168 kb |
| Host | smart-a7e98e0d-0d8d-4ab5-9bf4-51c489c44871 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367511282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3367511282 |
| Directory | /workspace/112.rv_timer_random/latest |
| Test location | /workspace/coverage/default/113.rv_timer_random.3791155338 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 124503948234 ps |
| CPU time | 792.56 seconds |
| Started | Mar 03 04:13:46 PM PST 24 |
| Finished | Mar 03 04:26:59 PM PST 24 |
| Peak memory | 191324 kb |
| Host | smart-19f984ef-8dc3-47c9-8965-0ce12b150422 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791155338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3791155338 |
| Directory | /workspace/113.rv_timer_random/latest |
| Test location | /workspace/coverage/default/114.rv_timer_random.2665265364 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 46504236910 ps |
| CPU time | 82.88 seconds |
| Started | Mar 03 04:13:45 PM PST 24 |
| Finished | Mar 03 04:15:08 PM PST 24 |
| Peak memory | 183164 kb |
| Host | smart-0429d387-9723-44c4-b613-b68e841d76ba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665265364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2665265364 |
| Directory | /workspace/114.rv_timer_random/latest |
| Test location | /workspace/coverage/default/115.rv_timer_random.473995350 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1771188078076 ps |
| CPU time | 1839.69 seconds |
| Started | Mar 03 04:13:46 PM PST 24 |
| Finished | Mar 03 04:44:26 PM PST 24 |
| Peak memory | 191392 kb |
| Host | smart-b9f3d13a-beb8-4ee1-affb-c334fb6ca875 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473995350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.473995350 |
| Directory | /workspace/115.rv_timer_random/latest |
| Test location | /workspace/coverage/default/116.rv_timer_random.2872668701 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 11442332129 ps |
| CPU time | 9.58 seconds |
| Started | Mar 03 04:13:53 PM PST 24 |
| Finished | Mar 03 04:14:03 PM PST 24 |
| Peak memory | 182880 kb |
| Host | smart-3adda71b-6562-4588-9c30-d896da0a45f3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872668701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2872668701 |
| Directory | /workspace/116.rv_timer_random/latest |
| Test location | /workspace/coverage/default/118.rv_timer_random.1582094857 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 64430738198 ps |
| CPU time | 54.16 seconds |
| Started | Mar 03 04:13:53 PM PST 24 |
| Finished | Mar 03 04:14:47 PM PST 24 |
| Peak memory | 183156 kb |
| Host | smart-da0f049e-3f95-4fa6-9f56-91cc327d0a86 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582094857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1582094857 |
| Directory | /workspace/118.rv_timer_random/latest |
| Test location | /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1184955729 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 277820536242 ps |
| CPU time | 567.79 seconds |
| Started | Mar 03 04:08:23 PM PST 24 |
| Finished | Mar 03 04:17:52 PM PST 24 |
| Peak memory | 183176 kb |
| Host | smart-77e6b0eb-83d5-48e6-9ef0-2a4b985b626e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184955729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_cfg_update_on_fly.1184955729 |
| Directory | /workspace/12.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/12.rv_timer_disabled.3280954196 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 134282295713 ps |
| CPU time | 218.88 seconds |
| Started | Mar 03 04:08:16 PM PST 24 |
| Finished | Mar 03 04:11:56 PM PST 24 |
| Peak memory | 183152 kb |
| Host | smart-6d751727-3348-48ee-b81f-8c3119bf6871 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3280954196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3280954196 |
| Directory | /workspace/12.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/12.rv_timer_random.2122577714 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 62154771207 ps |
| CPU time | 210.29 seconds |
| Started | Mar 03 04:08:16 PM PST 24 |
| Finished | Mar 03 04:11:47 PM PST 24 |
| Peak memory | 191360 kb |
| Host | smart-6b4dcfe7-b870-4461-ab2b-c15ab33da09d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122577714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2122577714 |
| Directory | /workspace/12.rv_timer_random/latest |
| Test location | /workspace/coverage/default/12.rv_timer_random_reset.2405037560 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 961240094 ps |
| CPU time | 1.51 seconds |
| Started | Mar 03 04:08:21 PM PST 24 |
| Finished | Mar 03 04:08:24 PM PST 24 |
| Peak memory | 191348 kb |
| Host | smart-66da44af-205a-43f6-afa8-8b598a0fe688 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2405037560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2405037560 |
| Directory | /workspace/12.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/12.rv_timer_stress_all.4040002502 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 272893383002 ps |
| CPU time | 258.02 seconds |
| Started | Mar 03 04:08:18 PM PST 24 |
| Finished | Mar 03 04:12:37 PM PST 24 |
| Peak memory | 191392 kb |
| Host | smart-eb55a9d2-3b87-446e-890b-155f74df41a9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040002502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all .4040002502 |
| Directory | /workspace/12.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/120.rv_timer_random.1243458273 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 409979058600 ps |
| CPU time | 424.98 seconds |
| Started | Mar 03 04:13:51 PM PST 24 |
| Finished | Mar 03 04:20:56 PM PST 24 |
| Peak memory | 193328 kb |
| Host | smart-527574a0-aee8-40c3-b764-7cf9073b43eb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243458273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1243458273 |
| Directory | /workspace/120.rv_timer_random/latest |
| Test location | /workspace/coverage/default/122.rv_timer_random.2555867500 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 305652898004 ps |
| CPU time | 291.85 seconds |
| Started | Mar 03 04:13:53 PM PST 24 |
| Finished | Mar 03 04:18:45 PM PST 24 |
| Peak memory | 191396 kb |
| Host | smart-be00ae81-9d84-4614-90a2-006b451ee436 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555867500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2555867500 |
| Directory | /workspace/122.rv_timer_random/latest |
| Test location | /workspace/coverage/default/123.rv_timer_random.3301237590 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 147718865474 ps |
| CPU time | 124.08 seconds |
| Started | Mar 03 04:13:51 PM PST 24 |
| Finished | Mar 03 04:15:55 PM PST 24 |
| Peak memory | 194156 kb |
| Host | smart-734da346-949d-4d94-a5cf-1fcc88efdfe4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301237590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3301237590 |
| Directory | /workspace/123.rv_timer_random/latest |
| Test location | /workspace/coverage/default/125.rv_timer_random.1582619953 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 179180796008 ps |
| CPU time | 92.23 seconds |
| Started | Mar 03 04:13:57 PM PST 24 |
| Finished | Mar 03 04:15:30 PM PST 24 |
| Peak memory | 183132 kb |
| Host | smart-229a67f7-93ac-4a2f-a5f0-92004879e758 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582619953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1582619953 |
| Directory | /workspace/125.rv_timer_random/latest |
| Test location | /workspace/coverage/default/126.rv_timer_random.1641370923 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 520157073694 ps |
| CPU time | 2796.15 seconds |
| Started | Mar 03 04:13:57 PM PST 24 |
| Finished | Mar 03 05:00:34 PM PST 24 |
| Peak memory | 191452 kb |
| Host | smart-6979dbb2-4651-491e-a85f-1cf16871b229 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641370923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1641370923 |
| Directory | /workspace/126.rv_timer_random/latest |
| Test location | /workspace/coverage/default/128.rv_timer_random.1411541605 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 123625317353 ps |
| CPU time | 241.1 seconds |
| Started | Mar 03 04:14:04 PM PST 24 |
| Finished | Mar 03 04:18:06 PM PST 24 |
| Peak memory | 191328 kb |
| Host | smart-726924d7-3a8a-424d-b2a5-3d3e4d147f00 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411541605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1411541605 |
| Directory | /workspace/128.rv_timer_random/latest |
| Test location | /workspace/coverage/default/129.rv_timer_random.1077150536 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 242537816305 ps |
| CPU time | 1304.16 seconds |
| Started | Mar 03 04:14:06 PM PST 24 |
| Finished | Mar 03 04:35:50 PM PST 24 |
| Peak memory | 191388 kb |
| Host | smart-0dc54d83-3090-4ef5-9b5d-52dfeb223182 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077150536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1077150536 |
| Directory | /workspace/129.rv_timer_random/latest |
| Test location | /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1998147158 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 75592288089 ps |
| CPU time | 47.96 seconds |
| Started | Mar 03 04:08:44 PM PST 24 |
| Finished | Mar 03 04:09:32 PM PST 24 |
| Peak memory | 183200 kb |
| Host | smart-4baf9e8b-763b-46ca-a7a9-3c2fdd5dda58 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998147158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.1998147158 |
| Directory | /workspace/13.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/13.rv_timer_random.197713429 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 134558920493 ps |
| CPU time | 2106.8 seconds |
| Started | Mar 03 04:08:20 PM PST 24 |
| Finished | Mar 03 04:43:27 PM PST 24 |
| Peak memory | 191372 kb |
| Host | smart-39d70500-225b-40df-9d46-bb0eb767e859 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197713429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.197713429 |
| Directory | /workspace/13.rv_timer_random/latest |
| Test location | /workspace/coverage/default/130.rv_timer_random.1150550440 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 45047605251 ps |
| CPU time | 28.52 seconds |
| Started | Mar 03 04:14:04 PM PST 24 |
| Finished | Mar 03 04:14:33 PM PST 24 |
| Peak memory | 183192 kb |
| Host | smart-32e827e0-9403-45da-8f43-913b3c18ede8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150550440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1150550440 |
| Directory | /workspace/130.rv_timer_random/latest |
| Test location | /workspace/coverage/default/131.rv_timer_random.3256288776 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 149744576446 ps |
| CPU time | 1490.37 seconds |
| Started | Mar 03 04:14:04 PM PST 24 |
| Finished | Mar 03 04:38:55 PM PST 24 |
| Peak memory | 194380 kb |
| Host | smart-c549d52c-571d-4031-b055-e7098799ea86 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256288776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3256288776 |
| Directory | /workspace/131.rv_timer_random/latest |
| Test location | /workspace/coverage/default/132.rv_timer_random.3449716008 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 65031010207 ps |
| CPU time | 1424.8 seconds |
| Started | Mar 03 04:14:05 PM PST 24 |
| Finished | Mar 03 04:37:50 PM PST 24 |
| Peak memory | 191368 kb |
| Host | smart-02cac490-073e-49d6-a682-64be50fe143e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449716008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3449716008 |
| Directory | /workspace/132.rv_timer_random/latest |
| Test location | /workspace/coverage/default/137.rv_timer_random.1878935590 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 141749464659 ps |
| CPU time | 81.93 seconds |
| Started | Mar 03 04:14:17 PM PST 24 |
| Finished | Mar 03 04:15:39 PM PST 24 |
| Peak memory | 183184 kb |
| Host | smart-c5f4fe0b-ebe9-4533-8d3d-b4ffe137fe00 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878935590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1878935590 |
| Directory | /workspace/137.rv_timer_random/latest |
| Test location | /workspace/coverage/default/139.rv_timer_random.1580932912 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 141777782865 ps |
| CPU time | 76.85 seconds |
| Started | Mar 03 04:14:16 PM PST 24 |
| Finished | Mar 03 04:15:34 PM PST 24 |
| Peak memory | 183176 kb |
| Host | smart-bcc72fdc-25df-4c1a-adde-9598515784a0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580932912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.1580932912 |
| Directory | /workspace/139.rv_timer_random/latest |
| Test location | /workspace/coverage/default/14.rv_timer_disabled.690888676 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 32854436264 ps |
| CPU time | 53.04 seconds |
| Started | Mar 03 04:08:24 PM PST 24 |
| Finished | Mar 03 04:09:17 PM PST 24 |
| Peak memory | 183176 kb |
| Host | smart-bbf58331-ab1f-4a7e-ad01-283036cdc76f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=690888676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.690888676 |
| Directory | /workspace/14.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/14.rv_timer_stress_all.4031939388 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 1048660684537 ps |
| CPU time | 266.85 seconds |
| Started | Mar 03 04:08:34 PM PST 24 |
| Finished | Mar 03 04:13:01 PM PST 24 |
| Peak memory | 191376 kb |
| Host | smart-ac682cd7-038c-4ab8-8a27-fe0e64d38f25 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031939388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all .4031939388 |
| Directory | /workspace/14.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/140.rv_timer_random.2190632026 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 78142542887 ps |
| CPU time | 146.25 seconds |
| Started | Mar 03 04:14:16 PM PST 24 |
| Finished | Mar 03 04:16:42 PM PST 24 |
| Peak memory | 191400 kb |
| Host | smart-71b0b0dc-1004-43f5-84f7-c578bca59018 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190632026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.2190632026 |
| Directory | /workspace/140.rv_timer_random/latest |
| Test location | /workspace/coverage/default/141.rv_timer_random.2863747999 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 26433240387 ps |
| CPU time | 67.8 seconds |
| Started | Mar 03 04:14:17 PM PST 24 |
| Finished | Mar 03 04:15:25 PM PST 24 |
| Peak memory | 183160 kb |
| Host | smart-5db89d42-e13b-4746-be74-5ba35e39c4d6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863747999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2863747999 |
| Directory | /workspace/141.rv_timer_random/latest |
| Test location | /workspace/coverage/default/142.rv_timer_random.3073635756 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 156668414341 ps |
| CPU time | 143.08 seconds |
| Started | Mar 03 04:14:15 PM PST 24 |
| Finished | Mar 03 04:16:38 PM PST 24 |
| Peak memory | 191408 kb |
| Host | smart-205aeee4-1859-463f-b82d-4ef9ffdb8a0a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073635756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3073635756 |
| Directory | /workspace/142.rv_timer_random/latest |
| Test location | /workspace/coverage/default/143.rv_timer_random.1240752322 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 640939600219 ps |
| CPU time | 906.03 seconds |
| Started | Mar 03 04:14:16 PM PST 24 |
| Finished | Mar 03 04:29:22 PM PST 24 |
| Peak memory | 191420 kb |
| Host | smart-b7b05e19-6c96-4caf-8e72-b044670f03ce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240752322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1240752322 |
| Directory | /workspace/143.rv_timer_random/latest |
| Test location | /workspace/coverage/default/145.rv_timer_random.1687150877 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 384865848389 ps |
| CPU time | 213.45 seconds |
| Started | Mar 03 04:14:16 PM PST 24 |
| Finished | Mar 03 04:17:50 PM PST 24 |
| Peak memory | 191412 kb |
| Host | smart-218f8197-4a14-4b30-9bf0-e330a3be7da0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687150877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1687150877 |
| Directory | /workspace/145.rv_timer_random/latest |
| Test location | /workspace/coverage/default/146.rv_timer_random.1825594562 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 165055067382 ps |
| CPU time | 1247.95 seconds |
| Started | Mar 03 04:14:16 PM PST 24 |
| Finished | Mar 03 04:35:04 PM PST 24 |
| Peak memory | 191388 kb |
| Host | smart-6796dfbf-2394-49af-9380-31834e0ecb31 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825594562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1825594562 |
| Directory | /workspace/146.rv_timer_random/latest |
| Test location | /workspace/coverage/default/147.rv_timer_random.2551248042 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 264948670709 ps |
| CPU time | 163.61 seconds |
| Started | Mar 03 04:14:16 PM PST 24 |
| Finished | Mar 03 04:17:00 PM PST 24 |
| Peak memory | 191388 kb |
| Host | smart-1050007f-a6c0-4e66-9d10-7472e7f6c301 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551248042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2551248042 |
| Directory | /workspace/147.rv_timer_random/latest |
| Test location | /workspace/coverage/default/148.rv_timer_random.125974993 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 1802588892785 ps |
| CPU time | 530.32 seconds |
| Started | Mar 03 04:14:16 PM PST 24 |
| Finished | Mar 03 04:23:07 PM PST 24 |
| Peak memory | 194520 kb |
| Host | smart-2c565fc0-b1d2-4585-830f-87a9d317f18c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125974993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.125974993 |
| Directory | /workspace/148.rv_timer_random/latest |
| Test location | /workspace/coverage/default/149.rv_timer_random.4145979269 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 1276306897810 ps |
| CPU time | 1182.71 seconds |
| Started | Mar 03 04:14:16 PM PST 24 |
| Finished | Mar 03 04:33:59 PM PST 24 |
| Peak memory | 191376 kb |
| Host | smart-1d0dab11-9cd8-4cb2-8d3c-67ca2dfb3798 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145979269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.4145979269 |
| Directory | /workspace/149.rv_timer_random/latest |
| Test location | /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1752344794 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1636054667848 ps |
| CPU time | 986.97 seconds |
| Started | Mar 03 04:08:32 PM PST 24 |
| Finished | Mar 03 04:24:59 PM PST 24 |
| Peak memory | 183208 kb |
| Host | smart-ecadb4e5-b92f-4481-b634-a9998c577327 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752344794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.1752344794 |
| Directory | /workspace/15.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/15.rv_timer_disabled.480398520 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 486777754632 ps |
| CPU time | 221.24 seconds |
| Started | Mar 03 04:08:30 PM PST 24 |
| Finished | Mar 03 04:12:11 PM PST 24 |
| Peak memory | 183164 kb |
| Host | smart-3acd594a-381c-4821-b3b2-11b87fe41047 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=480398520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.480398520 |
| Directory | /workspace/15.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/15.rv_timer_random.2802070416 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 387619832919 ps |
| CPU time | 387.98 seconds |
| Started | Mar 03 04:08:31 PM PST 24 |
| Finished | Mar 03 04:14:59 PM PST 24 |
| Peak memory | 191396 kb |
| Host | smart-52fb1cbb-0626-4805-bc01-a18806eb6715 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802070416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2802070416 |
| Directory | /workspace/15.rv_timer_random/latest |
| Test location | /workspace/coverage/default/15.rv_timer_random_reset.177562383 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 143429843212 ps |
| CPU time | 135.27 seconds |
| Started | Mar 03 04:08:31 PM PST 24 |
| Finished | Mar 03 04:10:47 PM PST 24 |
| Peak memory | 192540 kb |
| Host | smart-a19c7f59-8c94-4518-91a1-3ebc2ab1a6bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=177562383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.177562383 |
| Directory | /workspace/15.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/15.rv_timer_stress_all.648428505 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 192465178921 ps |
| CPU time | 207.92 seconds |
| Started | Mar 03 04:08:37 PM PST 24 |
| Finished | Mar 03 04:12:05 PM PST 24 |
| Peak memory | 191404 kb |
| Host | smart-feb46ed9-64a8-4455-9032-5df44683fdbb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648428505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all. 648428505 |
| Directory | /workspace/15.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/150.rv_timer_random.3817653397 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 114990251431 ps |
| CPU time | 266.26 seconds |
| Started | Mar 03 04:14:24 PM PST 24 |
| Finished | Mar 03 04:18:52 PM PST 24 |
| Peak memory | 193524 kb |
| Host | smart-0831be19-7b72-478f-a8ab-6d00ed6f6b8b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817653397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3817653397 |
| Directory | /workspace/150.rv_timer_random/latest |
| Test location | /workspace/coverage/default/151.rv_timer_random.1667241149 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 78081189241 ps |
| CPU time | 334.27 seconds |
| Started | Mar 03 04:14:24 PM PST 24 |
| Finished | Mar 03 04:20:00 PM PST 24 |
| Peak memory | 191400 kb |
| Host | smart-5687de2d-2f49-43b8-b4be-85232d2b085d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667241149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1667241149 |
| Directory | /workspace/151.rv_timer_random/latest |
| Test location | /workspace/coverage/default/154.rv_timer_random.889386608 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 31324484837 ps |
| CPU time | 207.4 seconds |
| Started | Mar 03 04:14:25 PM PST 24 |
| Finished | Mar 03 04:17:54 PM PST 24 |
| Peak memory | 191380 kb |
| Host | smart-0cc474a4-efab-4dca-812f-dc860ecd7165 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889386608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.889386608 |
| Directory | /workspace/154.rv_timer_random/latest |
| Test location | /workspace/coverage/default/156.rv_timer_random.2204680174 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 61261510380 ps |
| CPU time | 306.35 seconds |
| Started | Mar 03 04:14:26 PM PST 24 |
| Finished | Mar 03 04:19:33 PM PST 24 |
| Peak memory | 191388 kb |
| Host | smart-86791d73-4acb-40a8-bc10-88f150b3fcaf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204680174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2204680174 |
| Directory | /workspace/156.rv_timer_random/latest |
| Test location | /workspace/coverage/default/158.rv_timer_random.348300845 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 50756691107 ps |
| CPU time | 93.69 seconds |
| Started | Mar 03 04:14:25 PM PST 24 |
| Finished | Mar 03 04:16:00 PM PST 24 |
| Peak memory | 195084 kb |
| Host | smart-f6c22421-93c8-4637-b937-e039b883c25f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348300845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.348300845 |
| Directory | /workspace/158.rv_timer_random/latest |
| Test location | /workspace/coverage/default/159.rv_timer_random.2988111390 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 139333631013 ps |
| CPU time | 1886.82 seconds |
| Started | Mar 03 04:14:25 PM PST 24 |
| Finished | Mar 03 04:45:54 PM PST 24 |
| Peak memory | 194472 kb |
| Host | smart-672e8c3f-8bbc-480e-9e77-4e9b8cea5b45 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988111390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2988111390 |
| Directory | /workspace/159.rv_timer_random/latest |
| Test location | /workspace/coverage/default/16.rv_timer_disabled.3007928499 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 219985549921 ps |
| CPU time | 308.65 seconds |
| Started | Mar 03 04:08:36 PM PST 24 |
| Finished | Mar 03 04:13:45 PM PST 24 |
| Peak memory | 183148 kb |
| Host | smart-3e0950ab-901b-4fa5-9ae7-3b386a96327e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3007928499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3007928499 |
| Directory | /workspace/16.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/16.rv_timer_random_reset.1762368821 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 148920777 ps |
| CPU time | 1.33 seconds |
| Started | Mar 03 04:08:37 PM PST 24 |
| Finished | Mar 03 04:08:38 PM PST 24 |
| Peak memory | 191336 kb |
| Host | smart-fe8a0b3e-72cd-4246-907b-fdb6d971ed69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1762368821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1762368821 |
| Directory | /workspace/16.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/161.rv_timer_random.3620025293 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 540137346372 ps |
| CPU time | 200.53 seconds |
| Started | Mar 03 04:14:28 PM PST 24 |
| Finished | Mar 03 04:17:49 PM PST 24 |
| Peak memory | 191384 kb |
| Host | smart-0dfec4b2-9f21-4e3e-94e0-abeca565fe3a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620025293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3620025293 |
| Directory | /workspace/161.rv_timer_random/latest |
| Test location | /workspace/coverage/default/163.rv_timer_random.3275119903 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 252711412499 ps |
| CPU time | 155.58 seconds |
| Started | Mar 03 04:14:28 PM PST 24 |
| Finished | Mar 03 04:17:04 PM PST 24 |
| Peak memory | 191412 kb |
| Host | smart-beccf1c0-f5ba-4bb0-8355-9ebd5064d2f7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275119903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3275119903 |
| Directory | /workspace/163.rv_timer_random/latest |
| Test location | /workspace/coverage/default/165.rv_timer_random.2671721729 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 88208281503 ps |
| CPU time | 83.15 seconds |
| Started | Mar 03 04:14:34 PM PST 24 |
| Finished | Mar 03 04:15:57 PM PST 24 |
| Peak memory | 183184 kb |
| Host | smart-03de9c9d-0926-47b7-9743-88a8a950bb6e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671721729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2671721729 |
| Directory | /workspace/165.rv_timer_random/latest |
| Test location | /workspace/coverage/default/168.rv_timer_random.2265201371 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 51637231628 ps |
| CPU time | 496.88 seconds |
| Started | Mar 03 04:14:35 PM PST 24 |
| Finished | Mar 03 04:22:52 PM PST 24 |
| Peak memory | 183152 kb |
| Host | smart-90d131a0-74fb-4b64-ade5-94e9cfc10c9d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265201371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2265201371 |
| Directory | /workspace/168.rv_timer_random/latest |
| Test location | /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1699996201 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 970229936042 ps |
| CPU time | 288.95 seconds |
| Started | Mar 03 04:08:41 PM PST 24 |
| Finished | Mar 03 04:13:30 PM PST 24 |
| Peak memory | 183220 kb |
| Host | smart-34ed178f-9a18-4132-9904-59ae7b27a079 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699996201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.1699996201 |
| Directory | /workspace/17.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/17.rv_timer_disabled.1370511209 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 153347784458 ps |
| CPU time | 64.64 seconds |
| Started | Mar 03 04:08:42 PM PST 24 |
| Finished | Mar 03 04:09:47 PM PST 24 |
| Peak memory | 183192 kb |
| Host | smart-d77f7cf5-f18a-4a23-87b9-3e86ff688828 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1370511209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1370511209 |
| Directory | /workspace/17.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/17.rv_timer_random_reset.2063992409 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 62878100132 ps |
| CPU time | 323.4 seconds |
| Started | Mar 03 04:08:43 PM PST 24 |
| Finished | Mar 03 04:14:07 PM PST 24 |
| Peak memory | 183144 kb |
| Host | smart-02c61e15-9d6f-49f2-82c9-5a9695b109ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2063992409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2063992409 |
| Directory | /workspace/17.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/170.rv_timer_random.2161418895 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 125269338595 ps |
| CPU time | 1913.2 seconds |
| Started | Mar 03 04:14:35 PM PST 24 |
| Finished | Mar 03 04:46:29 PM PST 24 |
| Peak memory | 191384 kb |
| Host | smart-057b2dbd-b5b8-4f84-990f-fa0ce740220e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161418895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2161418895 |
| Directory | /workspace/170.rv_timer_random/latest |
| Test location | /workspace/coverage/default/171.rv_timer_random.421009095 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 1205437213376 ps |
| CPU time | 313.65 seconds |
| Started | Mar 03 04:14:40 PM PST 24 |
| Finished | Mar 03 04:19:55 PM PST 24 |
| Peak memory | 191388 kb |
| Host | smart-c1d2d183-e21e-4018-b470-72451899a800 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421009095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.421009095 |
| Directory | /workspace/171.rv_timer_random/latest |
| Test location | /workspace/coverage/default/172.rv_timer_random.3139281050 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 71361220166 ps |
| CPU time | 297.31 seconds |
| Started | Mar 03 04:14:41 PM PST 24 |
| Finished | Mar 03 04:19:39 PM PST 24 |
| Peak memory | 192568 kb |
| Host | smart-9182a59d-97e4-4df5-99a0-72061ca74777 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139281050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3139281050 |
| Directory | /workspace/172.rv_timer_random/latest |
| Test location | /workspace/coverage/default/173.rv_timer_random.2644667878 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 59941861924 ps |
| CPU time | 510.95 seconds |
| Started | Mar 03 04:14:46 PM PST 24 |
| Finished | Mar 03 04:23:17 PM PST 24 |
| Peak memory | 191384 kb |
| Host | smart-ce13a22a-c004-466f-a215-13871c6bab0e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644667878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2644667878 |
| Directory | /workspace/173.rv_timer_random/latest |
| Test location | /workspace/coverage/default/174.rv_timer_random.1476561783 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 68450168382 ps |
| CPU time | 169.88 seconds |
| Started | Mar 03 04:14:47 PM PST 24 |
| Finished | Mar 03 04:17:37 PM PST 24 |
| Peak memory | 191592 kb |
| Host | smart-71641fe9-c046-4e7d-b2fb-391a722b7fbb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476561783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.1476561783 |
| Directory | /workspace/174.rv_timer_random/latest |
| Test location | /workspace/coverage/default/175.rv_timer_random.736165208 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 380173856894 ps |
| CPU time | 569.59 seconds |
| Started | Mar 03 04:14:47 PM PST 24 |
| Finished | Mar 03 04:24:17 PM PST 24 |
| Peak memory | 194064 kb |
| Host | smart-889d4781-b2ff-4d35-838b-cda2333acba2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736165208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.736165208 |
| Directory | /workspace/175.rv_timer_random/latest |
| Test location | /workspace/coverage/default/176.rv_timer_random.1310843595 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 897902469828 ps |
| CPU time | 254.65 seconds |
| Started | Mar 03 04:14:46 PM PST 24 |
| Finished | Mar 03 04:19:01 PM PST 24 |
| Peak memory | 191376 kb |
| Host | smart-b454f305-48cb-443d-aa73-decb66ad414c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310843595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1310843595 |
| Directory | /workspace/176.rv_timer_random/latest |
| Test location | /workspace/coverage/default/177.rv_timer_random.2287663659 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 61792356320 ps |
| CPU time | 1041.74 seconds |
| Started | Mar 03 04:14:46 PM PST 24 |
| Finished | Mar 03 04:32:08 PM PST 24 |
| Peak memory | 191408 kb |
| Host | smart-b09583db-8693-4d4c-9790-18dc30cd5a70 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287663659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2287663659 |
| Directory | /workspace/177.rv_timer_random/latest |
| Test location | /workspace/coverage/default/178.rv_timer_random.2732934279 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 479205750279 ps |
| CPU time | 275.78 seconds |
| Started | Mar 03 04:14:49 PM PST 24 |
| Finished | Mar 03 04:19:25 PM PST 24 |
| Peak memory | 191404 kb |
| Host | smart-cdf7a437-5e82-402e-88a1-626bd8a976cb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732934279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2732934279 |
| Directory | /workspace/178.rv_timer_random/latest |
| Test location | /workspace/coverage/default/179.rv_timer_random.3156932824 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 57408558832 ps |
| CPU time | 106.33 seconds |
| Started | Mar 03 04:14:49 PM PST 24 |
| Finished | Mar 03 04:16:35 PM PST 24 |
| Peak memory | 191400 kb |
| Host | smart-a7350a2e-e204-4d3b-a51a-b1996ff56101 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156932824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3156932824 |
| Directory | /workspace/179.rv_timer_random/latest |
| Test location | /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3605845457 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 130913171503 ps |
| CPU time | 254.73 seconds |
| Started | Mar 03 04:08:48 PM PST 24 |
| Finished | Mar 03 04:13:03 PM PST 24 |
| Peak memory | 183140 kb |
| Host | smart-faf15e77-a288-48a8-9c3b-9c3f91b14772 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605845457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_cfg_update_on_fly.3605845457 |
| Directory | /workspace/18.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/18.rv_timer_disabled.1752706754 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 214089112757 ps |
| CPU time | 100.37 seconds |
| Started | Mar 03 04:08:47 PM PST 24 |
| Finished | Mar 03 04:10:27 PM PST 24 |
| Peak memory | 183184 kb |
| Host | smart-779d0902-5124-4c82-9e37-a2b422336250 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1752706754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1752706754 |
| Directory | /workspace/18.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/18.rv_timer_random.1699882089 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 248586322597 ps |
| CPU time | 60.3 seconds |
| Started | Mar 03 04:08:47 PM PST 24 |
| Finished | Mar 03 04:09:47 PM PST 24 |
| Peak memory | 183160 kb |
| Host | smart-f170e9db-35f7-4975-b7d5-e408ea66194b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699882089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1699882089 |
| Directory | /workspace/18.rv_timer_random/latest |
| Test location | /workspace/coverage/default/18.rv_timer_stress_all.1704857921 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 114822407818 ps |
| CPU time | 193.57 seconds |
| Started | Mar 03 04:09:00 PM PST 24 |
| Finished | Mar 03 04:12:15 PM PST 24 |
| Peak memory | 191368 kb |
| Host | smart-19c84821-3aa4-4294-90f2-c75b919790c4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704857921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all .1704857921 |
| Directory | /workspace/18.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/180.rv_timer_random.3715172382 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 19480261858 ps |
| CPU time | 143.48 seconds |
| Started | Mar 03 04:14:47 PM PST 24 |
| Finished | Mar 03 04:17:11 PM PST 24 |
| Peak memory | 183188 kb |
| Host | smart-0949d35f-0ea9-4512-8395-fbb64dc87dea |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715172382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3715172382 |
| Directory | /workspace/180.rv_timer_random/latest |
| Test location | /workspace/coverage/default/181.rv_timer_random.2348902037 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 205164468362 ps |
| CPU time | 1691.87 seconds |
| Started | Mar 03 04:14:55 PM PST 24 |
| Finished | Mar 03 04:43:07 PM PST 24 |
| Peak memory | 195200 kb |
| Host | smart-622f50d0-9290-48e8-93e3-7a898a9f6a71 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348902037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2348902037 |
| Directory | /workspace/181.rv_timer_random/latest |
| Test location | /workspace/coverage/default/183.rv_timer_random.2908067367 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 151124923948 ps |
| CPU time | 76.75 seconds |
| Started | Mar 03 04:14:51 PM PST 24 |
| Finished | Mar 03 04:16:08 PM PST 24 |
| Peak memory | 191420 kb |
| Host | smart-ee9a11f1-33a5-4928-801f-4e920c7a6d67 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908067367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2908067367 |
| Directory | /workspace/183.rv_timer_random/latest |
| Test location | /workspace/coverage/default/185.rv_timer_random.401998313 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 51956067216 ps |
| CPU time | 60.45 seconds |
| Started | Mar 03 04:14:51 PM PST 24 |
| Finished | Mar 03 04:15:52 PM PST 24 |
| Peak memory | 191372 kb |
| Host | smart-228ccd0f-a213-4e78-9cb3-7ca7819111b2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401998313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.401998313 |
| Directory | /workspace/185.rv_timer_random/latest |
| Test location | /workspace/coverage/default/186.rv_timer_random.4076791327 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 15580190295 ps |
| CPU time | 32.65 seconds |
| Started | Mar 03 04:14:52 PM PST 24 |
| Finished | Mar 03 04:15:24 PM PST 24 |
| Peak memory | 191336 kb |
| Host | smart-c0c59e6c-5dd8-4da5-b41a-212e85a48be1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076791327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.4076791327 |
| Directory | /workspace/186.rv_timer_random/latest |
| Test location | /workspace/coverage/default/188.rv_timer_random.2688497510 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 27835632333 ps |
| CPU time | 329.36 seconds |
| Started | Mar 03 04:14:58 PM PST 24 |
| Finished | Mar 03 04:20:27 PM PST 24 |
| Peak memory | 183220 kb |
| Host | smart-25b1499d-c5ab-4fb7-8993-918b98950c49 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688497510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2688497510 |
| Directory | /workspace/188.rv_timer_random/latest |
| Test location | /workspace/coverage/default/189.rv_timer_random.2687144113 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 5507785721 ps |
| CPU time | 22.31 seconds |
| Started | Mar 03 04:14:58 PM PST 24 |
| Finished | Mar 03 04:15:20 PM PST 24 |
| Peak memory | 192724 kb |
| Host | smart-349915f7-44bb-47d6-9aa3-0e661b51df74 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687144113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2687144113 |
| Directory | /workspace/189.rv_timer_random/latest |
| Test location | /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.589088600 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 150732226508 ps |
| CPU time | 132.79 seconds |
| Started | Mar 03 04:09:00 PM PST 24 |
| Finished | Mar 03 04:11:14 PM PST 24 |
| Peak memory | 183216 kb |
| Host | smart-56543d89-52f5-4644-a49e-9df2d77c1353 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589088600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.rv_timer_cfg_update_on_fly.589088600 |
| Directory | /workspace/19.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/19.rv_timer_disabled.1219348934 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 164806759317 ps |
| CPU time | 213.79 seconds |
| Started | Mar 03 04:09:01 PM PST 24 |
| Finished | Mar 03 04:12:35 PM PST 24 |
| Peak memory | 183176 kb |
| Host | smart-e6d144ea-bf28-42ef-b34b-8b9fb37f55fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1219348934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1219348934 |
| Directory | /workspace/19.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/19.rv_timer_random.3967697433 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 329566565107 ps |
| CPU time | 321.16 seconds |
| Started | Mar 03 04:08:59 PM PST 24 |
| Finished | Mar 03 04:14:20 PM PST 24 |
| Peak memory | 191368 kb |
| Host | smart-38c6b516-9604-4c04-88d3-d3d363434247 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967697433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3967697433 |
| Directory | /workspace/19.rv_timer_random/latest |
| Test location | /workspace/coverage/default/19.rv_timer_stress_all.387887506 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 174773661453 ps |
| CPU time | 272.06 seconds |
| Started | Mar 03 04:09:07 PM PST 24 |
| Finished | Mar 03 04:13:39 PM PST 24 |
| Peak memory | 194656 kb |
| Host | smart-f6cd07f4-cf56-4c18-ba99-aa6c7ae90f10 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387887506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all. 387887506 |
| Directory | /workspace/19.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/191.rv_timer_random.395006483 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 782060130997 ps |
| CPU time | 561.36 seconds |
| Started | Mar 03 04:15:07 PM PST 24 |
| Finished | Mar 03 04:24:28 PM PST 24 |
| Peak memory | 191380 kb |
| Host | smart-fbd4f856-cecd-435c-8abd-7735cab851a7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395006483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.395006483 |
| Directory | /workspace/191.rv_timer_random/latest |
| Test location | /workspace/coverage/default/192.rv_timer_random.3911468558 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 92193372651 ps |
| CPU time | 172.92 seconds |
| Started | Mar 03 04:15:03 PM PST 24 |
| Finished | Mar 03 04:17:56 PM PST 24 |
| Peak memory | 191416 kb |
| Host | smart-c123ca3d-c26d-4429-8ca4-5ed30d328749 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911468558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3911468558 |
| Directory | /workspace/192.rv_timer_random/latest |
| Test location | /workspace/coverage/default/193.rv_timer_random.3324055554 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 273815014637 ps |
| CPU time | 254.96 seconds |
| Started | Mar 03 04:15:03 PM PST 24 |
| Finished | Mar 03 04:19:18 PM PST 24 |
| Peak memory | 191380 kb |
| Host | smart-b4c58f48-676b-4575-a8b1-39a077e40213 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324055554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3324055554 |
| Directory | /workspace/193.rv_timer_random/latest |
| Test location | /workspace/coverage/default/195.rv_timer_random.2481337143 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 138783717536 ps |
| CPU time | 264.1 seconds |
| Started | Mar 03 04:15:03 PM PST 24 |
| Finished | Mar 03 04:19:28 PM PST 24 |
| Peak memory | 191396 kb |
| Host | smart-4d1ddd59-0dee-4235-84b4-bafd18e6214e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481337143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2481337143 |
| Directory | /workspace/195.rv_timer_random/latest |
| Test location | /workspace/coverage/default/196.rv_timer_random.3014874911 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 459897300918 ps |
| CPU time | 1253.5 seconds |
| Started | Mar 03 04:15:03 PM PST 24 |
| Finished | Mar 03 04:35:57 PM PST 24 |
| Peak memory | 191404 kb |
| Host | smart-6c406a43-371c-4811-9c63-89732d00e6e1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014874911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3014874911 |
| Directory | /workspace/196.rv_timer_random/latest |
| Test location | /workspace/coverage/default/198.rv_timer_random.1684751748 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1519652757719 ps |
| CPU time | 494.95 seconds |
| Started | Mar 03 04:15:03 PM PST 24 |
| Finished | Mar 03 04:23:18 PM PST 24 |
| Peak memory | 194556 kb |
| Host | smart-c16e23e1-5158-497c-b9ea-411bc3ba3808 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684751748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1684751748 |
| Directory | /workspace/198.rv_timer_random/latest |
| Test location | /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1126422019 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 551095674316 ps |
| CPU time | 295.01 seconds |
| Started | Mar 03 04:07:36 PM PST 24 |
| Finished | Mar 03 04:12:31 PM PST 24 |
| Peak memory | 183224 kb |
| Host | smart-258f1d43-2223-4ffd-a9f9-59380c0d42e8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126422019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_cfg_update_on_fly.1126422019 |
| Directory | /workspace/2.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/2.rv_timer_disabled.3317102765 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 65986971931 ps |
| CPU time | 98.42 seconds |
| Started | Mar 03 04:07:42 PM PST 24 |
| Finished | Mar 03 04:09:21 PM PST 24 |
| Peak memory | 183192 kb |
| Host | smart-d3707dbb-524b-43fb-ac28-987c598bada8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3317102765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3317102765 |
| Directory | /workspace/2.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/2.rv_timer_random_reset.1592610399 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 36098063675 ps |
| CPU time | 243.07 seconds |
| Started | Mar 03 04:07:40 PM PST 24 |
| Finished | Mar 03 04:11:43 PM PST 24 |
| Peak memory | 191388 kb |
| Host | smart-a5917e68-e2fc-4145-a42d-63222c5a162e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1592610399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1592610399 |
| Directory | /workspace/2.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/2.rv_timer_sec_cm.2227649650 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 87526523 ps |
| CPU time | 1.02 seconds |
| Started | Mar 03 04:07:37 PM PST 24 |
| Finished | Mar 03 04:07:38 PM PST 24 |
| Peak memory | 214664 kb |
| Host | smart-fd37c36c-2949-4a3c-964b-2a2b0314d859 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227649650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.2227649650 |
| Directory | /workspace/2.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/2.rv_timer_stress_all.2209147462 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 16160177213 ps |
| CPU time | 21.72 seconds |
| Started | Mar 03 04:07:37 PM PST 24 |
| Finished | Mar 03 04:07:59 PM PST 24 |
| Peak memory | 183204 kb |
| Host | smart-7279b581-29b2-49da-9618-dd7e08d839b6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209147462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all. 2209147462 |
| Directory | /workspace/2.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3452223622 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 1805399950216 ps |
| CPU time | 1236.65 seconds |
| Started | Mar 03 04:09:12 PM PST 24 |
| Finished | Mar 03 04:29:49 PM PST 24 |
| Peak memory | 183200 kb |
| Host | smart-9de8f3fc-4994-41e9-bfe2-65a3e4e7151d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452223622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.3452223622 |
| Directory | /workspace/20.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/20.rv_timer_disabled.4045061095 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 239015336462 ps |
| CPU time | 107.45 seconds |
| Started | Mar 03 04:09:10 PM PST 24 |
| Finished | Mar 03 04:10:58 PM PST 24 |
| Peak memory | 183176 kb |
| Host | smart-181610a3-0872-49e7-b1ea-4fffbf67b2f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4045061095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.4045061095 |
| Directory | /workspace/20.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/20.rv_timer_random.2787683276 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 58557518697 ps |
| CPU time | 433.1 seconds |
| Started | Mar 03 04:09:07 PM PST 24 |
| Finished | Mar 03 04:16:20 PM PST 24 |
| Peak memory | 191384 kb |
| Host | smart-dcae22e5-8e18-43df-b576-cef0a51fa79e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787683276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2787683276 |
| Directory | /workspace/20.rv_timer_random/latest |
| Test location | /workspace/coverage/default/20.rv_timer_random_reset.1480717186 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 46993151768 ps |
| CPU time | 89.37 seconds |
| Started | Mar 03 04:09:14 PM PST 24 |
| Finished | Mar 03 04:10:43 PM PST 24 |
| Peak memory | 191312 kb |
| Host | smart-575fc09e-644d-452c-b10b-8b3e6ae19ae4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1480717186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.1480717186 |
| Directory | /workspace/20.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/21.rv_timer_disabled.2955195518 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 133665353821 ps |
| CPU time | 194.75 seconds |
| Started | Mar 03 04:09:19 PM PST 24 |
| Finished | Mar 03 04:12:34 PM PST 24 |
| Peak memory | 183184 kb |
| Host | smart-037ac08b-a77d-4c5e-9d65-58057b3a61c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2955195518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2955195518 |
| Directory | /workspace/21.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/21.rv_timer_random_reset.3348662422 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 1717830932 ps |
| CPU time | 0.91 seconds |
| Started | Mar 03 04:09:21 PM PST 24 |
| Finished | Mar 03 04:09:22 PM PST 24 |
| Peak memory | 192636 kb |
| Host | smart-de2ec016-affb-44de-b1b9-49b91f303d35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3348662422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3348662422 |
| Directory | /workspace/21.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3139103498 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 127076157365 ps |
| CPU time | 31.85 seconds |
| Started | Mar 03 04:09:26 PM PST 24 |
| Finished | Mar 03 04:09:58 PM PST 24 |
| Peak memory | 183228 kb |
| Host | smart-02e04194-f2e6-4295-8ff6-406f01c476b1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139103498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_cfg_update_on_fly.3139103498 |
| Directory | /workspace/22.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/22.rv_timer_disabled.3911699188 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 994241477819 ps |
| CPU time | 259.44 seconds |
| Started | Mar 03 04:09:27 PM PST 24 |
| Finished | Mar 03 04:13:47 PM PST 24 |
| Peak memory | 183184 kb |
| Host | smart-acb7d4e4-8c46-4443-bcbe-fdf1f01c73e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3911699188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3911699188 |
| Directory | /workspace/22.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/22.rv_timer_random.1695138140 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 105717515819 ps |
| CPU time | 76.34 seconds |
| Started | Mar 03 04:09:25 PM PST 24 |
| Finished | Mar 03 04:10:41 PM PST 24 |
| Peak memory | 191356 kb |
| Host | smart-9fb875e1-cfa9-4793-9259-e497173bb03f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695138140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1695138140 |
| Directory | /workspace/22.rv_timer_random/latest |
| Test location | /workspace/coverage/default/22.rv_timer_random_reset.4215946906 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 1941844929 ps |
| CPU time | 1.36 seconds |
| Started | Mar 03 04:09:32 PM PST 24 |
| Finished | Mar 03 04:09:34 PM PST 24 |
| Peak memory | 182920 kb |
| Host | smart-bf8269a7-0e08-432b-8c9a-a9d60b489ac8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4215946906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.4215946906 |
| Directory | /workspace/22.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/22.rv_timer_stress_all.801893731 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 37840206 ps |
| CPU time | 0.63 seconds |
| Started | Mar 03 04:09:38 PM PST 24 |
| Finished | Mar 03 04:09:39 PM PST 24 |
| Peak memory | 182948 kb |
| Host | smart-bdf52646-ac1e-4fb8-be82-c73a2fbc968e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801893731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all. 801893731 |
| Directory | /workspace/22.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.3013395570 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 87942504362 ps |
| CPU time | 26.13 seconds |
| Started | Mar 03 04:09:38 PM PST 24 |
| Finished | Mar 03 04:10:04 PM PST 24 |
| Peak memory | 183212 kb |
| Host | smart-53122897-66a8-4b78-a4a4-81d1232cf3c5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013395570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.3013395570 |
| Directory | /workspace/23.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/23.rv_timer_disabled.3952510185 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 644606101467 ps |
| CPU time | 240.64 seconds |
| Started | Mar 03 04:09:37 PM PST 24 |
| Finished | Mar 03 04:13:38 PM PST 24 |
| Peak memory | 183164 kb |
| Host | smart-29b632cc-860c-4f50-a616-02a4aefe882b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3952510185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3952510185 |
| Directory | /workspace/23.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/23.rv_timer_random.3900682623 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 389673176538 ps |
| CPU time | 157.3 seconds |
| Started | Mar 03 04:09:45 PM PST 24 |
| Finished | Mar 03 04:12:23 PM PST 24 |
| Peak memory | 193752 kb |
| Host | smart-e74e4988-1c0a-4198-9481-569f4ce39ef5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900682623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3900682623 |
| Directory | /workspace/23.rv_timer_random/latest |
| Test location | /workspace/coverage/default/23.rv_timer_random_reset.2918449350 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 357682284 ps |
| CPU time | 0.74 seconds |
| Started | Mar 03 04:09:43 PM PST 24 |
| Finished | Mar 03 04:09:44 PM PST 24 |
| Peak memory | 182916 kb |
| Host | smart-c2e449dc-95d3-450f-9024-9fbc72c32d55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2918449350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2918449350 |
| Directory | /workspace/23.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1288647423 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 361959943560 ps |
| CPU time | 609.66 seconds |
| Started | Mar 03 04:09:50 PM PST 24 |
| Finished | Mar 03 04:20:00 PM PST 24 |
| Peak memory | 183188 kb |
| Host | smart-0dff1689-b32d-468d-959a-77803f584021 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288647423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_cfg_update_on_fly.1288647423 |
| Directory | /workspace/24.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/24.rv_timer_disabled.454846988 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 36114462036 ps |
| CPU time | 31.54 seconds |
| Started | Mar 03 04:09:50 PM PST 24 |
| Finished | Mar 03 04:10:21 PM PST 24 |
| Peak memory | 183184 kb |
| Host | smart-79ee88cf-0c27-47c7-acea-1a498dbd6dee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=454846988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.454846988 |
| Directory | /workspace/24.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/24.rv_timer_random.290570552 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 81111995392 ps |
| CPU time | 65.19 seconds |
| Started | Mar 03 04:09:50 PM PST 24 |
| Finished | Mar 03 04:10:56 PM PST 24 |
| Peak memory | 183180 kb |
| Host | smart-c550c9c5-4fbe-4f32-93bd-9dbfa8db0e8e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290570552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.290570552 |
| Directory | /workspace/24.rv_timer_random/latest |
| Test location | /workspace/coverage/default/24.rv_timer_random_reset.2361579490 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 45738966828 ps |
| CPU time | 39.2 seconds |
| Started | Mar 03 04:09:50 PM PST 24 |
| Finished | Mar 03 04:10:30 PM PST 24 |
| Peak memory | 183168 kb |
| Host | smart-81642e29-7a1c-401f-b1f3-ef3d2c6e063a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2361579490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2361579490 |
| Directory | /workspace/24.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.4058202149 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 15185869711 ps |
| CPU time | 130.69 seconds |
| Started | Mar 03 04:09:50 PM PST 24 |
| Finished | Mar 03 04:12:00 PM PST 24 |
| Peak memory | 197936 kb |
| Host | smart-ca3ee6f5-8734-43cf-a0a5-15d2630b132b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058202149 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.4058202149 |
| Directory | /workspace/24.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.3771526620 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 834177905106 ps |
| CPU time | 257.81 seconds |
| Started | Mar 03 04:09:58 PM PST 24 |
| Finished | Mar 03 04:14:16 PM PST 24 |
| Peak memory | 183184 kb |
| Host | smart-a4499634-3f33-4d8a-b952-a6c1f6ee13e3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771526620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_cfg_update_on_fly.3771526620 |
| Directory | /workspace/25.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/25.rv_timer_disabled.1231820353 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 109520877276 ps |
| CPU time | 45.65 seconds |
| Started | Mar 03 04:09:55 PM PST 24 |
| Finished | Mar 03 04:10:41 PM PST 24 |
| Peak memory | 183172 kb |
| Host | smart-bd16dc00-1bbf-45f8-b271-351173644ddb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1231820353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1231820353 |
| Directory | /workspace/25.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/25.rv_timer_random.2981003508 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 109139348085 ps |
| CPU time | 289.97 seconds |
| Started | Mar 03 04:09:55 PM PST 24 |
| Finished | Mar 03 04:14:45 PM PST 24 |
| Peak memory | 194580 kb |
| Host | smart-89c59ddc-3cf1-46b0-83f8-07d2bbd3e6fe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981003508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2981003508 |
| Directory | /workspace/25.rv_timer_random/latest |
| Test location | /workspace/coverage/default/25.rv_timer_random_reset.192915027 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 4490595272 ps |
| CPU time | 10.27 seconds |
| Started | Mar 03 04:09:55 PM PST 24 |
| Finished | Mar 03 04:10:06 PM PST 24 |
| Peak memory | 183180 kb |
| Host | smart-238764f5-984f-4255-a216-41b6a3918d7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=192915027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.192915027 |
| Directory | /workspace/25.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/25.rv_timer_stress_all.958892668 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1360246237908 ps |
| CPU time | 313.74 seconds |
| Started | Mar 03 04:10:05 PM PST 24 |
| Finished | Mar 03 04:15:19 PM PST 24 |
| Peak memory | 183224 kb |
| Host | smart-2c807f28-2945-40e0-a493-e26019ff2659 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958892668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all. 958892668 |
| Directory | /workspace/25.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.744374068 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 296040586293 ps |
| CPU time | 575.04 seconds |
| Started | Mar 03 04:10:02 PM PST 24 |
| Finished | Mar 03 04:19:37 PM PST 24 |
| Peak memory | 183208 kb |
| Host | smart-1b9c7d03-a0c8-4be3-b5ce-3f6ae5eea541 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744374068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.rv_timer_cfg_update_on_fly.744374068 |
| Directory | /workspace/26.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/26.rv_timer_disabled.3926483466 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 547411989202 ps |
| CPU time | 247.16 seconds |
| Started | Mar 03 04:10:03 PM PST 24 |
| Finished | Mar 03 04:14:10 PM PST 24 |
| Peak memory | 183196 kb |
| Host | smart-0ce7c3f4-30b9-4e23-975f-7786276b71e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3926483466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3926483466 |
| Directory | /workspace/26.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/26.rv_timer_random.218820360 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1491887384936 ps |
| CPU time | 427.3 seconds |
| Started | Mar 03 04:10:01 PM PST 24 |
| Finished | Mar 03 04:17:09 PM PST 24 |
| Peak memory | 191368 kb |
| Host | smart-90fadaef-5d23-4e5a-8068-6931287f0527 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218820360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.218820360 |
| Directory | /workspace/26.rv_timer_random/latest |
| Test location | /workspace/coverage/default/26.rv_timer_random_reset.1783146650 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1415480207 ps |
| CPU time | 1.23 seconds |
| Started | Mar 03 04:10:08 PM PST 24 |
| Finished | Mar 03 04:10:10 PM PST 24 |
| Peak memory | 193688 kb |
| Host | smart-1caeb554-ac62-46bc-a615-e272f303977f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1783146650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1783146650 |
| Directory | /workspace/26.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1692853651 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 228198291129 ps |
| CPU time | 387.19 seconds |
| Started | Mar 03 04:10:15 PM PST 24 |
| Finished | Mar 03 04:16:43 PM PST 24 |
| Peak memory | 183180 kb |
| Host | smart-921cb20e-1e13-413c-8c15-da9dbfcbb857 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692853651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.1692853651 |
| Directory | /workspace/27.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/27.rv_timer_disabled.2413876921 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 70096969984 ps |
| CPU time | 112.74 seconds |
| Started | Mar 03 04:10:08 PM PST 24 |
| Finished | Mar 03 04:12:01 PM PST 24 |
| Peak memory | 183148 kb |
| Host | smart-336cc5ef-a067-42a8-9eb8-7c2a43e35e9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2413876921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2413876921 |
| Directory | /workspace/27.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/27.rv_timer_random.49553031 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 25186427159 ps |
| CPU time | 6.95 seconds |
| Started | Mar 03 04:10:08 PM PST 24 |
| Finished | Mar 03 04:10:15 PM PST 24 |
| Peak memory | 182988 kb |
| Host | smart-9c201a60-3e05-404f-bbcc-115c64fcc1fe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49553031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.49553031 |
| Directory | /workspace/27.rv_timer_random/latest |
| Test location | /workspace/coverage/default/27.rv_timer_random_reset.1348693194 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 9851080058 ps |
| CPU time | 17.74 seconds |
| Started | Mar 03 04:10:14 PM PST 24 |
| Finished | Mar 03 04:10:33 PM PST 24 |
| Peak memory | 192064 kb |
| Host | smart-769f3111-9561-4be4-845d-0da8956923cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1348693194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1348693194 |
| Directory | /workspace/27.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/27.rv_timer_stress_all.879882055 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 1206890776838 ps |
| CPU time | 935.71 seconds |
| Started | Mar 03 04:10:13 PM PST 24 |
| Finished | Mar 03 04:25:49 PM PST 24 |
| Peak memory | 191348 kb |
| Host | smart-f2f3bb15-f56b-4baf-b9ed-f27fad667f0d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879882055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all. 879882055 |
| Directory | /workspace/27.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1181311242 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 1216881978188 ps |
| CPU time | 684.28 seconds |
| Started | Mar 03 04:10:21 PM PST 24 |
| Finished | Mar 03 04:21:46 PM PST 24 |
| Peak memory | 183124 kb |
| Host | smart-2e3590be-1afd-4cb8-9853-1b2981a7e28b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181311242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_cfg_update_on_fly.1181311242 |
| Directory | /workspace/28.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/28.rv_timer_disabled.4114458286 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 132368446955 ps |
| CPU time | 203.52 seconds |
| Started | Mar 03 04:10:20 PM PST 24 |
| Finished | Mar 03 04:13:44 PM PST 24 |
| Peak memory | 183200 kb |
| Host | smart-e2f5f955-4579-4248-87bc-a93fcab0e19f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4114458286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.4114458286 |
| Directory | /workspace/28.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/28.rv_timer_random_reset.1604295996 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 99359361013 ps |
| CPU time | 108.28 seconds |
| Started | Mar 03 04:10:21 PM PST 24 |
| Finished | Mar 03 04:12:09 PM PST 24 |
| Peak memory | 194536 kb |
| Host | smart-721cfa21-b172-464e-a212-6e23f174f309 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1604295996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1604295996 |
| Directory | /workspace/28.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.845114331 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 61327360674 ps |
| CPU time | 508.89 seconds |
| Started | Mar 03 04:10:20 PM PST 24 |
| Finished | Mar 03 04:18:49 PM PST 24 |
| Peak memory | 206132 kb |
| Host | smart-5e9076b3-8342-444c-9ffb-f72e1c59b900 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845114331 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.845114331 |
| Directory | /workspace/28.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2218473204 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 125603238503 ps |
| CPU time | 211.62 seconds |
| Started | Mar 03 04:10:27 PM PST 24 |
| Finished | Mar 03 04:13:59 PM PST 24 |
| Peak memory | 183204 kb |
| Host | smart-13096b40-33c7-43a1-888d-05a4929420c2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218473204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.2218473204 |
| Directory | /workspace/29.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/29.rv_timer_disabled.1880719388 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 129799857322 ps |
| CPU time | 208.14 seconds |
| Started | Mar 03 04:10:26 PM PST 24 |
| Finished | Mar 03 04:13:54 PM PST 24 |
| Peak memory | 183188 kb |
| Host | smart-8a541e02-a352-46f8-abba-165050cdfeba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1880719388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1880719388 |
| Directory | /workspace/29.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/29.rv_timer_random.924433792 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 225610530668 ps |
| CPU time | 247.3 seconds |
| Started | Mar 03 04:10:29 PM PST 24 |
| Finished | Mar 03 04:14:36 PM PST 24 |
| Peak memory | 191392 kb |
| Host | smart-361b053e-2a13-4f0b-b36f-0dc9ca529b46 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924433792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.924433792 |
| Directory | /workspace/29.rv_timer_random/latest |
| Test location | /workspace/coverage/default/29.rv_timer_random_reset.1068432954 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 34534147628 ps |
| CPU time | 293.34 seconds |
| Started | Mar 03 04:10:25 PM PST 24 |
| Finished | Mar 03 04:15:19 PM PST 24 |
| Peak memory | 183160 kb |
| Host | smart-020fa0f4-a001-4cd9-8847-c672d01ec799 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1068432954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1068432954 |
| Directory | /workspace/29.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/29.rv_timer_stress_all.1936422988 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 71209561 ps |
| CPU time | 0.57 seconds |
| Started | Mar 03 04:10:31 PM PST 24 |
| Finished | Mar 03 04:10:32 PM PST 24 |
| Peak memory | 182952 kb |
| Host | smart-bb87fa9f-5b29-449e-ba63-6ffdb935a86e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936422988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all .1936422988 |
| Directory | /workspace/29.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.631759256 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 206198315064 ps |
| CPU time | 354.76 seconds |
| Started | Mar 03 04:07:41 PM PST 24 |
| Finished | Mar 03 04:13:37 PM PST 24 |
| Peak memory | 183208 kb |
| Host | smart-7487ada9-ea49-41cd-8a40-e97f417f2362 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631759256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .rv_timer_cfg_update_on_fly.631759256 |
| Directory | /workspace/3.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/3.rv_timer_disabled.3141873088 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 147925219043 ps |
| CPU time | 217.39 seconds |
| Started | Mar 03 04:07:41 PM PST 24 |
| Finished | Mar 03 04:11:18 PM PST 24 |
| Peak memory | 183224 kb |
| Host | smart-172c9efe-8d86-449c-ba8c-434b4bd1292f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3141873088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3141873088 |
| Directory | /workspace/3.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/3.rv_timer_random.1006753978 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 91267363752 ps |
| CPU time | 57.97 seconds |
| Started | Mar 03 04:07:58 PM PST 24 |
| Finished | Mar 03 04:08:57 PM PST 24 |
| Peak memory | 183172 kb |
| Host | smart-be8dd33b-e383-4191-b916-1b3bf307c634 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006753978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1006753978 |
| Directory | /workspace/3.rv_timer_random/latest |
| Test location | /workspace/coverage/default/3.rv_timer_random_reset.3745064221 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 74055569282 ps |
| CPU time | 133.58 seconds |
| Started | Mar 03 04:07:43 PM PST 24 |
| Finished | Mar 03 04:09:57 PM PST 24 |
| Peak memory | 191376 kb |
| Host | smart-150f01c5-cf66-49ea-8f44-d702e1dbf8e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3745064221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3745064221 |
| Directory | /workspace/3.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/3.rv_timer_sec_cm.3846927538 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 518165450 ps |
| CPU time | 1.03 seconds |
| Started | Mar 03 04:07:43 PM PST 24 |
| Finished | Mar 03 04:07:44 PM PST 24 |
| Peak memory | 214692 kb |
| Host | smart-7923a99f-d301-4496-94e0-9a0faf0ae802 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846927538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3846927538 |
| Directory | /workspace/3.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/3.rv_timer_stress_all.1198373128 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 916160173872 ps |
| CPU time | 356.78 seconds |
| Started | Mar 03 04:07:42 PM PST 24 |
| Finished | Mar 03 04:13:39 PM PST 24 |
| Peak memory | 191444 kb |
| Host | smart-b1514358-eaee-43b0-bb83-b931863f8d48 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198373128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all. 1198373128 |
| Directory | /workspace/3.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/30.rv_timer_disabled.555598538 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 418952213981 ps |
| CPU time | 150.43 seconds |
| Started | Mar 03 04:10:33 PM PST 24 |
| Finished | Mar 03 04:13:03 PM PST 24 |
| Peak memory | 183188 kb |
| Host | smart-0c6b5eb2-e1a4-4af7-b61f-b691492acbf1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=555598538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.555598538 |
| Directory | /workspace/30.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/30.rv_timer_random.1310106214 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 228120947099 ps |
| CPU time | 901.86 seconds |
| Started | Mar 03 04:10:33 PM PST 24 |
| Finished | Mar 03 04:25:35 PM PST 24 |
| Peak memory | 191368 kb |
| Host | smart-075b60cc-5017-4373-ad1a-2c46d61836d6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310106214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1310106214 |
| Directory | /workspace/30.rv_timer_random/latest |
| Test location | /workspace/coverage/default/30.rv_timer_random_reset.2565454812 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 16959810279 ps |
| CPU time | 19.23 seconds |
| Started | Mar 03 04:10:38 PM PST 24 |
| Finished | Mar 03 04:10:57 PM PST 24 |
| Peak memory | 183184 kb |
| Host | smart-59be9a84-87e6-4e2d-ae3f-d106525ee969 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2565454812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2565454812 |
| Directory | /workspace/30.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.320074203 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 77360634361 ps |
| CPU time | 148.17 seconds |
| Started | Mar 03 04:10:45 PM PST 24 |
| Finished | Mar 03 04:13:14 PM PST 24 |
| Peak memory | 183200 kb |
| Host | smart-838d38f7-c39c-4489-9d1b-321aeb53e12e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320074203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.rv_timer_cfg_update_on_fly.320074203 |
| Directory | /workspace/31.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/31.rv_timer_disabled.855939379 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 89806394992 ps |
| CPU time | 127.61 seconds |
| Started | Mar 03 04:10:44 PM PST 24 |
| Finished | Mar 03 04:12:52 PM PST 24 |
| Peak memory | 183184 kb |
| Host | smart-9017a8df-5873-435f-9ed4-87313bcd4cf4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=855939379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.855939379 |
| Directory | /workspace/31.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/31.rv_timer_random_reset.2408488664 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 17597518663 ps |
| CPU time | 31.4 seconds |
| Started | Mar 03 04:10:45 PM PST 24 |
| Finished | Mar 03 04:11:16 PM PST 24 |
| Peak memory | 183192 kb |
| Host | smart-24e938ef-f832-4351-817b-df4da66316ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2408488664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2408488664 |
| Directory | /workspace/31.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3491334923 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 167858477343 ps |
| CPU time | 249.88 seconds |
| Started | Mar 03 04:10:44 PM PST 24 |
| Finished | Mar 03 04:14:55 PM PST 24 |
| Peak memory | 183204 kb |
| Host | smart-ee8ba152-78d6-4a7b-aa39-043bd7ad9b69 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491334923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_cfg_update_on_fly.3491334923 |
| Directory | /workspace/32.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/32.rv_timer_disabled.68475637 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 39111089842 ps |
| CPU time | 31.23 seconds |
| Started | Mar 03 04:10:44 PM PST 24 |
| Finished | Mar 03 04:11:15 PM PST 24 |
| Peak memory | 183184 kb |
| Host | smart-4c84128e-7d59-4e3b-864d-0947375d7c3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=68475637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.68475637 |
| Directory | /workspace/32.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/32.rv_timer_random.2675311116 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 28961883331 ps |
| CPU time | 73.75 seconds |
| Started | Mar 03 04:10:45 PM PST 24 |
| Finished | Mar 03 04:11:59 PM PST 24 |
| Peak memory | 183176 kb |
| Host | smart-1afacefb-9419-4f5c-8c0d-cf8e87037eef |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675311116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2675311116 |
| Directory | /workspace/32.rv_timer_random/latest |
| Test location | /workspace/coverage/default/32.rv_timer_random_reset.1998784321 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 233201703 ps |
| CPU time | 0.81 seconds |
| Started | Mar 03 04:10:55 PM PST 24 |
| Finished | Mar 03 04:10:56 PM PST 24 |
| Peak memory | 182952 kb |
| Host | smart-e9d04808-14b6-4b2b-9c0a-db1d1a8c27f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1998784321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1998784321 |
| Directory | /workspace/32.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/32.rv_timer_stress_all.1208805187 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 628466975824 ps |
| CPU time | 493.49 seconds |
| Started | Mar 03 04:10:51 PM PST 24 |
| Finished | Mar 03 04:19:05 PM PST 24 |
| Peak memory | 191416 kb |
| Host | smart-5f951731-917b-4ec6-ba89-ccd26f21d600 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208805187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all .1208805187 |
| Directory | /workspace/32.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.4275674508 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 681642110760 ps |
| CPU time | 443.28 seconds |
| Started | Mar 03 04:10:51 PM PST 24 |
| Finished | Mar 03 04:18:14 PM PST 24 |
| Peak memory | 183232 kb |
| Host | smart-2253d225-8396-4516-845b-1b50645b096f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275674508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.4275674508 |
| Directory | /workspace/33.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/33.rv_timer_disabled.2731900454 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 96485041550 ps |
| CPU time | 77.29 seconds |
| Started | Mar 03 04:10:52 PM PST 24 |
| Finished | Mar 03 04:12:09 PM PST 24 |
| Peak memory | 183208 kb |
| Host | smart-734755e0-3e16-4630-96c1-9f22e356fa3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2731900454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2731900454 |
| Directory | /workspace/33.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/33.rv_timer_random_reset.3796027997 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 323828300734 ps |
| CPU time | 176.15 seconds |
| Started | Mar 03 04:10:50 PM PST 24 |
| Finished | Mar 03 04:13:47 PM PST 24 |
| Peak memory | 183160 kb |
| Host | smart-e2d43a9e-3502-43fc-8bf1-33e4bb1d1492 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3796027997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3796027997 |
| Directory | /workspace/33.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/33.rv_timer_stress_all.1749756476 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 4785444960509 ps |
| CPU time | 1076.8 seconds |
| Started | Mar 03 04:10:56 PM PST 24 |
| Finished | Mar 03 04:28:53 PM PST 24 |
| Peak memory | 191472 kb |
| Host | smart-419208da-e169-45db-80b4-ebd57c38fe8a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749756476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all .1749756476 |
| Directory | /workspace/33.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/34.rv_timer_disabled.2499051190 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 89777399508 ps |
| CPU time | 132.45 seconds |
| Started | Mar 03 04:10:58 PM PST 24 |
| Finished | Mar 03 04:13:11 PM PST 24 |
| Peak memory | 183180 kb |
| Host | smart-72793b2f-c08a-43f6-9f2c-b084a19b3ab2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2499051190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2499051190 |
| Directory | /workspace/34.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/34.rv_timer_random.4263397128 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 54889188767 ps |
| CPU time | 85.12 seconds |
| Started | Mar 03 04:10:56 PM PST 24 |
| Finished | Mar 03 04:12:21 PM PST 24 |
| Peak memory | 191368 kb |
| Host | smart-d0635939-17f1-44ca-9bef-5879c1e06129 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263397128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.4263397128 |
| Directory | /workspace/34.rv_timer_random/latest |
| Test location | /workspace/coverage/default/34.rv_timer_random_reset.2320109468 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 33457729712 ps |
| CPU time | 438.18 seconds |
| Started | Mar 03 04:11:03 PM PST 24 |
| Finished | Mar 03 04:18:21 PM PST 24 |
| Peak memory | 183168 kb |
| Host | smart-89aa398f-65f8-44ed-bbe2-cb03f555b190 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2320109468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2320109468 |
| Directory | /workspace/34.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/34.rv_timer_stress_all.2262983701 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 77386437611 ps |
| CPU time | 96.34 seconds |
| Started | Mar 03 04:11:03 PM PST 24 |
| Finished | Mar 03 04:12:40 PM PST 24 |
| Peak memory | 191624 kb |
| Host | smart-6658e78f-d120-461d-b777-f597f013acef |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262983701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all .2262983701 |
| Directory | /workspace/34.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.214427424 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 216403387607 ps |
| CPU time | 206.59 seconds |
| Started | Mar 03 04:11:09 PM PST 24 |
| Finished | Mar 03 04:14:36 PM PST 24 |
| Peak memory | 183212 kb |
| Host | smart-e149d23b-79e6-43cf-8b52-a2faca32d159 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214427424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.rv_timer_cfg_update_on_fly.214427424 |
| Directory | /workspace/35.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/35.rv_timer_disabled.3341378994 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 15409963272 ps |
| CPU time | 26.62 seconds |
| Started | Mar 03 04:11:08 PM PST 24 |
| Finished | Mar 03 04:11:34 PM PST 24 |
| Peak memory | 183184 kb |
| Host | smart-089ccea4-955d-4ae2-b4aa-a954dab382d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3341378994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3341378994 |
| Directory | /workspace/35.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/35.rv_timer_random.3214732753 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 128747484365 ps |
| CPU time | 74.07 seconds |
| Started | Mar 03 04:11:02 PM PST 24 |
| Finished | Mar 03 04:12:17 PM PST 24 |
| Peak memory | 183160 kb |
| Host | smart-aea9b759-27a1-4197-8051-7d702a40c11c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214732753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3214732753 |
| Directory | /workspace/35.rv_timer_random/latest |
| Test location | /workspace/coverage/default/35.rv_timer_random_reset.3345446472 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 36597698 ps |
| CPU time | 0.73 seconds |
| Started | Mar 03 04:11:08 PM PST 24 |
| Finished | Mar 03 04:11:10 PM PST 24 |
| Peak memory | 182864 kb |
| Host | smart-00d142d7-11da-47f3-99da-18b2cdf31ce6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3345446472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3345446472 |
| Directory | /workspace/35.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/35.rv_timer_stress_all.4070167119 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 337697987815 ps |
| CPU time | 572.62 seconds |
| Started | Mar 03 04:11:21 PM PST 24 |
| Finished | Mar 03 04:20:53 PM PST 24 |
| Peak memory | 191400 kb |
| Host | smart-7d97d361-bd7a-4159-aa85-9f6dca9358d9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070167119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all .4070167119 |
| Directory | /workspace/35.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.4053402994 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 146233492648 ps |
| CPU time | 85.45 seconds |
| Started | Mar 03 04:11:21 PM PST 24 |
| Finished | Mar 03 04:12:46 PM PST 24 |
| Peak memory | 183176 kb |
| Host | smart-b12cee4e-b839-4e86-a9c8-f260edc02b99 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053402994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.4053402994 |
| Directory | /workspace/36.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/36.rv_timer_disabled.2842646480 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 303123203263 ps |
| CPU time | 92.77 seconds |
| Started | Mar 03 04:11:22 PM PST 24 |
| Finished | Mar 03 04:12:55 PM PST 24 |
| Peak memory | 183168 kb |
| Host | smart-e899a70b-f6f8-46a6-a74d-c695e366d52b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2842646480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2842646480 |
| Directory | /workspace/36.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/36.rv_timer_random.274638816 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 617297031063 ps |
| CPU time | 417.24 seconds |
| Started | Mar 03 04:11:14 PM PST 24 |
| Finished | Mar 03 04:18:12 PM PST 24 |
| Peak memory | 191364 kb |
| Host | smart-db90e2d2-2323-4d14-85d0-ce175f09465f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274638816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.274638816 |
| Directory | /workspace/36.rv_timer_random/latest |
| Test location | /workspace/coverage/default/36.rv_timer_random_reset.3084857746 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 208511876022 ps |
| CPU time | 556.74 seconds |
| Started | Mar 03 04:11:23 PM PST 24 |
| Finished | Mar 03 04:20:40 PM PST 24 |
| Peak memory | 191372 kb |
| Host | smart-a516fc1d-20b7-42ce-9ca5-931570a8c06d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3084857746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3084857746 |
| Directory | /workspace/36.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/36.rv_timer_stress_all.303855268 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 5514201387664 ps |
| CPU time | 705.4 seconds |
| Started | Mar 03 04:11:23 PM PST 24 |
| Finished | Mar 03 04:23:08 PM PST 24 |
| Peak memory | 191412 kb |
| Host | smart-a3d13753-b67b-408f-bbd5-7ad5de513955 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303855268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all. 303855268 |
| Directory | /workspace/36.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.2132020186 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 100695792772 ps |
| CPU time | 73.9 seconds |
| Started | Mar 03 04:11:22 PM PST 24 |
| Finished | Mar 03 04:12:36 PM PST 24 |
| Peak memory | 183224 kb |
| Host | smart-ff4cc767-c02f-4a67-9c00-041876aa07fd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132020186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.2132020186 |
| Directory | /workspace/37.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/37.rv_timer_random.4151553163 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 213248510719 ps |
| CPU time | 421.51 seconds |
| Started | Mar 03 04:11:21 PM PST 24 |
| Finished | Mar 03 04:18:23 PM PST 24 |
| Peak memory | 194724 kb |
| Host | smart-85bc7f87-3b51-4470-a900-9543fac395cd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151553163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.4151553163 |
| Directory | /workspace/37.rv_timer_random/latest |
| Test location | /workspace/coverage/default/37.rv_timer_random_reset.3885823273 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 20495014799 ps |
| CPU time | 50.72 seconds |
| Started | Mar 03 04:11:28 PM PST 24 |
| Finished | Mar 03 04:12:19 PM PST 24 |
| Peak memory | 183176 kb |
| Host | smart-65dea1c1-c45d-4d4f-b644-ced34da995f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3885823273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3885823273 |
| Directory | /workspace/37.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1292877211 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 14521851947 ps |
| CPU time | 29.71 seconds |
| Started | Mar 03 04:11:37 PM PST 24 |
| Finished | Mar 03 04:12:07 PM PST 24 |
| Peak memory | 183180 kb |
| Host | smart-7939f34c-d17b-4994-a2c7-ed6b976bfe6b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292877211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_cfg_update_on_fly.1292877211 |
| Directory | /workspace/38.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/38.rv_timer_disabled.4055699584 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 88826808024 ps |
| CPU time | 56.52 seconds |
| Started | Mar 03 04:11:34 PM PST 24 |
| Finished | Mar 03 04:12:30 PM PST 24 |
| Peak memory | 183184 kb |
| Host | smart-1bdcc54b-0824-402d-a8d2-1352d5e58d54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4055699584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.4055699584 |
| Directory | /workspace/38.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/38.rv_timer_random_reset.3814857304 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 302023276651 ps |
| CPU time | 126.78 seconds |
| Started | Mar 03 04:11:37 PM PST 24 |
| Finished | Mar 03 04:13:44 PM PST 24 |
| Peak memory | 191388 kb |
| Host | smart-c2c1fe18-a2f8-4e0c-85f1-9766882f407f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3814857304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.3814857304 |
| Directory | /workspace/38.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.3120083070 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 218914848062 ps |
| CPU time | 459.15 seconds |
| Started | Mar 03 04:11:34 PM PST 24 |
| Finished | Mar 03 04:19:14 PM PST 24 |
| Peak memory | 206052 kb |
| Host | smart-969256ea-0b78-4ed5-b5b3-c99418437a20 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120083070 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.3120083070 |
| Directory | /workspace/38.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.4183085107 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 361801742791 ps |
| CPU time | 357.28 seconds |
| Started | Mar 03 04:11:40 PM PST 24 |
| Finished | Mar 03 04:17:38 PM PST 24 |
| Peak memory | 183216 kb |
| Host | smart-ea195f3b-461e-4f51-a8b8-cd7662283082 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183085107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.4183085107 |
| Directory | /workspace/39.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/39.rv_timer_disabled.3113687143 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 59734412140 ps |
| CPU time | 101.29 seconds |
| Started | Mar 03 04:11:40 PM PST 24 |
| Finished | Mar 03 04:13:22 PM PST 24 |
| Peak memory | 183168 kb |
| Host | smart-29beb1ec-d460-4f62-98f8-39dd81ff2d95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3113687143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3113687143 |
| Directory | /workspace/39.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/39.rv_timer_random.1865167581 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 349678003130 ps |
| CPU time | 190.51 seconds |
| Started | Mar 03 04:11:34 PM PST 24 |
| Finished | Mar 03 04:14:45 PM PST 24 |
| Peak memory | 191552 kb |
| Host | smart-425659a8-e5e6-445c-8905-5e70164ee5e1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865167581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1865167581 |
| Directory | /workspace/39.rv_timer_random/latest |
| Test location | /workspace/coverage/default/39.rv_timer_random_reset.3235692600 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 13245614505 ps |
| CPU time | 23.65 seconds |
| Started | Mar 03 04:11:41 PM PST 24 |
| Finished | Mar 03 04:12:05 PM PST 24 |
| Peak memory | 183168 kb |
| Host | smart-2a3c05e8-f3fe-408e-a016-8a0f484ed431 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3235692600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3235692600 |
| Directory | /workspace/39.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/39.rv_timer_stress_all.2585598435 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 493044171311 ps |
| CPU time | 764.89 seconds |
| Started | Mar 03 04:11:40 PM PST 24 |
| Finished | Mar 03 04:24:26 PM PST 24 |
| Peak memory | 196016 kb |
| Host | smart-3602331a-6e6e-4ce1-8a07-9c4c98294808 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585598435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all .2585598435 |
| Directory | /workspace/39.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.3474925898 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 18158622339 ps |
| CPU time | 210.44 seconds |
| Started | Mar 03 04:11:40 PM PST 24 |
| Finished | Mar 03 04:15:11 PM PST 24 |
| Peak memory | 197960 kb |
| Host | smart-0956f820-19a5-4f6c-ad25-17ddd3dd690b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474925898 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.3474925898 |
| Directory | /workspace/39.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1000965296 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1337116280 ps |
| CPU time | 3.03 seconds |
| Started | Mar 03 04:07:43 PM PST 24 |
| Finished | Mar 03 04:07:46 PM PST 24 |
| Peak memory | 182948 kb |
| Host | smart-0ba50199-8f63-450c-bc1b-f7d4ec297ae6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000965296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_cfg_update_on_fly.1000965296 |
| Directory | /workspace/4.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/4.rv_timer_random.1430597632 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 416027560307 ps |
| CPU time | 527.56 seconds |
| Started | Mar 03 04:07:42 PM PST 24 |
| Finished | Mar 03 04:16:30 PM PST 24 |
| Peak memory | 191336 kb |
| Host | smart-42372c4f-490e-4d9a-8497-5ddd73d320f7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430597632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.1430597632 |
| Directory | /workspace/4.rv_timer_random/latest |
| Test location | /workspace/coverage/default/4.rv_timer_random_reset.2921124298 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 714496576 ps |
| CPU time | 1.75 seconds |
| Started | Mar 03 04:07:41 PM PST 24 |
| Finished | Mar 03 04:07:44 PM PST 24 |
| Peak memory | 182344 kb |
| Host | smart-bd68b2c0-03f1-48b3-986a-62fe0b1abe51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2921124298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2921124298 |
| Directory | /workspace/4.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/4.rv_timer_sec_cm.604435561 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 603852757 ps |
| CPU time | 0.87 seconds |
| Started | Mar 03 04:07:41 PM PST 24 |
| Finished | Mar 03 04:07:43 PM PST 24 |
| Peak memory | 213072 kb |
| Host | smart-77dfaec5-d8a4-4b96-9fbb-623524f91e10 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604435561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.604435561 |
| Directory | /workspace/4.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1436287624 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 1304374166252 ps |
| CPU time | 367.66 seconds |
| Started | Mar 03 04:11:48 PM PST 24 |
| Finished | Mar 03 04:17:56 PM PST 24 |
| Peak memory | 183128 kb |
| Host | smart-a104f921-8701-4a6c-9c45-0b028aedb9f3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436287624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.1436287624 |
| Directory | /workspace/40.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/40.rv_timer_disabled.1916313775 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 224728138323 ps |
| CPU time | 178.16 seconds |
| Started | Mar 03 04:11:48 PM PST 24 |
| Finished | Mar 03 04:14:46 PM PST 24 |
| Peak memory | 183144 kb |
| Host | smart-287bdb46-c888-49e8-ab25-7934efc881c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1916313775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1916313775 |
| Directory | /workspace/40.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/40.rv_timer_random.1036816965 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 230583440166 ps |
| CPU time | 358.34 seconds |
| Started | Mar 03 04:11:49 PM PST 24 |
| Finished | Mar 03 04:17:48 PM PST 24 |
| Peak memory | 194476 kb |
| Host | smart-16fde2c4-091f-4e86-a4b3-c759f0a61448 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036816965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1036816965 |
| Directory | /workspace/40.rv_timer_random/latest |
| Test location | /workspace/coverage/default/40.rv_timer_random_reset.1821073678 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 243308362634 ps |
| CPU time | 1037.35 seconds |
| Started | Mar 03 04:11:48 PM PST 24 |
| Finished | Mar 03 04:29:05 PM PST 24 |
| Peak memory | 191396 kb |
| Host | smart-58e2590b-d523-486d-b1f8-545e5f28e0f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1821073678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1821073678 |
| Directory | /workspace/40.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/40.rv_timer_stress_all.3128634947 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 429803623145 ps |
| CPU time | 925 seconds |
| Started | Mar 03 04:11:53 PM PST 24 |
| Finished | Mar 03 04:27:18 PM PST 24 |
| Peak memory | 191280 kb |
| Host | smart-34bba95a-d510-41ad-ad98-c92d0817d76c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128634947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all .3128634947 |
| Directory | /workspace/40.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2829060008 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 592026109610 ps |
| CPU time | 319.29 seconds |
| Started | Mar 03 04:11:54 PM PST 24 |
| Finished | Mar 03 04:17:13 PM PST 24 |
| Peak memory | 183196 kb |
| Host | smart-caf97c73-ddd7-4e9f-b5aa-90eed32d408a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829060008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.2829060008 |
| Directory | /workspace/41.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/41.rv_timer_disabled.1975603359 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 128054886711 ps |
| CPU time | 97.9 seconds |
| Started | Mar 03 04:11:52 PM PST 24 |
| Finished | Mar 03 04:13:30 PM PST 24 |
| Peak memory | 183152 kb |
| Host | smart-2c6c1e63-28a1-4942-b4c9-45a19ea2a4ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1975603359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1975603359 |
| Directory | /workspace/41.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/41.rv_timer_random.1784985193 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 134550105172 ps |
| CPU time | 472.17 seconds |
| Started | Mar 03 04:11:52 PM PST 24 |
| Finished | Mar 03 04:19:44 PM PST 24 |
| Peak memory | 193500 kb |
| Host | smart-9e20ad23-b83d-4a46-9e61-888b3b4d1604 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784985193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1784985193 |
| Directory | /workspace/41.rv_timer_random/latest |
| Test location | /workspace/coverage/default/41.rv_timer_random_reset.3644642621 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 162184439095 ps |
| CPU time | 74.01 seconds |
| Started | Mar 03 04:11:52 PM PST 24 |
| Finished | Mar 03 04:13:06 PM PST 24 |
| Peak memory | 183108 kb |
| Host | smart-e8f2d07f-da07-4743-ba5c-0b80d1b1f274 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3644642621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3644642621 |
| Directory | /workspace/41.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/41.rv_timer_stress_all.511393153 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 257006266899 ps |
| CPU time | 219.15 seconds |
| Started | Mar 03 04:11:52 PM PST 24 |
| Finished | Mar 03 04:15:31 PM PST 24 |
| Peak memory | 194892 kb |
| Host | smart-382bad73-6995-4cf1-b595-db54f1aaf406 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511393153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all. 511393153 |
| Directory | /workspace/41.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3649618558 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 443066477199 ps |
| CPU time | 255.04 seconds |
| Started | Mar 03 04:12:00 PM PST 24 |
| Finished | Mar 03 04:16:15 PM PST 24 |
| Peak memory | 183228 kb |
| Host | smart-d43eb698-79ec-4c6f-b6d1-5f8a124e831d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649618558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.3649618558 |
| Directory | /workspace/42.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/42.rv_timer_disabled.165140354 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 69983167101 ps |
| CPU time | 100.75 seconds |
| Started | Mar 03 04:12:00 PM PST 24 |
| Finished | Mar 03 04:13:41 PM PST 24 |
| Peak memory | 183160 kb |
| Host | smart-6f36813e-8eb9-45af-83a6-fcd600922da2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=165140354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.165140354 |
| Directory | /workspace/42.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/42.rv_timer_random.2051199425 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 152964900838 ps |
| CPU time | 1298.2 seconds |
| Started | Mar 03 04:12:00 PM PST 24 |
| Finished | Mar 03 04:33:39 PM PST 24 |
| Peak memory | 191364 kb |
| Host | smart-e854a589-9c49-432d-bcee-aa0664ab8873 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051199425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2051199425 |
| Directory | /workspace/42.rv_timer_random/latest |
| Test location | /workspace/coverage/default/42.rv_timer_random_reset.1574463780 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 1056506549 ps |
| CPU time | 2.54 seconds |
| Started | Mar 03 04:12:00 PM PST 24 |
| Finished | Mar 03 04:12:02 PM PST 24 |
| Peak memory | 183128 kb |
| Host | smart-0283c306-62c5-4ee9-8764-ccb0a3db609a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1574463780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1574463780 |
| Directory | /workspace/42.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/42.rv_timer_stress_all.2856440966 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 1195985652124 ps |
| CPU time | 590.75 seconds |
| Started | Mar 03 04:12:06 PM PST 24 |
| Finished | Mar 03 04:21:57 PM PST 24 |
| Peak memory | 191388 kb |
| Host | smart-f04f88f3-cedb-41f8-86db-dcfc3fcdbbd0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856440966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all .2856440966 |
| Directory | /workspace/42.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2944428281 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 1672540988142 ps |
| CPU time | 921.23 seconds |
| Started | Mar 03 04:12:04 PM PST 24 |
| Finished | Mar 03 04:27:26 PM PST 24 |
| Peak memory | 183192 kb |
| Host | smart-6557d4ca-67e9-43e9-9556-aafbc0a44101 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944428281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.2944428281 |
| Directory | /workspace/43.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/43.rv_timer_disabled.4160431654 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 148830501125 ps |
| CPU time | 211.71 seconds |
| Started | Mar 03 04:12:06 PM PST 24 |
| Finished | Mar 03 04:15:37 PM PST 24 |
| Peak memory | 183076 kb |
| Host | smart-092d0180-ed63-44d8-80d6-a5ccfd7787cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4160431654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.4160431654 |
| Directory | /workspace/43.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/43.rv_timer_random.885150222 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 52207371310 ps |
| CPU time | 101.26 seconds |
| Started | Mar 03 04:12:09 PM PST 24 |
| Finished | Mar 03 04:13:51 PM PST 24 |
| Peak memory | 193532 kb |
| Host | smart-e6ff6291-d9a8-4ec2-9c4c-a47ad93e5db0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885150222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.885150222 |
| Directory | /workspace/43.rv_timer_random/latest |
| Test location | /workspace/coverage/default/43.rv_timer_random_reset.4184079308 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 91991346625 ps |
| CPU time | 321.24 seconds |
| Started | Mar 03 04:12:07 PM PST 24 |
| Finished | Mar 03 04:17:29 PM PST 24 |
| Peak memory | 191372 kb |
| Host | smart-17b80e8a-26f2-4fe8-98f1-043c85f80a24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4184079308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.4184079308 |
| Directory | /workspace/43.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/43.rv_timer_stress_all.3881005607 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 288926880753 ps |
| CPU time | 133.92 seconds |
| Started | Mar 03 04:12:11 PM PST 24 |
| Finished | Mar 03 04:14:25 PM PST 24 |
| Peak memory | 183192 kb |
| Host | smart-ddb5a6aa-4c13-404e-8620-7daf3ab816aa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881005607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all .3881005607 |
| Directory | /workspace/43.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.161125102 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 11111536424 ps |
| CPU time | 7.41 seconds |
| Started | Mar 03 04:12:12 PM PST 24 |
| Finished | Mar 03 04:12:19 PM PST 24 |
| Peak memory | 183124 kb |
| Host | smart-b60fdd6d-e1cd-42a1-8b30-d8feb3eceeb2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161125102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.rv_timer_cfg_update_on_fly.161125102 |
| Directory | /workspace/44.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/44.rv_timer_random.2786805476 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 395609040746 ps |
| CPU time | 765.08 seconds |
| Started | Mar 03 04:12:11 PM PST 24 |
| Finished | Mar 03 04:24:56 PM PST 24 |
| Peak memory | 193888 kb |
| Host | smart-ab7dbaa2-2041-4da9-ad33-a4af33836319 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786805476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2786805476 |
| Directory | /workspace/44.rv_timer_random/latest |
| Test location | /workspace/coverage/default/44.rv_timer_random_reset.4021165012 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 127438187 ps |
| CPU time | 0.59 seconds |
| Started | Mar 03 04:12:11 PM PST 24 |
| Finished | Mar 03 04:12:11 PM PST 24 |
| Peak memory | 182948 kb |
| Host | smart-3e21ee47-6efb-4b1c-8759-7d83f75e8546 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4021165012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.4021165012 |
| Directory | /workspace/44.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.889022067 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 187534440917 ps |
| CPU time | 96.56 seconds |
| Started | Mar 03 04:12:22 PM PST 24 |
| Finished | Mar 03 04:13:59 PM PST 24 |
| Peak memory | 183196 kb |
| Host | smart-854ddc34-c401-49a9-88ac-cfcfca097bb2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889022067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.rv_timer_cfg_update_on_fly.889022067 |
| Directory | /workspace/45.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/45.rv_timer_disabled.558127398 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 216688005024 ps |
| CPU time | 157.11 seconds |
| Started | Mar 03 04:12:17 PM PST 24 |
| Finished | Mar 03 04:14:55 PM PST 24 |
| Peak memory | 183188 kb |
| Host | smart-343dbb16-0931-4a05-97b2-958e967aca1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=558127398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.558127398 |
| Directory | /workspace/45.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/45.rv_timer_random.2460603031 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 17491343982 ps |
| CPU time | 11.29 seconds |
| Started | Mar 03 04:12:22 PM PST 24 |
| Finished | Mar 03 04:12:34 PM PST 24 |
| Peak memory | 183172 kb |
| Host | smart-90e644b0-20ce-461f-8562-1d9259689e7a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460603031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2460603031 |
| Directory | /workspace/45.rv_timer_random/latest |
| Test location | /workspace/coverage/default/45.rv_timer_random_reset.1828083297 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 347343315 ps |
| CPU time | 1.59 seconds |
| Started | Mar 03 04:12:22 PM PST 24 |
| Finished | Mar 03 04:12:24 PM PST 24 |
| Peak memory | 193856 kb |
| Host | smart-4d3b9faa-b582-4970-a54d-2ff1e995ca2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1828083297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1828083297 |
| Directory | /workspace/45.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2812268115 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1267265150696 ps |
| CPU time | 737.19 seconds |
| Started | Mar 03 04:12:33 PM PST 24 |
| Finished | Mar 03 04:24:50 PM PST 24 |
| Peak memory | 183240 kb |
| Host | smart-1c1c15fd-3ffd-4ac2-b810-83324e32c396 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812268115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_cfg_update_on_fly.2812268115 |
| Directory | /workspace/46.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/46.rv_timer_disabled.3549079327 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 109808011929 ps |
| CPU time | 169.36 seconds |
| Started | Mar 03 04:12:33 PM PST 24 |
| Finished | Mar 03 04:15:22 PM PST 24 |
| Peak memory | 183176 kb |
| Host | smart-66977afa-ebfc-46e9-b60c-5786d86a6732 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3549079327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3549079327 |
| Directory | /workspace/46.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/46.rv_timer_random_reset.111039243 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 24130567393 ps |
| CPU time | 41.33 seconds |
| Started | Mar 03 04:12:29 PM PST 24 |
| Finished | Mar 03 04:13:10 PM PST 24 |
| Peak memory | 183184 kb |
| Host | smart-f3489bc5-b773-45de-b93a-53652753df88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=111039243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.111039243 |
| Directory | /workspace/46.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/46.rv_timer_stress_all.1781652954 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 285349070510 ps |
| CPU time | 548.31 seconds |
| Started | Mar 03 04:12:39 PM PST 24 |
| Finished | Mar 03 04:21:47 PM PST 24 |
| Peak memory | 195744 kb |
| Host | smart-48e6009a-54d6-496f-9cde-4628e083a581 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781652954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all .1781652954 |
| Directory | /workspace/46.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.770051099 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 117429644761 ps |
| CPU time | 232.21 seconds |
| Started | Mar 03 04:12:35 PM PST 24 |
| Finished | Mar 03 04:16:27 PM PST 24 |
| Peak memory | 183100 kb |
| Host | smart-0c5d0c1c-aae6-4f54-b999-26f340e11158 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770051099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.rv_timer_cfg_update_on_fly.770051099 |
| Directory | /workspace/47.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/47.rv_timer_disabled.2886797313 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 626646916443 ps |
| CPU time | 102.02 seconds |
| Started | Mar 03 04:12:34 PM PST 24 |
| Finished | Mar 03 04:14:16 PM PST 24 |
| Peak memory | 183208 kb |
| Host | smart-2019aca6-7b80-4c1c-a799-25d022983c46 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2886797313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2886797313 |
| Directory | /workspace/47.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/47.rv_timer_random.752121805 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 116550638530 ps |
| CPU time | 589.29 seconds |
| Started | Mar 03 04:12:36 PM PST 24 |
| Finished | Mar 03 04:22:26 PM PST 24 |
| Peak memory | 193240 kb |
| Host | smart-9783a894-94c3-426e-a0b6-70f50ce44b4b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752121805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.752121805 |
| Directory | /workspace/47.rv_timer_random/latest |
| Test location | /workspace/coverage/default/47.rv_timer_random_reset.3816596006 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 112417721259 ps |
| CPU time | 139.73 seconds |
| Started | Mar 03 04:12:35 PM PST 24 |
| Finished | Mar 03 04:14:55 PM PST 24 |
| Peak memory | 183160 kb |
| Host | smart-9ceaf96b-7d55-45ff-bc13-2f00995ad86c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3816596006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3816596006 |
| Directory | /workspace/47.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/48.rv_timer_disabled.3416794102 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 307885165966 ps |
| CPU time | 129.48 seconds |
| Started | Mar 03 04:12:41 PM PST 24 |
| Finished | Mar 03 04:14:50 PM PST 24 |
| Peak memory | 183180 kb |
| Host | smart-c9b22bbb-3113-40fb-aad8-569efd608749 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3416794102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3416794102 |
| Directory | /workspace/48.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/48.rv_timer_random.951154242 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 53063570619 ps |
| CPU time | 346.84 seconds |
| Started | Mar 03 04:12:40 PM PST 24 |
| Finished | Mar 03 04:18:27 PM PST 24 |
| Peak memory | 191384 kb |
| Host | smart-18bf37cb-42e1-470e-80ea-53dd80141222 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951154242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.951154242 |
| Directory | /workspace/48.rv_timer_random/latest |
| Test location | /workspace/coverage/default/48.rv_timer_random_reset.2743911652 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 82412040827 ps |
| CPU time | 34.56 seconds |
| Started | Mar 03 04:12:41 PM PST 24 |
| Finished | Mar 03 04:13:15 PM PST 24 |
| Peak memory | 191384 kb |
| Host | smart-fba73ddc-da76-4ae8-a341-20fb85814861 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2743911652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2743911652 |
| Directory | /workspace/48.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/48.rv_timer_stress_all.1672101884 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 935704601226 ps |
| CPU time | 426.41 seconds |
| Started | Mar 03 04:12:40 PM PST 24 |
| Finished | Mar 03 04:19:46 PM PST 24 |
| Peak memory | 196492 kb |
| Host | smart-d55b9ca5-cbd8-4285-b667-e1431b7ab5c4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672101884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all .1672101884 |
| Directory | /workspace/48.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1176690185 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1244800318900 ps |
| CPU time | 784.05 seconds |
| Started | Mar 03 04:12:46 PM PST 24 |
| Finished | Mar 03 04:25:50 PM PST 24 |
| Peak memory | 183220 kb |
| Host | smart-d4648176-30db-4c40-bc4a-0340b70b2ead |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176690185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.1176690185 |
| Directory | /workspace/49.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/49.rv_timer_disabled.1774758022 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 150405105909 ps |
| CPU time | 58.55 seconds |
| Started | Mar 03 04:12:40 PM PST 24 |
| Finished | Mar 03 04:13:39 PM PST 24 |
| Peak memory | 183192 kb |
| Host | smart-34a69a82-1949-41fd-85c1-a7b95e9259e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1774758022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1774758022 |
| Directory | /workspace/49.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/49.rv_timer_random_reset.3303553934 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 464881166877 ps |
| CPU time | 667.7 seconds |
| Started | Mar 03 04:12:48 PM PST 24 |
| Finished | Mar 03 04:23:56 PM PST 24 |
| Peak memory | 191364 kb |
| Host | smart-23ff655a-11f9-48c0-a140-60ea014ac596 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3303553934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3303553934 |
| Directory | /workspace/49.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.922983463 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 94633129074 ps |
| CPU time | 422.3 seconds |
| Started | Mar 03 04:12:47 PM PST 24 |
| Finished | Mar 03 04:19:50 PM PST 24 |
| Peak memory | 197876 kb |
| Host | smart-19dfce2b-36d8-4e28-920a-ccb056970c0c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922983463 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.922983463 |
| Directory | /workspace/49.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.rv_timer_disabled.1647171221 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 45154977056 ps |
| CPU time | 74.72 seconds |
| Started | Mar 03 04:07:47 PM PST 24 |
| Finished | Mar 03 04:09:02 PM PST 24 |
| Peak memory | 183180 kb |
| Host | smart-24cc3b92-6bfa-41ab-ad58-a85e810da06e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1647171221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1647171221 |
| Directory | /workspace/5.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/5.rv_timer_random.1945940762 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 179924944608 ps |
| CPU time | 104.25 seconds |
| Started | Mar 03 04:07:45 PM PST 24 |
| Finished | Mar 03 04:09:29 PM PST 24 |
| Peak memory | 191388 kb |
| Host | smart-b39d6e1e-0ffa-409d-a049-448e34482213 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945940762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1945940762 |
| Directory | /workspace/5.rv_timer_random/latest |
| Test location | /workspace/coverage/default/5.rv_timer_random_reset.3880543307 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 225771428696 ps |
| CPU time | 352.22 seconds |
| Started | Mar 03 04:07:45 PM PST 24 |
| Finished | Mar 03 04:13:38 PM PST 24 |
| Peak memory | 183160 kb |
| Host | smart-1d4656b8-8762-4ee3-82c5-ba9401341833 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3880543307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3880543307 |
| Directory | /workspace/5.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/5.rv_timer_stress_all.1904775301 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 170891662578 ps |
| CPU time | 325.39 seconds |
| Started | Mar 03 04:07:45 PM PST 24 |
| Finished | Mar 03 04:13:10 PM PST 24 |
| Peak memory | 195972 kb |
| Host | smart-cda768f7-e68b-4f69-9855-f789169ad743 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904775301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all. 1904775301 |
| Directory | /workspace/5.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/50.rv_timer_random.914919196 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 333186698098 ps |
| CPU time | 1277.54 seconds |
| Started | Mar 03 04:12:47 PM PST 24 |
| Finished | Mar 03 04:34:05 PM PST 24 |
| Peak memory | 191364 kb |
| Host | smart-79e6dedb-0526-4958-8699-b622a9bcfa43 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914919196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.914919196 |
| Directory | /workspace/50.rv_timer_random/latest |
| Test location | /workspace/coverage/default/51.rv_timer_random.3154769730 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 217984042886 ps |
| CPU time | 916.22 seconds |
| Started | Mar 03 04:12:54 PM PST 24 |
| Finished | Mar 03 04:28:10 PM PST 24 |
| Peak memory | 191376 kb |
| Host | smart-daaf31fa-f924-4e81-b375-9f61bda887a3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154769730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3154769730 |
| Directory | /workspace/51.rv_timer_random/latest |
| Test location | /workspace/coverage/default/53.rv_timer_random.2577197661 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 527266724670 ps |
| CPU time | 333.09 seconds |
| Started | Mar 03 04:12:58 PM PST 24 |
| Finished | Mar 03 04:18:31 PM PST 24 |
| Peak memory | 191384 kb |
| Host | smart-13a71a29-93f6-4dc4-9da7-a8af53d53544 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577197661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2577197661 |
| Directory | /workspace/53.rv_timer_random/latest |
| Test location | /workspace/coverage/default/54.rv_timer_random.571760344 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 429574132991 ps |
| CPU time | 352.35 seconds |
| Started | Mar 03 04:12:58 PM PST 24 |
| Finished | Mar 03 04:18:50 PM PST 24 |
| Peak memory | 191388 kb |
| Host | smart-e0f1d1dc-f9a2-4180-8883-3077b4bf2346 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571760344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.571760344 |
| Directory | /workspace/54.rv_timer_random/latest |
| Test location | /workspace/coverage/default/56.rv_timer_random.605580369 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 427530808700 ps |
| CPU time | 733.58 seconds |
| Started | Mar 03 04:12:58 PM PST 24 |
| Finished | Mar 03 04:25:12 PM PST 24 |
| Peak memory | 191384 kb |
| Host | smart-65243884-f116-4b1b-b03a-49cef59d432d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605580369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.605580369 |
| Directory | /workspace/56.rv_timer_random/latest |
| Test location | /workspace/coverage/default/57.rv_timer_random.948643419 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 611058386180 ps |
| CPU time | 810.03 seconds |
| Started | Mar 03 04:12:58 PM PST 24 |
| Finished | Mar 03 04:26:29 PM PST 24 |
| Peak memory | 191384 kb |
| Host | smart-1b0ec339-4c84-4ee2-bad4-1bcdc01d0903 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948643419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.948643419 |
| Directory | /workspace/57.rv_timer_random/latest |
| Test location | /workspace/coverage/default/58.rv_timer_random.1066458792 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 303415551399 ps |
| CPU time | 1342.41 seconds |
| Started | Mar 03 04:12:58 PM PST 24 |
| Finished | Mar 03 04:35:20 PM PST 24 |
| Peak memory | 191360 kb |
| Host | smart-7c80fc81-313b-44c7-88f0-90fac21236e4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066458792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1066458792 |
| Directory | /workspace/58.rv_timer_random/latest |
| Test location | /workspace/coverage/default/59.rv_timer_random.1704226047 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 661293401600 ps |
| CPU time | 611.17 seconds |
| Started | Mar 03 04:12:58 PM PST 24 |
| Finished | Mar 03 04:23:10 PM PST 24 |
| Peak memory | 191372 kb |
| Host | smart-656528d8-a641-4127-aca4-fa34bb4f0e3b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704226047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1704226047 |
| Directory | /workspace/59.rv_timer_random/latest |
| Test location | /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.2913563521 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 301604889542 ps |
| CPU time | 173.26 seconds |
| Started | Mar 03 04:07:46 PM PST 24 |
| Finished | Mar 03 04:10:40 PM PST 24 |
| Peak memory | 183228 kb |
| Host | smart-5a468d65-9c56-426e-b085-a07b2396fdd2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913563521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.2913563521 |
| Directory | /workspace/6.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/6.rv_timer_disabled.2051891448 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 57022385691 ps |
| CPU time | 97.63 seconds |
| Started | Mar 03 04:07:46 PM PST 24 |
| Finished | Mar 03 04:09:24 PM PST 24 |
| Peak memory | 183104 kb |
| Host | smart-09abe9af-7bcd-42b2-861a-1ae556cbb5a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2051891448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2051891448 |
| Directory | /workspace/6.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/6.rv_timer_random.3181513443 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 173049347495 ps |
| CPU time | 205.58 seconds |
| Started | Mar 03 04:07:46 PM PST 24 |
| Finished | Mar 03 04:11:12 PM PST 24 |
| Peak memory | 183172 kb |
| Host | smart-63f132d2-0c47-49ef-9248-7286bc1f2438 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181513443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3181513443 |
| Directory | /workspace/6.rv_timer_random/latest |
| Test location | /workspace/coverage/default/6.rv_timer_random_reset.1008053071 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 43004768481 ps |
| CPU time | 75.52 seconds |
| Started | Mar 03 04:07:43 PM PST 24 |
| Finished | Mar 03 04:08:59 PM PST 24 |
| Peak memory | 183192 kb |
| Host | smart-7ed1fb01-d04f-4f12-bca5-22001a888bc4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1008053071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1008053071 |
| Directory | /workspace/6.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/6.rv_timer_stress_all.4254579032 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 57986306 ps |
| CPU time | 0.59 seconds |
| Started | Mar 03 04:07:45 PM PST 24 |
| Finished | Mar 03 04:07:46 PM PST 24 |
| Peak memory | 182136 kb |
| Host | smart-e9e91988-05ee-4a0f-b5e0-be6442a860e5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254579032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all. 4254579032 |
| Directory | /workspace/6.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/60.rv_timer_random.1578079872 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 32278366704 ps |
| CPU time | 223.76 seconds |
| Started | Mar 03 04:12:59 PM PST 24 |
| Finished | Mar 03 04:16:43 PM PST 24 |
| Peak memory | 191384 kb |
| Host | smart-7874bb73-3925-461d-b9d4-824e82c71b5c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578079872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.1578079872 |
| Directory | /workspace/60.rv_timer_random/latest |
| Test location | /workspace/coverage/default/61.rv_timer_random.3407527319 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 27305266626 ps |
| CPU time | 24.69 seconds |
| Started | Mar 03 04:12:57 PM PST 24 |
| Finished | Mar 03 04:13:22 PM PST 24 |
| Peak memory | 183188 kb |
| Host | smart-bb31a95c-6c44-4202-8304-6d51fa563d8b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407527319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3407527319 |
| Directory | /workspace/61.rv_timer_random/latest |
| Test location | /workspace/coverage/default/62.rv_timer_random.3775544791 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 89654238665 ps |
| CPU time | 43.6 seconds |
| Started | Mar 03 04:12:59 PM PST 24 |
| Finished | Mar 03 04:13:42 PM PST 24 |
| Peak memory | 183184 kb |
| Host | smart-d2b0756b-c7f8-4a79-ad59-60aaf898e0f7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775544791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3775544791 |
| Directory | /workspace/62.rv_timer_random/latest |
| Test location | /workspace/coverage/default/63.rv_timer_random.1053102684 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 80934357010 ps |
| CPU time | 109.58 seconds |
| Started | Mar 03 04:12:58 PM PST 24 |
| Finished | Mar 03 04:14:47 PM PST 24 |
| Peak memory | 183168 kb |
| Host | smart-878bdacc-6823-4f78-84aa-4034a2e99de0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053102684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1053102684 |
| Directory | /workspace/63.rv_timer_random/latest |
| Test location | /workspace/coverage/default/64.rv_timer_random.3936979814 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 60792043537 ps |
| CPU time | 340.48 seconds |
| Started | Mar 03 04:12:57 PM PST 24 |
| Finished | Mar 03 04:18:38 PM PST 24 |
| Peak memory | 191376 kb |
| Host | smart-3a80b184-22a1-4d3f-b2c9-19ae37d84940 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936979814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3936979814 |
| Directory | /workspace/64.rv_timer_random/latest |
| Test location | /workspace/coverage/default/65.rv_timer_random.3469041712 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 80755766268 ps |
| CPU time | 143.97 seconds |
| Started | Mar 03 04:13:04 PM PST 24 |
| Finished | Mar 03 04:15:28 PM PST 24 |
| Peak memory | 191372 kb |
| Host | smart-6e91f8e1-f020-4ccd-b912-74eb0af4394e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469041712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3469041712 |
| Directory | /workspace/65.rv_timer_random/latest |
| Test location | /workspace/coverage/default/66.rv_timer_random.1692698448 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 160639022204 ps |
| CPU time | 85.47 seconds |
| Started | Mar 03 04:13:04 PM PST 24 |
| Finished | Mar 03 04:14:30 PM PST 24 |
| Peak memory | 183092 kb |
| Host | smart-8f44ed07-7ac9-46b9-8a1c-73cbbab95e26 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692698448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1692698448 |
| Directory | /workspace/66.rv_timer_random/latest |
| Test location | /workspace/coverage/default/67.rv_timer_random.2189809221 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 105070075447 ps |
| CPU time | 313.21 seconds |
| Started | Mar 03 04:13:05 PM PST 24 |
| Finished | Mar 03 04:18:18 PM PST 24 |
| Peak memory | 191340 kb |
| Host | smart-5ac4e7a8-ff27-4ffd-b12a-d64d7dcc59ab |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189809221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2189809221 |
| Directory | /workspace/67.rv_timer_random/latest |
| Test location | /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3513445396 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 211760909114 ps |
| CPU time | 360.21 seconds |
| Started | Mar 03 04:07:50 PM PST 24 |
| Finished | Mar 03 04:13:51 PM PST 24 |
| Peak memory | 183224 kb |
| Host | smart-ef3471ef-44f0-4192-9e82-5be34879f69a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513445396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.3513445396 |
| Directory | /workspace/7.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/7.rv_timer_disabled.2704672669 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 828983185269 ps |
| CPU time | 354.57 seconds |
| Started | Mar 03 04:07:46 PM PST 24 |
| Finished | Mar 03 04:13:40 PM PST 24 |
| Peak memory | 183180 kb |
| Host | smart-51e76dce-4b77-4b35-a21d-7b0005c85778 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2704672669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.2704672669 |
| Directory | /workspace/7.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/7.rv_timer_random.4123818491 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 1703952070739 ps |
| CPU time | 870.38 seconds |
| Started | Mar 03 04:07:43 PM PST 24 |
| Finished | Mar 03 04:22:14 PM PST 24 |
| Peak memory | 191368 kb |
| Host | smart-9c1a0b7c-2b32-4d53-83b6-26219259d20b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123818491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.4123818491 |
| Directory | /workspace/7.rv_timer_random/latest |
| Test location | /workspace/coverage/default/7.rv_timer_random_reset.863730593 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 19277883130 ps |
| CPU time | 428.56 seconds |
| Started | Mar 03 04:07:53 PM PST 24 |
| Finished | Mar 03 04:15:02 PM PST 24 |
| Peak memory | 183184 kb |
| Host | smart-5800df8d-1040-4050-98b6-3329493033ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=863730593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.863730593 |
| Directory | /workspace/7.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/7.rv_timer_stress_all.1206621948 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 233722367947 ps |
| CPU time | 951.78 seconds |
| Started | Mar 03 04:07:52 PM PST 24 |
| Finished | Mar 03 04:23:44 PM PST 24 |
| Peak memory | 191384 kb |
| Host | smart-9e95a5ee-a30b-477e-a1a7-e4ac5b3f7209 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206621948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all. 1206621948 |
| Directory | /workspace/7.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/71.rv_timer_random.1419548626 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 8252866755 ps |
| CPU time | 15.88 seconds |
| Started | Mar 03 04:13:12 PM PST 24 |
| Finished | Mar 03 04:13:28 PM PST 24 |
| Peak memory | 183168 kb |
| Host | smart-0264d43f-c5f7-4554-ba24-827764ca4865 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419548626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1419548626 |
| Directory | /workspace/71.rv_timer_random/latest |
| Test location | /workspace/coverage/default/72.rv_timer_random.2880745823 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 458447468122 ps |
| CPU time | 294.92 seconds |
| Started | Mar 03 04:13:10 PM PST 24 |
| Finished | Mar 03 04:18:05 PM PST 24 |
| Peak memory | 191368 kb |
| Host | smart-78972d59-f02e-41c4-ab54-d81bd835f594 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880745823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2880745823 |
| Directory | /workspace/72.rv_timer_random/latest |
| Test location | /workspace/coverage/default/73.rv_timer_random.3545922947 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 982567746468 ps |
| CPU time | 1048.62 seconds |
| Started | Mar 03 04:13:11 PM PST 24 |
| Finished | Mar 03 04:30:40 PM PST 24 |
| Peak memory | 191328 kb |
| Host | smart-d5ac06cf-6a66-4fc5-8598-36c847f06fc9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545922947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3545922947 |
| Directory | /workspace/73.rv_timer_random/latest |
| Test location | /workspace/coverage/default/74.rv_timer_random.1791321507 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 202843823672 ps |
| CPU time | 678.3 seconds |
| Started | Mar 03 04:13:11 PM PST 24 |
| Finished | Mar 03 04:24:30 PM PST 24 |
| Peak memory | 191320 kb |
| Host | smart-a55c44dd-2c27-4a03-9c96-0292afb27b54 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791321507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1791321507 |
| Directory | /workspace/74.rv_timer_random/latest |
| Test location | /workspace/coverage/default/75.rv_timer_random.3190858822 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 60164823528 ps |
| CPU time | 26.27 seconds |
| Started | Mar 03 04:13:12 PM PST 24 |
| Finished | Mar 03 04:13:39 PM PST 24 |
| Peak memory | 183160 kb |
| Host | smart-b438e87f-27e2-4480-a2e0-0b8fa79cac32 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190858822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3190858822 |
| Directory | /workspace/75.rv_timer_random/latest |
| Test location | /workspace/coverage/default/76.rv_timer_random.3699515434 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 34569017879 ps |
| CPU time | 63.68 seconds |
| Started | Mar 03 04:13:15 PM PST 24 |
| Finished | Mar 03 04:14:19 PM PST 24 |
| Peak memory | 191396 kb |
| Host | smart-477de094-6804-4428-9806-9dc0b2ea4a48 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699515434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3699515434 |
| Directory | /workspace/76.rv_timer_random/latest |
| Test location | /workspace/coverage/default/77.rv_timer_random.4071915867 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 509369307091 ps |
| CPU time | 271.08 seconds |
| Started | Mar 03 04:13:16 PM PST 24 |
| Finished | Mar 03 04:17:48 PM PST 24 |
| Peak memory | 191360 kb |
| Host | smart-1b349537-a81c-4383-9995-ecdb9730b2a1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071915867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.4071915867 |
| Directory | /workspace/77.rv_timer_random/latest |
| Test location | /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3656268118 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 184986844407 ps |
| CPU time | 329.66 seconds |
| Started | Mar 03 04:07:53 PM PST 24 |
| Finished | Mar 03 04:13:23 PM PST 24 |
| Peak memory | 183152 kb |
| Host | smart-06aa9478-df72-4645-b0f6-39d8db7cec0e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656268118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_cfg_update_on_fly.3656268118 |
| Directory | /workspace/8.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/8.rv_timer_disabled.270672874 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 130544532676 ps |
| CPU time | 186.06 seconds |
| Started | Mar 03 04:07:50 PM PST 24 |
| Finished | Mar 03 04:10:56 PM PST 24 |
| Peak memory | 183176 kb |
| Host | smart-8f754fb6-5d22-4817-a52c-d8b9741a0bb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=270672874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.270672874 |
| Directory | /workspace/8.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/8.rv_timer_random.222760038 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 134507234467 ps |
| CPU time | 277.91 seconds |
| Started | Mar 03 04:07:50 PM PST 24 |
| Finished | Mar 03 04:12:28 PM PST 24 |
| Peak memory | 194368 kb |
| Host | smart-6c0c4bd2-c1c5-4806-87fd-00247bc2246d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222760038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.222760038 |
| Directory | /workspace/8.rv_timer_random/latest |
| Test location | /workspace/coverage/default/8.rv_timer_random_reset.1189331557 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 236185936 ps |
| CPU time | 1.24 seconds |
| Started | Mar 03 04:07:50 PM PST 24 |
| Finished | Mar 03 04:07:52 PM PST 24 |
| Peak memory | 183104 kb |
| Host | smart-36173cd4-dc3d-41f2-9319-adb54a2ff6ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1189331557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1189331557 |
| Directory | /workspace/8.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/8.rv_timer_stress_all.706238238 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1074339970450 ps |
| CPU time | 527.17 seconds |
| Started | Mar 03 04:07:59 PM PST 24 |
| Finished | Mar 03 04:16:46 PM PST 24 |
| Peak memory | 191428 kb |
| Host | smart-ccf20e97-18d5-4c33-83c7-a64e6476610f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706238238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.706238238 |
| Directory | /workspace/8.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.2230602448 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 142068611882 ps |
| CPU time | 1000.36 seconds |
| Started | Mar 03 04:07:51 PM PST 24 |
| Finished | Mar 03 04:24:31 PM PST 24 |
| Peak memory | 200996 kb |
| Host | smart-f13f2dfb-5451-4276-8b32-96e81c339172 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230602448 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.2230602448 |
| Directory | /workspace/8.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/81.rv_timer_random.2552578943 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 689096333423 ps |
| CPU time | 467.52 seconds |
| Started | Mar 03 04:13:15 PM PST 24 |
| Finished | Mar 03 04:21:03 PM PST 24 |
| Peak memory | 191372 kb |
| Host | smart-824cf0e2-47e1-44e1-8e0e-af234e547a19 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552578943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2552578943 |
| Directory | /workspace/81.rv_timer_random/latest |
| Test location | /workspace/coverage/default/82.rv_timer_random.4027319742 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 35823671805 ps |
| CPU time | 68.68 seconds |
| Started | Mar 03 04:13:17 PM PST 24 |
| Finished | Mar 03 04:14:26 PM PST 24 |
| Peak memory | 183172 kb |
| Host | smart-d5966f92-7f25-443a-aee2-142dee3ddd4a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027319742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.4027319742 |
| Directory | /workspace/82.rv_timer_random/latest |
| Test location | /workspace/coverage/default/83.rv_timer_random.2237014623 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 223428824045 ps |
| CPU time | 77.35 seconds |
| Started | Mar 03 04:13:21 PM PST 24 |
| Finished | Mar 03 04:14:38 PM PST 24 |
| Peak memory | 183168 kb |
| Host | smart-b8b55b84-59d4-4617-a7aa-68102fd6a8fb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237014623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.2237014623 |
| Directory | /workspace/83.rv_timer_random/latest |
| Test location | /workspace/coverage/default/84.rv_timer_random.3221845786 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 93368332049 ps |
| CPU time | 89.75 seconds |
| Started | Mar 03 04:13:20 PM PST 24 |
| Finished | Mar 03 04:14:50 PM PST 24 |
| Peak memory | 191372 kb |
| Host | smart-1fc62067-eacd-4ad8-9b0f-9f28df3fde60 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221845786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3221845786 |
| Directory | /workspace/84.rv_timer_random/latest |
| Test location | /workspace/coverage/default/86.rv_timer_random.2182641983 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 580809007932 ps |
| CPU time | 136.8 seconds |
| Started | Mar 03 04:13:24 PM PST 24 |
| Finished | Mar 03 04:15:41 PM PST 24 |
| Peak memory | 191360 kb |
| Host | smart-a51bbccd-b20c-40e4-936a-963033311c02 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182641983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2182641983 |
| Directory | /workspace/86.rv_timer_random/latest |
| Test location | /workspace/coverage/default/87.rv_timer_random.4258296137 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 100235744026 ps |
| CPU time | 376.45 seconds |
| Started | Mar 03 04:13:21 PM PST 24 |
| Finished | Mar 03 04:19:37 PM PST 24 |
| Peak memory | 191388 kb |
| Host | smart-704da124-4e75-4358-bc23-0ec308f9f4d0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258296137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.4258296137 |
| Directory | /workspace/87.rv_timer_random/latest |
| Test location | /workspace/coverage/default/89.rv_timer_random.2645620126 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 40245279228 ps |
| CPU time | 76.36 seconds |
| Started | Mar 03 04:13:23 PM PST 24 |
| Finished | Mar 03 04:14:40 PM PST 24 |
| Peak memory | 191380 kb |
| Host | smart-5f8dc2f1-5cb9-4302-b80b-8946785253bd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645620126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2645620126 |
| Directory | /workspace/89.rv_timer_random/latest |
| Test location | /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.1388516380 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 16025298067 ps |
| CPU time | 30.83 seconds |
| Started | Mar 03 04:08:05 PM PST 24 |
| Finished | Mar 03 04:08:37 PM PST 24 |
| Peak memory | 183216 kb |
| Host | smart-70c16d71-f7e4-4057-a160-ff831ac70000 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388516380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_cfg_update_on_fly.1388516380 |
| Directory | /workspace/9.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/9.rv_timer_disabled.1663583928 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 365400010781 ps |
| CPU time | 140.9 seconds |
| Started | Mar 03 04:08:01 PM PST 24 |
| Finished | Mar 03 04:10:22 PM PST 24 |
| Peak memory | 183148 kb |
| Host | smart-f52b3c06-5b2d-4544-a0ba-fcc0acb6795a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1663583928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1663583928 |
| Directory | /workspace/9.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/9.rv_timer_random.818295240 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 38609244386 ps |
| CPU time | 662.2 seconds |
| Started | Mar 03 04:07:56 PM PST 24 |
| Finished | Mar 03 04:18:58 PM PST 24 |
| Peak memory | 183180 kb |
| Host | smart-82ee2278-f996-4b16-bbae-c96e1870a3b3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818295240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.818295240 |
| Directory | /workspace/9.rv_timer_random/latest |
| Test location | /workspace/coverage/default/9.rv_timer_random_reset.1689062416 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 77552345 ps |
| CPU time | 0.68 seconds |
| Started | Mar 03 04:08:00 PM PST 24 |
| Finished | Mar 03 04:08:01 PM PST 24 |
| Peak memory | 182904 kb |
| Host | smart-3a1eb2a2-5a34-43fa-9f9e-c03448efff04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1689062416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1689062416 |
| Directory | /workspace/9.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/9.rv_timer_stress_all.1514774180 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 512327123614 ps |
| CPU time | 183.8 seconds |
| Started | Mar 03 04:08:00 PM PST 24 |
| Finished | Mar 03 04:11:04 PM PST 24 |
| Peak memory | 194740 kb |
| Host | smart-b770110e-2e58-46a3-a212-e939477a6ad3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514774180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all. 1514774180 |
| Directory | /workspace/9.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/90.rv_timer_random.570146525 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 168384945259 ps |
| CPU time | 62.59 seconds |
| Started | Mar 03 04:13:28 PM PST 24 |
| Finished | Mar 03 04:14:31 PM PST 24 |
| Peak memory | 183000 kb |
| Host | smart-3e0099e4-ff55-41cb-b956-0786e20ff1e7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570146525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.570146525 |
| Directory | /workspace/90.rv_timer_random/latest |
| Test location | /workspace/coverage/default/91.rv_timer_random.3157988789 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 66035892104 ps |
| CPU time | 38.77 seconds |
| Started | Mar 03 04:13:28 PM PST 24 |
| Finished | Mar 03 04:14:07 PM PST 24 |
| Peak memory | 183372 kb |
| Host | smart-d4903cfe-c9e8-4520-8cab-079b725473d3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157988789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3157988789 |
| Directory | /workspace/91.rv_timer_random/latest |
| Test location | /workspace/coverage/default/93.rv_timer_random.3980882621 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 71747320231 ps |
| CPU time | 207.75 seconds |
| Started | Mar 03 04:13:36 PM PST 24 |
| Finished | Mar 03 04:17:03 PM PST 24 |
| Peak memory | 191396 kb |
| Host | smart-b291d4fa-12a5-43ea-b940-5370eec70e15 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980882621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3980882621 |
| Directory | /workspace/93.rv_timer_random/latest |
| Test location | /workspace/coverage/default/95.rv_timer_random.1457648716 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 148052367254 ps |
| CPU time | 251.77 seconds |
| Started | Mar 03 04:13:40 PM PST 24 |
| Finished | Mar 03 04:17:52 PM PST 24 |
| Peak memory | 194520 kb |
| Host | smart-0b5e0d34-7d4e-429b-8f99-21855f3d5e0d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457648716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1457648716 |
| Directory | /workspace/95.rv_timer_random/latest |
| Test location | /workspace/coverage/default/96.rv_timer_random.2041636607 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 223014068069 ps |
| CPU time | 400.74 seconds |
| Started | Mar 03 04:13:40 PM PST 24 |
| Finished | Mar 03 04:20:21 PM PST 24 |
| Peak memory | 191388 kb |
| Host | smart-3b63d8a7-97f7-480e-80a4-50f2f8f559f9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041636607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2041636607 |
| Directory | /workspace/96.rv_timer_random/latest |
| Test location | /workspace/coverage/default/97.rv_timer_random.3396442568 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 455288692141 ps |
| CPU time | 615.85 seconds |
| Started | Mar 03 04:13:39 PM PST 24 |
| Finished | Mar 03 04:23:55 PM PST 24 |
| Peak memory | 191384 kb |
| Host | smart-2aa5e277-4499-47a9-8926-33907a2b8815 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396442568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3396442568 |
| Directory | /workspace/97.rv_timer_random/latest |
| Test location | /workspace/coverage/default/98.rv_timer_random.2635333127 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 14822100220 ps |
| CPU time | 9.03 seconds |
| Started | Mar 03 04:13:38 PM PST 24 |
| Finished | Mar 03 04:13:47 PM PST 24 |
| Peak memory | 183148 kb |
| Host | smart-02070a20-bdaf-4f7f-9591-199c73a6bfdb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635333127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2635333127 |
| Directory | /workspace/98.rv_timer_random/latest |
| Test location | /workspace/coverage/default/99.rv_timer_random.322707813 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 236846417327 ps |
| CPU time | 226.91 seconds |
| Started | Mar 03 04:13:39 PM PST 24 |
| Finished | Mar 03 04:17:26 PM PST 24 |
| Peak memory | 194588 kb |
| Host | smart-ac176efb-b928-40f6-9c46-afc67e5f68b6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322707813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.322707813 |
| Directory | /workspace/99.rv_timer_random/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |