Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 576
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T509 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2448709750 Mar 05 12:43:10 PM PST 24 Mar 05 12:43:10 PM PST 24 18175698 ps
T510 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.304850981 Mar 05 12:43:23 PM PST 24 Mar 05 12:43:24 PM PST 24 81979756 ps
T511 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2635939003 Mar 05 12:42:53 PM PST 24 Mar 05 12:42:55 PM PST 24 71108046 ps
T512 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.303484229 Mar 05 12:43:04 PM PST 24 Mar 05 12:43:05 PM PST 24 13911414 ps
T513 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3160550122 Mar 05 12:43:22 PM PST 24 Mar 05 12:43:23 PM PST 24 14276723 ps
T514 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3858685829 Mar 05 12:43:21 PM PST 24 Mar 05 12:43:22 PM PST 24 25071121 ps
T515 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2316574118 Mar 05 12:43:10 PM PST 24 Mar 05 12:43:11 PM PST 24 18154070 ps
T516 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.767105477 Mar 05 12:43:00 PM PST 24 Mar 05 12:43:01 PM PST 24 210591741 ps
T517 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.132823149 Mar 05 12:43:19 PM PST 24 Mar 05 12:43:20 PM PST 24 19771145 ps
T518 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3273062495 Mar 05 12:43:25 PM PST 24 Mar 05 12:43:27 PM PST 24 207104832 ps
T519 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2255789582 Mar 05 12:43:07 PM PST 24 Mar 05 12:43:09 PM PST 24 226688718 ps
T520 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.198561161 Mar 05 12:43:14 PM PST 24 Mar 05 12:43:15 PM PST 24 16472091 ps
T521 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3258494643 Mar 05 12:43:05 PM PST 24 Mar 05 12:43:07 PM PST 24 13133166 ps
T522 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.705939908 Mar 05 12:43:19 PM PST 24 Mar 05 12:43:21 PM PST 24 58773132 ps
T523 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.831579991 Mar 05 12:43:13 PM PST 24 Mar 05 12:43:14 PM PST 24 75461896 ps
T101 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3685358477 Mar 05 12:43:18 PM PST 24 Mar 05 12:43:19 PM PST 24 14337454 ps
T524 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1128679532 Mar 05 12:43:29 PM PST 24 Mar 05 12:43:30 PM PST 24 17065726 ps
T123 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.4122617207 Mar 05 12:43:30 PM PST 24 Mar 05 12:43:31 PM PST 24 197949028 ps
T525 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3821191970 Mar 05 12:43:17 PM PST 24 Mar 05 12:43:20 PM PST 24 95703967 ps
T526 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3722897535 Mar 05 12:43:27 PM PST 24 Mar 05 12:43:27 PM PST 24 18653444 ps
T527 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3916919998 Mar 05 12:43:35 PM PST 24 Mar 05 12:43:36 PM PST 24 34972739 ps
T528 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1186194230 Mar 05 12:43:08 PM PST 24 Mar 05 12:43:09 PM PST 24 208294356 ps
T529 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1244528157 Mar 05 12:43:06 PM PST 24 Mar 05 12:43:08 PM PST 24 51594742 ps
T530 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2061826028 Mar 05 12:43:12 PM PST 24 Mar 05 12:43:12 PM PST 24 15789518 ps
T531 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1979886968 Mar 05 12:43:01 PM PST 24 Mar 05 12:43:02 PM PST 24 32205634 ps
T532 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.144144283 Mar 05 12:42:59 PM PST 24 Mar 05 12:43:00 PM PST 24 126960114 ps
T533 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.983107603 Mar 05 12:43:39 PM PST 24 Mar 05 12:43:41 PM PST 24 125942818 ps
T534 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.350605376 Mar 05 12:43:12 PM PST 24 Mar 05 12:43:15 PM PST 24 238888061 ps
T535 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.730524910 Mar 05 12:43:17 PM PST 24 Mar 05 12:43:19 PM PST 24 165291788 ps
T536 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.929666751 Mar 05 12:42:59 PM PST 24 Mar 05 12:43:00 PM PST 24 157801011 ps
T537 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2323299194 Mar 05 12:43:14 PM PST 24 Mar 05 12:43:15 PM PST 24 133063027 ps
T102 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.332243084 Mar 05 12:43:15 PM PST 24 Mar 05 12:43:19 PM PST 24 30453891 ps
T538 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3565528728 Mar 05 12:43:23 PM PST 24 Mar 05 12:43:24 PM PST 24 172742108 ps
T539 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.4024416808 Mar 05 12:43:25 PM PST 24 Mar 05 12:43:26 PM PST 24 21738694 ps
T540 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3367701151 Mar 05 12:43:16 PM PST 24 Mar 05 12:43:18 PM PST 24 1030293482 ps
T541 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.4220523315 Mar 05 12:43:04 PM PST 24 Mar 05 12:43:04 PM PST 24 29468053 ps
T103 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1352694481 Mar 05 12:43:01 PM PST 24 Mar 05 12:43:02 PM PST 24 54764067 ps
T542 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.856226104 Mar 05 12:42:47 PM PST 24 Mar 05 12:42:48 PM PST 24 13901852 ps
T104 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3632920858 Mar 05 12:42:53 PM PST 24 Mar 05 12:42:54 PM PST 24 137823584 ps
T543 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3999383384 Mar 05 12:43:02 PM PST 24 Mar 05 12:43:04 PM PST 24 164866873 ps
T544 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3446474054 Mar 05 12:43:10 PM PST 24 Mar 05 12:43:11 PM PST 24 38287864 ps
T545 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1944102654 Mar 05 12:43:09 PM PST 24 Mar 05 12:43:15 PM PST 24 11272789 ps
T546 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1694776643 Mar 05 12:43:18 PM PST 24 Mar 05 12:43:21 PM PST 24 112068871 ps
T547 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1892626453 Mar 05 12:43:25 PM PST 24 Mar 05 12:43:26 PM PST 24 89086347 ps
T548 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2935716614 Mar 05 12:43:23 PM PST 24 Mar 05 12:43:24 PM PST 24 78661988 ps
T549 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.4229034964 Mar 05 12:42:52 PM PST 24 Mar 05 12:43:00 PM PST 24 461125250 ps
T550 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3269227761 Mar 05 12:43:06 PM PST 24 Mar 05 12:43:07 PM PST 24 47781621 ps
T551 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3015054234 Mar 05 12:43:32 PM PST 24 Mar 05 12:43:33 PM PST 24 38393412 ps
T552 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2352256267 Mar 05 12:43:02 PM PST 24 Mar 05 12:43:04 PM PST 24 190559361 ps
T553 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1384451617 Mar 05 12:43:25 PM PST 24 Mar 05 12:43:26 PM PST 24 18691402 ps
T554 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3203394998 Mar 05 12:42:50 PM PST 24 Mar 05 12:42:54 PM PST 24 1184642986 ps
T105 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3629993445 Mar 05 12:42:59 PM PST 24 Mar 05 12:43:00 PM PST 24 14589498 ps
T555 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3365630170 Mar 05 12:43:15 PM PST 24 Mar 05 12:43:15 PM PST 24 88154711 ps
T556 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1228039916 Mar 05 12:43:27 PM PST 24 Mar 05 12:43:28 PM PST 24 75610778 ps
T557 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.576519658 Mar 05 12:43:23 PM PST 24 Mar 05 12:43:24 PM PST 24 10998741 ps
T558 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.200863663 Mar 05 12:43:28 PM PST 24 Mar 05 12:43:29 PM PST 24 34870155 ps
T106 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.4001799355 Mar 05 12:42:49 PM PST 24 Mar 05 12:42:50 PM PST 24 50480999 ps
T559 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3761214585 Mar 05 12:43:11 PM PST 24 Mar 05 12:43:12 PM PST 24 257149914 ps
T560 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.381182157 Mar 05 12:43:17 PM PST 24 Mar 05 12:43:19 PM PST 24 52176340 ps
T561 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3135600977 Mar 05 12:43:13 PM PST 24 Mar 05 12:43:14 PM PST 24 27324876 ps
T562 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.4147696528 Mar 05 12:43:12 PM PST 24 Mar 05 12:43:14 PM PST 24 324591945 ps
T563 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2031609559 Mar 05 12:42:53 PM PST 24 Mar 05 12:42:54 PM PST 24 50321122 ps
T564 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.4086869815 Mar 05 12:43:01 PM PST 24 Mar 05 12:43:02 PM PST 24 49046314 ps
T565 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.953578249 Mar 05 12:43:08 PM PST 24 Mar 05 12:43:10 PM PST 24 294690458 ps
T566 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1711537421 Mar 05 12:43:17 PM PST 24 Mar 05 12:43:19 PM PST 24 92992217 ps
T567 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1883262429 Mar 05 12:43:21 PM PST 24 Mar 05 12:43:23 PM PST 24 25873148 ps
T107 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1600644167 Mar 05 12:42:48 PM PST 24 Mar 05 12:42:49 PM PST 24 24336968 ps
T568 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2575235126 Mar 05 12:43:13 PM PST 24 Mar 05 12:43:13 PM PST 24 13845810 ps
T569 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2769671195 Mar 05 12:43:13 PM PST 24 Mar 05 12:43:13 PM PST 24 16583056 ps
T570 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3837710660 Mar 05 12:43:13 PM PST 24 Mar 05 12:43:14 PM PST 24 35736715 ps
T571 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2065991759 Mar 05 12:43:04 PM PST 24 Mar 05 12:43:05 PM PST 24 159741510 ps
T572 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3285470341 Mar 05 12:43:13 PM PST 24 Mar 05 12:43:14 PM PST 24 324918396 ps
T573 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3027218521 Mar 05 12:42:54 PM PST 24 Mar 05 12:42:55 PM PST 24 14967978 ps
T574 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2081165898 Mar 05 12:43:16 PM PST 24 Mar 05 12:43:20 PM PST 24 109703043 ps
T575 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2707579115 Mar 05 12:43:26 PM PST 24 Mar 05 12:43:27 PM PST 24 18422846 ps
T576 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1214661106 Mar 05 12:43:22 PM PST 24 Mar 05 12:43:23 PM PST 24 95696102 ps

Test location /workspace/coverage/default/109.rv_timer_random.300722915
Short name T1
Test name
Test status
Simulation time 80774653961 ps
CPU time 757.69 seconds
Started Mar 05 12:51:44 PM PST 24
Finished Mar 05 01:04:23 PM PST 24
Peak memory 194800 kb
Host smart-c7b8cef9-0b17-4df1-a38a-e07af05fdaaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300722915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.300722915
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.1727623809
Short name T13
Test name
Test status
Simulation time 248077312303 ps
CPU time 848.3 seconds
Started Mar 05 12:50:35 PM PST 24
Finished Mar 05 01:04:44 PM PST 24
Peak memory 208540 kb
Host smart-7de87f6d-d60f-48d4-9b49-06cc8276837d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727623809 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.1727623809
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.2257791532
Short name T8
Test name
Test status
Simulation time 587046862215 ps
CPU time 1475.89 seconds
Started Mar 05 12:50:01 PM PST 24
Finished Mar 05 01:14:37 PM PST 24
Peak memory 196168 kb
Host smart-ce11fdac-149b-4c91-831d-fe43a96c0392
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257791532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.2257791532
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3594861811
Short name T129
Test name
Test status
Simulation time 642721178885 ps
CPU time 3135.93 seconds
Started Mar 05 12:50:15 PM PST 24
Finished Mar 05 01:42:32 PM PST 24
Peak memory 191260 kb
Host smart-9491690f-3ee8-4a25-9937-37aad21c16d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594861811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3594861811
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2393756335
Short name T28
Test name
Test status
Simulation time 280580718 ps
CPU time 1.03 seconds
Started Mar 05 12:43:22 PM PST 24
Finished Mar 05 12:43:24 PM PST 24
Peak memory 195028 kb
Host smart-b606fd17-6401-4bd4-a38b-9a787da3b3f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393756335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2393756335
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.3611391333
Short name T69
Test name
Test status
Simulation time 2471531534286 ps
CPU time 1103.11 seconds
Started Mar 05 12:49:32 PM PST 24
Finished Mar 05 01:07:56 PM PST 24
Peak memory 191248 kb
Host smart-c85e87cb-a402-4ba4-a835-dba8c4137821
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611391333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.3611391333
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3443256230
Short name T184
Test name
Test status
Simulation time 694955780156 ps
CPU time 2243.06 seconds
Started Mar 05 12:50:09 PM PST 24
Finished Mar 05 01:27:33 PM PST 24
Peak memory 191320 kb
Host smart-0e94dead-8487-430a-b0c7-3b8ab55f5072
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443256230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3443256230
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3167667759
Short name T282
Test name
Test status
Simulation time 2341341560567 ps
CPU time 1495.49 seconds
Started Mar 05 12:49:45 PM PST 24
Finished Mar 05 01:14:40 PM PST 24
Peak memory 191224 kb
Host smart-93545788-0872-4f73-8c1b-40e32d2ddcd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167667759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3167667759
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.1712176854
Short name T74
Test name
Test status
Simulation time 480318904712 ps
CPU time 1459.01 seconds
Started Mar 05 12:49:33 PM PST 24
Finished Mar 05 01:13:52 PM PST 24
Peak memory 195816 kb
Host smart-67f02da5-2504-4c3f-ad95-7c2e0f0a0eaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712176854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1712176854
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1763155398
Short name T173
Test name
Test status
Simulation time 758864333189 ps
CPU time 2665.34 seconds
Started Mar 05 12:50:04 PM PST 24
Finished Mar 05 01:34:30 PM PST 24
Peak memory 195708 kb
Host smart-db0c568c-574c-4763-90c0-46b66e5e5962
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763155398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1763155398
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3230429917
Short name T92
Test name
Test status
Simulation time 13705930 ps
CPU time 0.6 seconds
Started Mar 05 12:43:06 PM PST 24
Finished Mar 05 12:43:07 PM PST 24
Peak memory 182624 kb
Host smart-f997b9c0-4f04-40c7-8b68-f39dc1447cd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230429917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3230429917
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/168.rv_timer_random.3817782876
Short name T10
Test name
Test status
Simulation time 290395200042 ps
CPU time 99.2 seconds
Started Mar 05 12:52:16 PM PST 24
Finished Mar 05 12:53:55 PM PST 24
Peak memory 195428 kb
Host smart-81c0c740-c8fb-4cea-bd80-193bb945b6a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817782876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3817782876
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.2558219815
Short name T44
Test name
Test status
Simulation time 816703585111 ps
CPU time 498.42 seconds
Started Mar 05 12:51:46 PM PST 24
Finished Mar 05 01:00:05 PM PST 24
Peak memory 193420 kb
Host smart-7119821b-b873-4132-b981-6838da425df8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558219815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2558219815
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.3870553687
Short name T177
Test name
Test status
Simulation time 2590881295567 ps
CPU time 1625.44 seconds
Started Mar 05 12:50:27 PM PST 24
Finished Mar 05 01:17:33 PM PST 24
Peak memory 191328 kb
Host smart-d7d614ac-7d5e-49bc-89c7-0920627c2acc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870553687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.3870553687
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2434138949
Short name T16
Test name
Test status
Simulation time 228480671 ps
CPU time 0.8 seconds
Started Mar 05 12:49:25 PM PST 24
Finished Mar 05 12:49:25 PM PST 24
Peak memory 213344 kb
Host smart-8b4b18a9-83e2-46aa-89a8-a5d5cffb0509
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434138949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2434138949
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3917577859
Short name T199
Test name
Test status
Simulation time 1192736556223 ps
CPU time 1610.77 seconds
Started Mar 05 12:49:33 PM PST 24
Finished Mar 05 01:16:24 PM PST 24
Peak memory 191348 kb
Host smart-8ee12d42-fa82-4cd2-a0d8-8101007d4b3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917577859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3917577859
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.345528096
Short name T75
Test name
Test status
Simulation time 871198726036 ps
CPU time 1089.23 seconds
Started Mar 05 12:50:19 PM PST 24
Finished Mar 05 01:08:29 PM PST 24
Peak memory 195840 kb
Host smart-90428fc8-8d76-4a3a-9bbe-acbe532d2faf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345528096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.
345528096
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_random.2038720248
Short name T170
Test name
Test status
Simulation time 434861694637 ps
CPU time 932.99 seconds
Started Mar 05 12:49:31 PM PST 24
Finished Mar 05 01:05:05 PM PST 24
Peak memory 194624 kb
Host smart-ed279422-bda1-4474-92c9-de8408f6b382
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038720248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2038720248
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random.4186354107
Short name T164
Test name
Test status
Simulation time 4545782201515 ps
CPU time 1276.86 seconds
Started Mar 05 12:49:33 PM PST 24
Finished Mar 05 01:10:50 PM PST 24
Peak memory 191292 kb
Host smart-fb02812e-2caf-495a-b687-e8631974c7da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186354107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.4186354107
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.817241327
Short name T201
Test name
Test status
Simulation time 283035071411 ps
CPU time 455.08 seconds
Started Mar 05 12:50:11 PM PST 24
Finished Mar 05 12:57:46 PM PST 24
Peak memory 191192 kb
Host smart-5813e92d-8a6f-44d1-873a-01e78f87c7c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817241327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.
817241327
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2918244778
Short name T279
Test name
Test status
Simulation time 270174389546 ps
CPU time 743.53 seconds
Started Mar 05 12:49:46 PM PST 24
Finished Mar 05 01:02:09 PM PST 24
Peak memory 195716 kb
Host smart-86e74e1d-58e5-4bff-b5c9-1c125e55ad6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918244778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2918244778
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_random.3377627136
Short name T116
Test name
Test status
Simulation time 186248402649 ps
CPU time 1328.78 seconds
Started Mar 05 12:49:28 PM PST 24
Finished Mar 05 01:11:38 PM PST 24
Peak memory 193476 kb
Host smart-3c61620c-af74-40ac-abe3-10a6a798387e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377627136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3377627136
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.198476400
Short name T258
Test name
Test status
Simulation time 108484637179 ps
CPU time 648.19 seconds
Started Mar 05 12:51:36 PM PST 24
Finished Mar 05 01:02:24 PM PST 24
Peak memory 191320 kb
Host smart-f28a9cd8-52c4-45ae-b9a8-15370d542224
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198476400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.198476400
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1064188333
Short name T232
Test name
Test status
Simulation time 455777328967 ps
CPU time 1326.14 seconds
Started Mar 05 12:52:37 PM PST 24
Finished Mar 05 01:14:44 PM PST 24
Peak memory 191316 kb
Host smart-dd6b5055-5934-430d-87de-372d29ccfebb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064188333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1064188333
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random.3025651623
Short name T273
Test name
Test status
Simulation time 199113541905 ps
CPU time 319.82 seconds
Started Mar 05 12:50:01 PM PST 24
Finished Mar 05 12:55:22 PM PST 24
Peak memory 191220 kb
Host smart-c8b937f1-8f18-4d4c-891a-8b001f186dbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025651623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3025651623
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.2327219202
Short name T259
Test name
Test status
Simulation time 517643669146 ps
CPU time 873.74 seconds
Started Mar 05 12:49:33 PM PST 24
Finished Mar 05 01:04:07 PM PST 24
Peak memory 191288 kb
Host smart-bd3b13b4-3391-40bb-b29a-bef137e0f615
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327219202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
2327219202
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3276729622
Short name T223
Test name
Test status
Simulation time 1455326581073 ps
CPU time 759.57 seconds
Started Mar 05 12:49:37 PM PST 24
Finished Mar 05 01:02:17 PM PST 24
Peak memory 194584 kb
Host smart-e24ab48d-6a7f-4d22-938b-c5a47974033f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276729622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3276729622
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_random.2918695934
Short name T246
Test name
Test status
Simulation time 385356617349 ps
CPU time 237.09 seconds
Started Mar 05 12:49:30 PM PST 24
Finished Mar 05 12:53:28 PM PST 24
Peak memory 191300 kb
Host smart-c0d1ad72-4e3e-4da1-b765-67c106f5f1fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918695934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2918695934
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.2769526922
Short name T213
Test name
Test status
Simulation time 96854980581 ps
CPU time 1334.77 seconds
Started Mar 05 12:51:56 PM PST 24
Finished Mar 05 01:14:11 PM PST 24
Peak memory 191292 kb
Host smart-d637bc42-4013-472a-87be-5067dfaf6133
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769526922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2769526922
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.662037551
Short name T22
Test name
Test status
Simulation time 115879074033 ps
CPU time 2889.88 seconds
Started Mar 05 12:52:03 PM PST 24
Finished Mar 05 01:40:13 PM PST 24
Peak memory 194388 kb
Host smart-9f54c5a9-4a83-452d-b13c-7c1069a92b6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662037551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.662037551
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.2904029113
Short name T334
Test name
Test status
Simulation time 524781425424 ps
CPU time 234.1 seconds
Started Mar 05 12:52:36 PM PST 24
Finished Mar 05 12:56:30 PM PST 24
Peak memory 191312 kb
Host smart-d03a8d75-6b4d-4efa-9c6b-ee9c98ce1f05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904029113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2904029113
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.124035392
Short name T25
Test name
Test status
Simulation time 200927847631 ps
CPU time 294.38 seconds
Started Mar 05 12:52:35 PM PST 24
Finished Mar 05 12:57:30 PM PST 24
Peak memory 191312 kb
Host smart-268f7f1f-e360-42b7-89f8-f7d408d3c31f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124035392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.124035392
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random.3259295964
Short name T211
Test name
Test status
Simulation time 238683698785 ps
CPU time 298.5 seconds
Started Mar 05 12:49:51 PM PST 24
Finished Mar 05 12:54:50 PM PST 24
Peak memory 191248 kb
Host smart-452e8909-8e72-4378-9525-a7fd2515b409
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259295964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3259295964
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1924193836
Short name T227
Test name
Test status
Simulation time 389384260352 ps
CPU time 619.35 seconds
Started Mar 05 12:50:10 PM PST 24
Finished Mar 05 01:00:30 PM PST 24
Peak memory 183120 kb
Host smart-7dc1557e-b639-43d1-ba02-fea8c4a4bb7f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924193836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.1924193836
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/151.rv_timer_random.3628707767
Short name T236
Test name
Test status
Simulation time 155663983066 ps
CPU time 243.44 seconds
Started Mar 05 12:52:03 PM PST 24
Finished Mar 05 12:56:07 PM PST 24
Peak memory 191372 kb
Host smart-90db5662-6a30-460d-9e1b-38c440b146aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628707767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3628707767
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.481564451
Short name T303
Test name
Test status
Simulation time 363392252646 ps
CPU time 923.36 seconds
Started Mar 05 12:50:03 PM PST 24
Finished Mar 05 01:05:27 PM PST 24
Peak memory 191308 kb
Host smart-15266183-4ffa-4549-bbea-fd9cc21e92ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481564451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
481564451
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.3722415556
Short name T144
Test name
Test status
Simulation time 433619051488 ps
CPU time 377.09 seconds
Started Mar 05 12:51:08 PM PST 24
Finished Mar 05 12:57:25 PM PST 24
Peak memory 191272 kb
Host smart-323a7751-575f-4f9f-bf90-ffe9e675db51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722415556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3722415556
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.968871393
Short name T341
Test name
Test status
Simulation time 118219544353 ps
CPU time 201.33 seconds
Started Mar 05 12:51:20 PM PST 24
Finished Mar 05 12:54:42 PM PST 24
Peak memory 191248 kb
Host smart-55047346-8c3a-435a-a2ff-a0b258f82f8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968871393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.968871393
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.2131302837
Short name T255
Test name
Test status
Simulation time 504162871178 ps
CPU time 377.67 seconds
Started Mar 05 12:51:35 PM PST 24
Finished Mar 05 12:57:53 PM PST 24
Peak memory 191292 kb
Host smart-a324d536-83d1-44d5-a772-f21a2e4109f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131302837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2131302837
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.804991749
Short name T235
Test name
Test status
Simulation time 100205287935 ps
CPU time 138.41 seconds
Started Mar 05 12:51:45 PM PST 24
Finished Mar 05 12:54:04 PM PST 24
Peak memory 193924 kb
Host smart-537fab12-d921-42c7-bcfc-ff1267f2828f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804991749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.804991749
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.3900307843
Short name T320
Test name
Test status
Simulation time 163296911086 ps
CPU time 454.21 seconds
Started Mar 05 12:51:55 PM PST 24
Finished Mar 05 12:59:30 PM PST 24
Peak memory 191316 kb
Host smart-0cb74823-83b9-4836-9710-faed59e65afb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900307843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3900307843
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.201008644
Short name T197
Test name
Test status
Simulation time 712577151808 ps
CPU time 1346.24 seconds
Started Mar 05 12:49:32 PM PST 24
Finished Mar 05 01:11:59 PM PST 24
Peak memory 183124 kb
Host smart-4a153372-4502-4a79-b0e0-217c5d8a4f34
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201008644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.rv_timer_cfg_update_on_fly.201008644
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3869959256
Short name T153
Test name
Test status
Simulation time 85715966240 ps
CPU time 250.1 seconds
Started Mar 05 12:49:37 PM PST 24
Finished Mar 05 12:53:47 PM PST 24
Peak memory 191200 kb
Host smart-3d553534-085a-4ca6-969e-a265f2226164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869959256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3869959256
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/173.rv_timer_random.3065056646
Short name T193
Test name
Test status
Simulation time 200587041777 ps
CPU time 777.6 seconds
Started Mar 05 12:52:16 PM PST 24
Finished Mar 05 01:05:14 PM PST 24
Peak memory 191240 kb
Host smart-9767d770-93d6-4ab8-ba5f-07edcfe6c244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065056646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3065056646
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.382546216
Short name T151
Test name
Test status
Simulation time 164435844412 ps
CPU time 310.09 seconds
Started Mar 05 12:49:45 PM PST 24
Finished Mar 05 12:54:55 PM PST 24
Peak memory 192424 kb
Host smart-bfe5868a-8ae1-4ba2-be45-659722bed289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382546216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.382546216
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.2208422263
Short name T240
Test name
Test status
Simulation time 763519264274 ps
CPU time 3097.77 seconds
Started Mar 05 12:50:00 PM PST 24
Finished Mar 05 01:41:39 PM PST 24
Peak memory 191260 kb
Host smart-18a9fbd2-d2cf-4473-ad36-80c00ad2028d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208422263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.2208422263
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.4018302927
Short name T260
Test name
Test status
Simulation time 262357659345 ps
CPU time 541.59 seconds
Started Mar 05 12:50:04 PM PST 24
Finished Mar 05 12:59:06 PM PST 24
Peak memory 191336 kb
Host smart-dd914651-d813-4090-af70-efa07a058405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018302927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.4018302927
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/66.rv_timer_random.2609585547
Short name T63
Test name
Test status
Simulation time 99277250185 ps
CPU time 598.8 seconds
Started Mar 05 12:51:17 PM PST 24
Finished Mar 05 01:01:16 PM PST 24
Peak memory 191308 kb
Host smart-cd73e3c9-6be4-4aef-8ce2-42d45009a26e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609585547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2609585547
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/70.rv_timer_random.3569019406
Short name T301
Test name
Test status
Simulation time 142568373816 ps
CPU time 1040.24 seconds
Started Mar 05 12:51:17 PM PST 24
Finished Mar 05 01:08:38 PM PST 24
Peak memory 191356 kb
Host smart-b0593861-307c-41a8-be9a-b16cd4aa635a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569019406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3569019406
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1201711799
Short name T119
Test name
Test status
Simulation time 248195697 ps
CPU time 1.02 seconds
Started Mar 05 12:43:07 PM PST 24
Finished Mar 05 12:43:08 PM PST 24
Peak memory 183264 kb
Host smart-5ba36f9d-7a17-4ddb-8f7c-cd37cd57404a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201711799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1201711799
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1156209503
Short name T262
Test name
Test status
Simulation time 161656053442 ps
CPU time 241.37 seconds
Started Mar 05 12:49:25 PM PST 24
Finished Mar 05 12:53:26 PM PST 24
Peak memory 182928 kb
Host smart-981fb25b-461e-4aee-b25d-ff2dc2b8ea72
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156209503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1156209503
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/126.rv_timer_random.2978824832
Short name T138
Test name
Test status
Simulation time 76013568927 ps
CPU time 118.73 seconds
Started Mar 05 12:51:55 PM PST 24
Finished Mar 05 12:53:55 PM PST 24
Peak memory 191352 kb
Host smart-19b85932-76d5-46df-978c-702c5e52a9ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978824832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2978824832
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.2590785447
Short name T45
Test name
Test status
Simulation time 654666502388 ps
CPU time 581.83 seconds
Started Mar 05 12:51:54 PM PST 24
Finished Mar 05 01:01:36 PM PST 24
Peak memory 191376 kb
Host smart-556de7ed-4ae1-495c-9dfb-506d876046e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590785447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2590785447
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.973186932
Short name T146
Test name
Test status
Simulation time 234456996947 ps
CPU time 948.67 seconds
Started Mar 05 12:51:56 PM PST 24
Finished Mar 05 01:07:45 PM PST 24
Peak memory 191148 kb
Host smart-197b4adb-a5e9-4fa7-9658-65cf4ff9532e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973186932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.973186932
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.4093251333
Short name T205
Test name
Test status
Simulation time 429936929866 ps
CPU time 426.11 seconds
Started Mar 05 12:52:12 PM PST 24
Finished Mar 05 12:59:18 PM PST 24
Peak memory 193892 kb
Host smart-6e7d4a9c-3ffc-48d1-96e5-9c1249db5ce3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093251333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.4093251333
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.442139721
Short name T77
Test name
Test status
Simulation time 545155243668 ps
CPU time 547.43 seconds
Started Mar 05 12:50:26 PM PST 24
Finished Mar 05 12:59:34 PM PST 24
Peak memory 183144 kb
Host smart-44e662cc-8611-437b-978b-436d84510079
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442139721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.rv_timer_cfg_update_on_fly.442139721
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.287189162
Short name T165
Test name
Test status
Simulation time 242841981245 ps
CPU time 325.46 seconds
Started Mar 05 12:51:00 PM PST 24
Finished Mar 05 12:56:25 PM PST 24
Peak memory 183064 kb
Host smart-78846f82-7d68-4004-9906-5c77e137ab86
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287189162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.287189162
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/73.rv_timer_random.2645995526
Short name T114
Test name
Test status
Simulation time 105197685463 ps
CPU time 213.17 seconds
Started Mar 05 12:51:18 PM PST 24
Finished Mar 05 12:54:51 PM PST 24
Peak memory 194596 kb
Host smart-322ef41c-c661-4c96-b47e-325295cc4ded
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645995526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2645995526
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3278583678
Short name T109
Test name
Test status
Simulation time 57976169 ps
CPU time 0.61 seconds
Started Mar 05 12:43:11 PM PST 24
Finished Mar 05 12:43:12 PM PST 24
Peak memory 191172 kb
Host smart-faa71113-ba20-4cf1-9f95-f98713eebb51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278583678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.3278583678
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.607923839
Short name T325
Test name
Test status
Simulation time 116408317478 ps
CPU time 165.19 seconds
Started Mar 05 12:49:24 PM PST 24
Finished Mar 05 12:52:09 PM PST 24
Peak memory 183088 kb
Host smart-73ced059-0c3e-4170-8e06-63e2383779e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607923839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.607923839
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/101.rv_timer_random.221727592
Short name T250
Test name
Test status
Simulation time 85589796350 ps
CPU time 322.53 seconds
Started Mar 05 12:51:38 PM PST 24
Finished Mar 05 12:57:00 PM PST 24
Peak memory 191308 kb
Host smart-45adfedc-9da0-46ec-8ae5-f3e6f1fd7a05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221727592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.221727592
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.249378241
Short name T306
Test name
Test status
Simulation time 216807010251 ps
CPU time 556.03 seconds
Started Mar 05 12:51:35 PM PST 24
Finished Mar 05 01:00:51 PM PST 24
Peak memory 191168 kb
Host smart-0c8475d2-96f8-4131-8922-a134cabe0b6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249378241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.249378241
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.4227353457
Short name T192
Test name
Test status
Simulation time 635738262602 ps
CPU time 511.18 seconds
Started Mar 05 12:51:55 PM PST 24
Finished Mar 05 01:00:26 PM PST 24
Peak memory 191292 kb
Host smart-ec694e4a-51be-4153-904e-aa8d21d514c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227353457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.4227353457
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3881305848
Short name T133
Test name
Test status
Simulation time 188206211933 ps
CPU time 754.2 seconds
Started Mar 05 12:52:04 PM PST 24
Finished Mar 05 01:04:38 PM PST 24
Peak memory 191328 kb
Host smart-107aeb10-b008-4563-bc9b-317b43bff517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881305848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3881305848
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.4046294115
Short name T245
Test name
Test status
Simulation time 267354612393 ps
CPU time 873.52 seconds
Started Mar 05 12:52:00 PM PST 24
Finished Mar 05 01:06:34 PM PST 24
Peak memory 191312 kb
Host smart-2ef9196f-1c8f-49c2-b3d7-fe63722cdee3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046294115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.4046294115
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.4255751087
Short name T207
Test name
Test status
Simulation time 346182943253 ps
CPU time 1245.72 seconds
Started Mar 05 12:52:14 PM PST 24
Finished Mar 05 01:13:00 PM PST 24
Peak memory 191324 kb
Host smart-3982675a-ffa0-4b6e-b668-10ce58e61705
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255751087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.4255751087
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2448878758
Short name T152
Test name
Test status
Simulation time 125005358093 ps
CPU time 781 seconds
Started Mar 05 12:52:12 PM PST 24
Finished Mar 05 01:05:13 PM PST 24
Peak memory 191312 kb
Host smart-0770ebe8-45f3-4b3b-87af-2a46bb03503a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448878758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2448878758
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.153503576
Short name T145
Test name
Test status
Simulation time 453375840868 ps
CPU time 470.18 seconds
Started Mar 05 12:52:36 PM PST 24
Finished Mar 05 01:00:27 PM PST 24
Peak memory 193732 kb
Host smart-aedae7b8-6a60-4432-b281-d8b9408c0b3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153503576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.153503576
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random.3763731325
Short name T340
Test name
Test status
Simulation time 189368537324 ps
CPU time 403.64 seconds
Started Mar 05 12:49:52 PM PST 24
Finished Mar 05 12:56:36 PM PST 24
Peak memory 191296 kb
Host smart-846356ab-19ab-4cd8-b8e1-e166387e88e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763731325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3763731325
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2296082320
Short name T161
Test name
Test status
Simulation time 389226106814 ps
CPU time 212.09 seconds
Started Mar 05 12:49:53 PM PST 24
Finished Mar 05 12:53:25 PM PST 24
Peak memory 183136 kb
Host smart-077dedc3-821a-4c9c-bb8e-eefd9f0583d9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296082320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2296082320
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3854530043
Short name T360
Test name
Test status
Simulation time 25337350794 ps
CPU time 15.16 seconds
Started Mar 05 12:50:43 PM PST 24
Finished Mar 05 12:50:58 PM PST 24
Peak memory 183140 kb
Host smart-df08c047-e5dd-4045-aceb-88dd3b5582ef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854530043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3854530043
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1859645589
Short name T231
Test name
Test status
Simulation time 192473528685 ps
CPU time 867.26 seconds
Started Mar 05 12:51:03 PM PST 24
Finished Mar 05 01:05:31 PM PST 24
Peak memory 195204 kb
Host smart-0da776ce-799a-4b60-a8f0-bc73aca0628b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859645589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1859645589
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.367429319
Short name T68
Test name
Test status
Simulation time 1435000215651 ps
CPU time 306.96 seconds
Started Mar 05 12:49:31 PM PST 24
Finished Mar 05 12:54:39 PM PST 24
Peak memory 191340 kb
Host smart-925e20c9-8dec-487d-b862-5fe89c4ed83b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367429319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.367429319
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/89.rv_timer_random.2042431263
Short name T180
Test name
Test status
Simulation time 209279184120 ps
CPU time 763.36 seconds
Started Mar 05 12:51:29 PM PST 24
Finished Mar 05 01:04:13 PM PST 24
Peak memory 191168 kb
Host smart-3e30d109-6137-4049-bc15-edad7fb58840
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042431263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2042431263
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.149529133
Short name T353
Test name
Test status
Simulation time 277545426180 ps
CPU time 274.25 seconds
Started Mar 05 12:49:25 PM PST 24
Finished Mar 05 12:53:59 PM PST 24
Peak memory 183128 kb
Host smart-38441c5c-49c1-437d-b44d-fd4bd8efb86e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149529133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.rv_timer_cfg_update_on_fly.149529133
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_random.1403005368
Short name T26
Test name
Test status
Simulation time 34239332114 ps
CPU time 55.78 seconds
Started Mar 05 12:49:09 PM PST 24
Finished Mar 05 12:50:05 PM PST 24
Peak memory 183096 kb
Host smart-3c2728d6-eee0-4829-bb71-24056ecc45a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403005368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1403005368
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3307662007
Short name T299
Test name
Test status
Simulation time 323601362286 ps
CPU time 539.57 seconds
Started Mar 05 12:49:38 PM PST 24
Finished Mar 05 12:58:38 PM PST 24
Peak memory 183080 kb
Host smart-f64a7b3b-0d75-4d14-b746-3d53d312dc59
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307662007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3307662007
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/102.rv_timer_random.3515979877
Short name T127
Test name
Test status
Simulation time 592863291222 ps
CPU time 609.46 seconds
Started Mar 05 12:51:39 PM PST 24
Finished Mar 05 01:01:48 PM PST 24
Peak memory 191344 kb
Host smart-dccfc82c-32c3-408d-bc84-128a5645b154
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515979877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3515979877
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.587033502
Short name T293
Test name
Test status
Simulation time 41132945816 ps
CPU time 1151.55 seconds
Started Mar 05 12:51:44 PM PST 24
Finished Mar 05 01:10:55 PM PST 24
Peak memory 191332 kb
Host smart-480b7005-c4f1-4dbe-84c5-1f73282c81be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587033502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.587033502
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1405223776
Short name T355
Test name
Test status
Simulation time 164261429402 ps
CPU time 120.41 seconds
Started Mar 05 12:49:33 PM PST 24
Finished Mar 05 12:51:34 PM PST 24
Peak memory 191296 kb
Host smart-93a3bf52-5bc0-4417-9f28-7ca42ab3dbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405223776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1405223776
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/136.rv_timer_random.1163814829
Short name T345
Test name
Test status
Simulation time 357832184132 ps
CPU time 91.74 seconds
Started Mar 05 12:51:56 PM PST 24
Finished Mar 05 12:53:28 PM PST 24
Peak memory 191240 kb
Host smart-7b5c20ab-2a5b-46e8-aa41-03e67dee705b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163814829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1163814829
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1899284782
Short name T229
Test name
Test status
Simulation time 96528923297 ps
CPU time 381.12 seconds
Started Mar 05 12:51:56 PM PST 24
Finished Mar 05 12:58:17 PM PST 24
Peak memory 191176 kb
Host smart-d5502084-ba8f-450b-8e6d-f8186b24725f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899284782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1899284782
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.469709941
Short name T285
Test name
Test status
Simulation time 298573434411 ps
CPU time 427.32 seconds
Started Mar 05 12:52:00 PM PST 24
Finished Mar 05 12:59:08 PM PST 24
Peak memory 191276 kb
Host smart-95f52613-ad51-4f2c-996b-5d36602b2742
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469709941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.469709941
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.589159420
Short name T187
Test name
Test status
Simulation time 617272430737 ps
CPU time 169.13 seconds
Started Mar 05 12:52:00 PM PST 24
Finished Mar 05 12:54:50 PM PST 24
Peak memory 191336 kb
Host smart-2492c461-829b-4dbc-8320-341a40d853aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589159420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.589159420
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2150589800
Short name T434
Test name
Test status
Simulation time 91243670555 ps
CPU time 132.34 seconds
Started Mar 05 12:52:04 PM PST 24
Finished Mar 05 12:54:16 PM PST 24
Peak memory 191316 kb
Host smart-4c460308-ede0-4fab-a302-d5a14a01b57a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150589800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2150589800
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2760352724
Short name T163
Test name
Test status
Simulation time 719763327109 ps
CPU time 662.69 seconds
Started Mar 05 12:52:00 PM PST 24
Finished Mar 05 01:03:04 PM PST 24
Peak memory 191312 kb
Host smart-b86c19b5-d7fe-4a8c-be7f-ec7257410328
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760352724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2760352724
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.923358534
Short name T204
Test name
Test status
Simulation time 372512947573 ps
CPU time 202.86 seconds
Started Mar 05 12:52:36 PM PST 24
Finished Mar 05 12:55:59 PM PST 24
Peak memory 191272 kb
Host smart-0c5c484d-7ea3-45fc-b7ed-a2c94809e03d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923358534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.923358534
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1349320033
Short name T135
Test name
Test status
Simulation time 69645528989 ps
CPU time 172.98 seconds
Started Mar 05 12:52:34 PM PST 24
Finished Mar 05 12:55:28 PM PST 24
Peak memory 191412 kb
Host smart-5ba780cc-084a-41ed-83de-2c34b00e9526
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349320033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1349320033
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3119319553
Short name T50
Test name
Test status
Simulation time 184504499256 ps
CPU time 348.01 seconds
Started Mar 05 12:52:36 PM PST 24
Finished Mar 05 12:58:24 PM PST 24
Peak memory 191312 kb
Host smart-9ff16bb2-3ed4-417b-bb08-7a51fbb1476f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119319553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3119319553
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.2696570455
Short name T175
Test name
Test status
Simulation time 671180348360 ps
CPU time 1968.82 seconds
Started Mar 05 12:52:44 PM PST 24
Finished Mar 05 01:25:33 PM PST 24
Peak memory 191244 kb
Host smart-5ad0ed75-96ae-40b7-8b78-48f289b9b673
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696570455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2696570455
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.348219104
Short name T83
Test name
Test status
Simulation time 168413196252 ps
CPU time 154.67 seconds
Started Mar 05 12:49:49 PM PST 24
Finished Mar 05 12:52:24 PM PST 24
Peak memory 183116 kb
Host smart-88651852-e01c-4eea-bf8f-543bd9720962
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348219104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.rv_timer_cfg_update_on_fly.348219104
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_random.1397753338
Short name T148
Test name
Test status
Simulation time 10024607713 ps
CPU time 18.09 seconds
Started Mar 05 12:50:03 PM PST 24
Finished Mar 05 12:50:21 PM PST 24
Peak memory 193244 kb
Host smart-f73ac938-ea85-4c67-bab5-9e89a432a85a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397753338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1397753338
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1262065852
Short name T218
Test name
Test status
Simulation time 548442839754 ps
CPU time 325.98 seconds
Started Mar 05 12:50:00 PM PST 24
Finished Mar 05 12:55:27 PM PST 24
Peak memory 183164 kb
Host smart-5f10a7c3-d6be-4710-afdd-ff64b0cccd95
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262065852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1262065852
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_random.4068176709
Short name T238
Test name
Test status
Simulation time 153201204664 ps
CPU time 959.24 seconds
Started Mar 05 12:50:08 PM PST 24
Finished Mar 05 01:06:07 PM PST 24
Peak memory 191332 kb
Host smart-745233e2-b844-4f90-b90a-17178c6c51d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068176709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.4068176709
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.2120081424
Short name T352
Test name
Test status
Simulation time 554139966792 ps
CPU time 983.86 seconds
Started Mar 05 12:50:16 PM PST 24
Finished Mar 05 01:06:40 PM PST 24
Peak memory 183132 kb
Host smart-276b2092-97cd-4705-b405-7a0caa14ab69
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120081424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.2120081424
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2087071943
Short name T264
Test name
Test status
Simulation time 45394180657 ps
CPU time 93.46 seconds
Started Mar 05 12:50:20 PM PST 24
Finished Mar 05 12:51:54 PM PST 24
Peak memory 183104 kb
Host smart-25fa5471-8acb-405d-8248-0222e606549e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087071943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2087071943
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2932986941
Short name T189
Test name
Test status
Simulation time 1379450085303 ps
CPU time 594.78 seconds
Started Mar 05 12:50:32 PM PST 24
Finished Mar 05 01:00:27 PM PST 24
Peak memory 183076 kb
Host smart-75439ac9-d4e7-481d-a75d-8d2b070fbac2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932986941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2932986941
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.823536426
Short name T308
Test name
Test status
Simulation time 634463323327 ps
CPU time 978.2 seconds
Started Mar 05 12:50:58 PM PST 24
Finished Mar 05 01:07:17 PM PST 24
Peak memory 191312 kb
Host smart-1ef0d03f-b03b-4b1d-a51b-791f24880cc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823536426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.
823536426
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3767412155
Short name T219
Test name
Test status
Simulation time 272650942068 ps
CPU time 474.94 seconds
Started Mar 05 12:49:29 PM PST 24
Finished Mar 05 12:57:24 PM PST 24
Peak memory 183160 kb
Host smart-b28153a0-4ec4-48ed-bf39-3086d2707b56
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767412155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.3767412155
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/65.rv_timer_random.516074920
Short name T191
Test name
Test status
Simulation time 44539209754 ps
CPU time 57.17 seconds
Started Mar 05 12:51:08 PM PST 24
Finished Mar 05 12:52:05 PM PST 24
Peak memory 191292 kb
Host smart-df948f99-0b96-4394-98f6-1bd695a42081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516074920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.516074920
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.652468162
Short name T237
Test name
Test status
Simulation time 153796687597 ps
CPU time 445.36 seconds
Started Mar 05 12:51:21 PM PST 24
Finished Mar 05 12:58:47 PM PST 24
Peak memory 191048 kb
Host smart-6ef26578-2ddc-47a6-913e-a997251cad8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652468162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.652468162
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2504110969
Short name T94
Test name
Test status
Simulation time 186666319 ps
CPU time 0.71 seconds
Started Mar 05 12:43:02 PM PST 24
Finished Mar 05 12:43:02 PM PST 24
Peak memory 192340 kb
Host smart-3b264650-a68f-4d28-8e48-881e82681f37
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504110969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.2504110969
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.676541758
Short name T466
Test name
Test status
Simulation time 936692162 ps
CPU time 2.51 seconds
Started Mar 05 12:43:07 PM PST 24
Finished Mar 05 12:43:10 PM PST 24
Peak memory 192088 kb
Host smart-4fa2ad20-d347-4599-b32e-6bdccb65b43a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676541758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.676541758
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2044833277
Short name T118
Test name
Test status
Simulation time 15071514 ps
CPU time 0.59 seconds
Started Mar 05 12:42:46 PM PST 24
Finished Mar 05 12:42:46 PM PST 24
Peak memory 182716 kb
Host smart-09c8fa8a-0e25-4404-a558-1785c6b87516
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044833277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2044833277
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2081165898
Short name T574
Test name
Test status
Simulation time 109703043 ps
CPU time 1.37 seconds
Started Mar 05 12:43:16 PM PST 24
Finished Mar 05 12:43:20 PM PST 24
Peak memory 197524 kb
Host smart-79ac4a48-22d4-4c47-be1b-5b090d944dfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081165898 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2081165898
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3629993445
Short name T105
Test name
Test status
Simulation time 14589498 ps
CPU time 0.58 seconds
Started Mar 05 12:42:59 PM PST 24
Finished Mar 05 12:43:00 PM PST 24
Peak memory 182556 kb
Host smart-696e9c27-823c-4c60-b137-26ac82f239e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629993445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3629993445
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.856226104
Short name T542
Test name
Test status
Simulation time 13901852 ps
CPU time 0.54 seconds
Started Mar 05 12:42:47 PM PST 24
Finished Mar 05 12:42:48 PM PST 24
Peak memory 181880 kb
Host smart-11ceb326-2dd9-4530-a1f1-84e059bfd1cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856226104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.856226104
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.929666751
Short name T536
Test name
Test status
Simulation time 157801011 ps
CPU time 0.79 seconds
Started Mar 05 12:42:59 PM PST 24
Finished Mar 05 12:43:00 PM PST 24
Peak memory 193204 kb
Host smart-96648e93-d708-4ba0-95b7-d99e645cc283
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929666751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.929666751
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3963669400
Short name T462
Test name
Test status
Simulation time 503540741 ps
CPU time 2.73 seconds
Started Mar 05 12:42:55 PM PST 24
Finished Mar 05 12:42:58 PM PST 24
Peak memory 197644 kb
Host smart-1e756e7b-27ef-45e1-8cac-90f71a807c2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963669400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3963669400
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2562583254
Short name T474
Test name
Test status
Simulation time 78119438 ps
CPU time 0.85 seconds
Started Mar 05 12:43:16 PM PST 24
Finished Mar 05 12:43:19 PM PST 24
Peak memory 193476 kb
Host smart-b0ddd9dc-543d-4600-a591-70cabdbc9d99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562583254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2562583254
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3593408115
Short name T99
Test name
Test status
Simulation time 26120628 ps
CPU time 0.7 seconds
Started Mar 05 12:43:13 PM PST 24
Finished Mar 05 12:43:15 PM PST 24
Peak memory 191472 kb
Host smart-8636dd0f-7b41-456c-92b7-f9b24e37b0ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593408115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3593408115
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2635939003
Short name T511
Test name
Test status
Simulation time 71108046 ps
CPU time 1.38 seconds
Started Mar 05 12:42:53 PM PST 24
Finished Mar 05 12:42:55 PM PST 24
Peak memory 190984 kb
Host smart-857b167f-9e41-4422-9f58-76f17a645ff8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635939003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2635939003
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3604785903
Short name T100
Test name
Test status
Simulation time 54596817 ps
CPU time 0.62 seconds
Started Mar 05 12:43:11 PM PST 24
Finished Mar 05 12:43:12 PM PST 24
Peak memory 182640 kb
Host smart-07c13a7b-eba7-4e6f-926c-0c2ab55a2dec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604785903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3604785903
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.620205912
Short name T454
Test name
Test status
Simulation time 18577390 ps
CPU time 0.67 seconds
Started Mar 05 12:42:55 PM PST 24
Finished Mar 05 12:42:56 PM PST 24
Peak memory 194700 kb
Host smart-f1987f14-b9cc-4a06-8c57-5c574405559a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620205912 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.620205912
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2312912163
Short name T496
Test name
Test status
Simulation time 16832784 ps
CPU time 0.57 seconds
Started Mar 05 12:43:00 PM PST 24
Finished Mar 05 12:43:01 PM PST 24
Peak memory 182692 kb
Host smart-e407c246-eb25-461b-8e85-ed2cc7b3c97c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312912163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2312912163
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1813523860
Short name T503
Test name
Test status
Simulation time 12817494 ps
CPU time 0.53 seconds
Started Mar 05 12:43:01 PM PST 24
Finished Mar 05 12:43:02 PM PST 24
Peak memory 182064 kb
Host smart-233cbc56-407e-442a-991c-ec361ca018e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813523860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.1813523860
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3999383384
Short name T543
Test name
Test status
Simulation time 164866873 ps
CPU time 2.68 seconds
Started Mar 05 12:43:02 PM PST 24
Finished Mar 05 12:43:04 PM PST 24
Peak memory 197628 kb
Host smart-6fdbb604-630c-448b-a832-73de8f766956
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999383384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3999383384
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.767105477
Short name T516
Test name
Test status
Simulation time 210591741 ps
CPU time 0.77 seconds
Started Mar 05 12:43:00 PM PST 24
Finished Mar 05 12:43:01 PM PST 24
Peak memory 193328 kb
Host smart-c2bdb8d1-5a02-4ba4-bea7-8b823c715180
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767105477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.767105477
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1883262429
Short name T567
Test name
Test status
Simulation time 25873148 ps
CPU time 1.09 seconds
Started Mar 05 12:43:21 PM PST 24
Finished Mar 05 12:43:23 PM PST 24
Peak memory 197600 kb
Host smart-e3d94be1-b1c8-4965-be8b-fe914c6d2e09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883262429 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.1883262429
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2935716614
Short name T548
Test name
Test status
Simulation time 78661988 ps
CPU time 0.6 seconds
Started Mar 05 12:43:23 PM PST 24
Finished Mar 05 12:43:24 PM PST 24
Peak memory 182720 kb
Host smart-72c824fa-e09d-42a3-9292-e8a2de3e7235
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935716614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2935716614
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1711537421
Short name T566
Test name
Test status
Simulation time 92992217 ps
CPU time 0.55 seconds
Started Mar 05 12:43:17 PM PST 24
Finished Mar 05 12:43:19 PM PST 24
Peak memory 182444 kb
Host smart-54d74e8e-faad-4a91-822b-2144187959ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711537421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1711537421
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.198561161
Short name T520
Test name
Test status
Simulation time 16472091 ps
CPU time 0.6 seconds
Started Mar 05 12:43:14 PM PST 24
Finished Mar 05 12:43:15 PM PST 24
Peak memory 191164 kb
Host smart-2bed1619-e11a-4640-9dee-b5cfc1de0ff5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198561161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_ti
mer_same_csr_outstanding.198561161
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2405255881
Short name T463
Test name
Test status
Simulation time 32932491 ps
CPU time 0.98 seconds
Started Mar 05 12:43:37 PM PST 24
Finished Mar 05 12:43:38 PM PST 24
Peak memory 196688 kb
Host smart-434cb67b-f276-410d-8bc2-52f733608ce3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405255881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.2405255881
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3135600977
Short name T561
Test name
Test status
Simulation time 27324876 ps
CPU time 1.26 seconds
Started Mar 05 12:43:13 PM PST 24
Finished Mar 05 12:43:14 PM PST 24
Peak memory 197576 kb
Host smart-de7e8047-baa9-4bf0-90ca-e00b45fb825b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135600977 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.3135600977
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.831579991
Short name T523
Test name
Test status
Simulation time 75461896 ps
CPU time 0.55 seconds
Started Mar 05 12:43:13 PM PST 24
Finished Mar 05 12:43:14 PM PST 24
Peak memory 182768 kb
Host smart-8a1ee8e4-226b-41a0-b5cb-a8e795404702
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831579991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.831579991
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2316574118
Short name T515
Test name
Test status
Simulation time 18154070 ps
CPU time 0.53 seconds
Started Mar 05 12:43:10 PM PST 24
Finished Mar 05 12:43:11 PM PST 24
Peak memory 182048 kb
Host smart-a655942c-b022-4882-b7e6-ac5fad3df359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316574118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2316574118
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2707579115
Short name T575
Test name
Test status
Simulation time 18422846 ps
CPU time 0.6 seconds
Started Mar 05 12:43:26 PM PST 24
Finished Mar 05 12:43:27 PM PST 24
Peak memory 191376 kb
Host smart-609822d0-3684-41fc-ab8e-68b5a6064c6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707579115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2707579115
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.628828514
Short name T505
Test name
Test status
Simulation time 101908882 ps
CPU time 2.16 seconds
Started Mar 05 12:43:08 PM PST 24
Finished Mar 05 12:43:10 PM PST 24
Peak memory 197516 kb
Host smart-e4eb8b4c-960b-40f4-8b02-05aae61836a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628828514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.628828514
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3761214585
Short name T559
Test name
Test status
Simulation time 257149914 ps
CPU time 1.28 seconds
Started Mar 05 12:43:11 PM PST 24
Finished Mar 05 12:43:12 PM PST 24
Peak memory 195244 kb
Host smart-e64091a2-945f-4e42-a5e5-3e235dfb4af9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761214585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3761214585
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3821191970
Short name T525
Test name
Test status
Simulation time 95703967 ps
CPU time 1.53 seconds
Started Mar 05 12:43:17 PM PST 24
Finished Mar 05 12:43:20 PM PST 24
Peak memory 197624 kb
Host smart-28fb76b0-e272-4539-9305-3ede60840240
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821191970 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3821191970
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2991237309
Short name T507
Test name
Test status
Simulation time 16653802 ps
CPU time 0.55 seconds
Started Mar 05 12:43:23 PM PST 24
Finished Mar 05 12:43:24 PM PST 24
Peak memory 182760 kb
Host smart-2d5e51bd-9f38-4601-95e0-3aacd484cab1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991237309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2991237309
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2643349372
Short name T465
Test name
Test status
Simulation time 37743275 ps
CPU time 0.54 seconds
Started Mar 05 12:43:21 PM PST 24
Finished Mar 05 12:43:23 PM PST 24
Peak memory 182540 kb
Host smart-cf50c287-c3dd-4079-bd01-bd1e1faa66cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643349372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2643349372
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.381182157
Short name T560
Test name
Test status
Simulation time 52176340 ps
CPU time 0.7 seconds
Started Mar 05 12:43:17 PM PST 24
Finished Mar 05 12:43:19 PM PST 24
Peak memory 192712 kb
Host smart-063d3290-aaa4-4be7-8550-c188a24ea540
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381182157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_ti
mer_same_csr_outstanding.381182157
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2477898835
Short name T492
Test name
Test status
Simulation time 59514989 ps
CPU time 1.43 seconds
Started Mar 05 12:43:21 PM PST 24
Finished Mar 05 12:43:24 PM PST 24
Peak memory 197552 kb
Host smart-ab5e8c54-56b6-41a8-9cfa-4686fa72d604
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477898835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2477898835
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.4224546930
Short name T30
Test name
Test status
Simulation time 138805669 ps
CPU time 0.83 seconds
Started Mar 05 12:43:03 PM PST 24
Finished Mar 05 12:43:04 PM PST 24
Peak memory 193724 kb
Host smart-216f425b-7d37-46dd-b1ff-d0fc625e778f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224546930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.4224546930
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.501981078
Short name T493
Test name
Test status
Simulation time 43639076 ps
CPU time 0.96 seconds
Started Mar 05 12:43:03 PM PST 24
Finished Mar 05 12:43:04 PM PST 24
Peak memory 197332 kb
Host smart-7f9da5ed-51d1-492e-92e5-e3a3b2994dce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501981078 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.501981078
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2626634265
Short name T486
Test name
Test status
Simulation time 17876241 ps
CPU time 0.61 seconds
Started Mar 05 12:43:12 PM PST 24
Finished Mar 05 12:43:13 PM PST 24
Peak memory 182792 kb
Host smart-bbd7b11a-e63f-40c0-9542-ec0bc2daabd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626634265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2626634265
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3750837159
Short name T461
Test name
Test status
Simulation time 14175854 ps
CPU time 0.59 seconds
Started Mar 05 12:43:20 PM PST 24
Finished Mar 05 12:43:21 PM PST 24
Peak memory 182192 kb
Host smart-4e0bef98-be36-4ccf-aec7-686a46e5b558
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750837159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3750837159
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.4288831300
Short name T31
Test name
Test status
Simulation time 21182278 ps
CPU time 0.8 seconds
Started Mar 05 12:43:14 PM PST 24
Finished Mar 05 12:43:15 PM PST 24
Peak memory 191060 kb
Host smart-1019f0b7-78c7-4ccc-9f38-c97edb853e0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288831300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.4288831300
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.366518177
Short name T469
Test name
Test status
Simulation time 76478812 ps
CPU time 1.61 seconds
Started Mar 05 12:43:10 PM PST 24
Finished Mar 05 12:43:12 PM PST 24
Peak memory 197648 kb
Host smart-59b8368f-471d-40e2-a6b9-9097ee92d54e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366518177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.366518177
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3015054234
Short name T551
Test name
Test status
Simulation time 38393412 ps
CPU time 0.86 seconds
Started Mar 05 12:43:32 PM PST 24
Finished Mar 05 12:43:33 PM PST 24
Peak memory 196136 kb
Host smart-81452195-1255-413f-b526-fec23a09aa6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015054234 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.3015054234
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.4041556144
Short name T478
Test name
Test status
Simulation time 47257315 ps
CPU time 0.57 seconds
Started Mar 05 12:43:03 PM PST 24
Finished Mar 05 12:43:04 PM PST 24
Peak memory 182576 kb
Host smart-783bf420-ab00-4585-9f5f-dd64a068c740
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041556144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.4041556144
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.705939908
Short name T522
Test name
Test status
Simulation time 58773132 ps
CPU time 0.74 seconds
Started Mar 05 12:43:19 PM PST 24
Finished Mar 05 12:43:21 PM PST 24
Peak memory 191720 kb
Host smart-f96efb52-6ccb-40aa-a82e-41f36e778f9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705939908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.705939908
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3770743423
Short name T53
Test name
Test status
Simulation time 69327396 ps
CPU time 1.32 seconds
Started Mar 05 12:43:15 PM PST 24
Finished Mar 05 12:43:17 PM PST 24
Peak memory 197440 kb
Host smart-5cae711f-7069-4050-8679-0084d833fbd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770743423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3770743423
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.983107603
Short name T533
Test name
Test status
Simulation time 125942818 ps
CPU time 1.31 seconds
Started Mar 05 12:43:39 PM PST 24
Finished Mar 05 12:43:41 PM PST 24
Peak memory 183076 kb
Host smart-f9877af7-cdc0-4453-bbae-6e0d2a7c27da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983107603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_in
tg_err.983107603
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3869158313
Short name T508
Test name
Test status
Simulation time 166955024 ps
CPU time 0.78 seconds
Started Mar 05 12:43:10 PM PST 24
Finished Mar 05 12:43:11 PM PST 24
Peak memory 195436 kb
Host smart-5657b4ea-e6c6-466e-bf40-7403ec74180a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869158313 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3869158313
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2035228568
Short name T97
Test name
Test status
Simulation time 38374799 ps
CPU time 0.59 seconds
Started Mar 05 12:43:15 PM PST 24
Finished Mar 05 12:43:17 PM PST 24
Peak memory 182708 kb
Host smart-1d4ab818-715f-4f40-8706-de85debd9041
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035228568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2035228568
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2807707508
Short name T457
Test name
Test status
Simulation time 51130815 ps
CPU time 0.54 seconds
Started Mar 05 12:43:10 PM PST 24
Finished Mar 05 12:43:11 PM PST 24
Peak memory 182308 kb
Host smart-fedd5b4e-e180-4688-bcb7-1f78895ebf13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807707508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2807707508
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3365630170
Short name T555
Test name
Test status
Simulation time 88154711 ps
CPU time 0.73 seconds
Started Mar 05 12:43:15 PM PST 24
Finished Mar 05 12:43:15 PM PST 24
Peak memory 192972 kb
Host smart-e919a379-9a44-4221-b05e-358800e56a8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365630170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3365630170
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1244528157
Short name T529
Test name
Test status
Simulation time 51594742 ps
CPU time 1.16 seconds
Started Mar 05 12:43:06 PM PST 24
Finished Mar 05 12:43:08 PM PST 24
Peak memory 195172 kb
Host smart-4e047517-3d06-4171-9ff4-fd5f12ca754d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244528157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1244528157
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3285470341
Short name T572
Test name
Test status
Simulation time 324918396 ps
CPU time 1.37 seconds
Started Mar 05 12:43:13 PM PST 24
Finished Mar 05 12:43:14 PM PST 24
Peak memory 195004 kb
Host smart-59afb3d3-f2fc-4236-9f55-41b46436ac46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285470341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3285470341
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.797102445
Short name T483
Test name
Test status
Simulation time 18799717 ps
CPU time 0.85 seconds
Started Mar 05 12:43:23 PM PST 24
Finished Mar 05 12:43:24 PM PST 24
Peak memory 197448 kb
Host smart-69554cd5-284d-4334-8c7d-558c1b7deeb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797102445 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.797102445
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1346437327
Short name T55
Test name
Test status
Simulation time 215685248 ps
CPU time 0.58 seconds
Started Mar 05 12:43:16 PM PST 24
Finished Mar 05 12:43:17 PM PST 24
Peak memory 191956 kb
Host smart-23d7b5c4-48d4-4024-8f9e-c5387168443c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346437327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1346437327
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3722897535
Short name T526
Test name
Test status
Simulation time 18653444 ps
CPU time 0.53 seconds
Started Mar 05 12:43:27 PM PST 24
Finished Mar 05 12:43:27 PM PST 24
Peak memory 182176 kb
Host smart-c590d9a0-78fb-47c3-bb45-2787c3269cd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722897535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3722897535
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3258494643
Short name T521
Test name
Test status
Simulation time 13133166 ps
CPU time 0.59 seconds
Started Mar 05 12:43:05 PM PST 24
Finished Mar 05 12:43:07 PM PST 24
Peak memory 192000 kb
Host smart-ee174ca6-7af5-4f73-bc2d-4495fc7c08c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258494643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.3258494643
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2539109530
Short name T458
Test name
Test status
Simulation time 239554101 ps
CPU time 2.36 seconds
Started Mar 05 12:43:02 PM PST 24
Finished Mar 05 12:43:05 PM PST 24
Peak memory 197636 kb
Host smart-85e249b5-65cf-489c-b054-e1b2e7ea7e35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539109530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2539109530
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2027120698
Short name T120
Test name
Test status
Simulation time 476229767 ps
CPU time 1.43 seconds
Started Mar 05 12:43:17 PM PST 24
Finished Mar 05 12:43:19 PM PST 24
Peak memory 183236 kb
Host smart-4454de70-0927-43d7-b0b6-a5620dc7c248
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027120698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2027120698
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1694776643
Short name T546
Test name
Test status
Simulation time 112068871 ps
CPU time 1.29 seconds
Started Mar 05 12:43:18 PM PST 24
Finished Mar 05 12:43:21 PM PST 24
Peak memory 197560 kb
Host smart-5cee3c12-2cd9-4e41-a99d-5416bc1c96a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694776643 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1694776643
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3685358477
Short name T101
Test name
Test status
Simulation time 14337454 ps
CPU time 0.55 seconds
Started Mar 05 12:43:18 PM PST 24
Finished Mar 05 12:43:19 PM PST 24
Peak memory 182684 kb
Host smart-e0ea7b88-0fe3-4908-b2b8-6455e57b25c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685358477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.3685358477
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1312999893
Short name T468
Test name
Test status
Simulation time 32428199 ps
CPU time 0.57 seconds
Started Mar 05 12:43:21 PM PST 24
Finished Mar 05 12:43:23 PM PST 24
Peak memory 182588 kb
Host smart-eaa17d4d-3100-44ee-9967-979339faf359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312999893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1312999893
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1228039916
Short name T556
Test name
Test status
Simulation time 75610778 ps
CPU time 0.79 seconds
Started Mar 05 12:43:27 PM PST 24
Finished Mar 05 12:43:28 PM PST 24
Peak memory 193236 kb
Host smart-58a84d60-fbaf-4337-9cb0-b4832b1dc1ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228039916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.1228039916
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2065991759
Short name T571
Test name
Test status
Simulation time 159741510 ps
CPU time 0.95 seconds
Started Mar 05 12:43:04 PM PST 24
Finished Mar 05 12:43:05 PM PST 24
Peak memory 196744 kb
Host smart-347a6b00-a2fe-4503-8141-504098facb56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065991759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2065991759
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.111165481
Short name T481
Test name
Test status
Simulation time 69223241 ps
CPU time 0.77 seconds
Started Mar 05 12:43:33 PM PST 24
Finished Mar 05 12:43:34 PM PST 24
Peak memory 193376 kb
Host smart-46db9cb3-cad8-40e7-a7a5-48b6fcf0f0ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111165481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in
tg_err.111165481
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.4244512959
Short name T470
Test name
Test status
Simulation time 55051900 ps
CPU time 0.69 seconds
Started Mar 05 12:43:32 PM PST 24
Finished Mar 05 12:43:32 PM PST 24
Peak memory 195312 kb
Host smart-334ecdc2-01cb-4c1c-9085-acc034e5298e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244512959 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.4244512959
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1779617405
Short name T66
Test name
Test status
Simulation time 51612988 ps
CPU time 0.58 seconds
Started Mar 05 12:43:19 PM PST 24
Finished Mar 05 12:43:21 PM PST 24
Peak memory 182708 kb
Host smart-3eb95b04-7b7a-4030-8cd0-329b87d45bcd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779617405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1779617405
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.986166841
Short name T500
Test name
Test status
Simulation time 17597278 ps
CPU time 0.55 seconds
Started Mar 05 12:43:17 PM PST 24
Finished Mar 05 12:43:19 PM PST 24
Peak memory 182620 kb
Host smart-67366fc5-2246-4b7f-aa4e-1ebc6c7dc4d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986166841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.986166841
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.458487203
Short name T95
Test name
Test status
Simulation time 68580813 ps
CPU time 0.73 seconds
Started Mar 05 12:43:15 PM PST 24
Finished Mar 05 12:43:20 PM PST 24
Peak memory 191528 kb
Host smart-3a00eae4-8836-4541-89c9-4043de207ca3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458487203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_ti
mer_same_csr_outstanding.458487203
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3273062495
Short name T518
Test name
Test status
Simulation time 207104832 ps
CPU time 1.98 seconds
Started Mar 05 12:43:25 PM PST 24
Finished Mar 05 12:43:27 PM PST 24
Peak memory 197280 kb
Host smart-cf67c887-c5c6-4003-95dc-61a1161732ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273062495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3273062495
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2323299194
Short name T537
Test name
Test status
Simulation time 133063027 ps
CPU time 1.38 seconds
Started Mar 05 12:43:14 PM PST 24
Finished Mar 05 12:43:15 PM PST 24
Peak memory 195356 kb
Host smart-505fdc44-b8fb-4277-b7ef-4c296a9a4862
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323299194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.2323299194
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.4024416808
Short name T539
Test name
Test status
Simulation time 21738694 ps
CPU time 0.71 seconds
Started Mar 05 12:43:25 PM PST 24
Finished Mar 05 12:43:26 PM PST 24
Peak memory 194348 kb
Host smart-bae1cddc-00f4-47a7-aba9-22a332c54f36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024416808 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.4024416808
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.332243084
Short name T102
Test name
Test status
Simulation time 30453891 ps
CPU time 0.59 seconds
Started Mar 05 12:43:15 PM PST 24
Finished Mar 05 12:43:19 PM PST 24
Peak memory 182720 kb
Host smart-73288a5b-844d-45ae-a74b-6e9f5522433b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332243084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.332243084
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.4193184820
Short name T498
Test name
Test status
Simulation time 46079990 ps
CPU time 0.55 seconds
Started Mar 05 12:43:31 PM PST 24
Finished Mar 05 12:43:32 PM PST 24
Peak memory 181900 kb
Host smart-2c65b93b-535f-4db0-908f-f45ee9289df7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193184820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.4193184820
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1186194230
Short name T528
Test name
Test status
Simulation time 208294356 ps
CPU time 0.58 seconds
Started Mar 05 12:43:08 PM PST 24
Finished Mar 05 12:43:09 PM PST 24
Peak memory 191436 kb
Host smart-77e2e408-193d-44c4-96e6-9369e7b007f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186194230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.1186194230
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2960957163
Short name T495
Test name
Test status
Simulation time 149328881 ps
CPU time 2.91 seconds
Started Mar 05 12:43:18 PM PST 24
Finished Mar 05 12:43:23 PM PST 24
Peak memory 197516 kb
Host smart-14c5874a-4fb9-4f2d-96b4-48782c6b705f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960957163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2960957163
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.4122617207
Short name T123
Test name
Test status
Simulation time 197949028 ps
CPU time 1.4 seconds
Started Mar 05 12:43:30 PM PST 24
Finished Mar 05 12:43:31 PM PST 24
Peak memory 183424 kb
Host smart-85b6b682-6c8b-4874-8bc5-e27c59196715
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122617207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.4122617207
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.4001799355
Short name T106
Test name
Test status
Simulation time 50480999 ps
CPU time 0.75 seconds
Started Mar 05 12:42:49 PM PST 24
Finished Mar 05 12:42:50 PM PST 24
Peak memory 192412 kb
Host smart-18770985-72b0-4799-816d-d1a8aee26a66
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001799355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.4001799355
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.4229034964
Short name T549
Test name
Test status
Simulation time 461125250 ps
CPU time 2.75 seconds
Started Mar 05 12:42:52 PM PST 24
Finished Mar 05 12:43:00 PM PST 24
Peak memory 193612 kb
Host smart-0a0634e3-5abf-415c-856e-ccea36329e9f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229034964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.4229034964
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3632920858
Short name T104
Test name
Test status
Simulation time 137823584 ps
CPU time 0.62 seconds
Started Mar 05 12:42:53 PM PST 24
Finished Mar 05 12:42:54 PM PST 24
Peak memory 182724 kb
Host smart-0d75f995-0813-4564-a894-6fce0a2a1d45
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632920858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.3632920858
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.4086869815
Short name T564
Test name
Test status
Simulation time 49046314 ps
CPU time 0.76 seconds
Started Mar 05 12:43:01 PM PST 24
Finished Mar 05 12:43:02 PM PST 24
Peak memory 195192 kb
Host smart-d2310742-d11e-47e3-a0f4-979092e64078
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086869815 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.4086869815
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2031609559
Short name T563
Test name
Test status
Simulation time 50321122 ps
CPU time 0.61 seconds
Started Mar 05 12:42:53 PM PST 24
Finished Mar 05 12:42:54 PM PST 24
Peak memory 182680 kb
Host smart-035fad86-b8a7-49e2-9424-a5bb73792d2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031609559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2031609559
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3027218521
Short name T573
Test name
Test status
Simulation time 14967978 ps
CPU time 0.62 seconds
Started Mar 05 12:42:54 PM PST 24
Finished Mar 05 12:42:55 PM PST 24
Peak memory 182476 kb
Host smart-8ef9523d-3033-4808-b40d-811684e17f47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027218521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3027218521
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.144144283
Short name T532
Test name
Test status
Simulation time 126960114 ps
CPU time 0.84 seconds
Started Mar 05 12:42:59 PM PST 24
Finished Mar 05 12:43:00 PM PST 24
Peak memory 191728 kb
Host smart-a0b574da-1117-4d0d-ac65-a1164a0482e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144144283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_tim
er_same_csr_outstanding.144144283
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2255789582
Short name T519
Test name
Test status
Simulation time 226688718 ps
CPU time 2 seconds
Started Mar 05 12:43:07 PM PST 24
Finished Mar 05 12:43:09 PM PST 24
Peak memory 197476 kb
Host smart-2e75a846-d997-4447-be2e-22083d4683f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255789582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2255789582
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2875266046
Short name T122
Test name
Test status
Simulation time 109280254 ps
CPU time 1.04 seconds
Started Mar 05 12:43:01 PM PST 24
Finished Mar 05 12:43:02 PM PST 24
Peak memory 183024 kb
Host smart-b5381f0c-0ed8-4558-bcb2-d4bed9c2021d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875266046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2875266046
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1384451617
Short name T553
Test name
Test status
Simulation time 18691402 ps
CPU time 0.57 seconds
Started Mar 05 12:43:25 PM PST 24
Finished Mar 05 12:43:26 PM PST 24
Peak memory 182576 kb
Host smart-2ac3be49-92fe-49bc-ad83-aa47c1068489
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384451617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1384451617
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1424166750
Short name T494
Test name
Test status
Simulation time 22114688 ps
CPU time 0.56 seconds
Started Mar 05 12:43:24 PM PST 24
Finished Mar 05 12:43:24 PM PST 24
Peak memory 182532 kb
Host smart-4b2d2895-15a6-4d37-9710-6081dfd514ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424166750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1424166750
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3664591068
Short name T487
Test name
Test status
Simulation time 85686091 ps
CPU time 0.52 seconds
Started Mar 05 12:43:21 PM PST 24
Finished Mar 05 12:43:22 PM PST 24
Peak memory 181840 kb
Host smart-5626946f-d8bc-4bcd-83d0-791f4fd6d0e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664591068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3664591068
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.132823149
Short name T517
Test name
Test status
Simulation time 19771145 ps
CPU time 0.55 seconds
Started Mar 05 12:43:19 PM PST 24
Finished Mar 05 12:43:20 PM PST 24
Peak memory 182376 kb
Host smart-cb092ab8-a40f-40c4-9e6a-daa27c67e2d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132823149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.132823149
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1128679532
Short name T524
Test name
Test status
Simulation time 17065726 ps
CPU time 0.55 seconds
Started Mar 05 12:43:29 PM PST 24
Finished Mar 05 12:43:30 PM PST 24
Peak memory 182448 kb
Host smart-50d49ac9-cc6a-4e65-a927-80f080425ac9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128679532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1128679532
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1287599318
Short name T488
Test name
Test status
Simulation time 28747024 ps
CPU time 0.57 seconds
Started Mar 05 12:43:09 PM PST 24
Finished Mar 05 12:43:10 PM PST 24
Peak memory 182600 kb
Host smart-14cc731f-ce25-4611-bff9-3a3cbc86c849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287599318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1287599318
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1724854416
Short name T480
Test name
Test status
Simulation time 15182456 ps
CPU time 0.58 seconds
Started Mar 05 12:43:22 PM PST 24
Finished Mar 05 12:43:23 PM PST 24
Peak memory 182012 kb
Host smart-95266a88-1c30-46ec-847f-2adcbb6e8652
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724854416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1724854416
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2869648071
Short name T475
Test name
Test status
Simulation time 11972326 ps
CPU time 0.53 seconds
Started Mar 05 12:43:04 PM PST 24
Finished Mar 05 12:43:04 PM PST 24
Peak memory 182212 kb
Host smart-390065b7-3dec-436e-9ace-e23d09776f5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869648071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2869648071
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2769671195
Short name T569
Test name
Test status
Simulation time 16583056 ps
CPU time 0.57 seconds
Started Mar 05 12:43:13 PM PST 24
Finished Mar 05 12:43:13 PM PST 24
Peak memory 182452 kb
Host smart-ae470ac3-9b3b-4d75-a2a0-67ab802c63e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769671195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2769671195
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3858685829
Short name T514
Test name
Test status
Simulation time 25071121 ps
CPU time 0.54 seconds
Started Mar 05 12:43:21 PM PST 24
Finished Mar 05 12:43:22 PM PST 24
Peak memory 182536 kb
Host smart-02f1ffde-032b-4c35-aa48-1ba8462b48ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858685829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3858685829
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1600644167
Short name T107
Test name
Test status
Simulation time 24336968 ps
CPU time 0.61 seconds
Started Mar 05 12:42:48 PM PST 24
Finished Mar 05 12:42:49 PM PST 24
Peak memory 182528 kb
Host smart-3ce48503-69fe-4f4d-bede-9284d977b76e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600644167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.1600644167
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.350605376
Short name T534
Test name
Test status
Simulation time 238888061 ps
CPU time 2.33 seconds
Started Mar 05 12:43:12 PM PST 24
Finished Mar 05 12:43:15 PM PST 24
Peak memory 193496 kb
Host smart-9d80cef0-c57b-4ae0-9dfb-017de2042745
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350605376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.350605376
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3446474054
Short name T544
Test name
Test status
Simulation time 38287864 ps
CPU time 0.61 seconds
Started Mar 05 12:43:10 PM PST 24
Finished Mar 05 12:43:11 PM PST 24
Peak memory 182192 kb
Host smart-ec5587ec-572a-435c-8d59-086a67016475
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446474054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3446474054
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3175322859
Short name T506
Test name
Test status
Simulation time 68748409 ps
CPU time 0.96 seconds
Started Mar 05 12:43:10 PM PST 24
Finished Mar 05 12:43:11 PM PST 24
Peak memory 197400 kb
Host smart-1cb4f729-572e-49a2-a190-e08750dbdbf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175322859 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.3175322859
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.24978899
Short name T54
Test name
Test status
Simulation time 22042012 ps
CPU time 0.57 seconds
Started Mar 05 12:43:12 PM PST 24
Finished Mar 05 12:43:13 PM PST 24
Peak memory 182696 kb
Host smart-639de01d-3166-46f2-af72-6850920a1d1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24978899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.24978899
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3269227761
Short name T550
Test name
Test status
Simulation time 47781621 ps
CPU time 0.58 seconds
Started Mar 05 12:43:06 PM PST 24
Finished Mar 05 12:43:07 PM PST 24
Peak memory 182572 kb
Host smart-59042fbe-4e9a-4e97-8fb0-55ebc67e9ded
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269227761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3269227761
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3393778148
Short name T67
Test name
Test status
Simulation time 101769932 ps
CPU time 0.69 seconds
Started Mar 05 12:43:09 PM PST 24
Finished Mar 05 12:43:10 PM PST 24
Peak memory 192112 kb
Host smart-8f31b3a7-ae2c-4cd3-a64a-5a7efca56ea8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393778148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3393778148
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.130074315
Short name T467
Test name
Test status
Simulation time 1410328052 ps
CPU time 2.45 seconds
Started Mar 05 12:42:50 PM PST 24
Finished Mar 05 12:42:54 PM PST 24
Peak memory 197584 kb
Host smart-daa967b4-095e-465f-aa84-ff01581545ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130074315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.130074315
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.660711303
Short name T29
Test name
Test status
Simulation time 363160708 ps
CPU time 1.34 seconds
Started Mar 05 12:43:10 PM PST 24
Finished Mar 05 12:43:11 PM PST 24
Peak memory 183388 kb
Host smart-7ccf4333-666c-4c6e-af89-cc6fd617896b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660711303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_int
g_err.660711303
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3060838235
Short name T489
Test name
Test status
Simulation time 29524623 ps
CPU time 0.57 seconds
Started Mar 05 12:43:18 PM PST 24
Finished Mar 05 12:43:20 PM PST 24
Peak memory 182624 kb
Host smart-df2a9898-06e1-40da-9fb1-7d1fb87dc858
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060838235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3060838235
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1214661106
Short name T576
Test name
Test status
Simulation time 95696102 ps
CPU time 0.52 seconds
Started Mar 05 12:43:22 PM PST 24
Finished Mar 05 12:43:23 PM PST 24
Peak memory 182552 kb
Host smart-890b4077-046f-487b-b34c-57ec438f823a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214661106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1214661106
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.251796186
Short name T497
Test name
Test status
Simulation time 14061705 ps
CPU time 0.62 seconds
Started Mar 05 12:43:13 PM PST 24
Finished Mar 05 12:43:15 PM PST 24
Peak memory 182448 kb
Host smart-b339158c-ea3d-4e23-aa48-0520f364c52b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251796186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.251796186
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2448709750
Short name T509
Test name
Test status
Simulation time 18175698 ps
CPU time 0.54 seconds
Started Mar 05 12:43:10 PM PST 24
Finished Mar 05 12:43:10 PM PST 24
Peak memory 182024 kb
Host smart-3b5f946e-729b-424d-a1e5-8aed5289ed73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448709750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.2448709750
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.4041229956
Short name T504
Test name
Test status
Simulation time 56271078 ps
CPU time 0.58 seconds
Started Mar 05 12:43:23 PM PST 24
Finished Mar 05 12:43:24 PM PST 24
Peak memory 182588 kb
Host smart-11a3f6b9-9140-4aa0-b714-45c4fbe75ace
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041229956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.4041229956
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3691044970
Short name T460
Test name
Test status
Simulation time 54128679 ps
CPU time 0.56 seconds
Started Mar 05 12:43:22 PM PST 24
Finished Mar 05 12:43:23 PM PST 24
Peak memory 182524 kb
Host smart-f6604a24-b878-4e55-bfe4-5cdd5af72c91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691044970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3691044970
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1944102654
Short name T545
Test name
Test status
Simulation time 11272789 ps
CPU time 0.54 seconds
Started Mar 05 12:43:09 PM PST 24
Finished Mar 05 12:43:15 PM PST 24
Peak memory 182552 kb
Host smart-56ed46f3-f6db-414a-bbad-a928a5318aba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944102654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1944102654
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.200863663
Short name T558
Test name
Test status
Simulation time 34870155 ps
CPU time 0.53 seconds
Started Mar 05 12:43:28 PM PST 24
Finished Mar 05 12:43:29 PM PST 24
Peak memory 182084 kb
Host smart-576c3a96-81b5-4518-93cc-8e3c6f4d9c87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200863663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.200863663
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2061826028
Short name T530
Test name
Test status
Simulation time 15789518 ps
CPU time 0.54 seconds
Started Mar 05 12:43:12 PM PST 24
Finished Mar 05 12:43:12 PM PST 24
Peak memory 182532 kb
Host smart-bcb69035-0b00-498c-965b-9cc35750d6d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061826028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2061826028
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.234535456
Short name T477
Test name
Test status
Simulation time 50829623 ps
CPU time 0.55 seconds
Started Mar 05 12:43:35 PM PST 24
Finished Mar 05 12:43:35 PM PST 24
Peak memory 182460 kb
Host smart-c51a0985-5213-4744-8ba8-a9b6b7ae003f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234535456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.234535456
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1352694481
Short name T103
Test name
Test status
Simulation time 54764067 ps
CPU time 0.77 seconds
Started Mar 05 12:43:01 PM PST 24
Finished Mar 05 12:43:02 PM PST 24
Peak memory 192404 kb
Host smart-4ea84bb1-33e8-47ef-8fd6-806de549b494
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352694481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1352694481
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1681648553
Short name T52
Test name
Test status
Simulation time 134804896 ps
CPU time 1.63 seconds
Started Mar 05 12:43:05 PM PST 24
Finished Mar 05 12:43:08 PM PST 24
Peak memory 182920 kb
Host smart-f0651d97-8dd0-41d3-a7a1-e21bb8580b6d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681648553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.1681648553
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2866713386
Short name T484
Test name
Test status
Simulation time 80837468 ps
CPU time 0.55 seconds
Started Mar 05 12:43:04 PM PST 24
Finished Mar 05 12:43:05 PM PST 24
Peak memory 182736 kb
Host smart-77f10760-4939-40fb-86e6-4be6279c7df5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866713386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2866713386
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.67951180
Short name T32
Test name
Test status
Simulation time 39984243 ps
CPU time 0.96 seconds
Started Mar 05 12:43:16 PM PST 24
Finished Mar 05 12:43:18 PM PST 24
Peak memory 197428 kb
Host smart-7fa2a466-0afb-418d-9e6c-8d902e4ab504
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67951180 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.67951180
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.4220523315
Short name T541
Test name
Test status
Simulation time 29468053 ps
CPU time 0.57 seconds
Started Mar 05 12:43:04 PM PST 24
Finished Mar 05 12:43:04 PM PST 24
Peak memory 182712 kb
Host smart-c866c950-721d-4237-8272-f5f6e73edd26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220523315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.4220523315
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.303484229
Short name T512
Test name
Test status
Simulation time 13911414 ps
CPU time 0.54 seconds
Started Mar 05 12:43:04 PM PST 24
Finished Mar 05 12:43:05 PM PST 24
Peak memory 182040 kb
Host smart-b792d1c4-796e-46b0-9724-53d088bc682a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303484229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.303484229
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.464227145
Short name T93
Test name
Test status
Simulation time 15074407 ps
CPU time 0.68 seconds
Started Mar 05 12:43:21 PM PST 24
Finished Mar 05 12:43:22 PM PST 24
Peak memory 191752 kb
Host smart-3b854cfc-1db5-4cf4-a950-da47650d263a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464227145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.464227145
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2761411974
Short name T501
Test name
Test status
Simulation time 122265754 ps
CPU time 2.85 seconds
Started Mar 05 12:43:12 PM PST 24
Finished Mar 05 12:43:16 PM PST 24
Peak memory 197548 kb
Host smart-911e9736-9614-4abb-8937-8f974aa9f449
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761411974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2761411974
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.90910384
Short name T473
Test name
Test status
Simulation time 135887074 ps
CPU time 1.07 seconds
Started Mar 05 12:43:21 PM PST 24
Finished Mar 05 12:43:22 PM PST 24
Peak memory 183404 kb
Host smart-234993bc-4c43-47e0-8dff-15a07e1f42dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90910384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_intg
_err.90910384
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1892626453
Short name T547
Test name
Test status
Simulation time 89086347 ps
CPU time 0.55 seconds
Started Mar 05 12:43:25 PM PST 24
Finished Mar 05 12:43:26 PM PST 24
Peak memory 182556 kb
Host smart-10b7ac42-aaa8-44b9-82a8-46ac82511b75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892626453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1892626453
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2369412695
Short name T471
Test name
Test status
Simulation time 76636280 ps
CPU time 0.56 seconds
Started Mar 05 12:43:21 PM PST 24
Finished Mar 05 12:43:27 PM PST 24
Peak memory 182564 kb
Host smart-034d91ca-959e-4e3e-9882-008930ccf7a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369412695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2369412695
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.304850981
Short name T510
Test name
Test status
Simulation time 81979756 ps
CPU time 0.55 seconds
Started Mar 05 12:43:23 PM PST 24
Finished Mar 05 12:43:24 PM PST 24
Peak memory 182488 kb
Host smart-1917bd11-9622-4c12-a39f-c8992bbea2c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304850981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.304850981
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3916919998
Short name T527
Test name
Test status
Simulation time 34972739 ps
CPU time 0.52 seconds
Started Mar 05 12:43:35 PM PST 24
Finished Mar 05 12:43:36 PM PST 24
Peak memory 181976 kb
Host smart-2a7c30e1-5411-44d3-942f-51cdd790a1b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916919998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3916919998
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.576519658
Short name T557
Test name
Test status
Simulation time 10998741 ps
CPU time 0.53 seconds
Started Mar 05 12:43:23 PM PST 24
Finished Mar 05 12:43:24 PM PST 24
Peak memory 181980 kb
Host smart-83518389-c3c7-4f78-95a3-1f7d453349e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576519658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.576519658
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.386150098
Short name T459
Test name
Test status
Simulation time 20184759 ps
CPU time 0.53 seconds
Started Mar 05 12:43:21 PM PST 24
Finished Mar 05 12:43:23 PM PST 24
Peak memory 181968 kb
Host smart-2214576f-12b7-4bb9-8fe7-2fb976ce6a72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386150098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.386150098
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3160550122
Short name T513
Test name
Test status
Simulation time 14276723 ps
CPU time 0.54 seconds
Started Mar 05 12:43:22 PM PST 24
Finished Mar 05 12:43:23 PM PST 24
Peak memory 181968 kb
Host smart-886a98a2-031a-4a9a-b8b4-dcba8be83c48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160550122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3160550122
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3565528728
Short name T538
Test name
Test status
Simulation time 172742108 ps
CPU time 0.55 seconds
Started Mar 05 12:43:23 PM PST 24
Finished Mar 05 12:43:24 PM PST 24
Peak memory 182452 kb
Host smart-19a9890c-dac3-46f9-b31d-8158e7be8a20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565528728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3565528728
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3651328909
Short name T455
Test name
Test status
Simulation time 23054919 ps
CPU time 0.53 seconds
Started Mar 05 12:43:44 PM PST 24
Finished Mar 05 12:43:45 PM PST 24
Peak memory 181792 kb
Host smart-88f639e6-8195-4716-9ef3-9fe32e4c7652
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651328909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3651328909
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3263571085
Short name T485
Test name
Test status
Simulation time 51355525 ps
CPU time 0.52 seconds
Started Mar 05 12:43:22 PM PST 24
Finished Mar 05 12:43:23 PM PST 24
Peak memory 182560 kb
Host smart-5d82ecb5-0b14-43e6-8c9a-a3d4d4a87cef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263571085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3263571085
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3837710660
Short name T570
Test name
Test status
Simulation time 35736715 ps
CPU time 0.85 seconds
Started Mar 05 12:43:13 PM PST 24
Finished Mar 05 12:43:14 PM PST 24
Peak memory 196196 kb
Host smart-aa9b8dea-6999-4080-8f6b-fa413b1c0f96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837710660 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.3837710660
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2575235126
Short name T568
Test name
Test status
Simulation time 13845810 ps
CPU time 0.62 seconds
Started Mar 05 12:43:13 PM PST 24
Finished Mar 05 12:43:13 PM PST 24
Peak memory 182712 kb
Host smart-ff811585-b56d-4020-91dc-f2a64b6dc47c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575235126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2575235126
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1979886968
Short name T531
Test name
Test status
Simulation time 32205634 ps
CPU time 0.53 seconds
Started Mar 05 12:43:01 PM PST 24
Finished Mar 05 12:43:02 PM PST 24
Peak memory 181992 kb
Host smart-0e92dd5c-a441-4670-8f46-ab67095a46ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979886968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1979886968
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.783030036
Short name T108
Test name
Test status
Simulation time 36056921 ps
CPU time 0.84 seconds
Started Mar 05 12:42:59 PM PST 24
Finished Mar 05 12:43:00 PM PST 24
Peak memory 194532 kb
Host smart-a6720adf-fdbf-4ae5-8b90-d59841e31182
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783030036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_tim
er_same_csr_outstanding.783030036
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3203394998
Short name T554
Test name
Test status
Simulation time 1184642986 ps
CPU time 1.96 seconds
Started Mar 05 12:42:50 PM PST 24
Finished Mar 05 12:42:54 PM PST 24
Peak memory 197604 kb
Host smart-eab96d55-5a6b-4edd-bef6-efbd8f8b7476
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203394998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3203394998
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.4147696528
Short name T562
Test name
Test status
Simulation time 324591945 ps
CPU time 0.8 seconds
Started Mar 05 12:43:12 PM PST 24
Finished Mar 05 12:43:14 PM PST 24
Peak memory 182964 kb
Host smart-5706ab8e-e989-4ef2-a7ed-cf5f4cdad49b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147696528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.4147696528
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1141987890
Short name T491
Test name
Test status
Simulation time 52738494 ps
CPU time 0.79 seconds
Started Mar 05 12:43:05 PM PST 24
Finished Mar 05 12:43:06 PM PST 24
Peak memory 196336 kb
Host smart-64f4c9be-ed5a-485a-9490-7b953567a762
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141987890 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1141987890
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.4041086740
Short name T479
Test name
Test status
Simulation time 13483385 ps
CPU time 0.57 seconds
Started Mar 05 12:43:10 PM PST 24
Finished Mar 05 12:43:11 PM PST 24
Peak memory 182740 kb
Host smart-3ce49670-d930-49b8-a8c2-1d322f7a8b4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041086740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.4041086740
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.647244503
Short name T453
Test name
Test status
Simulation time 29372790 ps
CPU time 0.59 seconds
Started Mar 05 12:43:11 PM PST 24
Finished Mar 05 12:43:12 PM PST 24
Peak memory 182520 kb
Host smart-ab844a0d-a97b-4414-8eae-a3af6b495548
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647244503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.647244503
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3476301250
Short name T33
Test name
Test status
Simulation time 51129501 ps
CPU time 0.71 seconds
Started Mar 05 12:43:02 PM PST 24
Finished Mar 05 12:43:03 PM PST 24
Peak memory 193104 kb
Host smart-ec6f22a4-cee2-4cac-a966-ea2f022404db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476301250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3476301250
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1181131298
Short name T456
Test name
Test status
Simulation time 101273475 ps
CPU time 1.28 seconds
Started Mar 05 12:43:27 PM PST 24
Finished Mar 05 12:43:29 PM PST 24
Peak memory 197592 kb
Host smart-1e6a5164-4d95-4c33-851e-0200a15d0727
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181131298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1181131298
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.26409987
Short name T121
Test name
Test status
Simulation time 244170417 ps
CPU time 1.15 seconds
Started Mar 05 12:43:11 PM PST 24
Finished Mar 05 12:43:12 PM PST 24
Peak memory 195008 kb
Host smart-b6d9bb4a-caf2-480c-918d-a0ca27a29fbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26409987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_intg
_err.26409987
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.730524910
Short name T535
Test name
Test status
Simulation time 165291788 ps
CPU time 1.15 seconds
Started Mar 05 12:43:17 PM PST 24
Finished Mar 05 12:43:19 PM PST 24
Peak memory 197532 kb
Host smart-ab0f8386-ff3b-4f6a-a4aa-798f9275992c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730524910 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.730524910
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.4248236297
Short name T57
Test name
Test status
Simulation time 12194731 ps
CPU time 0.55 seconds
Started Mar 05 12:43:01 PM PST 24
Finished Mar 05 12:43:02 PM PST 24
Peak memory 182656 kb
Host smart-74c9764d-1cf9-494c-9359-09ce04f30c61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248236297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.4248236297
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2221276126
Short name T499
Test name
Test status
Simulation time 13460086 ps
CPU time 0.52 seconds
Started Mar 05 12:43:08 PM PST 24
Finished Mar 05 12:43:09 PM PST 24
Peak memory 181976 kb
Host smart-887dc2dd-232a-44d7-8a20-4b174e7fd96f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221276126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2221276126
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3571242917
Short name T110
Test name
Test status
Simulation time 54856740 ps
CPU time 0.66 seconds
Started Mar 05 12:43:12 PM PST 24
Finished Mar 05 12:43:13 PM PST 24
Peak memory 191956 kb
Host smart-e282b3a3-6274-48e3-9e50-bcb7bde90919
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571242917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3571242917
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2167058291
Short name T502
Test name
Test status
Simulation time 570486208 ps
CPU time 2.6 seconds
Started Mar 05 12:43:15 PM PST 24
Finished Mar 05 12:43:19 PM PST 24
Peak memory 196280 kb
Host smart-f49f670c-ecba-4c3d-be76-8507681bf5f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167058291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2167058291
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.953578249
Short name T565
Test name
Test status
Simulation time 294690458 ps
CPU time 1.1 seconds
Started Mar 05 12:43:08 PM PST 24
Finished Mar 05 12:43:10 PM PST 24
Peak memory 193916 kb
Host smart-6a0c7dbd-055a-4d2c-b150-8e6a2ab6dae3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953578249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int
g_err.953578249
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3802560429
Short name T476
Test name
Test status
Simulation time 86200319 ps
CPU time 1.11 seconds
Started Mar 05 12:43:17 PM PST 24
Finished Mar 05 12:43:19 PM PST 24
Peak memory 197612 kb
Host smart-19c68f28-0298-408d-a55e-a55e921c15a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802560429 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3802560429
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2549660646
Short name T98
Test name
Test status
Simulation time 203878980 ps
CPU time 0.56 seconds
Started Mar 05 12:42:50 PM PST 24
Finished Mar 05 12:42:51 PM PST 24
Peak memory 191840 kb
Host smart-c7397cd0-7945-4e2b-b892-16f5e3aa5625
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549660646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2549660646
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1296697446
Short name T452
Test name
Test status
Simulation time 21436238 ps
CPU time 0.55 seconds
Started Mar 05 12:43:23 PM PST 24
Finished Mar 05 12:43:24 PM PST 24
Peak memory 182548 kb
Host smart-817527a3-eae4-49d3-bb9b-e6e494c2fdc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296697446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1296697446
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.477353111
Short name T96
Test name
Test status
Simulation time 32989482 ps
CPU time 0.78 seconds
Started Mar 05 12:42:59 PM PST 24
Finished Mar 05 12:43:00 PM PST 24
Peak memory 191724 kb
Host smart-5f2ade13-6a06-4ae3-aef6-7dcd76c84dc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477353111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim
er_same_csr_outstanding.477353111
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.4173145676
Short name T464
Test name
Test status
Simulation time 289569827 ps
CPU time 1.73 seconds
Started Mar 05 12:42:51 PM PST 24
Finished Mar 05 12:42:53 PM PST 24
Peak memory 197644 kb
Host smart-09ab23d7-d765-4e12-9d0d-82794fda5948
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173145676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.4173145676
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3367701151
Short name T540
Test name
Test status
Simulation time 1030293482 ps
CPU time 1.06 seconds
Started Mar 05 12:43:16 PM PST 24
Finished Mar 05 12:43:18 PM PST 24
Peak memory 182896 kb
Host smart-4ac7cee8-47a9-45e1-8326-86e9dcaeee7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367701151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.3367701151
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3486719786
Short name T472
Test name
Test status
Simulation time 109682872 ps
CPU time 0.83 seconds
Started Mar 05 12:43:02 PM PST 24
Finished Mar 05 12:43:03 PM PST 24
Peak memory 197240 kb
Host smart-736cb1b2-189d-4732-86a9-adfe8ce17b82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486719786 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3486719786
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2832436166
Short name T490
Test name
Test status
Simulation time 25768410 ps
CPU time 0.54 seconds
Started Mar 05 12:43:03 PM PST 24
Finished Mar 05 12:43:04 PM PST 24
Peak memory 182212 kb
Host smart-572d238d-7191-4f40-aaeb-e999b41d75ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832436166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2832436166
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1048968321
Short name T482
Test name
Test status
Simulation time 62522203 ps
CPU time 0.59 seconds
Started Mar 05 12:43:03 PM PST 24
Finished Mar 05 12:43:03 PM PST 24
Peak memory 182600 kb
Host smart-d7f0f17e-1319-4401-9aed-4b9c4d8ff32d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048968321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1048968321
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.58958732
Short name T56
Test name
Test status
Simulation time 77699324 ps
CPU time 0.83 seconds
Started Mar 05 12:43:04 PM PST 24
Finished Mar 05 12:43:05 PM PST 24
Peak memory 193120 kb
Host smart-cc47a3a1-6817-4302-8560-61c7845ee353
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58958732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_time
r_same_csr_outstanding.58958732
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2337808042
Short name T42
Test name
Test status
Simulation time 109073647 ps
CPU time 2.11 seconds
Started Mar 05 12:42:58 PM PST 24
Finished Mar 05 12:43:00 PM PST 24
Peak memory 197612 kb
Host smart-8d1ab4ea-9e02-4056-befb-d59229630c0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337808042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2337808042
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2352256267
Short name T552
Test name
Test status
Simulation time 190559361 ps
CPU time 1.12 seconds
Started Mar 05 12:43:02 PM PST 24
Finished Mar 05 12:43:04 PM PST 24
Peak memory 195064 kb
Host smart-13b23fe3-a867-4c7a-9037-6d7273f21d87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352256267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.2352256267
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.1979302318
Short name T402
Test name
Test status
Simulation time 142649292875 ps
CPU time 108.78 seconds
Started Mar 05 12:49:24 PM PST 24
Finished Mar 05 12:51:13 PM PST 24
Peak memory 182996 kb
Host smart-239aea06-3e9f-42b5-a801-e5680a7be1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979302318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.1979302318
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.3013034586
Short name T330
Test name
Test status
Simulation time 340895340027 ps
CPU time 259.15 seconds
Started Mar 05 12:49:25 PM PST 24
Finished Mar 05 12:53:44 PM PST 24
Peak memory 191188 kb
Host smart-0d6b69ee-6dbd-4c86-a8ff-20d93117f6cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013034586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3013034586
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.1226346174
Short name T405
Test name
Test status
Simulation time 115985977 ps
CPU time 0.71 seconds
Started Mar 05 12:49:24 PM PST 24
Finished Mar 05 12:49:25 PM PST 24
Peak memory 182840 kb
Host smart-7400e038-af16-4f8e-af30-b3b34ca231d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226346174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1226346174
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3833952761
Short name T73
Test name
Test status
Simulation time 277026421692 ps
CPU time 707.51 seconds
Started Mar 05 12:49:08 PM PST 24
Finished Mar 05 01:00:56 PM PST 24
Peak memory 191308 kb
Host smart-1ee80f1b-ada2-4a47-9775-62366f1b63ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833952761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3833952761
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3826631193
Short name T393
Test name
Test status
Simulation time 170370764173 ps
CPU time 245.89 seconds
Started Mar 05 12:49:24 PM PST 24
Finished Mar 05 12:53:31 PM PST 24
Peak memory 183056 kb
Host smart-ec126a94-86a2-48f4-9d59-7124d423849d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826631193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3826631193
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1208229440
Short name T17
Test name
Test status
Simulation time 217841077 ps
CPU time 0.8 seconds
Started Mar 05 12:49:27 PM PST 24
Finished Mar 05 12:49:29 PM PST 24
Peak memory 213516 kb
Host smart-bfed8730-8d4b-4d59-95a4-c5eb750161d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208229440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1208229440
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1608565488
Short name T71
Test name
Test status
Simulation time 269657154074 ps
CPU time 564 seconds
Started Mar 05 12:49:25 PM PST 24
Finished Mar 05 12:58:50 PM PST 24
Peak memory 191292 kb
Host smart-ba6a33cc-3712-4b74-93eb-2f27b75e2a45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608565488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1608565488
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.554799059
Short name T369
Test name
Test status
Simulation time 558654073617 ps
CPU time 250.4 seconds
Started Mar 05 12:49:36 PM PST 24
Finished Mar 05 12:53:47 PM PST 24
Peak memory 183028 kb
Host smart-c0276faa-4329-4627-a39a-8bc68c71b011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554799059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.554799059
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1014380513
Short name T286
Test name
Test status
Simulation time 71503814938 ps
CPU time 46.71 seconds
Started Mar 05 12:49:30 PM PST 24
Finished Mar 05 12:50:17 PM PST 24
Peak memory 182956 kb
Host smart-2a248b1d-b020-44a7-91a7-6319d8723bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014380513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1014380513
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.4050527640
Short name T38
Test name
Test status
Simulation time 62712418139 ps
CPU time 947.87 seconds
Started Mar 05 12:49:35 PM PST 24
Finished Mar 05 01:05:23 PM PST 24
Peak memory 206828 kb
Host smart-9985f5db-c336-45c7-bb36-b8f17f4d5669
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050527640 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.4050527640
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.1990503353
Short name T439
Test name
Test status
Simulation time 7967083588 ps
CPU time 10.71 seconds
Started Mar 05 12:51:34 PM PST 24
Finished Mar 05 12:51:45 PM PST 24
Peak memory 183132 kb
Host smart-558c62fc-b9bf-4107-b855-c950e9eca197
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990503353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1990503353
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.2545536507
Short name T311
Test name
Test status
Simulation time 146749072963 ps
CPU time 47.1 seconds
Started Mar 05 12:51:40 PM PST 24
Finished Mar 05 12:52:27 PM PST 24
Peak memory 183124 kb
Host smart-c278feb3-4d83-47f1-8995-a0dae4f90036
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545536507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2545536507
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.880476152
Short name T302
Test name
Test status
Simulation time 169733379771 ps
CPU time 134.21 seconds
Started Mar 05 12:51:38 PM PST 24
Finished Mar 05 12:53:53 PM PST 24
Peak memory 191328 kb
Host smart-d3003066-8e1d-4ada-a726-1ba4af21d5ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880476152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.880476152
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2427924434
Short name T354
Test name
Test status
Simulation time 62457579126 ps
CPU time 109.64 seconds
Started Mar 05 12:49:36 PM PST 24
Finished Mar 05 12:51:25 PM PST 24
Peak memory 183052 kb
Host smart-5c03cd36-576e-4797-96c7-5aec29bb0ef2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427924434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2427924434
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.631391708
Short name T398
Test name
Test status
Simulation time 203142657281 ps
CPU time 139.88 seconds
Started Mar 05 12:49:31 PM PST 24
Finished Mar 05 12:51:52 PM PST 24
Peak memory 183104 kb
Host smart-f3bdfad5-de2b-4c93-9f6a-b92146b1029d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631391708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.631391708
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.3718483336
Short name T248
Test name
Test status
Simulation time 361705919878 ps
CPU time 974.26 seconds
Started Mar 05 12:49:30 PM PST 24
Finished Mar 05 01:05:45 PM PST 24
Peak memory 191164 kb
Host smart-8e4397a2-4a3c-43ad-8244-6e415ac8b4e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718483336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.3718483336
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.2187944368
Short name T351
Test name
Test status
Simulation time 99936862484 ps
CPU time 64.09 seconds
Started Mar 05 12:51:43 PM PST 24
Finished Mar 05 12:52:48 PM PST 24
Peak memory 183120 kb
Host smart-6297603a-15c8-4875-86d1-13797e903de5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187944368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2187944368
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.3961207233
Short name T225
Test name
Test status
Simulation time 122834061407 ps
CPU time 686.5 seconds
Started Mar 05 12:51:45 PM PST 24
Finished Mar 05 01:03:12 PM PST 24
Peak memory 191324 kb
Host smart-d882393d-5e61-4e7e-8635-701e73f49a7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961207233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3961207233
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.253133599
Short name T252
Test name
Test status
Simulation time 36829569142 ps
CPU time 29.54 seconds
Started Mar 05 12:51:45 PM PST 24
Finished Mar 05 12:52:15 PM PST 24
Peak memory 191224 kb
Host smart-e0847cf7-a45c-42b7-9533-b492e5b7efea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253133599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.253133599
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.3386667915
Short name T408
Test name
Test status
Simulation time 43499755265 ps
CPU time 331.1 seconds
Started Mar 05 12:51:49 PM PST 24
Finished Mar 05 12:57:20 PM PST 24
Peak memory 191176 kb
Host smart-bcfed278-e549-409b-8bae-811acddb4145
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386667915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3386667915
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.3919854806
Short name T361
Test name
Test status
Simulation time 14250369461 ps
CPU time 11.13 seconds
Started Mar 05 12:51:44 PM PST 24
Finished Mar 05 12:51:56 PM PST 24
Peak memory 183116 kb
Host smart-b0121907-04dd-46d7-aebf-598f852195ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919854806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3919854806
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.472041847
Short name T217
Test name
Test status
Simulation time 78958059648 ps
CPU time 532.29 seconds
Started Mar 05 12:51:46 PM PST 24
Finished Mar 05 01:00:38 PM PST 24
Peak memory 191336 kb
Host smart-19f679a8-714f-44e7-b85b-fc12d14dc3c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472041847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.472041847
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.4124240597
Short name T6
Test name
Test status
Simulation time 153303564456 ps
CPU time 329.41 seconds
Started Mar 05 12:51:44 PM PST 24
Finished Mar 05 12:57:14 PM PST 24
Peak memory 191324 kb
Host smart-5ca7678f-dcec-487c-8ec5-a6e691a0a04e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124240597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.4124240597
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.2706366035
Short name T267
Test name
Test status
Simulation time 23096534792 ps
CPU time 149.43 seconds
Started Mar 05 12:51:44 PM PST 24
Finished Mar 05 12:54:14 PM PST 24
Peak memory 183108 kb
Host smart-cdd73371-7d1d-47fe-9d52-7727826e6747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706366035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2706366035
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.1349181140
Short name T113
Test name
Test status
Simulation time 38697127483 ps
CPU time 64.81 seconds
Started Mar 05 12:51:46 PM PST 24
Finished Mar 05 12:52:51 PM PST 24
Peak memory 183128 kb
Host smart-cf6908dd-0693-4580-ae19-51642c037479
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349181140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1349181140
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3293199589
Short name T414
Test name
Test status
Simulation time 5830019010 ps
CPU time 4.3 seconds
Started Mar 05 12:49:37 PM PST 24
Finished Mar 05 12:49:42 PM PST 24
Peak memory 183072 kb
Host smart-81570a56-8a5a-4ec8-a5ac-903b767b809f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293199589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3293199589
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1692810379
Short name T367
Test name
Test status
Simulation time 159979024752 ps
CPU time 244.36 seconds
Started Mar 05 12:49:30 PM PST 24
Finished Mar 05 12:53:35 PM PST 24
Peak memory 183104 kb
Host smart-156189f3-58b4-4a41-aac4-8d264a425841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692810379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1692810379
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.111818561
Short name T381
Test name
Test status
Simulation time 19268702579 ps
CPU time 322.34 seconds
Started Mar 05 12:49:35 PM PST 24
Finished Mar 05 12:54:58 PM PST 24
Peak memory 194032 kb
Host smart-c0968854-6eda-48c7-81f7-28fedeaa9422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111818561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.111818561
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.1859464862
Short name T195
Test name
Test status
Simulation time 5977182172064 ps
CPU time 2479.95 seconds
Started Mar 05 12:49:37 PM PST 24
Finished Mar 05 01:30:58 PM PST 24
Peak memory 191260 kb
Host smart-1bdf4ddf-3412-4a8f-9375-3ab7a294a98e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859464862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.1859464862
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.2547008875
Short name T230
Test name
Test status
Simulation time 241305437644 ps
CPU time 277.28 seconds
Started Mar 05 12:51:44 PM PST 24
Finished Mar 05 12:56:22 PM PST 24
Peak memory 191296 kb
Host smart-ef1dea9a-541f-4ae2-b499-4b9d37568b95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547008875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2547008875
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.4174872544
Short name T438
Test name
Test status
Simulation time 418308174066 ps
CPU time 689.61 seconds
Started Mar 05 12:51:43 PM PST 24
Finished Mar 05 01:03:13 PM PST 24
Peak memory 191324 kb
Host smart-15237a1f-50b4-4a5b-bd28-b3347b170a6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174872544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.4174872544
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.2307168452
Short name T210
Test name
Test status
Simulation time 236828083141 ps
CPU time 313.59 seconds
Started Mar 05 12:51:46 PM PST 24
Finished Mar 05 12:57:00 PM PST 24
Peak memory 191348 kb
Host smart-80d8a373-a54f-42b6-b8ec-475d4759e0a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307168452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.2307168452
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.793660868
Short name T314
Test name
Test status
Simulation time 81274466412 ps
CPU time 116.51 seconds
Started Mar 05 12:51:45 PM PST 24
Finished Mar 05 12:53:42 PM PST 24
Peak memory 194808 kb
Host smart-5142b323-d7e3-48cf-a0f0-9742d638d0b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793660868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.793660868
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.1242741856
Short name T266
Test name
Test status
Simulation time 123611909041 ps
CPU time 168.23 seconds
Started Mar 05 12:51:47 PM PST 24
Finished Mar 05 12:54:36 PM PST 24
Peak memory 191308 kb
Host smart-a5591f27-0e51-416d-a71f-a8b7153bc9ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242741856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1242741856
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.4142603333
Short name T117
Test name
Test status
Simulation time 1314367289140 ps
CPU time 1213.3 seconds
Started Mar 05 12:49:34 PM PST 24
Finished Mar 05 01:09:47 PM PST 24
Peak memory 183128 kb
Host smart-88472079-aa22-4b41-b98a-a171f200cf5e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142603333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.4142603333
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.474703552
Short name T404
Test name
Test status
Simulation time 250494881617 ps
CPU time 121.09 seconds
Started Mar 05 12:49:31 PM PST 24
Finished Mar 05 12:51:32 PM PST 24
Peak memory 183000 kb
Host smart-ee4c5058-0fe1-407f-87d4-285bfd475641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474703552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.474703552
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.2066682268
Short name T59
Test name
Test status
Simulation time 332604395016 ps
CPU time 670.78 seconds
Started Mar 05 12:49:36 PM PST 24
Finished Mar 05 01:00:47 PM PST 24
Peak memory 191220 kb
Host smart-dcf1864f-a8d9-44bc-8ac4-406fddf021dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066682268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2066682268
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.734090487
Short name T372
Test name
Test status
Simulation time 336457120 ps
CPU time 0.65 seconds
Started Mar 05 12:49:36 PM PST 24
Finished Mar 05 12:49:37 PM PST 24
Peak memory 182780 kb
Host smart-099edd29-e7a2-4cd6-8126-4732a6befc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734090487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.734090487
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.2280343386
Short name T396
Test name
Test status
Simulation time 52805231 ps
CPU time 0.61 seconds
Started Mar 05 12:49:33 PM PST 24
Finished Mar 05 12:49:34 PM PST 24
Peak memory 182860 kb
Host smart-5dbe224c-8606-4d50-9224-23870bcb7e50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280343386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.2280343386
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.390612097
Short name T27
Test name
Test status
Simulation time 539125500783 ps
CPU time 875.18 seconds
Started Mar 05 12:52:00 PM PST 24
Finished Mar 05 01:06:36 PM PST 24
Peak memory 191324 kb
Host smart-a7fda3e0-a295-48c7-ae90-e6d49869209d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390612097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.390612097
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.410237749
Short name T140
Test name
Test status
Simulation time 29628805853 ps
CPU time 57.09 seconds
Started Mar 05 12:51:55 PM PST 24
Finished Mar 05 12:52:52 PM PST 24
Peak memory 183124 kb
Host smart-8a299a61-fb1e-4dca-9429-2085a8db9027
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410237749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.410237749
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2941682620
Short name T420
Test name
Test status
Simulation time 98101261099 ps
CPU time 1963.37 seconds
Started Mar 05 12:51:55 PM PST 24
Finished Mar 05 01:24:40 PM PST 24
Peak memory 191320 kb
Host smart-03e100da-6543-4e24-94c3-92124a18e1b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941682620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2941682620
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.3348477484
Short name T335
Test name
Test status
Simulation time 111257989746 ps
CPU time 178.16 seconds
Started Mar 05 12:51:54 PM PST 24
Finished Mar 05 12:54:52 PM PST 24
Peak memory 191328 kb
Host smart-9d8a1a54-6c36-4d52-b58f-f37b92ac1b7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348477484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3348477484
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3706355073
Short name T400
Test name
Test status
Simulation time 51015419718 ps
CPU time 81.27 seconds
Started Mar 05 12:51:56 PM PST 24
Finished Mar 05 12:53:17 PM PST 24
Peak memory 183116 kb
Host smart-b8291abd-41ae-47e8-a20c-b536162fd88c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706355073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3706355073
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.90246268
Short name T304
Test name
Test status
Simulation time 253320139890 ps
CPU time 117.48 seconds
Started Mar 05 12:51:55 PM PST 24
Finished Mar 05 12:53:52 PM PST 24
Peak memory 191248 kb
Host smart-89fbecb4-d7fa-446f-b441-1abd736f258a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90246268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.90246268
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3736539009
Short name T87
Test name
Test status
Simulation time 401302588928 ps
CPU time 197.63 seconds
Started Mar 05 12:49:31 PM PST 24
Finished Mar 05 12:52:49 PM PST 24
Peak memory 183128 kb
Host smart-5de42fcc-2d4a-4702-b894-c2c3dddf9169
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736539009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3736539009
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.997798744
Short name T366
Test name
Test status
Simulation time 122294439111 ps
CPU time 192.41 seconds
Started Mar 05 12:49:31 PM PST 24
Finished Mar 05 12:52:44 PM PST 24
Peak memory 183104 kb
Host smart-ffdc3134-83b0-4720-a032-2d385a60c12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997798744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.997798744
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.2346117935
Short name T158
Test name
Test status
Simulation time 611852749902 ps
CPU time 374.98 seconds
Started Mar 05 12:49:34 PM PST 24
Finished Mar 05 12:55:49 PM PST 24
Peak memory 191300 kb
Host smart-1ac4044b-1cde-41c7-876b-86596400241a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346117935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2346117935
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.2760602538
Short name T348
Test name
Test status
Simulation time 58805740737 ps
CPU time 113.45 seconds
Started Mar 05 12:49:35 PM PST 24
Finished Mar 05 12:51:29 PM PST 24
Peak memory 191220 kb
Host smart-e2757d9e-8102-4683-a6ba-fd09913114fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760602538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2760602538
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.3372238717
Short name T261
Test name
Test status
Simulation time 325712739173 ps
CPU time 99.7 seconds
Started Mar 05 12:51:55 PM PST 24
Finished Mar 05 12:53:35 PM PST 24
Peak memory 191328 kb
Host smart-5f826379-6768-421c-a850-097e7cbc0283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372238717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3372238717
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.3336603809
Short name T150
Test name
Test status
Simulation time 38480934398 ps
CPU time 57.7 seconds
Started Mar 05 12:51:58 PM PST 24
Finished Mar 05 12:52:56 PM PST 24
Peak memory 183144 kb
Host smart-d7d16741-2db7-4430-9d80-d48661351b7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336603809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3336603809
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.1346374115
Short name T317
Test name
Test status
Simulation time 92104448680 ps
CPU time 186.72 seconds
Started Mar 05 12:51:54 PM PST 24
Finished Mar 05 12:55:01 PM PST 24
Peak memory 191316 kb
Host smart-0fd890b8-4163-4a50-9301-aa52ede48b63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346374115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1346374115
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.2694105191
Short name T215
Test name
Test status
Simulation time 721974757222 ps
CPU time 491.53 seconds
Started Mar 05 12:51:58 PM PST 24
Finished Mar 05 01:00:10 PM PST 24
Peak memory 191340 kb
Host smart-e7e661cb-0a9b-4e09-853c-e382e7e82412
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694105191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2694105191
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.455256349
Short name T143
Test name
Test status
Simulation time 24453478325 ps
CPU time 226.09 seconds
Started Mar 05 12:51:54 PM PST 24
Finished Mar 05 12:55:41 PM PST 24
Peak memory 183168 kb
Host smart-2d1f4c56-fe70-4ec2-b5a4-74020748fb3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455256349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.455256349
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.732816145
Short name T203
Test name
Test status
Simulation time 706104431209 ps
CPU time 540.97 seconds
Started Mar 05 12:52:02 PM PST 24
Finished Mar 05 01:01:03 PM PST 24
Peak memory 191300 kb
Host smart-b04422a7-093c-4d80-9729-6c716a366e69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732816145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.732816145
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.318027427
Short name T181
Test name
Test status
Simulation time 118124234483 ps
CPU time 120.47 seconds
Started Mar 05 12:52:03 PM PST 24
Finished Mar 05 12:54:03 PM PST 24
Peak memory 191224 kb
Host smart-a41c66ea-ed85-40ec-8924-effdec3ff767
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318027427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.318027427
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1298564903
Short name T443
Test name
Test status
Simulation time 256347662543 ps
CPU time 247.13 seconds
Started Mar 05 12:52:04 PM PST 24
Finished Mar 05 12:56:11 PM PST 24
Peak memory 191312 kb
Host smart-d3b00ae2-7949-4b8e-b8c2-61a286f9a1a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298564903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1298564903
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.3651857363
Short name T423
Test name
Test status
Simulation time 385174320549 ps
CPU time 171.17 seconds
Started Mar 05 12:49:36 PM PST 24
Finished Mar 05 12:52:28 PM PST 24
Peak memory 183004 kb
Host smart-63bdfac0-b099-4008-9630-e88f36c13ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651857363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3651857363
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.3065813425
Short name T20
Test name
Test status
Simulation time 73294397464 ps
CPU time 472.74 seconds
Started Mar 05 12:49:31 PM PST 24
Finished Mar 05 12:57:25 PM PST 24
Peak memory 194544 kb
Host smart-d2424b37-e3a8-4de9-9e4a-b8230ee6ab8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065813425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3065813425
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2188533382
Short name T131
Test name
Test status
Simulation time 235523644948 ps
CPU time 689.93 seconds
Started Mar 05 12:49:32 PM PST 24
Finished Mar 05 01:01:02 PM PST 24
Peak memory 191348 kb
Host smart-765e7418-9102-4e2b-b3a5-661d4fab12ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188533382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2188533382
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.1102006555
Short name T323
Test name
Test status
Simulation time 662480711803 ps
CPU time 260.68 seconds
Started Mar 05 12:52:03 PM PST 24
Finished Mar 05 12:56:24 PM PST 24
Peak memory 191340 kb
Host smart-abb14d1d-90a8-4dc5-9f98-ac5517f813ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102006555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1102006555
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.4062138353
Short name T209
Test name
Test status
Simulation time 7692171599 ps
CPU time 282.18 seconds
Started Mar 05 12:52:00 PM PST 24
Finished Mar 05 12:56:42 PM PST 24
Peak memory 183112 kb
Host smart-10360be2-3f35-4bc9-bc66-c9c576d93068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062138353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.4062138353
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.2576414681
Short name T79
Test name
Test status
Simulation time 9447890213 ps
CPU time 15.77 seconds
Started Mar 05 12:52:02 PM PST 24
Finished Mar 05 12:52:18 PM PST 24
Peak memory 183128 kb
Host smart-33024652-e525-4ce5-8ffa-2807be314cee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576414681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2576414681
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3045480922
Short name T358
Test name
Test status
Simulation time 114993361415 ps
CPU time 48.64 seconds
Started Mar 05 12:52:03 PM PST 24
Finished Mar 05 12:52:52 PM PST 24
Peak memory 183008 kb
Host smart-622aed75-c66d-4a4b-9bbc-bfb3218d907f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045480922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3045480922
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.73452511
Short name T274
Test name
Test status
Simulation time 87685323773 ps
CPU time 388.03 seconds
Started Mar 05 12:52:00 PM PST 24
Finished Mar 05 12:58:28 PM PST 24
Peak memory 191296 kb
Host smart-ca28c5c8-94e9-488d-9be0-9cdd07a41895
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73452511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.73452511
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.2801305541
Short name T387
Test name
Test status
Simulation time 38428361797 ps
CPU time 33.65 seconds
Started Mar 05 12:52:02 PM PST 24
Finished Mar 05 12:52:36 PM PST 24
Peak memory 183064 kb
Host smart-47ce655f-0f24-4c4b-b86a-726eee5c6360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801305541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2801305541
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2515011236
Short name T60
Test name
Test status
Simulation time 1862069683980 ps
CPU time 1051.18 seconds
Started Mar 05 12:49:38 PM PST 24
Finished Mar 05 01:07:09 PM PST 24
Peak memory 183128 kb
Host smart-00d78275-eaa3-4c92-a32e-59c43af94b46
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515011236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2515011236
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.3352094022
Short name T384
Test name
Test status
Simulation time 38414828303 ps
CPU time 24.43 seconds
Started Mar 05 12:49:33 PM PST 24
Finished Mar 05 12:49:57 PM PST 24
Peak memory 183112 kb
Host smart-8e2a582a-1746-487e-9d06-123c300f8be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352094022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3352094022
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.335439689
Short name T318
Test name
Test status
Simulation time 439986508860 ps
CPU time 260.95 seconds
Started Mar 05 12:49:32 PM PST 24
Finished Mar 05 12:53:53 PM PST 24
Peak memory 191224 kb
Host smart-7b68ac5d-ab4f-4a3f-a9d0-ae66b103e8a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335439689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.335439689
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.851645057
Short name T4
Test name
Test status
Simulation time 1963879482 ps
CPU time 4.07 seconds
Started Mar 05 12:49:33 PM PST 24
Finished Mar 05 12:49:37 PM PST 24
Peak memory 183032 kb
Host smart-7668fef5-01c1-460c-a2a8-95ebfd9bad82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851645057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.851645057
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.302386681
Short name T162
Test name
Test status
Simulation time 688327763465 ps
CPU time 441.59 seconds
Started Mar 05 12:49:33 PM PST 24
Finished Mar 05 12:56:55 PM PST 24
Peak memory 191308 kb
Host smart-2df606de-7978-4f2b-9a72-3a71548e139c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302386681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.
302386681
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.2979287064
Short name T23
Test name
Test status
Simulation time 12323317032 ps
CPU time 19.7 seconds
Started Mar 05 12:52:04 PM PST 24
Finished Mar 05 12:52:23 PM PST 24
Peak memory 191372 kb
Host smart-9777bc01-ce52-4186-a90a-265b948fb323
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979287064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.2979287064
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.3952382178
Short name T220
Test name
Test status
Simulation time 389424434347 ps
CPU time 206.13 seconds
Started Mar 05 12:52:11 PM PST 24
Finished Mar 05 12:55:37 PM PST 24
Peak memory 191240 kb
Host smart-de91136c-39bc-4c76-8ff4-7e0670db5307
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952382178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3952382178
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.3436975454
Short name T88
Test name
Test status
Simulation time 393979305217 ps
CPU time 488.23 seconds
Started Mar 05 12:52:14 PM PST 24
Finished Mar 05 01:00:22 PM PST 24
Peak memory 191312 kb
Host smart-93ca8ce1-9bf1-42c4-a66f-886425bbf3ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436975454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3436975454
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.957915647
Short name T276
Test name
Test status
Simulation time 194003641752 ps
CPU time 115.95 seconds
Started Mar 05 12:52:10 PM PST 24
Finished Mar 05 12:54:06 PM PST 24
Peak memory 193700 kb
Host smart-235212ff-fc62-40d7-897f-a4b39923ef8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957915647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.957915647
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.1581030460
Short name T305
Test name
Test status
Simulation time 12252944012 ps
CPU time 5.32 seconds
Started Mar 05 12:52:14 PM PST 24
Finished Mar 05 12:52:20 PM PST 24
Peak memory 182984 kb
Host smart-c045a193-c1c3-48e6-a050-6e59bd80050c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581030460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1581030460
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1100215347
Short name T126
Test name
Test status
Simulation time 290764163219 ps
CPU time 307.13 seconds
Started Mar 05 12:49:45 PM PST 24
Finished Mar 05 12:54:52 PM PST 24
Peak memory 183148 kb
Host smart-870e9763-a25f-4799-8436-d3de8a4f7b93
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100215347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1100215347
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1595685649
Short name T61
Test name
Test status
Simulation time 116019182829 ps
CPU time 172.9 seconds
Started Mar 05 12:49:43 PM PST 24
Finished Mar 05 12:52:36 PM PST 24
Peak memory 183172 kb
Host smart-bdb5218a-bfa9-4c23-a79f-b6a1d3660612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595685649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1595685649
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.1210575940
Short name T5
Test name
Test status
Simulation time 119193484991 ps
CPU time 446.56 seconds
Started Mar 05 12:49:36 PM PST 24
Finished Mar 05 12:57:02 PM PST 24
Peak memory 194408 kb
Host smart-196240f3-5953-4c64-afbe-7daf6fcaabbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210575940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1210575940
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.2345759212
Short name T363
Test name
Test status
Simulation time 7044315790 ps
CPU time 12.52 seconds
Started Mar 05 12:49:46 PM PST 24
Finished Mar 05 12:49:59 PM PST 24
Peak memory 191200 kb
Host smart-fbe51727-0f42-43f0-afed-e3fc47c2078a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345759212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2345759212
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.2810555906
Short name T440
Test name
Test status
Simulation time 148167549622 ps
CPU time 69.1 seconds
Started Mar 05 12:52:14 PM PST 24
Finished Mar 05 12:53:24 PM PST 24
Peak memory 183168 kb
Host smart-70d31679-cd58-4afd-bc3d-8c3693d8acc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810555906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2810555906
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.2985066960
Short name T90
Test name
Test status
Simulation time 77001403451 ps
CPU time 475.66 seconds
Started Mar 05 12:52:12 PM PST 24
Finished Mar 05 01:00:08 PM PST 24
Peak memory 191368 kb
Host smart-36c2a91e-6bbc-4489-ad30-91531b960adb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985066960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2985066960
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.1134098123
Short name T332
Test name
Test status
Simulation time 23066803590 ps
CPU time 183.59 seconds
Started Mar 05 12:52:12 PM PST 24
Finished Mar 05 12:55:16 PM PST 24
Peak memory 191392 kb
Host smart-6c2e504d-9d03-4a76-a6b7-5bbed336523c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134098123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1134098123
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2068942820
Short name T124
Test name
Test status
Simulation time 463644947919 ps
CPU time 228.94 seconds
Started Mar 05 12:52:11 PM PST 24
Finished Mar 05 12:56:00 PM PST 24
Peak memory 191300 kb
Host smart-2865dc9c-2416-47b3-bfc4-41b4d62fe552
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068942820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2068942820
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2023632302
Short name T142
Test name
Test status
Simulation time 130519409987 ps
CPU time 59.83 seconds
Started Mar 05 12:52:11 PM PST 24
Finished Mar 05 12:53:10 PM PST 24
Peak memory 191328 kb
Host smart-50bad831-4a18-4641-9cca-12d800828891
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023632302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2023632302
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.4205037179
Short name T316
Test name
Test status
Simulation time 250406512262 ps
CPU time 1227.46 seconds
Started Mar 05 12:52:36 PM PST 24
Finished Mar 05 01:13:04 PM PST 24
Peak memory 191296 kb
Host smart-4283494f-edfb-4f91-a813-bd77a3e0ddce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205037179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.4205037179
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1552244031
Short name T243
Test name
Test status
Simulation time 28311211802 ps
CPU time 574 seconds
Started Mar 05 12:52:35 PM PST 24
Finished Mar 05 01:02:09 PM PST 24
Peak memory 191328 kb
Host smart-fa7185c0-00b3-48b0-8e0d-337928b0dffd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552244031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1552244031
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3995041099
Short name T224
Test name
Test status
Simulation time 32372235200 ps
CPU time 16.55 seconds
Started Mar 05 12:49:42 PM PST 24
Finished Mar 05 12:49:59 PM PST 24
Peak memory 183128 kb
Host smart-0891d9b1-2f13-45f0-a056-4efcc459d9f1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995041099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3995041099
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.3492407298
Short name T448
Test name
Test status
Simulation time 157229888958 ps
CPU time 215.37 seconds
Started Mar 05 12:49:44 PM PST 24
Finished Mar 05 12:53:20 PM PST 24
Peak memory 183104 kb
Host smart-e77f0994-d82c-492c-971a-600bbd1095b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492407298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3492407298
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.3388851706
Short name T424
Test name
Test status
Simulation time 102144184261 ps
CPU time 1062.75 seconds
Started Mar 05 12:49:46 PM PST 24
Finished Mar 05 01:07:29 PM PST 24
Peak memory 191300 kb
Host smart-964f461b-3aa8-41d5-8516-7e3d37ae9797
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388851706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3388851706
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.4196976772
Short name T291
Test name
Test status
Simulation time 36298860282 ps
CPU time 56.36 seconds
Started Mar 05 12:49:46 PM PST 24
Finished Mar 05 12:50:42 PM PST 24
Peak memory 183024 kb
Host smart-90025583-0eb4-4467-8017-f790a5352947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196976772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.4196976772
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.3067453860
Short name T36
Test name
Test status
Simulation time 18539474228 ps
CPU time 152.16 seconds
Started Mar 05 12:49:43 PM PST 24
Finished Mar 05 12:52:15 PM PST 24
Peak memory 197872 kb
Host smart-5a2c23b7-dd23-4675-b079-82a6f0af68f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067453860 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.3067453860
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.1882957135
Short name T254
Test name
Test status
Simulation time 39066026599 ps
CPU time 73.28 seconds
Started Mar 05 12:52:35 PM PST 24
Finished Mar 05 12:53:49 PM PST 24
Peak memory 191160 kb
Host smart-f43cac31-876d-4811-91ce-a089f1763068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882957135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1882957135
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.1403664107
Short name T196
Test name
Test status
Simulation time 75270859538 ps
CPU time 123.1 seconds
Started Mar 05 12:52:35 PM PST 24
Finished Mar 05 12:54:38 PM PST 24
Peak memory 194556 kb
Host smart-a95c4c45-51bf-43c8-adbf-ff152c4805a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403664107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1403664107
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.1468092214
Short name T388
Test name
Test status
Simulation time 66217906001 ps
CPU time 55.45 seconds
Started Mar 05 12:52:34 PM PST 24
Finished Mar 05 12:53:30 PM PST 24
Peak memory 183120 kb
Host smart-97ad9088-47b4-4f17-bf58-f72bdafab99c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468092214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1468092214
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.3876471152
Short name T212
Test name
Test status
Simulation time 743372745942 ps
CPU time 611.02 seconds
Started Mar 05 12:52:36 PM PST 24
Finished Mar 05 01:02:47 PM PST 24
Peak memory 191316 kb
Host smart-50b212a9-9027-4bf1-9a7a-9fdd4178c617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876471152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3876471152
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.959896379
Short name T157
Test name
Test status
Simulation time 76652987307 ps
CPU time 117.34 seconds
Started Mar 05 12:52:34 PM PST 24
Finished Mar 05 12:54:31 PM PST 24
Peak memory 191336 kb
Host smart-15fd3363-1ea8-49e0-ae83-20af8d12907a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959896379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.959896379
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1712536957
Short name T154
Test name
Test status
Simulation time 40822624937 ps
CPU time 57.7 seconds
Started Mar 05 12:52:36 PM PST 24
Finished Mar 05 12:53:35 PM PST 24
Peak memory 182852 kb
Host smart-e9e96d14-9c62-4a50-89d8-7fa32bb056ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712536957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1712536957
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.4117402611
Short name T257
Test name
Test status
Simulation time 177082581551 ps
CPU time 130.67 seconds
Started Mar 05 12:52:41 PM PST 24
Finished Mar 05 12:54:51 PM PST 24
Peak memory 191392 kb
Host smart-934718ad-1d64-452c-bca8-1ed2e5a2158f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117402611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.4117402611
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.844392360
Short name T253
Test name
Test status
Simulation time 486683250469 ps
CPU time 253.31 seconds
Started Mar 05 12:49:42 PM PST 24
Finished Mar 05 12:53:55 PM PST 24
Peak memory 183100 kb
Host smart-a9c22965-2273-4743-8747-d6479ae64ab7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844392360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.844392360
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.4076461892
Short name T374
Test name
Test status
Simulation time 74391262627 ps
CPU time 112.91 seconds
Started Mar 05 12:49:46 PM PST 24
Finished Mar 05 12:51:39 PM PST 24
Peak memory 183104 kb
Host smart-9f1b348a-4b05-4ffe-9527-2e2ff04c1ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076461892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.4076461892
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.1520985723
Short name T378
Test name
Test status
Simulation time 45263714449 ps
CPU time 14.78 seconds
Started Mar 05 12:49:43 PM PST 24
Finished Mar 05 12:49:58 PM PST 24
Peak memory 194884 kb
Host smart-f5f4d440-8a78-4f9e-adbf-0699578fc752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520985723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1520985723
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1406185066
Short name T357
Test name
Test status
Simulation time 791801969807 ps
CPU time 278.15 seconds
Started Mar 05 12:49:44 PM PST 24
Finished Mar 05 12:54:23 PM PST 24
Peak memory 183204 kb
Host smart-cd99fbc6-f5d0-4435-b530-04237874b6a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406185066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1406185066
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/191.rv_timer_random.1905264746
Short name T275
Test name
Test status
Simulation time 478952591955 ps
CPU time 769.9 seconds
Started Mar 05 12:52:39 PM PST 24
Finished Mar 05 01:05:30 PM PST 24
Peak memory 191316 kb
Host smart-2b7e5b4d-6b7b-412f-82ba-7b13744eb0a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905264746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1905264746
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.1622742679
Short name T284
Test name
Test status
Simulation time 414711689616 ps
CPU time 233.01 seconds
Started Mar 05 12:52:40 PM PST 24
Finished Mar 05 12:56:33 PM PST 24
Peak memory 191316 kb
Host smart-2e50ef4a-f5e7-4e0a-b644-bc1fa1201ebd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622742679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1622742679
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.1404926949
Short name T125
Test name
Test status
Simulation time 961212962302 ps
CPU time 368.36 seconds
Started Mar 05 12:52:43 PM PST 24
Finished Mar 05 12:58:51 PM PST 24
Peak memory 191248 kb
Host smart-ad84ada2-d3f9-4cdc-a462-92d0a1e7a486
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404926949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1404926949
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.4261511479
Short name T226
Test name
Test status
Simulation time 19493534087 ps
CPU time 18.29 seconds
Started Mar 05 12:52:39 PM PST 24
Finished Mar 05 12:52:57 PM PST 24
Peak memory 183172 kb
Host smart-e2e45b49-70e9-41e7-a241-11e54847b4b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261511479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.4261511479
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.3639282176
Short name T313
Test name
Test status
Simulation time 186892429488 ps
CPU time 258.07 seconds
Started Mar 05 12:52:36 PM PST 24
Finished Mar 05 12:56:55 PM PST 24
Peak memory 193100 kb
Host smart-ff4009f4-dcc6-413c-b907-a1b1a8774b47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639282176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3639282176
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.1625530868
Short name T288
Test name
Test status
Simulation time 196731818480 ps
CPU time 488.21 seconds
Started Mar 05 12:52:37 PM PST 24
Finished Mar 05 01:00:46 PM PST 24
Peak memory 191236 kb
Host smart-bccadb50-a8bb-435e-a405-292dab23e19f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625530868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.1625530868
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.597079303
Short name T141
Test name
Test status
Simulation time 133938014878 ps
CPU time 136.76 seconds
Started Mar 05 12:49:28 PM PST 24
Finished Mar 05 12:51:45 PM PST 24
Peak memory 183116 kb
Host smart-8adfb27a-90b5-445b-a24c-6bbccc7cf44a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597079303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.rv_timer_cfg_update_on_fly.597079303
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.504903135
Short name T21
Test name
Test status
Simulation time 769365843280 ps
CPU time 328.9 seconds
Started Mar 05 12:49:27 PM PST 24
Finished Mar 05 12:54:56 PM PST 24
Peak memory 183120 kb
Host smart-d1c942dd-12f2-4a00-9a4b-5b57924d551a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504903135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.504903135
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.2955969490
Short name T221
Test name
Test status
Simulation time 75580410157 ps
CPU time 67.29 seconds
Started Mar 05 12:49:24 PM PST 24
Finished Mar 05 12:50:32 PM PST 24
Peak memory 191260 kb
Host smart-92101abc-6dcf-4351-93ee-52a00984cbe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955969490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.2955969490
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3612336283
Short name T421
Test name
Test status
Simulation time 185814351 ps
CPU time 1.08 seconds
Started Mar 05 12:49:21 PM PST 24
Finished Mar 05 12:49:22 PM PST 24
Peak memory 182980 kb
Host smart-e0d582f1-fa24-4ebf-95af-657d2d14e1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612336283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3612336283
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.4001597928
Short name T18
Test name
Test status
Simulation time 173265034 ps
CPU time 1.01 seconds
Started Mar 05 12:49:30 PM PST 24
Finished Mar 05 12:49:31 PM PST 24
Peak memory 214572 kb
Host smart-eb64b1a3-0d7c-4ea2-a5c7-2918c1d0ece7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001597928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.4001597928
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.1546513260
Short name T418
Test name
Test status
Simulation time 204243426942 ps
CPU time 314.46 seconds
Started Mar 05 12:49:25 PM PST 24
Finished Mar 05 12:54:40 PM PST 24
Peak memory 194432 kb
Host smart-ba9fec57-cb8b-45f7-bb1f-84fa326b136c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546513260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
1546513260
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.996880286
Short name T228
Test name
Test status
Simulation time 2901751135 ps
CPU time 5.52 seconds
Started Mar 05 12:49:45 PM PST 24
Finished Mar 05 12:49:51 PM PST 24
Peak memory 183116 kb
Host smart-38520eba-1a56-4c3b-a333-9ae3c8c394e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996880286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.rv_timer_cfg_update_on_fly.996880286
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.4055994840
Short name T451
Test name
Test status
Simulation time 142255391427 ps
CPU time 202.12 seconds
Started Mar 05 12:49:45 PM PST 24
Finished Mar 05 12:53:07 PM PST 24
Peak memory 183056 kb
Host smart-f0faf64a-f927-4752-b476-a0d93db46f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055994840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.4055994840
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.1129258753
Short name T324
Test name
Test status
Simulation time 109679853633 ps
CPU time 127.02 seconds
Started Mar 05 12:49:42 PM PST 24
Finished Mar 05 12:51:49 PM PST 24
Peak memory 191312 kb
Host smart-a1b019c4-329e-48fa-9520-5872efb5d746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129258753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.1129258753
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.571895830
Short name T347
Test name
Test status
Simulation time 470166662929 ps
CPU time 820.94 seconds
Started Mar 05 12:49:43 PM PST 24
Finished Mar 05 01:03:25 PM PST 24
Peak memory 191216 kb
Host smart-a7dc54b5-9db2-4434-a5a5-e863b5825827
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571895830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.
571895830
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_random.2800522945
Short name T283
Test name
Test status
Simulation time 156805852874 ps
CPU time 39.46 seconds
Started Mar 05 12:49:45 PM PST 24
Finished Mar 05 12:50:24 PM PST 24
Peak memory 193620 kb
Host smart-7e811457-8629-420f-af50-c989e57f7c74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800522945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2800522945
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3107038021
Short name T406
Test name
Test status
Simulation time 130004514 ps
CPU time 0.55 seconds
Started Mar 05 12:49:44 PM PST 24
Finished Mar 05 12:49:45 PM PST 24
Peak memory 182880 kb
Host smart-509523a3-45a7-4a2a-a9b5-e513a750ef98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107038021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3107038021
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.2547740703
Short name T70
Test name
Test status
Simulation time 54995766784 ps
CPU time 93.52 seconds
Started Mar 05 12:49:45 PM PST 24
Finished Mar 05 12:51:19 PM PST 24
Peak memory 191300 kb
Host smart-5190382b-3483-451c-b9dd-ca34f1e338b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547740703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.2547740703
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3633832466
Short name T326
Test name
Test status
Simulation time 1017111060172 ps
CPU time 376.91 seconds
Started Mar 05 12:49:44 PM PST 24
Finished Mar 05 12:56:01 PM PST 24
Peak memory 183124 kb
Host smart-96e3f369-826d-4945-8535-cd5bf8403c0a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633832466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3633832466
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.2176965824
Short name T389
Test name
Test status
Simulation time 40133261550 ps
CPU time 56.02 seconds
Started Mar 05 12:49:45 PM PST 24
Finished Mar 05 12:50:42 PM PST 24
Peak memory 183104 kb
Host smart-5cbf0108-85b8-4851-ac99-d6cb42ba215e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176965824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.2176965824
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.524475589
Short name T51
Test name
Test status
Simulation time 509751514313 ps
CPU time 686.89 seconds
Started Mar 05 12:49:53 PM PST 24
Finished Mar 05 01:01:20 PM PST 24
Peak memory 191252 kb
Host smart-29e1e032-2775-49b2-a537-c4b44cae7237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524475589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.524475589
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.951420250
Short name T336
Test name
Test status
Simulation time 52084052232 ps
CPU time 104.9 seconds
Started Mar 05 12:49:54 PM PST 24
Finished Mar 05 12:51:39 PM PST 24
Peak memory 191296 kb
Host smart-b9ad88bf-7a68-4248-b96e-c843626c054f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951420250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.951420250
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.550771274
Short name T34
Test name
Test status
Simulation time 26775507 ps
CPU time 0.56 seconds
Started Mar 05 12:49:54 PM PST 24
Finished Mar 05 12:49:55 PM PST 24
Peak memory 182772 kb
Host smart-2ef68d58-5e79-45de-bdba-31768eb9da84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550771274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.
550771274
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.93984696
Short name T37
Test name
Test status
Simulation time 90722089232 ps
CPU time 880.51 seconds
Started Mar 05 12:49:51 PM PST 24
Finished Mar 05 01:04:32 PM PST 24
Peak memory 206012 kb
Host smart-05b1e20e-2b81-4077-984b-c6a2ded0c965
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93984696 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.93984696
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1977043394
Short name T112
Test name
Test status
Simulation time 585878188798 ps
CPU time 535.83 seconds
Started Mar 05 12:49:53 PM PST 24
Finished Mar 05 12:58:49 PM PST 24
Peak memory 182984 kb
Host smart-d2623165-c517-4a8e-8a53-5451bd28f87c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977043394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1977043394
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.3656616279
Short name T450
Test name
Test status
Simulation time 131757456435 ps
CPU time 177.87 seconds
Started Mar 05 12:49:52 PM PST 24
Finished Mar 05 12:52:50 PM PST 24
Peak memory 183128 kb
Host smart-e3385c48-1a50-4837-9a00-5235c8215b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656616279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3656616279
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.1416643178
Short name T271
Test name
Test status
Simulation time 84661611433 ps
CPU time 69.84 seconds
Started Mar 05 12:49:57 PM PST 24
Finished Mar 05 12:51:07 PM PST 24
Peak memory 183096 kb
Host smart-70df64eb-2ba4-40a9-8a32-600b10d98ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416643178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1416643178
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.1027900742
Short name T84
Test name
Test status
Simulation time 101946019956 ps
CPU time 117.08 seconds
Started Mar 05 12:49:58 PM PST 24
Finished Mar 05 12:51:55 PM PST 24
Peak memory 183108 kb
Host smart-36b2b4a8-e1ee-45a4-a03d-32a2aeaecf6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027900742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.1027900742
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.2586152075
Short name T41
Test name
Test status
Simulation time 76155369679 ps
CPU time 692.64 seconds
Started Mar 05 12:49:53 PM PST 24
Finished Mar 05 01:01:26 PM PST 24
Peak memory 206084 kb
Host smart-b4757903-69b2-4f13-a401-c784cf65119a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586152075 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.2586152075
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.1759197736
Short name T382
Test name
Test status
Simulation time 44498818375 ps
CPU time 27.06 seconds
Started Mar 05 12:49:52 PM PST 24
Finished Mar 05 12:50:19 PM PST 24
Peak memory 183040 kb
Host smart-145d44e4-3225-4eb5-a816-ff0b6ae0e8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759197736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.1759197736
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.1230993438
Short name T169
Test name
Test status
Simulation time 116773143964 ps
CPU time 990.19 seconds
Started Mar 05 12:49:53 PM PST 24
Finished Mar 05 01:06:24 PM PST 24
Peak memory 193800 kb
Host smart-f4f0bbee-3c10-4bfb-88e6-c2079a08be8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230993438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.1230993438
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.416454780
Short name T309
Test name
Test status
Simulation time 159270769867 ps
CPU time 33.99 seconds
Started Mar 05 12:49:58 PM PST 24
Finished Mar 05 12:50:32 PM PST 24
Peak memory 194244 kb
Host smart-3a560b3f-ba2d-4345-935b-a0a67f75ba9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416454780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.416454780
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.221395751
Short name T247
Test name
Test status
Simulation time 104519621567 ps
CPU time 74.2 seconds
Started Mar 05 12:49:54 PM PST 24
Finished Mar 05 12:51:08 PM PST 24
Peak memory 191300 kb
Host smart-0c06b15a-be16-4b66-9136-18fed680ad65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221395751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
221395751
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2476163268
Short name T446
Test name
Test status
Simulation time 19036468115 ps
CPU time 30.92 seconds
Started Mar 05 12:50:00 PM PST 24
Finished Mar 05 12:50:32 PM PST 24
Peak memory 183052 kb
Host smart-0eafa32c-c1a1-4d89-b55d-2e2fae0ac4b9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476163268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2476163268
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.3331427329
Short name T390
Test name
Test status
Simulation time 91623238866 ps
CPU time 36.11 seconds
Started Mar 05 12:50:00 PM PST 24
Finished Mar 05 12:50:36 PM PST 24
Peak memory 183024 kb
Host smart-37b69eb9-c8dc-4871-87de-61648912f575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331427329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3331427329
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.548592953
Short name T159
Test name
Test status
Simulation time 104192849900 ps
CPU time 287.36 seconds
Started Mar 05 12:50:00 PM PST 24
Finished Mar 05 12:54:49 PM PST 24
Peak memory 191312 kb
Host smart-9b976521-13f0-4660-bea7-a139f1cce4a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548592953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.548592953
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.3434583594
Short name T9
Test name
Test status
Simulation time 100563890058 ps
CPU time 84.12 seconds
Started Mar 05 12:50:00 PM PST 24
Finished Mar 05 12:51:25 PM PST 24
Peak memory 191292 kb
Host smart-5554fa37-6df9-40a2-8d33-5781e30e03d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434583594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3434583594
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.900017784
Short name T338
Test name
Test status
Simulation time 343289386449 ps
CPU time 558.36 seconds
Started Mar 05 12:50:03 PM PST 24
Finished Mar 05 12:59:21 PM PST 24
Peak memory 191272 kb
Host smart-0120af22-1a12-4951-9a1a-beaff40a0698
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900017784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.
900017784
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.467847902
Short name T178
Test name
Test status
Simulation time 109115390797 ps
CPU time 92.73 seconds
Started Mar 05 12:50:00 PM PST 24
Finished Mar 05 12:51:33 PM PST 24
Peak memory 183116 kb
Host smart-0926a506-9539-4b60-939f-f5cd17afed2d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467847902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.467847902
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.1028371339
Short name T365
Test name
Test status
Simulation time 71283315817 ps
CPU time 83.45 seconds
Started Mar 05 12:50:01 PM PST 24
Finished Mar 05 12:51:25 PM PST 24
Peak memory 182992 kb
Host smart-53df5b8d-05cf-4c1e-8324-aaa6ad4f5da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028371339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1028371339
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.879611443
Short name T241
Test name
Test status
Simulation time 2083788510203 ps
CPU time 1545.4 seconds
Started Mar 05 12:50:01 PM PST 24
Finished Mar 05 01:15:47 PM PST 24
Peak memory 191308 kb
Host smart-3318d228-5333-40ad-836f-1159fa72762e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879611443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.879611443
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.1127965146
Short name T430
Test name
Test status
Simulation time 59552846 ps
CPU time 0.6 seconds
Started Mar 05 12:50:04 PM PST 24
Finished Mar 05 12:50:04 PM PST 24
Peak memory 182864 kb
Host smart-c4fd4425-d85e-4525-823b-15d38bfb2901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127965146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1127965146
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1984507698
Short name T280
Test name
Test status
Simulation time 98293581255 ps
CPU time 45.99 seconds
Started Mar 05 12:50:03 PM PST 24
Finished Mar 05 12:50:49 PM PST 24
Peak memory 183128 kb
Host smart-fbe55ee6-9d38-4229-aa44-87a40ea2e4d0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984507698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1984507698
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2942898294
Short name T383
Test name
Test status
Simulation time 70874316405 ps
CPU time 111.76 seconds
Started Mar 05 12:50:01 PM PST 24
Finished Mar 05 12:51:54 PM PST 24
Peak memory 183100 kb
Host smart-e887890a-55b9-436a-9a69-651821d8c44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942898294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2942898294
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2613130988
Short name T321
Test name
Test status
Simulation time 50496555309 ps
CPU time 92.27 seconds
Started Mar 05 12:50:01 PM PST 24
Finished Mar 05 12:51:34 PM PST 24
Peak memory 183128 kb
Host smart-9f7fdcbb-ebd2-47cc-8f7d-2103405f5cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613130988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2613130988
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.3748857003
Short name T397
Test name
Test status
Simulation time 126004317169 ps
CPU time 192.67 seconds
Started Mar 05 12:50:06 PM PST 24
Finished Mar 05 12:53:19 PM PST 24
Peak memory 183176 kb
Host smart-5d576794-bf1b-404f-8049-90b91b20aad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748857003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3748857003
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.4246787799
Short name T136
Test name
Test status
Simulation time 125946621956 ps
CPU time 197.73 seconds
Started Mar 05 12:50:03 PM PST 24
Finished Mar 05 12:53:21 PM PST 24
Peak memory 191160 kb
Host smart-6d7d34ae-2a2f-4b7d-a928-9fab38e20230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246787799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.4246787799
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2582288063
Short name T444
Test name
Test status
Simulation time 10707973478 ps
CPU time 17.96 seconds
Started Mar 05 12:50:04 PM PST 24
Finished Mar 05 12:50:23 PM PST 24
Peak memory 183104 kb
Host smart-f3fd5c28-1e6d-49f6-8682-6e0abce2fd3c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582288063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.2582288063
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2108272424
Short name T399
Test name
Test status
Simulation time 82656348385 ps
CPU time 123.74 seconds
Started Mar 05 12:50:01 PM PST 24
Finished Mar 05 12:52:06 PM PST 24
Peak memory 183172 kb
Host smart-369fdb5d-17f6-4e27-9b0a-fb3fc2c4549b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108272424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2108272424
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.2975877760
Short name T268
Test name
Test status
Simulation time 46752172542 ps
CPU time 261.15 seconds
Started Mar 05 12:50:00 PM PST 24
Finished Mar 05 12:54:22 PM PST 24
Peak memory 191308 kb
Host smart-d2ca2aae-0f0f-4366-abd4-90be72632a38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975877760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2975877760
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.3111503638
Short name T132
Test name
Test status
Simulation time 71379527151 ps
CPU time 108.86 seconds
Started Mar 05 12:50:03 PM PST 24
Finished Mar 05 12:51:53 PM PST 24
Peak memory 191300 kb
Host smart-e931a4eb-4aea-4338-a5a2-65d966b3c1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111503638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3111503638
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1240290220
Short name T168
Test name
Test status
Simulation time 244432671293 ps
CPU time 1658.38 seconds
Started Mar 05 12:49:59 PM PST 24
Finished Mar 05 01:17:38 PM PST 24
Peak memory 191312 kb
Host smart-5a8f4dab-f810-4d57-af97-45bb25f35382
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240290220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1240290220
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3252415107
Short name T186
Test name
Test status
Simulation time 954196516558 ps
CPU time 244.15 seconds
Started Mar 05 12:49:28 PM PST 24
Finished Mar 05 12:53:32 PM PST 24
Peak memory 183160 kb
Host smart-556a76ca-d9c4-4dce-9216-5b31e4c58e35
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252415107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.3252415107
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2259988864
Short name T386
Test name
Test status
Simulation time 352175743250 ps
CPU time 164.28 seconds
Started Mar 05 12:49:24 PM PST 24
Finished Mar 05 12:52:09 PM PST 24
Peak memory 183112 kb
Host smart-db634325-5d43-4930-9bee-e97797ab9115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259988864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2259988864
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.168109475
Short name T174
Test name
Test status
Simulation time 144887670839 ps
CPU time 1520.75 seconds
Started Mar 05 12:49:26 PM PST 24
Finished Mar 05 01:14:47 PM PST 24
Peak memory 191316 kb
Host smart-7862b6f8-8d75-4138-b7c9-0d66bf64d96a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168109475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.168109475
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.1113142010
Short name T2
Test name
Test status
Simulation time 50218927607 ps
CPU time 227.51 seconds
Started Mar 05 12:49:29 PM PST 24
Finished Mar 05 12:53:17 PM PST 24
Peak memory 183124 kb
Host smart-bf34f2c8-b6ec-4dba-abbb-0ce17af94028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113142010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1113142010
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3900327197
Short name T14
Test name
Test status
Simulation time 54160778 ps
CPU time 0.76 seconds
Started Mar 05 12:49:22 PM PST 24
Finished Mar 05 12:49:23 PM PST 24
Peak memory 213432 kb
Host smart-201ae0b8-c0c1-46e5-968c-442d423795fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900327197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3900327197
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2862446106
Short name T362
Test name
Test status
Simulation time 700359339321 ps
CPU time 221.38 seconds
Started Mar 05 12:49:22 PM PST 24
Finished Mar 05 12:53:04 PM PST 24
Peak memory 193920 kb
Host smart-b67a34a1-06ba-45bd-808c-bd7b294cab42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862446106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2862446106
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.3119845513
Short name T40
Test name
Test status
Simulation time 68961691787 ps
CPU time 99.61 seconds
Started Mar 05 12:49:23 PM PST 24
Finished Mar 05 12:51:02 PM PST 24
Peak memory 205916 kb
Host smart-eb30bfb9-1b4c-4467-927c-cd6fd6474bcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119845513 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.3119845513
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2200913047
Short name T349
Test name
Test status
Simulation time 16982472180 ps
CPU time 6.75 seconds
Started Mar 05 12:50:03 PM PST 24
Finished Mar 05 12:50:10 PM PST 24
Peak memory 182984 kb
Host smart-c0f67360-dba3-4928-a067-2e093894fe07
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200913047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2200913047
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3544506296
Short name T410
Test name
Test status
Simulation time 18925224832 ps
CPU time 30.71 seconds
Started Mar 05 12:50:02 PM PST 24
Finished Mar 05 12:50:33 PM PST 24
Peak memory 183028 kb
Host smart-45ee3775-c6a3-4f82-b52f-94f81fe8edb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544506296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3544506296
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.3547502388
Short name T24
Test name
Test status
Simulation time 84802080445 ps
CPU time 144.8 seconds
Started Mar 05 12:50:00 PM PST 24
Finished Mar 05 12:52:26 PM PST 24
Peak memory 193988 kb
Host smart-a19b75de-4112-42ee-889c-2f104bc27f49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547502388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3547502388
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2428289505
Short name T432
Test name
Test status
Simulation time 941724347291 ps
CPU time 259.71 seconds
Started Mar 05 12:50:01 PM PST 24
Finished Mar 05 12:54:21 PM PST 24
Peak memory 183104 kb
Host smart-5089a7bd-8dd9-4237-a9b0-80272cb2a018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428289505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2428289505
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2622851470
Short name T183
Test name
Test status
Simulation time 285398122323 ps
CPU time 534.67 seconds
Started Mar 05 12:50:01 PM PST 24
Finished Mar 05 12:58:57 PM PST 24
Peak memory 183124 kb
Host smart-35b46aec-25fd-4e36-9c2b-fd31e05ecf5c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622851470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2622851470
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1273444631
Short name T368
Test name
Test status
Simulation time 44124347333 ps
CPU time 67.54 seconds
Started Mar 05 12:50:06 PM PST 24
Finished Mar 05 12:51:14 PM PST 24
Peak memory 183176 kb
Host smart-06e836ab-268e-406e-9ebd-a0cf181e54ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273444631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1273444631
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.1443169709
Short name T137
Test name
Test status
Simulation time 333687225471 ps
CPU time 287.2 seconds
Started Mar 05 12:50:05 PM PST 24
Finished Mar 05 12:54:52 PM PST 24
Peak memory 191248 kb
Host smart-37f6f658-1fcf-4c0b-9c91-a85af2a97289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443169709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1443169709
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.812965536
Short name T433
Test name
Test status
Simulation time 191616586464 ps
CPU time 178.48 seconds
Started Mar 05 12:50:03 PM PST 24
Finished Mar 05 12:53:02 PM PST 24
Peak memory 183100 kb
Host smart-61dbe221-226a-4965-978b-9f80c27a8b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812965536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.812965536
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.3234178308
Short name T185
Test name
Test status
Simulation time 989704415675 ps
CPU time 706.47 seconds
Started Mar 05 12:50:06 PM PST 24
Finished Mar 05 01:01:53 PM PST 24
Peak memory 191408 kb
Host smart-b34fd8b2-777e-4255-a319-f0b9f18f3611
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234178308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.3234178308
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1387433255
Short name T62
Test name
Test status
Simulation time 102420825877 ps
CPU time 124.99 seconds
Started Mar 05 12:50:00 PM PST 24
Finished Mar 05 12:52:06 PM PST 24
Peak memory 183004 kb
Host smart-fef0895d-9a0b-4c15-93fc-fd0545efe2df
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387433255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.1387433255
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3409147166
Short name T407
Test name
Test status
Simulation time 606145279129 ps
CPU time 269.79 seconds
Started Mar 05 12:50:03 PM PST 24
Finished Mar 05 12:54:33 PM PST 24
Peak memory 183080 kb
Host smart-72956f42-c2f9-4275-848b-57f041fe610d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409147166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3409147166
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.2574954089
Short name T294
Test name
Test status
Simulation time 148648191356 ps
CPU time 144.55 seconds
Started Mar 05 12:50:05 PM PST 24
Finished Mar 05 12:52:30 PM PST 24
Peak memory 191244 kb
Host smart-367bf125-04fb-45d6-9119-6d481c128823
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574954089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2574954089
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.3609198884
Short name T19
Test name
Test status
Simulation time 59612075855 ps
CPU time 97.68 seconds
Started Mar 05 12:49:59 PM PST 24
Finished Mar 05 12:51:37 PM PST 24
Peak memory 183200 kb
Host smart-9fa6fab6-787e-4ebe-979c-069590fed099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609198884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3609198884
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2342958768
Short name T72
Test name
Test status
Simulation time 182551158627 ps
CPU time 496.48 seconds
Started Mar 05 12:50:04 PM PST 24
Finished Mar 05 12:58:20 PM PST 24
Peak memory 191384 kb
Host smart-254d7c02-3562-4626-98ed-d44f1e6383fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342958768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2342958768
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.4121025215
Short name T265
Test name
Test status
Simulation time 66847164838 ps
CPU time 37.92 seconds
Started Mar 05 12:50:03 PM PST 24
Finished Mar 05 12:50:41 PM PST 24
Peak memory 183132 kb
Host smart-29076cfa-1da0-45df-bebe-dcd1e89fe054
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121025215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.4121025215
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.647608742
Short name T385
Test name
Test status
Simulation time 52308564994 ps
CPU time 80.18 seconds
Started Mar 05 12:50:05 PM PST 24
Finished Mar 05 12:51:25 PM PST 24
Peak memory 183140 kb
Host smart-953539e2-2bbe-4960-a5ea-33a1fc9fdee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647608742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.647608742
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.3794623013
Short name T337
Test name
Test status
Simulation time 60488624080 ps
CPU time 111.64 seconds
Started Mar 05 12:50:03 PM PST 24
Finished Mar 05 12:51:55 PM PST 24
Peak memory 191356 kb
Host smart-f60d04e9-5c96-4104-90df-5441ea8f1112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794623013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3794623013
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.4050305497
Short name T422
Test name
Test status
Simulation time 217512251140 ps
CPU time 87.49 seconds
Started Mar 05 12:50:11 PM PST 24
Finished Mar 05 12:51:39 PM PST 24
Peak memory 183104 kb
Host smart-d7899bde-5ea1-4149-bf92-f0fb2b3d1fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050305497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.4050305497
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.879556425
Short name T3
Test name
Test status
Simulation time 14727575379 ps
CPU time 15.57 seconds
Started Mar 05 12:50:11 PM PST 24
Finished Mar 05 12:50:27 PM PST 24
Peak memory 183136 kb
Host smart-cc3750e3-e4a0-4b0f-a6a6-0209c860ff76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879556425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.879556425
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.510599815
Short name T379
Test name
Test status
Simulation time 126402750 ps
CPU time 1.04 seconds
Started Mar 05 12:50:11 PM PST 24
Finished Mar 05 12:50:12 PM PST 24
Peak memory 193668 kb
Host smart-b3421a70-7776-49b5-b114-6901334c6abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510599815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.510599815
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.214417388
Short name T81
Test name
Test status
Simulation time 1831732825328 ps
CPU time 384.51 seconds
Started Mar 05 12:50:09 PM PST 24
Finished Mar 05 12:56:33 PM PST 24
Peak memory 183140 kb
Host smart-a14f3ee4-4216-4a5f-9c2f-2d94fdec95a3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214417388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.rv_timer_cfg_update_on_fly.214417388
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3109712996
Short name T425
Test name
Test status
Simulation time 364423669496 ps
CPU time 105.95 seconds
Started Mar 05 12:50:08 PM PST 24
Finished Mar 05 12:51:55 PM PST 24
Peak memory 183116 kb
Host smart-58b0ea9b-7565-4b34-b3e4-4649f623c105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109712996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3109712996
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.410209880
Short name T46
Test name
Test status
Simulation time 301100102793 ps
CPU time 189.06 seconds
Started Mar 05 12:50:09 PM PST 24
Finished Mar 05 12:53:18 PM PST 24
Peak memory 191164 kb
Host smart-6c695ffe-f239-433d-8ff4-bf3d9067c154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410209880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.410209880
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.625913815
Short name T176
Test name
Test status
Simulation time 572445031945 ps
CPU time 974.12 seconds
Started Mar 05 12:50:12 PM PST 24
Finished Mar 05 01:06:27 PM PST 24
Peak memory 183104 kb
Host smart-e15bece0-4718-4e8e-bedb-cd155d3025a8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625913815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.rv_timer_cfg_update_on_fly.625913815
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.406301737
Short name T376
Test name
Test status
Simulation time 30179715286 ps
CPU time 46.28 seconds
Started Mar 05 12:50:14 PM PST 24
Finished Mar 05 12:51:01 PM PST 24
Peak memory 183176 kb
Host smart-0bee0950-e093-4010-aa92-05266e4afe0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406301737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.406301737
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.375163206
Short name T344
Test name
Test status
Simulation time 207274693821 ps
CPU time 250.53 seconds
Started Mar 05 12:50:12 PM PST 24
Finished Mar 05 12:54:23 PM PST 24
Peak memory 191248 kb
Host smart-76a33109-bac8-4c33-8c03-6af02288f61a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375163206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.375163206
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.177311687
Short name T370
Test name
Test status
Simulation time 16114592 ps
CPU time 0.53 seconds
Started Mar 05 12:50:10 PM PST 24
Finished Mar 05 12:50:10 PM PST 24
Peak memory 182588 kb
Host smart-1fdbdad9-0e94-4bbf-87c3-702fb9bf75e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177311687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.177311687
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3712238749
Short name T449
Test name
Test status
Simulation time 160684223233 ps
CPU time 61.06 seconds
Started Mar 05 12:50:07 PM PST 24
Finished Mar 05 12:51:09 PM PST 24
Peak memory 194500 kb
Host smart-0ac0e2fe-1429-4b31-8a5e-d2e61f7399da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712238749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3712238749
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.2128695052
Short name T11
Test name
Test status
Simulation time 45569549708 ps
CPU time 107.04 seconds
Started Mar 05 12:50:09 PM PST 24
Finished Mar 05 12:51:56 PM PST 24
Peak memory 197824 kb
Host smart-4e5d6bec-4d10-43eb-acf6-3807c4993004
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128695052 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.2128695052
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2899012270
Short name T416
Test name
Test status
Simulation time 44323207002 ps
CPU time 67.5 seconds
Started Mar 05 12:50:14 PM PST 24
Finished Mar 05 12:51:22 PM PST 24
Peak memory 183176 kb
Host smart-c383b33b-428c-4b2a-9618-4c80849de3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899012270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2899012270
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.1000561223
Short name T290
Test name
Test status
Simulation time 97072167818 ps
CPU time 42.64 seconds
Started Mar 05 12:50:10 PM PST 24
Finished Mar 05 12:50:53 PM PST 24
Peak memory 191328 kb
Host smart-12d7156c-52cd-4e1e-bdd8-03557297a2a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000561223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1000561223
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1836317201
Short name T208
Test name
Test status
Simulation time 56418828094 ps
CPU time 173.05 seconds
Started Mar 05 12:50:21 PM PST 24
Finished Mar 05 12:53:14 PM PST 24
Peak memory 183132 kb
Host smart-eafc2ba7-9c72-4aa7-bcec-51b8c46294a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836317201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1836317201
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2356093496
Short name T65
Test name
Test status
Simulation time 38345901136 ps
CPU time 68.72 seconds
Started Mar 05 12:50:18 PM PST 24
Finished Mar 05 12:51:27 PM PST 24
Peak memory 191360 kb
Host smart-1ea09089-564c-4186-b890-6cea1b11eb02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356093496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2356093496
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3547187087
Short name T233
Test name
Test status
Simulation time 6365338316 ps
CPU time 10.23 seconds
Started Mar 05 12:50:19 PM PST 24
Finished Mar 05 12:50:30 PM PST 24
Peak memory 182980 kb
Host smart-3df3986b-a84b-460f-9899-0d636b3a1def
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547187087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3547187087
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_random.134244348
Short name T312
Test name
Test status
Simulation time 149041411133 ps
CPU time 246.55 seconds
Started Mar 05 12:50:17 PM PST 24
Finished Mar 05 12:54:24 PM PST 24
Peak memory 191272 kb
Host smart-ea4608af-7a7d-498c-b3d8-3c8d2b8ebde4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134244348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.134244348
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.1009241078
Short name T356
Test name
Test status
Simulation time 9629529585 ps
CPU time 5.6 seconds
Started Mar 05 12:50:25 PM PST 24
Finished Mar 05 12:50:31 PM PST 24
Peak memory 183112 kb
Host smart-2f2ba9fd-1923-46a9-9f9b-f6798dc5a53c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009241078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.1009241078
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.1424954136
Short name T426
Test name
Test status
Simulation time 94265785185 ps
CPU time 143.82 seconds
Started Mar 05 12:50:26 PM PST 24
Finished Mar 05 12:52:50 PM PST 24
Peak memory 183100 kb
Host smart-7881ebc2-1279-4505-8e27-d80f0b95aadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424954136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1424954136
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.1737365247
Short name T333
Test name
Test status
Simulation time 208618878612 ps
CPU time 95.43 seconds
Started Mar 05 12:50:16 PM PST 24
Finished Mar 05 12:51:52 PM PST 24
Peak memory 191216 kb
Host smart-1a9fcd29-d9e6-4619-b28e-c61edbf978fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737365247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1737365247
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3171258300
Short name T292
Test name
Test status
Simulation time 44275660059 ps
CPU time 35.54 seconds
Started Mar 05 12:50:32 PM PST 24
Finished Mar 05 12:51:08 PM PST 24
Peak memory 183032 kb
Host smart-de047270-d258-4d58-a4a9-aa5e726058b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171258300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3171258300
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.2887594584
Short name T35
Test name
Test status
Simulation time 103720774970 ps
CPU time 163.61 seconds
Started Mar 05 12:50:25 PM PST 24
Finished Mar 05 12:53:10 PM PST 24
Peak memory 195136 kb
Host smart-ec01c321-0002-4468-b82d-bb5bbf4b3860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887594584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.2887594584
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3373381385
Short name T89
Test name
Test status
Simulation time 101291832376 ps
CPU time 176.88 seconds
Started Mar 05 12:49:21 PM PST 24
Finished Mar 05 12:52:18 PM PST 24
Peak memory 183132 kb
Host smart-d68684b3-737f-40f1-a4a0-4a715273d71b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373381385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3373381385
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.1518658157
Short name T364
Test name
Test status
Simulation time 105404882719 ps
CPU time 152.24 seconds
Started Mar 05 12:49:19 PM PST 24
Finished Mar 05 12:51:52 PM PST 24
Peak memory 183136 kb
Host smart-9d9b8e1b-4f72-4f1e-a25b-3ac05b7e6b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518658157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1518658157
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.1671572006
Short name T327
Test name
Test status
Simulation time 73689721900 ps
CPU time 71.02 seconds
Started Mar 05 12:49:22 PM PST 24
Finished Mar 05 12:50:33 PM PST 24
Peak memory 191212 kb
Host smart-9314e8a0-5737-4541-a76a-defc2aa4c366
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671572006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.1671572006
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.4012526269
Short name T413
Test name
Test status
Simulation time 31059993391 ps
CPU time 273.82 seconds
Started Mar 05 12:49:30 PM PST 24
Finished Mar 05 12:54:05 PM PST 24
Peak memory 194496 kb
Host smart-f7d6a895-3bbc-4e11-b770-ce50b288cafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012526269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.4012526269
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.698914610
Short name T15
Test name
Test status
Simulation time 37928636 ps
CPU time 0.73 seconds
Started Mar 05 12:49:18 PM PST 24
Finished Mar 05 12:49:19 PM PST 24
Peak memory 213536 kb
Host smart-5321795e-9048-4238-afe5-ced0758d81d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698914610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.698914610
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.806720175
Short name T375
Test name
Test status
Simulation time 373395770074 ps
CPU time 573.26 seconds
Started Mar 05 12:49:20 PM PST 24
Finished Mar 05 12:58:54 PM PST 24
Peak memory 195664 kb
Host smart-99874c68-bae9-45bc-ac85-12bd59386ac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806720175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.806720175
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.3535488630
Short name T380
Test name
Test status
Simulation time 249039045184 ps
CPU time 108.44 seconds
Started Mar 05 12:50:25 PM PST 24
Finished Mar 05 12:52:14 PM PST 24
Peak memory 183024 kb
Host smart-af306bd2-efac-46ec-8778-cb1fa7c070ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535488630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.3535488630
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3770627930
Short name T64
Test name
Test status
Simulation time 136043265347 ps
CPU time 1866.69 seconds
Started Mar 05 12:50:28 PM PST 24
Finished Mar 05 01:21:35 PM PST 24
Peak memory 191304 kb
Host smart-23e95b6a-edfb-4ed1-bada-051ff23dcaa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770627930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3770627930
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.297100252
Short name T300
Test name
Test status
Simulation time 315027808003 ps
CPU time 1016.27 seconds
Started Mar 05 12:50:26 PM PST 24
Finished Mar 05 01:07:22 PM PST 24
Peak memory 183228 kb
Host smart-41d7d0b1-537a-490e-9b11-2589c55852a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297100252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.297100252
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.1668327456
Short name T82
Test name
Test status
Simulation time 329569305292 ps
CPU time 198.46 seconds
Started Mar 05 12:50:26 PM PST 24
Finished Mar 05 12:53:45 PM PST 24
Peak memory 183104 kb
Host smart-e9bb5888-1356-4fdd-be7b-1b3ad4741934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668327456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1668327456
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.2035802390
Short name T441
Test name
Test status
Simulation time 39513340401 ps
CPU time 411.71 seconds
Started Mar 05 12:50:32 PM PST 24
Finished Mar 05 12:57:25 PM PST 24
Peak memory 183044 kb
Host smart-9690b405-6702-4563-bab7-8c51c515cf57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035802390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2035802390
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3639127992
Short name T442
Test name
Test status
Simulation time 342790634 ps
CPU time 0.75 seconds
Started Mar 05 12:50:33 PM PST 24
Finished Mar 05 12:50:34 PM PST 24
Peak memory 191164 kb
Host smart-307f109a-4a2c-4a44-8eb7-27de59483463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639127992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3639127992
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.582961435
Short name T182
Test name
Test status
Simulation time 562819187092 ps
CPU time 456.36 seconds
Started Mar 05 12:50:36 PM PST 24
Finished Mar 05 12:58:13 PM PST 24
Peak memory 191300 kb
Host smart-8b7417cb-e125-4b10-a81f-497cf4dd6d55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582961435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.
582961435
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1838093907
Short name T200
Test name
Test status
Simulation time 69290733487 ps
CPU time 128.7 seconds
Started Mar 05 12:50:33 PM PST 24
Finished Mar 05 12:52:43 PM PST 24
Peak memory 183140 kb
Host smart-e2c0409e-c51e-4ac6-b823-e9d3e4fc63aa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838093907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1838093907
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.4255451752
Short name T428
Test name
Test status
Simulation time 151288002522 ps
CPU time 221.25 seconds
Started Mar 05 12:50:34 PM PST 24
Finished Mar 05 12:54:15 PM PST 24
Peak memory 183024 kb
Host smart-0fc3946c-c03f-4353-bfc7-1103df190b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255451752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.4255451752
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.2669328692
Short name T7
Test name
Test status
Simulation time 481441105419 ps
CPU time 162.11 seconds
Started Mar 05 12:50:33 PM PST 24
Finished Mar 05 12:53:15 PM PST 24
Peak memory 191308 kb
Host smart-1b2ead94-f727-46e1-91b6-9957d34b76c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669328692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2669328692
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2100454
Short name T296
Test name
Test status
Simulation time 260253895502 ps
CPU time 138.73 seconds
Started Mar 05 12:50:34 PM PST 24
Finished Mar 05 12:52:54 PM PST 24
Peak memory 191316 kb
Host smart-9ae4beb9-290d-4b7f-b28a-5de454b86b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2100454
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.4194019505
Short name T373
Test name
Test status
Simulation time 663715746031 ps
CPU time 295.55 seconds
Started Mar 05 12:50:34 PM PST 24
Finished Mar 05 12:55:31 PM PST 24
Peak memory 191200 kb
Host smart-01462422-a561-477c-8660-650658023814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194019505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.4194019505
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3832287722
Short name T139
Test name
Test status
Simulation time 143411697638 ps
CPU time 213.56 seconds
Started Mar 05 12:50:44 PM PST 24
Finished Mar 05 12:54:17 PM PST 24
Peak memory 183128 kb
Host smart-587dc4c0-46ce-46e7-b18d-b2750199c42c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832287722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3832287722
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.1663939783
Short name T412
Test name
Test status
Simulation time 85234833233 ps
CPU time 62.44 seconds
Started Mar 05 12:50:42 PM PST 24
Finished Mar 05 12:51:45 PM PST 24
Peak memory 183104 kb
Host smart-22269a0f-cf34-420e-bb69-3b3c7bf7d1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663939783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1663939783
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.3013159423
Short name T256
Test name
Test status
Simulation time 53578892181 ps
CPU time 102.29 seconds
Started Mar 05 12:50:42 PM PST 24
Finished Mar 05 12:52:25 PM PST 24
Peak memory 183160 kb
Host smart-5d2016af-88d3-4ca3-b13f-e9c67a87e5ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013159423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3013159423
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.3174746350
Short name T310
Test name
Test status
Simulation time 101373302011 ps
CPU time 114.07 seconds
Started Mar 05 12:50:44 PM PST 24
Finished Mar 05 12:52:38 PM PST 24
Peak memory 191252 kb
Host smart-bf1a938f-d32e-49e1-b6ff-2c4ce9e2a54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174746350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3174746350
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.1392413545
Short name T166
Test name
Test status
Simulation time 684662981077 ps
CPU time 440.11 seconds
Started Mar 05 12:50:45 PM PST 24
Finished Mar 05 12:58:05 PM PST 24
Peak memory 191360 kb
Host smart-264556a2-e832-4231-ad9e-ede6af9d3e48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392413545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.1392413545
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2962990067
Short name T91
Test name
Test status
Simulation time 109832124523 ps
CPU time 90.59 seconds
Started Mar 05 12:50:43 PM PST 24
Finished Mar 05 12:52:14 PM PST 24
Peak memory 183124 kb
Host smart-a4a541f9-d5db-4004-ab01-c1660880bdcb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962990067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2962990067
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.1086278033
Short name T409
Test name
Test status
Simulation time 601508380117 ps
CPU time 229.09 seconds
Started Mar 05 12:50:43 PM PST 24
Finished Mar 05 12:54:33 PM PST 24
Peak memory 183116 kb
Host smart-12980eb8-34df-45c5-8df6-a72f6762d4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086278033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1086278033
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.517225465
Short name T47
Test name
Test status
Simulation time 19538293715 ps
CPU time 34.53 seconds
Started Mar 05 12:50:44 PM PST 24
Finished Mar 05 12:51:18 PM PST 24
Peak memory 191276 kb
Host smart-40be9613-c174-4d9f-822a-0a4cd1ca91b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517225465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.517225465
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.2562067992
Short name T395
Test name
Test status
Simulation time 1151191042 ps
CPU time 1.59 seconds
Started Mar 05 12:50:43 PM PST 24
Finished Mar 05 12:50:45 PM PST 24
Peak memory 182848 kb
Host smart-bfcc75c8-62f9-45c4-9642-5d27382d2fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562067992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2562067992
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3336334773
Short name T415
Test name
Test status
Simulation time 1509170857493 ps
CPU time 625.52 seconds
Started Mar 05 12:50:43 PM PST 24
Finished Mar 05 01:01:09 PM PST 24
Peak memory 191324 kb
Host smart-ec6fdd53-9268-45d8-b743-39145c6bd235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336334773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3336334773
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1362790928
Short name T445
Test name
Test status
Simulation time 189203413665 ps
CPU time 77.29 seconds
Started Mar 05 12:50:43 PM PST 24
Finished Mar 05 12:52:01 PM PST 24
Peak memory 183128 kb
Host smart-d8a5d2ee-ca22-4c43-8e00-75e2dc843904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362790928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1362790928
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.3663300566
Short name T244
Test name
Test status
Simulation time 89280901907 ps
CPU time 163.82 seconds
Started Mar 05 12:50:43 PM PST 24
Finished Mar 05 12:53:27 PM PST 24
Peak memory 183176 kb
Host smart-e654c020-b340-47bf-8d7e-fa18f3a982ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663300566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3663300566
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.1452126129
Short name T194
Test name
Test status
Simulation time 316023533095 ps
CPU time 167.19 seconds
Started Mar 05 12:50:54 PM PST 24
Finished Mar 05 12:53:41 PM PST 24
Peak memory 191252 kb
Host smart-7cb90e31-b97e-44c8-9e2f-a2ec23970861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452126129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1452126129
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.815079588
Short name T128
Test name
Test status
Simulation time 195303009000 ps
CPU time 167.12 seconds
Started Mar 05 12:50:54 PM PST 24
Finished Mar 05 12:53:41 PM PST 24
Peak memory 191348 kb
Host smart-5e6a1227-58eb-45c3-9d1c-31d49dfe3f69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815079588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.
815079588
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.866471570
Short name T12
Test name
Test status
Simulation time 68002405816 ps
CPU time 179.1 seconds
Started Mar 05 12:50:54 PM PST 24
Finished Mar 05 12:53:53 PM PST 24
Peak memory 206072 kb
Host smart-c62ba83a-1895-444d-bc2f-20ae15d2ac2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866471570 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.866471570
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3139201172
Short name T391
Test name
Test status
Simulation time 1559303411 ps
CPU time 1.27 seconds
Started Mar 05 12:50:51 PM PST 24
Finished Mar 05 12:50:53 PM PST 24
Peak memory 182888 kb
Host smart-bb52025d-31c5-405c-8695-fe74724a4397
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139201172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3139201172
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.2287400551
Short name T401
Test name
Test status
Simulation time 92536609913 ps
CPU time 67.26 seconds
Started Mar 05 12:50:53 PM PST 24
Finished Mar 05 12:52:01 PM PST 24
Peak memory 183052 kb
Host smart-17e812a3-ce72-41ac-a4df-949e70d3a23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287400551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2287400551
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.4812920
Short name T85
Test name
Test status
Simulation time 109357435488 ps
CPU time 102.17 seconds
Started Mar 05 12:50:53 PM PST 24
Finished Mar 05 12:52:35 PM PST 24
Peak memory 191180 kb
Host smart-2319e376-c4ef-4920-8f88-1eb9fb24c0e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4812920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.4812920
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.901991102
Short name T417
Test name
Test status
Simulation time 539618758 ps
CPU time 0.81 seconds
Started Mar 05 12:50:53 PM PST 24
Finished Mar 05 12:50:54 PM PST 24
Peak memory 191368 kb
Host smart-f72e8c9e-c318-4ec8-89fd-966e2f6d6196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901991102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.901991102
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2430641677
Short name T437
Test name
Test status
Simulation time 105816474657 ps
CPU time 58.41 seconds
Started Mar 05 12:50:53 PM PST 24
Finished Mar 05 12:51:51 PM PST 24
Peak memory 183076 kb
Host smart-dfcdbc8a-dcfe-4b14-9bbf-dc26ef237625
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430641677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2430641677
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2928875552
Short name T431
Test name
Test status
Simulation time 69171440447 ps
CPU time 104.71 seconds
Started Mar 05 12:50:53 PM PST 24
Finished Mar 05 12:52:38 PM PST 24
Peak memory 183104 kb
Host smart-ca991549-4c8a-4bc8-8366-3594266e7026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928875552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2928875552
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.1650048217
Short name T277
Test name
Test status
Simulation time 605717806868 ps
CPU time 1597.05 seconds
Started Mar 05 12:50:53 PM PST 24
Finished Mar 05 01:17:31 PM PST 24
Peak memory 194432 kb
Host smart-2cfc0f4e-20e1-4aae-89dd-fd561bef9a26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650048217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.1650048217
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.971618378
Short name T115
Test name
Test status
Simulation time 7369662086 ps
CPU time 11.97 seconds
Started Mar 05 12:50:58 PM PST 24
Finished Mar 05 12:51:10 PM PST 24
Peak memory 193804 kb
Host smart-43779229-a132-4af5-b800-c97ac01cde18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971618378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.971618378
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.3256644749
Short name T39
Test name
Test status
Simulation time 106027872890 ps
CPU time 1250.95 seconds
Started Mar 05 12:51:03 PM PST 24
Finished Mar 05 01:11:54 PM PST 24
Peak memory 214084 kb
Host smart-52748941-704d-49d9-88f1-51ec7a2f734f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256644749 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.3256644749
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1056556737
Short name T419
Test name
Test status
Simulation time 453688555460 ps
CPU time 231.33 seconds
Started Mar 05 12:51:00 PM PST 24
Finished Mar 05 12:54:52 PM PST 24
Peak memory 183140 kb
Host smart-5bf81628-1bcf-4166-a5cd-165de23b94ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056556737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1056556737
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.1856768371
Short name T272
Test name
Test status
Simulation time 115595493551 ps
CPU time 70.27 seconds
Started Mar 05 12:51:00 PM PST 24
Finished Mar 05 12:52:11 PM PST 24
Peak memory 183020 kb
Host smart-8bdafcc9-b8ab-4adf-85ca-44f969a04c51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856768371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1856768371
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3109795364
Short name T343
Test name
Test status
Simulation time 141236744409 ps
CPU time 202.82 seconds
Started Mar 05 12:51:13 PM PST 24
Finished Mar 05 12:54:36 PM PST 24
Peak memory 194392 kb
Host smart-939a053c-b926-4e21-a19d-09e5a1262a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109795364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3109795364
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1361870901
Short name T281
Test name
Test status
Simulation time 147640645835 ps
CPU time 596.15 seconds
Started Mar 05 12:51:00 PM PST 24
Finished Mar 05 01:00:56 PM PST 24
Peak memory 191296 kb
Host smart-cd296f55-acfe-4256-beaa-8e2bb93b19af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361870901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1361870901
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3796954943
Short name T222
Test name
Test status
Simulation time 1239963861913 ps
CPU time 702.6 seconds
Started Mar 05 12:50:59 PM PST 24
Finished Mar 05 01:02:42 PM PST 24
Peak memory 183048 kb
Host smart-e90c11c0-296a-44db-8baf-9058c1b9952b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796954943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3796954943
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3692772711
Short name T429
Test name
Test status
Simulation time 98163826599 ps
CPU time 78.56 seconds
Started Mar 05 12:51:00 PM PST 24
Finished Mar 05 12:52:19 PM PST 24
Peak memory 183052 kb
Host smart-63349c80-7f80-4898-beac-552b9a360924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692772711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3692772711
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.212429817
Short name T287
Test name
Test status
Simulation time 315521071482 ps
CPU time 281.6 seconds
Started Mar 05 12:51:00 PM PST 24
Finished Mar 05 12:55:42 PM PST 24
Peak memory 191312 kb
Host smart-5660f837-3189-4eaa-afe8-a6da52986e05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212429817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.212429817
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.4212670377
Short name T394
Test name
Test status
Simulation time 488527516 ps
CPU time 0.75 seconds
Started Mar 05 12:51:05 PM PST 24
Finished Mar 05 12:51:07 PM PST 24
Peak memory 182852 kb
Host smart-7399bd5d-b550-462f-9779-de9743c962af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212670377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.4212670377
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1475237534
Short name T435
Test name
Test status
Simulation time 80945330365 ps
CPU time 108.57 seconds
Started Mar 05 12:51:00 PM PST 24
Finished Mar 05 12:52:48 PM PST 24
Peak memory 183092 kb
Host smart-8578b390-0a94-442b-89db-066efeaf5430
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475237534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1475237534
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.107879778
Short name T350
Test name
Test status
Simulation time 821888301807 ps
CPU time 428.11 seconds
Started Mar 05 12:49:29 PM PST 24
Finished Mar 05 12:56:38 PM PST 24
Peak memory 183148 kb
Host smart-21595dfd-bdca-41d0-9ee6-e259826c788f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107879778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.rv_timer_cfg_update_on_fly.107879778
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.2306189899
Short name T436
Test name
Test status
Simulation time 130098295947 ps
CPU time 89.36 seconds
Started Mar 05 12:49:29 PM PST 24
Finished Mar 05 12:50:59 PM PST 24
Peak memory 183124 kb
Host smart-f2fa7976-d855-4ef9-b514-485aa47dde27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306189899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2306189899
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.4029112781
Short name T234
Test name
Test status
Simulation time 456570597860 ps
CPU time 326.39 seconds
Started Mar 05 12:49:38 PM PST 24
Finished Mar 05 12:55:04 PM PST 24
Peak memory 193904 kb
Host smart-5b79b315-cac9-43ac-b496-f98780d99c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029112781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.4029112781
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.627664951
Short name T249
Test name
Test status
Simulation time 544131520846 ps
CPU time 197.42 seconds
Started Mar 05 12:49:32 PM PST 24
Finished Mar 05 12:52:50 PM PST 24
Peak memory 191340 kb
Host smart-cdbc9488-7122-4cb1-9ce9-9c15f80a8772
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627664951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.627664951
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.2518446490
Short name T263
Test name
Test status
Simulation time 11131599610 ps
CPU time 17.15 seconds
Started Mar 05 12:51:11 PM PST 24
Finished Mar 05 12:51:28 PM PST 24
Peak memory 182776 kb
Host smart-4a42789f-cc45-453b-b5c0-417b816f8b56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518446490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2518446490
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.824538870
Short name T80
Test name
Test status
Simulation time 88807111739 ps
CPU time 111.72 seconds
Started Mar 05 12:51:07 PM PST 24
Finished Mar 05 12:52:59 PM PST 24
Peak memory 194128 kb
Host smart-33a8cc0f-518a-4ec8-b2ea-dc5a731a55d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824538870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.824538870
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.1801861359
Short name T329
Test name
Test status
Simulation time 68233786682 ps
CPU time 27.83 seconds
Started Mar 05 12:51:08 PM PST 24
Finished Mar 05 12:51:36 PM PST 24
Peak memory 182840 kb
Host smart-2eb59aba-1d85-4d55-9c5a-f92097d8a7d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801861359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1801861359
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.2978354735
Short name T307
Test name
Test status
Simulation time 24313862904 ps
CPU time 246.05 seconds
Started Mar 05 12:51:11 PM PST 24
Finished Mar 05 12:55:17 PM PST 24
Peak memory 183024 kb
Host smart-d30bfd60-03d3-451b-93f0-7abe1e2752b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978354735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2978354735
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.3464576600
Short name T198
Test name
Test status
Simulation time 348959465731 ps
CPU time 1309.13 seconds
Started Mar 05 12:51:10 PM PST 24
Finished Mar 05 01:13:00 PM PST 24
Peak memory 191296 kb
Host smart-09ef7b0e-c6a9-480a-bccd-1560e971dca2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464576600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3464576600
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.309027377
Short name T342
Test name
Test status
Simulation time 78628524092 ps
CPU time 128.91 seconds
Started Mar 05 12:51:08 PM PST 24
Finished Mar 05 12:53:17 PM PST 24
Peak memory 191224 kb
Host smart-45fd634c-d75e-49c4-a4aa-f8aeb82ceea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309027377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.309027377
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.713990612
Short name T278
Test name
Test status
Simulation time 171649798762 ps
CPU time 387.03 seconds
Started Mar 05 12:51:11 PM PST 24
Finished Mar 05 12:57:38 PM PST 24
Peak memory 191160 kb
Host smart-e4306d6e-9a56-4bdb-821e-df9c7f6c212e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713990612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.713990612
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.2935516687
Short name T239
Test name
Test status
Simulation time 195209954612 ps
CPU time 434.03 seconds
Started Mar 05 12:51:08 PM PST 24
Finished Mar 05 12:58:23 PM PST 24
Peak memory 194736 kb
Host smart-b453d46f-b128-479d-a61e-29ef985798b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935516687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2935516687
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3519003805
Short name T160
Test name
Test status
Simulation time 322751371871 ps
CPU time 560.84 seconds
Started Mar 05 12:51:06 PM PST 24
Finished Mar 05 01:00:27 PM PST 24
Peak memory 191300 kb
Host smart-e37b3a8e-ab34-4fe5-842e-ea48fe0e492e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519003805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3519003805
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2571950465
Short name T76
Test name
Test status
Simulation time 48685413920 ps
CPU time 27.86 seconds
Started Mar 05 12:51:12 PM PST 24
Finished Mar 05 12:51:40 PM PST 24
Peak memory 191296 kb
Host smart-addda6eb-0206-4fa6-b705-cb9242be0058
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571950465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2571950465
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.2659526000
Short name T392
Test name
Test status
Simulation time 48356361866 ps
CPU time 37.35 seconds
Started Mar 05 12:49:30 PM PST 24
Finished Mar 05 12:50:08 PM PST 24
Peak memory 183120 kb
Host smart-3ae232aa-4284-4c2e-8f3b-b4f375655649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659526000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2659526000
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.2600517607
Short name T58
Test name
Test status
Simulation time 169458741945 ps
CPU time 1972.44 seconds
Started Mar 05 12:49:34 PM PST 24
Finished Mar 05 01:22:27 PM PST 24
Peak memory 191300 kb
Host smart-db14a128-f996-47b0-b2fd-9b4e1532b479
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600517607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2600517607
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.3486901075
Short name T315
Test name
Test status
Simulation time 422390161676 ps
CPU time 111.4 seconds
Started Mar 05 12:49:29 PM PST 24
Finished Mar 05 12:51:21 PM PST 24
Peak memory 183128 kb
Host smart-30e1f763-252a-47b4-aede-f558f0f6dec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486901075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3486901075
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/61.rv_timer_random.1860329956
Short name T156
Test name
Test status
Simulation time 129792048521 ps
CPU time 160.85 seconds
Started Mar 05 12:51:07 PM PST 24
Finished Mar 05 12:53:48 PM PST 24
Peak memory 191196 kb
Host smart-8abc109b-4919-4951-9cf6-2819a19e9036
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860329956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1860329956
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.3026175903
Short name T78
Test name
Test status
Simulation time 896309512612 ps
CPU time 1421.85 seconds
Started Mar 05 12:51:07 PM PST 24
Finished Mar 05 01:14:49 PM PST 24
Peak memory 191300 kb
Host smart-9dc2d234-4cf7-4d5b-a3cb-f5b53eadaa18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026175903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3026175903
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.2203265985
Short name T319
Test name
Test status
Simulation time 38456314960 ps
CPU time 69.98 seconds
Started Mar 05 12:51:10 PM PST 24
Finished Mar 05 12:52:20 PM PST 24
Peak memory 191324 kb
Host smart-92a92cb8-3d92-4d8e-8220-64b76c0de933
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203265985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2203265985
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2617681462
Short name T190
Test name
Test status
Simulation time 22608524722 ps
CPU time 34.89 seconds
Started Mar 05 12:51:12 PM PST 24
Finished Mar 05 12:51:47 PM PST 24
Peak memory 191224 kb
Host smart-cec9284f-82f7-4c16-8104-73122b1eea43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617681462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2617681462
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.2992990002
Short name T111
Test name
Test status
Simulation time 396932525197 ps
CPU time 348.74 seconds
Started Mar 05 12:51:17 PM PST 24
Finished Mar 05 12:57:06 PM PST 24
Peak memory 191388 kb
Host smart-a1fbf5eb-1403-4bc9-ad3e-39643ef17dfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992990002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2992990002
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.3382254462
Short name T411
Test name
Test status
Simulation time 43656918998 ps
CPU time 88.01 seconds
Started Mar 05 12:51:15 PM PST 24
Finished Mar 05 12:52:44 PM PST 24
Peak memory 183000 kb
Host smart-f07c3f00-7fad-4dc6-987f-10fcf451f3a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382254462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3382254462
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.681210539
Short name T130
Test name
Test status
Simulation time 601592239565 ps
CPU time 599.2 seconds
Started Mar 05 12:51:22 PM PST 24
Finished Mar 05 01:01:22 PM PST 24
Peak memory 191300 kb
Host smart-ba6aff47-0757-4761-aeb0-9c8b5be0a842
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681210539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.681210539
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3760229520
Short name T43
Test name
Test status
Simulation time 91507795163 ps
CPU time 154.64 seconds
Started Mar 05 12:49:31 PM PST 24
Finished Mar 05 12:52:06 PM PST 24
Peak memory 182916 kb
Host smart-ee0f0d5c-bfd7-4851-aea1-6be2af711ebb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760229520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3760229520
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.387678630
Short name T331
Test name
Test status
Simulation time 174502089312 ps
CPU time 77.35 seconds
Started Mar 05 12:49:29 PM PST 24
Finished Mar 05 12:50:47 PM PST 24
Peak memory 194744 kb
Host smart-2cc0cf79-b703-4879-8af1-3e6675660aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387678630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.387678630
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/72.rv_timer_random.216907245
Short name T134
Test name
Test status
Simulation time 202912799956 ps
CPU time 395.15 seconds
Started Mar 05 12:51:17 PM PST 24
Finished Mar 05 12:57:52 PM PST 24
Peak memory 191248 kb
Host smart-a0711bae-103e-4254-9da5-74d41693e6b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216907245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.216907245
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.2862249212
Short name T214
Test name
Test status
Simulation time 90477576430 ps
CPU time 444.33 seconds
Started Mar 05 12:51:16 PM PST 24
Finished Mar 05 12:58:41 PM PST 24
Peak memory 183096 kb
Host smart-fb60bf31-913d-45c8-9f06-edd25ea85c6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862249212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2862249212
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3716474636
Short name T328
Test name
Test status
Simulation time 877953142085 ps
CPU time 1257.78 seconds
Started Mar 05 12:51:19 PM PST 24
Finished Mar 05 01:12:17 PM PST 24
Peak memory 194352 kb
Host smart-8f2e0458-7e13-4b7f-8640-4d74cc14aa3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716474636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3716474636
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.1483961601
Short name T171
Test name
Test status
Simulation time 284615184852 ps
CPU time 410.25 seconds
Started Mar 05 12:51:18 PM PST 24
Finished Mar 05 12:58:08 PM PST 24
Peak memory 193348 kb
Host smart-68b42fda-5871-4081-ba69-790bac13d15f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483961601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1483961601
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3514424963
Short name T298
Test name
Test status
Simulation time 877961393095 ps
CPU time 472.95 seconds
Started Mar 05 12:51:21 PM PST 24
Finished Mar 05 12:59:15 PM PST 24
Peak memory 191072 kb
Host smart-a557eec0-357e-4f0b-af5d-d6db63972938
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514424963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3514424963
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.221185514
Short name T289
Test name
Test status
Simulation time 96833075148 ps
CPU time 222.75 seconds
Started Mar 05 12:51:28 PM PST 24
Finished Mar 05 12:55:11 PM PST 24
Peak memory 191188 kb
Host smart-536d3a4c-7b84-494a-8641-1a6fbab83f8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221185514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.221185514
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3338545364
Short name T147
Test name
Test status
Simulation time 29811299750 ps
CPU time 54.12 seconds
Started Mar 05 12:49:38 PM PST 24
Finished Mar 05 12:50:32 PM PST 24
Peak memory 183128 kb
Host smart-fc198574-5cff-4e37-bdae-60acd0a01e83
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338545364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3338545364
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.4072448935
Short name T86
Test name
Test status
Simulation time 80941339076 ps
CPU time 126.8 seconds
Started Mar 05 12:49:31 PM PST 24
Finished Mar 05 12:51:39 PM PST 24
Peak memory 182936 kb
Host smart-cf4bcd56-7d0a-42d5-98db-2c853c97fbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072448935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.4072448935
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.1099211448
Short name T202
Test name
Test status
Simulation time 1579327068143 ps
CPU time 411.49 seconds
Started Mar 05 12:49:31 PM PST 24
Finished Mar 05 12:56:23 PM PST 24
Peak memory 191196 kb
Host smart-381e1387-eb65-4158-b30f-f1763511cea0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099211448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1099211448
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.4079324994
Short name T216
Test name
Test status
Simulation time 88559495361 ps
CPU time 239.98 seconds
Started Mar 05 12:49:33 PM PST 24
Finished Mar 05 12:53:33 PM PST 24
Peak memory 191292 kb
Host smart-1d9af68c-65de-4120-907b-47026efdfba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079324994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.4079324994
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.1872784463
Short name T339
Test name
Test status
Simulation time 1074490269734 ps
CPU time 2067.08 seconds
Started Mar 05 12:49:32 PM PST 24
Finished Mar 05 01:24:00 PM PST 24
Peak memory 191340 kb
Host smart-eeebe396-a265-4167-805a-ac5a21e77943
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872784463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
1872784463
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.2736937449
Short name T295
Test name
Test status
Simulation time 324509333204 ps
CPU time 453.92 seconds
Started Mar 05 12:51:28 PM PST 24
Finished Mar 05 12:59:02 PM PST 24
Peak memory 194552 kb
Host smart-6f427105-e7f2-4229-a2a0-db2f26d9326b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736937449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2736937449
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1559380787
Short name T206
Test name
Test status
Simulation time 398773288485 ps
CPU time 721.67 seconds
Started Mar 05 12:51:28 PM PST 24
Finished Mar 05 01:03:30 PM PST 24
Peak memory 191320 kb
Host smart-981b06cb-57a5-4be2-b3f3-930be71f4071
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559380787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1559380787
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1221405564
Short name T377
Test name
Test status
Simulation time 59003905925 ps
CPU time 106.81 seconds
Started Mar 05 12:51:28 PM PST 24
Finished Mar 05 12:53:15 PM PST 24
Peak memory 191312 kb
Host smart-f1d151c9-e70d-4db1-91e1-d6367203ed50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221405564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1221405564
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1198490474
Short name T269
Test name
Test status
Simulation time 25837088144 ps
CPU time 42.42 seconds
Started Mar 05 12:51:29 PM PST 24
Finished Mar 05 12:52:11 PM PST 24
Peak memory 183192 kb
Host smart-747a3123-ce18-49db-af19-b5827ab88fa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198490474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1198490474
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.4191061389
Short name T179
Test name
Test status
Simulation time 646579997276 ps
CPU time 326.27 seconds
Started Mar 05 12:51:28 PM PST 24
Finished Mar 05 12:56:54 PM PST 24
Peak memory 191304 kb
Host smart-802db95d-5435-439b-ac82-24cc13ebd1da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191061389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.4191061389
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.4189996406
Short name T149
Test name
Test status
Simulation time 123522979543 ps
CPU time 1893.12 seconds
Started Mar 05 12:51:29 PM PST 24
Finished Mar 05 01:23:03 PM PST 24
Peak memory 191292 kb
Host smart-17bd306f-ccbc-4f09-b915-969269b9b8a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189996406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.4189996406
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.508858624
Short name T172
Test name
Test status
Simulation time 83372636156 ps
CPU time 302.33 seconds
Started Mar 05 12:51:28 PM PST 24
Finished Mar 05 12:56:31 PM PST 24
Peak memory 191276 kb
Host smart-0d0a83ef-2751-4637-b789-7d8d32eaac99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508858624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.508858624
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.1230114077
Short name T447
Test name
Test status
Simulation time 44501894386 ps
CPU time 572.32 seconds
Started Mar 05 12:51:27 PM PST 24
Finished Mar 05 01:01:00 PM PST 24
Peak memory 183092 kb
Host smart-ae35034a-3353-4594-8bbd-cfd2ac8dae97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230114077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1230114077
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.3167191749
Short name T155
Test name
Test status
Simulation time 513956256396 ps
CPU time 319.1 seconds
Started Mar 05 12:51:28 PM PST 24
Finished Mar 05 12:56:47 PM PST 24
Peak memory 191296 kb
Host smart-4337d4f5-a1ad-431e-85d7-5ccfe313beb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167191749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3167191749
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.1389899895
Short name T297
Test name
Test status
Simulation time 756867252962 ps
CPU time 429.56 seconds
Started Mar 05 12:49:34 PM PST 24
Finished Mar 05 12:56:44 PM PST 24
Peak memory 183136 kb
Host smart-89da83ab-e060-404a-88ad-19c6fcc5ee97
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389899895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.1389899895
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.2463522320
Short name T49
Test name
Test status
Simulation time 56874197079 ps
CPU time 84.95 seconds
Started Mar 05 12:49:30 PM PST 24
Finished Mar 05 12:50:56 PM PST 24
Peak memory 182968 kb
Host smart-c6f219cf-a772-4e34-8cfd-73b095c6865c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463522320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2463522320
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.3034372273
Short name T427
Test name
Test status
Simulation time 85654433874 ps
CPU time 1563.02 seconds
Started Mar 05 12:49:30 PM PST 24
Finished Mar 05 01:15:34 PM PST 24
Peak memory 183092 kb
Host smart-e7c32a77-4dfb-4493-98cb-821636f6e490
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034372273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3034372273
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.664032075
Short name T251
Test name
Test status
Simulation time 284399600133 ps
CPU time 587.07 seconds
Started Mar 05 12:49:33 PM PST 24
Finished Mar 05 12:59:21 PM PST 24
Peak memory 191324 kb
Host smart-4f935765-57a8-4b30-bba2-ff8c7a69f889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664032075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.664032075
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.3698995017
Short name T322
Test name
Test status
Simulation time 187205825520 ps
CPU time 385.48 seconds
Started Mar 05 12:51:51 PM PST 24
Finished Mar 05 12:58:16 PM PST 24
Peak memory 194600 kb
Host smart-b121536a-6bad-4097-9d0e-60bb9bd72d4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698995017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3698995017
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.677025719
Short name T167
Test name
Test status
Simulation time 1247883401026 ps
CPU time 338.99 seconds
Started Mar 05 12:51:29 PM PST 24
Finished Mar 05 12:57:08 PM PST 24
Peak memory 191224 kb
Host smart-4a04e9eb-2bdd-40d1-b48d-fd02c97f2b25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677025719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.677025719
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3695922462
Short name T346
Test name
Test status
Simulation time 104469867919 ps
CPU time 163.56 seconds
Started Mar 05 12:51:29 PM PST 24
Finished Mar 05 12:54:13 PM PST 24
Peak memory 194688 kb
Host smart-ad8a33d4-62f6-475f-8a64-659b0f777fde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695922462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3695922462
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.1395489408
Short name T371
Test name
Test status
Simulation time 41071892463 ps
CPU time 59.26 seconds
Started Mar 05 12:51:28 PM PST 24
Finished Mar 05 12:52:28 PM PST 24
Peak memory 183092 kb
Host smart-e7ca3e01-e7b2-4344-b8e7-1ebe19d1b5fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395489408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1395489408
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.462746871
Short name T403
Test name
Test status
Simulation time 151073072107 ps
CPU time 145.52 seconds
Started Mar 05 12:51:34 PM PST 24
Finished Mar 05 12:54:00 PM PST 24
Peak memory 194412 kb
Host smart-2623d5fb-2515-4400-bc6d-f16127e6db80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462746871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.462746871
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3979933317
Short name T188
Test name
Test status
Simulation time 183791799504 ps
CPU time 994.3 seconds
Started Mar 05 12:51:34 PM PST 24
Finished Mar 05 01:08:09 PM PST 24
Peak memory 191224 kb
Host smart-d3d57607-bfda-4833-8e52-82f5b9357a56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979933317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3979933317
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.4181574597
Short name T359
Test name
Test status
Simulation time 12115453547 ps
CPU time 20.78 seconds
Started Mar 05 12:51:38 PM PST 24
Finished Mar 05 12:51:59 PM PST 24
Peak memory 183100 kb
Host smart-dc553768-d3b8-4238-b040-6e878b36066f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181574597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.4181574597
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2480875410
Short name T48
Test name
Test status
Simulation time 24957938630 ps
CPU time 51.51 seconds
Started Mar 05 12:51:39 PM PST 24
Finished Mar 05 12:52:30 PM PST 24
Peak memory 183096 kb
Host smart-736c074b-1196-4bed-b705-fc2c10c3033e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480875410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2480875410
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.715992899
Short name T242
Test name
Test status
Simulation time 122947118259 ps
CPU time 89.57 seconds
Started Mar 05 12:51:33 PM PST 24
Finished Mar 05 12:53:03 PM PST 24
Peak memory 191300 kb
Host smart-ccf272cd-2bce-432d-81fd-e2cbd1b1edab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715992899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.715992899
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1631501727
Short name T270
Test name
Test status
Simulation time 213075507792 ps
CPU time 114.95 seconds
Started Mar 05 12:51:34 PM PST 24
Finished Mar 05 12:53:30 PM PST 24
Peak memory 193444 kb
Host smart-e05443e7-a50c-4a72-815d-963d3435e9d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631501727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1631501727
Directory /workspace/99.rv_timer_random/latest
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