Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.51 99.36 98.73 100.00 100.00 100.00 98.98


Total test records in report: 580
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T509 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2681597175 Mar 07 12:56:15 PM PST 24 Mar 07 12:56:15 PM PST 24 53800341 ps
T84 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3971452051 Mar 07 12:56:17 PM PST 24 Mar 07 12:56:18 PM PST 24 25507127 ps
T85 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.2770328114 Mar 07 12:56:25 PM PST 24 Mar 07 12:56:26 PM PST 24 53850185 ps
T510 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.54897153 Mar 07 12:57:00 PM PST 24 Mar 07 12:57:01 PM PST 24 53552542 ps
T511 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1041884339 Mar 07 12:56:49 PM PST 24 Mar 07 12:56:50 PM PST 24 41019163 ps
T512 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2980082160 Mar 07 12:56:15 PM PST 24 Mar 07 12:56:17 PM PST 24 266812852 ps
T513 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2005463468 Mar 07 12:56:29 PM PST 24 Mar 07 12:56:30 PM PST 24 74518852 ps
T514 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.959796315 Mar 07 12:56:18 PM PST 24 Mar 07 12:56:19 PM PST 24 80220258 ps
T515 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3454808014 Mar 07 12:56:26 PM PST 24 Mar 07 12:56:27 PM PST 24 73837617 ps
T516 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2540546157 Mar 07 12:56:28 PM PST 24 Mar 07 12:56:29 PM PST 24 33718543 ps
T517 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.109563552 Mar 07 12:56:30 PM PST 24 Mar 07 12:56:32 PM PST 24 230585786 ps
T518 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1201529877 Mar 07 12:56:11 PM PST 24 Mar 07 12:56:11 PM PST 24 32147310 ps
T519 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3897271468 Mar 07 12:56:28 PM PST 24 Mar 07 12:56:29 PM PST 24 17006016 ps
T520 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2827913238 Mar 07 12:56:05 PM PST 24 Mar 07 12:56:07 PM PST 24 69343698 ps
T86 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.4264670572 Mar 07 12:56:14 PM PST 24 Mar 07 12:56:15 PM PST 24 30529005 ps
T521 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3311516925 Mar 07 12:56:17 PM PST 24 Mar 07 12:56:20 PM PST 24 238288043 ps
T522 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.732571398 Mar 07 12:56:22 PM PST 24 Mar 07 12:56:23 PM PST 24 35350935 ps
T523 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3790556176 Mar 07 12:56:26 PM PST 24 Mar 07 12:56:26 PM PST 24 73422414 ps
T524 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.4037370440 Mar 07 12:56:39 PM PST 24 Mar 07 12:56:41 PM PST 24 54030845 ps
T525 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1783980579 Mar 07 12:56:27 PM PST 24 Mar 07 12:56:28 PM PST 24 17050731 ps
T526 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3521336310 Mar 07 12:56:20 PM PST 24 Mar 07 12:56:22 PM PST 24 39459946 ps
T527 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2908915201 Mar 07 12:56:17 PM PST 24 Mar 07 12:56:18 PM PST 24 97098384 ps
T528 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2920766979 Mar 07 12:56:28 PM PST 24 Mar 07 12:56:28 PM PST 24 19607608 ps
T529 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2783186876 Mar 07 12:56:47 PM PST 24 Mar 07 12:56:47 PM PST 24 36011173 ps
T530 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.245944142 Mar 07 12:56:19 PM PST 24 Mar 07 12:56:21 PM PST 24 60640683 ps
T531 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1724017909 Mar 07 12:56:26 PM PST 24 Mar 07 12:56:27 PM PST 24 39884262 ps
T532 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2364591243 Mar 07 12:56:23 PM PST 24 Mar 07 12:56:24 PM PST 24 36552110 ps
T533 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2671209263 Mar 07 12:56:25 PM PST 24 Mar 07 12:56:26 PM PST 24 13986563 ps
T534 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1274892440 Mar 07 12:56:29 PM PST 24 Mar 07 12:56:32 PM PST 24 156307595 ps
T535 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.988577269 Mar 07 12:56:11 PM PST 24 Mar 07 12:56:12 PM PST 24 86360360 ps
T87 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1134033539 Mar 07 12:56:32 PM PST 24 Mar 07 12:56:33 PM PST 24 18613675 ps
T536 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.4165167021 Mar 07 12:56:42 PM PST 24 Mar 07 12:56:43 PM PST 24 25788806 ps
T537 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.270616475 Mar 07 12:56:24 PM PST 24 Mar 07 12:56:25 PM PST 24 64901752 ps
T538 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3277883749 Mar 07 12:56:26 PM PST 24 Mar 07 12:56:26 PM PST 24 38918066 ps
T539 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.211359689 Mar 07 12:56:43 PM PST 24 Mar 07 12:56:44 PM PST 24 22539427 ps
T540 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3585780853 Mar 07 12:56:10 PM PST 24 Mar 07 12:56:10 PM PST 24 25832729 ps
T88 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.664197770 Mar 07 12:56:10 PM PST 24 Mar 07 12:56:13 PM PST 24 412482961 ps
T541 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3869521777 Mar 07 12:56:45 PM PST 24 Mar 07 12:56:56 PM PST 24 11907703 ps
T542 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.794613934 Mar 07 12:56:30 PM PST 24 Mar 07 12:56:32 PM PST 24 135148342 ps
T543 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1778817412 Mar 07 12:56:23 PM PST 24 Mar 07 12:56:24 PM PST 24 26613751 ps
T544 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3809301220 Mar 07 12:56:44 PM PST 24 Mar 07 12:56:44 PM PST 24 29904151 ps
T545 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.885614275 Mar 07 12:56:42 PM PST 24 Mar 07 12:56:43 PM PST 24 11490484 ps
T546 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.4132140758 Mar 07 12:56:27 PM PST 24 Mar 07 12:56:28 PM PST 24 164128881 ps
T547 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3473187461 Mar 07 12:56:31 PM PST 24 Mar 07 12:56:32 PM PST 24 34970575 ps
T548 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.320287463 Mar 07 12:56:24 PM PST 24 Mar 07 12:56:25 PM PST 24 44964636 ps
T549 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1240580754 Mar 07 12:56:17 PM PST 24 Mar 07 12:56:19 PM PST 24 99959944 ps
T550 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1785583606 Mar 07 12:56:33 PM PST 24 Mar 07 12:56:34 PM PST 24 44257017 ps
T551 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.658644312 Mar 07 12:56:11 PM PST 24 Mar 07 12:56:11 PM PST 24 50572503 ps
T552 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.290288792 Mar 07 12:56:02 PM PST 24 Mar 07 12:56:04 PM PST 24 130227565 ps
T553 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1403678109 Mar 07 12:56:24 PM PST 24 Mar 07 12:56:26 PM PST 24 382457821 ps
T554 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3847292031 Mar 07 12:56:56 PM PST 24 Mar 07 12:56:57 PM PST 24 111023963 ps
T555 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1014005527 Mar 07 12:56:41 PM PST 24 Mar 07 12:56:42 PM PST 24 13128209 ps
T89 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1781811127 Mar 07 12:56:05 PM PST 24 Mar 07 12:56:06 PM PST 24 17027114 ps
T556 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1210126267 Mar 07 12:56:50 PM PST 24 Mar 07 12:56:50 PM PST 24 18694253 ps
T557 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3770330334 Mar 07 12:56:09 PM PST 24 Mar 07 12:56:12 PM PST 24 61590668 ps
T558 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2841118726 Mar 07 12:56:26 PM PST 24 Mar 07 12:56:27 PM PST 24 34200791 ps
T91 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3255666092 Mar 07 12:56:30 PM PST 24 Mar 07 12:56:31 PM PST 24 110547786 ps
T559 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1388046849 Mar 07 12:56:11 PM PST 24 Mar 07 12:56:12 PM PST 24 142667290 ps
T560 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.4226946167 Mar 07 12:56:41 PM PST 24 Mar 07 12:56:42 PM PST 24 14277306 ps
T561 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1257048927 Mar 07 12:56:09 PM PST 24 Mar 07 12:56:10 PM PST 24 43695941 ps
T562 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.748107521 Mar 07 12:56:17 PM PST 24 Mar 07 12:56:20 PM PST 24 46467441 ps
T563 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3971430235 Mar 07 12:56:22 PM PST 24 Mar 07 12:56:23 PM PST 24 41977631 ps
T564 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3858587815 Mar 07 12:56:33 PM PST 24 Mar 07 12:56:33 PM PST 24 121926012 ps
T90 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1702619444 Mar 07 12:56:39 PM PST 24 Mar 07 12:56:40 PM PST 24 21643470 ps
T565 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3543054822 Mar 07 12:56:31 PM PST 24 Mar 07 12:56:32 PM PST 24 28958275 ps
T566 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1039600425 Mar 07 12:56:28 PM PST 24 Mar 07 12:56:28 PM PST 24 19210553 ps
T567 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3695162626 Mar 07 12:56:44 PM PST 24 Mar 07 12:56:44 PM PST 24 15353157 ps
T568 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2236044053 Mar 07 12:56:22 PM PST 24 Mar 07 12:56:23 PM PST 24 112981027 ps
T569 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.887573939 Mar 07 12:56:56 PM PST 24 Mar 07 12:56:57 PM PST 24 46813848 ps
T570 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.513227335 Mar 07 12:57:11 PM PST 24 Mar 07 12:57:12 PM PST 24 90549027 ps
T571 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.597932697 Mar 07 12:56:20 PM PST 24 Mar 07 12:56:21 PM PST 24 15165776 ps
T572 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3367164910 Mar 07 12:56:48 PM PST 24 Mar 07 12:56:49 PM PST 24 46949225 ps
T573 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3901793089 Mar 07 12:56:32 PM PST 24 Mar 07 12:56:33 PM PST 24 43716146 ps
T574 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3554131679 Mar 07 12:56:38 PM PST 24 Mar 07 12:56:40 PM PST 24 320819514 ps
T575 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3269680769 Mar 07 12:56:20 PM PST 24 Mar 07 12:56:21 PM PST 24 19728152 ps
T576 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.759793113 Mar 07 12:56:20 PM PST 24 Mar 07 12:56:21 PM PST 24 17929440 ps
T577 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1619220466 Mar 07 12:56:27 PM PST 24 Mar 07 12:56:30 PM PST 24 474371927 ps
T578 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.701363842 Mar 07 12:56:24 PM PST 24 Mar 07 12:56:26 PM PST 24 241609962 ps
T579 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1592794129 Mar 07 12:56:48 PM PST 24 Mar 07 12:56:50 PM PST 24 180175984 ps
T580 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3184493196 Mar 07 12:56:25 PM PST 24 Mar 07 12:56:29 PM PST 24 1104142327 ps

Test location /workspace/coverage/default/11.rv_timer_stress_all.1540512386
Short name T10
Test name
Test status
Simulation time 689834520090 ps
CPU time 1668.44 seconds
Started Mar 07 01:01:34 PM PST 24
Finished Mar 07 01:29:23 PM PST 24
Peak memory 191652 kb
Host smart-d680dda8-8be3-447d-b204-3388ebcc1cfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540512386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1540512386
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.4265260451
Short name T14
Test name
Test status
Simulation time 47485823032 ps
CPU time 90.19 seconds
Started Mar 07 01:01:42 PM PST 24
Finished Mar 07 01:03:12 PM PST 24
Peak memory 206292 kb
Host smart-775336ce-f61d-437b-8ef9-f4461d3ea857
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265260451 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.4265260451
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_random.3059077069
Short name T130
Test name
Test status
Simulation time 850970011945 ps
CPU time 1071.11 seconds
Started Mar 07 01:01:46 PM PST 24
Finished Mar 07 01:19:37 PM PST 24
Peak memory 191568 kb
Host smart-0eef2496-05c1-4b56-b918-4d69e687aa31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059077069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3059077069
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.337180675
Short name T30
Test name
Test status
Simulation time 196777485 ps
CPU time 0.81 seconds
Started Mar 07 12:56:12 PM PST 24
Finished Mar 07 12:56:13 PM PST 24
Peak memory 193684 kb
Host smart-8006a849-c5f1-4041-b17c-de0e0f31be7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337180675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int
g_err.337180675
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.414178053
Short name T112
Test name
Test status
Simulation time 2401665554124 ps
CPU time 2902.75 seconds
Started Mar 07 01:01:26 PM PST 24
Finished Mar 07 01:49:51 PM PST 24
Peak memory 191656 kb
Host smart-4e6849e4-dfaa-4151-aaa5-c39ccb8396a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414178053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.414178053
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.4157546974
Short name T64
Test name
Test status
Simulation time 662492823988 ps
CPU time 945.3 seconds
Started Mar 07 01:01:39 PM PST 24
Finished Mar 07 01:17:25 PM PST 24
Peak memory 191648 kb
Host smart-3dcb9d15-c13f-442c-86df-2066dc6ae814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157546974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.4157546974
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.1391279140
Short name T136
Test name
Test status
Simulation time 3698081994706 ps
CPU time 1904.56 seconds
Started Mar 07 01:01:35 PM PST 24
Finished Mar 07 01:33:20 PM PST 24
Peak memory 191612 kb
Host smart-6cd8e840-8d1a-4539-8326-d4c06bbd9877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391279140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.1391279140
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.832909399
Short name T137
Test name
Test status
Simulation time 1271496871865 ps
CPU time 1368.57 seconds
Started Mar 07 01:01:52 PM PST 24
Finished Mar 07 01:24:41 PM PST 24
Peak memory 191556 kb
Host smart-1c0d38b9-0310-4b07-87c4-6f5f485b8f0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832909399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
832909399
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.2326328716
Short name T196
Test name
Test status
Simulation time 1551888576441 ps
CPU time 2138.36 seconds
Started Mar 07 01:01:25 PM PST 24
Finished Mar 07 01:37:04 PM PST 24
Peak memory 191568 kb
Host smart-d4115a62-0863-485b-b1ef-062ab8cd6251
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326328716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.2326328716
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.3504841028
Short name T36
Test name
Test status
Simulation time 79440676048 ps
CPU time 692.1 seconds
Started Mar 07 01:01:34 PM PST 24
Finished Mar 07 01:13:06 PM PST 24
Peak memory 206612 kb
Host smart-68b9aae9-8f29-4a3d-90ce-f1e35973345b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504841028 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.3504841028
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.1365815417
Short name T47
Test name
Test status
Simulation time 1110066712015 ps
CPU time 992.33 seconds
Started Mar 07 01:01:50 PM PST 24
Finished Mar 07 01:18:23 PM PST 24
Peak memory 191484 kb
Host smart-596a94d3-e8eb-4884-9c9c-eb3269f602a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365815417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.1365815417
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2449612242
Short name T9
Test name
Test status
Simulation time 1688108026022 ps
CPU time 1233.16 seconds
Started Mar 07 01:01:38 PM PST 24
Finished Mar 07 01:22:12 PM PST 24
Peak memory 191684 kb
Host smart-817f29fe-323c-4598-9a21-1485e4c5b2b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449612242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2449612242
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2323542532
Short name T20
Test name
Test status
Simulation time 130568464 ps
CPU time 0.74 seconds
Started Mar 07 01:01:10 PM PST 24
Finished Mar 07 01:01:11 PM PST 24
Peak memory 213564 kb
Host smart-90bceb8b-c55a-451d-981e-e5f6117db49f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323542532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2323542532
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.2523222563
Short name T258
Test name
Test status
Simulation time 1933236383098 ps
CPU time 1736.29 seconds
Started Mar 07 01:01:04 PM PST 24
Finished Mar 07 01:30:01 PM PST 24
Peak memory 195644 kb
Host smart-5687f694-b7d9-4d15-80e8-291da778650a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523222563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
2523222563
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3341713962
Short name T187
Test name
Test status
Simulation time 945654719546 ps
CPU time 1074.77 seconds
Started Mar 07 01:01:30 PM PST 24
Finished Mar 07 01:19:25 PM PST 24
Peak memory 191568 kb
Host smart-b77ffa72-0596-4d81-a342-3deaf9e2c98f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341713962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3341713962
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.456985433
Short name T58
Test name
Test status
Simulation time 1477428805761 ps
CPU time 1027.52 seconds
Started Mar 07 01:01:14 PM PST 24
Finished Mar 07 01:18:22 PM PST 24
Peak memory 196476 kb
Host smart-d9824dd4-0a80-4401-a014-d9c6258643c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456985433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.456985433
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2515849938
Short name T180
Test name
Test status
Simulation time 2121005946741 ps
CPU time 2434.4 seconds
Started Mar 07 01:01:52 PM PST 24
Finished Mar 07 01:42:27 PM PST 24
Peak memory 191636 kb
Host smart-5c64d43d-6304-4037-8730-61a1a4cdb3ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515849938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2515849938
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.663440304
Short name T274
Test name
Test status
Simulation time 2728067223632 ps
CPU time 1385.02 seconds
Started Mar 07 01:01:23 PM PST 24
Finished Mar 07 01:24:29 PM PST 24
Peak memory 191604 kb
Host smart-21de302a-ba19-4404-a92e-6d6b5eef0496
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663440304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.663440304
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_random.931359201
Short name T219
Test name
Test status
Simulation time 1925472292593 ps
CPU time 1517.76 seconds
Started Mar 07 01:01:18 PM PST 24
Finished Mar 07 01:26:36 PM PST 24
Peak memory 191572 kb
Host smart-01a311d9-d130-4f9d-bbcf-7b4c33eeb358
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931359201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.931359201
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.384349070
Short name T113
Test name
Test status
Simulation time 5991801671904 ps
CPU time 3309.27 seconds
Started Mar 07 01:01:29 PM PST 24
Finished Mar 07 01:56:39 PM PST 24
Peak memory 195328 kb
Host smart-c691bb66-1ac6-43e0-9a9d-5cc5821e64dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384349070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.384349070
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.483637006
Short name T148
Test name
Test status
Simulation time 877008272445 ps
CPU time 1151.85 seconds
Started Mar 07 01:01:20 PM PST 24
Finished Mar 07 01:20:33 PM PST 24
Peak memory 196156 kb
Host smart-72d85c42-8150-4f43-86f6-6242fe05786c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483637006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.483637006
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1467127760
Short name T265
Test name
Test status
Simulation time 233558236114 ps
CPU time 249.98 seconds
Started Mar 07 01:01:30 PM PST 24
Finished Mar 07 01:05:40 PM PST 24
Peak memory 191652 kb
Host smart-61498397-e64a-47dc-9594-c4854a7d30c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467127760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1467127760
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1272506764
Short name T81
Test name
Test status
Simulation time 12156980 ps
CPU time 0.56 seconds
Started Mar 07 12:56:21 PM PST 24
Finished Mar 07 12:56:21 PM PST 24
Peak memory 182356 kb
Host smart-f16b3202-4285-42e8-a469-0d076c264c70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272506764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1272506764
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.500490977
Short name T312
Test name
Test status
Simulation time 908639854674 ps
CPU time 640.55 seconds
Started Mar 07 01:01:36 PM PST 24
Finished Mar 07 01:12:17 PM PST 24
Peak memory 191588 kb
Host smart-f5fb4bca-f156-4b61-a7e8-fa1cb37403e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500490977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.
500490977
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_random.1018021915
Short name T261
Test name
Test status
Simulation time 529674095716 ps
CPU time 1354.35 seconds
Started Mar 07 01:01:44 PM PST 24
Finished Mar 07 01:24:19 PM PST 24
Peak memory 191596 kb
Host smart-9a7cc9d5-0727-49d4-8c0e-94f77ca318e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018021915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1018021915
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.194154094
Short name T177
Test name
Test status
Simulation time 587748435671 ps
CPU time 2334.21 seconds
Started Mar 07 01:01:47 PM PST 24
Finished Mar 07 01:40:42 PM PST 24
Peak memory 191624 kb
Host smart-f93f4038-c512-4428-9781-9eb9da37f19f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194154094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.
194154094
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_random.1660496813
Short name T125
Test name
Test status
Simulation time 682787413234 ps
CPU time 575.7 seconds
Started Mar 07 01:01:49 PM PST 24
Finished Mar 07 01:11:25 PM PST 24
Peak memory 191496 kb
Host smart-511a02c1-3873-4a1e-853d-64aa92bbcf4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660496813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1660496813
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.2509933328
Short name T122
Test name
Test status
Simulation time 297060498464 ps
CPU time 344.97 seconds
Started Mar 07 01:01:58 PM PST 24
Finished Mar 07 01:07:44 PM PST 24
Peak memory 191596 kb
Host smart-068783b0-23a4-4296-aa76-fc2117284b12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509933328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2509933328
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.4156624821
Short name T161
Test name
Test status
Simulation time 2172505487270 ps
CPU time 1473.8 seconds
Started Mar 07 01:01:41 PM PST 24
Finished Mar 07 01:26:15 PM PST 24
Peak memory 191564 kb
Host smart-8257f3d9-a0fa-4b20-932e-94d727f4e8fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156624821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.4156624821
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3631500663
Short name T251
Test name
Test status
Simulation time 6518859568516 ps
CPU time 2691.65 seconds
Started Mar 07 01:01:50 PM PST 24
Finished Mar 07 01:46:42 PM PST 24
Peak memory 191544 kb
Host smart-6c5782cf-413c-4f7f-b8f2-b1f2693336f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631500663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3631500663
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.3728826684
Short name T281
Test name
Test status
Simulation time 293254678744 ps
CPU time 159.54 seconds
Started Mar 07 01:01:29 PM PST 24
Finished Mar 07 01:04:09 PM PST 24
Peak memory 183320 kb
Host smart-2bab8fc0-1e48-400f-b2cf-d1c0c841779e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728826684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3728826684
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2777069731
Short name T186
Test name
Test status
Simulation time 527764747268 ps
CPU time 324.18 seconds
Started Mar 07 01:01:43 PM PST 24
Finished Mar 07 01:07:07 PM PST 24
Peak memory 183356 kb
Host smart-7ac28892-9cf5-4b97-bb51-77507e3c3f96
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777069731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2777069731
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/75.rv_timer_random.3823813672
Short name T114
Test name
Test status
Simulation time 666377766128 ps
CPU time 743.09 seconds
Started Mar 07 01:01:57 PM PST 24
Finished Mar 07 01:14:21 PM PST 24
Peak memory 191584 kb
Host smart-935c6c4d-4856-4693-b030-2f49b0d51637
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823813672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3823813672
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random.1950381686
Short name T249
Test name
Test status
Simulation time 273312856386 ps
CPU time 582.75 seconds
Started Mar 07 01:01:22 PM PST 24
Finished Mar 07 01:11:06 PM PST 24
Peak memory 193740 kb
Host smart-bd6e725b-69c0-405e-810b-2c2289be6a1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950381686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1950381686
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.3383820065
Short name T75
Test name
Test status
Simulation time 116347073596 ps
CPU time 185.08 seconds
Started Mar 07 01:01:45 PM PST 24
Finished Mar 07 01:04:51 PM PST 24
Peak memory 194424 kb
Host smart-3a445f46-7808-4a79-a230-5d376671451c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383820065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3383820065
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.1472343099
Short name T153
Test name
Test status
Simulation time 591817252343 ps
CPU time 587.37 seconds
Started Mar 07 01:02:00 PM PST 24
Finished Mar 07 01:11:48 PM PST 24
Peak memory 191588 kb
Host smart-c3e313f9-3fc1-4c56-8ab0-e3f2884802d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472343099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1472343099
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.2518655279
Short name T205
Test name
Test status
Simulation time 1082317547574 ps
CPU time 229.92 seconds
Started Mar 07 01:02:14 PM PST 24
Finished Mar 07 01:06:04 PM PST 24
Peak memory 195456 kb
Host smart-99f2cd3c-bd1d-41f1-8e6a-af0b36dcd5fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518655279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.2518655279
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.738817628
Short name T291
Test name
Test status
Simulation time 131693822005 ps
CPU time 291.5 seconds
Started Mar 07 01:01:06 PM PST 24
Finished Mar 07 01:05:58 PM PST 24
Peak memory 191608 kb
Host smart-8802df27-c394-45ee-a800-52ffebcef9e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738817628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.738817628
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.910887955
Short name T11
Test name
Test status
Simulation time 334840797065 ps
CPU time 1360.71 seconds
Started Mar 07 01:01:54 PM PST 24
Finished Mar 07 01:24:40 PM PST 24
Peak memory 191616 kb
Host smart-9e82c2cf-3144-4e64-ac7e-bfac061fbb50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910887955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.910887955
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.571909914
Short name T43
Test name
Test status
Simulation time 108699922446 ps
CPU time 222.58 seconds
Started Mar 07 01:02:04 PM PST 24
Finished Mar 07 01:05:47 PM PST 24
Peak memory 191692 kb
Host smart-f20527ad-a05e-4b3b-b056-d8fc74df14bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571909914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.571909914
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.268279661
Short name T140
Test name
Test status
Simulation time 3700386140252 ps
CPU time 936.48 seconds
Started Mar 07 01:02:00 PM PST 24
Finished Mar 07 01:17:37 PM PST 24
Peak memory 193260 kb
Host smart-70bab634-646a-4340-8c85-195db3fc9ab2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268279661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.268279661
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random.199942098
Short name T169
Test name
Test status
Simulation time 657600892496 ps
CPU time 1697.16 seconds
Started Mar 07 01:01:14 PM PST 24
Finished Mar 07 01:29:32 PM PST 24
Peak memory 191596 kb
Host smart-a4fc1944-555a-4b26-a1f7-14a863e169b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199942098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.199942098
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random.3071812754
Short name T266
Test name
Test status
Simulation time 190617823704 ps
CPU time 108.81 seconds
Started Mar 07 01:01:48 PM PST 24
Finished Mar 07 01:03:37 PM PST 24
Peak memory 191532 kb
Host smart-69aebb01-f714-447e-8dfe-9ef59b967b44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071812754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3071812754
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.3408109098
Short name T240
Test name
Test status
Simulation time 616563768446 ps
CPU time 2311.24 seconds
Started Mar 07 01:01:48 PM PST 24
Finished Mar 07 01:40:19 PM PST 24
Peak memory 191588 kb
Host smart-fc6453a8-1d33-4e6b-a54e-b74c9437c140
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408109098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3408109098
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.4034080585
Short name T151
Test name
Test status
Simulation time 136319235007 ps
CPU time 383.82 seconds
Started Mar 07 01:01:48 PM PST 24
Finished Mar 07 01:08:12 PM PST 24
Peak memory 191644 kb
Host smart-bd2b751a-996c-4298-a231-b40cdcfd3014
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034080585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.4034080585
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.3543152879
Short name T290
Test name
Test status
Simulation time 114653147477 ps
CPU time 322.57 seconds
Started Mar 07 01:01:05 PM PST 24
Finished Mar 07 01:06:28 PM PST 24
Peak memory 191596 kb
Host smart-3215e0f5-136e-457a-8294-9dcb563fb4e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543152879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3543152879
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.773934629
Short name T189
Test name
Test status
Simulation time 624004360660 ps
CPU time 439.83 seconds
Started Mar 07 01:01:58 PM PST 24
Finished Mar 07 01:09:19 PM PST 24
Peak memory 191640 kb
Host smart-9af9024a-170a-4c2e-b4dc-9b78c8f7de61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773934629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.773934629
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.1304171452
Short name T128
Test name
Test status
Simulation time 402910324837 ps
CPU time 580.1 seconds
Started Mar 07 01:02:00 PM PST 24
Finished Mar 07 01:11:40 PM PST 24
Peak memory 191516 kb
Host smart-cdfdc87e-e792-43cc-b8d3-34048d2d1c75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304171452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1304171452
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.1186257455
Short name T225
Test name
Test status
Simulation time 95062694869 ps
CPU time 166.89 seconds
Started Mar 07 01:01:58 PM PST 24
Finished Mar 07 01:04:46 PM PST 24
Peak memory 191644 kb
Host smart-314e2fdf-6b52-489d-a4af-036941535271
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186257455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.1186257455
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3016176774
Short name T319
Test name
Test status
Simulation time 166702361677 ps
CPU time 671.62 seconds
Started Mar 07 01:02:04 PM PST 24
Finished Mar 07 01:13:15 PM PST 24
Peak memory 191592 kb
Host smart-5ab6cdbf-f5f9-4df4-b71f-903f757af97d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016176774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3016176774
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random.389985847
Short name T164
Test name
Test status
Simulation time 185933723090 ps
CPU time 618.73 seconds
Started Mar 07 01:01:35 PM PST 24
Finished Mar 07 01:11:54 PM PST 24
Peak memory 192992 kb
Host smart-154a1736-1933-4939-993d-75c9dd93f2a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389985847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.389985847
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3603716024
Short name T143
Test name
Test status
Simulation time 992020389022 ps
CPU time 753.59 seconds
Started Mar 07 01:01:43 PM PST 24
Finished Mar 07 01:14:17 PM PST 24
Peak memory 183408 kb
Host smart-720943cd-4859-4af3-9bd7-239c22e285b6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603716024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3603716024
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_random.2524948529
Short name T339
Test name
Test status
Simulation time 144414698026 ps
CPU time 357.09 seconds
Started Mar 07 01:01:45 PM PST 24
Finished Mar 07 01:07:42 PM PST 24
Peak memory 191572 kb
Host smart-755e2660-dc98-4347-8012-0ef150e8990e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524948529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2524948529
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.535430479
Short name T245
Test name
Test status
Simulation time 216696129246 ps
CPU time 602.79 seconds
Started Mar 07 01:01:58 PM PST 24
Finished Mar 07 01:12:01 PM PST 24
Peak memory 195864 kb
Host smart-c0aa93ae-55b7-4737-b298-7178cb948dfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535430479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
535430479
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/56.rv_timer_random.2396121698
Short name T132
Test name
Test status
Simulation time 328529214728 ps
CPU time 138.46 seconds
Started Mar 07 01:01:59 PM PST 24
Finished Mar 07 01:04:18 PM PST 24
Peak memory 191584 kb
Host smart-24d5b03e-6191-4e1a-aacb-8cc1f132e3fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396121698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2396121698
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1657727998
Short name T154
Test name
Test status
Simulation time 318949171071 ps
CPU time 125.53 seconds
Started Mar 07 01:01:53 PM PST 24
Finished Mar 07 01:03:59 PM PST 24
Peak memory 191476 kb
Host smart-4704a50d-c65c-4258-857a-f170b5a23889
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657727998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1657727998
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.29959225
Short name T56
Test name
Test status
Simulation time 407630622 ps
CPU time 1.34 seconds
Started Mar 07 12:56:33 PM PST 24
Finished Mar 07 12:56:35 PM PST 24
Peak memory 195256 kb
Host smart-dc63dbc7-c475-4474-ac00-ddda48b902f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29959225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_int
g_err.29959225
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/107.rv_timer_random.3296019748
Short name T300
Test name
Test status
Simulation time 501944139119 ps
CPU time 528.4 seconds
Started Mar 07 01:01:46 PM PST 24
Finished Mar 07 01:10:35 PM PST 24
Peak memory 191584 kb
Host smart-8ec29519-2863-472f-b0cd-88dd06fcea42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296019748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3296019748
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.3984426339
Short name T45
Test name
Test status
Simulation time 166964016933 ps
CPU time 551.63 seconds
Started Mar 07 01:02:07 PM PST 24
Finished Mar 07 01:11:19 PM PST 24
Peak memory 191596 kb
Host smart-88c8c948-0f17-4e2a-a120-c6dd1a00d636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984426339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3984426339
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3522423747
Short name T284
Test name
Test status
Simulation time 2052453883740 ps
CPU time 1112.48 seconds
Started Mar 07 01:02:08 PM PST 24
Finished Mar 07 01:20:40 PM PST 24
Peak memory 191564 kb
Host smart-54ec6c9a-0639-43ef-b9a8-0fe62367ac17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522423747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3522423747
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1466521459
Short name T430
Test name
Test status
Simulation time 312613565176 ps
CPU time 476.57 seconds
Started Mar 07 01:01:40 PM PST 24
Finished Mar 07 01:09:36 PM PST 24
Peak memory 183332 kb
Host smart-f5ee3845-af6f-42b0-be86-b2947866a2e4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466521459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1466521459
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3089020394
Short name T5
Test name
Test status
Simulation time 1034624688939 ps
CPU time 2239.12 seconds
Started Mar 07 01:01:20 PM PST 24
Finished Mar 07 01:38:40 PM PST 24
Peak memory 191644 kb
Host smart-6d6163a8-32c6-44d9-b0aa-e23098df253f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089020394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3089020394
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/164.rv_timer_random.2836946548
Short name T176
Test name
Test status
Simulation time 783022373880 ps
CPU time 581.76 seconds
Started Mar 07 01:01:59 PM PST 24
Finished Mar 07 01:11:42 PM PST 24
Peak memory 191596 kb
Host smart-4eb7b898-25ef-4f61-bdf7-7e3f00f34d30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836946548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2836946548
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.3338933632
Short name T318
Test name
Test status
Simulation time 119980402108 ps
CPU time 367.32 seconds
Started Mar 07 01:01:57 PM PST 24
Finished Mar 07 01:08:04 PM PST 24
Peak memory 191636 kb
Host smart-e16cf43d-0692-4e76-a0d9-c4fa90f563a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338933632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3338933632
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1183968038
Short name T211
Test name
Test status
Simulation time 582933761247 ps
CPU time 1865.04 seconds
Started Mar 07 01:01:40 PM PST 24
Finished Mar 07 01:32:45 PM PST 24
Peak memory 195272 kb
Host smart-5c00cbf4-5234-4963-9e20-75d759840cd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183968038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1183968038
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.409966973
Short name T208
Test name
Test status
Simulation time 1559131795607 ps
CPU time 905.21 seconds
Started Mar 07 01:01:49 PM PST 24
Finished Mar 07 01:16:55 PM PST 24
Peak memory 183376 kb
Host smart-06d7ee91-d704-420c-87a1-a36ab0f9a7b8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409966973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.rv_timer_cfg_update_on_fly.409966973
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2675036937
Short name T301
Test name
Test status
Simulation time 240965903436 ps
CPU time 435.99 seconds
Started Mar 07 01:01:51 PM PST 24
Finished Mar 07 01:09:07 PM PST 24
Peak memory 183440 kb
Host smart-2f123494-ee03-42cd-8f71-3959111cd692
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675036937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2675036937
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1473129263
Short name T202
Test name
Test status
Simulation time 688479859914 ps
CPU time 356.82 seconds
Started Mar 07 01:01:26 PM PST 24
Finished Mar 07 01:07:24 PM PST 24
Peak memory 183372 kb
Host smart-67c39bf5-c689-437d-b926-502c8c5ae239
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473129263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1473129263
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/58.rv_timer_random.3325647662
Short name T120
Test name
Test status
Simulation time 375229420248 ps
CPU time 552.98 seconds
Started Mar 07 01:01:51 PM PST 24
Finished Mar 07 01:11:05 PM PST 24
Peak memory 191592 kb
Host smart-b98e0ca0-098a-496a-9171-6d49b1426ddd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325647662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3325647662
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.2786969533
Short name T171
Test name
Test status
Simulation time 287978511606 ps
CPU time 229.34 seconds
Started Mar 07 01:01:53 PM PST 24
Finished Mar 07 01:05:43 PM PST 24
Peak memory 191644 kb
Host smart-393b4d0c-cfe7-4dfb-ae38-0a7341f7e306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786969533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2786969533
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1766314203
Short name T272
Test name
Test status
Simulation time 281036812330 ps
CPU time 368.63 seconds
Started Mar 07 01:02:01 PM PST 24
Finished Mar 07 01:08:09 PM PST 24
Peak memory 191564 kb
Host smart-d20e6150-8941-44e5-9f6c-f3aa26045d7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766314203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1766314203
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3249416008
Short name T255
Test name
Test status
Simulation time 96317677658 ps
CPU time 162.19 seconds
Started Mar 07 01:00:56 PM PST 24
Finished Mar 07 01:03:39 PM PST 24
Peak memory 191648 kb
Host smart-90398e98-1aef-4c31-acc7-39283f57a24d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249416008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3249416008
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_random.1393779607
Short name T2
Test name
Test status
Simulation time 72307333299 ps
CPU time 134.69 seconds
Started Mar 07 01:01:11 PM PST 24
Finished Mar 07 01:03:26 PM PST 24
Peak memory 191488 kb
Host smart-557e04fe-820e-49f0-9246-783ed9db8de5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393779607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1393779607
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.4127826098
Short name T134
Test name
Test status
Simulation time 3079965514812 ps
CPU time 650.42 seconds
Started Mar 07 01:01:21 PM PST 24
Finished Mar 07 01:12:13 PM PST 24
Peak memory 191564 kb
Host smart-35923a3b-db86-43ae-adcb-eee2d3174007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127826098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.4127826098
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2610028566
Short name T275
Test name
Test status
Simulation time 177136912064 ps
CPU time 344.4 seconds
Started Mar 07 01:01:11 PM PST 24
Finished Mar 07 01:06:56 PM PST 24
Peak memory 183368 kb
Host smart-2e34dd10-5352-404f-9b02-b6f8d31d16fc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610028566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2610028566
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/111.rv_timer_random.356693402
Short name T200
Test name
Test status
Simulation time 287318854076 ps
CPU time 344.54 seconds
Started Mar 07 01:01:50 PM PST 24
Finished Mar 07 01:07:35 PM PST 24
Peak memory 191544 kb
Host smart-496ac3ea-9d53-4aac-9eaf-bafbda3404ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356693402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.356693402
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.2107947505
Short name T48
Test name
Test status
Simulation time 495987160094 ps
CPU time 290.01 seconds
Started Mar 07 01:01:56 PM PST 24
Finished Mar 07 01:06:46 PM PST 24
Peak memory 191540 kb
Host smart-297978d0-c6cb-4298-82a3-ec666e745800
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107947505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2107947505
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2226742828
Short name T121
Test name
Test status
Simulation time 658148671484 ps
CPU time 560.26 seconds
Started Mar 07 01:01:26 PM PST 24
Finished Mar 07 01:10:46 PM PST 24
Peak memory 191580 kb
Host smart-5ffc8edb-09a3-44d0-8e4b-2989b539851e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226742828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2226742828
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.4028946452
Short name T455
Test name
Test status
Simulation time 69257289612 ps
CPU time 86.19 seconds
Started Mar 07 01:02:09 PM PST 24
Finished Mar 07 01:03:35 PM PST 24
Peak memory 183452 kb
Host smart-93dafd7a-7942-47e8-9833-abdc1fb8c09e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028946452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.4028946452
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.2815377196
Short name T163
Test name
Test status
Simulation time 703941981122 ps
CPU time 342.97 seconds
Started Mar 07 01:02:05 PM PST 24
Finished Mar 07 01:07:48 PM PST 24
Peak memory 194972 kb
Host smart-711c77e9-d2dd-41e6-b5ca-4f22bf794176
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815377196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2815377196
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3061233708
Short name T65
Test name
Test status
Simulation time 118326756046 ps
CPU time 59.53 seconds
Started Mar 07 01:01:50 PM PST 24
Finished Mar 07 01:02:50 PM PST 24
Peak memory 183384 kb
Host smart-77fa7406-914e-4e85-b14d-f431476c191a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061233708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3061233708
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2599616812
Short name T210
Test name
Test status
Simulation time 736363149902 ps
CPU time 395.35 seconds
Started Mar 07 01:01:24 PM PST 24
Finished Mar 07 01:08:00 PM PST 24
Peak memory 183368 kb
Host smart-3a843655-91dc-4516-9ca2-c6a186c9617d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599616812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2599616812
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/139.rv_timer_random.363452420
Short name T172
Test name
Test status
Simulation time 320706547027 ps
CPU time 204 seconds
Started Mar 07 01:02:04 PM PST 24
Finished Mar 07 01:05:28 PM PST 24
Peak memory 191604 kb
Host smart-5b5be826-ad5c-4666-951a-00202acf33e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363452420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.363452420
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3401214537
Short name T336
Test name
Test status
Simulation time 889521522220 ps
CPU time 447.82 seconds
Started Mar 07 01:01:16 PM PST 24
Finished Mar 07 01:08:44 PM PST 24
Peak memory 183376 kb
Host smart-ec96974f-592b-455b-b74a-51583abbbb2f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401214537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3401214537
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.3780589919
Short name T321
Test name
Test status
Simulation time 411182802877 ps
CPU time 836.64 seconds
Started Mar 07 01:01:20 PM PST 24
Finished Mar 07 01:15:18 PM PST 24
Peak memory 191564 kb
Host smart-1527c003-bb64-49d6-9a01-2e2c3300fb37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780589919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.3780589919
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/146.rv_timer_random.1745958947
Short name T297
Test name
Test status
Simulation time 575495083788 ps
CPU time 473.57 seconds
Started Mar 07 01:02:01 PM PST 24
Finished Mar 07 01:09:55 PM PST 24
Peak memory 191692 kb
Host smart-ecf0c4b0-83f4-4739-939d-d9bab8ecdfa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745958947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1745958947
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.2265940720
Short name T185
Test name
Test status
Simulation time 223098438645 ps
CPU time 671.27 seconds
Started Mar 07 01:02:11 PM PST 24
Finished Mar 07 01:13:23 PM PST 24
Peak memory 192972 kb
Host smart-5c2412e8-0c86-4d1a-b4e5-344f344b4b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265940720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2265940720
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.2471884188
Short name T273
Test name
Test status
Simulation time 308457027432 ps
CPU time 649.66 seconds
Started Mar 07 01:02:04 PM PST 24
Finished Mar 07 01:12:54 PM PST 24
Peak memory 194092 kb
Host smart-c80c8ba8-ab76-4e79-bf24-5785de5e6c4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471884188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2471884188
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.341772198
Short name T191
Test name
Test status
Simulation time 188022198616 ps
CPU time 312.47 seconds
Started Mar 07 01:01:07 PM PST 24
Finished Mar 07 01:06:29 PM PST 24
Peak memory 191584 kb
Host smart-423fb1df-3d24-4499-ab22-083e758a43b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341772198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.341772198
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random.2260548852
Short name T123
Test name
Test status
Simulation time 389525811976 ps
CPU time 434.67 seconds
Started Mar 07 01:01:36 PM PST 24
Finished Mar 07 01:08:51 PM PST 24
Peak memory 194692 kb
Host smart-d2b0ee9b-2575-46cb-90ad-861e124ceee3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260548852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2260548852
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.3098594272
Short name T68
Test name
Test status
Simulation time 323702047879 ps
CPU time 479.37 seconds
Started Mar 07 01:01:41 PM PST 24
Finished Mar 07 01:09:41 PM PST 24
Peak memory 191560 kb
Host smart-9e2d1a7d-ec60-4e25-b440-df27092a02d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098594272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.3098594272
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.1551866589
Short name T230
Test name
Test status
Simulation time 123390722658 ps
CPU time 221.21 seconds
Started Mar 07 01:01:04 PM PST 24
Finished Mar 07 01:04:45 PM PST 24
Peak memory 183348 kb
Host smart-42626fea-0203-4acb-8d7c-69cc583ccf0b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551866589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.1551866589
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_random.1329052049
Short name T241
Test name
Test status
Simulation time 104357679374 ps
CPU time 174.78 seconds
Started Mar 07 01:01:52 PM PST 24
Finished Mar 07 01:04:47 PM PST 24
Peak memory 191572 kb
Host smart-42e6bc25-1b13-4c58-a202-21d748b3ad2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329052049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1329052049
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.907983201
Short name T50
Test name
Test status
Simulation time 8122484847 ps
CPU time 14.15 seconds
Started Mar 07 01:01:42 PM PST 24
Finished Mar 07 01:01:56 PM PST 24
Peak memory 191620 kb
Host smart-3f620d1b-703d-46db-a153-f3b20203772e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907983201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.907983201
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.631655825
Short name T303
Test name
Test status
Simulation time 180223361575 ps
CPU time 643.39 seconds
Started Mar 07 01:01:37 PM PST 24
Finished Mar 07 01:12:21 PM PST 24
Peak memory 191588 kb
Host smart-a7ec6fc2-1619-42aa-b381-3bae848ca067
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631655825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.
631655825
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_random.289070744
Short name T209
Test name
Test status
Simulation time 599739721000 ps
CPU time 334.09 seconds
Started Mar 07 01:01:10 PM PST 24
Finished Mar 07 01:06:45 PM PST 24
Peak memory 191628 kb
Host smart-1b6d2a26-5dc0-4263-b192-0409b6d7ff13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289070744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.289070744
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.1656475582
Short name T350
Test name
Test status
Simulation time 88161838417 ps
CPU time 60.96 seconds
Started Mar 07 01:01:44 PM PST 24
Finished Mar 07 01:02:45 PM PST 24
Peak memory 183436 kb
Host smart-782ff0d2-00ca-4805-95ef-7d6c14a32b28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656475582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1656475582
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.4264670572
Short name T86
Test name
Test status
Simulation time 30529005 ps
CPU time 0.81 seconds
Started Mar 07 12:56:14 PM PST 24
Finished Mar 07 12:56:15 PM PST 24
Peak memory 192492 kb
Host smart-8e0ee3e0-84c3-4422-9ba8-e9358036a9f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264670572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.4264670572
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.894442086
Short name T34
Test name
Test status
Simulation time 63210650 ps
CPU time 2.23 seconds
Started Mar 07 12:56:14 PM PST 24
Finished Mar 07 12:56:16 PM PST 24
Peak memory 193404 kb
Host smart-08031f2d-3164-41bd-b07e-7ba8d9677900
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894442086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.894442086
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1116318663
Short name T101
Test name
Test status
Simulation time 29329389 ps
CPU time 0.58 seconds
Started Mar 07 12:56:13 PM PST 24
Finished Mar 07 12:56:14 PM PST 24
Peak memory 182736 kb
Host smart-f2a00a90-d56e-43dc-b722-16f64f1d2e45
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116318663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.1116318663
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2844137088
Short name T459
Test name
Test status
Simulation time 28535865 ps
CPU time 0.67 seconds
Started Mar 07 12:56:15 PM PST 24
Finished Mar 07 12:56:16 PM PST 24
Peak memory 193944 kb
Host smart-c1c78fac-437a-472c-a2fc-3e83e6973785
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844137088 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2844137088
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1257048927
Short name T561
Test name
Test status
Simulation time 43695941 ps
CPU time 0.55 seconds
Started Mar 07 12:56:09 PM PST 24
Finished Mar 07 12:56:10 PM PST 24
Peak memory 182368 kb
Host smart-6a081b78-93a0-4b08-a0d1-eeb882777148
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257048927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1257048927
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3269680769
Short name T575
Test name
Test status
Simulation time 19728152 ps
CPU time 0.55 seconds
Started Mar 07 12:56:20 PM PST 24
Finished Mar 07 12:56:21 PM PST 24
Peak memory 182180 kb
Host smart-6a549efd-eab0-44d5-9061-d9258a0acc40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269680769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3269680769
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3585780853
Short name T540
Test name
Test status
Simulation time 25832729 ps
CPU time 0.6 seconds
Started Mar 07 12:56:10 PM PST 24
Finished Mar 07 12:56:10 PM PST 24
Peak memory 191572 kb
Host smart-4c0dd659-1e8f-4169-bbc8-3927b72422be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585780853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.3585780853
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.290288792
Short name T552
Test name
Test status
Simulation time 130227565 ps
CPU time 1.68 seconds
Started Mar 07 12:56:02 PM PST 24
Finished Mar 07 12:56:04 PM PST 24
Peak memory 197572 kb
Host smart-51472641-f235-48d7-84e3-58c18c2d7964
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290288792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.290288792
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.988577269
Short name T535
Test name
Test status
Simulation time 86360360 ps
CPU time 1.05 seconds
Started Mar 07 12:56:11 PM PST 24
Finished Mar 07 12:56:12 PM PST 24
Peak memory 194872 kb
Host smart-a261b21c-f973-45d1-b47a-fd13c897e9f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988577269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_int
g_err.988577269
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.451447
Short name T501
Test name
Test status
Simulation time 53422316 ps
CPU time 0.74 seconds
Started Mar 07 12:56:18 PM PST 24
Finished Mar 07 12:56:19 PM PST 24
Peak memory 192300 kb
Host smart-2a259972-6805-4ff1-a7d5-d8f1f34b92a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_aliasing.451447
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2126023100
Short name T55
Test name
Test status
Simulation time 597933949 ps
CPU time 1.58 seconds
Started Mar 07 12:56:19 PM PST 24
Finished Mar 07 12:56:21 PM PST 24
Peak memory 192288 kb
Host smart-d0014110-6877-4c50-8779-9ae6a760c97e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126023100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2126023100
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3144965035
Short name T33
Test name
Test status
Simulation time 135011308 ps
CPU time 0.53 seconds
Started Mar 07 12:56:05 PM PST 24
Finished Mar 07 12:56:06 PM PST 24
Peak memory 182736 kb
Host smart-2b89378d-5bab-4fdc-a729-2f314ac36623
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144965035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3144965035
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1388046849
Short name T559
Test name
Test status
Simulation time 142667290 ps
CPU time 0.89 seconds
Started Mar 07 12:56:11 PM PST 24
Finished Mar 07 12:56:12 PM PST 24
Peak memory 196524 kb
Host smart-5d62997a-6291-4813-a9f8-fc37f622ca58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388046849 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.1388046849
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.879936466
Short name T489
Test name
Test status
Simulation time 72787882 ps
CPU time 0.58 seconds
Started Mar 07 12:56:13 PM PST 24
Finished Mar 07 12:56:14 PM PST 24
Peak memory 182724 kb
Host smart-c836fe39-c5b6-48b3-a343-8c9ab75eaa29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879936466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.879936466
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3551865296
Short name T495
Test name
Test status
Simulation time 50716465 ps
CPU time 0.55 seconds
Started Mar 07 12:56:18 PM PST 24
Finished Mar 07 12:56:18 PM PST 24
Peak memory 182448 kb
Host smart-6b10be5d-60eb-4de4-9fb3-8dc850bb8395
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551865296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3551865296
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1401108679
Short name T78
Test name
Test status
Simulation time 58838982 ps
CPU time 0.79 seconds
Started Mar 07 12:56:02 PM PST 24
Finished Mar 07 12:56:03 PM PST 24
Peak memory 193444 kb
Host smart-9e2f815f-6e9c-443e-b8bd-593f0feb1a97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401108679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.1401108679
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2827913238
Short name T520
Test name
Test status
Simulation time 69343698 ps
CPU time 1.8 seconds
Started Mar 07 12:56:05 PM PST 24
Finished Mar 07 12:56:07 PM PST 24
Peak memory 197608 kb
Host smart-15081c7e-df91-416a-8337-3530fc21b6f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827913238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2827913238
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.896639265
Short name T57
Test name
Test status
Simulation time 56655530 ps
CPU time 0.84 seconds
Started Mar 07 12:56:03 PM PST 24
Finished Mar 07 12:56:04 PM PST 24
Peak memory 183164 kb
Host smart-05c89e2c-8509-4657-a68a-ee5880a9c03c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896639265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.896639265
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2005463468
Short name T513
Test name
Test status
Simulation time 74518852 ps
CPU time 0.88 seconds
Started Mar 07 12:56:29 PM PST 24
Finished Mar 07 12:56:30 PM PST 24
Peak memory 196392 kb
Host smart-42ee3e17-adc0-42dc-b726-5f3a6fc788dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005463468 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2005463468
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2540546157
Short name T516
Test name
Test status
Simulation time 33718543 ps
CPU time 0.51 seconds
Started Mar 07 12:56:28 PM PST 24
Finished Mar 07 12:56:29 PM PST 24
Peak memory 182248 kb
Host smart-6b098ae5-56bc-432a-9bce-c66f51d30da0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540546157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2540546157
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1778817412
Short name T543
Test name
Test status
Simulation time 26613751 ps
CPU time 0.58 seconds
Started Mar 07 12:56:23 PM PST 24
Finished Mar 07 12:56:24 PM PST 24
Peak memory 182628 kb
Host smart-33f481c0-0996-488e-aa84-efc29b73b8e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778817412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1778817412
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.217030232
Short name T97
Test name
Test status
Simulation time 15753765 ps
CPU time 0.61 seconds
Started Mar 07 12:56:24 PM PST 24
Finished Mar 07 12:56:25 PM PST 24
Peak memory 192000 kb
Host smart-e0d30d6c-efef-4790-8b0a-b2e02ea1471f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217030232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_ti
mer_same_csr_outstanding.217030232
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1240580754
Short name T549
Test name
Test status
Simulation time 99959944 ps
CPU time 2.18 seconds
Started Mar 07 12:56:17 PM PST 24
Finished Mar 07 12:56:19 PM PST 24
Peak memory 197420 kb
Host smart-0d194b4a-edb7-4fae-8da5-1d54ab1376ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240580754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1240580754
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2933021418
Short name T505
Test name
Test status
Simulation time 185790125 ps
CPU time 0.82 seconds
Started Mar 07 12:56:22 PM PST 24
Finished Mar 07 12:56:23 PM PST 24
Peak memory 182860 kb
Host smart-9713cf05-5558-473e-8d69-e0bcfea20a2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933021418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.2933021418
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1724017909
Short name T531
Test name
Test status
Simulation time 39884262 ps
CPU time 0.88 seconds
Started Mar 07 12:56:26 PM PST 24
Finished Mar 07 12:56:27 PM PST 24
Peak memory 195996 kb
Host smart-414b0422-999c-4cae-b484-96243fe5ae14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724017909 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1724017909
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2504262255
Short name T83
Test name
Test status
Simulation time 17481953 ps
CPU time 0.57 seconds
Started Mar 07 12:56:27 PM PST 24
Finished Mar 07 12:56:28 PM PST 24
Peak memory 182724 kb
Host smart-449de4b6-6559-41da-98b8-76679c1db921
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504262255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2504262255
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2671209263
Short name T533
Test name
Test status
Simulation time 13986563 ps
CPU time 0.53 seconds
Started Mar 07 12:56:25 PM PST 24
Finished Mar 07 12:56:26 PM PST 24
Peak memory 181992 kb
Host smart-aa837f82-ea6a-43ab-af5e-174c8dcc82e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671209263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2671209263
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3901793089
Short name T573
Test name
Test status
Simulation time 43716146 ps
CPU time 0.69 seconds
Started Mar 07 12:56:32 PM PST 24
Finished Mar 07 12:56:33 PM PST 24
Peak memory 192068 kb
Host smart-4ffd4beb-1479-4d44-9108-fdae6619d407
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901793089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3901793089
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.320287463
Short name T548
Test name
Test status
Simulation time 44964636 ps
CPU time 1.26 seconds
Started Mar 07 12:56:24 PM PST 24
Finished Mar 07 12:56:25 PM PST 24
Peak memory 197712 kb
Host smart-f1bb2f23-6e1a-4b09-bc5f-91a0b942ed91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320287463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.320287463
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1566268538
Short name T104
Test name
Test status
Simulation time 56090875 ps
CPU time 0.85 seconds
Started Mar 07 12:56:25 PM PST 24
Finished Mar 07 12:56:26 PM PST 24
Peak memory 193420 kb
Host smart-3690dff9-267b-4cfe-adde-5ac10e9346e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566268538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.1566268538
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.732571398
Short name T522
Test name
Test status
Simulation time 35350935 ps
CPU time 1.04 seconds
Started Mar 07 12:56:22 PM PST 24
Finished Mar 07 12:56:23 PM PST 24
Peak memory 197452 kb
Host smart-21898a3a-1634-457f-a902-646d4a5d7788
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732571398 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.732571398
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1134033539
Short name T87
Test name
Test status
Simulation time 18613675 ps
CPU time 0.57 seconds
Started Mar 07 12:56:32 PM PST 24
Finished Mar 07 12:56:33 PM PST 24
Peak memory 182716 kb
Host smart-40c355c8-1b60-445e-ad7e-d21753a17d77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134033539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1134033539
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3543054822
Short name T565
Test name
Test status
Simulation time 28958275 ps
CPU time 0.58 seconds
Started Mar 07 12:56:31 PM PST 24
Finished Mar 07 12:56:32 PM PST 24
Peak memory 182572 kb
Host smart-e29fff15-10b5-460b-9875-bbfd7dcbed82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543054822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3543054822
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3858587815
Short name T564
Test name
Test status
Simulation time 121926012 ps
CPU time 0.69 seconds
Started Mar 07 12:56:33 PM PST 24
Finished Mar 07 12:56:33 PM PST 24
Peak memory 193272 kb
Host smart-f0109398-e2c2-4c6a-bd44-e7d6ef43bb53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858587815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3858587815
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1274892440
Short name T534
Test name
Test status
Simulation time 156307595 ps
CPU time 2.98 seconds
Started Mar 07 12:56:29 PM PST 24
Finished Mar 07 12:56:32 PM PST 24
Peak memory 197588 kb
Host smart-0a3f2931-e8b7-4337-83f7-a017c7eccb6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274892440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1274892440
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3460659803
Short name T31
Test name
Test status
Simulation time 275797582 ps
CPU time 1.14 seconds
Started Mar 07 12:56:30 PM PST 24
Finished Mar 07 12:56:32 PM PST 24
Peak memory 195176 kb
Host smart-9c441724-4c9a-42cf-8caf-14c76215e64c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460659803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3460659803
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3897271468
Short name T519
Test name
Test status
Simulation time 17006016 ps
CPU time 0.68 seconds
Started Mar 07 12:56:28 PM PST 24
Finished Mar 07 12:56:29 PM PST 24
Peak memory 193820 kb
Host smart-865121f0-86b9-45f7-b874-ba3d0976ffb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897271468 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3897271468
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3971430235
Short name T563
Test name
Test status
Simulation time 41977631 ps
CPU time 0.6 seconds
Started Mar 07 12:56:22 PM PST 24
Finished Mar 07 12:56:23 PM PST 24
Peak memory 182804 kb
Host smart-90548e14-275f-4d71-88b5-1f2407aeaf3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971430235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3971430235
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3277883749
Short name T538
Test name
Test status
Simulation time 38918066 ps
CPU time 0.53 seconds
Started Mar 07 12:56:26 PM PST 24
Finished Mar 07 12:56:26 PM PST 24
Peak memory 182100 kb
Host smart-a0ecf41e-9c8f-46c6-807c-06dccaea0066
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277883749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3277883749
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.109730527
Short name T94
Test name
Test status
Simulation time 19937606 ps
CPU time 0.63 seconds
Started Mar 07 12:56:23 PM PST 24
Finished Mar 07 12:56:24 PM PST 24
Peak memory 191972 kb
Host smart-c07a1144-7ddf-49e1-86bc-400f6d5f71f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109730527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti
mer_same_csr_outstanding.109730527
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.109563552
Short name T517
Test name
Test status
Simulation time 230585786 ps
CPU time 1.51 seconds
Started Mar 07 12:56:30 PM PST 24
Finished Mar 07 12:56:32 PM PST 24
Peak memory 197544 kb
Host smart-090d58b2-fe6e-430f-8df2-6801809d0aab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109563552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.109563552
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3554131679
Short name T574
Test name
Test status
Simulation time 320819514 ps
CPU time 1.07 seconds
Started Mar 07 12:56:38 PM PST 24
Finished Mar 07 12:56:40 PM PST 24
Peak memory 194936 kb
Host smart-33b5e764-0d69-48a9-aabd-0b1481628cfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554131679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3554131679
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.786952282
Short name T506
Test name
Test status
Simulation time 25988016 ps
CPU time 0.79 seconds
Started Mar 07 12:56:29 PM PST 24
Finished Mar 07 12:56:29 PM PST 24
Peak memory 195352 kb
Host smart-ec153552-3ea7-4370-847b-d0d7b6154803
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786952282 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.786952282
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3255666092
Short name T91
Test name
Test status
Simulation time 110547786 ps
CPU time 0.61 seconds
Started Mar 07 12:56:30 PM PST 24
Finished Mar 07 12:56:31 PM PST 24
Peak memory 182716 kb
Host smart-f182e366-0ebe-4015-b4e1-5678a6ebe414
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255666092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3255666092
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.16474010
Short name T474
Test name
Test status
Simulation time 12960572 ps
CPU time 0.6 seconds
Started Mar 07 12:56:26 PM PST 24
Finished Mar 07 12:56:27 PM PST 24
Peak memory 182544 kb
Host smart-c582de23-7e25-4ce7-9d75-9fe9edbb9623
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16474010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.16474010
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1039600425
Short name T566
Test name
Test status
Simulation time 19210553 ps
CPU time 0.67 seconds
Started Mar 07 12:56:28 PM PST 24
Finished Mar 07 12:56:28 PM PST 24
Peak memory 192088 kb
Host smart-9880d9f7-8295-4d1b-939e-f604ba27950e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039600425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.1039600425
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.794613934
Short name T542
Test name
Test status
Simulation time 135148342 ps
CPU time 0.98 seconds
Started Mar 07 12:56:30 PM PST 24
Finished Mar 07 12:56:32 PM PST 24
Peak memory 196444 kb
Host smart-497a4ed3-874a-48c1-b6f4-c8b0a8cce74e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794613934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.794613934
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1592794129
Short name T579
Test name
Test status
Simulation time 180175984 ps
CPU time 1.31 seconds
Started Mar 07 12:56:48 PM PST 24
Finished Mar 07 12:56:50 PM PST 24
Peak memory 195196 kb
Host smart-6bd0972a-5514-4fab-bfbc-8e1df3bafed4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592794129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1592794129
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.270616475
Short name T537
Test name
Test status
Simulation time 64901752 ps
CPU time 0.92 seconds
Started Mar 07 12:56:24 PM PST 24
Finished Mar 07 12:56:25 PM PST 24
Peak memory 197140 kb
Host smart-1be51633-2340-44cf-b35a-4969bd0d3663
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270616475 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.270616475
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3923710832
Short name T487
Test name
Test status
Simulation time 128335232 ps
CPU time 0.54 seconds
Started Mar 07 12:56:29 PM PST 24
Finished Mar 07 12:56:30 PM PST 24
Peak memory 182716 kb
Host smart-24d24dcf-dd91-4358-8757-e9a987b8495f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923710832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3923710832
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2921839475
Short name T481
Test name
Test status
Simulation time 18212555 ps
CPU time 0.63 seconds
Started Mar 07 12:56:29 PM PST 24
Finished Mar 07 12:56:30 PM PST 24
Peak memory 182532 kb
Host smart-0b8d8074-3e3e-4508-861d-bb7f058d0e2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921839475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2921839475
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3918925910
Short name T96
Test name
Test status
Simulation time 354124081 ps
CPU time 0.78 seconds
Started Mar 07 12:56:32 PM PST 24
Finished Mar 07 12:56:33 PM PST 24
Peak memory 193156 kb
Host smart-a27f91c2-dce7-443d-8976-fd0ba82b7096
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918925910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3918925910
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.701363842
Short name T578
Test name
Test status
Simulation time 241609962 ps
CPU time 2.1 seconds
Started Mar 07 12:56:24 PM PST 24
Finished Mar 07 12:56:26 PM PST 24
Peak memory 197588 kb
Host smart-ea481589-95cc-4168-84e3-272b61e602bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701363842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.701363842
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3847292031
Short name T554
Test name
Test status
Simulation time 111023963 ps
CPU time 0.9 seconds
Started Mar 07 12:56:56 PM PST 24
Finished Mar 07 12:56:57 PM PST 24
Peak memory 193364 kb
Host smart-05c0384c-89b1-4d58-a713-c5045020c4ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847292031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3847292031
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.346050588
Short name T472
Test name
Test status
Simulation time 64841912 ps
CPU time 0.92 seconds
Started Mar 07 12:56:28 PM PST 24
Finished Mar 07 12:56:29 PM PST 24
Peak memory 197432 kb
Host smart-c10f73c6-8168-41ec-993e-8aff9763ceb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346050588 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.346050588
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1783980579
Short name T525
Test name
Test status
Simulation time 17050731 ps
CPU time 0.62 seconds
Started Mar 07 12:56:27 PM PST 24
Finished Mar 07 12:56:28 PM PST 24
Peak memory 182740 kb
Host smart-85780195-1c2a-47e4-b269-e73e2390f5bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783980579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1783980579
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1785583606
Short name T550
Test name
Test status
Simulation time 44257017 ps
CPU time 0.55 seconds
Started Mar 07 12:56:33 PM PST 24
Finished Mar 07 12:56:34 PM PST 24
Peak memory 182528 kb
Host smart-6cd917e2-96e2-4f53-9003-52dcc1b45ebc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785583606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1785583606
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3790556176
Short name T523
Test name
Test status
Simulation time 73422414 ps
CPU time 0.63 seconds
Started Mar 07 12:56:26 PM PST 24
Finished Mar 07 12:56:26 PM PST 24
Peak memory 191952 kb
Host smart-58d8f7dd-92ff-4265-8219-4f528a78ce78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790556176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.3790556176
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1037512176
Short name T483
Test name
Test status
Simulation time 26742794 ps
CPU time 1.31 seconds
Started Mar 07 12:56:30 PM PST 24
Finished Mar 07 12:56:41 PM PST 24
Peak memory 197660 kb
Host smart-af8abdf8-0b10-49fa-b867-766332ee90a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037512176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1037512176
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2323222167
Short name T103
Test name
Test status
Simulation time 143637415 ps
CPU time 0.86 seconds
Started Mar 07 12:56:26 PM PST 24
Finished Mar 07 12:56:27 PM PST 24
Peak memory 183148 kb
Host smart-9b9b62c0-a58e-4527-8f02-5807655a17ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323222167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2323222167
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3434434105
Short name T477
Test name
Test status
Simulation time 69651183 ps
CPU time 0.88 seconds
Started Mar 07 12:56:47 PM PST 24
Finished Mar 07 12:56:49 PM PST 24
Peak memory 197348 kb
Host smart-1e411ae2-58f9-4765-a7f0-9493376a8ad2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434434105 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3434434105
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2962675041
Short name T488
Test name
Test status
Simulation time 16598212 ps
CPU time 0.6 seconds
Started Mar 07 12:56:24 PM PST 24
Finished Mar 07 12:56:25 PM PST 24
Peak memory 182704 kb
Host smart-53f7c440-727a-44f5-a6aa-fad37ecfbbc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962675041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2962675041
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2159807196
Short name T478
Test name
Test status
Simulation time 12908330 ps
CPU time 0.53 seconds
Started Mar 07 12:56:27 PM PST 24
Finished Mar 07 12:56:28 PM PST 24
Peak memory 182524 kb
Host smart-4e886191-ab72-446e-8851-edd064890609
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159807196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.2159807196
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3455529838
Short name T95
Test name
Test status
Simulation time 51368273 ps
CPU time 0.59 seconds
Started Mar 07 12:56:43 PM PST 24
Finished Mar 07 12:56:44 PM PST 24
Peak memory 192020 kb
Host smart-6dffef32-5482-4186-8e54-3a0843687972
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455529838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3455529838
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3789833466
Short name T499
Test name
Test status
Simulation time 70533629 ps
CPU time 1.62 seconds
Started Mar 07 12:56:25 PM PST 24
Finished Mar 07 12:56:27 PM PST 24
Peak memory 197592 kb
Host smart-3496c48a-ad94-47c7-a852-7e80e19522f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789833466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3789833466
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.4165167021
Short name T536
Test name
Test status
Simulation time 25788806 ps
CPU time 0.75 seconds
Started Mar 07 12:56:42 PM PST 24
Finished Mar 07 12:56:43 PM PST 24
Peak memory 194644 kb
Host smart-cc21fcb4-e489-40e7-a1e3-ac20cf0c6e20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165167021 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.4165167021
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1702619444
Short name T90
Test name
Test status
Simulation time 21643470 ps
CPU time 0.53 seconds
Started Mar 07 12:56:39 PM PST 24
Finished Mar 07 12:56:40 PM PST 24
Peak memory 182256 kb
Host smart-6d3ad542-aa28-45a7-9707-add46d9cd055
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702619444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1702619444
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1041884339
Short name T511
Test name
Test status
Simulation time 41019163 ps
CPU time 0.54 seconds
Started Mar 07 12:56:49 PM PST 24
Finished Mar 07 12:56:50 PM PST 24
Peak memory 182576 kb
Host smart-a7a595b0-ecef-4b5a-80a7-95f551fabc56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041884339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1041884339
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2783186876
Short name T529
Test name
Test status
Simulation time 36011173 ps
CPU time 0.63 seconds
Started Mar 07 12:56:47 PM PST 24
Finished Mar 07 12:56:47 PM PST 24
Peak memory 191180 kb
Host smart-96643d0d-63d9-4133-b979-40c08f48b32e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783186876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.2783186876
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.4037370440
Short name T524
Test name
Test status
Simulation time 54030845 ps
CPU time 1.16 seconds
Started Mar 07 12:56:39 PM PST 24
Finished Mar 07 12:56:41 PM PST 24
Peak memory 197572 kb
Host smart-d96a50e5-cc43-4a46-8eec-6ff038c0572b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037370440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.4037370440
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1801258509
Short name T105
Test name
Test status
Simulation time 187212268 ps
CPU time 1.1 seconds
Started Mar 07 12:56:47 PM PST 24
Finished Mar 07 12:56:48 PM PST 24
Peak memory 183092 kb
Host smart-9a0b368e-2ff7-4ef5-91f8-765e7f2d512a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801258509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1801258509
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3085727210
Short name T467
Test name
Test status
Simulation time 145399347 ps
CPU time 1.37 seconds
Started Mar 07 12:56:46 PM PST 24
Finished Mar 07 12:56:48 PM PST 24
Peak memory 197612 kb
Host smart-21cf3bd7-c5ff-4cf3-87d9-0db9c64e5417
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085727210 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3085727210
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2989283035
Short name T35
Test name
Test status
Simulation time 13510542 ps
CPU time 0.55 seconds
Started Mar 07 12:57:03 PM PST 24
Finished Mar 07 12:57:04 PM PST 24
Peak memory 182332 kb
Host smart-123024a8-4fe0-408c-98b4-d8d727b4e252
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989283035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2989283035
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.546787841
Short name T464
Test name
Test status
Simulation time 11251857 ps
CPU time 0.55 seconds
Started Mar 07 12:56:57 PM PST 24
Finished Mar 07 12:56:58 PM PST 24
Peak memory 181988 kb
Host smart-693fee9c-9597-4bfd-8962-9c8e9c72615e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546787841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.546787841
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2168849930
Short name T92
Test name
Test status
Simulation time 124542690 ps
CPU time 0.79 seconds
Started Mar 07 12:56:53 PM PST 24
Finished Mar 07 12:56:55 PM PST 24
Peak memory 193424 kb
Host smart-4cf058d8-fbb4-4834-a631-6be047469c0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168849930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2168849930
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2953033522
Short name T460
Test name
Test status
Simulation time 430522213 ps
CPU time 2.38 seconds
Started Mar 07 12:56:56 PM PST 24
Finished Mar 07 12:56:59 PM PST 24
Peak memory 197632 kb
Host smart-6cf29ff7-0248-471b-9d9f-1ea82394176f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953033522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2953033522
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1902554902
Short name T32
Test name
Test status
Simulation time 193786792 ps
CPU time 1.13 seconds
Started Mar 07 12:56:40 PM PST 24
Finished Mar 07 12:56:42 PM PST 24
Peak memory 194992 kb
Host smart-43195033-246b-4848-9f1b-60ec850bc624
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902554902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1902554902
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2732843650
Short name T480
Test name
Test status
Simulation time 17000479 ps
CPU time 0.62 seconds
Started Mar 07 12:56:11 PM PST 24
Finished Mar 07 12:56:12 PM PST 24
Peak memory 182644 kb
Host smart-954b4bda-6c2a-4097-b9d3-46eba799447c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732843650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.2732843650
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.179023720
Short name T100
Test name
Test status
Simulation time 40215381 ps
CPU time 1.51 seconds
Started Mar 07 12:56:11 PM PST 24
Finished Mar 07 12:56:12 PM PST 24
Peak memory 191092 kb
Host smart-c49000be-36c2-43e8-8299-41cd8ee7c0e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179023720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_b
ash.179023720
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.476935255
Short name T80
Test name
Test status
Simulation time 16604086 ps
CPU time 0.59 seconds
Started Mar 07 12:56:09 PM PST 24
Finished Mar 07 12:56:10 PM PST 24
Peak memory 182720 kb
Host smart-beffca9a-2587-4953-8d2b-3b4704036d71
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476935255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.476935255
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3890686277
Short name T53
Test name
Test status
Simulation time 227686226 ps
CPU time 0.82 seconds
Started Mar 07 12:56:27 PM PST 24
Finished Mar 07 12:56:28 PM PST 24
Peak memory 196472 kb
Host smart-7b502748-d106-42c8-a588-99f8f7d0d482
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890686277 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3890686277
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1781811127
Short name T89
Test name
Test status
Simulation time 17027114 ps
CPU time 0.58 seconds
Started Mar 07 12:56:05 PM PST 24
Finished Mar 07 12:56:06 PM PST 24
Peak memory 191936 kb
Host smart-0e85884b-a289-46e9-9711-8139816a01a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781811127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1781811127
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1201529877
Short name T518
Test name
Test status
Simulation time 32147310 ps
CPU time 0.64 seconds
Started Mar 07 12:56:11 PM PST 24
Finished Mar 07 12:56:11 PM PST 24
Peak memory 182444 kb
Host smart-0554bbf7-12e7-4fe6-a25a-4fa86957dcfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201529877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1201529877
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.658644312
Short name T551
Test name
Test status
Simulation time 50572503 ps
CPU time 0.63 seconds
Started Mar 07 12:56:11 PM PST 24
Finished Mar 07 12:56:11 PM PST 24
Peak memory 191636 kb
Host smart-3a10d0c7-d277-4924-b77d-fdc87636e271
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658644312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_tim
er_same_csr_outstanding.658644312
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3770330334
Short name T557
Test name
Test status
Simulation time 61590668 ps
CPU time 2.96 seconds
Started Mar 07 12:56:09 PM PST 24
Finished Mar 07 12:56:12 PM PST 24
Peak memory 197688 kb
Host smart-01201bdd-9b55-486a-8d77-4b8490fa9b8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770330334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.3770330334
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.959796315
Short name T514
Test name
Test status
Simulation time 80220258 ps
CPU time 0.84 seconds
Started Mar 07 12:56:18 PM PST 24
Finished Mar 07 12:56:19 PM PST 24
Peak memory 183100 kb
Host smart-655bca22-b754-4fc2-9305-d85f228dd622
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959796315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_int
g_err.959796315
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.887573939
Short name T569
Test name
Test status
Simulation time 46813848 ps
CPU time 0.63 seconds
Started Mar 07 12:56:56 PM PST 24
Finished Mar 07 12:56:57 PM PST 24
Peak memory 182552 kb
Host smart-df349c35-5331-4670-b78a-d4377361ccad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887573939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.887573939
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1014005527
Short name T555
Test name
Test status
Simulation time 13128209 ps
CPU time 0.56 seconds
Started Mar 07 12:56:41 PM PST 24
Finished Mar 07 12:56:42 PM PST 24
Peak memory 181932 kb
Host smart-9a9c62c3-4ce6-4a2d-9d23-e423cd0bd7c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014005527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1014005527
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3809301220
Short name T544
Test name
Test status
Simulation time 29904151 ps
CPU time 0.56 seconds
Started Mar 07 12:56:44 PM PST 24
Finished Mar 07 12:56:44 PM PST 24
Peak memory 182564 kb
Host smart-cd98896b-2e64-4feb-bc6e-1076a48cb07d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809301220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3809301220
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3995528570
Short name T496
Test name
Test status
Simulation time 35398086 ps
CPU time 0.52 seconds
Started Mar 07 12:56:50 PM PST 24
Finished Mar 07 12:56:51 PM PST 24
Peak memory 182192 kb
Host smart-2365df93-4e26-4c5e-9679-1d76d9e2b862
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995528570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3995528570
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.4226946167
Short name T560
Test name
Test status
Simulation time 14277306 ps
CPU time 0.58 seconds
Started Mar 07 12:56:41 PM PST 24
Finished Mar 07 12:56:42 PM PST 24
Peak memory 182652 kb
Host smart-0d61449f-793f-471d-a60d-aa5707a695db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226946167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.4226946167
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2211410234
Short name T492
Test name
Test status
Simulation time 45341362 ps
CPU time 0.55 seconds
Started Mar 07 12:56:40 PM PST 24
Finished Mar 07 12:56:41 PM PST 24
Peak memory 182540 kb
Host smart-d2770118-d618-4c8f-b50f-cf10a62db22e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211410234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2211410234
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3106245670
Short name T497
Test name
Test status
Simulation time 41021125 ps
CPU time 0.57 seconds
Started Mar 07 12:56:37 PM PST 24
Finished Mar 07 12:56:38 PM PST 24
Peak memory 182524 kb
Host smart-998eba2c-e668-4736-94eb-db667863dfac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106245670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.3106245670
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1118381685
Short name T461
Test name
Test status
Simulation time 27123523 ps
CPU time 0.56 seconds
Started Mar 07 12:56:54 PM PST 24
Finished Mar 07 12:56:55 PM PST 24
Peak memory 182468 kb
Host smart-823ccd68-5edb-42ac-81f0-b4b1157ad637
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118381685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1118381685
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1754661398
Short name T462
Test name
Test status
Simulation time 74867340 ps
CPU time 0.54 seconds
Started Mar 07 12:56:51 PM PST 24
Finished Mar 07 12:56:51 PM PST 24
Peak memory 182572 kb
Host smart-ca4592f3-9dcf-4deb-b9f6-64bdd40361c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754661398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1754661398
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2034050208
Short name T468
Test name
Test status
Simulation time 43159272 ps
CPU time 0.52 seconds
Started Mar 07 12:57:01 PM PST 24
Finished Mar 07 12:57:01 PM PST 24
Peak memory 182552 kb
Host smart-1dc14e5e-57cb-49a1-b081-d0b87ca2c621
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034050208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2034050208
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2189978390
Short name T79
Test name
Test status
Simulation time 49772087 ps
CPU time 0.71 seconds
Started Mar 07 12:56:21 PM PST 24
Finished Mar 07 12:56:22 PM PST 24
Peak memory 182644 kb
Host smart-fb772d98-7903-4d4d-8541-167847da4166
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189978390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.2189978390
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.664197770
Short name T88
Test name
Test status
Simulation time 412482961 ps
CPU time 3.66 seconds
Started Mar 07 12:56:10 PM PST 24
Finished Mar 07 12:56:13 PM PST 24
Peak memory 192548 kb
Host smart-22765241-2c64-412b-8257-65e64e8b9316
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664197770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.664197770
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.597932697
Short name T571
Test name
Test status
Simulation time 15165776 ps
CPU time 0.55 seconds
Started Mar 07 12:56:20 PM PST 24
Finished Mar 07 12:56:21 PM PST 24
Peak memory 182756 kb
Host smart-f419f88f-087a-42e3-ba96-463f17a37834
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597932697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_re
set.597932697
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.978249245
Short name T485
Test name
Test status
Simulation time 55600833 ps
CPU time 0.98 seconds
Started Mar 07 12:56:17 PM PST 24
Finished Mar 07 12:56:18 PM PST 24
Peak memory 197444 kb
Host smart-cd744a7c-3e93-41df-894d-b7554c3dc35a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978249245 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.978249245
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3101132291
Short name T476
Test name
Test status
Simulation time 47964681 ps
CPU time 0.59 seconds
Started Mar 07 12:56:24 PM PST 24
Finished Mar 07 12:56:25 PM PST 24
Peak memory 182732 kb
Host smart-706df13c-cac8-43be-b854-bd86270e0051
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101132291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3101132291
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.759793113
Short name T576
Test name
Test status
Simulation time 17929440 ps
CPU time 0.56 seconds
Started Mar 07 12:56:20 PM PST 24
Finished Mar 07 12:56:21 PM PST 24
Peak memory 181932 kb
Host smart-933d02db-dd2e-478e-8783-be65f66d0730
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759793113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.759793113
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2349888676
Short name T98
Test name
Test status
Simulation time 28205916 ps
CPU time 0.72 seconds
Started Mar 07 12:56:24 PM PST 24
Finished Mar 07 12:56:25 PM PST 24
Peak memory 193216 kb
Host smart-cdd40726-d250-42de-8744-370768ab7452
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349888676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.2349888676
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3521336310
Short name T526
Test name
Test status
Simulation time 39459946 ps
CPU time 1.78 seconds
Started Mar 07 12:56:20 PM PST 24
Finished Mar 07 12:56:22 PM PST 24
Peak memory 197548 kb
Host smart-29832e54-ce49-49a3-9b29-d43537ff589f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521336310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3521336310
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2908915201
Short name T527
Test name
Test status
Simulation time 97098384 ps
CPU time 1.33 seconds
Started Mar 07 12:56:17 PM PST 24
Finished Mar 07 12:56:18 PM PST 24
Peak memory 195128 kb
Host smart-130ffc87-4bd4-48b0-afc8-7b206b1c9e5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908915201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2908915201
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3213454511
Short name T473
Test name
Test status
Simulation time 15286480 ps
CPU time 0.51 seconds
Started Mar 07 12:56:59 PM PST 24
Finished Mar 07 12:57:00 PM PST 24
Peak memory 182560 kb
Host smart-57d4b073-ef09-4b5d-aa12-ea58a1017db6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213454511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3213454511
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1210126267
Short name T556
Test name
Test status
Simulation time 18694253 ps
CPU time 0.53 seconds
Started Mar 07 12:56:50 PM PST 24
Finished Mar 07 12:56:50 PM PST 24
Peak memory 182200 kb
Host smart-13d14d19-aac3-4e17-9ec8-92b4863b88f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210126267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1210126267
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3403826681
Short name T494
Test name
Test status
Simulation time 41926839 ps
CPU time 0.55 seconds
Started Mar 07 12:56:55 PM PST 24
Finished Mar 07 12:56:57 PM PST 24
Peak memory 182524 kb
Host smart-7b85e5b0-a758-43bd-99e3-62a19f5bb923
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403826681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.3403826681
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.211359689
Short name T539
Test name
Test status
Simulation time 22539427 ps
CPU time 0.58 seconds
Started Mar 07 12:56:43 PM PST 24
Finished Mar 07 12:56:44 PM PST 24
Peak memory 182588 kb
Host smart-e035b186-81cb-4d85-a8b8-cbdefb066e6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211359689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.211359689
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.885614275
Short name T545
Test name
Test status
Simulation time 11490484 ps
CPU time 0.56 seconds
Started Mar 07 12:56:42 PM PST 24
Finished Mar 07 12:56:43 PM PST 24
Peak memory 182564 kb
Host smart-75fc739e-8660-430d-8451-6f36ddd825a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885614275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.885614275
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3569768755
Short name T465
Test name
Test status
Simulation time 15024103 ps
CPU time 0.54 seconds
Started Mar 07 12:57:05 PM PST 24
Finished Mar 07 12:57:07 PM PST 24
Peak memory 181968 kb
Host smart-1996d99d-4f45-4f86-ab28-ce6f9d91dd50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569768755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3569768755
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1431847310
Short name T470
Test name
Test status
Simulation time 101868770 ps
CPU time 0.57 seconds
Started Mar 07 12:56:56 PM PST 24
Finished Mar 07 12:57:01 PM PST 24
Peak memory 182580 kb
Host smart-c0db82cd-785e-4732-900d-f68142c289a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431847310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1431847310
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3276691085
Short name T471
Test name
Test status
Simulation time 16329314 ps
CPU time 0.56 seconds
Started Mar 07 12:56:48 PM PST 24
Finished Mar 07 12:56:49 PM PST 24
Peak memory 182536 kb
Host smart-97a4363f-ea3a-4830-b2df-49b1f1c3d0fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276691085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3276691085
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1677643054
Short name T469
Test name
Test status
Simulation time 15229018 ps
CPU time 0.56 seconds
Started Mar 07 12:56:56 PM PST 24
Finished Mar 07 12:56:57 PM PST 24
Peak memory 182536 kb
Host smart-9001660e-ad1f-4648-9290-4a0e228be2f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677643054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1677643054
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3029684669
Short name T479
Test name
Test status
Simulation time 13809938 ps
CPU time 0.51 seconds
Started Mar 07 12:56:43 PM PST 24
Finished Mar 07 12:56:44 PM PST 24
Peak memory 181976 kb
Host smart-938004d1-6391-42df-b72d-d34724cbb0c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029684669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3029684669
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1565327045
Short name T82
Test name
Test status
Simulation time 58738127 ps
CPU time 0.86 seconds
Started Mar 07 12:56:17 PM PST 24
Finished Mar 07 12:56:18 PM PST 24
Peak memory 192464 kb
Host smart-de25e15c-d5cf-4d09-88f1-1cfed6726b75
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565327045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1565327045
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3184493196
Short name T580
Test name
Test status
Simulation time 1104142327 ps
CPU time 3.8 seconds
Started Mar 07 12:56:25 PM PST 24
Finished Mar 07 12:56:29 PM PST 24
Peak memory 192468 kb
Host smart-0f4f8a14-8ba2-4748-ad44-34150bc31da0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184493196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3184493196
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3623329652
Short name T490
Test name
Test status
Simulation time 41385344 ps
CPU time 0.54 seconds
Started Mar 07 12:56:19 PM PST 24
Finished Mar 07 12:56:19 PM PST 24
Peak memory 182100 kb
Host smart-e83ec6a1-d6dc-4db3-81af-7d10e67fe924
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623329652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3623329652
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2980082160
Short name T512
Test name
Test status
Simulation time 266812852 ps
CPU time 1.76 seconds
Started Mar 07 12:56:15 PM PST 24
Finished Mar 07 12:56:17 PM PST 24
Peak memory 197660 kb
Host smart-1f59838d-1c63-4b40-9ce1-c27ce6deab8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980082160 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.2980082160
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1693234708
Short name T504
Test name
Test status
Simulation time 16113516 ps
CPU time 0.59 seconds
Started Mar 07 12:56:15 PM PST 24
Finished Mar 07 12:56:15 PM PST 24
Peak memory 182812 kb
Host smart-569aaca2-cabd-4128-83d4-4475ac200baf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693234708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1693234708
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.197976500
Short name T463
Test name
Test status
Simulation time 17754920 ps
CPU time 0.57 seconds
Started Mar 07 12:56:18 PM PST 24
Finished Mar 07 12:56:18 PM PST 24
Peak memory 182556 kb
Host smart-47a51d79-b5cc-4456-9002-16d87728f233
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197976500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.197976500
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3815523478
Short name T484
Test name
Test status
Simulation time 40763259 ps
CPU time 0.8 seconds
Started Mar 07 12:56:12 PM PST 24
Finished Mar 07 12:56:13 PM PST 24
Peak memory 193392 kb
Host smart-b0adef93-fa43-4d64-a512-5a922079d672
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815523478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.3815523478
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3311516925
Short name T521
Test name
Test status
Simulation time 238288043 ps
CPU time 2.25 seconds
Started Mar 07 12:56:17 PM PST 24
Finished Mar 07 12:56:20 PM PST 24
Peak memory 197608 kb
Host smart-b852da4b-0dbb-4926-8a5d-b167e6439996
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311516925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3311516925
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1994871076
Short name T502
Test name
Test status
Simulation time 411404977 ps
CPU time 1.27 seconds
Started Mar 07 12:56:17 PM PST 24
Finished Mar 07 12:56:18 PM PST 24
Peak memory 195040 kb
Host smart-d71bd02d-c157-434e-925f-1e68470f9115
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994871076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1994871076
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.848656787
Short name T482
Test name
Test status
Simulation time 41538205 ps
CPU time 0.52 seconds
Started Mar 07 12:57:16 PM PST 24
Finished Mar 07 12:57:17 PM PST 24
Peak memory 181912 kb
Host smart-a9639daa-adec-45f0-baac-f88beab46871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848656787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.848656787
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3844822421
Short name T498
Test name
Test status
Simulation time 34963701 ps
CPU time 0.55 seconds
Started Mar 07 12:57:21 PM PST 24
Finished Mar 07 12:57:22 PM PST 24
Peak memory 182204 kb
Host smart-c978f3e9-1cab-4790-90f4-325ac3da1da3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844822421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3844822421
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3695162626
Short name T567
Test name
Test status
Simulation time 15353157 ps
CPU time 0.55 seconds
Started Mar 07 12:56:44 PM PST 24
Finished Mar 07 12:56:44 PM PST 24
Peak memory 182584 kb
Host smart-3dd7a7d2-3b86-46e6-bf62-d73a6258317e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695162626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3695162626
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.54897153
Short name T510
Test name
Test status
Simulation time 53552542 ps
CPU time 0.57 seconds
Started Mar 07 12:57:00 PM PST 24
Finished Mar 07 12:57:01 PM PST 24
Peak memory 182524 kb
Host smart-83f6ebb5-4259-466b-ba29-4caaf4b7ccac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54897153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.54897153
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1608902076
Short name T458
Test name
Test status
Simulation time 27948944 ps
CPU time 0.55 seconds
Started Mar 07 12:56:41 PM PST 24
Finished Mar 07 12:56:42 PM PST 24
Peak memory 182544 kb
Host smart-ae083c81-fe0c-4feb-8a61-9e728ec02740
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608902076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1608902076
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2246054087
Short name T457
Test name
Test status
Simulation time 81293200 ps
CPU time 0.52 seconds
Started Mar 07 12:56:39 PM PST 24
Finished Mar 07 12:56:40 PM PST 24
Peak memory 182104 kb
Host smart-5a8e7b02-3ef6-4436-83ea-692283a51b68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246054087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2246054087
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3367164910
Short name T572
Test name
Test status
Simulation time 46949225 ps
CPU time 0.58 seconds
Started Mar 07 12:56:48 PM PST 24
Finished Mar 07 12:56:49 PM PST 24
Peak memory 182488 kb
Host smart-824fd867-1250-4e20-b1d5-0aaeff10b94b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367164910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3367164910
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3559445950
Short name T493
Test name
Test status
Simulation time 39649129 ps
CPU time 0.51 seconds
Started Mar 07 12:56:48 PM PST 24
Finished Mar 07 12:56:48 PM PST 24
Peak memory 182008 kb
Host smart-5e52b64b-cc8a-4840-bb78-a9bf766f598e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559445950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3559445950
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.513227335
Short name T570
Test name
Test status
Simulation time 90549027 ps
CPU time 0.55 seconds
Started Mar 07 12:57:11 PM PST 24
Finished Mar 07 12:57:12 PM PST 24
Peak memory 182596 kb
Host smart-fe28d922-8fee-4735-8b33-1517bce98bfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513227335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.513227335
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3869521777
Short name T541
Test name
Test status
Simulation time 11907703 ps
CPU time 0.53 seconds
Started Mar 07 12:56:45 PM PST 24
Finished Mar 07 12:56:56 PM PST 24
Peak memory 182076 kb
Host smart-b72d3534-ae48-4d17-81a8-253138e6ce47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869521777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3869521777
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.250119609
Short name T500
Test name
Test status
Simulation time 62032988 ps
CPU time 0.79 seconds
Started Mar 07 12:56:25 PM PST 24
Finished Mar 07 12:56:26 PM PST 24
Peak memory 195348 kb
Host smart-b0a0b8dd-63a7-48bb-83fa-40bbc933046d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250119609 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.250119609
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3555462809
Short name T69
Test name
Test status
Simulation time 24199696 ps
CPU time 0.68 seconds
Started Mar 07 12:56:18 PM PST 24
Finished Mar 07 12:56:19 PM PST 24
Peak memory 182716 kb
Host smart-9ec5a978-6cfb-468a-b58a-1c6178b4e70d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555462809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3555462809
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3705717274
Short name T508
Test name
Test status
Simulation time 32376997 ps
CPU time 0.52 seconds
Started Mar 07 12:56:27 PM PST 24
Finished Mar 07 12:56:27 PM PST 24
Peak memory 182168 kb
Host smart-cd4cb3d9-845b-4ce8-a0a9-0df2b2d706c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705717274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.3705717274
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3209906673
Short name T54
Test name
Test status
Simulation time 39410007 ps
CPU time 0.81 seconds
Started Mar 07 12:56:25 PM PST 24
Finished Mar 07 12:56:26 PM PST 24
Peak memory 193156 kb
Host smart-18d9eb73-dffa-4175-9cdb-d4c0e1db0a87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209906673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3209906673
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.748107521
Short name T562
Test name
Test status
Simulation time 46467441 ps
CPU time 2.21 seconds
Started Mar 07 12:56:17 PM PST 24
Finished Mar 07 12:56:20 PM PST 24
Peak memory 197596 kb
Host smart-d48c1333-1efb-4f19-bc6c-7b20d0995d0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748107521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.748107521
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2236044053
Short name T568
Test name
Test status
Simulation time 112981027 ps
CPU time 1.45 seconds
Started Mar 07 12:56:22 PM PST 24
Finished Mar 07 12:56:23 PM PST 24
Peak memory 197676 kb
Host smart-16cbfd8c-7cf7-4f30-ba31-443b931c06cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236044053 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2236044053
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.2770328114
Short name T85
Test name
Test status
Simulation time 53850185 ps
CPU time 0.63 seconds
Started Mar 07 12:56:25 PM PST 24
Finished Mar 07 12:56:26 PM PST 24
Peak memory 182640 kb
Host smart-956ce6a0-3fc1-4fc0-b8ec-38ed3a2a9edc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770328114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.2770328114
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.4024822558
Short name T475
Test name
Test status
Simulation time 32789044 ps
CPU time 0.58 seconds
Started Mar 07 12:56:23 PM PST 24
Finished Mar 07 12:56:24 PM PST 24
Peak memory 182508 kb
Host smart-065053c9-0e8b-4f13-aa53-1ed93802aebc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024822558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.4024822558
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1254953170
Short name T507
Test name
Test status
Simulation time 15129820 ps
CPU time 0.57 seconds
Started Mar 07 12:56:27 PM PST 24
Finished Mar 07 12:56:28 PM PST 24
Peak memory 191124 kb
Host smart-f5c15e16-2c49-4081-8e63-e203da638e39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254953170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1254953170
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2741315286
Short name T466
Test name
Test status
Simulation time 207649997 ps
CPU time 2.78 seconds
Started Mar 07 12:56:18 PM PST 24
Finished Mar 07 12:56:21 PM PST 24
Peak memory 197612 kb
Host smart-7bd44a4e-a78b-4828-b2d5-5c85637ef8b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741315286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2741315286
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2854079771
Short name T102
Test name
Test status
Simulation time 128259383 ps
CPU time 1.05 seconds
Started Mar 07 12:56:21 PM PST 24
Finished Mar 07 12:56:22 PM PST 24
Peak memory 194704 kb
Host smart-a7034b1a-36f2-4dcc-9276-ba8ce9a9f3a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854079771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2854079771
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.52292332
Short name T52
Test name
Test status
Simulation time 83872189 ps
CPU time 0.74 seconds
Started Mar 07 12:56:24 PM PST 24
Finished Mar 07 12:56:25 PM PST 24
Peak memory 195080 kb
Host smart-be6900e2-a667-4e3c-8379-00400af2c149
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52292332 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.52292332
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3971452051
Short name T84
Test name
Test status
Simulation time 25507127 ps
CPU time 0.56 seconds
Started Mar 07 12:56:17 PM PST 24
Finished Mar 07 12:56:18 PM PST 24
Peak memory 182808 kb
Host smart-26e40561-3c8e-4515-aa46-9a878b66fe30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971452051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3971452051
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2681597175
Short name T509
Test name
Test status
Simulation time 53800341 ps
CPU time 0.54 seconds
Started Mar 07 12:56:15 PM PST 24
Finished Mar 07 12:56:15 PM PST 24
Peak memory 181960 kb
Host smart-a6e3ab04-259d-4c00-9cf5-fc27c472a787
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681597175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2681597175
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2746028297
Short name T93
Test name
Test status
Simulation time 85846910 ps
CPU time 0.66 seconds
Started Mar 07 12:56:26 PM PST 24
Finished Mar 07 12:56:27 PM PST 24
Peak memory 191984 kb
Host smart-30716262-b261-4157-9312-b11a1d82205f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746028297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2746028297
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.245944142
Short name T530
Test name
Test status
Simulation time 60640683 ps
CPU time 1.42 seconds
Started Mar 07 12:56:19 PM PST 24
Finished Mar 07 12:56:21 PM PST 24
Peak memory 197640 kb
Host smart-ad192cd4-2c59-49a8-b21d-595caa8edb22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245944142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.245944142
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1403678109
Short name T553
Test name
Test status
Simulation time 382457821 ps
CPU time 1.4 seconds
Started Mar 07 12:56:24 PM PST 24
Finished Mar 07 12:56:26 PM PST 24
Peak memory 194688 kb
Host smart-8f878f95-2edf-402c-825a-323a56c4e843
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403678109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1403678109
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2051824461
Short name T486
Test name
Test status
Simulation time 117758861 ps
CPU time 0.84 seconds
Started Mar 07 12:56:26 PM PST 24
Finished Mar 07 12:56:27 PM PST 24
Peak memory 195760 kb
Host smart-09451de2-5258-4e18-bef5-78a6b76a7494
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051824461 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2051824461
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2364591243
Short name T532
Test name
Test status
Simulation time 36552110 ps
CPU time 0.53 seconds
Started Mar 07 12:56:23 PM PST 24
Finished Mar 07 12:56:24 PM PST 24
Peak memory 182700 kb
Host smart-eb8c8e38-dcda-42d0-abd4-b686e0c4b9af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364591243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2364591243
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3959899139
Short name T503
Test name
Test status
Simulation time 51398453 ps
CPU time 0.54 seconds
Started Mar 07 12:56:15 PM PST 24
Finished Mar 07 12:56:16 PM PST 24
Peak memory 182596 kb
Host smart-8a73fb11-c7b4-4da4-b555-492c93ffeba8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959899139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3959899139
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2841118726
Short name T558
Test name
Test status
Simulation time 34200791 ps
CPU time 0.73 seconds
Started Mar 07 12:56:26 PM PST 24
Finished Mar 07 12:56:27 PM PST 24
Peak memory 193088 kb
Host smart-8a2e065c-003a-4cb1-af9b-40890484408d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841118726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2841118726
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1619220466
Short name T577
Test name
Test status
Simulation time 474371927 ps
CPU time 2.09 seconds
Started Mar 07 12:56:27 PM PST 24
Finished Mar 07 12:56:30 PM PST 24
Peak memory 197552 kb
Host smart-956ddb72-efeb-452f-be99-d236344fdd97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619220466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1619220466
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.4132140758
Short name T546
Test name
Test status
Simulation time 164128881 ps
CPU time 0.8 seconds
Started Mar 07 12:56:27 PM PST 24
Finished Mar 07 12:56:28 PM PST 24
Peak memory 182860 kb
Host smart-cabbe405-f14b-4c20-8662-8191eeed8377
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132140758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.4132140758
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2920766979
Short name T528
Test name
Test status
Simulation time 19607608 ps
CPU time 0.62 seconds
Started Mar 07 12:56:28 PM PST 24
Finished Mar 07 12:56:28 PM PST 24
Peak memory 194012 kb
Host smart-d41d4491-eb91-4d75-ada3-10915c40ed74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920766979 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2920766979
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3453115119
Short name T491
Test name
Test status
Simulation time 38742113 ps
CPU time 0.55 seconds
Started Mar 07 12:56:23 PM PST 24
Finished Mar 07 12:56:24 PM PST 24
Peak memory 182528 kb
Host smart-2d3437ae-6017-499f-b4c3-5bc5eca3b92a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453115119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3453115119
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3473187461
Short name T547
Test name
Test status
Simulation time 34970575 ps
CPU time 0.79 seconds
Started Mar 07 12:56:31 PM PST 24
Finished Mar 07 12:56:32 PM PST 24
Peak memory 191672 kb
Host smart-d375c435-bff6-4451-b348-b45706b5f332
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473187461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.3473187461
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.397113605
Short name T456
Test name
Test status
Simulation time 139028651 ps
CPU time 1.83 seconds
Started Mar 07 12:56:31 PM PST 24
Finished Mar 07 12:56:33 PM PST 24
Peak memory 197640 kb
Host smart-40a70e3f-4e85-47fc-a129-f88e1cc69147
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397113605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.397113605
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3454808014
Short name T515
Test name
Test status
Simulation time 73837617 ps
CPU time 1.08 seconds
Started Mar 07 12:56:26 PM PST 24
Finished Mar 07 12:56:27 PM PST 24
Peak memory 194932 kb
Host smart-59e26ff2-733e-4265-9a87-347b877d0ecd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454808014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3454808014
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1766654910
Short name T221
Test name
Test status
Simulation time 69914693465 ps
CPU time 69.82 seconds
Started Mar 07 01:01:02 PM PST 24
Finished Mar 07 01:02:13 PM PST 24
Peak memory 183376 kb
Host smart-d3d6689c-a940-44a8-8e3d-80254bc5fc14
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766654910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1766654910
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2586145178
Short name T384
Test name
Test status
Simulation time 411079349099 ps
CPU time 177.21 seconds
Started Mar 07 01:01:08 PM PST 24
Finished Mar 07 01:04:05 PM PST 24
Peak memory 183384 kb
Host smart-cfc92c02-38fa-409d-b2b0-5a8f80f193de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586145178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2586145178
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.152713881
Short name T390
Test name
Test status
Simulation time 114318593 ps
CPU time 3.9 seconds
Started Mar 07 01:01:11 PM PST 24
Finished Mar 07 01:01:16 PM PST 24
Peak memory 183328 kb
Host smart-abc0f4ea-e3cd-4efc-90a9-e4a60184288e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152713881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.152713881
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2620831013
Short name T311
Test name
Test status
Simulation time 256133464091 ps
CPU time 158.6 seconds
Started Mar 07 01:01:06 PM PST 24
Finished Mar 07 01:03:45 PM PST 24
Peak memory 183360 kb
Host smart-dc3a7bbd-49e4-4129-97ff-7c8a332d14c5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620831013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2620831013
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.1926570909
Short name T379
Test name
Test status
Simulation time 239386776751 ps
CPU time 255.11 seconds
Started Mar 07 01:01:05 PM PST 24
Finished Mar 07 01:05:20 PM PST 24
Peak memory 183432 kb
Host smart-cfca4991-5cd1-4da8-ba61-97c9e8d14f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926570909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1926570909
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.2822677868
Short name T340
Test name
Test status
Simulation time 414050892650 ps
CPU time 523.46 seconds
Started Mar 07 01:01:20 PM PST 24
Finished Mar 07 01:10:04 PM PST 24
Peak memory 191636 kb
Host smart-3bc52298-9bc1-44fe-b0fe-b01e36335ddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822677868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2822677868
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.1135496725
Short name T309
Test name
Test status
Simulation time 40430501797 ps
CPU time 221.35 seconds
Started Mar 07 01:00:56 PM PST 24
Finished Mar 07 01:04:38 PM PST 24
Peak memory 183396 kb
Host smart-62869a1c-c7dc-4889-9c62-a890c3545510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135496725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1135496725
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.3023769429
Short name T21
Test name
Test status
Simulation time 92687461 ps
CPU time 0.92 seconds
Started Mar 07 01:01:07 PM PST 24
Finished Mar 07 01:01:08 PM PST 24
Peak memory 214604 kb
Host smart-8f9807cc-0591-4ddd-917f-017271f06ccb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023769429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3023769429
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.2484630045
Short name T41
Test name
Test status
Simulation time 44614442000 ps
CPU time 490.07 seconds
Started Mar 07 01:00:56 PM PST 24
Finished Mar 07 01:09:06 PM PST 24
Peak memory 206272 kb
Host smart-2eadff70-861b-425c-8c30-39c19d328dbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484630045 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.2484630045
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.1241769175
Short name T248
Test name
Test status
Simulation time 9295915641 ps
CPU time 9.98 seconds
Started Mar 07 01:01:17 PM PST 24
Finished Mar 07 01:01:27 PM PST 24
Peak memory 183360 kb
Host smart-1b936321-b727-4d22-82aa-18c18f751569
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241769175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.1241769175
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.1329337207
Short name T362
Test name
Test status
Simulation time 21437650866 ps
CPU time 32.79 seconds
Started Mar 07 01:01:24 PM PST 24
Finished Mar 07 01:01:57 PM PST 24
Peak memory 183372 kb
Host smart-efab9dc7-63fd-41b9-8f1b-15c83867233f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329337207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1329337207
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2042560310
Short name T388
Test name
Test status
Simulation time 162701992 ps
CPU time 1.53 seconds
Started Mar 07 01:01:19 PM PST 24
Finished Mar 07 01:01:21 PM PST 24
Peak memory 183272 kb
Host smart-ec8e9e50-13f7-42a1-9eb4-daeed01ca437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042560310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2042560310
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.1182803631
Short name T392
Test name
Test status
Simulation time 14308165226 ps
CPU time 25.33 seconds
Started Mar 07 01:01:51 PM PST 24
Finished Mar 07 01:02:17 PM PST 24
Peak memory 183372 kb
Host smart-c3c5f938-f93f-4e57-8c17-a5e89ce03060
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182803631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1182803631
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.2345025871
Short name T415
Test name
Test status
Simulation time 162827866910 ps
CPU time 46.69 seconds
Started Mar 07 01:01:43 PM PST 24
Finished Mar 07 01:02:30 PM PST 24
Peak memory 183392 kb
Host smart-1948301f-eb0c-48a6-9097-cc534777b8ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345025871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2345025871
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.262039735
Short name T433
Test name
Test status
Simulation time 82918247771 ps
CPU time 151.59 seconds
Started Mar 07 01:01:46 PM PST 24
Finished Mar 07 01:04:18 PM PST 24
Peak memory 191600 kb
Host smart-3da04d43-26f9-4d60-b4e2-b7b7c6fb4f1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262039735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.262039735
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1242595352
Short name T159
Test name
Test status
Simulation time 620406053457 ps
CPU time 918.79 seconds
Started Mar 07 01:01:49 PM PST 24
Finished Mar 07 01:17:09 PM PST 24
Peak memory 191628 kb
Host smart-184d19a6-8441-4783-8c74-e4735a272469
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242595352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1242595352
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.637668706
Short name T206
Test name
Test status
Simulation time 171093154046 ps
CPU time 534.9 seconds
Started Mar 07 01:01:53 PM PST 24
Finished Mar 07 01:10:49 PM PST 24
Peak memory 191596 kb
Host smart-e62c6244-b162-4163-bc9f-34d6e4c9c7d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637668706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.637668706
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.889501830
Short name T213
Test name
Test status
Simulation time 538325459783 ps
CPU time 1866.27 seconds
Started Mar 07 01:01:49 PM PST 24
Finished Mar 07 01:32:56 PM PST 24
Peak memory 191588 kb
Host smart-00f4d239-2c38-4766-b9c0-9d4599628a44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889501830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.889501830
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.419680399
Short name T404
Test name
Test status
Simulation time 315468547384 ps
CPU time 69.66 seconds
Started Mar 07 01:01:06 PM PST 24
Finished Mar 07 01:02:16 PM PST 24
Peak memory 183392 kb
Host smart-fa556177-ad74-48ab-8c59-dbd76da20d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419680399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.419680399
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.474971853
Short name T324
Test name
Test status
Simulation time 138268240320 ps
CPU time 453.03 seconds
Started Mar 07 01:01:35 PM PST 24
Finished Mar 07 01:09:08 PM PST 24
Peak memory 191632 kb
Host smart-57b57083-e90d-46c3-8138-e612d567582d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474971853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.474971853
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1194104943
Short name T437
Test name
Test status
Simulation time 38384300936 ps
CPU time 35.55 seconds
Started Mar 07 01:01:20 PM PST 24
Finished Mar 07 01:01:57 PM PST 24
Peak memory 194476 kb
Host smart-f1860cf8-7a82-4976-ae3b-cba0942e15af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194104943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1194104943
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.2833870907
Short name T397
Test name
Test status
Simulation time 24731937391 ps
CPU time 36.95 seconds
Started Mar 07 01:01:59 PM PST 24
Finished Mar 07 01:02:36 PM PST 24
Peak memory 183396 kb
Host smart-4f778b8c-4b29-4fba-ad6d-4d281dc5004f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833870907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2833870907
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.4105705101
Short name T260
Test name
Test status
Simulation time 602647485445 ps
CPU time 297.55 seconds
Started Mar 07 01:01:49 PM PST 24
Finished Mar 07 01:06:46 PM PST 24
Peak memory 194828 kb
Host smart-c9c4bf91-11b9-418c-b6f4-c41a23ac38bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105705101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.4105705101
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.3270105270
Short name T226
Test name
Test status
Simulation time 216220096008 ps
CPU time 181.57 seconds
Started Mar 07 01:01:46 PM PST 24
Finished Mar 07 01:04:48 PM PST 24
Peak memory 191584 kb
Host smart-d0928262-1ba0-45f5-85f3-294619db0fbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270105270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3270105270
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.578269119
Short name T24
Test name
Test status
Simulation time 539587770106 ps
CPU time 313.19 seconds
Started Mar 07 01:01:55 PM PST 24
Finished Mar 07 01:07:08 PM PST 24
Peak memory 191692 kb
Host smart-eb7dcfd7-e272-4088-93e1-944b45c7f246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578269119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.578269119
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3931842511
Short name T170
Test name
Test status
Simulation time 110506516418 ps
CPU time 187.77 seconds
Started Mar 07 01:01:58 PM PST 24
Finished Mar 07 01:05:06 PM PST 24
Peak memory 191536 kb
Host smart-8ec2c02d-ec80-48c5-8f91-2aa7a401bfa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931842511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3931842511
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.3495799822
Short name T348
Test name
Test status
Simulation time 40617938565 ps
CPU time 73.81 seconds
Started Mar 07 01:01:56 PM PST 24
Finished Mar 07 01:03:09 PM PST 24
Peak memory 191540 kb
Host smart-da337781-b0b3-4dd9-a1de-b514ae3c12bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495799822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3495799822
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.1596040315
Short name T267
Test name
Test status
Simulation time 582376448924 ps
CPU time 354.3 seconds
Started Mar 07 01:01:48 PM PST 24
Finished Mar 07 01:07:42 PM PST 24
Peak memory 191596 kb
Host smart-e75c5205-40be-4f27-abe5-7310ddcac5ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596040315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1596040315
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.2854773235
Short name T246
Test name
Test status
Simulation time 288846557249 ps
CPU time 504.14 seconds
Started Mar 07 01:02:00 PM PST 24
Finished Mar 07 01:10:24 PM PST 24
Peak memory 191612 kb
Host smart-5eef78ba-9e75-4185-8a64-9fa9231e3728
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854773235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2854773235
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3410307704
Short name T262
Test name
Test status
Simulation time 220961320548 ps
CPU time 404.75 seconds
Started Mar 07 01:01:01 PM PST 24
Finished Mar 07 01:07:46 PM PST 24
Peak memory 183396 kb
Host smart-550ea834-6afe-4714-8c99-b5356903697e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410307704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3410307704
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.982378465
Short name T46
Test name
Test status
Simulation time 59684194786 ps
CPU time 88.05 seconds
Started Mar 07 01:01:15 PM PST 24
Finished Mar 07 01:02:43 PM PST 24
Peak memory 183456 kb
Host smart-d9141492-14ec-42da-8c60-d59707c6340f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982378465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.982378465
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.585173903
Short name T216
Test name
Test status
Simulation time 234763396088 ps
CPU time 665.85 seconds
Started Mar 07 01:01:40 PM PST 24
Finished Mar 07 01:12:46 PM PST 24
Peak memory 195008 kb
Host smart-30d3e9b7-cd46-4dbc-9aad-7fa1007ced88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585173903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.585173903
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3229627763
Short name T259
Test name
Test status
Simulation time 363035965383 ps
CPU time 274.69 seconds
Started Mar 07 01:01:12 PM PST 24
Finished Mar 07 01:05:47 PM PST 24
Peak memory 195012 kb
Host smart-b31905b5-8d47-4914-8f2a-25145d1082a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229627763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3229627763
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.3267575948
Short name T40
Test name
Test status
Simulation time 23095806470 ps
CPU time 179.5 seconds
Started Mar 07 01:01:22 PM PST 24
Finished Mar 07 01:04:22 PM PST 24
Peak memory 197604 kb
Host smart-f6d0323f-f1d8-4270-bcb3-522c037439f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267575948 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.3267575948
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/122.rv_timer_random.2480380744
Short name T184
Test name
Test status
Simulation time 25636786299 ps
CPU time 123.97 seconds
Started Mar 07 01:02:05 PM PST 24
Finished Mar 07 01:04:09 PM PST 24
Peak memory 191528 kb
Host smart-c38c3e9c-fb39-4008-a217-29a5c123616b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480380744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2480380744
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1794579728
Short name T280
Test name
Test status
Simulation time 76936938469 ps
CPU time 196.53 seconds
Started Mar 07 01:01:59 PM PST 24
Finished Mar 07 01:05:16 PM PST 24
Peak memory 191612 kb
Host smart-572eac12-b9ae-4d7c-b2ac-5e391824b789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794579728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1794579728
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.1752855459
Short name T174
Test name
Test status
Simulation time 247784506151 ps
CPU time 392.76 seconds
Started Mar 07 01:02:00 PM PST 24
Finished Mar 07 01:08:34 PM PST 24
Peak memory 191612 kb
Host smart-8eace94a-4f0e-4c12-9a71-696b0bc4b16f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752855459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1752855459
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2752884149
Short name T252
Test name
Test status
Simulation time 163036118888 ps
CPU time 136.55 seconds
Started Mar 07 01:02:00 PM PST 24
Finished Mar 07 01:04:17 PM PST 24
Peak memory 192692 kb
Host smart-9739d865-2178-4a75-8706-b500c4fae515
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752884149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2752884149
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1760715014
Short name T347
Test name
Test status
Simulation time 191473650461 ps
CPU time 115.66 seconds
Started Mar 07 01:02:05 PM PST 24
Finished Mar 07 01:04:01 PM PST 24
Peak memory 183408 kb
Host smart-a7284404-9238-4558-9b95-623ccda53729
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760715014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1760715014
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.393039951
Short name T183
Test name
Test status
Simulation time 84595957306 ps
CPU time 630.69 seconds
Started Mar 07 01:02:00 PM PST 24
Finished Mar 07 01:12:31 PM PST 24
Peak memory 194732 kb
Host smart-136d19ac-9215-45fb-a1a0-7271aa790406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393039951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.393039951
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2729876130
Short name T414
Test name
Test status
Simulation time 223000554205 ps
CPU time 167.13 seconds
Started Mar 07 01:01:24 PM PST 24
Finished Mar 07 01:04:12 PM PST 24
Peak memory 183364 kb
Host smart-ddb623d7-612f-4dd2-8bc0-d476c579409b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729876130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2729876130
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3228356330
Short name T335
Test name
Test status
Simulation time 142645545401 ps
CPU time 273.13 seconds
Started Mar 07 01:01:11 PM PST 24
Finished Mar 07 01:05:45 PM PST 24
Peak memory 183456 kb
Host smart-f9a7fac0-a072-4818-b379-cca571afae50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228356330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3228356330
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.1367994469
Short name T217
Test name
Test status
Simulation time 13438573676 ps
CPU time 20.09 seconds
Started Mar 07 01:02:06 PM PST 24
Finished Mar 07 01:02:26 PM PST 24
Peak memory 183412 kb
Host smart-0f2082ba-62d8-4c11-873c-c77aeb114406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367994469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1367994469
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.1428838866
Short name T22
Test name
Test status
Simulation time 156937969154 ps
CPU time 58.23 seconds
Started Mar 07 01:02:06 PM PST 24
Finished Mar 07 01:03:05 PM PST 24
Peak memory 183388 kb
Host smart-63f275af-94b9-455c-a4ea-9461232e8baf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428838866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1428838866
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.877193175
Short name T326
Test name
Test status
Simulation time 19697686908 ps
CPU time 31.21 seconds
Started Mar 07 01:02:08 PM PST 24
Finished Mar 07 01:02:39 PM PST 24
Peak memory 183348 kb
Host smart-5fa83f6e-ed12-4b98-9b00-92806f6c7dce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877193175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.877193175
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.4212850743
Short name T168
Test name
Test status
Simulation time 161437782274 ps
CPU time 343.52 seconds
Started Mar 07 01:02:14 PM PST 24
Finished Mar 07 01:07:57 PM PST 24
Peak memory 191604 kb
Host smart-294a997a-0471-4194-964e-a39c70a913d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212850743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.4212850743
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3745069673
Short name T29
Test name
Test status
Simulation time 341588082910 ps
CPU time 160.39 seconds
Started Mar 07 01:01:55 PM PST 24
Finished Mar 07 01:04:36 PM PST 24
Peak memory 191624 kb
Host smart-9bbf9155-0f08-4bac-8b46-1f0bcfca5b7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745069673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3745069673
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.2583467337
Short name T304
Test name
Test status
Simulation time 269328341241 ps
CPU time 241.17 seconds
Started Mar 07 01:02:12 PM PST 24
Finished Mar 07 01:06:13 PM PST 24
Peak memory 191620 kb
Host smart-16863a49-002e-4310-8e10-beca82bc34d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583467337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.2583467337
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.102955019
Short name T129
Test name
Test status
Simulation time 4784602668 ps
CPU time 6.51 seconds
Started Mar 07 01:02:03 PM PST 24
Finished Mar 07 01:02:10 PM PST 24
Peak memory 183420 kb
Host smart-a9dd97df-4b17-4124-96fe-507c4cf5f341
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102955019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.102955019
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.635690389
Short name T268
Test name
Test status
Simulation time 490593226715 ps
CPU time 245.86 seconds
Started Mar 07 01:02:09 PM PST 24
Finished Mar 07 01:06:15 PM PST 24
Peak memory 191608 kb
Host smart-ad0f6c6b-9895-4834-9666-3e01f4f4a2e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635690389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.635690389
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.3985902622
Short name T327
Test name
Test status
Simulation time 121339398278 ps
CPU time 103.35 seconds
Started Mar 07 01:02:03 PM PST 24
Finished Mar 07 01:03:46 PM PST 24
Peak memory 194368 kb
Host smart-4cc7adee-648a-44c3-98e4-12fe3594b514
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985902622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3985902622
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.558590016
Short name T439
Test name
Test status
Simulation time 107089149413 ps
CPU time 139.32 seconds
Started Mar 07 01:01:25 PM PST 24
Finished Mar 07 01:03:45 PM PST 24
Peak memory 183312 kb
Host smart-c42680bf-df3c-40de-ab5b-ac9e28daffa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558590016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.558590016
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.431982416
Short name T4
Test name
Test status
Simulation time 66663062206 ps
CPU time 210.22 seconds
Started Mar 07 01:01:22 PM PST 24
Finished Mar 07 01:04:53 PM PST 24
Peak memory 191612 kb
Host smart-7e071d80-56ce-444c-b423-4a54e2735e85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431982416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.431982416
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.2551948056
Short name T434
Test name
Test status
Simulation time 76042239 ps
CPU time 0.84 seconds
Started Mar 07 01:01:31 PM PST 24
Finished Mar 07 01:01:32 PM PST 24
Peak memory 183020 kb
Host smart-2071de7b-ad49-4b87-ac34-f6e642352ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551948056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2551948056
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.4214699401
Short name T310
Test name
Test status
Simulation time 42542598236 ps
CPU time 1167.55 seconds
Started Mar 07 01:02:01 PM PST 24
Finished Mar 07 01:21:29 PM PST 24
Peak memory 194048 kb
Host smart-33a9cf80-41f5-4e6e-9228-48f8dd6d7a3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214699401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.4214699401
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.2782205518
Short name T257
Test name
Test status
Simulation time 150582741880 ps
CPU time 499.94 seconds
Started Mar 07 01:01:54 PM PST 24
Finished Mar 07 01:10:14 PM PST 24
Peak memory 194860 kb
Host smart-12e1f183-b321-4a77-af13-8f30f06c5ec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782205518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2782205518
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.504932965
Short name T424
Test name
Test status
Simulation time 13063459923 ps
CPU time 21.71 seconds
Started Mar 07 01:01:59 PM PST 24
Finished Mar 07 01:02:21 PM PST 24
Peak memory 183368 kb
Host smart-1f790e3c-c550-4d76-960e-6c73fd874934
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504932965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.504932965
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1123728771
Short name T406
Test name
Test status
Simulation time 67167214043 ps
CPU time 149.04 seconds
Started Mar 07 01:02:02 PM PST 24
Finished Mar 07 01:04:31 PM PST 24
Peak memory 191576 kb
Host smart-02b1eeba-ca28-4594-b218-23d32da584d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123728771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1123728771
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.4062498025
Short name T359
Test name
Test status
Simulation time 181030381995 ps
CPU time 389.17 seconds
Started Mar 07 01:02:06 PM PST 24
Finished Mar 07 01:08:36 PM PST 24
Peak memory 191572 kb
Host smart-06826bc8-9e64-4d2b-bc3a-9aaddc6fba02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062498025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.4062498025
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1099607210
Short name T106
Test name
Test status
Simulation time 37566552928 ps
CPU time 88.37 seconds
Started Mar 07 01:02:08 PM PST 24
Finished Mar 07 01:03:36 PM PST 24
Peak memory 191628 kb
Host smart-5b7d8455-5c2a-4cd4-8e92-030940e43312
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099607210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1099607210
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.2974334978
Short name T407
Test name
Test status
Simulation time 15119104604 ps
CPU time 10.08 seconds
Started Mar 07 01:02:07 PM PST 24
Finished Mar 07 01:02:18 PM PST 24
Peak memory 183408 kb
Host smart-419b61b6-8e7d-4348-98a2-365338017748
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974334978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2974334978
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.4216588159
Short name T270
Test name
Test status
Simulation time 1562618747191 ps
CPU time 635.45 seconds
Started Mar 07 01:02:11 PM PST 24
Finished Mar 07 01:12:46 PM PST 24
Peak memory 194912 kb
Host smart-c85a1ca6-24af-4fa3-818c-026a3484e7f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216588159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.4216588159
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.4060041149
Short name T12
Test name
Test status
Simulation time 27630458889 ps
CPU time 49.44 seconds
Started Mar 07 01:02:05 PM PST 24
Finished Mar 07 01:02:54 PM PST 24
Peak memory 191536 kb
Host smart-1009c6c6-62d0-438d-8fa0-4121c34c6783
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060041149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.4060041149
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.3660070412
Short name T247
Test name
Test status
Simulation time 309915414497 ps
CPU time 499.78 seconds
Started Mar 07 01:01:18 PM PST 24
Finished Mar 07 01:09:38 PM PST 24
Peak memory 183384 kb
Host smart-0c993f9e-fde4-44e4-a133-bcfb983adbb3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660070412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.3660070412
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.3434179287
Short name T428
Test name
Test status
Simulation time 358559053738 ps
CPU time 145.62 seconds
Started Mar 07 01:01:43 PM PST 24
Finished Mar 07 01:04:09 PM PST 24
Peak memory 183308 kb
Host smart-3b598dd3-1f34-464f-a2e0-2f1f342245bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434179287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3434179287
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3105376794
Short name T416
Test name
Test status
Simulation time 93072572 ps
CPU time 0.57 seconds
Started Mar 07 01:01:28 PM PST 24
Finished Mar 07 01:01:29 PM PST 24
Peak memory 183084 kb
Host smart-d049c590-e954-40f2-b53e-64a2a5ce3047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105376794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3105376794
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2930033772
Short name T44
Test name
Test status
Simulation time 745023030802 ps
CPU time 584.07 seconds
Started Mar 07 01:01:22 PM PST 24
Finished Mar 07 01:11:07 PM PST 24
Peak memory 191564 kb
Host smart-f9db5be0-05ba-4690-ad7d-bc12b895a615
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930033772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2930033772
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/151.rv_timer_random.3777469951
Short name T127
Test name
Test status
Simulation time 33099836109 ps
CPU time 26 seconds
Started Mar 07 01:02:01 PM PST 24
Finished Mar 07 01:02:27 PM PST 24
Peak memory 183444 kb
Host smart-a218f392-ecfc-4e1a-bde9-bab180decdd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777469951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3777469951
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3274658500
Short name T118
Test name
Test status
Simulation time 82904776767 ps
CPU time 355.35 seconds
Started Mar 07 01:01:59 PM PST 24
Finished Mar 07 01:07:54 PM PST 24
Peak memory 191536 kb
Host smart-be0ec0ac-29e7-409c-83bd-fbf33cd50427
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274658500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3274658500
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3846064776
Short name T344
Test name
Test status
Simulation time 61968472585 ps
CPU time 98.54 seconds
Started Mar 07 01:02:01 PM PST 24
Finished Mar 07 01:03:40 PM PST 24
Peak memory 191520 kb
Host smart-ef0642ed-3810-4c8e-9889-12e2b096747e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846064776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3846064776
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.3636076226
Short name T393
Test name
Test status
Simulation time 86767714146 ps
CPU time 139.83 seconds
Started Mar 07 01:01:26 PM PST 24
Finished Mar 07 01:03:46 PM PST 24
Peak memory 183348 kb
Host smart-790c3096-651b-44d9-b80b-fa78c8f7410e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636076226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3636076226
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1903772406
Short name T181
Test name
Test status
Simulation time 212117816207 ps
CPU time 284.76 seconds
Started Mar 07 01:01:24 PM PST 24
Finished Mar 07 01:06:10 PM PST 24
Peak memory 191648 kb
Host smart-4ed666a2-8c04-4db9-ab69-9e42cd83da5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903772406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1903772406
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.1516230474
Short name T99
Test name
Test status
Simulation time 410883926867 ps
CPU time 731.53 seconds
Started Mar 07 01:01:31 PM PST 24
Finished Mar 07 01:13:43 PM PST 24
Peak memory 208268 kb
Host smart-47866844-fe0d-49d3-a79b-5c8a3f9cfefe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516230474 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.1516230474
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.2381569134
Short name T313
Test name
Test status
Simulation time 793932102763 ps
CPU time 212.27 seconds
Started Mar 07 01:02:05 PM PST 24
Finished Mar 07 01:05:38 PM PST 24
Peak memory 195132 kb
Host smart-87e04767-80a7-4c99-955b-f581012e31eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381569134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.2381569134
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.1935509817
Short name T178
Test name
Test status
Simulation time 754856683356 ps
CPU time 587.96 seconds
Started Mar 07 01:02:05 PM PST 24
Finished Mar 07 01:11:53 PM PST 24
Peak memory 191584 kb
Host smart-4c973a01-99f4-41b3-8b28-b2b27cf6bcba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935509817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1935509817
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.1679439891
Short name T332
Test name
Test status
Simulation time 58698392827 ps
CPU time 46.26 seconds
Started Mar 07 01:02:02 PM PST 24
Finished Mar 07 01:02:48 PM PST 24
Peak memory 183396 kb
Host smart-df8fe81e-4e41-47fc-8b1d-5cc29a1383d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679439891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1679439891
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.2033063613
Short name T256
Test name
Test status
Simulation time 426517273540 ps
CPU time 398.43 seconds
Started Mar 07 01:02:03 PM PST 24
Finished Mar 07 01:08:41 PM PST 24
Peak memory 191540 kb
Host smart-b2e13da9-cc48-43a7-a965-ae0afbde079a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033063613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2033063613
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.1957611000
Short name T271
Test name
Test status
Simulation time 72328082052 ps
CPU time 802.58 seconds
Started Mar 07 01:01:58 PM PST 24
Finished Mar 07 01:15:21 PM PST 24
Peak memory 191560 kb
Host smart-1dd3f9b2-9c88-4daa-b44c-c4aa8c6213ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957611000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.1957611000
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.4259212696
Short name T436
Test name
Test status
Simulation time 139289328201 ps
CPU time 99.85 seconds
Started Mar 07 01:02:07 PM PST 24
Finished Mar 07 01:03:47 PM PST 24
Peak memory 191488 kb
Host smart-7c19a85a-aa90-436f-933e-0ee7d7600b32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259212696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.4259212696
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.3774997411
Short name T358
Test name
Test status
Simulation time 70309609643 ps
CPU time 1287.88 seconds
Started Mar 07 01:02:08 PM PST 24
Finished Mar 07 01:23:36 PM PST 24
Peak memory 191576 kb
Host smart-a43cacf8-d1c2-431a-b3be-0849e63f09ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774997411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3774997411
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3921049855
Short name T203
Test name
Test status
Simulation time 1070237941505 ps
CPU time 616.99 seconds
Started Mar 07 01:01:25 PM PST 24
Finished Mar 07 01:11:43 PM PST 24
Peak memory 183352 kb
Host smart-afeb51fb-3337-4d7e-8c31-110e9266af0a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921049855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3921049855
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.908785094
Short name T405
Test name
Test status
Simulation time 63799265125 ps
CPU time 99.38 seconds
Started Mar 07 01:01:20 PM PST 24
Finished Mar 07 01:03:00 PM PST 24
Peak memory 183392 kb
Host smart-2b496071-1c77-4f24-add3-db227a9312e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908785094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.908785094
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.1460617376
Short name T242
Test name
Test status
Simulation time 229193702124 ps
CPU time 402.76 seconds
Started Mar 07 01:01:35 PM PST 24
Finished Mar 07 01:08:18 PM PST 24
Peak memory 193940 kb
Host smart-6a453b07-0fca-47b7-a685-30a355cb5484
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460617376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1460617376
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.31320759
Short name T421
Test name
Test status
Simulation time 731768337 ps
CPU time 1.47 seconds
Started Mar 07 01:01:20 PM PST 24
Finished Mar 07 01:01:22 PM PST 24
Peak memory 183292 kb
Host smart-04d29b71-ba9c-42b4-ba15-df932f99f6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31320759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.31320759
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.1616219460
Short name T391
Test name
Test status
Simulation time 623513859044 ps
CPU time 528.77 seconds
Started Mar 07 01:01:16 PM PST 24
Finished Mar 07 01:10:05 PM PST 24
Peak memory 191588 kb
Host smart-6e8e72c9-b8b9-48a5-8527-1664d30a6ed0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616219460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.1616219460
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/171.rv_timer_random.7083859
Short name T167
Test name
Test status
Simulation time 141647965743 ps
CPU time 125.42 seconds
Started Mar 07 01:02:07 PM PST 24
Finished Mar 07 01:04:12 PM PST 24
Peak memory 191596 kb
Host smart-fb466999-e720-4205-9495-d810287282f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7083859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.7083859
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.1250005683
Short name T292
Test name
Test status
Simulation time 347776548532 ps
CPU time 211.75 seconds
Started Mar 07 01:01:55 PM PST 24
Finished Mar 07 01:05:27 PM PST 24
Peak memory 191596 kb
Host smart-1ed339f6-e468-4b7a-b840-871c589144d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250005683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1250005683
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.3248483948
Short name T27
Test name
Test status
Simulation time 163049528445 ps
CPU time 511.15 seconds
Started Mar 07 01:01:57 PM PST 24
Finished Mar 07 01:10:28 PM PST 24
Peak memory 194368 kb
Host smart-7f6a63b2-59cb-4e0e-8e5f-2b6cb5b014e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248483948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3248483948
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.1414913494
Short name T222
Test name
Test status
Simulation time 386292498628 ps
CPU time 127.05 seconds
Started Mar 07 01:01:59 PM PST 24
Finished Mar 07 01:04:06 PM PST 24
Peak memory 191644 kb
Host smart-8b6905db-05cf-462c-bffd-476922018d61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414913494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1414913494
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.3749573629
Short name T232
Test name
Test status
Simulation time 111565143274 ps
CPU time 67.91 seconds
Started Mar 07 01:01:58 PM PST 24
Finished Mar 07 01:03:07 PM PST 24
Peak memory 193780 kb
Host smart-f5814120-795b-41f7-9c3e-eb6c759a02ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749573629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3749573629
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.1396971778
Short name T282
Test name
Test status
Simulation time 59083507522 ps
CPU time 50.51 seconds
Started Mar 07 01:02:03 PM PST 24
Finished Mar 07 01:02:54 PM PST 24
Peak memory 183376 kb
Host smart-f2a5dde8-30ea-4c42-a585-9da9f323682e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396971778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1396971778
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.432597908
Short name T228
Test name
Test status
Simulation time 74683509917 ps
CPU time 721.57 seconds
Started Mar 07 01:02:02 PM PST 24
Finished Mar 07 01:14:03 PM PST 24
Peak memory 194780 kb
Host smart-735f3bfc-868e-41ac-81af-4c313825eac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432597908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.432597908
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.2923093472
Short name T77
Test name
Test status
Simulation time 149800451583 ps
CPU time 254.28 seconds
Started Mar 07 01:02:04 PM PST 24
Finished Mar 07 01:06:18 PM PST 24
Peak memory 191596 kb
Host smart-e2edc016-f1b8-403e-ac55-5a01f40a4af3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923093472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2923093472
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.1568135061
Short name T233
Test name
Test status
Simulation time 77469870151 ps
CPU time 41.57 seconds
Started Mar 07 01:01:28 PM PST 24
Finished Mar 07 01:02:10 PM PST 24
Peak memory 183252 kb
Host smart-ebaf35ed-738c-4319-a4ab-5b860690f944
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568135061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.1568135061
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1877301282
Short name T443
Test name
Test status
Simulation time 173667262867 ps
CPU time 277.33 seconds
Started Mar 07 01:01:24 PM PST 24
Finished Mar 07 01:06:02 PM PST 24
Peak memory 183396 kb
Host smart-fd2a9570-ad9c-424c-a6db-7b6333a9679d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877301282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1877301282
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.69722409
Short name T298
Test name
Test status
Simulation time 12502271551 ps
CPU time 9.63 seconds
Started Mar 07 01:01:26 PM PST 24
Finished Mar 07 01:01:36 PM PST 24
Peak memory 183384 kb
Host smart-37703b6b-b451-43d9-a688-dc632a3a6b14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69722409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.69722409
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.659500053
Short name T425
Test name
Test status
Simulation time 6985566275 ps
CPU time 23.13 seconds
Started Mar 07 01:01:22 PM PST 24
Finished Mar 07 01:01:46 PM PST 24
Peak memory 191492 kb
Host smart-d6163cfe-287e-4bbc-9883-eb9f76196dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659500053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.659500053
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.520700555
Short name T263
Test name
Test status
Simulation time 481757470223 ps
CPU time 287.1 seconds
Started Mar 07 01:01:26 PM PST 24
Finished Mar 07 01:06:15 PM PST 24
Peak memory 191628 kb
Host smart-4e25bdce-4782-4216-a017-b8bfc94d01a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520700555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.
520700555
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/182.rv_timer_random.1533301246
Short name T276
Test name
Test status
Simulation time 1298909636639 ps
CPU time 440.08 seconds
Started Mar 07 01:02:06 PM PST 24
Finished Mar 07 01:09:26 PM PST 24
Peak memory 191600 kb
Host smart-b3787c03-748a-4399-a16b-d95120ce01e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533301246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1533301246
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1148760206
Short name T28
Test name
Test status
Simulation time 920426101767 ps
CPU time 440.48 seconds
Started Mar 07 01:02:09 PM PST 24
Finished Mar 07 01:09:30 PM PST 24
Peak memory 191600 kb
Host smart-d1aceaf0-f21e-47b1-8723-8edc2f8cc433
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148760206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1148760206
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1961413980
Short name T294
Test name
Test status
Simulation time 346833297471 ps
CPU time 271.56 seconds
Started Mar 07 01:02:13 PM PST 24
Finished Mar 07 01:06:44 PM PST 24
Peak memory 194300 kb
Host smart-b6381330-719f-4434-ba33-b2a1e6b4f818
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961413980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1961413980
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.4256253444
Short name T420
Test name
Test status
Simulation time 105336436967 ps
CPU time 119.3 seconds
Started Mar 07 01:02:06 PM PST 24
Finished Mar 07 01:04:05 PM PST 24
Peak memory 191600 kb
Host smart-108ee989-5a86-4663-992f-67ccd7418b0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256253444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.4256253444
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.3459806881
Short name T427
Test name
Test status
Simulation time 98548349933 ps
CPU time 76 seconds
Started Mar 07 01:02:07 PM PST 24
Finished Mar 07 01:03:23 PM PST 24
Peak memory 191604 kb
Host smart-0a02b025-4c14-4025-b0c4-5c8212dfa991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459806881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3459806881
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1135483797
Short name T215
Test name
Test status
Simulation time 527050284231 ps
CPU time 296.18 seconds
Started Mar 07 01:02:09 PM PST 24
Finished Mar 07 01:07:05 PM PST 24
Peak memory 191600 kb
Host smart-a388715c-b76d-4255-b771-6fa73e3da955
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135483797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1135483797
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.3380799693
Short name T250
Test name
Test status
Simulation time 764144111397 ps
CPU time 940.58 seconds
Started Mar 07 01:02:07 PM PST 24
Finished Mar 07 01:17:48 PM PST 24
Peak memory 191632 kb
Host smart-0daf5548-253f-48bf-88db-676a914001ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380799693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3380799693
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3870525670
Short name T351
Test name
Test status
Simulation time 64855064028 ps
CPU time 1580.25 seconds
Started Mar 07 01:02:05 PM PST 24
Finished Mar 07 01:28:25 PM PST 24
Peak memory 191612 kb
Host smart-7ddf1754-c209-4de5-9837-56f7c103d6d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870525670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3870525670
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.827721367
Short name T116
Test name
Test status
Simulation time 348599298866 ps
CPU time 562.15 seconds
Started Mar 07 01:01:25 PM PST 24
Finished Mar 07 01:10:48 PM PST 24
Peak memory 183368 kb
Host smart-c9525257-39d8-453c-b255-dd7633ebe2d9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827721367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.827721367
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1902650964
Short name T408
Test name
Test status
Simulation time 181887180271 ps
CPU time 244.62 seconds
Started Mar 07 01:01:41 PM PST 24
Finished Mar 07 01:05:46 PM PST 24
Peak memory 183456 kb
Host smart-8f119e9f-ce9d-4d36-9d05-d5a9eddde660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902650964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1902650964
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.2696929952
Short name T431
Test name
Test status
Simulation time 25888340844 ps
CPU time 45.4 seconds
Started Mar 07 01:01:40 PM PST 24
Finished Mar 07 01:02:26 PM PST 24
Peak memory 183396 kb
Host smart-489cd6d1-394f-4f8a-8a68-30af3a5daef0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696929952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2696929952
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.1962040126
Short name T155
Test name
Test status
Simulation time 68788825841 ps
CPU time 79.51 seconds
Started Mar 07 01:01:36 PM PST 24
Finished Mar 07 01:02:56 PM PST 24
Peak memory 191660 kb
Host smart-67be9ffd-1847-4bb4-9378-6486b4981bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962040126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1962040126
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.2932673472
Short name T394
Test name
Test status
Simulation time 164149422917 ps
CPU time 91.83 seconds
Started Mar 07 01:02:04 PM PST 24
Finished Mar 07 01:03:36 PM PST 24
Peak memory 183416 kb
Host smart-b80f5396-3c12-49ab-b031-e4615f297f09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932673472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2932673472
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.542269486
Short name T277
Test name
Test status
Simulation time 21962002259 ps
CPU time 18.4 seconds
Started Mar 07 01:02:13 PM PST 24
Finished Mar 07 01:02:31 PM PST 24
Peak memory 195292 kb
Host smart-13ce8fe4-0bff-4b31-bcb7-e9869c993ed5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542269486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.542269486
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.1822295827
Short name T330
Test name
Test status
Simulation time 91886148920 ps
CPU time 155.81 seconds
Started Mar 07 01:02:11 PM PST 24
Finished Mar 07 01:04:47 PM PST 24
Peak memory 191600 kb
Host smart-b499211f-44cf-4f93-a3c8-f8d668c7854e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822295827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1822295827
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.3952873802
Short name T231
Test name
Test status
Simulation time 22945137361 ps
CPU time 41.62 seconds
Started Mar 07 01:02:13 PM PST 24
Finished Mar 07 01:02:55 PM PST 24
Peak memory 183392 kb
Host smart-b9792b6d-44a0-42f5-8397-842cba8659e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952873802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3952873802
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3865565309
Short name T285
Test name
Test status
Simulation time 131227318948 ps
CPU time 150.56 seconds
Started Mar 07 01:02:12 PM PST 24
Finished Mar 07 01:04:42 PM PST 24
Peak memory 183388 kb
Host smart-37603e66-9610-45e2-82d4-3facb1233322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865565309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3865565309
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1438167286
Short name T193
Test name
Test status
Simulation time 278510389493 ps
CPU time 105.52 seconds
Started Mar 07 01:02:09 PM PST 24
Finished Mar 07 01:03:54 PM PST 24
Peak memory 191564 kb
Host smart-da39f3e4-9f6f-4b89-953b-9a24915ff74d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438167286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1438167286
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.3919002750
Short name T199
Test name
Test status
Simulation time 34466286021 ps
CPU time 63.16 seconds
Started Mar 07 01:02:11 PM PST 24
Finished Mar 07 01:03:15 PM PST 24
Peak memory 191576 kb
Host smart-96c4358d-6743-47c4-b544-dd95e6653586
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919002750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3919002750
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.646832696
Short name T224
Test name
Test status
Simulation time 1430115965339 ps
CPU time 668.4 seconds
Started Mar 07 01:02:13 PM PST 24
Finished Mar 07 01:13:21 PM PST 24
Peak memory 191616 kb
Host smart-1c36dede-b2c8-439d-89ce-8d5368639cf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646832696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.646832696
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.918632665
Short name T223
Test name
Test status
Simulation time 89109358759 ps
CPU time 67.7 seconds
Started Mar 07 01:02:12 PM PST 24
Finished Mar 07 01:03:19 PM PST 24
Peak memory 183392 kb
Host smart-e1843ac1-9b35-4331-8fee-196b886bf5b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918632665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.918632665
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2432604370
Short name T165
Test name
Test status
Simulation time 607253651642 ps
CPU time 234.9 seconds
Started Mar 07 01:00:59 PM PST 24
Finished Mar 07 01:04:55 PM PST 24
Peak memory 183384 kb
Host smart-ecc17194-0f24-4670-ba49-c377567691b6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432604370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2432604370
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.4001270894
Short name T374
Test name
Test status
Simulation time 143869550472 ps
CPU time 56.65 seconds
Started Mar 07 01:01:02 PM PST 24
Finished Mar 07 01:01:59 PM PST 24
Peak memory 183276 kb
Host smart-219e4f10-792a-4f96-870f-452202723190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001270894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.4001270894
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3627728205
Short name T237
Test name
Test status
Simulation time 75800945509 ps
CPU time 80.98 seconds
Started Mar 07 01:01:02 PM PST 24
Finished Mar 07 01:02:24 PM PST 24
Peak memory 183376 kb
Host smart-9f8933d4-2a02-4928-82f8-a9324d1b1131
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627728205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3627728205
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1890334319
Short name T360
Test name
Test status
Simulation time 269123120 ps
CPU time 0.86 seconds
Started Mar 07 01:01:21 PM PST 24
Finished Mar 07 01:01:23 PM PST 24
Peak memory 183096 kb
Host smart-634cef04-a13c-46c7-bb19-e4dbb7b5dca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890334319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1890334319
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.2582615839
Short name T19
Test name
Test status
Simulation time 341990287 ps
CPU time 0.9 seconds
Started Mar 07 01:01:14 PM PST 24
Finished Mar 07 01:01:15 PM PST 24
Peak memory 214680 kb
Host smart-34914413-1f91-4cf2-ad5d-e317c7f39988
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582615839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.2582615839
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.847586241
Short name T333
Test name
Test status
Simulation time 448474200793 ps
CPU time 441.52 seconds
Started Mar 07 01:01:29 PM PST 24
Finished Mar 07 01:08:56 PM PST 24
Peak memory 183392 kb
Host smart-01348915-4981-45b3-bad0-0df772f7edaa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847586241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.rv_timer_cfg_update_on_fly.847586241
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1685323385
Short name T367
Test name
Test status
Simulation time 57387863810 ps
CPU time 39.21 seconds
Started Mar 07 01:01:24 PM PST 24
Finished Mar 07 01:02:04 PM PST 24
Peak memory 183336 kb
Host smart-01922329-d5e0-4416-8e77-2cd80cc8f76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685323385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1685323385
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.895183874
Short name T107
Test name
Test status
Simulation time 125151496604 ps
CPU time 565.92 seconds
Started Mar 07 01:01:28 PM PST 24
Finished Mar 07 01:10:55 PM PST 24
Peak memory 191612 kb
Host smart-5f0d732f-51cf-4388-9455-020ff1c9ea79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895183874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.895183874
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.1635791407
Short name T378
Test name
Test status
Simulation time 308946150 ps
CPU time 0.88 seconds
Started Mar 07 01:01:36 PM PST 24
Finished Mar 07 01:01:36 PM PST 24
Peak memory 191468 kb
Host smart-3c9cd12f-1538-4eeb-bed5-8b93d121ed90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635791407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.1635791407
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.795060508
Short name T320
Test name
Test status
Simulation time 73273000794 ps
CPU time 132.4 seconds
Started Mar 07 01:01:27 PM PST 24
Finished Mar 07 01:03:40 PM PST 24
Peak memory 183448 kb
Host smart-762dbc2a-afbd-44b3-9830-bb6cd4959466
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795060508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.rv_timer_cfg_update_on_fly.795060508
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3679493514
Short name T7
Test name
Test status
Simulation time 368134601922 ps
CPU time 73.28 seconds
Started Mar 07 01:01:25 PM PST 24
Finished Mar 07 01:02:38 PM PST 24
Peak memory 183312 kb
Host smart-44eda261-290e-41d7-81bb-7c5c29af5677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679493514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3679493514
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.374507267
Short name T323
Test name
Test status
Simulation time 183326572596 ps
CPU time 66.92 seconds
Started Mar 07 01:01:30 PM PST 24
Finished Mar 07 01:02:37 PM PST 24
Peak memory 183496 kb
Host smart-44059820-bf98-455a-8120-31d274ee78e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374507267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.374507267
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.303908697
Short name T37
Test name
Test status
Simulation time 228645199177 ps
CPU time 549.01 seconds
Started Mar 07 01:01:42 PM PST 24
Finished Mar 07 01:10:52 PM PST 24
Peak memory 198084 kb
Host smart-b4fea763-4e86-4333-a33c-0e1bef3506c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303908697 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.303908697
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3358262131
Short name T152
Test name
Test status
Simulation time 10636950841 ps
CPU time 18.68 seconds
Started Mar 07 01:01:45 PM PST 24
Finished Mar 07 01:02:04 PM PST 24
Peak memory 183332 kb
Host smart-111ffcdb-dc97-419c-a4be-a81a8ca9653a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358262131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3358262131
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.2729819608
Short name T451
Test name
Test status
Simulation time 142322314867 ps
CPU time 192.32 seconds
Started Mar 07 01:01:32 PM PST 24
Finished Mar 07 01:04:45 PM PST 24
Peak memory 183376 kb
Host smart-a834752a-8082-46be-b792-fee669b74989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729819608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.2729819608
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.3633273046
Short name T175
Test name
Test status
Simulation time 391651795788 ps
CPU time 512.21 seconds
Started Mar 07 01:01:34 PM PST 24
Finished Mar 07 01:10:07 PM PST 24
Peak memory 191624 kb
Host smart-939adcf3-38ff-4c52-9dbe-cb0ebfa1c834
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633273046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3633273046
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.538873368
Short name T365
Test name
Test status
Simulation time 1054329120 ps
CPU time 1.38 seconds
Started Mar 07 01:01:37 PM PST 24
Finished Mar 07 01:01:38 PM PST 24
Peak memory 183068 kb
Host smart-dd29baa8-235d-4292-8eee-8a0f20d5b58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538873368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.538873368
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.3360026620
Short name T316
Test name
Test status
Simulation time 31813856021 ps
CPU time 59.88 seconds
Started Mar 07 01:01:28 PM PST 24
Finished Mar 07 01:02:29 PM PST 24
Peak memory 183468 kb
Host smart-4b9af820-f92b-41c1-80bd-65243ef3d3ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360026620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.3360026620
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.8819073
Short name T138
Test name
Test status
Simulation time 3244266633982 ps
CPU time 829.07 seconds
Started Mar 07 01:01:28 PM PST 24
Finished Mar 07 01:15:18 PM PST 24
Peak memory 183376 kb
Host smart-98bf2eac-5f34-4813-bd4d-d5c819af42f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8819073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
rv_timer_cfg_update_on_fly.8819073
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1386122645
Short name T361
Test name
Test status
Simulation time 35861454939 ps
CPU time 53.84 seconds
Started Mar 07 01:01:27 PM PST 24
Finished Mar 07 01:02:22 PM PST 24
Peak memory 183408 kb
Host smart-977785cf-30b2-46e7-af21-8a3abca2d98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386122645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1386122645
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.2362459689
Short name T293
Test name
Test status
Simulation time 102298343511 ps
CPU time 146.71 seconds
Started Mar 07 01:01:28 PM PST 24
Finished Mar 07 01:03:56 PM PST 24
Peak memory 192784 kb
Host smart-2794e998-6a0c-4fdb-a595-fde28ffd5472
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362459689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2362459689
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3908167947
Short name T444
Test name
Test status
Simulation time 39854446608 ps
CPU time 31.31 seconds
Started Mar 07 01:01:35 PM PST 24
Finished Mar 07 01:02:06 PM PST 24
Peak memory 191680 kb
Host smart-9ca79663-68de-4033-a547-d3deaabaef12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908167947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3908167947
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2311182739
Short name T158
Test name
Test status
Simulation time 836919343856 ps
CPU time 623.63 seconds
Started Mar 07 01:01:36 PM PST 24
Finished Mar 07 01:12:00 PM PST 24
Peak memory 195684 kb
Host smart-91cd2991-af1a-47a7-ab3c-8b6d4a82a66b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311182739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2311182739
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.124957678
Short name T306
Test name
Test status
Simulation time 306582362448 ps
CPU time 471.85 seconds
Started Mar 07 01:01:36 PM PST 24
Finished Mar 07 01:09:28 PM PST 24
Peak memory 183412 kb
Host smart-4ef5575f-d0fc-4ef2-b7b2-7ee86cc24a43
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124957678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.rv_timer_cfg_update_on_fly.124957678
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.125120802
Short name T370
Test name
Test status
Simulation time 40724858426 ps
CPU time 58.14 seconds
Started Mar 07 01:01:30 PM PST 24
Finished Mar 07 01:02:28 PM PST 24
Peak memory 183308 kb
Host smart-f7a319f5-0ad3-4e19-9cd3-1462383752da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125120802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.125120802
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1961492198
Short name T124
Test name
Test status
Simulation time 385095139393 ps
CPU time 144.13 seconds
Started Mar 07 01:01:32 PM PST 24
Finished Mar 07 01:03:57 PM PST 24
Peak memory 195140 kb
Host smart-2820c2fe-556f-4e0b-b08c-640d9b664bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961492198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1961492198
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.4030626128
Short name T62
Test name
Test status
Simulation time 700507248037 ps
CPU time 304.87 seconds
Started Mar 07 01:01:31 PM PST 24
Finished Mar 07 01:06:36 PM PST 24
Peak memory 195808 kb
Host smart-36dfade4-7d18-43ea-be2d-cf254cb2c7de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030626128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.4030626128
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.1630252577
Short name T279
Test name
Test status
Simulation time 135377674257 ps
CPU time 260.18 seconds
Started Mar 07 01:01:37 PM PST 24
Finished Mar 07 01:05:58 PM PST 24
Peak memory 183412 kb
Host smart-10bac7cd-e72f-4489-843b-f4e464763177
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630252577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.1630252577
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.1320335768
Short name T372
Test name
Test status
Simulation time 319770395012 ps
CPU time 202.62 seconds
Started Mar 07 01:01:41 PM PST 24
Finished Mar 07 01:05:04 PM PST 24
Peak memory 183364 kb
Host smart-25fdb5d0-a68b-4783-be16-1951a80e2f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320335768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1320335768
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.1260229803
Short name T204
Test name
Test status
Simulation time 166052087189 ps
CPU time 918.73 seconds
Started Mar 07 01:01:30 PM PST 24
Finished Mar 07 01:16:49 PM PST 24
Peak memory 191596 kb
Host smart-a8a41193-a546-4284-bf0c-692b31c56bf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260229803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1260229803
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3821008071
Short name T108
Test name
Test status
Simulation time 1200944426826 ps
CPU time 626.33 seconds
Started Mar 07 01:01:18 PM PST 24
Finished Mar 07 01:11:44 PM PST 24
Peak memory 191572 kb
Host smart-87c09a39-e591-4d5b-8304-099066d13f3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821008071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3821008071
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1381169684
Short name T334
Test name
Test status
Simulation time 339308145985 ps
CPU time 403.73 seconds
Started Mar 07 01:01:26 PM PST 24
Finished Mar 07 01:08:10 PM PST 24
Peak memory 183344 kb
Host smart-d89bd83e-93a0-43d8-b011-aa4d62923dfb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381169684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.1381169684
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2917263157
Short name T447
Test name
Test status
Simulation time 190703033710 ps
CPU time 217.37 seconds
Started Mar 07 01:01:33 PM PST 24
Finished Mar 07 01:05:11 PM PST 24
Peak memory 183404 kb
Host smart-b94a3c2b-dd66-40b2-80d5-cd4f3d2f0118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917263157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2917263157
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.1295209327
Short name T448
Test name
Test status
Simulation time 93148057025 ps
CPU time 330.52 seconds
Started Mar 07 01:01:28 PM PST 24
Finished Mar 07 01:06:59 PM PST 24
Peak memory 183396 kb
Host smart-fe75772f-d395-403d-89b8-247ccfcf51a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295209327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1295209327
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.4188096297
Short name T179
Test name
Test status
Simulation time 121678235708 ps
CPU time 27.66 seconds
Started Mar 07 01:01:37 PM PST 24
Finished Mar 07 01:02:05 PM PST 24
Peak memory 194876 kb
Host smart-8f08f013-6aa6-4b50-8633-789066103a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188096297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.4188096297
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.506102749
Short name T39
Test name
Test status
Simulation time 78987551721 ps
CPU time 601.72 seconds
Started Mar 07 01:01:35 PM PST 24
Finished Mar 07 01:11:36 PM PST 24
Peak memory 206876 kb
Host smart-b1017f30-880e-4276-96e2-564e2dd9c492
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506102749 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.506102749
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.141155711
Short name T353
Test name
Test status
Simulation time 710465367117 ps
CPU time 1170.12 seconds
Started Mar 07 01:01:49 PM PST 24
Finished Mar 07 01:21:20 PM PST 24
Peak memory 183372 kb
Host smart-e5c21ad8-7ef4-4d07-8132-f090d4a4ac85
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141155711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.141155711
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.798812083
Short name T401
Test name
Test status
Simulation time 144385254138 ps
CPU time 195.33 seconds
Started Mar 07 01:01:36 PM PST 24
Finished Mar 07 01:04:52 PM PST 24
Peak memory 183416 kb
Host smart-51b83fbb-1607-44a2-bac7-e682f2dd8970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798812083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.798812083
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3637963676
Short name T287
Test name
Test status
Simulation time 65385089797 ps
CPU time 195.19 seconds
Started Mar 07 01:01:42 PM PST 24
Finished Mar 07 01:04:57 PM PST 24
Peak memory 183312 kb
Host smart-3fa6efdf-8070-4e66-bf8b-0559668251ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637963676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3637963676
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.3695373504
Short name T63
Test name
Test status
Simulation time 33874205470 ps
CPU time 88.36 seconds
Started Mar 07 01:01:30 PM PST 24
Finished Mar 07 01:02:59 PM PST 24
Peak memory 194772 kb
Host smart-cc251740-3583-46f3-9dc6-a5c4c31949d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695373504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.3695373504
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1867335906
Short name T66
Test name
Test status
Simulation time 1056064678 ps
CPU time 1.78 seconds
Started Mar 07 01:01:41 PM PST 24
Finished Mar 07 01:01:43 PM PST 24
Peak memory 182976 kb
Host smart-04d16181-32a1-40b2-a39c-0f5f0f328914
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867335906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1867335906
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_random.1159682210
Short name T289
Test name
Test status
Simulation time 121896231957 ps
CPU time 129.17 seconds
Started Mar 07 01:01:41 PM PST 24
Finished Mar 07 01:03:50 PM PST 24
Peak memory 183376 kb
Host smart-f102f423-9853-4785-9ab7-e6bbcf59126b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159682210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1159682210
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2108478344
Short name T371
Test name
Test status
Simulation time 128373446 ps
CPU time 0.65 seconds
Started Mar 07 01:01:45 PM PST 24
Finished Mar 07 01:01:45 PM PST 24
Peak memory 183072 kb
Host smart-4a3f2c76-8636-48de-be1a-3f5b90a883ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108478344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2108478344
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.999126639
Short name T338
Test name
Test status
Simulation time 404475262157 ps
CPU time 436.4 seconds
Started Mar 07 01:01:41 PM PST 24
Finished Mar 07 01:08:57 PM PST 24
Peak memory 183376 kb
Host smart-02919022-65ab-480d-8311-eb7a50cefbcd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999126639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.rv_timer_cfg_update_on_fly.999126639
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.4186675233
Short name T402
Test name
Test status
Simulation time 150859179181 ps
CPU time 105.56 seconds
Started Mar 07 01:01:34 PM PST 24
Finished Mar 07 01:03:19 PM PST 24
Peak memory 183360 kb
Host smart-bb8fd143-dbcb-4880-9262-0684febf5bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186675233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.4186675233
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.1225411553
Short name T283
Test name
Test status
Simulation time 231195649801 ps
CPU time 248.42 seconds
Started Mar 07 01:01:39 PM PST 24
Finished Mar 07 01:05:47 PM PST 24
Peak memory 191588 kb
Host smart-0f85ee53-64a1-4f2b-b140-73e92757da70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225411553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1225411553
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.3368627425
Short name T419
Test name
Test status
Simulation time 38645167828 ps
CPU time 68.09 seconds
Started Mar 07 01:01:38 PM PST 24
Finished Mar 07 01:02:46 PM PST 24
Peak memory 191656 kb
Host smart-240c9b61-0373-4182-b88d-b9cecc137df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368627425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3368627425
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.299150823
Short name T61
Test name
Test status
Simulation time 1922099592593 ps
CPU time 814.47 seconds
Started Mar 07 01:01:40 PM PST 24
Finished Mar 07 01:15:15 PM PST 24
Peak memory 195968 kb
Host smart-2c35fa12-a277-484e-aeb4-715612890097
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299150823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.
299150823
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.556202011
Short name T440
Test name
Test status
Simulation time 26310610205 ps
CPU time 39.88 seconds
Started Mar 07 01:01:10 PM PST 24
Finished Mar 07 01:01:50 PM PST 24
Peak memory 183364 kb
Host smart-c65995c1-9dbe-4593-9c36-11fcc98108fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556202011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.556202011
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.670867945
Short name T166
Test name
Test status
Simulation time 168365564108 ps
CPU time 1850.07 seconds
Started Mar 07 01:01:00 PM PST 24
Finished Mar 07 01:31:51 PM PST 24
Peak memory 191516 kb
Host smart-660c465a-af85-47c3-963a-3aa031c71774
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670867945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.670867945
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3324851163
Short name T229
Test name
Test status
Simulation time 36075211189 ps
CPU time 141.32 seconds
Started Mar 07 01:01:02 PM PST 24
Finished Mar 07 01:03:29 PM PST 24
Peak memory 191560 kb
Host smart-9c005664-6fa5-44bf-9728-967ef2585d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324851163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3324851163
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.1076734967
Short name T17
Test name
Test status
Simulation time 214428736 ps
CPU time 0.78 seconds
Started Mar 07 01:01:21 PM PST 24
Finished Mar 07 01:01:23 PM PST 24
Peak memory 213492 kb
Host smart-52727baa-0b62-4b0b-874a-991028e40c5d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076734967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1076734967
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2622498317
Short name T72
Test name
Test status
Simulation time 35667035166 ps
CPU time 30.74 seconds
Started Mar 07 01:01:36 PM PST 24
Finished Mar 07 01:02:07 PM PST 24
Peak memory 183364 kb
Host smart-cabee1f9-4eb6-4cf7-a4c8-2d44af27971e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622498317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2622498317
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2456762246
Short name T115
Test name
Test status
Simulation time 142983658509 ps
CPU time 163.56 seconds
Started Mar 07 01:01:45 PM PST 24
Finished Mar 07 01:04:29 PM PST 24
Peak memory 191576 kb
Host smart-f0695592-ccec-4be8-9878-8decf0cd9919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456762246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2456762246
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1597525571
Short name T325
Test name
Test status
Simulation time 252770151773 ps
CPU time 404.26 seconds
Started Mar 07 01:01:46 PM PST 24
Finished Mar 07 01:08:30 PM PST 24
Peak memory 194032 kb
Host smart-17103897-d671-478b-ac0b-edd39e6b0aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597525571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1597525571
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.2290171124
Short name T382
Test name
Test status
Simulation time 181118480835 ps
CPU time 53.75 seconds
Started Mar 07 01:01:43 PM PST 24
Finished Mar 07 01:02:37 PM PST 24
Peak memory 183272 kb
Host smart-2de77703-35ab-4a92-8438-bb7c43fb12ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290171124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.2290171124
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.2806146591
Short name T16
Test name
Test status
Simulation time 31149295880 ps
CPU time 316.36 seconds
Started Mar 07 01:01:50 PM PST 24
Finished Mar 07 01:07:07 PM PST 24
Peak memory 198080 kb
Host smart-5e9267b5-cb35-4752-b99a-f494a465cf53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806146591 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.2806146591
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1144364242
Short name T317
Test name
Test status
Simulation time 184510364702 ps
CPU time 81.91 seconds
Started Mar 07 01:01:42 PM PST 24
Finished Mar 07 01:03:09 PM PST 24
Peak memory 183360 kb
Host smart-487d8d51-6f24-460b-b19c-9192900c2e4d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144364242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1144364242
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3106995311
Short name T411
Test name
Test status
Simulation time 320917771435 ps
CPU time 133.16 seconds
Started Mar 07 01:01:43 PM PST 24
Finished Mar 07 01:03:56 PM PST 24
Peak memory 183392 kb
Host smart-0781a4f2-d762-42b1-a720-fa99f76b2bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106995311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3106995311
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.905107464
Short name T188
Test name
Test status
Simulation time 344573399364 ps
CPU time 429.63 seconds
Started Mar 07 01:01:38 PM PST 24
Finished Mar 07 01:08:48 PM PST 24
Peak memory 183332 kb
Host smart-1f993659-19a1-4490-bb69-c6aec8605b95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905107464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.905107464
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.892677988
Short name T322
Test name
Test status
Simulation time 285764394208 ps
CPU time 198.76 seconds
Started Mar 07 01:01:38 PM PST 24
Finished Mar 07 01:04:57 PM PST 24
Peak memory 191484 kb
Host smart-a4a345aa-bfdc-4ea9-b200-91c58c8d7348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892677988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.892677988
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1748900259
Short name T355
Test name
Test status
Simulation time 3074638913 ps
CPU time 5.94 seconds
Started Mar 07 01:01:34 PM PST 24
Finished Mar 07 01:01:40 PM PST 24
Peak memory 183360 kb
Host smart-14178323-3851-4545-9da6-1871f0f5ef0f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748900259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.1748900259
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.4005648530
Short name T426
Test name
Test status
Simulation time 178789714104 ps
CPU time 62.52 seconds
Started Mar 07 01:01:48 PM PST 24
Finished Mar 07 01:02:51 PM PST 24
Peak memory 183364 kb
Host smart-e3f1c683-4ef8-49fa-96f1-ae1dc47739eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005648530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.4005648530
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1457914471
Short name T453
Test name
Test status
Simulation time 5777594083 ps
CPU time 8.78 seconds
Started Mar 07 01:01:31 PM PST 24
Finished Mar 07 01:01:40 PM PST 24
Peak memory 183224 kb
Host smart-f3ccd898-393c-4d0f-8055-7367fa06a783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457914471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1457914471
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2807104492
Short name T1
Test name
Test status
Simulation time 557067965457 ps
CPU time 495.33 seconds
Started Mar 07 01:01:42 PM PST 24
Finished Mar 07 01:09:58 PM PST 24
Peak memory 183420 kb
Host smart-d8dd99cd-ea87-43bf-8cd8-189876b19d00
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807104492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2807104492
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.602729792
Short name T366
Test name
Test status
Simulation time 276211134072 ps
CPU time 207.93 seconds
Started Mar 07 01:01:39 PM PST 24
Finished Mar 07 01:05:07 PM PST 24
Peak memory 183384 kb
Host smart-bbb7f7c5-7d19-4581-8cac-8b390e279c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602729792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.602729792
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.838126615
Short name T337
Test name
Test status
Simulation time 36927747865 ps
CPU time 62.74 seconds
Started Mar 07 01:01:36 PM PST 24
Finished Mar 07 01:02:39 PM PST 24
Peak memory 183380 kb
Host smart-590f1a7d-c49d-4609-8541-fa49c7b88233
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838126615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.838126615
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.179517673
Short name T147
Test name
Test status
Simulation time 129949793000 ps
CPU time 574.35 seconds
Started Mar 07 01:01:37 PM PST 24
Finished Mar 07 01:11:12 PM PST 24
Peak memory 191636 kb
Host smart-e7e755ca-13d7-4563-b3bb-6b4f6b0e7fe8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179517673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.
179517673
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1343886235
Short name T49
Test name
Test status
Simulation time 168774410957 ps
CPU time 72.75 seconds
Started Mar 07 01:01:44 PM PST 24
Finished Mar 07 01:02:57 PM PST 24
Peak memory 183400 kb
Host smart-0733af85-7d1f-48ae-a157-b38d07060727
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343886235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.1343886235
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.230749676
Short name T438
Test name
Test status
Simulation time 701147295618 ps
CPU time 308.66 seconds
Started Mar 07 01:01:36 PM PST 24
Finished Mar 07 01:06:45 PM PST 24
Peak memory 183444 kb
Host smart-3510f06d-20e1-4ca7-9f84-7fc5d3e08256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230749676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.230749676
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.489731957
Short name T307
Test name
Test status
Simulation time 267195033072 ps
CPU time 101.49 seconds
Started Mar 07 01:01:42 PM PST 24
Finished Mar 07 01:03:24 PM PST 24
Peak memory 191580 kb
Host smart-8a92fab0-143a-45c3-b481-86afea12612f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489731957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.489731957
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3262833736
Short name T442
Test name
Test status
Simulation time 80748936 ps
CPU time 0.71 seconds
Started Mar 07 01:01:39 PM PST 24
Finished Mar 07 01:01:40 PM PST 24
Peak memory 183204 kb
Host smart-ba5e422d-8197-4278-89f5-735afb402699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262833736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3262833736
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3692411381
Short name T364
Test name
Test status
Simulation time 203068136028 ps
CPU time 243.94 seconds
Started Mar 07 01:01:44 PM PST 24
Finished Mar 07 01:05:48 PM PST 24
Peak memory 191556 kb
Host smart-9592d746-93ee-481f-860e-b70f54746734
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692411381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3692411381
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3351329114
Short name T423
Test name
Test status
Simulation time 157572099726 ps
CPU time 117.4 seconds
Started Mar 07 01:01:36 PM PST 24
Finished Mar 07 01:03:34 PM PST 24
Peak memory 183432 kb
Host smart-20063575-f84c-47af-9170-9e84a92b5b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351329114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3351329114
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.488789348
Short name T194
Test name
Test status
Simulation time 1387851703496 ps
CPU time 968.54 seconds
Started Mar 07 01:01:41 PM PST 24
Finished Mar 07 01:17:50 PM PST 24
Peak memory 191572 kb
Host smart-0a457ce9-0823-4c27-ab6a-5d52d713f17e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488789348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.488789348
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.2321789060
Short name T238
Test name
Test status
Simulation time 56339374639 ps
CPU time 157.66 seconds
Started Mar 07 01:01:43 PM PST 24
Finished Mar 07 01:04:21 PM PST 24
Peak memory 191580 kb
Host smart-d9889713-bdb2-4a6c-8f76-1e99e4ccfe27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321789060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2321789060
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.144581944
Short name T435
Test name
Test status
Simulation time 172688970686 ps
CPU time 296.07 seconds
Started Mar 07 01:01:38 PM PST 24
Finished Mar 07 01:06:34 PM PST 24
Peak memory 183392 kb
Host smart-2bc8013c-8eb7-4264-af4d-ffb25d4b6b8c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144581944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.rv_timer_cfg_update_on_fly.144581944
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1257575427
Short name T449
Test name
Test status
Simulation time 224421380046 ps
CPU time 157.86 seconds
Started Mar 07 01:01:45 PM PST 24
Finished Mar 07 01:04:23 PM PST 24
Peak memory 183344 kb
Host smart-5e18454a-62f4-45a1-be7c-85aa5058ad6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257575427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1257575427
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.1228179119
Short name T403
Test name
Test status
Simulation time 215375463602 ps
CPU time 385.81 seconds
Started Mar 07 01:01:43 PM PST 24
Finished Mar 07 01:08:08 PM PST 24
Peak memory 191692 kb
Host smart-4c270f95-2a46-4ac6-95b8-e5e48df4f96b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228179119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1228179119
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3059330381
Short name T432
Test name
Test status
Simulation time 1126152367 ps
CPU time 1.06 seconds
Started Mar 07 01:01:56 PM PST 24
Finished Mar 07 01:01:57 PM PST 24
Peak memory 183028 kb
Host smart-fae90032-8564-417f-91b1-27d7aade1758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059330381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3059330381
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.2119727861
Short name T207
Test name
Test status
Simulation time 219811338612 ps
CPU time 182.02 seconds
Started Mar 07 01:01:58 PM PST 24
Finished Mar 07 01:05:01 PM PST 24
Peak memory 183448 kb
Host smart-ed087e59-f72d-4e21-99a8-f64d28ba16df
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119727861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.2119727861
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2886145960
Short name T386
Test name
Test status
Simulation time 78690410999 ps
CPU time 63.59 seconds
Started Mar 07 01:01:54 PM PST 24
Finished Mar 07 01:02:58 PM PST 24
Peak memory 183340 kb
Host smart-8fe47b75-c35e-4e4e-a5f4-3bd0517ab0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886145960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2886145960
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.634593650
Short name T139
Test name
Test status
Simulation time 44746110579 ps
CPU time 18.14 seconds
Started Mar 07 01:01:48 PM PST 24
Finished Mar 07 01:02:06 PM PST 24
Peak memory 183116 kb
Host smart-b3d57199-b221-4e84-98e7-8687fa494dc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634593650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.634593650
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.154821802
Short name T345
Test name
Test status
Simulation time 128601399613 ps
CPU time 40.81 seconds
Started Mar 07 01:01:46 PM PST 24
Finished Mar 07 01:02:27 PM PST 24
Peak memory 191564 kb
Host smart-5086b373-1df1-4898-abf2-a936b989d715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154821802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.154821802
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.1361900575
Short name T278
Test name
Test status
Simulation time 2029856769014 ps
CPU time 1268.38 seconds
Started Mar 07 01:01:52 PM PST 24
Finished Mar 07 01:23:01 PM PST 24
Peak memory 191436 kb
Host smart-1f532ab0-8775-4c34-91c0-297f7f29590c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361900575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.1361900575
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.2170149999
Short name T342
Test name
Test status
Simulation time 33900967489 ps
CPU time 57.19 seconds
Started Mar 07 01:01:54 PM PST 24
Finished Mar 07 01:02:51 PM PST 24
Peak memory 183432 kb
Host smart-d687ff49-6715-42b7-ab66-45f308fcae47
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170149999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.2170149999
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.327379730
Short name T383
Test name
Test status
Simulation time 630087526686 ps
CPU time 236.98 seconds
Started Mar 07 01:01:50 PM PST 24
Finished Mar 07 01:05:47 PM PST 24
Peak memory 183496 kb
Host smart-16d43aaf-d725-48f5-b5b4-bb7df71f27a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327379730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.327379730
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.3950136964
Short name T144
Test name
Test status
Simulation time 110013299910 ps
CPU time 200.95 seconds
Started Mar 07 01:01:45 PM PST 24
Finished Mar 07 01:05:06 PM PST 24
Peak memory 191608 kb
Host smart-226d4bfa-6fa2-4349-8cb3-0185aad5cdc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950136964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3950136964
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.3955039623
Short name T133
Test name
Test status
Simulation time 62473868045 ps
CPU time 275.48 seconds
Started Mar 07 01:01:56 PM PST 24
Finished Mar 07 01:06:32 PM PST 24
Peak memory 194544 kb
Host smart-327a3fd0-5012-4d28-8db7-496f41ff09c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955039623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.3955039623
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.531747161
Short name T110
Test name
Test status
Simulation time 717190224279 ps
CPU time 545.02 seconds
Started Mar 07 01:01:42 PM PST 24
Finished Mar 07 01:10:47 PM PST 24
Peak memory 191604 kb
Host smart-51cde27f-7989-44f2-a8af-60e35179d9ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531747161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.
531747161
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.2165685778
Short name T369
Test name
Test status
Simulation time 259913338378 ps
CPU time 172.45 seconds
Started Mar 07 01:01:44 PM PST 24
Finished Mar 07 01:04:37 PM PST 24
Peak memory 183320 kb
Host smart-f18f4fd1-27b7-4ab7-adb4-38d4e39e1562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165685778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.2165685778
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3776156122
Short name T76
Test name
Test status
Simulation time 189449971 ps
CPU time 0.61 seconds
Started Mar 07 01:01:39 PM PST 24
Finished Mar 07 01:01:40 PM PST 24
Peak memory 183100 kb
Host smart-bcc4e873-1a1d-4e4c-90b9-760473ea2686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776156122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3776156122
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1654828343
Short name T70
Test name
Test status
Simulation time 299955155461 ps
CPU time 166.55 seconds
Started Mar 07 01:01:49 PM PST 24
Finished Mar 07 01:04:36 PM PST 24
Peak memory 191592 kb
Host smart-dda1bb80-9b20-41e5-97a8-820ed839bf75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654828343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1654828343
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3892503243
Short name T119
Test name
Test status
Simulation time 885349009343 ps
CPU time 333.04 seconds
Started Mar 07 01:01:25 PM PST 24
Finished Mar 07 01:06:59 PM PST 24
Peak memory 183404 kb
Host smart-6e72a433-c511-40b6-ad16-f379ca2bb7ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892503243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3892503243
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2010400299
Short name T368
Test name
Test status
Simulation time 92612870952 ps
CPU time 69.28 seconds
Started Mar 07 01:01:17 PM PST 24
Finished Mar 07 01:02:26 PM PST 24
Peak memory 183360 kb
Host smart-ec04b4f3-4ce2-43cd-a424-41d3095088ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010400299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2010400299
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.3030571102
Short name T192
Test name
Test status
Simulation time 345494144978 ps
CPU time 1037.81 seconds
Started Mar 07 01:01:03 PM PST 24
Finished Mar 07 01:18:21 PM PST 24
Peak memory 194872 kb
Host smart-b486a367-5ad1-4699-a38f-3ac7b2dfffa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030571102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3030571102
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2190981087
Short name T314
Test name
Test status
Simulation time 212162560003 ps
CPU time 90.56 seconds
Started Mar 07 01:01:25 PM PST 24
Finished Mar 07 01:03:01 PM PST 24
Peak memory 191584 kb
Host smart-bb71aef3-63bc-404e-a565-e74090b2cf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190981087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2190981087
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2786656275
Short name T18
Test name
Test status
Simulation time 139803283 ps
CPU time 0.75 seconds
Started Mar 07 01:01:05 PM PST 24
Finished Mar 07 01:01:06 PM PST 24
Peak memory 213532 kb
Host smart-7d447381-98f2-4764-91b4-c6df237f2815
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786656275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2786656275
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.3449677016
Short name T42
Test name
Test status
Simulation time 158111543252 ps
CPU time 689.19 seconds
Started Mar 07 01:01:03 PM PST 24
Finished Mar 07 01:12:33 PM PST 24
Peak memory 210568 kb
Host smart-32860822-61e9-4998-9bd1-329e578146eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449677016 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.3449677016
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.577679490
Short name T220
Test name
Test status
Simulation time 338987409572 ps
CPU time 187.95 seconds
Started Mar 07 01:01:38 PM PST 24
Finished Mar 07 01:04:46 PM PST 24
Peak memory 183400 kb
Host smart-e653e42b-b084-456b-90f5-9233c79d1d65
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577679490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.rv_timer_cfg_update_on_fly.577679490
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2181896180
Short name T400
Test name
Test status
Simulation time 138729964971 ps
CPU time 215.93 seconds
Started Mar 07 01:01:48 PM PST 24
Finished Mar 07 01:05:24 PM PST 24
Peak memory 183388 kb
Host smart-05087436-2bec-4882-9540-212740f7fe95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181896180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2181896180
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.2228293590
Short name T328
Test name
Test status
Simulation time 148572250180 ps
CPU time 131.42 seconds
Started Mar 07 01:01:56 PM PST 24
Finished Mar 07 01:04:08 PM PST 24
Peak memory 191508 kb
Host smart-9f9cb8fa-80b8-49c1-be05-626b69b168e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228293590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.2228293590
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.783964414
Short name T329
Test name
Test status
Simulation time 1153326592524 ps
CPU time 944.92 seconds
Started Mar 07 01:01:47 PM PST 24
Finished Mar 07 01:17:32 PM PST 24
Peak memory 191584 kb
Host smart-90711a96-3afc-4cef-8c21-d79088f70bb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783964414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.
783964414
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3500331885
Short name T357
Test name
Test status
Simulation time 530350149423 ps
CPU time 305.8 seconds
Started Mar 07 01:01:50 PM PST 24
Finished Mar 07 01:06:55 PM PST 24
Peak memory 183328 kb
Host smart-c725f2ef-7471-4e89-9db8-56ac723995f9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500331885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3500331885
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.499532939
Short name T398
Test name
Test status
Simulation time 382379087560 ps
CPU time 146.89 seconds
Started Mar 07 01:01:43 PM PST 24
Finished Mar 07 01:04:10 PM PST 24
Peak memory 183296 kb
Host smart-44bcd4a6-8089-408b-be8b-a00547384557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499532939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.499532939
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2481057817
Short name T445
Test name
Test status
Simulation time 3272572065 ps
CPU time 5.19 seconds
Started Mar 07 01:01:45 PM PST 24
Finished Mar 07 01:01:51 PM PST 24
Peak memory 183216 kb
Host smart-774dadbf-e4e2-4ec6-8648-1de89706d410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481057817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2481057817
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2497048990
Short name T157
Test name
Test status
Simulation time 214993612533 ps
CPU time 402.11 seconds
Started Mar 07 01:01:41 PM PST 24
Finished Mar 07 01:08:24 PM PST 24
Peak memory 183364 kb
Host smart-137e4e99-83ad-40d1-9649-9712cc075ea7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497048990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2497048990
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1843853439
Short name T380
Test name
Test status
Simulation time 602430487763 ps
CPU time 244.62 seconds
Started Mar 07 01:01:42 PM PST 24
Finished Mar 07 01:05:47 PM PST 24
Peak memory 183416 kb
Host smart-b988c36f-7cd2-4494-8cf1-aa4a2f01b83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843853439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1843853439
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.2325654675
Short name T302
Test name
Test status
Simulation time 32740884701 ps
CPU time 48.31 seconds
Started Mar 07 01:01:47 PM PST 24
Finished Mar 07 01:02:35 PM PST 24
Peak memory 183360 kb
Host smart-e43e7bf3-c81b-4edc-bf8f-481924457206
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325654675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2325654675
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.3793079413
Short name T417
Test name
Test status
Simulation time 158311249308 ps
CPU time 61.83 seconds
Started Mar 07 01:01:50 PM PST 24
Finished Mar 07 01:02:52 PM PST 24
Peak memory 191600 kb
Host smart-de06edf3-bd29-4b82-9fe0-9fff4094c1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793079413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.3793079413
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.2823518865
Short name T59
Test name
Test status
Simulation time 1689187682875 ps
CPU time 825.51 seconds
Started Mar 07 01:01:45 PM PST 24
Finished Mar 07 01:15:31 PM PST 24
Peak memory 191620 kb
Host smart-05f801af-b29e-4af2-be62-77a8c90e0ace
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823518865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.2823518865
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.942637414
Short name T305
Test name
Test status
Simulation time 260019160358 ps
CPU time 146.82 seconds
Started Mar 07 01:01:46 PM PST 24
Finished Mar 07 01:04:13 PM PST 24
Peak memory 183356 kb
Host smart-1eaf7d6b-1acc-4d7f-8bc5-1727f8a613da
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942637414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.rv_timer_cfg_update_on_fly.942637414
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.1513750185
Short name T373
Test name
Test status
Simulation time 136968459409 ps
CPU time 195.23 seconds
Started Mar 07 01:01:48 PM PST 24
Finished Mar 07 01:05:04 PM PST 24
Peak memory 183404 kb
Host smart-1de9bf86-4a24-488c-93f4-1440c411a416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513750185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1513750185
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.2122153624
Short name T354
Test name
Test status
Simulation time 129524416505 ps
CPU time 235.14 seconds
Started Mar 07 01:01:40 PM PST 24
Finished Mar 07 01:05:35 PM PST 24
Peak memory 191620 kb
Host smart-7a00eb62-5d1c-48bc-8f00-b6b4a3e587e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122153624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2122153624
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.1151590657
Short name T446
Test name
Test status
Simulation time 2601201873 ps
CPU time 5 seconds
Started Mar 07 01:01:46 PM PST 24
Finished Mar 07 01:01:51 PM PST 24
Peak memory 183408 kb
Host smart-fcfd3993-c586-4a8b-806e-5e1a0a9be8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151590657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1151590657
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3583161567
Short name T387
Test name
Test status
Simulation time 233148161812 ps
CPU time 311.94 seconds
Started Mar 07 01:01:46 PM PST 24
Finished Mar 07 01:06:58 PM PST 24
Peak memory 183356 kb
Host smart-d5f59c0c-1bca-444a-bcce-4d662cd846fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583161567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3583161567
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.637117205
Short name T308
Test name
Test status
Simulation time 22703885028 ps
CPU time 62.64 seconds
Started Mar 07 01:01:56 PM PST 24
Finished Mar 07 01:02:59 PM PST 24
Peak memory 183332 kb
Host smart-c3c32d6f-af44-42a4-be66-aed8fea972f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637117205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.637117205
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.2704342364
Short name T15
Test name
Test status
Simulation time 58366226078 ps
CPU time 631.74 seconds
Started Mar 07 01:01:46 PM PST 24
Finished Mar 07 01:12:18 PM PST 24
Peak memory 209008 kb
Host smart-ac353849-9062-42d6-a835-d391ba130cea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704342364 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.2704342364
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1450463800
Short name T182
Test name
Test status
Simulation time 98932387326 ps
CPU time 91.9 seconds
Started Mar 07 01:01:50 PM PST 24
Finished Mar 07 01:03:22 PM PST 24
Peak memory 183408 kb
Host smart-04218a65-83cf-43f9-b7c0-b61a63bc2a43
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450463800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1450463800
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1783676958
Short name T389
Test name
Test status
Simulation time 66688178164 ps
CPU time 53.47 seconds
Started Mar 07 01:01:44 PM PST 24
Finished Mar 07 01:02:37 PM PST 24
Peak memory 183432 kb
Host smart-f5158a7d-8b1a-43aa-bcd2-4f379fd99028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783676958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1783676958
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.3356623454
Short name T117
Test name
Test status
Simulation time 110915940767 ps
CPU time 342.24 seconds
Started Mar 07 01:01:49 PM PST 24
Finished Mar 07 01:07:32 PM PST 24
Peak memory 191564 kb
Host smart-bbadf983-bc21-48c0-8562-b96fa8c39e17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356623454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3356623454
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3570730104
Short name T418
Test name
Test status
Simulation time 82628307186 ps
CPU time 445.65 seconds
Started Mar 07 01:02:00 PM PST 24
Finished Mar 07 01:09:26 PM PST 24
Peak memory 191604 kb
Host smart-3d1da590-bbc6-4f2e-a2b8-17188951ed42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570730104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3570730104
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.1350803940
Short name T422
Test name
Test status
Simulation time 782732915502 ps
CPU time 325.43 seconds
Started Mar 07 01:01:47 PM PST 24
Finished Mar 07 01:07:12 PM PST 24
Peak memory 194156 kb
Host smart-b577befe-87f8-4793-aa45-a3d8f3c5c47d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350803940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.1350803940
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1302343000
Short name T111
Test name
Test status
Simulation time 570453933908 ps
CPU time 491.09 seconds
Started Mar 07 01:01:51 PM PST 24
Finished Mar 07 01:10:07 PM PST 24
Peak memory 183420 kb
Host smart-b6747c2e-6ae9-468c-a32d-ee0d2fdbaf21
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302343000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1302343000
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3081664911
Short name T410
Test name
Test status
Simulation time 33268692787 ps
CPU time 53.32 seconds
Started Mar 07 01:01:45 PM PST 24
Finished Mar 07 01:02:38 PM PST 24
Peak memory 183412 kb
Host smart-cd8410a7-b686-4c6e-8170-11cf2bf98aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081664911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3081664911
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.1364900929
Short name T413
Test name
Test status
Simulation time 275597110603 ps
CPU time 123.82 seconds
Started Mar 07 01:01:59 PM PST 24
Finished Mar 07 01:04:03 PM PST 24
Peak memory 191584 kb
Host smart-68dab1d3-fc61-4450-88d5-3d58be42bc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364900929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1364900929
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2412190602
Short name T109
Test name
Test status
Simulation time 8728791649 ps
CPU time 14.75 seconds
Started Mar 07 01:01:45 PM PST 24
Finished Mar 07 01:02:00 PM PST 24
Peak memory 183404 kb
Host smart-02208ab2-89ac-461d-be96-404989fdc87e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412190602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2412190602
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_random.1179263707
Short name T160
Test name
Test status
Simulation time 2193113786999 ps
CPU time 1434.97 seconds
Started Mar 07 01:01:55 PM PST 24
Finished Mar 07 01:25:50 PM PST 24
Peak memory 191592 kb
Host smart-c23c77db-a6c1-4b73-9df0-d95a397145ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179263707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.1179263707
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2338567297
Short name T253
Test name
Test status
Simulation time 71416210282 ps
CPU time 1104.91 seconds
Started Mar 07 01:01:49 PM PST 24
Finished Mar 07 01:20:14 PM PST 24
Peak memory 183444 kb
Host smart-df7e64aa-2bd9-46a8-8236-efc9c23e9844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338567297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2338567297
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.109843877
Short name T8
Test name
Test status
Simulation time 250062510445 ps
CPU time 436.92 seconds
Started Mar 07 01:02:00 PM PST 24
Finished Mar 07 01:09:17 PM PST 24
Peak memory 183328 kb
Host smart-add304f9-f9b7-48ff-9cde-736b309e1f24
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109843877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.109843877
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.3727156604
Short name T381
Test name
Test status
Simulation time 6723125169 ps
CPU time 3.73 seconds
Started Mar 07 01:01:48 PM PST 24
Finished Mar 07 01:01:52 PM PST 24
Peak memory 183208 kb
Host smart-882a6ea0-1dc1-40c4-80c0-3bd9f25fbda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727156604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3727156604
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.3462637711
Short name T146
Test name
Test status
Simulation time 21065311304 ps
CPU time 38.1 seconds
Started Mar 07 01:01:51 PM PST 24
Finished Mar 07 01:02:29 PM PST 24
Peak memory 191632 kb
Host smart-7199900a-7fac-4703-b10d-363f4650b52e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462637711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3462637711
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3182494944
Short name T23
Test name
Test status
Simulation time 62019930606 ps
CPU time 67.74 seconds
Started Mar 07 01:01:54 PM PST 24
Finished Mar 07 01:03:02 PM PST 24
Peak memory 191600 kb
Host smart-c953206f-cc59-49dd-981f-e25b00901a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182494944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3182494944
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2119434752
Short name T71
Test name
Test status
Simulation time 1313577162044 ps
CPU time 639.64 seconds
Started Mar 07 01:01:47 PM PST 24
Finished Mar 07 01:12:27 PM PST 24
Peak memory 191612 kb
Host smart-4a8c997f-9a69-45d4-91a7-a17d97982b81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119434752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2119434752
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.381941541
Short name T441
Test name
Test status
Simulation time 64886410749 ps
CPU time 132.92 seconds
Started Mar 07 01:01:53 PM PST 24
Finished Mar 07 01:04:07 PM PST 24
Peak memory 197928 kb
Host smart-1ac84101-b1de-4973-aefe-b3997f8ee2f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381941541 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.381941541
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.260924510
Short name T141
Test name
Test status
Simulation time 89265889873 ps
CPU time 89.96 seconds
Started Mar 07 01:01:46 PM PST 24
Finished Mar 07 01:03:16 PM PST 24
Peak memory 183360 kb
Host smart-159615d7-8ec5-4f2a-9033-b5d4a1067b18
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260924510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.rv_timer_cfg_update_on_fly.260924510
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.678135882
Short name T377
Test name
Test status
Simulation time 107274058340 ps
CPU time 77.71 seconds
Started Mar 07 01:01:47 PM PST 24
Finished Mar 07 01:03:04 PM PST 24
Peak memory 183396 kb
Host smart-18d5cf86-c29a-4167-be67-30166beae535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678135882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.678135882
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.4231192520
Short name T201
Test name
Test status
Simulation time 701029485755 ps
CPU time 484.41 seconds
Started Mar 07 01:01:58 PM PST 24
Finished Mar 07 01:10:03 PM PST 24
Peak memory 191588 kb
Host smart-9fd77af5-4b85-49f6-9ac6-a6fe29259257
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231192520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.4231192520
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1679885320
Short name T74
Test name
Test status
Simulation time 104620337727 ps
CPU time 137.68 seconds
Started Mar 07 01:01:54 PM PST 24
Finished Mar 07 01:04:12 PM PST 24
Peak memory 191620 kb
Host smart-ee0f0f48-d2eb-4d01-975c-e280260210d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679885320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1679885320
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.476456638
Short name T73
Test name
Test status
Simulation time 50104587357 ps
CPU time 37.34 seconds
Started Mar 07 01:01:05 PM PST 24
Finished Mar 07 01:01:43 PM PST 24
Peak memory 183408 kb
Host smart-82a4122f-fc00-4052-8547-7fa47da7384d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476456638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.476456638
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.4077637042
Short name T352
Test name
Test status
Simulation time 39902317911 ps
CPU time 19.32 seconds
Started Mar 07 01:01:13 PM PST 24
Finished Mar 07 01:01:32 PM PST 24
Peak memory 183348 kb
Host smart-48a2d685-aff8-4743-b807-2cdbb7fa1e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077637042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.4077637042
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1936717789
Short name T60
Test name
Test status
Simulation time 2261143299301 ps
CPU time 385.67 seconds
Started Mar 07 01:01:22 PM PST 24
Finished Mar 07 01:07:48 PM PST 24
Peak memory 191592 kb
Host smart-5db34f71-49bb-400a-89a7-ddd930370c49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936717789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1936717789
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.1392688196
Short name T38
Test name
Test status
Simulation time 85801269562 ps
CPU time 353.69 seconds
Started Mar 07 01:01:36 PM PST 24
Finished Mar 07 01:07:30 PM PST 24
Peak memory 207560 kb
Host smart-c455c19f-e420-4cf7-ac11-7dfcdbd1b08b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392688196 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.1392688196
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.2394182950
Short name T346
Test name
Test status
Simulation time 315518512276 ps
CPU time 377.06 seconds
Started Mar 07 01:01:49 PM PST 24
Finished Mar 07 01:08:06 PM PST 24
Peak memory 191552 kb
Host smart-3df7a593-5102-4925-9dbb-96a9e8e6a33a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394182950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2394182950
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.522708701
Short name T149
Test name
Test status
Simulation time 261600281529 ps
CPU time 177.85 seconds
Started Mar 07 01:01:58 PM PST 24
Finished Mar 07 01:04:57 PM PST 24
Peak memory 191384 kb
Host smart-00c7aef2-01c5-4312-bdc0-12c41f9345b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522708701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.522708701
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.3616831864
Short name T264
Test name
Test status
Simulation time 369002154111 ps
CPU time 707.3 seconds
Started Mar 07 01:01:58 PM PST 24
Finished Mar 07 01:13:46 PM PST 24
Peak memory 191576 kb
Host smart-a5e79e1d-a21b-473b-b929-180e57215273
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616831864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3616831864
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1948117036
Short name T239
Test name
Test status
Simulation time 65252183722 ps
CPU time 100.46 seconds
Started Mar 07 01:01:51 PM PST 24
Finished Mar 07 01:03:32 PM PST 24
Peak memory 191648 kb
Host smart-ce710418-47b9-4715-a195-b048724b0c1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948117036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1948117036
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2786389978
Short name T131
Test name
Test status
Simulation time 188770488198 ps
CPU time 893.07 seconds
Started Mar 07 01:01:59 PM PST 24
Finished Mar 07 01:16:52 PM PST 24
Peak memory 191592 kb
Host smart-90b6654f-f342-47f5-9539-a55b6794e819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786389978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2786389978
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.390861548
Short name T212
Test name
Test status
Simulation time 685673789482 ps
CPU time 390.19 seconds
Started Mar 07 01:01:46 PM PST 24
Finished Mar 07 01:08:16 PM PST 24
Peak memory 194036 kb
Host smart-8549efd5-9c8c-4333-83f5-421b0f632887
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390861548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.390861548
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1441613237
Short name T295
Test name
Test status
Simulation time 10145127334 ps
CPU time 16.95 seconds
Started Mar 07 01:01:46 PM PST 24
Finished Mar 07 01:02:03 PM PST 24
Peak memory 183380 kb
Host smart-29da1884-0d9e-40be-a8ca-4766f538f91f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441613237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1441613237
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.281779869
Short name T296
Test name
Test status
Simulation time 588166376314 ps
CPU time 947.96 seconds
Started Mar 07 01:01:59 PM PST 24
Finished Mar 07 01:17:47 PM PST 24
Peak memory 194556 kb
Host smart-24bde2b5-6104-4a1f-b424-5a2524ae9b8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281779869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.281779869
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1896805989
Short name T412
Test name
Test status
Simulation time 11474170115 ps
CPU time 9.1 seconds
Started Mar 07 01:01:43 PM PST 24
Finished Mar 07 01:01:52 PM PST 24
Peak memory 183332 kb
Host smart-8956f2a2-d22c-43a2-9e7c-8aa74a97a06b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896805989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1896805989
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.134951777
Short name T396
Test name
Test status
Simulation time 64934666280 ps
CPU time 88.68 seconds
Started Mar 07 01:01:31 PM PST 24
Finished Mar 07 01:03:00 PM PST 24
Peak memory 183384 kb
Host smart-eb70e282-3326-4a4e-8567-0c1b4b67dbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134951777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.134951777
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.1722944708
Short name T409
Test name
Test status
Simulation time 251105560004 ps
CPU time 212.29 seconds
Started Mar 07 01:01:29 PM PST 24
Finished Mar 07 01:05:02 PM PST 24
Peak memory 193828 kb
Host smart-feb7639f-8f52-4e60-96df-37e54a54a4b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722944708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1722944708
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2498316245
Short name T236
Test name
Test status
Simulation time 79773758715 ps
CPU time 82.44 seconds
Started Mar 07 01:00:59 PM PST 24
Finished Mar 07 01:02:22 PM PST 24
Peak memory 195068 kb
Host smart-0da40606-fcf3-4693-8b23-96bee6f0e47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498316245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2498316245
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.2877540747
Short name T399
Test name
Test status
Simulation time 51168932075 ps
CPU time 71.75 seconds
Started Mar 07 01:01:47 PM PST 24
Finished Mar 07 01:02:59 PM PST 24
Peak memory 183376 kb
Host smart-ad6620fe-a877-4e00-9e40-76195eba022b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877540747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2877540747
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.531800321
Short name T269
Test name
Test status
Simulation time 857187360675 ps
CPU time 652.69 seconds
Started Mar 07 01:01:45 PM PST 24
Finished Mar 07 01:12:37 PM PST 24
Peak memory 191556 kb
Host smart-ec1a9296-3ba5-4ec3-8386-1049e19bf780
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531800321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.531800321
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.2648436604
Short name T145
Test name
Test status
Simulation time 169627920849 ps
CPU time 131.76 seconds
Started Mar 07 01:01:45 PM PST 24
Finished Mar 07 01:03:57 PM PST 24
Peak memory 191536 kb
Host smart-b257e6e1-5572-4084-8928-be5f8912002d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648436604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2648436604
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.1602060510
Short name T150
Test name
Test status
Simulation time 623221133989 ps
CPU time 340.27 seconds
Started Mar 07 01:01:46 PM PST 24
Finished Mar 07 01:07:26 PM PST 24
Peak memory 193768 kb
Host smart-52785e13-96ab-47b6-9350-a2e0e06010bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602060510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1602060510
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.3872550323
Short name T429
Test name
Test status
Simulation time 277358838944 ps
CPU time 129.56 seconds
Started Mar 07 01:01:50 PM PST 24
Finished Mar 07 01:04:00 PM PST 24
Peak memory 191516 kb
Host smart-3df9227e-6ac0-40ec-9dc7-0bb60cdf39b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872550323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3872550323
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.3007161125
Short name T51
Test name
Test status
Simulation time 71429772653 ps
CPU time 36.57 seconds
Started Mar 07 01:01:58 PM PST 24
Finished Mar 07 01:02:35 PM PST 24
Peak memory 183352 kb
Host smart-4837affc-7131-4e7a-93a1-55ca110350e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007161125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3007161125
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.417912355
Short name T452
Test name
Test status
Simulation time 479041535926 ps
CPU time 300.97 seconds
Started Mar 07 01:01:50 PM PST 24
Finished Mar 07 01:06:51 PM PST 24
Peak memory 191632 kb
Host smart-dad358f4-a1c6-408d-9a1f-9950f81a9888
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417912355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.417912355
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.1548676971
Short name T454
Test name
Test status
Simulation time 490001434580 ps
CPU time 104.66 seconds
Started Mar 07 01:01:47 PM PST 24
Finished Mar 07 01:03:32 PM PST 24
Peak memory 192668 kb
Host smart-59e9ca09-ff7d-4576-88f4-b738c1b50309
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548676971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1548676971
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.2178576046
Short name T288
Test name
Test status
Simulation time 1042098920563 ps
CPU time 537.99 seconds
Started Mar 07 01:01:20 PM PST 24
Finished Mar 07 01:10:19 PM PST 24
Peak memory 183388 kb
Host smart-3485d2de-182d-4f83-8f0a-4656553b85eb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178576046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.2178576046
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.2403788119
Short name T363
Test name
Test status
Simulation time 277410322559 ps
CPU time 188.24 seconds
Started Mar 07 01:01:19 PM PST 24
Finished Mar 07 01:04:28 PM PST 24
Peak memory 183412 kb
Host smart-31259f55-8bfe-4ec5-876d-8d226446018f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403788119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.2403788119
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.1456758440
Short name T227
Test name
Test status
Simulation time 163182200889 ps
CPU time 217.28 seconds
Started Mar 07 01:01:14 PM PST 24
Finished Mar 07 01:04:51 PM PST 24
Peak memory 191632 kb
Host smart-db259f39-9fdc-4246-ae3a-0f7265071163
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456758440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1456758440
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2258788650
Short name T286
Test name
Test status
Simulation time 57861181242 ps
CPU time 106.89 seconds
Started Mar 07 01:01:25 PM PST 24
Finished Mar 07 01:03:13 PM PST 24
Peak memory 191596 kb
Host smart-1e54fe44-7dd6-469c-b7a8-ae3ce95c23ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258788650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2258788650
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.2243204558
Short name T341
Test name
Test status
Simulation time 368536636428 ps
CPU time 221.7 seconds
Started Mar 07 01:01:21 PM PST 24
Finished Mar 07 01:05:04 PM PST 24
Peak memory 191440 kb
Host smart-eab20baf-1a00-4463-a0cc-4309cc73c0db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243204558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
2243204558
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.4222162609
Short name T214
Test name
Test status
Simulation time 408891029324 ps
CPU time 345.34 seconds
Started Mar 07 01:01:50 PM PST 24
Finished Mar 07 01:07:36 PM PST 24
Peak memory 191628 kb
Host smart-8a1dcf6f-b6d8-45f9-9df0-eed2ffceadc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222162609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.4222162609
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.2049561591
Short name T331
Test name
Test status
Simulation time 162788862071 ps
CPU time 199.3 seconds
Started Mar 07 01:01:50 PM PST 24
Finished Mar 07 01:05:09 PM PST 24
Peak memory 191588 kb
Host smart-7c40d9ba-db14-4bb5-9f8b-93396b6c17f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049561591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2049561591
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.1542174662
Short name T356
Test name
Test status
Simulation time 149125373220 ps
CPU time 86.45 seconds
Started Mar 07 01:01:50 PM PST 24
Finished Mar 07 01:03:17 PM PST 24
Peak memory 191592 kb
Host smart-36f02ae3-4320-4fa8-9381-0ceb96c47064
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542174662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1542174662
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3374347644
Short name T6
Test name
Test status
Simulation time 49043395978 ps
CPU time 82.26 seconds
Started Mar 07 01:01:46 PM PST 24
Finished Mar 07 01:03:08 PM PST 24
Peak memory 183408 kb
Host smart-b45b8c78-f53f-4db8-8185-6722dd864efc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374347644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3374347644
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.2817056406
Short name T315
Test name
Test status
Simulation time 283745061263 ps
CPU time 271.21 seconds
Started Mar 07 01:01:49 PM PST 24
Finished Mar 07 01:06:20 PM PST 24
Peak memory 193612 kb
Host smart-27e3f46b-384c-440e-8e14-dbcd48325669
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817056406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.2817056406
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.964072086
Short name T450
Test name
Test status
Simulation time 84515570010 ps
CPU time 103.71 seconds
Started Mar 07 01:01:53 PM PST 24
Finished Mar 07 01:03:37 PM PST 24
Peak memory 191584 kb
Host smart-91b93502-8c8e-4cd4-b14c-5d7c34941dbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964072086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.964072086
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.4294197867
Short name T25
Test name
Test status
Simulation time 110794425977 ps
CPU time 230.51 seconds
Started Mar 07 01:01:58 PM PST 24
Finished Mar 07 01:05:49 PM PST 24
Peak memory 191580 kb
Host smart-da9004dd-46ca-4b72-81ed-b6fa80c2b301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294197867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.4294197867
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.1892140126
Short name T173
Test name
Test status
Simulation time 248910327471 ps
CPU time 128.53 seconds
Started Mar 07 01:01:49 PM PST 24
Finished Mar 07 01:03:58 PM PST 24
Peak memory 183360 kb
Host smart-b96d00df-0fd1-4dd9-95e4-78848e173469
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892140126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1892140126
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1225231065
Short name T126
Test name
Test status
Simulation time 155419586065 ps
CPU time 257.51 seconds
Started Mar 07 01:01:10 PM PST 24
Finished Mar 07 01:05:28 PM PST 24
Peak memory 183340 kb
Host smart-68caffad-d774-4c53-84dc-8c6756c519d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225231065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1225231065
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3039064607
Short name T395
Test name
Test status
Simulation time 666305027635 ps
CPU time 295.01 seconds
Started Mar 07 01:01:20 PM PST 24
Finished Mar 07 01:06:16 PM PST 24
Peak memory 183316 kb
Host smart-b3c4d04f-884e-46a9-ac08-fb22af9e017e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039064607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3039064607
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1936047560
Short name T375
Test name
Test status
Simulation time 82333242 ps
CPU time 0.54 seconds
Started Mar 07 01:01:07 PM PST 24
Finished Mar 07 01:01:08 PM PST 24
Peak memory 183052 kb
Host smart-b748575d-1bbc-4f20-88da-24583e6cf279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936047560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1936047560
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.180563311
Short name T244
Test name
Test status
Simulation time 454221928739 ps
CPU time 212.92 seconds
Started Mar 07 01:01:57 PM PST 24
Finished Mar 07 01:05:30 PM PST 24
Peak memory 191692 kb
Host smart-04a9bcb1-ec11-4aff-ab34-c3e9e437b01f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180563311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.180563311
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.227876434
Short name T190
Test name
Test status
Simulation time 128758327630 ps
CPU time 1028.98 seconds
Started Mar 07 01:01:53 PM PST 24
Finished Mar 07 01:19:02 PM PST 24
Peak memory 191492 kb
Host smart-ad44ac86-7f85-4f56-a44e-320be6d5872c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227876434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.227876434
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.288282308
Short name T195
Test name
Test status
Simulation time 292909373846 ps
CPU time 183.17 seconds
Started Mar 07 01:01:53 PM PST 24
Finished Mar 07 01:04:57 PM PST 24
Peak memory 191576 kb
Host smart-af2d2b5c-b73e-44a8-a9c2-385796d4e566
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288282308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.288282308
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2640118253
Short name T349
Test name
Test status
Simulation time 48321274657 ps
CPU time 80.28 seconds
Started Mar 07 01:01:57 PM PST 24
Finished Mar 07 01:03:17 PM PST 24
Peak memory 191452 kb
Host smart-e2def075-dfcb-4dbd-abcb-c79d16ef111b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640118253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2640118253
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.91665461
Short name T67
Test name
Test status
Simulation time 73667500033 ps
CPU time 130.05 seconds
Started Mar 07 01:01:48 PM PST 24
Finished Mar 07 01:03:58 PM PST 24
Peak memory 194756 kb
Host smart-27988003-2a18-426c-b0a6-0cf1cfe2774a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91665461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.91665461
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3987326577
Short name T218
Test name
Test status
Simulation time 289051970727 ps
CPU time 1428.75 seconds
Started Mar 07 01:01:51 PM PST 24
Finished Mar 07 01:25:40 PM PST 24
Peak memory 191556 kb
Host smart-d4fba226-c898-4ce3-8ab3-8d2cdb486684
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987326577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3987326577
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.1461414887
Short name T299
Test name
Test status
Simulation time 22775512970 ps
CPU time 30.88 seconds
Started Mar 07 01:01:57 PM PST 24
Finished Mar 07 01:02:28 PM PST 24
Peak memory 183324 kb
Host smart-1d67bc4e-9417-43b1-abe2-6cd6329f96a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461414887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1461414887
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.1568767446
Short name T26
Test name
Test status
Simulation time 136543572402 ps
CPU time 187.77 seconds
Started Mar 07 01:01:58 PM PST 24
Finished Mar 07 01:05:06 PM PST 24
Peak memory 191564 kb
Host smart-17a7fc0c-9779-4971-905c-4e62973b3c03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568767446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1568767446
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.2188530366
Short name T3
Test name
Test status
Simulation time 622838533553 ps
CPU time 315.79 seconds
Started Mar 07 01:01:52 PM PST 24
Finished Mar 07 01:07:08 PM PST 24
Peak memory 191576 kb
Host smart-e1e52506-b549-4d54-b0ad-74150dd55ebf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188530366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2188530366
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.3397801270
Short name T254
Test name
Test status
Simulation time 564476649457 ps
CPU time 1003.59 seconds
Started Mar 07 01:01:30 PM PST 24
Finished Mar 07 01:18:14 PM PST 24
Peak memory 183304 kb
Host smart-7e000cde-efba-4214-a109-00e250694f31
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397801270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.3397801270
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.553449827
Short name T376
Test name
Test status
Simulation time 22741583463 ps
CPU time 36.46 seconds
Started Mar 07 01:01:21 PM PST 24
Finished Mar 07 01:01:58 PM PST 24
Peak memory 183384 kb
Host smart-5bc1bde4-e6f4-4227-94a3-610f07fba579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553449827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.553449827
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.4061804444
Short name T198
Test name
Test status
Simulation time 4391473024 ps
CPU time 12.07 seconds
Started Mar 07 01:01:26 PM PST 24
Finished Mar 07 01:01:42 PM PST 24
Peak memory 194380 kb
Host smart-74edf888-7815-468f-b44e-8bb4914d22a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061804444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.4061804444
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2736387423
Short name T197
Test name
Test status
Simulation time 13764378945 ps
CPU time 26.53 seconds
Started Mar 07 01:01:34 PM PST 24
Finished Mar 07 01:02:01 PM PST 24
Peak memory 183452 kb
Host smart-d28fea73-796e-47b3-94a8-f898e43f0e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736387423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2736387423
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.419850001
Short name T13
Test name
Test status
Simulation time 65696463532 ps
CPU time 97.02 seconds
Started Mar 07 01:01:58 PM PST 24
Finished Mar 07 01:03:36 PM PST 24
Peak memory 195092 kb
Host smart-f5bbdbd2-3bb4-446e-805f-126935ec9806
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419850001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.419850001
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3053337209
Short name T135
Test name
Test status
Simulation time 441282871337 ps
CPU time 404.64 seconds
Started Mar 07 01:02:00 PM PST 24
Finished Mar 07 01:08:45 PM PST 24
Peak memory 191592 kb
Host smart-e0bd20c2-ddcf-46f4-ae90-f2916a8e42c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053337209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3053337209
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.2224682599
Short name T142
Test name
Test status
Simulation time 2685638165167 ps
CPU time 683.17 seconds
Started Mar 07 01:01:52 PM PST 24
Finished Mar 07 01:13:16 PM PST 24
Peak memory 191576 kb
Host smart-92d85e15-ee2c-44d8-861a-33f9d202d8c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224682599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2224682599
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3565384834
Short name T162
Test name
Test status
Simulation time 586639643087 ps
CPU time 688.16 seconds
Started Mar 07 01:01:54 PM PST 24
Finished Mar 07 01:13:22 PM PST 24
Peak memory 191644 kb
Host smart-d0825131-a5b6-4256-b7a7-9d64e094e21a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565384834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3565384834
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2270113427
Short name T235
Test name
Test status
Simulation time 633886292487 ps
CPU time 256.57 seconds
Started Mar 07 01:01:54 PM PST 24
Finished Mar 07 01:06:11 PM PST 24
Peak memory 191572 kb
Host smart-566d984d-588d-4636-9795-118fe95e6590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270113427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2270113427
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.2914200009
Short name T385
Test name
Test status
Simulation time 210369631246 ps
CPU time 95.64 seconds
Started Mar 07 01:01:40 PM PST 24
Finished Mar 07 01:03:16 PM PST 24
Peak memory 191564 kb
Host smart-5c2e6669-0177-4dc1-b2df-dbb9d94de15e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914200009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.2914200009
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3174757131
Short name T243
Test name
Test status
Simulation time 125318858113 ps
CPU time 956.33 seconds
Started Mar 07 01:01:51 PM PST 24
Finished Mar 07 01:17:47 PM PST 24
Peak memory 191644 kb
Host smart-51c759e5-fa33-4581-9b5f-441e8c151456
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174757131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3174757131
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.3868127228
Short name T234
Test name
Test status
Simulation time 34138301761 ps
CPU time 620.78 seconds
Started Mar 07 01:01:58 PM PST 24
Finished Mar 07 01:12:19 PM PST 24
Peak memory 191572 kb
Host smart-38727379-c0f7-4f77-90d4-a2986e812ab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868127228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3868127228
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1257656948
Short name T343
Test name
Test status
Simulation time 213270742018 ps
CPU time 410.44 seconds
Started Mar 07 01:01:47 PM PST 24
Finished Mar 07 01:08:38 PM PST 24
Peak memory 191648 kb
Host smart-7c3dcebe-c47c-446f-894d-91e358d473ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257656948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1257656948
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1755120886
Short name T156
Test name
Test status
Simulation time 90868242038 ps
CPU time 279.99 seconds
Started Mar 07 01:01:45 PM PST 24
Finished Mar 07 01:06:25 PM PST 24
Peak memory 191572 kb
Host smart-bba1777f-c5c0-4eba-aff1-b690bb127868
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755120886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1755120886
Directory /workspace/99.rv_timer_random/latest
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