Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 582
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T508 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.434050977 Mar 10 01:12:15 PM PDT 24 Mar 10 01:12:16 PM PDT 24 60220791 ps
T509 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2884503630 Mar 10 01:12:38 PM PDT 24 Mar 10 01:12:39 PM PDT 24 16057563 ps
T510 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.4158390942 Mar 10 01:12:16 PM PDT 24 Mar 10 01:12:17 PM PDT 24 128402893 ps
T511 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3102775289 Mar 10 01:12:13 PM PDT 24 Mar 10 01:12:14 PM PDT 24 38260040 ps
T512 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.974425921 Mar 10 01:12:28 PM PDT 24 Mar 10 01:12:29 PM PDT 24 13546816 ps
T513 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3213721664 Mar 10 01:12:20 PM PDT 24 Mar 10 01:12:21 PM PDT 24 36782489 ps
T514 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.592527375 Mar 10 01:12:10 PM PDT 24 Mar 10 01:12:11 PM PDT 24 12239195 ps
T515 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1552386699 Mar 10 01:12:30 PM PDT 24 Mar 10 01:12:31 PM PDT 24 25705180 ps
T516 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1777064393 Mar 10 01:12:30 PM PDT 24 Mar 10 01:12:31 PM PDT 24 45580292 ps
T517 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1147107479 Mar 10 01:12:31 PM PDT 24 Mar 10 01:12:32 PM PDT 24 184468641 ps
T103 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3406140472 Mar 10 01:12:24 PM PDT 24 Mar 10 01:12:26 PM PDT 24 116920513 ps
T104 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2023273767 Mar 10 01:12:15 PM PDT 24 Mar 10 01:12:16 PM PDT 24 476579135 ps
T518 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4220692877 Mar 10 01:12:09 PM PDT 24 Mar 10 01:12:10 PM PDT 24 183074091 ps
T519 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1419739264 Mar 10 01:12:31 PM PDT 24 Mar 10 01:12:31 PM PDT 24 23613832 ps
T520 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3449724249 Mar 10 01:12:29 PM PDT 24 Mar 10 01:12:31 PM PDT 24 83335363 ps
T89 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1988054301 Mar 10 01:12:12 PM PDT 24 Mar 10 01:12:13 PM PDT 24 55643727 ps
T521 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3499160357 Mar 10 01:12:22 PM PDT 24 Mar 10 01:12:24 PM PDT 24 219624817 ps
T102 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3877932614 Mar 10 01:12:24 PM PDT 24 Mar 10 01:12:25 PM PDT 24 98747497 ps
T522 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.533952643 Mar 10 01:12:24 PM PDT 24 Mar 10 01:12:27 PM PDT 24 774040467 ps
T523 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3810345314 Mar 10 01:12:20 PM PDT 24 Mar 10 01:12:20 PM PDT 24 43767194 ps
T524 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3490882622 Mar 10 01:12:24 PM PDT 24 Mar 10 01:12:26 PM PDT 24 16839638 ps
T525 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3648091334 Mar 10 01:12:26 PM PDT 24 Mar 10 01:12:27 PM PDT 24 58104511 ps
T526 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1667758259 Mar 10 01:12:24 PM PDT 24 Mar 10 01:12:25 PM PDT 24 28397192 ps
T527 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1162734477 Mar 10 01:12:16 PM PDT 24 Mar 10 01:12:18 PM PDT 24 219258754 ps
T528 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.167677100 Mar 10 01:12:14 PM PDT 24 Mar 10 01:12:16 PM PDT 24 26911067 ps
T529 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3688367874 Mar 10 01:12:23 PM PDT 24 Mar 10 01:12:25 PM PDT 24 237281184 ps
T530 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.283629286 Mar 10 01:12:33 PM PDT 24 Mar 10 01:12:34 PM PDT 24 36965125 ps
T531 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.748032105 Mar 10 01:12:33 PM PDT 24 Mar 10 01:12:34 PM PDT 24 73578416 ps
T90 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2132977383 Mar 10 01:12:21 PM PDT 24 Mar 10 01:12:22 PM PDT 24 41840974 ps
T532 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.4120329142 Mar 10 01:12:23 PM PDT 24 Mar 10 01:12:25 PM PDT 24 165995513 ps
T533 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.412471539 Mar 10 01:12:23 PM PDT 24 Mar 10 01:12:24 PM PDT 24 12982694 ps
T534 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3444975646 Mar 10 01:12:13 PM PDT 24 Mar 10 01:12:14 PM PDT 24 19415987 ps
T535 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2461290072 Mar 10 01:12:31 PM PDT 24 Mar 10 01:12:32 PM PDT 24 126522648 ps
T536 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.4059660826 Mar 10 01:12:27 PM PDT 24 Mar 10 01:12:29 PM PDT 24 217734580 ps
T537 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.349883348 Mar 10 01:12:37 PM PDT 24 Mar 10 01:12:39 PM PDT 24 25787160 ps
T91 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2742603100 Mar 10 01:12:11 PM PDT 24 Mar 10 01:12:12 PM PDT 24 36248609 ps
T538 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1557418300 Mar 10 01:12:36 PM PDT 24 Mar 10 01:12:36 PM PDT 24 154786072 ps
T539 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.387629339 Mar 10 01:12:28 PM PDT 24 Mar 10 01:12:29 PM PDT 24 45480815 ps
T540 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.4080602254 Mar 10 01:12:10 PM PDT 24 Mar 10 01:12:13 PM PDT 24 2441973105 ps
T541 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.128305935 Mar 10 01:12:28 PM PDT 24 Mar 10 01:12:30 PM PDT 24 29011022 ps
T542 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.8234357 Mar 10 01:12:15 PM PDT 24 Mar 10 01:12:16 PM PDT 24 53915846 ps
T543 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.788578944 Mar 10 01:12:29 PM PDT 24 Mar 10 01:12:30 PM PDT 24 14083865 ps
T544 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.4015400091 Mar 10 01:12:26 PM PDT 24 Mar 10 01:12:27 PM PDT 24 159121983 ps
T545 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2071718124 Mar 10 01:12:22 PM PDT 24 Mar 10 01:12:24 PM PDT 24 84565752 ps
T546 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.881344994 Mar 10 01:12:21 PM PDT 24 Mar 10 01:12:22 PM PDT 24 28871092 ps
T547 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.4276698263 Mar 10 01:12:24 PM PDT 24 Mar 10 01:12:27 PM PDT 24 55781751 ps
T548 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.956240243 Mar 10 01:12:26 PM PDT 24 Mar 10 01:12:27 PM PDT 24 13214307 ps
T549 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.765161460 Mar 10 01:12:29 PM PDT 24 Mar 10 01:12:31 PM PDT 24 25610666 ps
T550 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.963554590 Mar 10 01:12:28 PM PDT 24 Mar 10 01:12:29 PM PDT 24 87440994 ps
T551 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2272058164 Mar 10 01:12:26 PM PDT 24 Mar 10 01:12:28 PM PDT 24 83205341 ps
T552 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2044744141 Mar 10 01:12:24 PM PDT 24 Mar 10 01:12:25 PM PDT 24 29318745 ps
T553 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2017461666 Mar 10 01:12:35 PM PDT 24 Mar 10 01:12:36 PM PDT 24 46126445 ps
T554 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1358834431 Mar 10 01:12:31 PM PDT 24 Mar 10 01:12:31 PM PDT 24 12586879 ps
T555 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2899099250 Mar 10 01:12:16 PM PDT 24 Mar 10 01:12:16 PM PDT 24 16754591 ps
T556 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3067426998 Mar 10 01:12:26 PM PDT 24 Mar 10 01:12:26 PM PDT 24 15911195 ps
T557 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1933777898 Mar 10 01:12:30 PM PDT 24 Mar 10 01:12:31 PM PDT 24 53477108 ps
T558 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1227297527 Mar 10 01:12:21 PM PDT 24 Mar 10 01:12:22 PM PDT 24 74320088 ps
T559 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.283848611 Mar 10 01:12:23 PM PDT 24 Mar 10 01:12:24 PM PDT 24 16650144 ps
T560 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2913461598 Mar 10 01:12:21 PM PDT 24 Mar 10 01:12:22 PM PDT 24 37268128 ps
T561 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2815744731 Mar 10 01:12:34 PM PDT 24 Mar 10 01:12:35 PM PDT 24 16943997 ps
T562 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2602643642 Mar 10 01:12:15 PM PDT 24 Mar 10 01:12:15 PM PDT 24 15853698 ps
T563 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.497886226 Mar 10 01:12:17 PM PDT 24 Mar 10 01:12:19 PM PDT 24 495107524 ps
T564 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.839162019 Mar 10 01:12:30 PM PDT 24 Mar 10 01:12:30 PM PDT 24 43002469 ps
T565 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1443158567 Mar 10 01:12:21 PM PDT 24 Mar 10 01:12:22 PM PDT 24 29171238 ps
T566 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2123569564 Mar 10 01:12:26 PM PDT 24 Mar 10 01:12:27 PM PDT 24 46814599 ps
T567 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.787019899 Mar 10 01:12:34 PM PDT 24 Mar 10 01:12:35 PM PDT 24 11109102 ps
T568 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1103376004 Mar 10 01:12:26 PM PDT 24 Mar 10 01:12:27 PM PDT 24 33129419 ps
T569 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1519062583 Mar 10 01:12:25 PM PDT 24 Mar 10 01:12:29 PM PDT 24 1065989230 ps
T570 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1237545051 Mar 10 01:12:16 PM PDT 24 Mar 10 01:12:17 PM PDT 24 81044252 ps
T571 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1168435549 Mar 10 01:12:08 PM PDT 24 Mar 10 01:12:09 PM PDT 24 98946477 ps
T572 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2795312355 Mar 10 01:12:24 PM PDT 24 Mar 10 01:12:25 PM PDT 24 26654895 ps
T573 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2841536207 Mar 10 01:12:26 PM PDT 24 Mar 10 01:12:27 PM PDT 24 76420017 ps
T574 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1600247712 Mar 10 01:12:28 PM PDT 24 Mar 10 01:12:29 PM PDT 24 17145712 ps
T575 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.277237285 Mar 10 01:12:22 PM PDT 24 Mar 10 01:12:26 PM PDT 24 160234939 ps
T576 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2740949731 Mar 10 01:12:29 PM PDT 24 Mar 10 01:12:30 PM PDT 24 42086899 ps
T577 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1522163199 Mar 10 01:12:39 PM PDT 24 Mar 10 01:12:40 PM PDT 24 36608899 ps
T578 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2195973323 Mar 10 01:12:25 PM PDT 24 Mar 10 01:12:27 PM PDT 24 230142585 ps
T579 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.235676590 Mar 10 01:12:27 PM PDT 24 Mar 10 01:12:27 PM PDT 24 20235373 ps
T580 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1512240629 Mar 10 01:12:28 PM PDT 24 Mar 10 01:12:29 PM PDT 24 112656293 ps
T581 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.692881566 Mar 10 01:12:36 PM PDT 24 Mar 10 01:12:37 PM PDT 24 44434760 ps
T582 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2809160394 Mar 10 01:12:23 PM PDT 24 Mar 10 01:12:24 PM PDT 24 17565349 ps
T92 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2108581987 Mar 10 01:12:16 PM PDT 24 Mar 10 01:12:17 PM PDT 24 16530445 ps

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.3817357750
Short name T5
Test name
Test status
Simulation time 220536684305 ps
CPU time 588.26 seconds
Started Mar 10 01:13:36 PM PDT 24
Finished Mar 10 01:23:25 PM PDT 24
Peak memory 198020 kb
Host smart-42b27800-6b94-43cc-9932-2e5204b67201
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817357750 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.3817357750
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.1912290637
Short name T10
Test name
Test status
Simulation time 446975521481 ps
CPU time 815.38 seconds
Started Mar 10 01:13:42 PM PDT 24
Finished Mar 10 01:27:18 PM PDT 24
Peak memory 191568 kb
Host smart-a16a32a6-f434-4de6-a02e-854215cc7bb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912290637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.1912290637
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.959984328
Short name T81
Test name
Test status
Simulation time 2508156949299 ps
CPU time 2078.21 seconds
Started Mar 10 01:13:55 PM PDT 24
Finished Mar 10 01:48:34 PM PDT 24
Peak memory 196136 kb
Host smart-f7c26ef3-9cd5-4ea4-b88d-c70dc8d329d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959984328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.
959984328
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.81042805
Short name T13
Test name
Test status
Simulation time 119980010 ps
CPU time 0.79 seconds
Started Mar 10 01:13:11 PM PDT 24
Finished Mar 10 01:13:13 PM PDT 24
Peak memory 213412 kb
Host smart-b1070d83-b385-48dc-8d85-68819092fb01
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81042805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.81042805
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2538578643
Short name T161
Test name
Test status
Simulation time 1535238976937 ps
CPU time 3209.33 seconds
Started Mar 10 01:13:47 PM PDT 24
Finished Mar 10 02:07:17 PM PDT 24
Peak memory 191572 kb
Host smart-7710ce67-59fa-4958-b4fd-8a0709a08a6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538578643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2538578643
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3685964189
Short name T30
Test name
Test status
Simulation time 36856692 ps
CPU time 0.86 seconds
Started Mar 10 01:12:15 PM PDT 24
Finished Mar 10 01:12:16 PM PDT 24
Peak memory 192480 kb
Host smart-8ce73b3e-19a5-404e-aa66-a91e5e9d28ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685964189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3685964189
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1655858304
Short name T177
Test name
Test status
Simulation time 524320720595 ps
CPU time 1337.14 seconds
Started Mar 10 01:13:47 PM PDT 24
Finished Mar 10 01:36:04 PM PDT 24
Peak memory 191560 kb
Host smart-6c6fa2a9-3103-45b0-afe5-3ad1999db1a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655858304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1655858304
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.2369600768
Short name T115
Test name
Test status
Simulation time 435479637582 ps
CPU time 2546.86 seconds
Started Mar 10 01:13:20 PM PDT 24
Finished Mar 10 01:55:47 PM PDT 24
Peak memory 191560 kb
Host smart-d63a3b99-7eaf-4582-a999-26b97b9e617e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369600768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.2369600768
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2058699806
Short name T239
Test name
Test status
Simulation time 368971476520 ps
CPU time 1227.95 seconds
Started Mar 10 01:13:36 PM PDT 24
Finished Mar 10 01:34:04 PM PDT 24
Peak memory 191640 kb
Host smart-d9942afd-b271-49ff-ac95-8db5593de58f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058699806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2058699806
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.2502513104
Short name T68
Test name
Test status
Simulation time 264610087972 ps
CPU time 619.68 seconds
Started Mar 10 01:13:30 PM PDT 24
Finished Mar 10 01:23:50 PM PDT 24
Peak memory 195592 kb
Host smart-1daa66ca-78cc-4738-8d48-c75de0f88b96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502513104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.2502513104
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2943281102
Short name T153
Test name
Test status
Simulation time 1584203828478 ps
CPU time 762.51 seconds
Started Mar 10 01:13:43 PM PDT 24
Finished Mar 10 01:26:26 PM PDT 24
Peak memory 191628 kb
Host smart-6fc2e6f5-ded1-4787-a917-657bde769b62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943281102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2943281102
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2763940296
Short name T150
Test name
Test status
Simulation time 750542591490 ps
CPU time 1229.5 seconds
Started Mar 10 01:14:12 PM PDT 24
Finished Mar 10 01:34:41 PM PDT 24
Peak memory 191512 kb
Host smart-f2a4e490-da95-446e-abfb-e705749bd9f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763940296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2763940296
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3877932614
Short name T102
Test name
Test status
Simulation time 98747497 ps
CPU time 1.12 seconds
Started Mar 10 01:12:24 PM PDT 24
Finished Mar 10 01:12:25 PM PDT 24
Peak memory 195068 kb
Host smart-0f071a2a-cdf4-400d-930b-f939c58e2152
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877932614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3877932614
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2541477671
Short name T273
Test name
Test status
Simulation time 1366982026708 ps
CPU time 1260.98 seconds
Started Mar 10 01:14:01 PM PDT 24
Finished Mar 10 01:35:02 PM PDT 24
Peak memory 191604 kb
Host smart-7fa0dd50-17be-4e60-8845-316ebde1d500
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541477671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2541477671
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.685292118
Short name T84
Test name
Test status
Simulation time 5045915816348 ps
CPU time 1843.7 seconds
Started Mar 10 01:13:37 PM PDT 24
Finished Mar 10 01:44:21 PM PDT 24
Peak memory 191572 kb
Host smart-4e3867a2-7021-4fcd-a3ba-34a1811cb097
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685292118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.
685292118
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1561399254
Short name T216
Test name
Test status
Simulation time 836031937839 ps
CPU time 1048.45 seconds
Started Mar 10 01:13:42 PM PDT 24
Finished Mar 10 01:31:10 PM PDT 24
Peak memory 191836 kb
Host smart-9dc2de93-525d-4bfd-86d2-1d59a9f97765
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561399254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1561399254
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.3786949682
Short name T210
Test name
Test status
Simulation time 584859413106 ps
CPU time 3352.99 seconds
Started Mar 10 01:13:55 PM PDT 24
Finished Mar 10 02:09:49 PM PDT 24
Peak memory 191512 kb
Host smart-019dd9a5-d6d2-49b8-853f-f1482f1aae8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786949682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.3786949682
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_random.3517222948
Short name T19
Test name
Test status
Simulation time 344222016889 ps
CPU time 700.84 seconds
Started Mar 10 01:13:46 PM PDT 24
Finished Mar 10 01:25:27 PM PDT 24
Peak memory 191588 kb
Host smart-e51ac9c7-e6f1-4e50-989f-30b0ee91f840
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517222948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3517222948
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.202597351
Short name T121
Test name
Test status
Simulation time 143730021017 ps
CPU time 233.82 seconds
Started Mar 10 01:13:43 PM PDT 24
Finished Mar 10 01:17:37 PM PDT 24
Peak memory 194616 kb
Host smart-ac9d74cf-4b88-4a8c-9064-25cf3c4cbc16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202597351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
202597351
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_random.803187743
Short name T323
Test name
Test status
Simulation time 823795314744 ps
CPU time 558.09 seconds
Started Mar 10 01:14:06 PM PDT 24
Finished Mar 10 01:23:24 PM PDT 24
Peak memory 191540 kb
Host smart-7048c8af-0a7f-4e48-b91d-0b7fb926b9cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803187743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.803187743
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1875315949
Short name T134
Test name
Test status
Simulation time 132879396695 ps
CPU time 537.71 seconds
Started Mar 10 01:14:38 PM PDT 24
Finished Mar 10 01:23:37 PM PDT 24
Peak memory 191596 kb
Host smart-827a3f88-0739-475c-8ec5-9a526c721cdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875315949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1875315949
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.760548759
Short name T159
Test name
Test status
Simulation time 142683052782 ps
CPU time 1542.48 seconds
Started Mar 10 01:16:01 PM PDT 24
Finished Mar 10 01:41:44 PM PDT 24
Peak memory 183340 kb
Host smart-0353b0ff-a6d8-49e8-adf3-09848c95c6fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760548759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.760548759
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random.3308205902
Short name T275
Test name
Test status
Simulation time 355260621802 ps
CPU time 301.03 seconds
Started Mar 10 01:13:41 PM PDT 24
Finished Mar 10 01:18:43 PM PDT 24
Peak memory 191828 kb
Host smart-4def75fd-fc4f-4e2e-96d1-1db362c802fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308205902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3308205902
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.3494604535
Short name T279
Test name
Test status
Simulation time 428039332000 ps
CPU time 1075.26 seconds
Started Mar 10 01:13:59 PM PDT 24
Finished Mar 10 01:31:55 PM PDT 24
Peak memory 191624 kb
Host smart-d69a01ad-1f27-4259-ba28-cfdb0ec517cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494604535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.3494604535
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/164.rv_timer_random.3118621928
Short name T168
Test name
Test status
Simulation time 735361435603 ps
CPU time 509.06 seconds
Started Mar 10 01:16:00 PM PDT 24
Finished Mar 10 01:24:29 PM PDT 24
Peak memory 194812 kb
Host smart-0384b241-e6c9-4856-a1bb-7a53721477f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118621928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3118621928
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random.1777759670
Short name T205
Test name
Test status
Simulation time 194962280038 ps
CPU time 2034.68 seconds
Started Mar 10 01:13:13 PM PDT 24
Finished Mar 10 01:47:09 PM PDT 24
Peak memory 191512 kb
Host smart-1a9c88b1-1402-4510-805f-c7d38353997a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777759670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1777759670
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3641322321
Short name T158
Test name
Test status
Simulation time 3892069877999 ps
CPU time 2137.49 seconds
Started Mar 10 01:13:56 PM PDT 24
Finished Mar 10 01:49:34 PM PDT 24
Peak memory 195088 kb
Host smart-9614b444-5c19-4afe-bf86-53fb0d154b2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641322321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3641322321
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.2470479376
Short name T64
Test name
Test status
Simulation time 692682013490 ps
CPU time 749.92 seconds
Started Mar 10 01:14:27 PM PDT 24
Finished Mar 10 01:26:57 PM PDT 24
Peak memory 191572 kb
Host smart-1be6fd8e-1b60-48e9-a0b0-ea46db60620e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470479376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.2470479376
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.1211248984
Short name T69
Test name
Test status
Simulation time 1564994181241 ps
CPU time 884.35 seconds
Started Mar 10 01:13:25 PM PDT 24
Finished Mar 10 01:28:10 PM PDT 24
Peak memory 195984 kb
Host smart-559de13f-52e4-47aa-9ae3-d03d8f93182f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211248984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1211248984
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/149.rv_timer_random.2648380664
Short name T128
Test name
Test status
Simulation time 522558301857 ps
CPU time 967.56 seconds
Started Mar 10 01:15:44 PM PDT 24
Finished Mar 10 01:31:52 PM PDT 24
Peak memory 194048 kb
Host smart-4597b63c-3d96-4a9e-922f-4a73560fe056
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648380664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2648380664
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random.2835711169
Short name T302
Test name
Test status
Simulation time 336385385116 ps
CPU time 371.9 seconds
Started Mar 10 01:13:58 PM PDT 24
Finished Mar 10 01:20:10 PM PDT 24
Peak memory 191552 kb
Host smart-175e0ef5-277e-4426-8411-9c45ebcebe7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835711169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2835711169
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1205215407
Short name T197
Test name
Test status
Simulation time 3143841612132 ps
CPU time 1748.23 seconds
Started Mar 10 01:14:01 PM PDT 24
Finished Mar 10 01:43:10 PM PDT 24
Peak memory 195844 kb
Host smart-1ac42d76-12a3-4c48-bee2-7c4a6438368b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205215407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1205215407
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/62.rv_timer_random.30835951
Short name T290
Test name
Test status
Simulation time 185978250280 ps
CPU time 2271.86 seconds
Started Mar 10 01:14:39 PM PDT 24
Finished Mar 10 01:52:31 PM PDT 24
Peak memory 191608 kb
Host smart-51bee2a7-b76b-4dab-8f26-4b4ed9f145fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30835951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.30835951
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.2786002666
Short name T170
Test name
Test status
Simulation time 767363386822 ps
CPU time 1192.02 seconds
Started Mar 10 01:14:41 PM PDT 24
Finished Mar 10 01:34:33 PM PDT 24
Peak memory 191580 kb
Host smart-ceac5f11-15c0-4d7f-8076-6ed0662100ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786002666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2786002666
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3564476305
Short name T164
Test name
Test status
Simulation time 1279220729390 ps
CPU time 1269.36 seconds
Started Mar 10 01:13:30 PM PDT 24
Finished Mar 10 01:34:39 PM PDT 24
Peak memory 183404 kb
Host smart-792d3803-b785-45fc-ac21-ef7246a0f50a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564476305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3564476305
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.4005183254
Short name T222
Test name
Test status
Simulation time 910386300093 ps
CPU time 1989.18 seconds
Started Mar 10 01:13:24 PM PDT 24
Finished Mar 10 01:46:34 PM PDT 24
Peak memory 191540 kb
Host smart-ed862e00-9264-48b2-aba7-7705d5817e28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005183254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
4005183254
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_random.1584737451
Short name T113
Test name
Test status
Simulation time 423477965445 ps
CPU time 424.18 seconds
Started Mar 10 01:13:12 PM PDT 24
Finished Mar 10 01:20:17 PM PDT 24
Peak memory 194640 kb
Host smart-a740c017-8987-4b6d-8755-0d242d75f808
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584737451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1584737451
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.1394139912
Short name T157
Test name
Test status
Simulation time 88985697519 ps
CPU time 630.59 seconds
Started Mar 10 01:15:29 PM PDT 24
Finished Mar 10 01:26:00 PM PDT 24
Peak memory 191548 kb
Host smart-d94f02dc-8362-4724-be61-acb39384a2f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394139912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1394139912
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1173796793
Short name T114
Test name
Test status
Simulation time 160677754789 ps
CPU time 299.22 seconds
Started Mar 10 01:15:43 PM PDT 24
Finished Mar 10 01:20:43 PM PDT 24
Peak memory 193604 kb
Host smart-92647114-581b-43b0-9310-dfd524ca064a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173796793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1173796793
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.3961911721
Short name T324
Test name
Test status
Simulation time 138842511963 ps
CPU time 666.78 seconds
Started Mar 10 01:15:49 PM PDT 24
Finished Mar 10 01:26:56 PM PDT 24
Peak memory 191604 kb
Host smart-17a30e42-6430-4a17-b31e-585396e982f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961911721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3961911721
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/160.rv_timer_random.2157991705
Short name T178
Test name
Test status
Simulation time 688398221859 ps
CPU time 411.61 seconds
Started Mar 10 01:15:55 PM PDT 24
Finished Mar 10 01:22:47 PM PDT 24
Peak memory 191612 kb
Host smart-e39644a5-59ae-4482-b89a-61c64c204384
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157991705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.2157991705
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.1081727432
Short name T251
Test name
Test status
Simulation time 244415926102 ps
CPU time 332.21 seconds
Started Mar 10 01:16:04 PM PDT 24
Finished Mar 10 01:21:36 PM PDT 24
Peak memory 191512 kb
Host smart-1f003c17-ea45-4ab6-a4cb-330c38c3de22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081727432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1081727432
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.614814168
Short name T78
Test name
Test status
Simulation time 88649926868 ps
CPU time 298.93 seconds
Started Mar 10 01:13:36 PM PDT 24
Finished Mar 10 01:18:35 PM PDT 24
Peak memory 191544 kb
Host smart-06098196-e3b6-4e0f-9fc3-14774f0b44ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614814168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.614814168
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_random.1603285464
Short name T51
Test name
Test status
Simulation time 690544065360 ps
CPU time 421.7 seconds
Started Mar 10 01:13:35 PM PDT 24
Finished Mar 10 01:20:37 PM PDT 24
Peak memory 191496 kb
Host smart-c6761c4a-2b26-4297-bbc2-ce004f5e7a87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603285464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1603285464
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2215678561
Short name T193
Test name
Test status
Simulation time 1103445804995 ps
CPU time 324.66 seconds
Started Mar 10 01:13:40 PM PDT 24
Finished Mar 10 01:19:05 PM PDT 24
Peak memory 191600 kb
Host smart-cb574238-348d-4367-be96-8f446d197f35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215678561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2215678561
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.2725721864
Short name T192
Test name
Test status
Simulation time 1168725336635 ps
CPU time 320.63 seconds
Started Mar 10 01:14:00 PM PDT 24
Finished Mar 10 01:19:21 PM PDT 24
Peak memory 183352 kb
Host smart-dab6610d-e949-4e53-8a7e-db6e25f558e6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725721864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.2725721864
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/63.rv_timer_random.3632029611
Short name T182
Test name
Test status
Simulation time 424437800106 ps
CPU time 452.62 seconds
Started Mar 10 01:14:37 PM PDT 24
Finished Mar 10 01:22:11 PM PDT 24
Peak memory 191556 kb
Host smart-e8729296-3c3a-4ef3-bd79-4230946465c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632029611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3632029611
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random.2472495170
Short name T142
Test name
Test status
Simulation time 78839332911 ps
CPU time 209.33 seconds
Started Mar 10 01:13:21 PM PDT 24
Finished Mar 10 01:16:51 PM PDT 24
Peak memory 191416 kb
Host smart-8170c337-6669-4199-bd45-40c945d19c73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472495170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2472495170
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2431953361
Short name T137
Test name
Test status
Simulation time 139479735964 ps
CPU time 73.4 seconds
Started Mar 10 01:13:13 PM PDT 24
Finished Mar 10 01:14:27 PM PDT 24
Peak memory 183328 kb
Host smart-85009dff-fc55-4ebd-858a-6a505621de31
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431953361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2431953361
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/107.rv_timer_random.2560726062
Short name T245
Test name
Test status
Simulation time 611440516854 ps
CPU time 415.27 seconds
Started Mar 10 01:15:08 PM PDT 24
Finished Mar 10 01:22:03 PM PDT 24
Peak memory 191504 kb
Host smart-932476ee-6ef1-4fdf-8a79-93ac0cedcc16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560726062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2560726062
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1155974086
Short name T244
Test name
Test status
Simulation time 340171117581 ps
CPU time 339.04 seconds
Started Mar 10 01:15:27 PM PDT 24
Finished Mar 10 01:21:06 PM PDT 24
Peak memory 191500 kb
Host smart-8315445f-eaaa-4bbb-bafb-a2193e501dd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155974086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1155974086
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.1148506698
Short name T232
Test name
Test status
Simulation time 291864444018 ps
CPU time 2172.47 seconds
Started Mar 10 01:15:32 PM PDT 24
Finished Mar 10 01:51:45 PM PDT 24
Peak memory 191532 kb
Host smart-d6032510-2c15-413f-bd20-b6c272fd7d18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148506698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1148506698
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.1532625182
Short name T160
Test name
Test status
Simulation time 144364433183 ps
CPU time 540.74 seconds
Started Mar 10 01:16:06 PM PDT 24
Finished Mar 10 01:25:07 PM PDT 24
Peak memory 191580 kb
Host smart-d81ec42c-68fc-4a88-b5f6-69b51499070a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532625182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1532625182
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.417545837
Short name T219
Test name
Test status
Simulation time 349297743711 ps
CPU time 347.61 seconds
Started Mar 10 01:16:09 PM PDT 24
Finished Mar 10 01:21:57 PM PDT 24
Peak memory 191528 kb
Host smart-15e2a971-43ba-4642-af41-ec16fd21fa38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417545837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.417545837
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.780280881
Short name T145
Test name
Test status
Simulation time 26027310204 ps
CPU time 205 seconds
Started Mar 10 01:16:25 PM PDT 24
Finished Mar 10 01:19:50 PM PDT 24
Peak memory 191428 kb
Host smart-f4871019-0c3f-4409-94da-9e74239c9263
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780280881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.780280881
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.544879790
Short name T55
Test name
Test status
Simulation time 1107209631807 ps
CPU time 481.1 seconds
Started Mar 10 01:13:23 PM PDT 24
Finished Mar 10 01:21:24 PM PDT 24
Peak memory 191504 kb
Host smart-8a776a4f-66e4-4c84-8820-2a40cc6e87d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544879790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.544879790
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.4011248184
Short name T100
Test name
Test status
Simulation time 52508124 ps
CPU time 0.88 seconds
Started Mar 10 01:12:10 PM PDT 24
Finished Mar 10 01:12:11 PM PDT 24
Peak memory 193380 kb
Host smart-1ad15620-5af3-437a-9ff3-c3688ba8405f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011248184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.4011248184
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/117.rv_timer_random.660703326
Short name T148
Test name
Test status
Simulation time 124447228343 ps
CPU time 375.48 seconds
Started Mar 10 01:15:18 PM PDT 24
Finished Mar 10 01:21:33 PM PDT 24
Peak memory 193752 kb
Host smart-7275f093-4d9a-450f-9397-ed91077c5bdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660703326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.660703326
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.4016690706
Short name T294
Test name
Test status
Simulation time 423600276945 ps
CPU time 389.09 seconds
Started Mar 10 01:15:36 PM PDT 24
Finished Mar 10 01:22:06 PM PDT 24
Peak memory 191616 kb
Host smart-05ed5451-663b-4399-93c8-f3a0bc28e0b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016690706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.4016690706
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.330277068
Short name T9
Test name
Test status
Simulation time 564083219383 ps
CPU time 892.45 seconds
Started Mar 10 01:15:35 PM PDT 24
Finished Mar 10 01:30:28 PM PDT 24
Peak memory 191604 kb
Host smart-beea2d2a-b681-433e-bd8e-976555d1aac7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330277068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.330277068
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3098717132
Short name T54
Test name
Test status
Simulation time 278835196628 ps
CPU time 119.2 seconds
Started Mar 10 01:15:42 PM PDT 24
Finished Mar 10 01:17:42 PM PDT 24
Peak memory 193968 kb
Host smart-eee08d54-2057-4e8f-9120-f9d61120425f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098717132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3098717132
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.108493223
Short name T143
Test name
Test status
Simulation time 184062283499 ps
CPU time 450.76 seconds
Started Mar 10 01:15:44 PM PDT 24
Finished Mar 10 01:23:15 PM PDT 24
Peak memory 191544 kb
Host smart-b2b1ca7b-c28f-4b42-bbc3-3237d0ec5190
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108493223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.108493223
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.780840849
Short name T295
Test name
Test status
Simulation time 255133425962 ps
CPU time 234.23 seconds
Started Mar 10 01:15:43 PM PDT 24
Finished Mar 10 01:19:37 PM PDT 24
Peak memory 191564 kb
Host smart-8d27f465-3839-41fc-a0de-8bde39401853
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780840849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.780840849
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.3331713005
Short name T283
Test name
Test status
Simulation time 319222369234 ps
CPU time 1806.64 seconds
Started Mar 10 01:15:44 PM PDT 24
Finished Mar 10 01:45:51 PM PDT 24
Peak memory 191612 kb
Host smart-10c443f7-a55a-478d-8d5f-ea7e02089c56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331713005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3331713005
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.1317245685
Short name T59
Test name
Test status
Simulation time 254699495928 ps
CPU time 130.48 seconds
Started Mar 10 01:16:00 PM PDT 24
Finished Mar 10 01:18:12 PM PDT 24
Peak memory 191432 kb
Host smart-fef089f7-6c87-42bb-89b2-0efeee00543f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317245685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1317245685
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.2641292139
Short name T224
Test name
Test status
Simulation time 71087969552 ps
CPU time 123.44 seconds
Started Mar 10 01:13:36 PM PDT 24
Finished Mar 10 01:15:40 PM PDT 24
Peak memory 183432 kb
Host smart-0f29c24e-f308-4d09-9789-6383d121b515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641292139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2641292139
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2692943
Short name T26
Test name
Test status
Simulation time 6317391498369 ps
CPU time 1864.32 seconds
Started Mar 10 01:13:36 PM PDT 24
Finished Mar 10 01:44:40 PM PDT 24
Peak memory 191540 kb
Host smart-2d290c8c-f395-4887-8564-eabe24dc8a27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.2692943
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/174.rv_timer_random.2837364185
Short name T271
Test name
Test status
Simulation time 60205491091 ps
CPU time 105.39 seconds
Started Mar 10 01:16:03 PM PDT 24
Finished Mar 10 01:17:49 PM PDT 24
Peak memory 191608 kb
Host smart-c9799a79-f538-4c94-a9c7-a08f9b21e2c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837364185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2837364185
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.708421274
Short name T360
Test name
Test status
Simulation time 157592930151 ps
CPU time 729.75 seconds
Started Mar 10 01:16:09 PM PDT 24
Finished Mar 10 01:28:19 PM PDT 24
Peak memory 191604 kb
Host smart-6f51b7be-dcbb-4436-89c1-05932890eaf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708421274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.708421274
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.2734828246
Short name T286
Test name
Test status
Simulation time 201668471067 ps
CPU time 207.41 seconds
Started Mar 10 01:16:17 PM PDT 24
Finished Mar 10 01:19:45 PM PDT 24
Peak memory 191536 kb
Host smart-42109968-4548-4616-b944-05a936e8ffdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734828246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2734828246
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.3121340705
Short name T345
Test name
Test status
Simulation time 186364420052 ps
CPU time 286.81 seconds
Started Mar 10 01:16:21 PM PDT 24
Finished Mar 10 01:21:08 PM PDT 24
Peak memory 183388 kb
Host smart-500a6b2c-e892-4ae1-82b7-3e486fbf8dc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121340705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3121340705
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.836125702
Short name T199
Test name
Test status
Simulation time 1735745378611 ps
CPU time 627.01 seconds
Started Mar 10 01:13:32 PM PDT 24
Finished Mar 10 01:23:59 PM PDT 24
Peak memory 183292 kb
Host smart-61cc1858-2190-469f-a193-f2b8299330bd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836125702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.rv_timer_cfg_update_on_fly.836125702
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2632717953
Short name T66
Test name
Test status
Simulation time 256862139921 ps
CPU time 418.52 seconds
Started Mar 10 01:13:47 PM PDT 24
Finished Mar 10 01:20:45 PM PDT 24
Peak memory 191536 kb
Host smart-87a05da5-50ed-4192-acd3-a1872847d258
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632717953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2632717953
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3098727260
Short name T342
Test name
Test status
Simulation time 166150789986 ps
CPU time 155.22 seconds
Started Mar 10 01:14:21 PM PDT 24
Finished Mar 10 01:16:56 PM PDT 24
Peak memory 194860 kb
Host smart-c16449d2-b773-4b2f-930f-70706ac4e908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098727260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3098727260
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/52.rv_timer_random.3254844832
Short name T335
Test name
Test status
Simulation time 165965333425 ps
CPU time 622.83 seconds
Started Mar 10 01:14:26 PM PDT 24
Finished Mar 10 01:24:49 PM PDT 24
Peak memory 191524 kb
Host smart-c3db0154-6eef-4bcd-861e-51cd285efb50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254844832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3254844832
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1734764311
Short name T352
Test name
Test status
Simulation time 53234057121 ps
CPU time 1259.08 seconds
Started Mar 10 01:13:25 PM PDT 24
Finished Mar 10 01:34:25 PM PDT 24
Peak memory 183400 kb
Host smart-d510d94b-7656-442d-8a5c-659cd30c0b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734764311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1734764311
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/88.rv_timer_random.1593013361
Short name T278
Test name
Test status
Simulation time 361944255689 ps
CPU time 479.17 seconds
Started Mar 10 01:14:52 PM PDT 24
Finished Mar 10 01:22:51 PM PDT 24
Peak memory 191588 kb
Host smart-a5fd08c0-cb2e-48c9-8fe4-ea6faff7b8d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593013361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1593013361
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.4010790820
Short name T301
Test name
Test status
Simulation time 74775987477 ps
CPU time 140.28 seconds
Started Mar 10 01:13:26 PM PDT 24
Finished Mar 10 01:15:46 PM PDT 24
Peak memory 183356 kb
Host smart-838f9a65-a5eb-49da-9511-e5bca1b17d24
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010790820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.4010790820
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/100.rv_timer_random.3331308147
Short name T130
Test name
Test status
Simulation time 382564488667 ps
CPU time 623.01 seconds
Started Mar 10 01:15:02 PM PDT 24
Finished Mar 10 01:25:25 PM PDT 24
Peak memory 191528 kb
Host smart-0c8f88f4-7a69-45c5-a6ec-980e6380ba8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331308147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3331308147
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.3347595559
Short name T270
Test name
Test status
Simulation time 185958457024 ps
CPU time 116.78 seconds
Started Mar 10 01:15:01 PM PDT 24
Finished Mar 10 01:16:58 PM PDT 24
Peak memory 183412 kb
Host smart-0ec937b0-311c-438e-85d8-32f69ee2fbba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347595559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3347595559
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.2038129336
Short name T306
Test name
Test status
Simulation time 2316300811855 ps
CPU time 561.62 seconds
Started Mar 10 01:15:07 PM PDT 24
Finished Mar 10 01:24:29 PM PDT 24
Peak memory 191532 kb
Host smart-c9487233-3700-471e-bc79-1802a2165582
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038129336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2038129336
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.1509282519
Short name T188
Test name
Test status
Simulation time 421457471753 ps
CPU time 350.48 seconds
Started Mar 10 01:13:27 PM PDT 24
Finished Mar 10 01:19:17 PM PDT 24
Peak memory 191520 kb
Host smart-edd232c7-8c1e-4029-b60a-3e66f85e60fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509282519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1509282519
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.929895458
Short name T338
Test name
Test status
Simulation time 647294224 ps
CPU time 0.82 seconds
Started Mar 10 01:15:27 PM PDT 24
Finished Mar 10 01:15:28 PM PDT 24
Peak memory 183020 kb
Host smart-1016f334-27a0-43c9-a018-ebc14a21e172
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929895458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.929895458
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.457939783
Short name T126
Test name
Test status
Simulation time 608238940633 ps
CPU time 1373.35 seconds
Started Mar 10 01:15:44 PM PDT 24
Finished Mar 10 01:38:38 PM PDT 24
Peak memory 191516 kb
Host smart-fda4f374-ffa4-427d-a77c-d9f99db3b6e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457939783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.457939783
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.2438790809
Short name T258
Test name
Test status
Simulation time 474298332093 ps
CPU time 348.5 seconds
Started Mar 10 01:13:43 PM PDT 24
Finished Mar 10 01:19:32 PM PDT 24
Peak memory 191588 kb
Host smart-f7f0deb2-51ce-4a5d-8143-2be5aca1223f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438790809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.2438790809
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3941305299
Short name T3
Test name
Test status
Simulation time 2507501035847 ps
CPU time 1306.83 seconds
Started Mar 10 01:13:39 PM PDT 24
Finished Mar 10 01:35:26 PM PDT 24
Peak memory 183360 kb
Host smart-7601de2c-77ff-4210-8335-d03a74334e8c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941305299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3941305299
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/180.rv_timer_random.3344549911
Short name T316
Test name
Test status
Simulation time 102601204501 ps
CPU time 67.02 seconds
Started Mar 10 01:16:10 PM PDT 24
Finished Mar 10 01:17:17 PM PDT 24
Peak memory 191512 kb
Host smart-7d841d7f-31df-418a-bfc3-16ac6e67d773
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344549911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3344549911
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.1608933478
Short name T236
Test name
Test status
Simulation time 454138542375 ps
CPU time 431.57 seconds
Started Mar 10 01:16:24 PM PDT 24
Finished Mar 10 01:23:36 PM PDT 24
Peak memory 191536 kb
Host smart-b57b61ce-36d8-4e12-8fd5-a10523f1a980
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608933478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1608933478
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.1150810672
Short name T45
Test name
Test status
Simulation time 335871767562 ps
CPU time 1002.1 seconds
Started Mar 10 01:13:17 PM PDT 24
Finished Mar 10 01:30:00 PM PDT 24
Peak memory 214264 kb
Host smart-bd443a55-ad06-4272-9dd9-ae3ea77f0546
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150810672 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.1150810672
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.3624677900
Short name T351
Test name
Test status
Simulation time 1858969216764 ps
CPU time 669.81 seconds
Started Mar 10 01:13:38 PM PDT 24
Finished Mar 10 01:24:48 PM PDT 24
Peak memory 191444 kb
Host smart-7e6aceb3-c23e-4a39-9ae3-0dd0e3881d9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624677900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.3624677900
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1223796722
Short name T214
Test name
Test status
Simulation time 753505418728 ps
CPU time 393.17 seconds
Started Mar 10 01:13:49 PM PDT 24
Finished Mar 10 01:20:22 PM PDT 24
Peak memory 183336 kb
Host smart-6b7c6716-3244-459a-a075-2ab5fad80a2d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223796722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.1223796722
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2775889100
Short name T319
Test name
Test status
Simulation time 975440352321 ps
CPU time 972.38 seconds
Started Mar 10 01:13:52 PM PDT 24
Finished Mar 10 01:30:05 PM PDT 24
Peak memory 191572 kb
Host smart-d5412f29-58b7-451f-b65c-991b8637c267
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775889100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2775889100
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_random.3469497050
Short name T292
Test name
Test status
Simulation time 95618361542 ps
CPU time 109.6 seconds
Started Mar 10 01:13:55 PM PDT 24
Finished Mar 10 01:15:45 PM PDT 24
Peak memory 191484 kb
Host smart-24cf8860-a852-41a1-b95a-77f565fb0634
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469497050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3469497050
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.232974631
Short name T317
Test name
Test status
Simulation time 111951860407 ps
CPU time 41.41 seconds
Started Mar 10 01:13:55 PM PDT 24
Finished Mar 10 01:14:37 PM PDT 24
Peak memory 191468 kb
Host smart-ef349dc0-0570-438c-aca4-26e14d870923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232974631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.232974631
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.4006698128
Short name T194
Test name
Test status
Simulation time 112554637038 ps
CPU time 187.12 seconds
Started Mar 10 01:13:56 PM PDT 24
Finished Mar 10 01:17:04 PM PDT 24
Peak memory 183404 kb
Host smart-c7304a8a-774b-4714-be16-d9a63698fb8a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006698128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.4006698128
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3880801374
Short name T179
Test name
Test status
Simulation time 70059071812 ps
CPU time 253.43 seconds
Started Mar 10 01:13:56 PM PDT 24
Finished Mar 10 01:18:09 PM PDT 24
Peak memory 191636 kb
Host smart-7641c30b-c8ac-4d65-9078-f44bd4eaba2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880801374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3880801374
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.1892228685
Short name T241
Test name
Test status
Simulation time 315324877136 ps
CPU time 574 seconds
Started Mar 10 01:14:42 PM PDT 24
Finished Mar 10 01:24:16 PM PDT 24
Peak memory 191600 kb
Host smart-9171ebb5-a4c5-4316-8344-0fbf8129ad4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892228685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.1892228685
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.1256317415
Short name T330
Test name
Test status
Simulation time 313960801542 ps
CPU time 180.09 seconds
Started Mar 10 01:14:43 PM PDT 24
Finished Mar 10 01:17:43 PM PDT 24
Peak memory 194188 kb
Host smart-f2a4251d-a0d1-4fe4-9ef8-a34e11ce233b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256317415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1256317415
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.1514586551
Short name T154
Test name
Test status
Simulation time 2012077787713 ps
CPU time 574.61 seconds
Started Mar 10 01:14:47 PM PDT 24
Finished Mar 10 01:24:21 PM PDT 24
Peak memory 191592 kb
Host smart-dab911fd-22ff-48a5-a57b-a22937d5f546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514586551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1514586551
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2878248446
Short name T263
Test name
Test status
Simulation time 32776009001 ps
CPU time 238.03 seconds
Started Mar 10 01:14:52 PM PDT 24
Finished Mar 10 01:18:50 PM PDT 24
Peak memory 191480 kb
Host smart-c6542a71-504d-4ed8-97f3-bbcf1dff097d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878248446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2878248446
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1988054301
Short name T89
Test name
Test status
Simulation time 55643727 ps
CPU time 0.81 seconds
Started Mar 10 01:12:12 PM PDT 24
Finished Mar 10 01:12:13 PM PDT 24
Peak memory 192332 kb
Host smart-5561d3c8-8c28-4509-897e-a6f6f1d02a32
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988054301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.1988054301
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1871889848
Short name T73
Test name
Test status
Simulation time 400038380 ps
CPU time 3.36 seconds
Started Mar 10 01:12:13 PM PDT 24
Finished Mar 10 01:12:17 PM PDT 24
Peak memory 182988 kb
Host smart-5a6de56d-f021-46a2-a3dc-0b92540fec2f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871889848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.1871889848
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1417436787
Short name T61
Test name
Test status
Simulation time 24366327 ps
CPU time 0.54 seconds
Started Mar 10 01:12:09 PM PDT 24
Finished Mar 10 01:12:10 PM PDT 24
Peak memory 182060 kb
Host smart-4bf03435-8bd3-4697-a48f-753356de24dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417436787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.1417436787
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.738665261
Short name T62
Test name
Test status
Simulation time 75118563 ps
CPU time 0.86 seconds
Started Mar 10 01:12:11 PM PDT 24
Finished Mar 10 01:12:12 PM PDT 24
Peak memory 195576 kb
Host smart-21537c51-6c73-47ae-87cd-18f19b3024b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738665261 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.738665261
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.592527375
Short name T514
Test name
Test status
Simulation time 12239195 ps
CPU time 0.56 seconds
Started Mar 10 01:12:10 PM PDT 24
Finished Mar 10 01:12:11 PM PDT 24
Peak memory 182692 kb
Host smart-78085ade-649c-4273-b6f1-d7e2b6e61263
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592527375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.592527375
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3444975646
Short name T534
Test name
Test status
Simulation time 19415987 ps
CPU time 0.56 seconds
Started Mar 10 01:12:13 PM PDT 24
Finished Mar 10 01:12:14 PM PDT 24
Peak memory 182496 kb
Host smart-21c395a9-5ed5-474d-826b-6670eef60c9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444975646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3444975646
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3064309113
Short name T475
Test name
Test status
Simulation time 74058453 ps
CPU time 1.14 seconds
Started Mar 10 01:12:13 PM PDT 24
Finished Mar 10 01:12:15 PM PDT 24
Peak memory 197124 kb
Host smart-f8461717-5372-42d2-89f1-899247ee3e22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064309113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3064309113
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1168435549
Short name T571
Test name
Test status
Simulation time 98946477 ps
CPU time 1.13 seconds
Started Mar 10 01:12:08 PM PDT 24
Finished Mar 10 01:12:09 PM PDT 24
Peak memory 195188 kb
Host smart-1972099d-50f8-41f7-84e8-fee99d0a9795
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168435549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1168435549
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2742603100
Short name T91
Test name
Test status
Simulation time 36248609 ps
CPU time 0.65 seconds
Started Mar 10 01:12:11 PM PDT 24
Finished Mar 10 01:12:12 PM PDT 24
Peak memory 182772 kb
Host smart-382cfa16-a68c-4f7a-bb2b-af1c721de1ec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742603100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.2742603100
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.4080602254
Short name T540
Test name
Test status
Simulation time 2441973105 ps
CPU time 2.66 seconds
Started Mar 10 01:12:10 PM PDT 24
Finished Mar 10 01:12:13 PM PDT 24
Peak memory 191172 kb
Host smart-143426cd-3423-4fd2-b671-3a72ade5e5aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080602254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.4080602254
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1133233873
Short name T485
Test name
Test status
Simulation time 18231654 ps
CPU time 0.56 seconds
Started Mar 10 01:12:10 PM PDT 24
Finished Mar 10 01:12:11 PM PDT 24
Peak memory 182688 kb
Host smart-17663574-5dfb-44ed-9bdb-ec6f783418b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133233873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1133233873
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2422392835
Short name T458
Test name
Test status
Simulation time 48822370 ps
CPU time 0.75 seconds
Started Mar 10 01:12:12 PM PDT 24
Finished Mar 10 01:12:13 PM PDT 24
Peak memory 194912 kb
Host smart-d877a36e-e267-41e0-be71-5055cb849229
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422392835 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2422392835
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2418001886
Short name T471
Test name
Test status
Simulation time 18277999 ps
CPU time 0.6 seconds
Started Mar 10 01:12:10 PM PDT 24
Finished Mar 10 01:12:11 PM PDT 24
Peak memory 191928 kb
Host smart-e240e50b-6658-47c8-93d4-d9e48f7f7973
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418001886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2418001886
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1173196883
Short name T457
Test name
Test status
Simulation time 13665429 ps
CPU time 0.58 seconds
Started Mar 10 01:12:10 PM PDT 24
Finished Mar 10 01:12:11 PM PDT 24
Peak memory 182620 kb
Host smart-6f3edb50-0ac0-4506-9ad7-814b3c79e5f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173196883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.1173196883
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4220692877
Short name T518
Test name
Test status
Simulation time 183074091 ps
CPU time 0.61 seconds
Started Mar 10 01:12:09 PM PDT 24
Finished Mar 10 01:12:10 PM PDT 24
Peak memory 191416 kb
Host smart-fa301b9b-6c23-442a-b4a3-9bcfc187cfa7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220692877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.4220692877
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3958149592
Short name T491
Test name
Test status
Simulation time 308640103 ps
CPU time 3 seconds
Started Mar 10 01:12:11 PM PDT 24
Finished Mar 10 01:12:14 PM PDT 24
Peak memory 197600 kb
Host smart-2d4b4940-63e1-4625-a389-4f81914c4286
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958149592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3958149592
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3102775289
Short name T511
Test name
Test status
Simulation time 38260040 ps
CPU time 0.82 seconds
Started Mar 10 01:12:13 PM PDT 24
Finished Mar 10 01:12:14 PM PDT 24
Peak memory 182916 kb
Host smart-d499cf40-ba22-40bf-849b-17bb9da65547
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102775289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3102775289
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1666121695
Short name T49
Test name
Test status
Simulation time 73684374 ps
CPU time 0.75 seconds
Started Mar 10 01:12:24 PM PDT 24
Finished Mar 10 01:12:26 PM PDT 24
Peak memory 195572 kb
Host smart-16c4771b-0b85-4803-99aa-40e979d9152c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666121695 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.1666121695
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2795312355
Short name T572
Test name
Test status
Simulation time 26654895 ps
CPU time 0.6 seconds
Started Mar 10 01:12:24 PM PDT 24
Finished Mar 10 01:12:25 PM PDT 24
Peak memory 182676 kb
Host smart-1236b18c-7474-4a7c-8676-073bd0e1ed8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795312355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2795312355
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1831622125
Short name T462
Test name
Test status
Simulation time 68494008 ps
CPU time 0.55 seconds
Started Mar 10 01:12:23 PM PDT 24
Finished Mar 10 01:12:24 PM PDT 24
Peak memory 182516 kb
Host smart-a0e91797-ba39-447c-a56b-8f7517ae4d33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831622125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1831622125
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.235676590
Short name T579
Test name
Test status
Simulation time 20235373 ps
CPU time 0.73 seconds
Started Mar 10 01:12:27 PM PDT 24
Finished Mar 10 01:12:27 PM PDT 24
Peak memory 193276 kb
Host smart-305f45de-4e8d-4312-a5a8-22632cd8f67c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235676590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_ti
mer_same_csr_outstanding.235676590
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.4276698263
Short name T547
Test name
Test status
Simulation time 55781751 ps
CPU time 2.73 seconds
Started Mar 10 01:12:24 PM PDT 24
Finished Mar 10 01:12:27 PM PDT 24
Peak memory 197592 kb
Host smart-8f02c6be-a7b9-47c4-8329-e8105a398e43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276698263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.4276698263
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.4015400091
Short name T544
Test name
Test status
Simulation time 159121983 ps
CPU time 0.78 seconds
Started Mar 10 01:12:26 PM PDT 24
Finished Mar 10 01:12:27 PM PDT 24
Peak memory 182904 kb
Host smart-bb2101b0-bd88-43e3-bac5-21b57854845a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015400091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.4015400091
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3649945985
Short name T498
Test name
Test status
Simulation time 232400346 ps
CPU time 0.73 seconds
Started Mar 10 01:12:25 PM PDT 24
Finished Mar 10 01:12:26 PM PDT 24
Peak memory 195112 kb
Host smart-efb8045b-7691-4de4-8185-5dbdf53e3da4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649945985 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.3649945985
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3973041072
Short name T466
Test name
Test status
Simulation time 59724657 ps
CPU time 0.61 seconds
Started Mar 10 01:12:22 PM PDT 24
Finished Mar 10 01:12:23 PM PDT 24
Peak memory 182712 kb
Host smart-9d09f88f-26ad-422c-b38a-44249895cba2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973041072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3973041072
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2514239458
Short name T468
Test name
Test status
Simulation time 24180098 ps
CPU time 0.61 seconds
Started Mar 10 01:12:22 PM PDT 24
Finished Mar 10 01:12:23 PM PDT 24
Peak memory 182504 kb
Host smart-087ad541-8e80-4ebb-b0ab-a5d4392f3561
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514239458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2514239458
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2025330192
Short name T98
Test name
Test status
Simulation time 17544506 ps
CPU time 0.62 seconds
Started Mar 10 01:12:24 PM PDT 24
Finished Mar 10 01:12:26 PM PDT 24
Peak memory 191412 kb
Host smart-38d6e74c-0f0b-4235-b27d-e84379893292
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025330192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2025330192
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.922739335
Short name T482
Test name
Test status
Simulation time 184412016 ps
CPU time 2.68 seconds
Started Mar 10 01:12:20 PM PDT 24
Finished Mar 10 01:12:23 PM PDT 24
Peak memory 197588 kb
Host smart-4de79237-f2e9-4aad-bf1c-4d124afe22be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922739335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.922739335
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3449724249
Short name T520
Test name
Test status
Simulation time 83335363 ps
CPU time 1.09 seconds
Started Mar 10 01:12:29 PM PDT 24
Finished Mar 10 01:12:31 PM PDT 24
Peak memory 183348 kb
Host smart-b60947a9-e25b-42d8-8430-467322b360d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449724249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3449724249
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3369554442
Short name T500
Test name
Test status
Simulation time 35961641 ps
CPU time 0.86 seconds
Started Mar 10 01:12:21 PM PDT 24
Finished Mar 10 01:12:22 PM PDT 24
Peak memory 196368 kb
Host smart-1dec3079-57d4-4a4c-b3a9-e735b13d9ac0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369554442 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3369554442
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2132977383
Short name T90
Test name
Test status
Simulation time 41840974 ps
CPU time 0.55 seconds
Started Mar 10 01:12:21 PM PDT 24
Finished Mar 10 01:12:22 PM PDT 24
Peak memory 182404 kb
Host smart-386bbd3f-2a93-4000-8e1b-afb94cd5d9c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132977383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2132977383
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2044744141
Short name T552
Test name
Test status
Simulation time 29318745 ps
CPU time 0.59 seconds
Started Mar 10 01:12:24 PM PDT 24
Finished Mar 10 01:12:25 PM PDT 24
Peak memory 182560 kb
Host smart-7c62dfc3-17f8-4de6-80c4-ac636cc24edc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044744141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2044744141
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1227297527
Short name T558
Test name
Test status
Simulation time 74320088 ps
CPU time 0.63 seconds
Started Mar 10 01:12:21 PM PDT 24
Finished Mar 10 01:12:22 PM PDT 24
Peak memory 191488 kb
Host smart-912a3d62-b676-4348-bdf0-d5c2475f1101
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227297527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1227297527
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2856819232
Short name T470
Test name
Test status
Simulation time 119688216 ps
CPU time 2.44 seconds
Started Mar 10 01:12:25 PM PDT 24
Finished Mar 10 01:12:28 PM PDT 24
Peak memory 197512 kb
Host smart-948b370d-e534-4e42-a867-f49c4a36ce7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856819232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2856819232
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.4120329142
Short name T532
Test name
Test status
Simulation time 165995513 ps
CPU time 1.11 seconds
Started Mar 10 01:12:23 PM PDT 24
Finished Mar 10 01:12:25 PM PDT 24
Peak memory 183252 kb
Host smart-898c7db8-1300-4a16-a6db-8935b25384c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120329142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.4120329142
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.811296335
Short name T504
Test name
Test status
Simulation time 68826779 ps
CPU time 0.96 seconds
Started Mar 10 01:12:31 PM PDT 24
Finished Mar 10 01:12:32 PM PDT 24
Peak memory 197044 kb
Host smart-40dace17-f51a-4f45-8db6-1cd644499737
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811296335 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.811296335
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2665362403
Short name T87
Test name
Test status
Simulation time 14273195 ps
CPU time 0.56 seconds
Started Mar 10 01:12:29 PM PDT 24
Finished Mar 10 01:12:30 PM PDT 24
Peak memory 182688 kb
Host smart-001719e4-216f-4626-99a9-5784351fc1ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665362403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2665362403
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.274162091
Short name T483
Test name
Test status
Simulation time 14019537 ps
CPU time 0.59 seconds
Started Mar 10 01:12:26 PM PDT 24
Finished Mar 10 01:12:27 PM PDT 24
Peak memory 181888 kb
Host smart-62fd395e-a101-4ffb-8d18-2715275eea86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274162091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.274162091
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2123569564
Short name T566
Test name
Test status
Simulation time 46814599 ps
CPU time 0.73 seconds
Started Mar 10 01:12:26 PM PDT 24
Finished Mar 10 01:12:27 PM PDT 24
Peak memory 191736 kb
Host smart-9b28a167-470b-4de4-8a2d-562a3add3862
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123569564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2123569564
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.533952643
Short name T522
Test name
Test status
Simulation time 774040467 ps
CPU time 2.17 seconds
Started Mar 10 01:12:24 PM PDT 24
Finished Mar 10 01:12:27 PM PDT 24
Peak memory 197596 kb
Host smart-d9438e2d-11f4-4283-b3eb-5a54275e8d74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533952643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.533952643
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1512240629
Short name T580
Test name
Test status
Simulation time 112656293 ps
CPU time 0.85 seconds
Started Mar 10 01:12:28 PM PDT 24
Finished Mar 10 01:12:29 PM PDT 24
Peak memory 193552 kb
Host smart-7ee68a73-1a74-469b-af4b-1b19b1a5d30b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512240629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1512240629
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.64568502
Short name T507
Test name
Test status
Simulation time 36512986 ps
CPU time 0.9 seconds
Started Mar 10 01:12:26 PM PDT 24
Finished Mar 10 01:12:27 PM PDT 24
Peak memory 197016 kb
Host smart-51389cab-2ca2-4db8-a232-888816de0682
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64568502 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.64568502
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.788578944
Short name T543
Test name
Test status
Simulation time 14083865 ps
CPU time 0.57 seconds
Started Mar 10 01:12:29 PM PDT 24
Finished Mar 10 01:12:30 PM PDT 24
Peak memory 182744 kb
Host smart-4659e83c-acf3-4ffb-9dba-2e8438336672
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788578944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.788578944
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.974425921
Short name T512
Test name
Test status
Simulation time 13546816 ps
CPU time 0.54 seconds
Started Mar 10 01:12:28 PM PDT 24
Finished Mar 10 01:12:29 PM PDT 24
Peak memory 182128 kb
Host smart-0d0dfd26-3197-4bce-939e-8340a6393612
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974425921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.974425921
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3990384771
Short name T76
Test name
Test status
Simulation time 45610299 ps
CPU time 0.72 seconds
Started Mar 10 01:12:25 PM PDT 24
Finished Mar 10 01:12:26 PM PDT 24
Peak memory 193320 kb
Host smart-689a01c2-7775-45f8-b93d-47e9a587fd4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990384771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3990384771
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2208186827
Short name T480
Test name
Test status
Simulation time 133046230 ps
CPU time 2.62 seconds
Started Mar 10 01:12:26 PM PDT 24
Finished Mar 10 01:12:29 PM PDT 24
Peak memory 197584 kb
Host smart-bc307ee5-c092-40ed-9ef9-a03616602093
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208186827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2208186827
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.166024166
Short name T29
Test name
Test status
Simulation time 287543036 ps
CPU time 0.86 seconds
Started Mar 10 01:12:25 PM PDT 24
Finished Mar 10 01:12:26 PM PDT 24
Peak memory 193440 kb
Host smart-020f820f-dfdc-4ec3-9712-d92843df6f50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166024166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_in
tg_err.166024166
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.128305935
Short name T541
Test name
Test status
Simulation time 29011022 ps
CPU time 1.3 seconds
Started Mar 10 01:12:28 PM PDT 24
Finished Mar 10 01:12:30 PM PDT 24
Peak memory 197576 kb
Host smart-8c593d4a-ede9-4893-b68d-164673b2f90f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128305935 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.128305935
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.839162019
Short name T564
Test name
Test status
Simulation time 43002469 ps
CPU time 0.56 seconds
Started Mar 10 01:12:30 PM PDT 24
Finished Mar 10 01:12:30 PM PDT 24
Peak memory 182376 kb
Host smart-63375828-f7d9-4f22-a8e0-70c63f671e27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839162019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.839162019
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.434741637
Short name T495
Test name
Test status
Simulation time 17632534 ps
CPU time 0.54 seconds
Started Mar 10 01:12:30 PM PDT 24
Finished Mar 10 01:12:30 PM PDT 24
Peak memory 182028 kb
Host smart-d13fb8c4-b345-454b-9d3a-b262d0e7998f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434741637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.434741637
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3490882622
Short name T524
Test name
Test status
Simulation time 16839638 ps
CPU time 0.69 seconds
Started Mar 10 01:12:24 PM PDT 24
Finished Mar 10 01:12:26 PM PDT 24
Peak memory 191660 kb
Host smart-d00d8773-92b4-46e0-bae7-98b8b14eacb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490882622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3490882622
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3873436265
Short name T47
Test name
Test status
Simulation time 184802910 ps
CPU time 1.03 seconds
Started Mar 10 01:12:27 PM PDT 24
Finished Mar 10 01:12:28 PM PDT 24
Peak memory 196056 kb
Host smart-a024b287-2920-41fb-9d17-58f68c4b51e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873436265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3873436265
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3406140472
Short name T103
Test name
Test status
Simulation time 116920513 ps
CPU time 1.4 seconds
Started Mar 10 01:12:24 PM PDT 24
Finished Mar 10 01:12:26 PM PDT 24
Peak memory 195212 kb
Host smart-dc67c43d-abfd-4553-b262-a43333817c32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406140472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3406140472
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3982813338
Short name T479
Test name
Test status
Simulation time 31008527 ps
CPU time 0.9 seconds
Started Mar 10 01:12:27 PM PDT 24
Finished Mar 10 01:12:28 PM PDT 24
Peak memory 196440 kb
Host smart-391f4240-bc93-4101-8bec-57c9af467a06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982813338 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3982813338
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3026462014
Short name T32
Test name
Test status
Simulation time 14690579 ps
CPU time 0.58 seconds
Started Mar 10 01:12:33 PM PDT 24
Finished Mar 10 01:12:34 PM PDT 24
Peak memory 182748 kb
Host smart-5f725343-5988-4ec8-a1fb-3bc61a653b38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026462014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3026462014
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3648091334
Short name T525
Test name
Test status
Simulation time 58104511 ps
CPU time 0.56 seconds
Started Mar 10 01:12:26 PM PDT 24
Finished Mar 10 01:12:27 PM PDT 24
Peak memory 182584 kb
Host smart-881fce89-0341-4c20-a3a3-fe41b5cbfd71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648091334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3648091334
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1103376004
Short name T568
Test name
Test status
Simulation time 33129419 ps
CPU time 0.75 seconds
Started Mar 10 01:12:26 PM PDT 24
Finished Mar 10 01:12:27 PM PDT 24
Peak memory 193068 kb
Host smart-68485aeb-fa0b-4c70-8673-1e264c15e642
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103376004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1103376004
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2317756249
Short name T494
Test name
Test status
Simulation time 58024979 ps
CPU time 1.45 seconds
Started Mar 10 01:12:28 PM PDT 24
Finished Mar 10 01:12:30 PM PDT 24
Peak memory 197612 kb
Host smart-2cd46990-9ee4-4c8f-95a5-aad9aeea6617
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317756249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2317756249
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.963554590
Short name T550
Test name
Test status
Simulation time 87440994 ps
CPU time 0.83 seconds
Started Mar 10 01:12:28 PM PDT 24
Finished Mar 10 01:12:29 PM PDT 24
Peak memory 193672 kb
Host smart-d24b3ff0-5d95-478a-abfd-97209b652bf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963554590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.963554590
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2461290072
Short name T535
Test name
Test status
Simulation time 126522648 ps
CPU time 0.93 seconds
Started Mar 10 01:12:31 PM PDT 24
Finished Mar 10 01:12:32 PM PDT 24
Peak memory 196508 kb
Host smart-de1e8c1d-b6ab-4e2c-910b-5e9d92ecfe05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461290072 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2461290072
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1600247712
Short name T574
Test name
Test status
Simulation time 17145712 ps
CPU time 0.65 seconds
Started Mar 10 01:12:28 PM PDT 24
Finished Mar 10 01:12:29 PM PDT 24
Peak memory 182668 kb
Host smart-c0739fca-0ab8-46c8-937d-21651eb20ab6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600247712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1600247712
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.501605332
Short name T474
Test name
Test status
Simulation time 20343902 ps
CPU time 0.54 seconds
Started Mar 10 01:12:28 PM PDT 24
Finished Mar 10 01:12:29 PM PDT 24
Peak memory 182184 kb
Host smart-b8405a9e-a526-49a5-9f5d-ec2385e5e1b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501605332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.501605332
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.283629286
Short name T530
Test name
Test status
Simulation time 36965125 ps
CPU time 0.81 seconds
Started Mar 10 01:12:33 PM PDT 24
Finished Mar 10 01:12:34 PM PDT 24
Peak memory 193404 kb
Host smart-b370b190-849c-476b-a110-e5ef5e9404cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283629286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti
mer_same_csr_outstanding.283629286
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.75106909
Short name T467
Test name
Test status
Simulation time 34511909 ps
CPU time 1.03 seconds
Started Mar 10 01:12:26 PM PDT 24
Finished Mar 10 01:12:27 PM PDT 24
Peak memory 197420 kb
Host smart-8e57505e-2ebc-4109-920c-a421d6354d1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75106909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.75106909
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2195973323
Short name T578
Test name
Test status
Simulation time 230142585 ps
CPU time 1.12 seconds
Started Mar 10 01:12:25 PM PDT 24
Finished Mar 10 01:12:27 PM PDT 24
Peak memory 195168 kb
Host smart-38c4d3c1-7036-45c3-af5c-a7c11a0eb6db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195973323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2195973323
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2740949731
Short name T576
Test name
Test status
Simulation time 42086899 ps
CPU time 0.85 seconds
Started Mar 10 01:12:29 PM PDT 24
Finished Mar 10 01:12:30 PM PDT 24
Peak memory 197000 kb
Host smart-5a44cda9-008b-459f-9613-fdd12c79eac6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740949731 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.2740949731
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3179228201
Short name T88
Test name
Test status
Simulation time 45985772 ps
CPU time 0.58 seconds
Started Mar 10 01:12:28 PM PDT 24
Finished Mar 10 01:12:29 PM PDT 24
Peak memory 182304 kb
Host smart-a4a25888-5cd0-45ff-9b61-1627f712f08d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179228201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3179228201
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1053111343
Short name T459
Test name
Test status
Simulation time 43315529 ps
CPU time 0.53 seconds
Started Mar 10 01:12:28 PM PDT 24
Finished Mar 10 01:12:29 PM PDT 24
Peak memory 181964 kb
Host smart-dc8c655a-2ad3-4442-aa4d-ebc61a5b4192
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053111343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1053111343
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.41917354
Short name T94
Test name
Test status
Simulation time 24405428 ps
CPU time 0.69 seconds
Started Mar 10 01:12:27 PM PDT 24
Finished Mar 10 01:12:27 PM PDT 24
Peak memory 191936 kb
Host smart-2367b0e2-9feb-4154-a7c0-4a7a03bd9920
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41917354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_tim
er_same_csr_outstanding.41917354
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.4059660826
Short name T536
Test name
Test status
Simulation time 217734580 ps
CPU time 1.34 seconds
Started Mar 10 01:12:27 PM PDT 24
Finished Mar 10 01:12:29 PM PDT 24
Peak memory 196540 kb
Host smart-4de11fa0-de5b-4ae8-a030-b51d90c8ae77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059660826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.4059660826
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.387629339
Short name T539
Test name
Test status
Simulation time 45480815 ps
CPU time 0.81 seconds
Started Mar 10 01:12:28 PM PDT 24
Finished Mar 10 01:12:29 PM PDT 24
Peak memory 183180 kb
Host smart-ec79afec-3a3d-42b4-beb1-b8c37c0ca092
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387629339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_in
tg_err.387629339
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.988903076
Short name T463
Test name
Test status
Simulation time 19546129 ps
CPU time 0.8 seconds
Started Mar 10 01:12:34 PM PDT 24
Finished Mar 10 01:12:35 PM PDT 24
Peak memory 195904 kb
Host smart-5e44aa57-b47e-4709-b99b-ae8b5b820fd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988903076 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.988903076
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2262133682
Short name T506
Test name
Test status
Simulation time 87921015 ps
CPU time 0.61 seconds
Started Mar 10 01:12:31 PM PDT 24
Finished Mar 10 01:12:32 PM PDT 24
Peak memory 182748 kb
Host smart-03046601-30db-4662-bf94-baac2d618f45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262133682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2262133682
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3067426998
Short name T556
Test name
Test status
Simulation time 15911195 ps
CPU time 0.55 seconds
Started Mar 10 01:12:26 PM PDT 24
Finished Mar 10 01:12:26 PM PDT 24
Peak memory 182452 kb
Host smart-86f81da4-0981-46b5-8326-fa0e4d747df8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067426998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3067426998
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3353854116
Short name T77
Test name
Test status
Simulation time 96260598 ps
CPU time 0.74 seconds
Started Mar 10 01:12:33 PM PDT 24
Finished Mar 10 01:12:34 PM PDT 24
Peak memory 191744 kb
Host smart-39df1655-934c-43d8-88c4-bd096581f899
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353854116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3353854116
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3703872978
Short name T490
Test name
Test status
Simulation time 24942059 ps
CPU time 1.24 seconds
Started Mar 10 01:12:24 PM PDT 24
Finished Mar 10 01:12:26 PM PDT 24
Peak memory 197512 kb
Host smart-fe31f810-76cc-4bcf-b8d4-78a617e8746d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703872978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3703872978
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2841536207
Short name T573
Test name
Test status
Simulation time 76420017 ps
CPU time 1.07 seconds
Started Mar 10 01:12:26 PM PDT 24
Finished Mar 10 01:12:27 PM PDT 24
Peak memory 183336 kb
Host smart-d5a28b72-2822-4dbc-9328-ffbca3d9c195
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841536207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2841536207
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1572580
Short name T74
Test name
Test status
Simulation time 51213317 ps
CPU time 0.71 seconds
Started Mar 10 01:12:17 PM PDT 24
Finished Mar 10 01:12:17 PM PDT 24
Peak memory 192400 kb
Host smart-2c0d644c-70f8-4b2b-8336-c5bd38b337ac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_aliasin
g.1572580
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3499160357
Short name T521
Test name
Test status
Simulation time 219624817 ps
CPU time 1.61 seconds
Started Mar 10 01:12:22 PM PDT 24
Finished Mar 10 01:12:24 PM PDT 24
Peak memory 191084 kb
Host smart-ad8f6878-71ae-418b-93f8-6b0df16639cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499160357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.3499160357
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.8234357
Short name T542
Test name
Test status
Simulation time 53915846 ps
CPU time 0.6 seconds
Started Mar 10 01:12:15 PM PDT 24
Finished Mar 10 01:12:16 PM PDT 24
Peak memory 191916 kb
Host smart-06293792-e50e-48d8-a979-8322f1d9c01d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8234357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_rese
t.8234357
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.881344994
Short name T546
Test name
Test status
Simulation time 28871092 ps
CPU time 0.75 seconds
Started Mar 10 01:12:21 PM PDT 24
Finished Mar 10 01:12:22 PM PDT 24
Peak memory 195064 kb
Host smart-75cbe435-f9ef-405a-8b08-23fdcf92e47d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881344994 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.881344994
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2108581987
Short name T92
Test name
Test status
Simulation time 16530445 ps
CPU time 0.57 seconds
Started Mar 10 01:12:16 PM PDT 24
Finished Mar 10 01:12:17 PM PDT 24
Peak memory 182656 kb
Host smart-0ba12d1c-017f-49d9-bda0-8c21ad5522b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108581987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2108581987
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.621058269
Short name T488
Test name
Test status
Simulation time 11493024 ps
CPU time 0.53 seconds
Started Mar 10 01:12:16 PM PDT 24
Finished Mar 10 01:12:16 PM PDT 24
Peak memory 181872 kb
Host smart-414b5c46-3f47-40be-8d2f-221fc9a61e04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621058269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.621058269
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.595711832
Short name T95
Test name
Test status
Simulation time 55285473 ps
CPU time 0.63 seconds
Started Mar 10 01:12:19 PM PDT 24
Finished Mar 10 01:12:20 PM PDT 24
Peak memory 191928 kb
Host smart-02770bc3-dcae-4418-afb1-c3911312a7aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595711832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_tim
er_same_csr_outstanding.595711832
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.497886226
Short name T563
Test name
Test status
Simulation time 495107524 ps
CPU time 2.31 seconds
Started Mar 10 01:12:17 PM PDT 24
Finished Mar 10 01:12:19 PM PDT 24
Peak memory 197552 kb
Host smart-a9eae353-d8bf-45fd-b9d7-ddec81a26997
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497886226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.497886226
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.4158390942
Short name T510
Test name
Test status
Simulation time 128402893 ps
CPU time 0.88 seconds
Started Mar 10 01:12:16 PM PDT 24
Finished Mar 10 01:12:17 PM PDT 24
Peak memory 193232 kb
Host smart-4443704a-3f66-456a-bae8-8a874c248be6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158390942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.4158390942
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1836230371
Short name T487
Test name
Test status
Simulation time 47401917 ps
CPU time 0.6 seconds
Started Mar 10 01:12:31 PM PDT 24
Finished Mar 10 01:12:32 PM PDT 24
Peak memory 182536 kb
Host smart-144b47ac-0c52-49e4-98bd-b543b58b714b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836230371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1836230371
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2118503477
Short name T477
Test name
Test status
Simulation time 46198649 ps
CPU time 0.55 seconds
Started Mar 10 01:12:30 PM PDT 24
Finished Mar 10 01:12:31 PM PDT 24
Peak memory 182488 kb
Host smart-811912ca-1c05-4c3f-b4bd-441140c42e24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118503477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.2118503477
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1147107479
Short name T517
Test name
Test status
Simulation time 184468641 ps
CPU time 0.52 seconds
Started Mar 10 01:12:31 PM PDT 24
Finished Mar 10 01:12:32 PM PDT 24
Peak memory 181956 kb
Host smart-e7f3d16e-74ea-452a-b16a-bdc10b5ae2e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147107479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.1147107479
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2815744731
Short name T561
Test name
Test status
Simulation time 16943997 ps
CPU time 0.53 seconds
Started Mar 10 01:12:34 PM PDT 24
Finished Mar 10 01:12:35 PM PDT 24
Peak memory 182572 kb
Host smart-d9cb7ada-270c-4785-99c6-793196d0586e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815744731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2815744731
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1777064393
Short name T516
Test name
Test status
Simulation time 45580292 ps
CPU time 0.55 seconds
Started Mar 10 01:12:30 PM PDT 24
Finished Mar 10 01:12:31 PM PDT 24
Peak memory 182584 kb
Host smart-d7ff61ae-7d7c-4797-9b84-088dd813207a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777064393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1777064393
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3138716555
Short name T476
Test name
Test status
Simulation time 43010154 ps
CPU time 0.57 seconds
Started Mar 10 01:12:31 PM PDT 24
Finished Mar 10 01:12:32 PM PDT 24
Peak memory 182536 kb
Host smart-f26d2675-0668-42c1-9b1e-c94662d72a35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138716555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3138716555
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3185444430
Short name T461
Test name
Test status
Simulation time 42916107 ps
CPU time 0.59 seconds
Started Mar 10 01:12:32 PM PDT 24
Finished Mar 10 01:12:32 PM PDT 24
Peak memory 182572 kb
Host smart-ae244dae-31fc-488f-91c9-f51affd869e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185444430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.3185444430
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.787019899
Short name T567
Test name
Test status
Simulation time 11109102 ps
CPU time 0.57 seconds
Started Mar 10 01:12:34 PM PDT 24
Finished Mar 10 01:12:35 PM PDT 24
Peak memory 182480 kb
Host smart-a5c5c112-ac08-4f98-a6db-3a13290c3466
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787019899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.787019899
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1358834431
Short name T554
Test name
Test status
Simulation time 12586879 ps
CPU time 0.53 seconds
Started Mar 10 01:12:31 PM PDT 24
Finished Mar 10 01:12:31 PM PDT 24
Peak memory 182556 kb
Host smart-ad51f369-0c95-406f-ae27-df28bc2abf4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358834431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1358834431
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1493222349
Short name T478
Test name
Test status
Simulation time 22544982 ps
CPU time 0.56 seconds
Started Mar 10 01:12:33 PM PDT 24
Finished Mar 10 01:12:34 PM PDT 24
Peak memory 182448 kb
Host smart-2f74645b-f1b4-4e42-9f88-61863eee8fea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493222349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1493222349
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1528146153
Short name T489
Test name
Test status
Simulation time 537409092 ps
CPU time 1.69 seconds
Started Mar 10 01:12:22 PM PDT 24
Finished Mar 10 01:12:24 PM PDT 24
Peak memory 183044 kb
Host smart-b1d35783-a7d0-4e97-96e0-734b0b4d0b12
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528146153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.1528146153
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3018526931
Short name T493
Test name
Test status
Simulation time 15010758 ps
CPU time 0.55 seconds
Started Mar 10 01:12:20 PM PDT 24
Finished Mar 10 01:12:21 PM PDT 24
Peak memory 182792 kb
Host smart-d09dd403-88ec-4ff8-8144-75648f9731d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018526931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3018526931
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.167677100
Short name T528
Test name
Test status
Simulation time 26911067 ps
CPU time 1.28 seconds
Started Mar 10 01:12:14 PM PDT 24
Finished Mar 10 01:12:16 PM PDT 24
Peak memory 197588 kb
Host smart-89933dc2-e107-48f9-b4d5-1ccc65997489
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167677100 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.167677100
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2899099250
Short name T555
Test name
Test status
Simulation time 16754591 ps
CPU time 0.59 seconds
Started Mar 10 01:12:16 PM PDT 24
Finished Mar 10 01:12:16 PM PDT 24
Peak memory 182628 kb
Host smart-294cd7f2-67f2-41dd-83c7-5926f229966e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899099250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2899099250
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1060109339
Short name T497
Test name
Test status
Simulation time 19392570 ps
CPU time 0.57 seconds
Started Mar 10 01:12:22 PM PDT 24
Finished Mar 10 01:12:23 PM PDT 24
Peak memory 182564 kb
Host smart-a2046cd2-1091-4e19-8cde-20ddfe9d2b6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060109339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1060109339
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2328009739
Short name T97
Test name
Test status
Simulation time 14412008 ps
CPU time 0.71 seconds
Started Mar 10 01:12:21 PM PDT 24
Finished Mar 10 01:12:22 PM PDT 24
Peak memory 191964 kb
Host smart-a4a4bb79-77c6-40bc-b4a8-2067766d37d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328009739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.2328009739
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3467719141
Short name T50
Test name
Test status
Simulation time 164682116 ps
CPU time 2.93 seconds
Started Mar 10 01:12:16 PM PDT 24
Finished Mar 10 01:12:19 PM PDT 24
Peak memory 197592 kb
Host smart-0ec00145-dbef-42fb-a4aa-ee421ab75efa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467719141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3467719141
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1162734477
Short name T527
Test name
Test status
Simulation time 219258754 ps
CPU time 1.38 seconds
Started Mar 10 01:12:16 PM PDT 24
Finished Mar 10 01:12:18 PM PDT 24
Peak memory 194940 kb
Host smart-1c175b5f-0543-44dd-9706-6c65abf80dff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162734477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.1162734477
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1481473192
Short name T492
Test name
Test status
Simulation time 13052860 ps
CPU time 0.59 seconds
Started Mar 10 01:12:36 PM PDT 24
Finished Mar 10 01:12:36 PM PDT 24
Peak memory 182568 kb
Host smart-4351049e-1bd0-4c6a-ade5-e1efd325caa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481473192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1481473192
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.748032105
Short name T531
Test name
Test status
Simulation time 73578416 ps
CPU time 0.58 seconds
Started Mar 10 01:12:33 PM PDT 24
Finished Mar 10 01:12:34 PM PDT 24
Peak memory 182472 kb
Host smart-c84bf9a0-2a6a-4cdf-a28c-ea4696a4d046
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748032105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.748032105
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.761869892
Short name T486
Test name
Test status
Simulation time 12202932 ps
CPU time 0.61 seconds
Started Mar 10 01:12:31 PM PDT 24
Finished Mar 10 01:12:32 PM PDT 24
Peak memory 182592 kb
Host smart-2606f92b-5cf7-407f-b750-8cef58b61088
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761869892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.761869892
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2632358377
Short name T464
Test name
Test status
Simulation time 26949980 ps
CPU time 0.57 seconds
Started Mar 10 01:12:32 PM PDT 24
Finished Mar 10 01:12:33 PM PDT 24
Peak memory 182544 kb
Host smart-6cfa9997-c73b-4b63-a624-aa9325723018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632358377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.2632358377
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1419739264
Short name T519
Test name
Test status
Simulation time 23613832 ps
CPU time 0.56 seconds
Started Mar 10 01:12:31 PM PDT 24
Finished Mar 10 01:12:31 PM PDT 24
Peak memory 182512 kb
Host smart-930939ad-00e2-4d53-ab0c-1dd285cb09de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419739264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.1419739264
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1552386699
Short name T515
Test name
Test status
Simulation time 25705180 ps
CPU time 0.54 seconds
Started Mar 10 01:12:30 PM PDT 24
Finished Mar 10 01:12:31 PM PDT 24
Peak memory 182488 kb
Host smart-cf4d00e0-1525-49f1-97eb-c0944dd610cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552386699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.1552386699
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3103712501
Short name T460
Test name
Test status
Simulation time 14279423 ps
CPU time 0.56 seconds
Started Mar 10 01:12:35 PM PDT 24
Finished Mar 10 01:12:35 PM PDT 24
Peak memory 181936 kb
Host smart-9e1da972-844c-4622-befd-f01c904f3da0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103712501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3103712501
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1536832945
Short name T502
Test name
Test status
Simulation time 60765372 ps
CPU time 0.59 seconds
Started Mar 10 01:12:31 PM PDT 24
Finished Mar 10 01:12:32 PM PDT 24
Peak memory 182544 kb
Host smart-80254c57-ddc1-4ba5-b92d-51998f44e112
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536832945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1536832945
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2017461666
Short name T553
Test name
Test status
Simulation time 46126445 ps
CPU time 0.55 seconds
Started Mar 10 01:12:35 PM PDT 24
Finished Mar 10 01:12:36 PM PDT 24
Peak memory 182136 kb
Host smart-fa52b0b9-5268-480d-bf2e-2f4ff34efac1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017461666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2017461666
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1933777898
Short name T557
Test name
Test status
Simulation time 53477108 ps
CPU time 0.55 seconds
Started Mar 10 01:12:30 PM PDT 24
Finished Mar 10 01:12:31 PM PDT 24
Peak memory 182004 kb
Host smart-ece6b2fd-dc35-4562-9ec1-e0aaa2a3cccf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933777898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1933777898
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1237545051
Short name T570
Test name
Test status
Simulation time 81044252 ps
CPU time 0.8 seconds
Started Mar 10 01:12:16 PM PDT 24
Finished Mar 10 01:12:17 PM PDT 24
Peak memory 192208 kb
Host smart-9a9ddb44-a289-48c2-8084-0a41b62e97bc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237545051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1237545051
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2913461598
Short name T560
Test name
Test status
Simulation time 37268128 ps
CPU time 1.46 seconds
Started Mar 10 01:12:21 PM PDT 24
Finished Mar 10 01:12:22 PM PDT 24
Peak memory 191124 kb
Host smart-4ae8f31d-6144-4723-a8ae-af044a250277
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913461598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2913461598
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3735801658
Short name T503
Test name
Test status
Simulation time 165930493 ps
CPU time 0.55 seconds
Started Mar 10 01:12:14 PM PDT 24
Finished Mar 10 01:12:15 PM PDT 24
Peak memory 182708 kb
Host smart-438c8c58-ae3b-4c51-bb5b-c6210412bdab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735801658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3735801658
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1443158567
Short name T565
Test name
Test status
Simulation time 29171238 ps
CPU time 0.83 seconds
Started Mar 10 01:12:21 PM PDT 24
Finished Mar 10 01:12:22 PM PDT 24
Peak memory 196136 kb
Host smart-b7fde77f-f492-4d09-a1cd-db67d542391f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443158567 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1443158567
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3571582591
Short name T48
Test name
Test status
Simulation time 15436899 ps
CPU time 0.56 seconds
Started Mar 10 01:12:22 PM PDT 24
Finished Mar 10 01:12:23 PM PDT 24
Peak memory 182292 kb
Host smart-f12c13f5-5fe0-480e-9020-b3b3729517c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571582591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3571582591
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.4012901357
Short name T484
Test name
Test status
Simulation time 42788040 ps
CPU time 0.53 seconds
Started Mar 10 01:12:14 PM PDT 24
Finished Mar 10 01:12:15 PM PDT 24
Peak memory 182148 kb
Host smart-3c095225-7836-47fa-af0a-cd273285718a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012901357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.4012901357
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2602643642
Short name T562
Test name
Test status
Simulation time 15853698 ps
CPU time 0.59 seconds
Started Mar 10 01:12:15 PM PDT 24
Finished Mar 10 01:12:15 PM PDT 24
Peak memory 191448 kb
Host smart-be51a66f-8d89-4c5a-8011-529c03abe26e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602643642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.2602643642
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.434050977
Short name T508
Test name
Test status
Simulation time 60220791 ps
CPU time 0.97 seconds
Started Mar 10 01:12:15 PM PDT 24
Finished Mar 10 01:12:16 PM PDT 24
Peak memory 197332 kb
Host smart-bb334240-007a-4020-a698-80af38123f66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434050977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.434050977
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2023273767
Short name T104
Test name
Test status
Simulation time 476579135 ps
CPU time 1.16 seconds
Started Mar 10 01:12:15 PM PDT 24
Finished Mar 10 01:12:16 PM PDT 24
Peak memory 195040 kb
Host smart-5fe0ebf5-bccd-483a-8bb1-90213c800256
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023273767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2023273767
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.274394719
Short name T472
Test name
Test status
Simulation time 30847479 ps
CPU time 0.56 seconds
Started Mar 10 01:12:33 PM PDT 24
Finished Mar 10 01:12:34 PM PDT 24
Peak memory 181992 kb
Host smart-57da2925-fd65-4bda-96cf-e00a6495bb6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274394719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.274394719
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1522163199
Short name T577
Test name
Test status
Simulation time 36608899 ps
CPU time 0.57 seconds
Started Mar 10 01:12:39 PM PDT 24
Finished Mar 10 01:12:40 PM PDT 24
Peak memory 182544 kb
Host smart-035e5169-1b90-42fb-94e8-cdc2f180bed5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522163199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1522163199
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.692881566
Short name T581
Test name
Test status
Simulation time 44434760 ps
CPU time 0.53 seconds
Started Mar 10 01:12:36 PM PDT 24
Finished Mar 10 01:12:37 PM PDT 24
Peak memory 181892 kb
Host smart-d96f06a2-ec39-427d-aa12-f6c38591622f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692881566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.692881566
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2155225585
Short name T456
Test name
Test status
Simulation time 14840679 ps
CPU time 0.56 seconds
Started Mar 10 01:12:43 PM PDT 24
Finished Mar 10 01:12:43 PM PDT 24
Peak memory 182468 kb
Host smart-5d89c35b-bb14-4cb4-a303-dcd83f1a4320
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155225585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2155225585
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2884503630
Short name T509
Test name
Test status
Simulation time 16057563 ps
CPU time 0.55 seconds
Started Mar 10 01:12:38 PM PDT 24
Finished Mar 10 01:12:39 PM PDT 24
Peak memory 182020 kb
Host smart-2ffa64bd-0058-4760-beb2-5b36009f3619
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884503630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2884503630
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2449878244
Short name T496
Test name
Test status
Simulation time 23622556 ps
CPU time 0.55 seconds
Started Mar 10 01:12:40 PM PDT 24
Finished Mar 10 01:12:41 PM PDT 24
Peak memory 182568 kb
Host smart-c84959ff-87ae-4654-bfa9-19bc1317a023
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449878244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2449878244
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1557418300
Short name T538
Test name
Test status
Simulation time 154786072 ps
CPU time 0.56 seconds
Started Mar 10 01:12:36 PM PDT 24
Finished Mar 10 01:12:36 PM PDT 24
Peak memory 182580 kb
Host smart-5812bfd6-a224-4c9b-9c21-9c64399532c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557418300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1557418300
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.163013526
Short name T465
Test name
Test status
Simulation time 14693850 ps
CPU time 0.58 seconds
Started Mar 10 01:12:37 PM PDT 24
Finished Mar 10 01:12:39 PM PDT 24
Peak memory 182136 kb
Host smart-78931d28-3391-4b05-b6f2-3bde8ebdc2eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163013526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.163013526
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3873976645
Short name T499
Test name
Test status
Simulation time 24193402 ps
CPU time 0.54 seconds
Started Mar 10 01:12:33 PM PDT 24
Finished Mar 10 01:12:34 PM PDT 24
Peak memory 182020 kb
Host smart-1f911739-0c71-4a02-b0cc-f85e8404eac3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873976645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3873976645
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.349883348
Short name T537
Test name
Test status
Simulation time 25787160 ps
CPU time 0.59 seconds
Started Mar 10 01:12:37 PM PDT 24
Finished Mar 10 01:12:39 PM PDT 24
Peak memory 182552 kb
Host smart-e12215ce-e4da-4156-a212-609a3448c41b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349883348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.349883348
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.963512225
Short name T70
Test name
Test status
Simulation time 77520760 ps
CPU time 1.15 seconds
Started Mar 10 01:12:23 PM PDT 24
Finished Mar 10 01:12:24 PM PDT 24
Peak memory 197572 kb
Host smart-d9d99e74-b8b9-4a06-ab43-b12c4209a91e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963512225 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.963512225
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2058041525
Short name T469
Test name
Test status
Simulation time 68174800 ps
CPU time 0.6 seconds
Started Mar 10 01:12:21 PM PDT 24
Finished Mar 10 01:12:22 PM PDT 24
Peak memory 182696 kb
Host smart-0de82e61-2303-42af-bf28-bd332820aabe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058041525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2058041525
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.4241537241
Short name T505
Test name
Test status
Simulation time 15075977 ps
CPU time 0.54 seconds
Started Mar 10 01:12:22 PM PDT 24
Finished Mar 10 01:12:23 PM PDT 24
Peak memory 182000 kb
Host smart-b9c2706b-8dfd-4e5c-8782-86b4ecb45d15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241537241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.4241537241
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1912942946
Short name T96
Test name
Test status
Simulation time 68794698 ps
CPU time 0.65 seconds
Started Mar 10 01:12:17 PM PDT 24
Finished Mar 10 01:12:18 PM PDT 24
Peak memory 191992 kb
Host smart-a1a5d358-0b63-41b9-a0ce-25be21cc85da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912942946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1912942946
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1801938395
Short name T481
Test name
Test status
Simulation time 119540051 ps
CPU time 2.48 seconds
Started Mar 10 01:12:16 PM PDT 24
Finished Mar 10 01:12:19 PM PDT 24
Peak memory 197580 kb
Host smart-6ce0941c-04a5-46ce-9c97-2bdd184c4752
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801938395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1801938395
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1687966860
Short name T46
Test name
Test status
Simulation time 343158343 ps
CPU time 0.85 seconds
Started Mar 10 01:12:28 PM PDT 24
Finished Mar 10 01:12:29 PM PDT 24
Peak memory 196672 kb
Host smart-f5088cd9-1c4a-4f5f-9894-c36c4502e01e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687966860 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1687966860
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.4229113348
Short name T31
Test name
Test status
Simulation time 16281130 ps
CPU time 0.56 seconds
Started Mar 10 01:12:23 PM PDT 24
Finished Mar 10 01:12:24 PM PDT 24
Peak memory 182256 kb
Host smart-b1ae468e-faba-48f4-8129-8e914912e209
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229113348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.4229113348
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.412471539
Short name T533
Test name
Test status
Simulation time 12982694 ps
CPU time 0.57 seconds
Started Mar 10 01:12:23 PM PDT 24
Finished Mar 10 01:12:24 PM PDT 24
Peak memory 182156 kb
Host smart-4cfab325-725b-4d2d-b2d1-a7ae7b7361c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412471539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.412471539
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2809160394
Short name T582
Test name
Test status
Simulation time 17565349 ps
CPU time 0.66 seconds
Started Mar 10 01:12:23 PM PDT 24
Finished Mar 10 01:12:24 PM PDT 24
Peak memory 191392 kb
Host smart-32f2c189-6d20-4a55-b25f-2af653e344b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809160394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.2809160394
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1519062583
Short name T569
Test name
Test status
Simulation time 1065989230 ps
CPU time 3.16 seconds
Started Mar 10 01:12:25 PM PDT 24
Finished Mar 10 01:12:29 PM PDT 24
Peak memory 197540 kb
Host smart-421cd4a8-c883-4c4b-8042-59cea7a9e2d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519062583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1519062583
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3688367874
Short name T529
Test name
Test status
Simulation time 237281184 ps
CPU time 1.28 seconds
Started Mar 10 01:12:23 PM PDT 24
Finished Mar 10 01:12:25 PM PDT 24
Peak memory 183372 kb
Host smart-24c37805-6a58-4d64-9172-35de2c470908
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688367874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.3688367874
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1667758259
Short name T526
Test name
Test status
Simulation time 28397192 ps
CPU time 0.64 seconds
Started Mar 10 01:12:24 PM PDT 24
Finished Mar 10 01:12:25 PM PDT 24
Peak memory 193084 kb
Host smart-576ef37f-edfe-4850-9069-e119dc2f4e07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667758259 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1667758259
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2905815404
Short name T501
Test name
Test status
Simulation time 16275483 ps
CPU time 0.6 seconds
Started Mar 10 01:12:24 PM PDT 24
Finished Mar 10 01:12:25 PM PDT 24
Peak memory 182756 kb
Host smart-0c9fcc4d-3639-4c99-aa6b-96adb785e130
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905815404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2905815404
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.283848611
Short name T559
Test name
Test status
Simulation time 16650144 ps
CPU time 0.59 seconds
Started Mar 10 01:12:23 PM PDT 24
Finished Mar 10 01:12:24 PM PDT 24
Peak memory 182484 kb
Host smart-9dbd54e5-37bc-451e-a69f-f377202b3370
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283848611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.283848611
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3271096982
Short name T93
Test name
Test status
Simulation time 33058514 ps
CPU time 0.65 seconds
Started Mar 10 01:12:21 PM PDT 24
Finished Mar 10 01:12:22 PM PDT 24
Peak memory 192044 kb
Host smart-bb5dfd88-9d91-4355-93c2-e705d21d5ed7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271096982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3271096982
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.277237285
Short name T575
Test name
Test status
Simulation time 160234939 ps
CPU time 2.81 seconds
Started Mar 10 01:12:22 PM PDT 24
Finished Mar 10 01:12:26 PM PDT 24
Peak memory 197628 kb
Host smart-3c8c9aa3-c794-4bc9-a6da-fa2259791243
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277237285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.277237285
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1533303711
Short name T27
Test name
Test status
Simulation time 42640157 ps
CPU time 0.81 seconds
Started Mar 10 01:12:22 PM PDT 24
Finished Mar 10 01:12:23 PM PDT 24
Peak memory 183172 kb
Host smart-6cc25d01-7c73-4e14-b4fc-2891ad32403c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533303711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1533303711
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3810345314
Short name T523
Test name
Test status
Simulation time 43767194 ps
CPU time 0.58 seconds
Started Mar 10 01:12:20 PM PDT 24
Finished Mar 10 01:12:20 PM PDT 24
Peak memory 192872 kb
Host smart-82d43a88-ae90-47ca-86e6-5ae4976b15df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810345314 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3810345314
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1361398371
Short name T75
Test name
Test status
Simulation time 56291820 ps
CPU time 0.6 seconds
Started Mar 10 01:12:21 PM PDT 24
Finished Mar 10 01:12:22 PM PDT 24
Peak memory 182780 kb
Host smart-8bc8fbe0-f8ee-418d-9bd3-63df0e355616
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361398371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1361398371
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3372390747
Short name T473
Test name
Test status
Simulation time 28073974 ps
CPU time 0.54 seconds
Started Mar 10 01:12:24 PM PDT 24
Finished Mar 10 01:12:25 PM PDT 24
Peak memory 182516 kb
Host smart-3e443373-bd77-45a1-a914-fc82ffe2e1c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372390747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3372390747
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3213721664
Short name T513
Test name
Test status
Simulation time 36782489 ps
CPU time 0.75 seconds
Started Mar 10 01:12:20 PM PDT 24
Finished Mar 10 01:12:21 PM PDT 24
Peak memory 193200 kb
Host smart-cfeb9dbe-0db0-41c8-b01f-5465f46cd882
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213721664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.3213721664
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2272058164
Short name T551
Test name
Test status
Simulation time 83205341 ps
CPU time 1.3 seconds
Started Mar 10 01:12:26 PM PDT 24
Finished Mar 10 01:12:28 PM PDT 24
Peak memory 197636 kb
Host smart-a23527d0-68a5-49e9-af84-df8d1d890932
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272058164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2272058164
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2032185380
Short name T28
Test name
Test status
Simulation time 254759375 ps
CPU time 0.81 seconds
Started Mar 10 01:12:22 PM PDT 24
Finished Mar 10 01:12:23 PM PDT 24
Peak memory 193532 kb
Host smart-b7781d15-315f-4f4b-a381-f3044803365b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032185380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2032185380
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.765161460
Short name T549
Test name
Test status
Simulation time 25610666 ps
CPU time 1.18 seconds
Started Mar 10 01:12:29 PM PDT 24
Finished Mar 10 01:12:31 PM PDT 24
Peak memory 197604 kb
Host smart-54c82be6-fb72-4b2a-a8b7-424e75fa2d10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765161460 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.765161460
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.407963607
Short name T60
Test name
Test status
Simulation time 13751035 ps
CPU time 0.59 seconds
Started Mar 10 01:12:21 PM PDT 24
Finished Mar 10 01:12:22 PM PDT 24
Peak memory 182352 kb
Host smart-4a7ec090-38a6-41a0-9e52-5aa328e64956
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407963607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.407963607
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.956240243
Short name T548
Test name
Test status
Simulation time 13214307 ps
CPU time 0.56 seconds
Started Mar 10 01:12:26 PM PDT 24
Finished Mar 10 01:12:27 PM PDT 24
Peak memory 182580 kb
Host smart-86f5f834-aa08-4f39-ba7b-dc666b302f30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956240243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.956240243
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2024041700
Short name T99
Test name
Test status
Simulation time 13172675 ps
CPU time 0.6 seconds
Started Mar 10 01:12:24 PM PDT 24
Finished Mar 10 01:12:25 PM PDT 24
Peak memory 192032 kb
Host smart-f9c0cb65-bbc9-4843-85f5-353ab92ff86e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024041700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2024041700
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2071718124
Short name T545
Test name
Test status
Simulation time 84565752 ps
CPU time 1.44 seconds
Started Mar 10 01:12:22 PM PDT 24
Finished Mar 10 01:12:24 PM PDT 24
Peak memory 191220 kb
Host smart-81218fc5-773a-477c-8319-7a374a9aa2cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071718124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2071718124
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3499715723
Short name T101
Test name
Test status
Simulation time 68885629 ps
CPU time 1.1 seconds
Started Mar 10 01:12:23 PM PDT 24
Finished Mar 10 01:12:24 PM PDT 24
Peak memory 183380 kb
Host smart-8def4856-f84e-4bd2-83b5-c202ca1edd06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499715723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3499715723
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.1923194881
Short name T426
Test name
Test status
Simulation time 70476578518 ps
CPU time 121.5 seconds
Started Mar 10 01:13:13 PM PDT 24
Finished Mar 10 01:15:15 PM PDT 24
Peak memory 183308 kb
Host smart-60cb2c69-093e-4321-971f-93ddd2d6c677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923194881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.1923194881
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.508872169
Short name T362
Test name
Test status
Simulation time 48426826938 ps
CPU time 478.58 seconds
Started Mar 10 01:13:12 PM PDT 24
Finished Mar 10 01:21:11 PM PDT 24
Peak memory 191500 kb
Host smart-3f9f1b39-03c8-4dc9-ba14-1876035c5b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508872169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.508872169
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.537495209
Short name T15
Test name
Test status
Simulation time 246209971 ps
CPU time 0.87 seconds
Started Mar 10 01:13:23 PM PDT 24
Finished Mar 10 01:13:24 PM PDT 24
Peak memory 213540 kb
Host smart-fd053cfe-b092-4146-b48b-35ece816e449
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537495209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.537495209
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2427522787
Short name T254
Test name
Test status
Simulation time 1443792379685 ps
CPU time 1070.83 seconds
Started Mar 10 01:13:08 PM PDT 24
Finished Mar 10 01:30:59 PM PDT 24
Peak memory 191512 kb
Host smart-1e7d3edf-df09-416e-a543-8ba1b679913c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427522787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2427522787
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1986211831
Short name T413
Test name
Test status
Simulation time 53590349002 ps
CPU time 53.57 seconds
Started Mar 10 01:13:22 PM PDT 24
Finished Mar 10 01:14:16 PM PDT 24
Peak memory 183268 kb
Host smart-fb1ae326-3e34-4818-85b2-b1cac8bb0aa6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986211831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1986211831
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3155693267
Short name T387
Test name
Test status
Simulation time 86654214595 ps
CPU time 76.23 seconds
Started Mar 10 01:13:09 PM PDT 24
Finished Mar 10 01:14:25 PM PDT 24
Peak memory 183380 kb
Host smart-f000b834-19ff-4924-9c69-93ffc0c604c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155693267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3155693267
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.3024689990
Short name T262
Test name
Test status
Simulation time 422019878059 ps
CPU time 308.04 seconds
Started Mar 10 01:13:13 PM PDT 24
Finished Mar 10 01:18:22 PM PDT 24
Peak memory 191468 kb
Host smart-8c293eb8-9251-4281-b2da-473a31fa6d69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024689990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3024689990
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3181884975
Short name T237
Test name
Test status
Simulation time 98693787443 ps
CPU time 55.57 seconds
Started Mar 10 01:13:09 PM PDT 24
Finished Mar 10 01:14:05 PM PDT 24
Peak memory 183372 kb
Host smart-5a0fa15b-cfc2-4a8a-9aff-2a9c5c3dff22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181884975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3181884975
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.4211097270
Short name T14
Test name
Test status
Simulation time 82395113 ps
CPU time 0.93 seconds
Started Mar 10 01:13:12 PM PDT 24
Finished Mar 10 01:13:14 PM PDT 24
Peak memory 214588 kb
Host smart-72c0cd6b-b718-4767-bad7-0e7dd8858a74
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211097270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.4211097270
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1675363436
Short name T252
Test name
Test status
Simulation time 1024960575942 ps
CPU time 574.17 seconds
Started Mar 10 01:13:17 PM PDT 24
Finished Mar 10 01:22:52 PM PDT 24
Peak memory 195792 kb
Host smart-f37e472e-3ec1-488d-a1fd-33da96f1a65f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675363436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1675363436
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.2303242245
Short name T410
Test name
Test status
Simulation time 23696513307 ps
CPU time 256.08 seconds
Started Mar 10 01:13:07 PM PDT 24
Finished Mar 10 01:17:23 PM PDT 24
Peak memory 206240 kb
Host smart-bb1a6f51-9e09-44d6-b46f-b2fad1e903d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303242245 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.2303242245
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.456614061
Short name T384
Test name
Test status
Simulation time 11671699278 ps
CPU time 17.28 seconds
Started Mar 10 01:13:27 PM PDT 24
Finished Mar 10 01:13:45 PM PDT 24
Peak memory 183400 kb
Host smart-647d9032-c58a-4dbd-b174-c2b7df06eae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456614061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.456614061
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.2360291232
Short name T218
Test name
Test status
Simulation time 202679092653 ps
CPU time 216.47 seconds
Started Mar 10 01:13:19 PM PDT 24
Finished Mar 10 01:16:56 PM PDT 24
Peak memory 191552 kb
Host smart-f88d74d6-13a2-4321-a3a8-ab480b45e6bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360291232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2360291232
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.51068401
Short name T353
Test name
Test status
Simulation time 116329483877 ps
CPU time 65.88 seconds
Started Mar 10 01:13:28 PM PDT 24
Finished Mar 10 01:14:34 PM PDT 24
Peak memory 191604 kb
Host smart-c74d9162-9e25-4fc0-8418-0a06c07ab0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51068401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.51068401
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/102.rv_timer_random.4226904565
Short name T253
Test name
Test status
Simulation time 49445537459 ps
CPU time 102.03 seconds
Started Mar 10 01:15:02 PM PDT 24
Finished Mar 10 01:16:44 PM PDT 24
Peak memory 191480 kb
Host smart-66fa2bcc-5ab4-49a3-8d62-d9f261297bbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226904565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.4226904565
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.3111671716
Short name T333
Test name
Test status
Simulation time 44518192484 ps
CPU time 64.94 seconds
Started Mar 10 01:15:02 PM PDT 24
Finished Mar 10 01:16:07 PM PDT 24
Peak memory 191572 kb
Host smart-1a9566ba-398d-4856-b435-cf2928ee7e03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111671716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3111671716
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.762058592
Short name T310
Test name
Test status
Simulation time 47274068494 ps
CPU time 77.11 seconds
Started Mar 10 01:15:02 PM PDT 24
Finished Mar 10 01:16:19 PM PDT 24
Peak memory 183316 kb
Host smart-3ccdf376-afd2-4806-8456-3ce2839acd0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762058592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.762058592
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.4232172048
Short name T309
Test name
Test status
Simulation time 194771930184 ps
CPU time 140.06 seconds
Started Mar 10 01:15:07 PM PDT 24
Finished Mar 10 01:17:27 PM PDT 24
Peak memory 191596 kb
Host smart-80520c27-ac03-4b99-952e-d0fe3a13b7b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232172048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.4232172048
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.1507064189
Short name T288
Test name
Test status
Simulation time 124521845146 ps
CPU time 124.73 seconds
Started Mar 10 01:15:14 PM PDT 24
Finished Mar 10 01:17:19 PM PDT 24
Peak memory 194852 kb
Host smart-c8f5345f-33ce-4996-a3ae-89a42f4542b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507064189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1507064189
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.2960670151
Short name T112
Test name
Test status
Simulation time 102582218230 ps
CPU time 181.98 seconds
Started Mar 10 01:15:13 PM PDT 24
Finished Mar 10 01:18:15 PM PDT 24
Peak memory 191600 kb
Host smart-2a7b3c99-cecc-4424-acc3-06ba282aaf1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960670151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2960670151
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.3604485703
Short name T397
Test name
Test status
Simulation time 94893714484 ps
CPU time 134.39 seconds
Started Mar 10 01:13:26 PM PDT 24
Finished Mar 10 01:15:40 PM PDT 24
Peak memory 183332 kb
Host smart-e71b9bd4-6787-4676-b013-2cb22325475b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604485703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.3604485703
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1744127625
Short name T445
Test name
Test status
Simulation time 439817018 ps
CPU time 0.74 seconds
Started Mar 10 01:13:33 PM PDT 24
Finished Mar 10 01:13:34 PM PDT 24
Peak memory 183052 kb
Host smart-171e2cab-6e93-4cc2-9272-e09fda8b47f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744127625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1744127625
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.2105576756
Short name T33
Test name
Test status
Simulation time 96699817690 ps
CPU time 767.88 seconds
Started Mar 10 01:13:27 PM PDT 24
Finished Mar 10 01:26:15 PM PDT 24
Peak memory 200344 kb
Host smart-87a0c0cf-54ad-4d3a-b984-6bf7c9e81ac1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105576756 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.2105576756
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.480411000
Short name T105
Test name
Test status
Simulation time 273301309794 ps
CPU time 254.94 seconds
Started Mar 10 01:15:16 PM PDT 24
Finished Mar 10 01:19:31 PM PDT 24
Peak memory 191540 kb
Host smart-f4b88ddf-eaca-40b0-94e5-80588e57586f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480411000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.480411000
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.1113142737
Short name T428
Test name
Test status
Simulation time 312954142885 ps
CPU time 147.3 seconds
Started Mar 10 01:15:16 PM PDT 24
Finished Mar 10 01:17:43 PM PDT 24
Peak memory 193412 kb
Host smart-8806c075-3534-4799-930d-6c05cf0b2df0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113142737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1113142737
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.518983907
Short name T421
Test name
Test status
Simulation time 10747893117 ps
CPU time 17.48 seconds
Started Mar 10 01:15:14 PM PDT 24
Finished Mar 10 01:15:31 PM PDT 24
Peak memory 183404 kb
Host smart-4539937a-385d-47b2-979b-19431f618057
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518983907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.518983907
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.3194915272
Short name T139
Test name
Test status
Simulation time 145264066326 ps
CPU time 882.7 seconds
Started Mar 10 01:15:17 PM PDT 24
Finished Mar 10 01:30:00 PM PDT 24
Peak memory 194408 kb
Host smart-ac55be85-5a5f-4576-a11c-c6724a957419
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194915272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3194915272
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.2793472165
Short name T272
Test name
Test status
Simulation time 169316602934 ps
CPU time 947.62 seconds
Started Mar 10 01:15:17 PM PDT 24
Finished Mar 10 01:31:05 PM PDT 24
Peak memory 191556 kb
Host smart-99d43d40-2299-4669-9d14-051f4b1c9d33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793472165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2793472165
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.2907167716
Short name T267
Test name
Test status
Simulation time 142038706617 ps
CPU time 220.03 seconds
Started Mar 10 01:15:18 PM PDT 24
Finished Mar 10 01:18:58 PM PDT 24
Peak memory 191604 kb
Host smart-9d1ed08e-6bd6-4d88-b594-3f0faba54a25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907167716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2907167716
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1599773242
Short name T129
Test name
Test status
Simulation time 151930430765 ps
CPU time 375.82 seconds
Started Mar 10 01:15:20 PM PDT 24
Finished Mar 10 01:21:36 PM PDT 24
Peak memory 191532 kb
Host smart-d9ace0df-b387-4aff-a5f4-fcf76b551c86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599773242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1599773242
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.3348096781
Short name T409
Test name
Test status
Simulation time 113974443506 ps
CPU time 25.86 seconds
Started Mar 10 01:15:26 PM PDT 24
Finished Mar 10 01:15:53 PM PDT 24
Peak memory 183340 kb
Host smart-57648e7c-53c2-4ce0-8f04-d7cce7fc2d9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348096781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3348096781
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.3951067934
Short name T280
Test name
Test status
Simulation time 129116633549 ps
CPU time 125.54 seconds
Started Mar 10 01:15:24 PM PDT 24
Finished Mar 10 01:17:30 PM PDT 24
Peak memory 191588 kb
Host smart-2baa2dcc-8354-4714-83e1-7e6697d73bbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951067934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3951067934
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.162231414
Short name T361
Test name
Test status
Simulation time 75589029556 ps
CPU time 23.15 seconds
Started Mar 10 01:13:27 PM PDT 24
Finished Mar 10 01:13:50 PM PDT 24
Peak memory 183384 kb
Host smart-ef3dce76-21e0-45fb-a560-d02ae8a7f50f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162231414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.rv_timer_cfg_update_on_fly.162231414
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1809711253
Short name T375
Test name
Test status
Simulation time 676437186574 ps
CPU time 271.22 seconds
Started Mar 10 01:13:27 PM PDT 24
Finished Mar 10 01:17:58 PM PDT 24
Peak memory 183372 kb
Host smart-5f15a25c-f7c1-46dd-a7e7-9233943de916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809711253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1809711253
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.1975777462
Short name T191
Test name
Test status
Simulation time 125526999111 ps
CPU time 221.09 seconds
Started Mar 10 01:13:27 PM PDT 24
Finished Mar 10 01:17:09 PM PDT 24
Peak memory 191488 kb
Host smart-00ad2d93-c3e9-42a8-bac2-582f3659d314
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975777462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1975777462
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.736271289
Short name T138
Test name
Test status
Simulation time 22222245552 ps
CPU time 160.39 seconds
Started Mar 10 01:13:29 PM PDT 24
Finished Mar 10 01:16:09 PM PDT 24
Peak memory 183288 kb
Host smart-4fc8f6a1-4d64-4eb7-89c1-0c059eeef8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736271289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.736271289
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3523496922
Short name T18
Test name
Test status
Simulation time 4197732779815 ps
CPU time 1044.78 seconds
Started Mar 10 01:13:26 PM PDT 24
Finished Mar 10 01:30:51 PM PDT 24
Peak memory 191604 kb
Host smart-363fabe0-bf22-480f-bfa6-e4f68432bd11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523496922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3523496922
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.845021778
Short name T181
Test name
Test status
Simulation time 342203839831 ps
CPU time 148.03 seconds
Started Mar 10 01:15:23 PM PDT 24
Finished Mar 10 01:17:52 PM PDT 24
Peak memory 191580 kb
Host smart-a34c1c69-9ff4-4e73-b0ce-83a196ac465d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845021778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.845021778
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.2893523478
Short name T144
Test name
Test status
Simulation time 313587322122 ps
CPU time 265.26 seconds
Started Mar 10 01:15:24 PM PDT 24
Finished Mar 10 01:19:50 PM PDT 24
Peak memory 191560 kb
Host smart-24b32074-6067-4047-a0a8-c59d20dda156
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893523478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2893523478
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.318244332
Short name T250
Test name
Test status
Simulation time 277659457592 ps
CPU time 1171.56 seconds
Started Mar 10 01:15:23 PM PDT 24
Finished Mar 10 01:34:55 PM PDT 24
Peak memory 191552 kb
Host smart-6a7d500e-838d-411b-bcf6-2492fc178f6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318244332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.318244332
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1798615144
Short name T358
Test name
Test status
Simulation time 137083184615 ps
CPU time 121.03 seconds
Started Mar 10 01:15:24 PM PDT 24
Finished Mar 10 01:17:26 PM PDT 24
Peak memory 183412 kb
Host smart-4581f3a4-bb39-4c5c-9482-2f4109b3e9f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798615144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1798615144
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2705327655
Short name T350
Test name
Test status
Simulation time 66924315922 ps
CPU time 56.43 seconds
Started Mar 10 01:15:22 PM PDT 24
Finished Mar 10 01:16:19 PM PDT 24
Peak memory 191560 kb
Host smart-46b05cd9-d29b-41fa-927d-67633c88afef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705327655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2705327655
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3303367762
Short name T25
Test name
Test status
Simulation time 74116128060 ps
CPU time 131.63 seconds
Started Mar 10 01:15:29 PM PDT 24
Finished Mar 10 01:17:41 PM PDT 24
Peak memory 191564 kb
Host smart-1ba3d695-361a-43e7-a578-a36964d673e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303367762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3303367762
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.4292112148
Short name T156
Test name
Test status
Simulation time 78516700652 ps
CPU time 1700.23 seconds
Started Mar 10 01:15:27 PM PDT 24
Finished Mar 10 01:43:47 PM PDT 24
Peak memory 191544 kb
Host smart-a89f2b01-4272-45a1-8bcb-844c681b72ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292112148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.4292112148
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1194096571
Short name T298
Test name
Test status
Simulation time 3012654512514 ps
CPU time 1605.94 seconds
Started Mar 10 01:13:29 PM PDT 24
Finished Mar 10 01:40:15 PM PDT 24
Peak memory 183400 kb
Host smart-f8773dcb-4afa-4df5-bf87-b58e1dab775c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194096571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1194096571
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2491726287
Short name T419
Test name
Test status
Simulation time 159575731668 ps
CPU time 64.28 seconds
Started Mar 10 01:13:28 PM PDT 24
Finished Mar 10 01:14:33 PM PDT 24
Peak memory 183320 kb
Host smart-e9124ad3-c38f-4d95-9c3e-0a4ce2c11401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491726287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2491726287
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.721114969
Short name T186
Test name
Test status
Simulation time 125847653161 ps
CPU time 108.28 seconds
Started Mar 10 01:13:37 PM PDT 24
Finished Mar 10 01:15:25 PM PDT 24
Peak memory 191540 kb
Host smart-ae93e7d9-7fb2-44a0-9e20-f9e83c353bfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721114969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.721114969
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.883890223
Short name T141
Test name
Test status
Simulation time 180919489349 ps
CPU time 1811.52 seconds
Started Mar 10 01:13:35 PM PDT 24
Finished Mar 10 01:43:47 PM PDT 24
Peak memory 183348 kb
Host smart-f2873358-d24c-40ea-aac7-2c1d356a5033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883890223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.883890223
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.3156190026
Short name T147
Test name
Test status
Simulation time 896191631278 ps
CPU time 761.6 seconds
Started Mar 10 01:15:34 PM PDT 24
Finished Mar 10 01:28:16 PM PDT 24
Peak memory 193292 kb
Host smart-74b8fc2f-f955-41ed-b64e-e8d40ef81638
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156190026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3156190026
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.2868912076
Short name T225
Test name
Test status
Simulation time 474920699630 ps
CPU time 187.68 seconds
Started Mar 10 01:15:33 PM PDT 24
Finished Mar 10 01:18:41 PM PDT 24
Peak memory 191592 kb
Host smart-ef2e758e-6992-44dc-8c37-763602e77717
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868912076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2868912076
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.986041562
Short name T268
Test name
Test status
Simulation time 246179984378 ps
CPU time 1824.02 seconds
Started Mar 10 01:15:33 PM PDT 24
Finished Mar 10 01:45:58 PM PDT 24
Peak memory 191560 kb
Host smart-c44f5b27-2442-4e49-86f0-3c718275637d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986041562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.986041562
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.156592963
Short name T291
Test name
Test status
Simulation time 570566773392 ps
CPU time 1315.07 seconds
Started Mar 10 01:15:36 PM PDT 24
Finished Mar 10 01:37:32 PM PDT 24
Peak memory 191560 kb
Host smart-5972c007-4681-4054-bebb-72d5f6c64a75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156592963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.156592963
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.2841309856
Short name T318
Test name
Test status
Simulation time 118077056079 ps
CPU time 69.49 seconds
Started Mar 10 01:15:34 PM PDT 24
Finished Mar 10 01:16:44 PM PDT 24
Peak memory 183356 kb
Host smart-9fdcbed5-83c7-4545-90a7-ae36dec8c6cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841309856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2841309856
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.3995796378
Short name T311
Test name
Test status
Simulation time 1057443214019 ps
CPU time 491.65 seconds
Started Mar 10 01:15:36 PM PDT 24
Finished Mar 10 01:23:48 PM PDT 24
Peak memory 191616 kb
Host smart-f435cedd-d674-429a-a244-e731cad3b7e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995796378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3995796378
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.1918813561
Short name T204
Test name
Test status
Simulation time 519930804699 ps
CPU time 146.48 seconds
Started Mar 10 01:15:34 PM PDT 24
Finished Mar 10 01:18:01 PM PDT 24
Peak memory 191520 kb
Host smart-2fd28c68-e288-4287-a4e8-72909fb50278
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918813561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.1918813561
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.1827526865
Short name T348
Test name
Test status
Simulation time 82174250645 ps
CPU time 46.5 seconds
Started Mar 10 01:13:37 PM PDT 24
Finished Mar 10 01:14:24 PM PDT 24
Peak memory 183252 kb
Host smart-0195e847-1561-4ffb-8434-5f7ddad81f31
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827526865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.1827526865
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.31322735
Short name T368
Test name
Test status
Simulation time 181989208489 ps
CPU time 291.62 seconds
Started Mar 10 01:13:31 PM PDT 24
Finished Mar 10 01:18:23 PM PDT 24
Peak memory 183336 kb
Host smart-035dce9f-8c16-43bc-901a-225c7caa8855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31322735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.31322735
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.2059289352
Short name T289
Test name
Test status
Simulation time 59479895135 ps
CPU time 113.35 seconds
Started Mar 10 01:13:28 PM PDT 24
Finished Mar 10 01:15:22 PM PDT 24
Peak memory 193664 kb
Host smart-19802149-c9e1-4644-8a9d-82a6a93757d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059289352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2059289352
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.4055551293
Short name T108
Test name
Test status
Simulation time 42815495765 ps
CPU time 75.89 seconds
Started Mar 10 01:13:35 PM PDT 24
Finished Mar 10 01:14:51 PM PDT 24
Peak memory 183356 kb
Host smart-0a3463f5-9eea-4e16-bfe7-89e2ac4dcb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055551293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.4055551293
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.3253100812
Short name T184
Test name
Test status
Simulation time 1397038893756 ps
CPU time 695.24 seconds
Started Mar 10 01:13:36 PM PDT 24
Finished Mar 10 01:25:11 PM PDT 24
Peak memory 191496 kb
Host smart-0854bee8-d6e5-4a07-9ce2-7c2cc41b1125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253100812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.3253100812
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.3250163098
Short name T149
Test name
Test status
Simulation time 81025419597 ps
CPU time 220.81 seconds
Started Mar 10 01:15:37 PM PDT 24
Finished Mar 10 01:19:18 PM PDT 24
Peak memory 191572 kb
Host smart-5aacd5e3-7325-4524-b7e0-7f201cbc8d02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250163098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3250163098
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.2527680490
Short name T233
Test name
Test status
Simulation time 130453798411 ps
CPU time 60.09 seconds
Started Mar 10 01:15:38 PM PDT 24
Finished Mar 10 01:16:39 PM PDT 24
Peak memory 183392 kb
Host smart-b921ddd3-f6d2-49d0-9f08-3fb06ff7d41e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527680490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2527680490
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.2604710480
Short name T269
Test name
Test status
Simulation time 186443896906 ps
CPU time 322.11 seconds
Started Mar 10 01:15:40 PM PDT 24
Finished Mar 10 01:21:02 PM PDT 24
Peak memory 191592 kb
Host smart-b7a2cafc-f993-48ea-b7c9-b1564c42273b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604710480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2604710480
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3815004368
Short name T327
Test name
Test status
Simulation time 279887619186 ps
CPU time 304.75 seconds
Started Mar 10 01:15:43 PM PDT 24
Finished Mar 10 01:20:48 PM PDT 24
Peak memory 191516 kb
Host smart-b417a6c6-a554-480b-9354-b3a0734e1832
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815004368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3815004368
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1488385910
Short name T312
Test name
Test status
Simulation time 180342362546 ps
CPU time 179.11 seconds
Started Mar 10 01:15:39 PM PDT 24
Finished Mar 10 01:18:38 PM PDT 24
Peak memory 191600 kb
Host smart-c9912fe3-fe76-4b7c-b272-dc1be959549c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488385910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1488385910
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3685559042
Short name T287
Test name
Test status
Simulation time 59703193860 ps
CPU time 445.13 seconds
Started Mar 10 01:15:44 PM PDT 24
Finished Mar 10 01:23:09 PM PDT 24
Peak memory 191592 kb
Host smart-5302c99f-0f68-4027-acfe-21ddeba0baaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685559042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3685559042
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1152178275
Short name T336
Test name
Test status
Simulation time 62214772970 ps
CPU time 77.92 seconds
Started Mar 10 01:15:45 PM PDT 24
Finished Mar 10 01:17:03 PM PDT 24
Peak memory 195304 kb
Host smart-ae3ef1b7-5f29-4464-8ff8-e00b3577f45d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152178275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1152178275
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.3375796015
Short name T140
Test name
Test status
Simulation time 429518765613 ps
CPU time 245.64 seconds
Started Mar 10 01:13:36 PM PDT 24
Finished Mar 10 01:17:42 PM PDT 24
Peak memory 183352 kb
Host smart-bfca0294-d67f-4fcb-9e72-22518b391f57
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375796015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.3375796015
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2785934346
Short name T431
Test name
Test status
Simulation time 142660576761 ps
CPU time 25.15 seconds
Started Mar 10 01:13:37 PM PDT 24
Finished Mar 10 01:14:03 PM PDT 24
Peak memory 183384 kb
Host smart-8c6ff2c6-3f5c-43bb-80b0-b2b2fc67a18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785934346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2785934346
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.32218675
Short name T243
Test name
Test status
Simulation time 449400538449 ps
CPU time 304.39 seconds
Started Mar 10 01:13:34 PM PDT 24
Finished Mar 10 01:18:38 PM PDT 24
Peak memory 191560 kb
Host smart-bb875279-27c5-4b03-891c-9467ddd854aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32218675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.32218675
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1962584269
Short name T82
Test name
Test status
Simulation time 51850443872 ps
CPU time 79.66 seconds
Started Mar 10 01:13:31 PM PDT 24
Finished Mar 10 01:14:50 PM PDT 24
Peak memory 195040 kb
Host smart-c4f7c21d-73ae-4c60-bdeb-6c0f3d134789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962584269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1962584269
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.3723195565
Short name T38
Test name
Test status
Simulation time 100332218724 ps
CPU time 921.64 seconds
Started Mar 10 01:13:34 PM PDT 24
Finished Mar 10 01:28:56 PM PDT 24
Peak memory 209376 kb
Host smart-f74a86a5-6378-42ae-9ccc-69d0f084bfa6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723195565 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.3723195565
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.756340029
Short name T213
Test name
Test status
Simulation time 920114206187 ps
CPU time 221.96 seconds
Started Mar 10 01:15:44 PM PDT 24
Finished Mar 10 01:19:26 PM PDT 24
Peak memory 191504 kb
Host smart-0ce44699-50ff-44ec-b25d-3f0fe279c992
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756340029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.756340029
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2840074942
Short name T437
Test name
Test status
Simulation time 47085818097 ps
CPU time 243.93 seconds
Started Mar 10 01:15:45 PM PDT 24
Finished Mar 10 01:19:49 PM PDT 24
Peak memory 191604 kb
Host smart-cf2dd94f-9da0-4e45-a19a-0ea2ca7f8eba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840074942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2840074942
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1664514605
Short name T321
Test name
Test status
Simulation time 32150211342 ps
CPU time 44.84 seconds
Started Mar 10 01:15:52 PM PDT 24
Finished Mar 10 01:16:38 PM PDT 24
Peak memory 183252 kb
Host smart-dae1b4c3-445b-4c36-91aa-cea24e26fb9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664514605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1664514605
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.206137565
Short name T231
Test name
Test status
Simulation time 212089146459 ps
CPU time 449.71 seconds
Started Mar 10 01:15:50 PM PDT 24
Finished Mar 10 01:23:20 PM PDT 24
Peak memory 194700 kb
Host smart-e29695a2-784b-4ffe-afe3-9ee3fbbcad83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206137565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.206137565
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.1648029377
Short name T284
Test name
Test status
Simulation time 55333097263 ps
CPU time 46.72 seconds
Started Mar 10 01:15:52 PM PDT 24
Finished Mar 10 01:16:39 PM PDT 24
Peak memory 183252 kb
Host smart-040f7599-480b-45f5-9233-e9ab08b0f419
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648029377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1648029377
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.853190355
Short name T109
Test name
Test status
Simulation time 82740866207 ps
CPU time 24.51 seconds
Started Mar 10 01:13:30 PM PDT 24
Finished Mar 10 01:13:55 PM PDT 24
Peak memory 183408 kb
Host smart-85dc0bc6-e3a4-41bc-8527-5a7ae1974a45
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853190355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.rv_timer_cfg_update_on_fly.853190355
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2156267085
Short name T388
Test name
Test status
Simulation time 86793696788 ps
CPU time 123.07 seconds
Started Mar 10 01:13:31 PM PDT 24
Finished Mar 10 01:15:34 PM PDT 24
Peak memory 183328 kb
Host smart-f1c5436c-c92c-467d-bdc9-715483c97833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156267085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2156267085
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.87125598
Short name T57
Test name
Test status
Simulation time 3569820219 ps
CPU time 8.03 seconds
Started Mar 10 01:13:41 PM PDT 24
Finished Mar 10 01:13:49 PM PDT 24
Peak memory 183348 kb
Host smart-1a52ae09-20b1-4a85-91a9-ea6322e07454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87125598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.87125598
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.535210257
Short name T221
Test name
Test status
Simulation time 1822263093241 ps
CPU time 316.5 seconds
Started Mar 10 01:13:37 PM PDT 24
Finished Mar 10 01:18:54 PM PDT 24
Peak memory 195920 kb
Host smart-9b703473-4206-429c-aaf7-9757021eabed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535210257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.
535210257
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/161.rv_timer_random.732889729
Short name T155
Test name
Test status
Simulation time 75743459947 ps
CPU time 132.78 seconds
Started Mar 10 01:15:55 PM PDT 24
Finished Mar 10 01:18:07 PM PDT 24
Peak memory 191520 kb
Host smart-5e35bc52-1952-4592-819c-d94f9f9c17c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732889729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.732889729
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.3388812979
Short name T7
Test name
Test status
Simulation time 140020585585 ps
CPU time 305.76 seconds
Started Mar 10 01:15:55 PM PDT 24
Finished Mar 10 01:21:02 PM PDT 24
Peak memory 191492 kb
Host smart-3c0586b5-a2bd-40dc-b0ae-bd9a7b3bb02c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388812979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3388812979
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.947465628
Short name T439
Test name
Test status
Simulation time 154209626961 ps
CPU time 586.44 seconds
Started Mar 10 01:15:54 PM PDT 24
Finished Mar 10 01:25:41 PM PDT 24
Peak memory 191492 kb
Host smart-bd3ab281-8d05-4408-a0a7-388a76c810a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947465628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.947465628
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.1711846989
Short name T171
Test name
Test status
Simulation time 120244495985 ps
CPU time 118.72 seconds
Started Mar 10 01:16:00 PM PDT 24
Finished Mar 10 01:18:00 PM PDT 24
Peak memory 191492 kb
Host smart-39e67813-8c73-4afe-83ac-2411a5bc8633
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711846989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1711846989
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3359191977
Short name T328
Test name
Test status
Simulation time 37950861528 ps
CPU time 66.26 seconds
Started Mar 10 01:16:04 PM PDT 24
Finished Mar 10 01:17:10 PM PDT 24
Peak memory 191584 kb
Host smart-e3ab01ca-2c3b-4b56-a8e7-d8e440903474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359191977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3359191977
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.1040761448
Short name T79
Test name
Test status
Simulation time 286173018128 ps
CPU time 96 seconds
Started Mar 10 01:16:03 PM PDT 24
Finished Mar 10 01:17:40 PM PDT 24
Peak memory 191564 kb
Host smart-4a39513e-803e-49b2-8463-107d6338f994
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040761448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1040761448
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.4060805592
Short name T371
Test name
Test status
Simulation time 655114467090 ps
CPU time 287.64 seconds
Started Mar 10 01:13:36 PM PDT 24
Finished Mar 10 01:18:24 PM PDT 24
Peak memory 183396 kb
Host smart-ea472fd0-fe04-4f2d-9db3-aa108963cc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060805592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.4060805592
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.3403364516
Short name T202
Test name
Test status
Simulation time 73244179887 ps
CPU time 58.77 seconds
Started Mar 10 01:13:45 PM PDT 24
Finished Mar 10 01:14:44 PM PDT 24
Peak memory 183356 kb
Host smart-27c46f3e-6831-419f-8d9f-2a8dc942271b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403364516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3403364516
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.2104528883
Short name T36
Test name
Test status
Simulation time 42069424970 ps
CPU time 353.01 seconds
Started Mar 10 01:13:37 PM PDT 24
Finished Mar 10 01:19:30 PM PDT 24
Peak memory 206276 kb
Host smart-3ab93b08-719b-4e6b-8e8a-8ad365a89b09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104528883 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.2104528883
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/171.rv_timer_random.677051678
Short name T450
Test name
Test status
Simulation time 119310724419 ps
CPU time 204.8 seconds
Started Mar 10 01:16:07 PM PDT 24
Finished Mar 10 01:19:32 PM PDT 24
Peak memory 191592 kb
Host smart-ab6e4c1d-f145-4bf3-a3b9-9c693b98b403
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677051678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.677051678
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.139024812
Short name T185
Test name
Test status
Simulation time 599862059732 ps
CPU time 406.45 seconds
Started Mar 10 01:16:06 PM PDT 24
Finished Mar 10 01:22:53 PM PDT 24
Peak memory 191568 kb
Host smart-9ef8abfb-4a01-41a9-ba1e-14f942d4460e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139024812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.139024812
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.376365114
Short name T203
Test name
Test status
Simulation time 636797970988 ps
CPU time 356.7 seconds
Started Mar 10 01:16:10 PM PDT 24
Finished Mar 10 01:22:07 PM PDT 24
Peak memory 191484 kb
Host smart-98d949d1-3949-49f8-9c8b-39ba4fadd017
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376365114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.376365114
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.1958993676
Short name T4
Test name
Test status
Simulation time 67747768810 ps
CPU time 104.44 seconds
Started Mar 10 01:16:09 PM PDT 24
Finished Mar 10 01:17:53 PM PDT 24
Peak memory 191512 kb
Host smart-6e26f8dc-0805-4e2b-af5c-97e08fc5d713
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958993676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1958993676
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.2454151994
Short name T119
Test name
Test status
Simulation time 65344009801 ps
CPU time 101.49 seconds
Started Mar 10 01:16:10 PM PDT 24
Finished Mar 10 01:17:52 PM PDT 24
Peak memory 194024 kb
Host smart-e34c28c8-23b6-48fe-8ddb-0baccb581998
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454151994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2454151994
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2557713652
Short name T357
Test name
Test status
Simulation time 47432341686 ps
CPU time 47.26 seconds
Started Mar 10 01:13:36 PM PDT 24
Finished Mar 10 01:14:24 PM PDT 24
Peak memory 183304 kb
Host smart-42b97d36-fe69-4caf-995d-73f3161e6bf4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557713652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.2557713652
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_random.2849351650
Short name T434
Test name
Test status
Simulation time 116079614514 ps
CPU time 540.16 seconds
Started Mar 10 01:13:41 PM PDT 24
Finished Mar 10 01:22:41 PM PDT 24
Peak memory 191580 kb
Host smart-a2c3cb33-933e-4d9a-9eff-c4181a6b7f1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849351650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2849351650
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1910453196
Short name T260
Test name
Test status
Simulation time 42399753847 ps
CPU time 89.14 seconds
Started Mar 10 01:13:39 PM PDT 24
Finished Mar 10 01:15:08 PM PDT 24
Peak memory 183356 kb
Host smart-586e0ec8-a064-4148-b4ad-273c472d0089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910453196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1910453196
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.3124363578
Short name T34
Test name
Test status
Simulation time 34986882162 ps
CPU time 132.14 seconds
Started Mar 10 01:13:42 PM PDT 24
Finished Mar 10 01:15:54 PM PDT 24
Peak memory 198056 kb
Host smart-1360bfe0-b0da-46b7-87c0-003818d301b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124363578 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.3124363578
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.rv_timer_random.3362935989
Short name T43
Test name
Test status
Simulation time 125442271007 ps
CPU time 188.14 seconds
Started Mar 10 01:16:10 PM PDT 24
Finished Mar 10 01:19:19 PM PDT 24
Peak memory 191596 kb
Host smart-c85685dc-ca31-4317-9d53-fa32ee204347
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362935989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3362935989
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.1215261963
Short name T265
Test name
Test status
Simulation time 572313441919 ps
CPU time 290.63 seconds
Started Mar 10 01:16:17 PM PDT 24
Finished Mar 10 01:21:08 PM PDT 24
Peak memory 191536 kb
Host smart-548f0aba-29c8-46bd-9584-be0e321a2fd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215261963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1215261963
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.14944752
Short name T200
Test name
Test status
Simulation time 71719847741 ps
CPU time 189.91 seconds
Started Mar 10 01:16:15 PM PDT 24
Finished Mar 10 01:19:25 PM PDT 24
Peak memory 191536 kb
Host smart-5c69f7ba-45b2-4d3d-9136-f2d2db62ab74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14944752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.14944752
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1977777809
Short name T116
Test name
Test status
Simulation time 394904379328 ps
CPU time 270.24 seconds
Started Mar 10 01:16:14 PM PDT 24
Finished Mar 10 01:20:45 PM PDT 24
Peak memory 191608 kb
Host smart-f534ee29-bf17-4e7e-82cb-b3a4fe7bddc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977777809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1977777809
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1127577765
Short name T80
Test name
Test status
Simulation time 74601082826 ps
CPU time 39.32 seconds
Started Mar 10 01:16:17 PM PDT 24
Finished Mar 10 01:16:56 PM PDT 24
Peak memory 183404 kb
Host smart-05a21c50-27a2-4c52-9e63-bf1c2ed8a0a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127577765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1127577765
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2904836421
Short name T209
Test name
Test status
Simulation time 401246504470 ps
CPU time 290.82 seconds
Started Mar 10 01:16:15 PM PDT 24
Finished Mar 10 01:21:06 PM PDT 24
Peak memory 191556 kb
Host smart-b73bae24-b053-4db3-bcea-fef86829d4a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904836421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2904836421
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.2206892182
Short name T40
Test name
Test status
Simulation time 5272186794 ps
CPU time 8.09 seconds
Started Mar 10 01:16:21 PM PDT 24
Finished Mar 10 01:16:30 PM PDT 24
Peak memory 183016 kb
Host smart-8f7d81bc-15b2-44cf-97de-d1320a18d3a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206892182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2206892182
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.1014907851
Short name T322
Test name
Test status
Simulation time 437100305450 ps
CPU time 743.49 seconds
Started Mar 10 01:13:45 PM PDT 24
Finished Mar 10 01:26:09 PM PDT 24
Peak memory 183352 kb
Host smart-e06bc336-d7a0-4950-aa79-84a1c025a791
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014907851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.1014907851
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.2362344317
Short name T451
Test name
Test status
Simulation time 65635042297 ps
CPU time 98.41 seconds
Started Mar 10 01:13:37 PM PDT 24
Finished Mar 10 01:15:15 PM PDT 24
Peak memory 183304 kb
Host smart-f68df28b-bd54-42a9-a5bc-f71b8c22a376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362344317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2362344317
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.644054645
Short name T165
Test name
Test status
Simulation time 42347979511 ps
CPU time 49.44 seconds
Started Mar 10 01:13:37 PM PDT 24
Finished Mar 10 01:14:26 PM PDT 24
Peak memory 191636 kb
Host smart-9f6cee97-898e-49c1-9c06-6c6844c26561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644054645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.644054645
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.743409294
Short name T212
Test name
Test status
Simulation time 190971997980 ps
CPU time 185.57 seconds
Started Mar 10 01:16:21 PM PDT 24
Finished Mar 10 01:19:27 PM PDT 24
Peak memory 191504 kb
Host smart-29af6288-6abc-488a-b0ae-e6c50e4be9f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743409294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.743409294
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.4097339926
Short name T329
Test name
Test status
Simulation time 7821690546 ps
CPU time 13.9 seconds
Started Mar 10 01:16:22 PM PDT 24
Finished Mar 10 01:16:36 PM PDT 24
Peak memory 183412 kb
Host smart-264403d4-327a-4dc2-a042-ee60ec3a2784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097339926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.4097339926
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3690444718
Short name T344
Test name
Test status
Simulation time 608885256490 ps
CPU time 520.1 seconds
Started Mar 10 01:16:20 PM PDT 24
Finished Mar 10 01:25:01 PM PDT 24
Peak memory 191520 kb
Host smart-1e61252c-daf5-4609-9382-48b802681faa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690444718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3690444718
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.447643072
Short name T411
Test name
Test status
Simulation time 40125040522 ps
CPU time 39.49 seconds
Started Mar 10 01:16:21 PM PDT 24
Finished Mar 10 01:17:00 PM PDT 24
Peak memory 183376 kb
Host smart-4f2e756e-a5e3-44b1-bd15-2f6f2d17945a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447643072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.447643072
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3357079266
Short name T211
Test name
Test status
Simulation time 465258711521 ps
CPU time 154.41 seconds
Started Mar 10 01:16:26 PM PDT 24
Finished Mar 10 01:19:01 PM PDT 24
Peak memory 191564 kb
Host smart-c5fff0a9-eb51-4a92-b997-256ea3824027
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357079266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3357079266
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.2629731840
Short name T349
Test name
Test status
Simulation time 175380191666 ps
CPU time 85.73 seconds
Started Mar 10 01:16:31 PM PDT 24
Finished Mar 10 01:17:57 PM PDT 24
Peak memory 183404 kb
Host smart-9c3b3090-80c6-4899-af49-979429641b67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629731840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2629731840
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2118475602
Short name T332
Test name
Test status
Simulation time 127738372415 ps
CPU time 211.54 seconds
Started Mar 10 01:16:33 PM PDT 24
Finished Mar 10 01:20:05 PM PDT 24
Peak memory 191612 kb
Host smart-49ef661a-d907-46f7-9f20-dda9f7903c77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118475602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2118475602
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3315926892
Short name T382
Test name
Test status
Simulation time 7913207745 ps
CPU time 5.04 seconds
Started Mar 10 01:16:33 PM PDT 24
Finished Mar 10 01:16:38 PM PDT 24
Peak memory 183408 kb
Host smart-8a1a155d-5062-4474-b121-57029301849d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315926892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3315926892
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1586645304
Short name T404
Test name
Test status
Simulation time 69160409309 ps
CPU time 102.06 seconds
Started Mar 10 01:13:22 PM PDT 24
Finished Mar 10 01:15:04 PM PDT 24
Peak memory 183396 kb
Host smart-24a2e9a4-0dcd-4c24-b0b5-7b5376e9c324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586645304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1586645304
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.2441587841
Short name T406
Test name
Test status
Simulation time 142866113001 ps
CPU time 44.17 seconds
Started Mar 10 01:13:22 PM PDT 24
Finished Mar 10 01:14:07 PM PDT 24
Peak memory 195580 kb
Host smart-62ba4204-620a-4247-a192-6e8d94d69893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441587841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2441587841
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3019152008
Short name T16
Test name
Test status
Simulation time 328155784 ps
CPU time 0.95 seconds
Started Mar 10 01:13:18 PM PDT 24
Finished Mar 10 01:13:19 PM PDT 24
Peak memory 214612 kb
Host smart-719b4b4c-2ebb-4072-a5a6-23850cdc1649
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019152008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3019152008
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2851376897
Short name T363
Test name
Test status
Simulation time 1097115262330 ps
CPU time 575.87 seconds
Started Mar 10 01:13:38 PM PDT 24
Finished Mar 10 01:23:14 PM PDT 24
Peak memory 183396 kb
Host smart-0e78fcde-7cd7-4e5c-b108-b1c0b06e38db
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851376897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2851376897
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1823943633
Short name T380
Test name
Test status
Simulation time 211310696302 ps
CPU time 178.61 seconds
Started Mar 10 01:13:44 PM PDT 24
Finished Mar 10 01:16:42 PM PDT 24
Peak memory 183380 kb
Host smart-f49e3e29-e40b-4876-b432-672e5660e6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823943633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1823943633
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.360868853
Short name T230
Test name
Test status
Simulation time 661740159746 ps
CPU time 3210.41 seconds
Started Mar 10 01:13:43 PM PDT 24
Finished Mar 10 02:07:14 PM PDT 24
Peak memory 191604 kb
Host smart-b4efecbc-5655-4f48-a72b-dab9a5336762
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360868853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.360868853
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.2451382249
Short name T418
Test name
Test status
Simulation time 212930682 ps
CPU time 2.13 seconds
Started Mar 10 01:13:35 PM PDT 24
Finished Mar 10 01:13:38 PM PDT 24
Peak memory 183228 kb
Host smart-dea19c01-1d13-487c-ad75-638973009682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451382249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2451382249
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.825217707
Short name T297
Test name
Test status
Simulation time 513751511880 ps
CPU time 864.8 seconds
Started Mar 10 01:13:45 PM PDT 24
Finished Mar 10 01:28:10 PM PDT 24
Peak memory 183316 kb
Host smart-b1ef81d3-0a20-4424-a0bb-52ee6e563219
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825217707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.rv_timer_cfg_update_on_fly.825217707
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3955858733
Short name T390
Test name
Test status
Simulation time 278775746286 ps
CPU time 182.28 seconds
Started Mar 10 01:13:38 PM PDT 24
Finished Mar 10 01:16:41 PM PDT 24
Peak memory 183308 kb
Host smart-68fa74d5-47fe-4d9b-bc91-fb66f70768ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955858733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3955858733
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.1710594056
Short name T107
Test name
Test status
Simulation time 229610854201 ps
CPU time 290.4 seconds
Started Mar 10 01:13:41 PM PDT 24
Finished Mar 10 01:18:31 PM PDT 24
Peak memory 191604 kb
Host smart-8ce5d580-00e2-46c8-90ff-4565b5de69dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710594056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1710594056
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1084351115
Short name T300
Test name
Test status
Simulation time 87289671854 ps
CPU time 85.82 seconds
Started Mar 10 01:13:36 PM PDT 24
Finished Mar 10 01:15:01 PM PDT 24
Peak memory 183344 kb
Host smart-26b9186d-ebf6-4253-a264-15b677daa969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084351115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1084351115
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1808502248
Short name T226
Test name
Test status
Simulation time 923849667074 ps
CPU time 728.82 seconds
Started Mar 10 01:13:39 PM PDT 24
Finished Mar 10 01:25:48 PM PDT 24
Peak memory 195584 kb
Host smart-78e0a0fe-4fac-4dae-8a1c-ea8cc578b766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808502248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1808502248
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.1423731153
Short name T44
Test name
Test status
Simulation time 32577774134 ps
CPU time 263.16 seconds
Started Mar 10 01:13:39 PM PDT 24
Finished Mar 10 01:18:02 PM PDT 24
Peak memory 197976 kb
Host smart-45bd7a19-b6aa-461f-8ca6-9d990f58cd2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423731153 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.1423731153
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.4287489141
Short name T453
Test name
Test status
Simulation time 1311121579438 ps
CPU time 452.13 seconds
Started Mar 10 01:13:37 PM PDT 24
Finished Mar 10 01:21:10 PM PDT 24
Peak memory 183388 kb
Host smart-2578f851-a920-4136-a962-3fc199cf4d9d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287489141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.4287489141
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.1964510373
Short name T23
Test name
Test status
Simulation time 556318789043 ps
CPU time 233.22 seconds
Started Mar 10 01:13:37 PM PDT 24
Finished Mar 10 01:17:31 PM PDT 24
Peak memory 183392 kb
Host smart-aa03f2fd-117a-4385-8130-f78863498ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964510373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1964510373
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.3275485018
Short name T132
Test name
Test status
Simulation time 14687874887 ps
CPU time 25.45 seconds
Started Mar 10 01:13:41 PM PDT 24
Finished Mar 10 01:14:07 PM PDT 24
Peak memory 183404 kb
Host smart-2dc39bfd-87ff-498f-9f81-ebc93fe54c13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275485018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3275485018
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.3085261720
Short name T39
Test name
Test status
Simulation time 52817550030 ps
CPU time 423.57 seconds
Started Mar 10 01:13:46 PM PDT 24
Finished Mar 10 01:20:50 PM PDT 24
Peak memory 206284 kb
Host smart-8c720761-4635-4c46-8559-3c7840eb587b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085261720 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.3085261720
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1241395529
Short name T22
Test name
Test status
Simulation time 299166711326 ps
CPU time 564.7 seconds
Started Mar 10 01:13:39 PM PDT 24
Finished Mar 10 01:23:03 PM PDT 24
Peak memory 183280 kb
Host smart-e3ba26d4-bdde-4d31-803f-68d6227a7202
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241395529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1241395529
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1877699020
Short name T449
Test name
Test status
Simulation time 98094171690 ps
CPU time 35.47 seconds
Started Mar 10 01:13:38 PM PDT 24
Finished Mar 10 01:14:13 PM PDT 24
Peak memory 183268 kb
Host smart-afc728f9-5d94-4c80-9967-a8b6fd3894ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877699020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1877699020
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3997664659
Short name T85
Test name
Test status
Simulation time 122656782 ps
CPU time 0.67 seconds
Started Mar 10 01:13:46 PM PDT 24
Finished Mar 10 01:13:47 PM PDT 24
Peak memory 183008 kb
Host smart-312cb793-1934-4193-bf4e-f9cecc385043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997664659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3997664659
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2421932022
Short name T423
Test name
Test status
Simulation time 743218413877 ps
CPU time 748.04 seconds
Started Mar 10 01:13:38 PM PDT 24
Finished Mar 10 01:26:06 PM PDT 24
Peak memory 183308 kb
Host smart-7bfd1422-0d44-4e72-8bfe-871dd12f7b96
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421932022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2421932022
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.1149897031
Short name T443
Test name
Test status
Simulation time 6845455521 ps
CPU time 9.48 seconds
Started Mar 10 01:13:40 PM PDT 24
Finished Mar 10 01:13:49 PM PDT 24
Peak memory 183392 kb
Host smart-255e37af-34e9-488b-bf15-8d6081607db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149897031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.1149897031
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.18985010
Short name T111
Test name
Test status
Simulation time 191782245489 ps
CPU time 440.31 seconds
Started Mar 10 01:13:45 PM PDT 24
Finished Mar 10 01:21:05 PM PDT 24
Peak memory 191544 kb
Host smart-4c465eb9-b7e7-4a21-83c5-cb38ec6abef8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18985010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.18985010
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1679512098
Short name T366
Test name
Test status
Simulation time 2509933278 ps
CPU time 1.28 seconds
Started Mar 10 01:13:45 PM PDT 24
Finished Mar 10 01:13:46 PM PDT 24
Peak memory 191548 kb
Host smart-1713456d-acb6-4751-84d3-1dccb1aac43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679512098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1679512098
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.4128275317
Short name T343
Test name
Test status
Simulation time 1484525439469 ps
CPU time 896.93 seconds
Started Mar 10 01:13:40 PM PDT 24
Finished Mar 10 01:28:37 PM PDT 24
Peak memory 183312 kb
Host smart-6e8af96b-b912-488e-b49f-c5b5bd4ee279
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128275317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.4128275317
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.523324355
Short name T374
Test name
Test status
Simulation time 99071441287 ps
CPU time 138.47 seconds
Started Mar 10 01:13:43 PM PDT 24
Finished Mar 10 01:16:02 PM PDT 24
Peak memory 183344 kb
Host smart-c2541d7a-2c36-42de-948e-895f13d4acc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523324355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.523324355
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.1441816116
Short name T125
Test name
Test status
Simulation time 162806530606 ps
CPU time 302.39 seconds
Started Mar 10 01:13:43 PM PDT 24
Finished Mar 10 01:18:46 PM PDT 24
Peak memory 191572 kb
Host smart-b397d382-a1fd-4e07-867b-6733c68ca03b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441816116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1441816116
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.16501951
Short name T455
Test name
Test status
Simulation time 21166757619 ps
CPU time 82.51 seconds
Started Mar 10 01:13:40 PM PDT 24
Finished Mar 10 01:15:03 PM PDT 24
Peak memory 183308 kb
Host smart-db95f1a9-7233-4d70-91a2-1bc0e1eb8263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16501951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.16501951
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2443855149
Short name T67
Test name
Test status
Simulation time 616811782859 ps
CPU time 505.97 seconds
Started Mar 10 01:13:42 PM PDT 24
Finished Mar 10 01:22:08 PM PDT 24
Peak memory 191572 kb
Host smart-569c6fab-5111-4bd2-8fff-849129b8615c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443855149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2443855149
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.610893646
Short name T325
Test name
Test status
Simulation time 1319769351801 ps
CPU time 759.65 seconds
Started Mar 10 01:13:46 PM PDT 24
Finished Mar 10 01:26:26 PM PDT 24
Peak memory 183372 kb
Host smart-c3d94c89-f84c-43d3-ae2c-d1f0cfc2e166
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610893646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.610893646
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.3743234883
Short name T441
Test name
Test status
Simulation time 49872365037 ps
CPU time 74.74 seconds
Started Mar 10 01:13:42 PM PDT 24
Finished Mar 10 01:14:57 PM PDT 24
Peak memory 183392 kb
Host smart-0fc496f6-957d-43ac-a73b-ba742ecf259c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743234883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3743234883
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.622081162
Short name T359
Test name
Test status
Simulation time 141569383898 ps
CPU time 75.21 seconds
Started Mar 10 01:13:43 PM PDT 24
Finished Mar 10 01:14:58 PM PDT 24
Peak memory 191516 kb
Host smart-903967a1-93a3-4ceb-91b8-691cb0ef4d1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622081162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.622081162
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.1897615783
Short name T341
Test name
Test status
Simulation time 3705734311 ps
CPU time 28.07 seconds
Started Mar 10 01:13:43 PM PDT 24
Finished Mar 10 01:14:11 PM PDT 24
Peak memory 183252 kb
Host smart-64e6b252-0677-49f8-872d-4cb23e534901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897615783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1897615783
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.2348163988
Short name T228
Test name
Test status
Simulation time 400055564706 ps
CPU time 665.25 seconds
Started Mar 10 01:13:42 PM PDT 24
Finished Mar 10 01:24:47 PM PDT 24
Peak memory 195424 kb
Host smart-a298dc0e-2fc9-4d1f-a398-b79c5c7cb96e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348163988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.2348163988
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2160700226
Short name T24
Test name
Test status
Simulation time 457009629206 ps
CPU time 816.53 seconds
Started Mar 10 01:13:42 PM PDT 24
Finished Mar 10 01:27:19 PM PDT 24
Peak memory 183424 kb
Host smart-84f0970a-31ae-41bf-8cdc-846992dd1762
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160700226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.2160700226
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.4255390508
Short name T407
Test name
Test status
Simulation time 72969607843 ps
CPU time 101.96 seconds
Started Mar 10 01:13:41 PM PDT 24
Finished Mar 10 01:15:23 PM PDT 24
Peak memory 183264 kb
Host smart-532870d3-766f-4439-ac02-4474c6cd6fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255390508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.4255390508
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.2069547980
Short name T326
Test name
Test status
Simulation time 150329154063 ps
CPU time 182.68 seconds
Started Mar 10 01:13:47 PM PDT 24
Finished Mar 10 01:16:50 PM PDT 24
Peak memory 193820 kb
Host smart-b56b4fb9-4ce9-465b-9ee4-e07e4f3608cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069547980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2069547980
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3907602104
Short name T133
Test name
Test status
Simulation time 34989181299 ps
CPU time 36.88 seconds
Started Mar 10 01:13:47 PM PDT 24
Finished Mar 10 01:14:24 PM PDT 24
Peak memory 183304 kb
Host smart-cd203a2d-6518-4091-9905-68efed5cce86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907602104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3907602104
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1853108886
Short name T106
Test name
Test status
Simulation time 488620746519 ps
CPU time 495.57 seconds
Started Mar 10 01:13:42 PM PDT 24
Finished Mar 10 01:21:58 PM PDT 24
Peak memory 183396 kb
Host smart-30bf4841-6d0b-4513-8774-cfa52e107a2f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853108886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1853108886
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.1251405537
Short name T448
Test name
Test status
Simulation time 463430030517 ps
CPU time 188.64 seconds
Started Mar 10 01:13:43 PM PDT 24
Finished Mar 10 01:16:51 PM PDT 24
Peak memory 183264 kb
Host smart-62fe098c-daa1-46bc-82bb-00a1d8cfd484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251405537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1251405537
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.1085094086
Short name T190
Test name
Test status
Simulation time 507815222846 ps
CPU time 735.66 seconds
Started Mar 10 01:13:41 PM PDT 24
Finished Mar 10 01:25:56 PM PDT 24
Peak memory 194284 kb
Host smart-d0e825c5-132f-4f9e-b77a-91093fc0e8af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085094086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1085094086
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1349147116
Short name T234
Test name
Test status
Simulation time 54757860065 ps
CPU time 73 seconds
Started Mar 10 01:13:44 PM PDT 24
Finished Mar 10 01:14:57 PM PDT 24
Peak memory 191608 kb
Host smart-3165c56c-aeb7-488b-a4fd-7a04346c1036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349147116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1349147116
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3800988419
Short name T166
Test name
Test status
Simulation time 61298616297 ps
CPU time 114.36 seconds
Started Mar 10 01:13:41 PM PDT 24
Finished Mar 10 01:15:35 PM PDT 24
Peak memory 183380 kb
Host smart-35c72e76-9be8-48e4-a561-45af9fd4347f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800988419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.3800988419
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.4229283522
Short name T416
Test name
Test status
Simulation time 43846927315 ps
CPU time 63.35 seconds
Started Mar 10 01:13:46 PM PDT 24
Finished Mar 10 01:14:50 PM PDT 24
Peak memory 183312 kb
Host smart-40a84a03-b76e-4ad4-9860-4082e0f4f263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229283522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.4229283522
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.2538175801
Short name T120
Test name
Test status
Simulation time 17743528141 ps
CPU time 56.68 seconds
Started Mar 10 01:13:42 PM PDT 24
Finished Mar 10 01:14:39 PM PDT 24
Peak memory 183320 kb
Host smart-7c750cf3-a83f-4c7a-86ba-598be8cb88c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538175801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2538175801
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2467415075
Short name T438
Test name
Test status
Simulation time 100054403353 ps
CPU time 19.85 seconds
Started Mar 10 01:13:45 PM PDT 24
Finished Mar 10 01:14:05 PM PDT 24
Peak memory 183316 kb
Host smart-5bd222d1-feed-461f-a548-979e0b4daca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467415075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2467415075
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.4038082337
Short name T308
Test name
Test status
Simulation time 10594532659 ps
CPU time 20.18 seconds
Started Mar 10 01:13:23 PM PDT 24
Finished Mar 10 01:13:44 PM PDT 24
Peak memory 183444 kb
Host smart-173202f6-56ee-41f4-9349-114b8bd9227c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038082337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.4038082337
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1644230621
Short name T369
Test name
Test status
Simulation time 577797676484 ps
CPU time 229.67 seconds
Started Mar 10 01:13:23 PM PDT 24
Finished Mar 10 01:17:13 PM PDT 24
Peak memory 183340 kb
Host smart-1c6c8283-0ed0-4e00-8cc7-933529b36c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644230621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1644230621
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.2523235409
Short name T83
Test name
Test status
Simulation time 60009208947 ps
CPU time 239.06 seconds
Started Mar 10 01:13:13 PM PDT 24
Finished Mar 10 01:17:13 PM PDT 24
Peak memory 183412 kb
Host smart-86d89dd2-b102-4aaa-95e3-a7e672c430b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523235409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.2523235409
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3116409313
Short name T227
Test name
Test status
Simulation time 40096525875 ps
CPU time 43.84 seconds
Started Mar 10 01:13:20 PM PDT 24
Finished Mar 10 01:14:04 PM PDT 24
Peak memory 191548 kb
Host smart-2dfb404a-6814-4fba-9b2a-836574f7c435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116409313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3116409313
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3087849007
Short name T247
Test name
Test status
Simulation time 538358022597 ps
CPU time 329.51 seconds
Started Mar 10 01:13:43 PM PDT 24
Finished Mar 10 01:19:13 PM PDT 24
Peak memory 183268 kb
Host smart-2db6d8c2-7d62-451f-96aa-589656c266ed
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087849007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3087849007
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.4271808771
Short name T381
Test name
Test status
Simulation time 72013613111 ps
CPU time 30.38 seconds
Started Mar 10 01:13:46 PM PDT 24
Finished Mar 10 01:14:16 PM PDT 24
Peak memory 183376 kb
Host smart-60a4d448-66d5-42c5-a5d3-8cb79a091455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271808771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.4271808771
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.207838299
Short name T320
Test name
Test status
Simulation time 150345715214 ps
CPU time 536.03 seconds
Started Mar 10 01:13:43 PM PDT 24
Finished Mar 10 01:22:39 PM PDT 24
Peak memory 195076 kb
Host smart-6f84da8f-922d-4dd3-9cfb-0a1cbbcf9bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207838299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.207838299
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2819254174
Short name T118
Test name
Test status
Simulation time 924642126912 ps
CPU time 474.16 seconds
Started Mar 10 01:13:51 PM PDT 24
Finished Mar 10 01:21:45 PM PDT 24
Peak memory 183364 kb
Host smart-b92d817e-44fc-4531-b674-57ec9e690dcc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819254174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2819254174
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.2116466166
Short name T414
Test name
Test status
Simulation time 547514450768 ps
CPU time 230.91 seconds
Started Mar 10 01:13:54 PM PDT 24
Finished Mar 10 01:17:45 PM PDT 24
Peak memory 183392 kb
Host smart-358e5352-ff8d-4a25-98b9-069f0e07c3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116466166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.2116466166
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.976793714
Short name T442
Test name
Test status
Simulation time 57474819357 ps
CPU time 378.78 seconds
Started Mar 10 01:13:52 PM PDT 24
Finished Mar 10 01:20:11 PM PDT 24
Peak memory 191316 kb
Host smart-50d539d5-5e14-44da-a642-d622f6e2a1eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976793714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.976793714
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.1169413204
Short name T2
Test name
Test status
Simulation time 44298451 ps
CPU time 0.56 seconds
Started Mar 10 01:13:49 PM PDT 24
Finished Mar 10 01:13:50 PM PDT 24
Peak memory 182940 kb
Host smart-119b8b2c-e01f-445c-a8ca-5798351dea93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169413204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1169413204
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2546802041
Short name T392
Test name
Test status
Simulation time 339731630631 ps
CPU time 238.15 seconds
Started Mar 10 01:13:47 PM PDT 24
Finished Mar 10 01:17:46 PM PDT 24
Peak memory 191584 kb
Host smart-b7ba31d8-2422-4d9d-8319-d692996d2c37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546802041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2546802041
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.749010035
Short name T37
Test name
Test status
Simulation time 65549146643 ps
CPU time 473.95 seconds
Started Mar 10 01:13:48 PM PDT 24
Finished Mar 10 01:21:42 PM PDT 24
Peak memory 206816 kb
Host smart-d5a92656-8646-45b5-bbb8-cf7c036bba15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749010035 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.749010035
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.4017009062
Short name T86
Test name
Test status
Simulation time 235927211385 ps
CPU time 69.38 seconds
Started Mar 10 01:13:49 PM PDT 24
Finished Mar 10 01:14:58 PM PDT 24
Peak memory 183376 kb
Host smart-2bd637ef-bdb3-4bf4-bbdb-b56304cb6e03
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017009062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.4017009062
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.1016218867
Short name T394
Test name
Test status
Simulation time 191755172922 ps
CPU time 81.03 seconds
Started Mar 10 01:13:48 PM PDT 24
Finished Mar 10 01:15:09 PM PDT 24
Peak memory 183392 kb
Host smart-46a889b4-1c56-436f-b27b-d89ff17685f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016218867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.1016218867
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.4284483378
Short name T314
Test name
Test status
Simulation time 213562501461 ps
CPU time 551.85 seconds
Started Mar 10 01:13:54 PM PDT 24
Finished Mar 10 01:23:06 PM PDT 24
Peak memory 183408 kb
Host smart-0b4a7db7-0cab-462b-ad0d-704136adbeef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284483378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.4284483378
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.3089830168
Short name T299
Test name
Test status
Simulation time 22643048527 ps
CPU time 21.09 seconds
Started Mar 10 01:13:50 PM PDT 24
Finished Mar 10 01:14:11 PM PDT 24
Peak memory 183300 kb
Host smart-2781ea03-08ea-4851-a74d-d538582ce038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089830168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3089830168
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2299180880
Short name T385
Test name
Test status
Simulation time 87454394141 ps
CPU time 132.25 seconds
Started Mar 10 01:13:48 PM PDT 24
Finished Mar 10 01:16:00 PM PDT 24
Peak memory 183372 kb
Host smart-4a55a1f4-ba1b-44ba-95a6-d1e08344b56b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299180880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2299180880
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.2419163124
Short name T400
Test name
Test status
Simulation time 104987922422 ps
CPU time 81.09 seconds
Started Mar 10 01:13:48 PM PDT 24
Finished Mar 10 01:15:09 PM PDT 24
Peak memory 183388 kb
Host smart-c917728e-d2df-4533-a090-89bcab944b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419163124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2419163124
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.3851418012
Short name T331
Test name
Test status
Simulation time 1577870771242 ps
CPU time 274.33 seconds
Started Mar 10 01:13:48 PM PDT 24
Finished Mar 10 01:18:23 PM PDT 24
Peak memory 191552 kb
Host smart-009d52fa-0947-4145-b4c8-79b1cef525a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851418012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3851418012
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.294498517
Short name T169
Test name
Test status
Simulation time 103650779986 ps
CPU time 204.51 seconds
Started Mar 10 01:13:48 PM PDT 24
Finished Mar 10 01:17:13 PM PDT 24
Peak memory 194896 kb
Host smart-d19c9579-0283-418c-988a-f32879ede3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294498517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.294498517
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.1637957108
Short name T11
Test name
Test status
Simulation time 22609431391 ps
CPU time 110.02 seconds
Started Mar 10 01:13:48 PM PDT 24
Finished Mar 10 01:15:38 PM PDT 24
Peak memory 198088 kb
Host smart-e3749278-2b53-4eb8-8f93-c6a8c657a06b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637957108 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.1637957108
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.72235642
Short name T172
Test name
Test status
Simulation time 109710567358 ps
CPU time 60.71 seconds
Started Mar 10 01:13:50 PM PDT 24
Finished Mar 10 01:14:51 PM PDT 24
Peak memory 183384 kb
Host smart-a4804f91-2088-4d63-8190-92b5bd229cfd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72235642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.rv_timer_cfg_update_on_fly.72235642
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3533490604
Short name T377
Test name
Test status
Simulation time 133260133017 ps
CPU time 94.59 seconds
Started Mar 10 01:13:48 PM PDT 24
Finished Mar 10 01:15:23 PM PDT 24
Peak memory 183220 kb
Host smart-1c0ab34f-7aaf-43ff-bf7e-f9fdf6f44254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533490604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3533490604
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.2852261056
Short name T124
Test name
Test status
Simulation time 293311872619 ps
CPU time 350.78 seconds
Started Mar 10 01:13:51 PM PDT 24
Finished Mar 10 01:19:43 PM PDT 24
Peak memory 193752 kb
Host smart-63a5d6ac-ffc6-40ce-b598-bd6e8de50e8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852261056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2852261056
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.1418148098
Short name T376
Test name
Test status
Simulation time 408621017 ps
CPU time 1.2 seconds
Started Mar 10 01:13:48 PM PDT 24
Finished Mar 10 01:13:49 PM PDT 24
Peak memory 183188 kb
Host smart-61f81a03-d0fa-47aa-ab5f-0df6ee80de3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418148098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.1418148098
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3815667810
Short name T383
Test name
Test status
Simulation time 311170035983 ps
CPU time 447.5 seconds
Started Mar 10 01:13:49 PM PDT 24
Finished Mar 10 01:21:17 PM PDT 24
Peak memory 194696 kb
Host smart-b58de19a-2b49-4f7e-9155-199d2d33303f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815667810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3815667810
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.4180263457
Short name T1
Test name
Test status
Simulation time 429588629076 ps
CPU time 765.17 seconds
Started Mar 10 01:13:49 PM PDT 24
Finished Mar 10 01:26:35 PM PDT 24
Peak memory 183408 kb
Host smart-9f7099e4-8894-432c-88d4-b8f4c6280b65
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180263457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.4180263457
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.677609951
Short name T399
Test name
Test status
Simulation time 421587422209 ps
CPU time 179.8 seconds
Started Mar 10 01:13:48 PM PDT 24
Finished Mar 10 01:16:48 PM PDT 24
Peak memory 183336 kb
Host smart-c37c4e46-40c5-473f-b158-5c0324b391f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677609951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.677609951
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.4185456491
Short name T229
Test name
Test status
Simulation time 354358093018 ps
CPU time 1202.93 seconds
Started Mar 10 01:13:49 PM PDT 24
Finished Mar 10 01:33:52 PM PDT 24
Peak memory 191488 kb
Host smart-9bdb4c49-e544-4f29-b8d5-f58d527df7a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185456491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.4185456491
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.3593039017
Short name T152
Test name
Test status
Simulation time 74264692945 ps
CPU time 71.31 seconds
Started Mar 10 01:13:48 PM PDT 24
Finished Mar 10 01:14:59 PM PDT 24
Peak memory 183276 kb
Host smart-9fe4d63a-fe37-4403-843c-397f0ab59de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593039017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3593039017
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.710874700
Short name T53
Test name
Test status
Simulation time 516532027826 ps
CPU time 292.24 seconds
Started Mar 10 01:13:56 PM PDT 24
Finished Mar 10 01:18:49 PM PDT 24
Peak memory 183328 kb
Host smart-26e26116-76aa-451f-b163-f6cd6ba9401b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710874700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.rv_timer_cfg_update_on_fly.710874700
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.477207786
Short name T389
Test name
Test status
Simulation time 143014730185 ps
CPU time 108.23 seconds
Started Mar 10 01:13:54 PM PDT 24
Finished Mar 10 01:15:42 PM PDT 24
Peak memory 183376 kb
Host smart-3141acc0-8da0-499f-b45d-6a4339f81541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477207786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.477207786
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.2683582522
Short name T261
Test name
Test status
Simulation time 352554264317 ps
CPU time 422.67 seconds
Started Mar 10 01:14:01 PM PDT 24
Finished Mar 10 01:21:04 PM PDT 24
Peak memory 191588 kb
Host smart-8b290730-3eac-47e8-894d-284ed2f1f24f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683582522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2683582522
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.786744727
Short name T163
Test name
Test status
Simulation time 393480030893 ps
CPU time 213.59 seconds
Started Mar 10 01:13:57 PM PDT 24
Finished Mar 10 01:17:31 PM PDT 24
Peak memory 183400 kb
Host smart-633546db-a932-42c9-9f07-82035c0f30ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786744727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.786744727
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.263455900
Short name T365
Test name
Test status
Simulation time 138174245268 ps
CPU time 187.26 seconds
Started Mar 10 01:13:56 PM PDT 24
Finished Mar 10 01:17:03 PM PDT 24
Peak memory 183236 kb
Host smart-bd2656b5-29f8-40cf-af82-da0126f4b61b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263455900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.263455900
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.4039960552
Short name T386
Test name
Test status
Simulation time 89583295909 ps
CPU time 130.5 seconds
Started Mar 10 01:13:57 PM PDT 24
Finished Mar 10 01:16:08 PM PDT 24
Peak memory 183344 kb
Host smart-341e9000-22ec-4836-baaa-55ecc6446a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039960552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.4039960552
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2346368554
Short name T412
Test name
Test status
Simulation time 14369895063 ps
CPU time 14.47 seconds
Started Mar 10 01:13:55 PM PDT 24
Finished Mar 10 01:14:10 PM PDT 24
Peak memory 195144 kb
Host smart-1533df0e-c876-46c1-b43f-15a2e4d4969f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346368554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2346368554
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3950260770
Short name T393
Test name
Test status
Simulation time 51961531719 ps
CPU time 74.92 seconds
Started Mar 10 01:13:55 PM PDT 24
Finished Mar 10 01:15:10 PM PDT 24
Peak memory 183208 kb
Host smart-50746030-879e-4e31-bf16-843ab1738fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950260770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3950260770
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.2751260452
Short name T65
Test name
Test status
Simulation time 1695906297113 ps
CPU time 701.06 seconds
Started Mar 10 01:13:55 PM PDT 24
Finished Mar 10 01:25:36 PM PDT 24
Peak memory 191628 kb
Host smart-41ae9f41-8a1b-4757-a5bd-f4f37334e0f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751260452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.2751260452
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3404156073
Short name T379
Test name
Test status
Simulation time 30619788569 ps
CPU time 47.05 seconds
Started Mar 10 01:13:56 PM PDT 24
Finished Mar 10 01:14:43 PM PDT 24
Peak memory 183380 kb
Host smart-75463544-d166-4acf-acd6-ebc21a590a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404156073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3404156073
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.2967037964
Short name T447
Test name
Test status
Simulation time 91142554519 ps
CPU time 1085.89 seconds
Started Mar 10 01:13:55 PM PDT 24
Finished Mar 10 01:32:01 PM PDT 24
Peak memory 191520 kb
Host smart-29195c86-9879-4bf3-ad34-5d986e2ff1e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967037964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2967037964
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3124322601
Short name T58
Test name
Test status
Simulation time 229403257713 ps
CPU time 408.31 seconds
Started Mar 10 01:13:57 PM PDT 24
Finished Mar 10 01:20:46 PM PDT 24
Peak memory 195096 kb
Host smart-18d47822-d0c1-4b88-91c6-715897bbdcb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124322601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3124322601
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.126239505
Short name T356
Test name
Test status
Simulation time 666544527865 ps
CPU time 405.89 seconds
Started Mar 10 01:13:13 PM PDT 24
Finished Mar 10 01:20:00 PM PDT 24
Peak memory 183328 kb
Host smart-829674c3-86d6-4b4d-9c41-b2c97b6b1dfd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126239505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.rv_timer_cfg_update_on_fly.126239505
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.792760485
Short name T378
Test name
Test status
Simulation time 394437260795 ps
CPU time 174.6 seconds
Started Mar 10 01:13:11 PM PDT 24
Finished Mar 10 01:16:06 PM PDT 24
Peak memory 183220 kb
Host smart-6b9caf30-3dd4-4b20-9e38-fa3d81221637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792760485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.792760485
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.3433374750
Short name T249
Test name
Test status
Simulation time 175995738299 ps
CPU time 259.58 seconds
Started Mar 10 01:13:25 PM PDT 24
Finished Mar 10 01:17:45 PM PDT 24
Peak memory 194480 kb
Host smart-54b05aa7-126f-427a-ade6-3223371c6dee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433374750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3433374750
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2102038666
Short name T196
Test name
Test status
Simulation time 172144518427 ps
CPU time 62.31 seconds
Started Mar 10 01:13:14 PM PDT 24
Finished Mar 10 01:14:16 PM PDT 24
Peak memory 193872 kb
Host smart-27cbb79b-1441-43e7-a406-b22743348b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102038666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2102038666
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.1997706501
Short name T17
Test name
Test status
Simulation time 343125107 ps
CPU time 0.93 seconds
Started Mar 10 01:13:13 PM PDT 24
Finished Mar 10 01:13:15 PM PDT 24
Peak memory 214632 kb
Host smart-55797469-c371-4afe-962c-235ea407dcba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997706501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1997706501
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.2943716253
Short name T373
Test name
Test status
Simulation time 1325606023301 ps
CPU time 321.09 seconds
Started Mar 10 01:13:17 PM PDT 24
Finished Mar 10 01:18:38 PM PDT 24
Peak memory 194868 kb
Host smart-427b95f9-0526-4d33-97c8-d015e2330cb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943716253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
2943716253
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1727181204
Short name T175
Test name
Test status
Simulation time 926454838043 ps
CPU time 505.78 seconds
Started Mar 10 01:13:58 PM PDT 24
Finished Mar 10 01:22:24 PM PDT 24
Peak memory 183412 kb
Host smart-244efc6c-f50a-4b3f-a3fa-70d1b35b1821
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727181204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1727181204
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.3483133003
Short name T372
Test name
Test status
Simulation time 4116698436 ps
CPU time 7.18 seconds
Started Mar 10 01:13:58 PM PDT 24
Finished Mar 10 01:14:05 PM PDT 24
Peak memory 183208 kb
Host smart-e58c6f74-7458-418a-a10f-15cdd9ab27b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483133003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.3483133003
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.2943700796
Short name T189
Test name
Test status
Simulation time 379475501345 ps
CPU time 1467.39 seconds
Started Mar 10 01:13:55 PM PDT 24
Finished Mar 10 01:38:23 PM PDT 24
Peak memory 191556 kb
Host smart-7bfae85b-5dae-4ef2-9a68-7ae808f60ee6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943700796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2943700796
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.3245112366
Short name T354
Test name
Test status
Simulation time 104636833955 ps
CPU time 98.13 seconds
Started Mar 10 01:13:58 PM PDT 24
Finished Mar 10 01:15:36 PM PDT 24
Peak memory 195020 kb
Host smart-bb7384f7-f740-48a0-9333-fded22402392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245112366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3245112366
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.388607536
Short name T63
Test name
Test status
Simulation time 876468880771 ps
CPU time 661.64 seconds
Started Mar 10 01:14:00 PM PDT 24
Finished Mar 10 01:25:02 PM PDT 24
Peak memory 191600 kb
Host smart-43a1bd55-7174-4ff5-96d3-387ccef43400
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388607536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.
388607536
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2793576411
Short name T217
Test name
Test status
Simulation time 133445924105 ps
CPU time 233.47 seconds
Started Mar 10 01:14:03 PM PDT 24
Finished Mar 10 01:17:57 PM PDT 24
Peak memory 183420 kb
Host smart-a02e7f3a-0077-446d-b01b-c4f0816ddcad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793576411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2793576411
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3302032856
Short name T52
Test name
Test status
Simulation time 646547695917 ps
CPU time 270.52 seconds
Started Mar 10 01:14:05 PM PDT 24
Finished Mar 10 01:18:36 PM PDT 24
Peak memory 183284 kb
Host smart-f6007a20-2f5e-4796-ad99-931f83f108c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302032856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3302032856
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1945258067
Short name T446
Test name
Test status
Simulation time 1629185095207 ps
CPU time 607.24 seconds
Started Mar 10 01:13:59 PM PDT 24
Finished Mar 10 01:24:07 PM PDT 24
Peak memory 193852 kb
Host smart-96e1b940-33fb-4bd0-8329-bfbcc656b1ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945258067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1945258067
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2951108212
Short name T402
Test name
Test status
Simulation time 1482154188 ps
CPU time 1.29 seconds
Started Mar 10 01:13:59 PM PDT 24
Finished Mar 10 01:14:00 PM PDT 24
Peak memory 183100 kb
Host smart-f05d0a76-a1dc-4dce-b157-a5ba1db5c18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951108212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2951108212
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.518632714
Short name T303
Test name
Test status
Simulation time 268087297563 ps
CPU time 175.4 seconds
Started Mar 10 01:14:03 PM PDT 24
Finished Mar 10 01:16:59 PM PDT 24
Peak memory 183300 kb
Host smart-78212ca9-76ff-46cd-a3cd-7d5ff6920ce9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518632714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.518632714
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.593034785
Short name T427
Test name
Test status
Simulation time 323293846293 ps
CPU time 231.34 seconds
Started Mar 10 01:14:04 PM PDT 24
Finished Mar 10 01:17:55 PM PDT 24
Peak memory 183400 kb
Host smart-e6224886-fb40-48bc-9736-92a158ef85c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593034785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.593034785
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.1603843995
Short name T206
Test name
Test status
Simulation time 1209917810453 ps
CPU time 363.26 seconds
Started Mar 10 01:13:59 PM PDT 24
Finished Mar 10 01:20:03 PM PDT 24
Peak memory 191428 kb
Host smart-9c5da686-bfe2-421d-aca4-1233b36fafaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603843995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1603843995
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.676854464
Short name T187
Test name
Test status
Simulation time 219364488381 ps
CPU time 98.51 seconds
Started Mar 10 01:14:04 PM PDT 24
Finished Mar 10 01:15:43 PM PDT 24
Peak memory 195128 kb
Host smart-58bb95c2-fd30-451c-84d4-03d11dd65795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676854464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.676854464
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.265044951
Short name T340
Test name
Test status
Simulation time 367443102419 ps
CPU time 411.86 seconds
Started Mar 10 01:14:05 PM PDT 24
Finished Mar 10 01:20:57 PM PDT 24
Peak memory 183384 kb
Host smart-01074d82-0fcc-4283-8e3f-99d89fb67c58
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265044951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.rv_timer_cfg_update_on_fly.265044951
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.2001842964
Short name T56
Test name
Test status
Simulation time 855504223699 ps
CPU time 260.22 seconds
Started Mar 10 01:14:01 PM PDT 24
Finished Mar 10 01:18:21 PM PDT 24
Peak memory 183332 kb
Host smart-1631ced6-1939-4a3d-86a0-ea7f829bde91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001842964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2001842964
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.4185551831
Short name T282
Test name
Test status
Simulation time 287312389601 ps
CPU time 179.06 seconds
Started Mar 10 01:14:04 PM PDT 24
Finished Mar 10 01:17:04 PM PDT 24
Peak memory 191580 kb
Host smart-18271ff0-2abb-4d80-9684-7f24d0c5f0d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185551831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.4185551831
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.2370299999
Short name T454
Test name
Test status
Simulation time 34292223738 ps
CPU time 47.34 seconds
Started Mar 10 01:14:04 PM PDT 24
Finished Mar 10 01:14:52 PM PDT 24
Peak memory 191536 kb
Host smart-55db5025-d58e-4216-85f6-2c7644b9e812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370299999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2370299999
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2888966911
Short name T183
Test name
Test status
Simulation time 140001975734 ps
CPU time 256.39 seconds
Started Mar 10 01:14:01 PM PDT 24
Finished Mar 10 01:18:17 PM PDT 24
Peak memory 183268 kb
Host smart-26653d2f-2020-4467-bbcd-e4665cb5f254
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888966911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2888966911
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3796644762
Short name T422
Test name
Test status
Simulation time 368099997456 ps
CPU time 89.43 seconds
Started Mar 10 01:14:04 PM PDT 24
Finished Mar 10 01:15:35 PM PDT 24
Peak memory 183380 kb
Host smart-65d2af80-0cd8-4494-8733-6efe0bb2a572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796644762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3796644762
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.2822866361
Short name T208
Test name
Test status
Simulation time 282726710244 ps
CPU time 305.58 seconds
Started Mar 10 01:14:04 PM PDT 24
Finished Mar 10 01:19:10 PM PDT 24
Peak memory 191484 kb
Host smart-673799c7-9464-4963-b7af-1dc972e29ab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822866361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2822866361
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1162484465
Short name T433
Test name
Test status
Simulation time 474787049 ps
CPU time 1.29 seconds
Started Mar 10 01:14:05 PM PDT 24
Finished Mar 10 01:14:07 PM PDT 24
Peak memory 183004 kb
Host smart-088ae5a0-3c8e-404b-b430-1023642dccd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162484465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1162484465
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.314629197
Short name T307
Test name
Test status
Simulation time 264438240008 ps
CPU time 200.23 seconds
Started Mar 10 01:14:07 PM PDT 24
Finished Mar 10 01:17:28 PM PDT 24
Peak memory 183396 kb
Host smart-104f7c63-bdc6-4c48-9586-7692a6c645f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314629197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
314629197
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3804834849
Short name T304
Test name
Test status
Simulation time 30933448016 ps
CPU time 21.16 seconds
Started Mar 10 01:14:06 PM PDT 24
Finished Mar 10 01:14:28 PM PDT 24
Peak memory 183404 kb
Host smart-6edb12df-bd1e-450a-99a4-ded46051d19b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804834849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3804834849
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2756491391
Short name T417
Test name
Test status
Simulation time 20447492202 ps
CPU time 32.47 seconds
Started Mar 10 01:14:06 PM PDT 24
Finished Mar 10 01:14:39 PM PDT 24
Peak memory 183312 kb
Host smart-c6f26573-ed58-40a2-9ff9-970f1eb759e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756491391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2756491391
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.4064694204
Short name T264
Test name
Test status
Simulation time 78506381379 ps
CPU time 1733.58 seconds
Started Mar 10 01:14:06 PM PDT 24
Finished Mar 10 01:43:00 PM PDT 24
Peak memory 191492 kb
Host smart-840044c3-4828-4404-bba2-a9fbe931eeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064694204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.4064694204
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.4167027814
Short name T429
Test name
Test status
Simulation time 90494979435 ps
CPU time 63.75 seconds
Started Mar 10 01:14:08 PM PDT 24
Finished Mar 10 01:15:12 PM PDT 24
Peak memory 194076 kb
Host smart-2c15ef30-6485-43b9-a67f-49c0c1fd660d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167027814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.4167027814
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1853988125
Short name T235
Test name
Test status
Simulation time 899729918291 ps
CPU time 526.34 seconds
Started Mar 10 01:14:08 PM PDT 24
Finished Mar 10 01:22:55 PM PDT 24
Peak memory 183332 kb
Host smart-04b0840a-9312-43ad-a2e8-eff6655fd079
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853988125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1853988125
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.2035892731
Short name T370
Test name
Test status
Simulation time 49396816825 ps
CPU time 39.75 seconds
Started Mar 10 01:14:05 PM PDT 24
Finished Mar 10 01:14:46 PM PDT 24
Peak memory 183336 kb
Host smart-dd7939e1-6f55-47aa-b93a-1ec47736b082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035892731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2035892731
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.3886036444
Short name T259
Test name
Test status
Simulation time 198465574566 ps
CPU time 254.7 seconds
Started Mar 10 01:14:06 PM PDT 24
Finished Mar 10 01:18:21 PM PDT 24
Peak memory 191576 kb
Host smart-9a825d6c-fcd9-4f4d-8439-ba511d166076
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886036444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3886036444
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2834887012
Short name T334
Test name
Test status
Simulation time 18375120311 ps
CPU time 144.72 seconds
Started Mar 10 01:14:08 PM PDT 24
Finished Mar 10 01:16:33 PM PDT 24
Peak memory 183300 kb
Host smart-6ff123e0-7cff-421b-b624-8728acf792d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834887012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2834887012
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.86301779
Short name T173
Test name
Test status
Simulation time 1030981664395 ps
CPU time 594.19 seconds
Started Mar 10 01:14:10 PM PDT 24
Finished Mar 10 01:24:05 PM PDT 24
Peak memory 183288 kb
Host smart-f7b8e9a9-fa4f-42d1-9514-77e9eb31528e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86301779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.rv_timer_cfg_update_on_fly.86301779
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2156758429
Short name T6
Test name
Test status
Simulation time 483253229691 ps
CPU time 169.1 seconds
Started Mar 10 01:14:09 PM PDT 24
Finished Mar 10 01:16:59 PM PDT 24
Peak memory 183312 kb
Host smart-28391fc7-7814-4dec-bf7f-99a70a59f114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156758429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2156758429
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.3883437115
Short name T432
Test name
Test status
Simulation time 289182642938 ps
CPU time 175.17 seconds
Started Mar 10 01:14:12 PM PDT 24
Finished Mar 10 01:17:07 PM PDT 24
Peak memory 191476 kb
Host smart-c37b6025-114f-4d71-8ac9-94e74bcbc47b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883437115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3883437115
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.1848694447
Short name T296
Test name
Test status
Simulation time 62282104884 ps
CPU time 339.8 seconds
Started Mar 10 01:14:11 PM PDT 24
Finished Mar 10 01:19:51 PM PDT 24
Peak memory 183392 kb
Host smart-9c9776cb-c452-403f-afa1-6a4d2ca8a1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848694447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1848694447
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.574810985
Short name T403
Test name
Test status
Simulation time 21366531770 ps
CPU time 196.7 seconds
Started Mar 10 01:14:17 PM PDT 24
Finished Mar 10 01:17:34 PM PDT 24
Peak memory 183324 kb
Host smart-6fbc1ddd-ba8f-4566-ab53-80c20bbf3c0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574810985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
574810985
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3915087040
Short name T452
Test name
Test status
Simulation time 899630679879 ps
CPU time 506.09 seconds
Started Mar 10 01:14:21 PM PDT 24
Finished Mar 10 01:22:48 PM PDT 24
Peak memory 183420 kb
Host smart-ae922816-fc1a-47bb-ba3f-8383648a4209
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915087040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3915087040
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.746685853
Short name T398
Test name
Test status
Simulation time 124336728631 ps
CPU time 192.73 seconds
Started Mar 10 01:14:21 PM PDT 24
Finished Mar 10 01:17:34 PM PDT 24
Peak memory 183284 kb
Host smart-615c6aa1-a7ae-4d39-a869-c572fe1e165c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746685853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.746685853
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.3147095684
Short name T195
Test name
Test status
Simulation time 226921352485 ps
CPU time 159.27 seconds
Started Mar 10 01:14:17 PM PDT 24
Finished Mar 10 01:16:56 PM PDT 24
Peak memory 191512 kb
Host smart-7d111c52-1cfb-4e08-8739-5f8ddec8a45e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147095684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3147095684
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3239220040
Short name T401
Test name
Test status
Simulation time 268377339 ps
CPU time 0.68 seconds
Started Mar 10 01:14:21 PM PDT 24
Finished Mar 10 01:14:22 PM PDT 24
Peak memory 183020 kb
Host smart-9d5f55d3-7228-412f-a92a-700d9b0626ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239220040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3239220040
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.88532625
Short name T346
Test name
Test status
Simulation time 746467023119 ps
CPU time 1224.86 seconds
Started Mar 10 01:14:21 PM PDT 24
Finished Mar 10 01:34:46 PM PDT 24
Peak memory 191592 kb
Host smart-74eb2fa6-7d05-494d-abe0-472815e99889
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88532625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.88532625
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2157046677
Short name T180
Test name
Test status
Simulation time 987733703567 ps
CPU time 962.37 seconds
Started Mar 10 01:14:21 PM PDT 24
Finished Mar 10 01:30:23 PM PDT 24
Peak memory 183236 kb
Host smart-734d3567-9f73-424a-8c1d-624d451f8e77
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157046677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2157046677
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3557197878
Short name T435
Test name
Test status
Simulation time 211180378043 ps
CPU time 326.19 seconds
Started Mar 10 01:14:21 PM PDT 24
Finished Mar 10 01:19:48 PM PDT 24
Peak memory 183340 kb
Host smart-0be8fa99-5fcd-4940-886c-f899a72474e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557197878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3557197878
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.1856142612
Short name T110
Test name
Test status
Simulation time 118107020430 ps
CPU time 239.08 seconds
Started Mar 10 01:14:21 PM PDT 24
Finished Mar 10 01:18:21 PM PDT 24
Peak memory 191556 kb
Host smart-3496432d-2467-4c5e-8506-301465cfedaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856142612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1856142612
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3819452162
Short name T41
Test name
Test status
Simulation time 584446524562 ps
CPU time 336.41 seconds
Started Mar 10 01:13:24 PM PDT 24
Finished Mar 10 01:19:01 PM PDT 24
Peak memory 183312 kb
Host smart-a69d2f64-cf70-42c6-a0cc-87e3a65147e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819452162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3819452162
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.4050411617
Short name T396
Test name
Test status
Simulation time 88977975966 ps
CPU time 125.69 seconds
Started Mar 10 01:13:22 PM PDT 24
Finished Mar 10 01:15:28 PM PDT 24
Peak memory 183396 kb
Host smart-a6f4130d-6374-4af7-b5c0-c3b70e924c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050411617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.4050411617
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.1409420208
Short name T281
Test name
Test status
Simulation time 36610365349 ps
CPU time 599.56 seconds
Started Mar 10 01:13:11 PM PDT 24
Finished Mar 10 01:23:11 PM PDT 24
Peak memory 183220 kb
Host smart-e01c1cdb-74e8-436b-a975-241f2d6e399f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409420208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1409420208
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.354185664
Short name T355
Test name
Test status
Simulation time 104482648349 ps
CPU time 94.58 seconds
Started Mar 10 01:13:16 PM PDT 24
Finished Mar 10 01:14:51 PM PDT 24
Peak memory 191560 kb
Host smart-0cec879b-2de8-4af2-ad0e-e9068d135cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354185664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.354185664
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1308400011
Short name T274
Test name
Test status
Simulation time 2619000575701 ps
CPU time 3218.4 seconds
Started Mar 10 01:13:28 PM PDT 24
Finished Mar 10 02:07:06 PM PDT 24
Peak memory 191532 kb
Host smart-b97cff90-b20b-43de-8418-24b0cf86ec75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308400011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1308400011
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.3455173381
Short name T123
Test name
Test status
Simulation time 282292142029 ps
CPU time 476.98 seconds
Started Mar 10 01:14:32 PM PDT 24
Finished Mar 10 01:22:29 PM PDT 24
Peak memory 191476 kb
Host smart-936a29ef-65b3-4e85-9b1b-c3422ff49338
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455173381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3455173381
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.1429841147
Short name T71
Test name
Test status
Simulation time 334877322433 ps
CPU time 502.67 seconds
Started Mar 10 01:14:29 PM PDT 24
Finished Mar 10 01:22:52 PM PDT 24
Peak memory 191540 kb
Host smart-8c64501d-f245-4aba-9b62-f823ada170ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429841147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1429841147
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1162121891
Short name T248
Test name
Test status
Simulation time 1018549812023 ps
CPU time 471.41 seconds
Started Mar 10 01:14:27 PM PDT 24
Finished Mar 10 01:22:20 PM PDT 24
Peak memory 191616 kb
Host smart-a4f578aa-487b-423b-b814-6c57840f6d52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162121891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1162121891
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.4219880493
Short name T174
Test name
Test status
Simulation time 34138388107 ps
CPU time 56.98 seconds
Started Mar 10 01:14:25 PM PDT 24
Finished Mar 10 01:15:22 PM PDT 24
Peak memory 191580 kb
Host smart-ef76973f-79c6-4fa4-80d8-c0bed2cc0fc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219880493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.4219880493
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.4152160996
Short name T285
Test name
Test status
Simulation time 277867727751 ps
CPU time 403.93 seconds
Started Mar 10 01:14:27 PM PDT 24
Finished Mar 10 01:21:11 PM PDT 24
Peak memory 191536 kb
Host smart-ed1745cc-a73e-45d9-84c6-902a6b1136a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152160996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.4152160996
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.1743541378
Short name T436
Test name
Test status
Simulation time 139465394264 ps
CPU time 43.22 seconds
Started Mar 10 01:14:27 PM PDT 24
Finished Mar 10 01:15:11 PM PDT 24
Peak memory 183404 kb
Host smart-3c084837-f91a-431a-8b48-5e36e61f27ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743541378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.1743541378
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1306973504
Short name T223
Test name
Test status
Simulation time 235584794717 ps
CPU time 645.29 seconds
Started Mar 10 01:14:27 PM PDT 24
Finished Mar 10 01:25:13 PM PDT 24
Peak memory 194868 kb
Host smart-cdfef4ab-c801-438d-9937-f9af8f128cdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306973504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1306973504
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3211865753
Short name T122
Test name
Test status
Simulation time 123788236123 ps
CPU time 328.37 seconds
Started Mar 10 01:14:31 PM PDT 24
Finished Mar 10 01:20:00 PM PDT 24
Peak memory 191516 kb
Host smart-2e66dfdd-aa60-484f-8f47-b5fb56774e37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211865753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3211865753
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.3425767584
Short name T339
Test name
Test status
Simulation time 54193546849 ps
CPU time 25.13 seconds
Started Mar 10 01:14:31 PM PDT 24
Finished Mar 10 01:14:57 PM PDT 24
Peak memory 183420 kb
Host smart-fe836779-596c-41a3-a024-89ef271d272b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425767584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3425767584
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1148609803
Short name T395
Test name
Test status
Simulation time 610374343755 ps
CPU time 302.5 seconds
Started Mar 10 01:13:18 PM PDT 24
Finished Mar 10 01:18:21 PM PDT 24
Peak memory 183272 kb
Host smart-5da3ef07-c67d-47d4-af95-5c4574ae2db2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148609803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1148609803
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.2684143211
Short name T424
Test name
Test status
Simulation time 233868228438 ps
CPU time 71.36 seconds
Started Mar 10 01:13:19 PM PDT 24
Finished Mar 10 01:14:30 PM PDT 24
Peak memory 183312 kb
Host smart-a399619d-dc3f-4a87-a144-c2aa392d9c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684143211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2684143211
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.1475029482
Short name T257
Test name
Test status
Simulation time 153891931976 ps
CPU time 658.46 seconds
Started Mar 10 01:13:24 PM PDT 24
Finished Mar 10 01:24:22 PM PDT 24
Peak memory 191512 kb
Host smart-a0a57738-4fd0-429b-ba9c-186f5c5ae93c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475029482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1475029482
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.4063102275
Short name T420
Test name
Test status
Simulation time 266392616663 ps
CPU time 117.71 seconds
Started Mar 10 01:13:24 PM PDT 24
Finished Mar 10 01:15:21 PM PDT 24
Peak memory 191556 kb
Host smart-61d8be01-49be-4a24-910f-99e8f5c4ed39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063102275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.4063102275
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1420529799
Short name T246
Test name
Test status
Simulation time 575422740259 ps
CPU time 1330.1 seconds
Started Mar 10 01:13:27 PM PDT 24
Finished Mar 10 01:35:38 PM PDT 24
Peak memory 195180 kb
Host smart-95b08dd3-ca62-467d-9c83-8733dc5eec2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420529799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1420529799
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.242692827
Short name T12
Test name
Test status
Simulation time 88661545193 ps
CPU time 415.67 seconds
Started Mar 10 01:13:14 PM PDT 24
Finished Mar 10 01:20:10 PM PDT 24
Peak memory 206192 kb
Host smart-8e8bafd0-6b84-44ef-9c43-c596656a175f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242692827 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.242692827
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.366924068
Short name T444
Test name
Test status
Simulation time 175611355234 ps
CPU time 960.09 seconds
Started Mar 10 01:14:32 PM PDT 24
Finished Mar 10 01:30:33 PM PDT 24
Peak memory 194440 kb
Host smart-ab52794a-0bee-4ce2-8d74-2257602e55a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366924068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.366924068
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.1928893669
Short name T131
Test name
Test status
Simulation time 1055370293780 ps
CPU time 597.28 seconds
Started Mar 10 01:14:30 PM PDT 24
Finished Mar 10 01:24:28 PM PDT 24
Peak memory 191540 kb
Host smart-c99ef60a-9223-4152-b84c-edc5628433c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928893669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1928893669
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2488182496
Short name T220
Test name
Test status
Simulation time 99828323290 ps
CPU time 142.06 seconds
Started Mar 10 01:14:37 PM PDT 24
Finished Mar 10 01:17:00 PM PDT 24
Peak memory 191512 kb
Host smart-328cea8b-8a10-40fe-9b48-66fafd660ccd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488182496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2488182496
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.3000883545
Short name T176
Test name
Test status
Simulation time 146459892569 ps
CPU time 116.04 seconds
Started Mar 10 01:14:38 PM PDT 24
Finished Mar 10 01:16:34 PM PDT 24
Peak memory 191596 kb
Host smart-709eaa54-3102-4359-84f3-578d3ff76547
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000883545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3000883545
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.4074681462
Short name T315
Test name
Test status
Simulation time 40263041093 ps
CPU time 63.73 seconds
Started Mar 10 01:14:37 PM PDT 24
Finished Mar 10 01:15:42 PM PDT 24
Peak memory 183388 kb
Host smart-ff30f4f4-e794-4f92-887b-e88f56cbc23d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074681462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.4074681462
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.926626840
Short name T391
Test name
Test status
Simulation time 176674037 ps
CPU time 6.72 seconds
Started Mar 10 01:14:38 PM PDT 24
Finished Mar 10 01:14:46 PM PDT 24
Peak memory 183276 kb
Host smart-312c13d0-fdb5-4304-aea1-4310b6a76582
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926626840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.926626840
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.2574641436
Short name T146
Test name
Test status
Simulation time 533884797679 ps
CPU time 308.35 seconds
Started Mar 10 01:14:36 PM PDT 24
Finished Mar 10 01:19:45 PM PDT 24
Peak memory 191592 kb
Host smart-b200d181-d2a7-41c0-a393-189559c72460
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574641436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2574641436
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.206880789
Short name T266
Test name
Test status
Simulation time 357045014479 ps
CPU time 331.8 seconds
Started Mar 10 01:13:24 PM PDT 24
Finished Mar 10 01:18:56 PM PDT 24
Peak memory 183380 kb
Host smart-15a1bd64-ea93-4095-8d4f-d4c2a8973104
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206880789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.rv_timer_cfg_update_on_fly.206880789
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1441106250
Short name T8
Test name
Test status
Simulation time 139530489760 ps
CPU time 186.36 seconds
Started Mar 10 01:13:24 PM PDT 24
Finished Mar 10 01:16:31 PM PDT 24
Peak memory 183300 kb
Host smart-1614c223-a85c-49d7-ad1d-d0e0508e15af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441106250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1441106250
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.1849856499
Short name T276
Test name
Test status
Simulation time 61911932770 ps
CPU time 459.18 seconds
Started Mar 10 01:13:25 PM PDT 24
Finished Mar 10 01:21:04 PM PDT 24
Peak memory 191500 kb
Host smart-a51f5bf3-35ce-44eb-9734-3e39ddcf3b3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849856499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1849856499
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.607482685
Short name T136
Test name
Test status
Simulation time 574217732552 ps
CPU time 1438.1 seconds
Started Mar 10 01:13:25 PM PDT 24
Finished Mar 10 01:37:23 PM PDT 24
Peak memory 191468 kb
Host smart-894a37ca-bf94-4e64-9b9b-7f1084ce9757
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607482685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.607482685
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/71.rv_timer_random.1724677438
Short name T277
Test name
Test status
Simulation time 94589449353 ps
CPU time 42.87 seconds
Started Mar 10 01:14:49 PM PDT 24
Finished Mar 10 01:15:32 PM PDT 24
Peak memory 191484 kb
Host smart-85e38304-bc32-4273-8339-36a0813b403e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724677438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1724677438
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.786705886
Short name T201
Test name
Test status
Simulation time 487208996118 ps
CPU time 3559.92 seconds
Started Mar 10 01:14:41 PM PDT 24
Finished Mar 10 02:14:02 PM PDT 24
Peak memory 191548 kb
Host smart-51d7a72b-13d4-40b5-9e8b-96442cfdeaea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786705886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.786705886
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3512082178
Short name T415
Test name
Test status
Simulation time 182987265428 ps
CPU time 1640.25 seconds
Started Mar 10 01:14:42 PM PDT 24
Finished Mar 10 01:42:03 PM PDT 24
Peak memory 191580 kb
Host smart-c341ce37-1a84-4a01-ae6f-94b4189349c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512082178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3512082178
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.4261031003
Short name T135
Test name
Test status
Simulation time 264419946173 ps
CPU time 228.54 seconds
Started Mar 10 01:14:40 PM PDT 24
Finished Mar 10 01:18:30 PM PDT 24
Peak memory 191528 kb
Host smart-d02cf1ed-fa65-469a-bdc3-74b5cf08a22f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261031003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.4261031003
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.4264586827
Short name T198
Test name
Test status
Simulation time 206324154416 ps
CPU time 67.43 seconds
Started Mar 10 01:14:40 PM PDT 24
Finished Mar 10 01:15:48 PM PDT 24
Peak memory 183336 kb
Host smart-79565963-ce77-451a-bc56-708a05404021
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264586827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.4264586827
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.3609541251
Short name T408
Test name
Test status
Simulation time 210414639592 ps
CPU time 372.96 seconds
Started Mar 10 01:14:46 PM PDT 24
Finished Mar 10 01:20:59 PM PDT 24
Peak memory 183276 kb
Host smart-16f04fee-d4dd-419e-ba5c-9c6ef47ea19f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609541251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3609541251
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1387113687
Short name T215
Test name
Test status
Simulation time 134880207790 ps
CPU time 218.46 seconds
Started Mar 10 01:13:26 PM PDT 24
Finished Mar 10 01:17:04 PM PDT 24
Peak memory 183300 kb
Host smart-2cc20f87-e41a-4a6b-b712-a912aa27af34
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387113687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1387113687
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.562696605
Short name T430
Test name
Test status
Simulation time 891757214776 ps
CPU time 271.28 seconds
Started Mar 10 01:13:16 PM PDT 24
Finished Mar 10 01:17:48 PM PDT 24
Peak memory 183312 kb
Host smart-b2c1cbdd-641c-47f3-8afe-0c6e911cead1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562696605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.562696605
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.1616589596
Short name T207
Test name
Test status
Simulation time 37775649539 ps
CPU time 69.86 seconds
Started Mar 10 01:13:15 PM PDT 24
Finished Mar 10 01:14:26 PM PDT 24
Peak memory 183284 kb
Host smart-bc4e733f-92bc-44dd-acf5-3220886b50ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616589596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1616589596
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.422740454
Short name T42
Test name
Test status
Simulation time 196934814778 ps
CPU time 134.86 seconds
Started Mar 10 01:13:29 PM PDT 24
Finished Mar 10 01:15:44 PM PDT 24
Peak memory 183332 kb
Host smart-7989ad87-1f4c-4f6d-bbdc-b5b313d46709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422740454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.422740454
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2029404336
Short name T405
Test name
Test status
Simulation time 42177207893 ps
CPU time 69.12 seconds
Started Mar 10 01:13:28 PM PDT 24
Finished Mar 10 01:14:37 PM PDT 24
Peak memory 183144 kb
Host smart-e04dc850-79fb-4b0e-ae3f-28a093e65add
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029404336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2029404336
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.2083473971
Short name T305
Test name
Test status
Simulation time 189718622065 ps
CPU time 140.63 seconds
Started Mar 10 01:14:45 PM PDT 24
Finished Mar 10 01:17:06 PM PDT 24
Peak memory 191452 kb
Host smart-c1eca36c-0673-4f37-aa71-4206488587e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083473971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2083473971
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.871292342
Short name T238
Test name
Test status
Simulation time 458709367153 ps
CPU time 285.56 seconds
Started Mar 10 01:14:46 PM PDT 24
Finished Mar 10 01:19:32 PM PDT 24
Peak memory 191564 kb
Host smart-acfe3387-5361-491d-bc36-761261f0f4ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871292342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.871292342
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.3187879691
Short name T255
Test name
Test status
Simulation time 524731513384 ps
CPU time 292.68 seconds
Started Mar 10 01:14:45 PM PDT 24
Finished Mar 10 01:19:38 PM PDT 24
Peak memory 191608 kb
Host smart-eacc8913-0baa-4db2-a9f2-a3b6ca3cf8bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187879691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3187879691
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.4271009881
Short name T337
Test name
Test status
Simulation time 115449115618 ps
CPU time 111.48 seconds
Started Mar 10 01:14:52 PM PDT 24
Finished Mar 10 01:16:43 PM PDT 24
Peak memory 191476 kb
Host smart-1b5cbcbf-2068-4029-a474-110a75c5d44f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271009881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.4271009881
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.3899316634
Short name T242
Test name
Test status
Simulation time 65076191054 ps
CPU time 122.85 seconds
Started Mar 10 01:14:52 PM PDT 24
Finished Mar 10 01:16:55 PM PDT 24
Peak memory 194048 kb
Host smart-376127c1-6d22-46fd-8df8-aa5af4d57adc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899316634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3899316634
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2662890197
Short name T21
Test name
Test status
Simulation time 164350624840 ps
CPU time 1191.89 seconds
Started Mar 10 01:14:51 PM PDT 24
Finished Mar 10 01:34:44 PM PDT 24
Peak memory 191492 kb
Host smart-ce228aac-7664-4453-9cd6-c0f7bc3ef189
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662890197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2662890197
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.2138781798
Short name T425
Test name
Test status
Simulation time 72592925918 ps
CPU time 374.37 seconds
Started Mar 10 01:14:50 PM PDT 24
Finished Mar 10 01:21:05 PM PDT 24
Peak memory 183376 kb
Host smart-40dc955b-da8a-4d77-94ef-c9a3b872b3f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138781798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2138781798
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.143808653
Short name T72
Test name
Test status
Simulation time 1157978143090 ps
CPU time 649.59 seconds
Started Mar 10 01:14:52 PM PDT 24
Finished Mar 10 01:25:42 PM PDT 24
Peak memory 191584 kb
Host smart-4ca15ff0-05a4-44f4-8f44-5e90ac9a8304
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143808653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.143808653
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.3487040240
Short name T20
Test name
Test status
Simulation time 6037527965194 ps
CPU time 1674.24 seconds
Started Mar 10 01:13:28 PM PDT 24
Finished Mar 10 01:41:22 PM PDT 24
Peak memory 183320 kb
Host smart-895e133e-436e-462c-bf6c-c5283b204b3a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487040240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.3487040240
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.2799339334
Short name T367
Test name
Test status
Simulation time 74591783441 ps
CPU time 104.76 seconds
Started Mar 10 01:13:26 PM PDT 24
Finished Mar 10 01:15:11 PM PDT 24
Peak memory 183336 kb
Host smart-019a5927-80c3-4033-b33f-7cf5f6701d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799339334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2799339334
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.601255755
Short name T347
Test name
Test status
Simulation time 204419781009 ps
CPU time 72.47 seconds
Started Mar 10 01:13:27 PM PDT 24
Finished Mar 10 01:14:40 PM PDT 24
Peak memory 194856 kb
Host smart-12d57606-d2f8-4de1-87f0-3f4ff04bc1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601255755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.601255755
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3200052886
Short name T167
Test name
Test status
Simulation time 749617285692 ps
CPU time 598.93 seconds
Started Mar 10 01:13:28 PM PDT 24
Finished Mar 10 01:23:27 PM PDT 24
Peak memory 195868 kb
Host smart-799006fb-a8e1-4b2c-84aa-9351e10b1b4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200052886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3200052886
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.2073360902
Short name T35
Test name
Test status
Simulation time 239611150428 ps
CPU time 813.48 seconds
Started Mar 10 01:13:26 PM PDT 24
Finished Mar 10 01:26:59 PM PDT 24
Peak memory 213944 kb
Host smart-be014bd2-f3eb-4e2d-88bd-946a77218191
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073360902 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.2073360902
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.2811822548
Short name T240
Test name
Test status
Simulation time 102841790773 ps
CPU time 1467.37 seconds
Started Mar 10 01:14:57 PM PDT 24
Finished Mar 10 01:39:25 PM PDT 24
Peak memory 191516 kb
Host smart-e50f40cc-227e-4e2b-a712-a3898b37ab1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811822548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2811822548
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3018069439
Short name T256
Test name
Test status
Simulation time 169966618740 ps
CPU time 136.5 seconds
Started Mar 10 01:14:58 PM PDT 24
Finished Mar 10 01:17:14 PM PDT 24
Peak memory 191600 kb
Host smart-8905e988-c318-492d-b555-65a35a65bf52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018069439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3018069439
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3137785512
Short name T127
Test name
Test status
Simulation time 99762016205 ps
CPU time 135.66 seconds
Started Mar 10 01:14:58 PM PDT 24
Finished Mar 10 01:17:14 PM PDT 24
Peak memory 191512 kb
Host smart-4870a602-d227-453f-b2d4-9c5349ce9229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137785512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3137785512
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.4102119504
Short name T117
Test name
Test status
Simulation time 119745705578 ps
CPU time 157.83 seconds
Started Mar 10 01:14:57 PM PDT 24
Finished Mar 10 01:17:35 PM PDT 24
Peak memory 191556 kb
Host smart-593dde20-57aa-4381-992a-09180080e05c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102119504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.4102119504
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1161339302
Short name T293
Test name
Test status
Simulation time 966747828389 ps
CPU time 561.98 seconds
Started Mar 10 01:14:56 PM PDT 24
Finished Mar 10 01:24:19 PM PDT 24
Peak memory 191564 kb
Host smart-e18dec2e-a8f3-45bb-9311-2d94fbeab29a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161339302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1161339302
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3959515357
Short name T162
Test name
Test status
Simulation time 152484387830 ps
CPU time 1764.81 seconds
Started Mar 10 01:15:00 PM PDT 24
Finished Mar 10 01:44:25 PM PDT 24
Peak memory 194748 kb
Host smart-30681e4b-f841-40bd-8778-4da24720568d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959515357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3959515357
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3909014882
Short name T313
Test name
Test status
Simulation time 106463502082 ps
CPU time 662.02 seconds
Started Mar 10 01:14:58 PM PDT 24
Finished Mar 10 01:26:01 PM PDT 24
Peak memory 191428 kb
Host smart-22db7a18-0fb6-425e-9db6-0c38f9bcaeb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909014882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3909014882
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.754597492
Short name T151
Test name
Test status
Simulation time 521288260677 ps
CPU time 206.87 seconds
Started Mar 10 01:14:58 PM PDT 24
Finished Mar 10 01:18:25 PM PDT 24
Peak memory 191608 kb
Host smart-432b5a50-2a52-4d0c-a3ed-f6004d165f3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754597492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.754597492
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.720096943
Short name T364
Test name
Test status
Simulation time 1661357620125 ps
CPU time 324.73 seconds
Started Mar 10 01:14:58 PM PDT 24
Finished Mar 10 01:20:23 PM PDT 24
Peak memory 193644 kb
Host smart-a512edda-fdcb-48d4-959d-fe037d18cb54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720096943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.720096943
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1555393841
Short name T440
Test name
Test status
Simulation time 326022448935 ps
CPU time 178.47 seconds
Started Mar 10 01:15:04 PM PDT 24
Finished Mar 10 01:18:03 PM PDT 24
Peak memory 191600 kb
Host smart-cd4d6775-733e-4596-b34c-03b043fbc38c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555393841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1555393841
Directory /workspace/99.rv_timer_random/latest
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