Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 578
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T512 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.539042257 Mar 12 12:49:25 PM PDT 24 Mar 12 12:49:30 PM PDT 24 226246471 ps
T513 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1410444061 Mar 12 12:49:19 PM PDT 24 Mar 12 12:49:20 PM PDT 24 20227974 ps
T514 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1566050770 Mar 12 12:49:20 PM PDT 24 Mar 12 12:49:21 PM PDT 24 31814357 ps
T515 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.4163502728 Mar 12 12:49:20 PM PDT 24 Mar 12 12:49:20 PM PDT 24 13231707 ps
T516 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.392758378 Mar 12 12:49:25 PM PDT 24 Mar 12 12:49:26 PM PDT 24 12026420 ps
T94 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.4293817148 Mar 12 12:49:17 PM PDT 24 Mar 12 12:49:19 PM PDT 24 179729608 ps
T517 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2954644668 Mar 12 12:49:13 PM PDT 24 Mar 12 12:49:14 PM PDT 24 86112961 ps
T518 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.208464139 Mar 12 12:49:25 PM PDT 24 Mar 12 12:49:28 PM PDT 24 25027843 ps
T519 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1669850150 Mar 12 12:49:21 PM PDT 24 Mar 12 12:49:22 PM PDT 24 102104123 ps
T80 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1087691316 Mar 12 12:49:15 PM PDT 24 Mar 12 12:49:16 PM PDT 24 12575944 ps
T520 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.557825796 Mar 12 12:49:17 PM PDT 24 Mar 12 12:49:18 PM PDT 24 53873136 ps
T521 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3306167130 Mar 12 12:49:13 PM PDT 24 Mar 12 12:49:15 PM PDT 24 77869017 ps
T522 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2125029630 Mar 12 12:49:19 PM PDT 24 Mar 12 12:49:21 PM PDT 24 84715809 ps
T523 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.370634053 Mar 12 12:49:18 PM PDT 24 Mar 12 12:49:19 PM PDT 24 32038609 ps
T524 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2058706875 Mar 12 12:49:09 PM PDT 24 Mar 12 12:49:10 PM PDT 24 15111755 ps
T525 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3917395484 Mar 12 12:49:16 PM PDT 24 Mar 12 12:49:18 PM PDT 24 12772412 ps
T526 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2457318509 Mar 12 12:49:04 PM PDT 24 Mar 12 12:49:05 PM PDT 24 47989872 ps
T527 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.4253998994 Mar 12 12:49:20 PM PDT 24 Mar 12 12:49:21 PM PDT 24 61802324 ps
T528 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3637957120 Mar 12 12:49:18 PM PDT 24 Mar 12 12:49:20 PM PDT 24 230485029 ps
T529 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2213220132 Mar 12 12:49:12 PM PDT 24 Mar 12 12:49:14 PM PDT 24 83991728 ps
T530 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.12494507 Mar 12 12:49:20 PM PDT 24 Mar 12 12:49:21 PM PDT 24 71016677 ps
T531 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1974078668 Mar 12 12:49:17 PM PDT 24 Mar 12 12:49:19 PM PDT 24 89553566 ps
T532 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2918257321 Mar 12 12:49:11 PM PDT 24 Mar 12 12:49:12 PM PDT 24 85215455 ps
T533 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2786411331 Mar 12 12:49:17 PM PDT 24 Mar 12 12:49:18 PM PDT 24 137749886 ps
T534 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.703547029 Mar 12 12:49:15 PM PDT 24 Mar 12 12:49:16 PM PDT 24 45225987 ps
T535 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1639571393 Mar 12 12:49:05 PM PDT 24 Mar 12 12:49:07 PM PDT 24 250284575 ps
T536 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.4212437238 Mar 12 12:49:15 PM PDT 24 Mar 12 12:49:16 PM PDT 24 24188882 ps
T537 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1605636276 Mar 12 12:49:02 PM PDT 24 Mar 12 12:49:02 PM PDT 24 59420805 ps
T81 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.22689291 Mar 12 12:49:10 PM PDT 24 Mar 12 12:49:12 PM PDT 24 27105704 ps
T93 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3429414511 Mar 12 12:49:17 PM PDT 24 Mar 12 12:49:18 PM PDT 24 306274097 ps
T538 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2279154034 Mar 12 12:49:05 PM PDT 24 Mar 12 12:49:06 PM PDT 24 137543066 ps
T539 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.324628868 Mar 12 12:49:25 PM PDT 24 Mar 12 12:49:27 PM PDT 24 17569690 ps
T540 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.4036779378 Mar 12 12:49:03 PM PDT 24 Mar 12 12:49:04 PM PDT 24 114412915 ps
T541 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3769031987 Mar 12 12:49:24 PM PDT 24 Mar 12 12:49:26 PM PDT 24 16683628 ps
T542 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1447272000 Mar 12 12:49:09 PM PDT 24 Mar 12 12:49:10 PM PDT 24 60973967 ps
T543 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.616784646 Mar 12 12:49:24 PM PDT 24 Mar 12 12:49:25 PM PDT 24 18686934 ps
T544 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2652054073 Mar 12 12:49:05 PM PDT 24 Mar 12 12:49:06 PM PDT 24 32372762 ps
T95 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.4293931100 Mar 12 12:49:25 PM PDT 24 Mar 12 12:49:27 PM PDT 24 924329026 ps
T545 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3328939243 Mar 12 12:49:22 PM PDT 24 Mar 12 12:49:23 PM PDT 24 31471996 ps
T546 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.265595313 Mar 12 12:49:13 PM PDT 24 Mar 12 12:49:14 PM PDT 24 22743702 ps
T82 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3366944087 Mar 12 12:49:20 PM PDT 24 Mar 12 12:49:20 PM PDT 24 25919058 ps
T547 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2758821887 Mar 12 12:49:17 PM PDT 24 Mar 12 12:49:18 PM PDT 24 15716286 ps
T83 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.191236188 Mar 12 12:49:14 PM PDT 24 Mar 12 12:49:15 PM PDT 24 49075444 ps
T548 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2053055598 Mar 12 12:49:14 PM PDT 24 Mar 12 12:49:15 PM PDT 24 14581967 ps
T96 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2118057087 Mar 12 12:49:14 PM PDT 24 Mar 12 12:49:16 PM PDT 24 92186494 ps
T549 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3393248662 Mar 12 12:49:19 PM PDT 24 Mar 12 12:49:21 PM PDT 24 83998134 ps
T550 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1606061102 Mar 12 12:49:12 PM PDT 24 Mar 12 12:49:13 PM PDT 24 34007113 ps
T86 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3520801383 Mar 12 12:49:20 PM PDT 24 Mar 12 12:49:21 PM PDT 24 31456386 ps
T551 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.61841704 Mar 12 12:49:15 PM PDT 24 Mar 12 12:49:16 PM PDT 24 101265434 ps
T552 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3476159630 Mar 12 12:49:20 PM PDT 24 Mar 12 12:49:20 PM PDT 24 14321444 ps
T553 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2453692237 Mar 12 12:49:19 PM PDT 24 Mar 12 12:49:21 PM PDT 24 67459054 ps
T554 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.721944454 Mar 12 12:49:09 PM PDT 24 Mar 12 12:49:10 PM PDT 24 48100156 ps
T555 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.228209056 Mar 12 12:49:11 PM PDT 24 Mar 12 12:49:12 PM PDT 24 48210591 ps
T556 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1507278966 Mar 12 12:49:26 PM PDT 24 Mar 12 12:49:29 PM PDT 24 25428390 ps
T557 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.380354501 Mar 12 12:49:21 PM PDT 24 Mar 12 12:49:22 PM PDT 24 24676384 ps
T84 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1595929966 Mar 12 12:49:00 PM PDT 24 Mar 12 12:49:01 PM PDT 24 13710516 ps
T558 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3464623098 Mar 12 12:49:11 PM PDT 24 Mar 12 12:49:13 PM PDT 24 28150997 ps
T559 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.948424675 Mar 12 12:49:16 PM PDT 24 Mar 12 12:49:17 PM PDT 24 28161137 ps
T560 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1686247510 Mar 12 12:49:21 PM PDT 24 Mar 12 12:49:23 PM PDT 24 29876259 ps
T561 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2824093712 Mar 12 12:49:18 PM PDT 24 Mar 12 12:49:19 PM PDT 24 33152554 ps
T562 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2096293399 Mar 12 12:49:04 PM PDT 24 Mar 12 12:49:05 PM PDT 24 12532185 ps
T563 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2301595753 Mar 12 12:49:10 PM PDT 24 Mar 12 12:49:11 PM PDT 24 319328756 ps
T564 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1060738717 Mar 12 12:49:08 PM PDT 24 Mar 12 12:49:09 PM PDT 24 38121648 ps
T565 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3696425495 Mar 12 12:49:17 PM PDT 24 Mar 12 12:49:17 PM PDT 24 13734186 ps
T566 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.325532514 Mar 12 12:49:14 PM PDT 24 Mar 12 12:49:15 PM PDT 24 20364939 ps
T567 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1643195882 Mar 12 12:49:08 PM PDT 24 Mar 12 12:49:10 PM PDT 24 64670881 ps
T568 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.535285914 Mar 12 12:49:18 PM PDT 24 Mar 12 12:49:19 PM PDT 24 40930686 ps
T85 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1111633685 Mar 12 12:49:13 PM PDT 24 Mar 12 12:49:13 PM PDT 24 52588130 ps
T569 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3349537515 Mar 12 12:49:13 PM PDT 24 Mar 12 12:49:13 PM PDT 24 42457098 ps
T570 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3969687962 Mar 12 12:49:20 PM PDT 24 Mar 12 12:49:21 PM PDT 24 16644498 ps
T571 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2985154775 Mar 12 12:49:26 PM PDT 24 Mar 12 12:49:28 PM PDT 24 24162767 ps
T572 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1747969190 Mar 12 12:49:10 PM PDT 24 Mar 12 12:49:12 PM PDT 24 20703964 ps
T573 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.4106675309 Mar 12 12:49:12 PM PDT 24 Mar 12 12:49:13 PM PDT 24 30304495 ps
T574 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1173797967 Mar 12 12:49:10 PM PDT 24 Mar 12 12:49:11 PM PDT 24 23943534 ps
T575 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4197095060 Mar 12 12:49:06 PM PDT 24 Mar 12 12:49:07 PM PDT 24 14981906 ps
T576 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2677131094 Mar 12 12:49:20 PM PDT 24 Mar 12 12:49:21 PM PDT 24 18742106 ps
T577 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3881469454 Mar 12 12:49:20 PM PDT 24 Mar 12 12:49:21 PM PDT 24 20218309 ps
T578 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.975611665 Mar 12 12:49:21 PM PDT 24 Mar 12 12:49:22 PM PDT 24 87892160 ps

Test location /workspace/coverage/default/195.rv_timer_random.1403277312
Short name T4
Test name
Test status
Simulation time 318144435034 ps
CPU time 428.29 seconds
Started Mar 12 12:32:09 PM PDT 24
Finished Mar 12 12:39:18 PM PDT 24
Peak memory 191584 kb
Host smart-971e2246-3b03-4cec-9c0b-b56bb50650f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403277312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1403277312
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.976372154
Short name T11
Test name
Test status
Simulation time 202213610674 ps
CPU time 536.06 seconds
Started Mar 12 12:31:33 PM PDT 24
Finished Mar 12 12:40:29 PM PDT 24
Peak memory 207516 kb
Host smart-51c17ffa-fb04-46d4-94c9-f7b6f080f1a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976372154 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.976372154
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.861280493
Short name T122
Test name
Test status
Simulation time 730566350766 ps
CPU time 1946.77 seconds
Started Mar 12 12:31:12 PM PDT 24
Finished Mar 12 01:03:39 PM PDT 24
Peak memory 191544 kb
Host smart-2825b110-e073-4722-8b8a-7c5d30a077b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861280493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.861280493
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.4155994642
Short name T100
Test name
Test status
Simulation time 3155491121572 ps
CPU time 3117.98 seconds
Started Mar 12 12:31:01 PM PDT 24
Finished Mar 12 01:22:59 PM PDT 24
Peak memory 191480 kb
Host smart-2af51677-24f3-403f-80e2-0fce3f5cf2c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155994642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
4155994642
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.27706156
Short name T28
Test name
Test status
Simulation time 464779538 ps
CPU time 1.1 seconds
Started Mar 12 12:49:06 PM PDT 24
Finished Mar 12 12:49:07 PM PDT 24
Peak memory 183596 kb
Host smart-cb497a32-364a-4cd0-905d-92c9305bacc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27706156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_intg
_err.27706156
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.242442764
Short name T166
Test name
Test status
Simulation time 806024170861 ps
CPU time 1771.41 seconds
Started Mar 12 12:31:41 PM PDT 24
Finished Mar 12 01:01:13 PM PDT 24
Peak memory 191512 kb
Host smart-b839ae4d-6e0b-4570-9dd6-17857d91b55c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242442764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
242442764
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1356286023
Short name T148
Test name
Test status
Simulation time 849302727781 ps
CPU time 5927.11 seconds
Started Mar 12 12:31:15 PM PDT 24
Finished Mar 12 02:10:03 PM PDT 24
Peak memory 191472 kb
Host smart-b77e9389-5edd-4bdd-9790-ae48b7d2b8dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356286023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1356286023
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_random.2259225271
Short name T3
Test name
Test status
Simulation time 416128438082 ps
CPU time 3563.68 seconds
Started Mar 12 12:31:44 PM PDT 24
Finished Mar 12 01:31:08 PM PDT 24
Peak memory 191544 kb
Host smart-37df14c3-9184-4942-95d5-0dc1b9fefdb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259225271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2259225271
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.563994828
Short name T157
Test name
Test status
Simulation time 3047475259224 ps
CPU time 1912.08 seconds
Started Mar 12 12:31:34 PM PDT 24
Finished Mar 12 01:03:26 PM PDT 24
Peak memory 196292 kb
Host smart-470a074d-911f-460c-86bb-1cc1ba22b214
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563994828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
563994828
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2894894204
Short name T149
Test name
Test status
Simulation time 484654954693 ps
CPU time 2645.38 seconds
Started Mar 12 12:31:35 PM PDT 24
Finished Mar 12 01:15:41 PM PDT 24
Peak memory 196316 kb
Host smart-529ff50a-1086-4f61-b164-d466142cc66b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894894204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2894894204
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1709669848
Short name T153
Test name
Test status
Simulation time 2088087003090 ps
CPU time 1824.7 seconds
Started Mar 12 12:31:29 PM PDT 24
Finished Mar 12 01:01:55 PM PDT 24
Peak memory 195484 kb
Host smart-e12e417b-9f9b-4b13-8a56-f961d892bae4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709669848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1709669848
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.4000104257
Short name T52
Test name
Test status
Simulation time 73886484 ps
CPU time 0.73 seconds
Started Mar 12 12:49:00 PM PDT 24
Finished Mar 12 12:49:01 PM PDT 24
Peak memory 192196 kb
Host smart-407f48cc-a9eb-4266-b46c-28e4f407ccd0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000104257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.4000104257
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.3413136936
Short name T114
Test name
Test status
Simulation time 362203029580 ps
CPU time 703.11 seconds
Started Mar 12 12:32:39 PM PDT 24
Finished Mar 12 12:44:22 PM PDT 24
Peak memory 191236 kb
Host smart-91937675-e2a5-4f7d-ba8e-bc1fbd491db5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413136936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.3413136936
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2360882063
Short name T18
Test name
Test status
Simulation time 64983466 ps
CPU time 0.83 seconds
Started Mar 12 12:31:12 PM PDT 24
Finished Mar 12 12:31:14 PM PDT 24
Peak memory 213412 kb
Host smart-80040eb2-4dc8-488b-a367-0c7e01cefc56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360882063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2360882063
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2622933112
Short name T221
Test name
Test status
Simulation time 596022670567 ps
CPU time 1501.85 seconds
Started Mar 12 12:31:33 PM PDT 24
Finished Mar 12 12:56:35 PM PDT 24
Peak memory 196180 kb
Host smart-8a9dedcd-6ef6-4b61-a8d5-6850ebb24bd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622933112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2622933112
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2660323982
Short name T160
Test name
Test status
Simulation time 1761009903130 ps
CPU time 1530.77 seconds
Started Mar 12 12:31:36 PM PDT 24
Finished Mar 12 12:57:07 PM PDT 24
Peak memory 195600 kb
Host smart-a473f0dc-b41c-41bf-9998-0b9348b50587
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660323982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2660323982
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1438744870
Short name T142
Test name
Test status
Simulation time 628429231011 ps
CPU time 1737.37 seconds
Started Mar 12 12:31:33 PM PDT 24
Finished Mar 12 01:00:31 PM PDT 24
Peak memory 191484 kb
Host smart-ab4e36d2-5582-469c-8261-c51ead860be9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438744870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1438744870
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/173.rv_timer_random.21507814
Short name T109
Test name
Test status
Simulation time 689435486192 ps
CPU time 1195.05 seconds
Started Mar 12 12:31:58 PM PDT 24
Finished Mar 12 12:51:54 PM PDT 24
Peak memory 191452 kb
Host smart-63e660b3-237f-43bf-902a-a7763ff30f50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21507814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.21507814
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2011760731
Short name T170
Test name
Test status
Simulation time 438081663593 ps
CPU time 1030.4 seconds
Started Mar 12 12:31:29 PM PDT 24
Finished Mar 12 12:48:40 PM PDT 24
Peak memory 191572 kb
Host smart-e50162c2-c76c-4a49-aacc-c245a799d4c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011760731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2011760731
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/65.rv_timer_random.3850501058
Short name T5
Test name
Test status
Simulation time 333749309874 ps
CPU time 273.14 seconds
Started Mar 12 12:31:38 PM PDT 24
Finished Mar 12 12:36:12 PM PDT 24
Peak memory 191520 kb
Host smart-96e65b0d-0bdd-47dd-81d1-dccbd1a0fa74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850501058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3850501058
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random.4058797227
Short name T123
Test name
Test status
Simulation time 305930814848 ps
CPU time 292.94 seconds
Started Mar 12 12:31:23 PM PDT 24
Finished Mar 12 12:36:16 PM PDT 24
Peak memory 191532 kb
Host smart-a6a98081-b675-4f55-9cdd-d9c658b8cb93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058797227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.4058797227
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.2454268472
Short name T244
Test name
Test status
Simulation time 171384680138 ps
CPU time 789.81 seconds
Started Mar 12 12:31:57 PM PDT 24
Finished Mar 12 12:45:07 PM PDT 24
Peak memory 191504 kb
Host smart-82ee9c48-e7aa-48d1-912c-4f34b6c43cf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454268472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.2454268472
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.1002101824
Short name T281
Test name
Test status
Simulation time 498483009865 ps
CPU time 285.86 seconds
Started Mar 12 12:32:00 PM PDT 24
Finished Mar 12 12:36:46 PM PDT 24
Peak memory 191528 kb
Host smart-dd8dbe2b-051a-4079-adae-e35963bc6350
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002101824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1002101824
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.14775336
Short name T61
Test name
Test status
Simulation time 468541441697 ps
CPU time 1183.56 seconds
Started Mar 12 12:31:32 PM PDT 24
Finished Mar 12 12:51:15 PM PDT 24
Peak memory 191476 kb
Host smart-2b374ca3-d068-4412-b3f2-66ce7c5275ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14775336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.14775336
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_random.1995262357
Short name T215
Test name
Test status
Simulation time 2712699078126 ps
CPU time 598.94 seconds
Started Mar 12 12:31:28 PM PDT 24
Finished Mar 12 12:41:27 PM PDT 24
Peak memory 191556 kb
Host smart-62a91b89-2722-45a2-a3d0-5a927ba57358
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995262357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1995262357
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2688315139
Short name T161
Test name
Test status
Simulation time 336378507965 ps
CPU time 1089.74 seconds
Started Mar 12 12:31:53 PM PDT 24
Finished Mar 12 12:50:03 PM PDT 24
Peak memory 193660 kb
Host smart-9c98a470-3398-45f6-bb61-3dd2808ec830
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688315139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2688315139
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.4228062267
Short name T132
Test name
Test status
Simulation time 228812266416 ps
CPU time 380.5 seconds
Started Mar 12 12:31:30 PM PDT 24
Finished Mar 12 12:37:51 PM PDT 24
Peak memory 183288 kb
Host smart-90ac52c2-62f6-4cf0-a0da-0f6cc703ffca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228062267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.4228062267
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3167227872
Short name T97
Test name
Test status
Simulation time 2587436963676 ps
CPU time 733.12 seconds
Started Mar 12 12:31:36 PM PDT 24
Finished Mar 12 12:43:49 PM PDT 24
Peak memory 183344 kb
Host smart-8dfbd4a9-4858-4bcf-a15f-942720e09f1c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167227872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3167227872
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/149.rv_timer_random.1402844387
Short name T322
Test name
Test status
Simulation time 675205900502 ps
CPU time 2790.03 seconds
Started Mar 12 12:32:02 PM PDT 24
Finished Mar 12 01:18:32 PM PDT 24
Peak memory 191512 kb
Host smart-9a38e6ca-6362-4ea6-b4c7-13ecce7bb71b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402844387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1402844387
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.2090499226
Short name T271
Test name
Test status
Simulation time 117392861955 ps
CPU time 438.92 seconds
Started Mar 12 12:31:25 PM PDT 24
Finished Mar 12 12:38:44 PM PDT 24
Peak memory 191444 kb
Host smart-95cb29bb-7711-44f3-9a25-7f836512f28f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090499226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2090499226
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.1103157986
Short name T184
Test name
Test status
Simulation time 238741422114 ps
CPU time 430.38 seconds
Started Mar 12 12:31:53 PM PDT 24
Finished Mar 12 12:39:03 PM PDT 24
Peak memory 191468 kb
Host smart-33246697-366c-4b6b-a8a8-4b06c5f0e92c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103157986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1103157986
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.4210505650
Short name T241
Test name
Test status
Simulation time 789385440634 ps
CPU time 256.62 seconds
Started Mar 12 12:31:19 PM PDT 24
Finished Mar 12 12:35:36 PM PDT 24
Peak memory 195232 kb
Host smart-c67d4f7b-fb3e-4cb9-a197-7e7919321772
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210505650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.4210505650
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/138.rv_timer_random.3253513801
Short name T113
Test name
Test status
Simulation time 587796359509 ps
CPU time 1675.24 seconds
Started Mar 12 12:31:58 PM PDT 24
Finished Mar 12 12:59:54 PM PDT 24
Peak memory 191524 kb
Host smart-31cface8-47a2-41fa-b9a2-50cac652e69c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253513801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3253513801
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.871285043
Short name T272
Test name
Test status
Simulation time 714735538730 ps
CPU time 444.8 seconds
Started Mar 12 12:31:58 PM PDT 24
Finished Mar 12 12:39:23 PM PDT 24
Peak memory 191456 kb
Host smart-4d95d125-feb6-40fb-a016-834df22b8a70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871285043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.871285043
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random.1086128605
Short name T25
Test name
Test status
Simulation time 165260865871 ps
CPU time 131.05 seconds
Started Mar 12 12:31:27 PM PDT 24
Finished Mar 12 12:33:38 PM PDT 24
Peak memory 191504 kb
Host smart-c20617bf-a031-4e33-8eb3-f9cee1d62a02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086128605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1086128605
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1776105468
Short name T189
Test name
Test status
Simulation time 168312304792 ps
CPU time 265.74 seconds
Started Mar 12 12:32:39 PM PDT 24
Finished Mar 12 12:37:05 PM PDT 24
Peak memory 183000 kb
Host smart-ca771810-fcd7-4a1d-a4c1-7eb836043fe5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776105468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1776105468
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_random.1201877454
Short name T430
Test name
Test status
Simulation time 325793050060 ps
CPU time 326.68 seconds
Started Mar 12 12:31:32 PM PDT 24
Finished Mar 12 12:36:58 PM PDT 24
Peak memory 191872 kb
Host smart-0b06061b-4b3b-4d26-b9c7-6b9c3cd38c7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201877454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1201877454
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1421580027
Short name T111
Test name
Test status
Simulation time 582241579841 ps
CPU time 877.74 seconds
Started Mar 12 12:31:54 PM PDT 24
Finished Mar 12 12:46:32 PM PDT 24
Peak memory 191500 kb
Host smart-326a1dbc-212a-42f8-951d-4db4ba4ea045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421580027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1421580027
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1666447851
Short name T255
Test name
Test status
Simulation time 81559619720 ps
CPU time 305.24 seconds
Started Mar 12 12:32:04 PM PDT 24
Finished Mar 12 12:37:10 PM PDT 24
Peak memory 191476 kb
Host smart-a654de55-f54f-43d5-9386-5e26deb04983
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666447851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1666447851
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.1685957591
Short name T58
Test name
Test status
Simulation time 306207428579 ps
CPU time 625.09 seconds
Started Mar 12 12:31:35 PM PDT 24
Finished Mar 12 12:42:00 PM PDT 24
Peak memory 191464 kb
Host smart-da01b5f6-5fae-437a-953e-e637754ec2b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685957591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.1685957591
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.1147434647
Short name T146
Test name
Test status
Simulation time 280085512587 ps
CPU time 915.96 seconds
Started Mar 12 12:31:35 PM PDT 24
Finished Mar 12 12:46:51 PM PDT 24
Peak memory 191512 kb
Host smart-4dece2a0-b30c-4843-9d8a-3294dccf84d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147434647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.1147434647
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/99.rv_timer_random.4264414678
Short name T101
Test name
Test status
Simulation time 652643963596 ps
CPU time 741.36 seconds
Started Mar 12 12:31:45 PM PDT 24
Finished Mar 12 12:44:07 PM PDT 24
Peak memory 191440 kb
Host smart-00306ec4-e819-4f67-9eae-ad2f3ad2f3f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264414678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.4264414678
Directory /workspace/99.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.455978124
Short name T328
Test name
Test status
Simulation time 182341617758 ps
CPU time 197.37 seconds
Started Mar 12 12:32:00 PM PDT 24
Finished Mar 12 12:35:18 PM PDT 24
Peak memory 191556 kb
Host smart-80d56aba-2ee1-4bc1-9f1b-c393ff1f4923
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455978124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.455978124
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.3675407616
Short name T194
Test name
Test status
Simulation time 111572923715 ps
CPU time 542.15 seconds
Started Mar 12 12:31:15 PM PDT 24
Finished Mar 12 12:40:17 PM PDT 24
Peak memory 191524 kb
Host smart-15a06fcb-7e12-49ed-bc75-2c8d17f092f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675407616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3675407616
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1950357625
Short name T242
Test name
Test status
Simulation time 561043071336 ps
CPU time 745.6 seconds
Started Mar 12 12:31:34 PM PDT 24
Finished Mar 12 12:44:00 PM PDT 24
Peak memory 196776 kb
Host smart-2e3a4c44-5835-4b75-a155-d5fdf4165855
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950357625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1950357625
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.2451936102
Short name T207
Test name
Test status
Simulation time 1634427478665 ps
CPU time 1124.18 seconds
Started Mar 12 12:31:35 PM PDT 24
Finished Mar 12 12:50:20 PM PDT 24
Peak memory 195484 kb
Host smart-21afad39-53a4-469e-886c-4a383e3c160a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451936102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.2451936102
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_random.375360932
Short name T314
Test name
Test status
Simulation time 1427374953370 ps
CPU time 979.77 seconds
Started Mar 12 12:31:36 PM PDT 24
Finished Mar 12 12:47:56 PM PDT 24
Peak memory 191580 kb
Host smart-5c6598e2-8583-449a-9b5b-ed265eaee244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375360932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.375360932
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random.10307291
Short name T214
Test name
Test status
Simulation time 193387794229 ps
CPU time 127.28 seconds
Started Mar 12 12:31:53 PM PDT 24
Finished Mar 12 12:34:01 PM PDT 24
Peak memory 191644 kb
Host smart-af9bdec3-6bb1-448b-a6b4-1e7562cbf6e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10307291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.10307291
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.623132207
Short name T197
Test name
Test status
Simulation time 361388879268 ps
CPU time 203.36 seconds
Started Mar 12 12:31:41 PM PDT 24
Finished Mar 12 12:35:05 PM PDT 24
Peak memory 194736 kb
Host smart-bce17dc0-6351-4214-b96a-2eb4eb17a384
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623132207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.623132207
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random.3453925444
Short name T63
Test name
Test status
Simulation time 146328597032 ps
CPU time 243.74 seconds
Started Mar 12 12:31:28 PM PDT 24
Finished Mar 12 12:35:32 PM PDT 24
Peak memory 195012 kb
Host smart-c92398fc-f759-4a78-8ad7-732b7d8d92e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453925444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3453925444
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.2161936341
Short name T431
Test name
Test status
Simulation time 2187168514344 ps
CPU time 415.05 seconds
Started Mar 12 12:31:52 PM PDT 24
Finished Mar 12 12:38:47 PM PDT 24
Peak memory 191648 kb
Host smart-32f2a304-5a43-4d08-ae33-1190d6bd1f61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161936341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2161936341
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.746513569
Short name T236
Test name
Test status
Simulation time 123445318855 ps
CPU time 909.24 seconds
Started Mar 12 12:31:45 PM PDT 24
Finished Mar 12 12:47:00 PM PDT 24
Peak memory 191520 kb
Host smart-e95fc932-ce98-4e95-bed6-23451ababa03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746513569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.746513569
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3897701260
Short name T70
Test name
Test status
Simulation time 29228873 ps
CPU time 0.8 seconds
Started Mar 12 12:49:16 PM PDT 24
Finished Mar 12 12:49:17 PM PDT 24
Peak memory 191996 kb
Host smart-4bab4a59-3e5c-4034-9ac3-8b0a94d0567e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897701260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3897701260
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/105.rv_timer_random.125642704
Short name T222
Test name
Test status
Simulation time 32992849726 ps
CPU time 33.36 seconds
Started Mar 12 12:31:39 PM PDT 24
Finished Mar 12 12:32:13 PM PDT 24
Peak memory 183308 kb
Host smart-dffc9895-0ab0-474b-b5cf-d8f00db656b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125642704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.125642704
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.1001176912
Short name T178
Test name
Test status
Simulation time 62740887243 ps
CPU time 428.22 seconds
Started Mar 12 12:31:54 PM PDT 24
Finished Mar 12 12:39:02 PM PDT 24
Peak memory 191512 kb
Host smart-84d2d13d-0cf4-4e70-bc2d-ab361af5248b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001176912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1001176912
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.124265019
Short name T292
Test name
Test status
Simulation time 163862692367 ps
CPU time 723.49 seconds
Started Mar 12 12:32:06 PM PDT 24
Finished Mar 12 12:44:10 PM PDT 24
Peak memory 191496 kb
Host smart-f24e1915-b4f8-4237-a280-522e99e1f8c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124265019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.124265019
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2414383139
Short name T240
Test name
Test status
Simulation time 367041367484 ps
CPU time 901.75 seconds
Started Mar 12 12:31:15 PM PDT 24
Finished Mar 12 12:46:17 PM PDT 24
Peak memory 195188 kb
Host smart-86a3cd30-60b7-42e0-9624-d8acbc520b24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414383139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2414383139
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/172.rv_timer_random.913224375
Short name T285
Test name
Test status
Simulation time 1598453801236 ps
CPU time 698.97 seconds
Started Mar 12 12:31:50 PM PDT 24
Finished Mar 12 12:43:29 PM PDT 24
Peak memory 193656 kb
Host smart-bdf87ae6-38be-4315-8093-ec1f6aa77d2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913224375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.913224375
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.3001972503
Short name T284
Test name
Test status
Simulation time 1655559669609 ps
CPU time 525.11 seconds
Started Mar 12 12:31:11 PM PDT 24
Finished Mar 12 12:39:56 PM PDT 24
Peak memory 191528 kb
Host smart-b98aa889-727c-47c0-a0d7-31f9b28fbd0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001972503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
3001972503
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_random.2215100447
Short name T20
Test name
Test status
Simulation time 1029665913632 ps
CPU time 643.59 seconds
Started Mar 12 12:31:12 PM PDT 24
Finished Mar 12 12:41:57 PM PDT 24
Peak memory 191484 kb
Host smart-cdd528da-f02c-4d2b-97c0-99644525bbd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215100447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.2215100447
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1788097184
Short name T185
Test name
Test status
Simulation time 783873280029 ps
CPU time 1419.27 seconds
Started Mar 12 12:32:39 PM PDT 24
Finished Mar 12 12:56:18 PM PDT 24
Peak memory 191184 kb
Host smart-9a3d9b1b-1c97-4c01-a858-db7997acf27f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788097184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1788097184
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.645973937
Short name T107
Test name
Test status
Simulation time 30753866142 ps
CPU time 57.54 seconds
Started Mar 12 12:31:36 PM PDT 24
Finished Mar 12 12:32:33 PM PDT 24
Peak memory 183268 kb
Host smart-645c9b77-c14f-4e05-9510-f409845b21da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645973937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.645973937
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.4266739307
Short name T289
Test name
Test status
Simulation time 544351926944 ps
CPU time 489.77 seconds
Started Mar 12 12:31:50 PM PDT 24
Finished Mar 12 12:40:00 PM PDT 24
Peak memory 183308 kb
Host smart-9cef65dc-dc2d-414d-96d8-935c096e7edd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266739307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.4266739307
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/64.rv_timer_random.1416564745
Short name T307
Test name
Test status
Simulation time 349642086897 ps
CPU time 186.53 seconds
Started Mar 12 12:31:47 PM PDT 24
Finished Mar 12 12:34:54 PM PDT 24
Peak memory 191628 kb
Host smart-800bb7f9-f810-44c6-be96-3a2fc34d0012
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416564745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1416564745
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2893604105
Short name T172
Test name
Test status
Simulation time 572009146900 ps
CPU time 2170.98 seconds
Started Mar 12 12:31:46 PM PDT 24
Finished Mar 12 01:07:57 PM PDT 24
Peak memory 191428 kb
Host smart-71be1050-3bbc-4af7-9309-8188db543053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893604105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2893604105
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.4293817148
Short name T94
Test name
Test status
Simulation time 179729608 ps
CPU time 1.27 seconds
Started Mar 12 12:49:17 PM PDT 24
Finished Mar 12 12:49:19 PM PDT 24
Peak memory 195560 kb
Host smart-0bb6bee0-16c9-47ba-9ace-cd438138ab7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293817148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.4293817148
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.4245378806
Short name T125
Test name
Test status
Simulation time 356692363635 ps
CPU time 182.46 seconds
Started Mar 12 12:30:59 PM PDT 24
Finished Mar 12 12:34:02 PM PDT 24
Peak memory 183328 kb
Host smart-75e9ebd0-f9fe-4ba1-9333-7d29b6dc94de
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245378806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.4245378806
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3596099342
Short name T167
Test name
Test status
Simulation time 70971146889 ps
CPU time 110.05 seconds
Started Mar 12 12:31:11 PM PDT 24
Finished Mar 12 12:33:02 PM PDT 24
Peak memory 195144 kb
Host smart-1ccce1d5-82ab-4c71-91aa-34794b0e6cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596099342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3596099342
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.2480938311
Short name T340
Test name
Test status
Simulation time 1155828822433 ps
CPU time 552.86 seconds
Started Mar 12 12:31:31 PM PDT 24
Finished Mar 12 12:40:44 PM PDT 24
Peak memory 191596 kb
Host smart-822b02d1-9e0b-4a8d-baad-14ecb0877e0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480938311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
2480938311
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.947534736
Short name T128
Test name
Test status
Simulation time 177892227600 ps
CPU time 143.97 seconds
Started Mar 12 12:31:37 PM PDT 24
Finished Mar 12 12:34:01 PM PDT 24
Peak memory 183260 kb
Host smart-a8aae6e3-850f-41f3-8e51-7be2bd2e602e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947534736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.947534736
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/102.rv_timer_random.2252453312
Short name T126
Test name
Test status
Simulation time 593605487080 ps
CPU time 661.75 seconds
Started Mar 12 12:31:48 PM PDT 24
Finished Mar 12 12:42:50 PM PDT 24
Peak memory 193684 kb
Host smart-aee8d19b-420a-48c4-bfff-e9b0e08577ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252453312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2252453312
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.823239796
Short name T302
Test name
Test status
Simulation time 105236748672 ps
CPU time 2461.15 seconds
Started Mar 12 12:31:57 PM PDT 24
Finished Mar 12 01:12:58 PM PDT 24
Peak memory 191500 kb
Host smart-79217d19-1f19-412b-bd55-54c377ba4428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823239796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.823239796
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.893426322
Short name T147
Test name
Test status
Simulation time 374117612138 ps
CPU time 571.65 seconds
Started Mar 12 12:31:36 PM PDT 24
Finished Mar 12 12:41:07 PM PDT 24
Peak memory 191532 kb
Host smart-2d6282fb-b2ea-43db-95f2-2a52b7187e68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893426322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.
893426322
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/129.rv_timer_random.3332661138
Short name T235
Test name
Test status
Simulation time 286801862514 ps
CPU time 244.44 seconds
Started Mar 12 12:31:47 PM PDT 24
Finished Mar 12 12:35:51 PM PDT 24
Peak memory 191508 kb
Host smart-1a5aafcc-d86f-45d6-a361-debe5964e050
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332661138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3332661138
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.2502651792
Short name T171
Test name
Test status
Simulation time 107161955311 ps
CPU time 169.58 seconds
Started Mar 12 12:31:53 PM PDT 24
Finished Mar 12 12:34:42 PM PDT 24
Peak memory 191468 kb
Host smart-d50d8ea6-cbbf-427f-90be-b2ce1a80bd25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502651792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2502651792
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3965529867
Short name T199
Test name
Test status
Simulation time 321531877988 ps
CPU time 70.55 seconds
Started Mar 12 12:32:01 PM PDT 24
Finished Mar 12 12:33:11 PM PDT 24
Peak memory 191532 kb
Host smart-c42922d6-5d0d-4492-b691-d54bfbbbd55f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965529867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3965529867
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.3248660321
Short name T177
Test name
Test status
Simulation time 402599527727 ps
CPU time 312.36 seconds
Started Mar 12 12:31:57 PM PDT 24
Finished Mar 12 12:37:10 PM PDT 24
Peak memory 191472 kb
Host smart-02045948-5c89-4c79-b529-45ed093b2177
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248660321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3248660321
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.2520830545
Short name T223
Test name
Test status
Simulation time 144455639050 ps
CPU time 495.49 seconds
Started Mar 12 12:31:55 PM PDT 24
Finished Mar 12 12:40:11 PM PDT 24
Peak memory 191508 kb
Host smart-889f8ca6-f7c5-4cf0-bd34-b94bfb6eaee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520830545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2520830545
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.405232737
Short name T414
Test name
Test status
Simulation time 124018816509 ps
CPU time 290.76 seconds
Started Mar 12 12:31:37 PM PDT 24
Finished Mar 12 12:36:28 PM PDT 24
Peak memory 191524 kb
Host smart-c46e479b-c38e-422c-81e5-a4939fa42f98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405232737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.405232737
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.2593910987
Short name T301
Test name
Test status
Simulation time 80263908932 ps
CPU time 145.59 seconds
Started Mar 12 12:32:03 PM PDT 24
Finished Mar 12 12:34:29 PM PDT 24
Peak memory 183388 kb
Host smart-2775c3a6-cd0e-4ce8-b609-5181e6fe6ae6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593910987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2593910987
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.283051265
Short name T117
Test name
Test status
Simulation time 412645944632 ps
CPU time 1500.69 seconds
Started Mar 12 12:31:26 PM PDT 24
Finished Mar 12 12:56:27 PM PDT 24
Peak memory 191556 kb
Host smart-11346a9c-caad-4440-9228-c290ad3961f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283051265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.
283051265
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_random.2017076020
Short name T138
Test name
Test status
Simulation time 47997914637 ps
CPU time 224.45 seconds
Started Mar 12 12:31:21 PM PDT 24
Finished Mar 12 12:35:05 PM PDT 24
Peak memory 191528 kb
Host smart-e4052875-2fdf-478b-acc1-a23c1bd65be1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017076020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2017076020
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3112456315
Short name T252
Test name
Test status
Simulation time 1319526000937 ps
CPU time 694.64 seconds
Started Mar 12 12:31:36 PM PDT 24
Finished Mar 12 12:43:11 PM PDT 24
Peak memory 183312 kb
Host smart-ea0b07a1-0f1e-4863-bd00-503107f9cb6b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112456315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3112456315
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2140082962
Short name T32
Test name
Test status
Simulation time 2261804638721 ps
CPU time 881.05 seconds
Started Mar 12 12:31:44 PM PDT 24
Finished Mar 12 12:46:25 PM PDT 24
Peak memory 191500 kb
Host smart-736750ac-0a82-4980-9e04-e31520e0bf15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140082962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2140082962
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_random.3075308939
Short name T312
Test name
Test status
Simulation time 202626243012 ps
CPU time 664.62 seconds
Started Mar 12 12:32:39 PM PDT 24
Finished Mar 12 12:43:44 PM PDT 24
Peak memory 191196 kb
Host smart-b64b04ba-ca29-46ec-8a47-7e6b4e3034a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075308939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3075308939
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.3054770015
Short name T229
Test name
Test status
Simulation time 1281647080262 ps
CPU time 747.51 seconds
Started Mar 12 12:31:30 PM PDT 24
Finished Mar 12 12:43:57 PM PDT 24
Peak memory 183292 kb
Host smart-d2f38c15-64f0-46d4-ad21-bd3e3d1e2fa9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054770015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.3054770015
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1185748716
Short name T155
Test name
Test status
Simulation time 4947868841222 ps
CPU time 1131.23 seconds
Started Mar 12 12:31:38 PM PDT 24
Finished Mar 12 12:50:30 PM PDT 24
Peak memory 183320 kb
Host smart-42aafb3f-d7c5-4515-9aff-1b65e15617fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185748716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1185748716
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/51.rv_timer_random.2922964466
Short name T311
Test name
Test status
Simulation time 80590833598 ps
CPU time 139.28 seconds
Started Mar 12 12:31:37 PM PDT 24
Finished Mar 12 12:33:56 PM PDT 24
Peak memory 192632 kb
Host smart-da272f0c-bfed-4bd2-9697-660c40b1fc0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922964466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2922964466
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.509240898
Short name T163
Test name
Test status
Simulation time 95978841415 ps
CPU time 195.54 seconds
Started Mar 12 12:31:37 PM PDT 24
Finished Mar 12 12:34:53 PM PDT 24
Peak memory 183420 kb
Host smart-5263634b-8c4b-4bf9-acab-cf74fc153aa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509240898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.509240898
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.448171093
Short name T295
Test name
Test status
Simulation time 245529124724 ps
CPU time 488.64 seconds
Started Mar 12 12:31:42 PM PDT 24
Finished Mar 12 12:39:50 PM PDT 24
Peak memory 191492 kb
Host smart-6f6d9947-11e9-46e5-bbd8-d3c57e3f67bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448171093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.448171093
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.868807646
Short name T145
Test name
Test status
Simulation time 191000428196 ps
CPU time 313.78 seconds
Started Mar 12 12:31:57 PM PDT 24
Finished Mar 12 12:37:11 PM PDT 24
Peak memory 194412 kb
Host smart-fa06c37e-3de1-462a-b54d-28f488d92827
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868807646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.868807646
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3992946992
Short name T491
Test name
Test status
Simulation time 1383793508 ps
CPU time 3.5 seconds
Started Mar 12 12:49:10 PM PDT 24
Finished Mar 12 12:49:13 PM PDT 24
Peak memory 191444 kb
Host smart-553a700e-dc52-4d3a-8db4-f6ddf4664a3a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992946992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3992946992
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.197040566
Short name T77
Test name
Test status
Simulation time 53253825 ps
CPU time 0.6 seconds
Started Mar 12 12:48:58 PM PDT 24
Finished Mar 12 12:48:59 PM PDT 24
Peak memory 182988 kb
Host smart-89e163da-7201-430f-998a-79e34b70d0df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197040566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_re
set.197040566
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2279154034
Short name T538
Test name
Test status
Simulation time 137543066 ps
CPU time 0.96 seconds
Started Mar 12 12:49:05 PM PDT 24
Finished Mar 12 12:49:06 PM PDT 24
Peak memory 197564 kb
Host smart-3f9ff97d-30c6-4add-adc6-2f680928f40b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279154034 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2279154034
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.640654640
Short name T78
Test name
Test status
Simulation time 12588854 ps
CPU time 0.53 seconds
Started Mar 12 12:49:05 PM PDT 24
Finished Mar 12 12:49:05 PM PDT 24
Peak memory 182624 kb
Host smart-1043f746-b87c-41b3-b23a-46e698990672
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640654640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.640654640
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2096293399
Short name T562
Test name
Test status
Simulation time 12532185 ps
CPU time 0.54 seconds
Started Mar 12 12:49:04 PM PDT 24
Finished Mar 12 12:49:05 PM PDT 24
Peak memory 182016 kb
Host smart-d3f89ee1-72d0-446d-ab0e-84b83ec2acb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096293399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2096293399
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1643195882
Short name T567
Test name
Test status
Simulation time 64670881 ps
CPU time 0.61 seconds
Started Mar 12 12:49:08 PM PDT 24
Finished Mar 12 12:49:10 PM PDT 24
Peak memory 191764 kb
Host smart-714663db-f96e-458e-89e1-d7eb3f4a1ebf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643195882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1643195882
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2574026548
Short name T455
Test name
Test status
Simulation time 26876093 ps
CPU time 1.24 seconds
Started Mar 12 12:49:04 PM PDT 24
Finished Mar 12 12:49:06 PM PDT 24
Peak memory 197784 kb
Host smart-1d74ac8a-68c2-42d0-b0ca-271c67b35667
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574026548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2574026548
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1421838722
Short name T68
Test name
Test status
Simulation time 97231323 ps
CPU time 0.72 seconds
Started Mar 12 12:49:09 PM PDT 24
Finished Mar 12 12:49:10 PM PDT 24
Peak memory 183060 kb
Host smart-69b9eb9d-a5d0-43cf-b7f7-9eb3c05be3c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421838722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1421838722
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1639571393
Short name T535
Test name
Test status
Simulation time 250284575 ps
CPU time 2.55 seconds
Started Mar 12 12:49:05 PM PDT 24
Finished Mar 12 12:49:07 PM PDT 24
Peak memory 192448 kb
Host smart-acbd1c91-94d9-4e9f-929a-1aeceafb739c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639571393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.1639571393
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2530967979
Short name T486
Test name
Test status
Simulation time 104813462 ps
CPU time 0.55 seconds
Started Mar 12 12:49:09 PM PDT 24
Finished Mar 12 12:49:10 PM PDT 24
Peak memory 183008 kb
Host smart-84efe787-ffb7-4182-b4ee-8ec3b5dedad8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530967979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.2530967979
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.4068443103
Short name T31
Test name
Test status
Simulation time 21805022 ps
CPU time 0.74 seconds
Started Mar 12 12:49:14 PM PDT 24
Finished Mar 12 12:49:15 PM PDT 24
Peak memory 195572 kb
Host smart-512081e9-5b0c-4551-bdf1-8b0d45137b87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068443103 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.4068443103
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1595929966
Short name T84
Test name
Test status
Simulation time 13710516 ps
CPU time 0.55 seconds
Started Mar 12 12:49:00 PM PDT 24
Finished Mar 12 12:49:01 PM PDT 24
Peak memory 182684 kb
Host smart-438ba2af-8b02-4ed7-95bf-5a523fa126a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595929966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1595929966
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.660415370
Short name T488
Test name
Test status
Simulation time 14924034 ps
CPU time 0.54 seconds
Started Mar 12 12:48:59 PM PDT 24
Finished Mar 12 12:49:00 PM PDT 24
Peak memory 182816 kb
Host smart-7911d40a-cc1f-4f4b-b8e2-b0b434aad702
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660415370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.660415370
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4197095060
Short name T575
Test name
Test status
Simulation time 14981906 ps
CPU time 0.59 seconds
Started Mar 12 12:49:06 PM PDT 24
Finished Mar 12 12:49:07 PM PDT 24
Peak memory 192368 kb
Host smart-ef9809ed-4d25-446f-9970-68c25d4b4390
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197095060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.4197095060
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1028485369
Short name T505
Test name
Test status
Simulation time 386224435 ps
CPU time 2.78 seconds
Started Mar 12 12:49:16 PM PDT 24
Finished Mar 12 12:49:19 PM PDT 24
Peak memory 197264 kb
Host smart-fc3a60ab-e174-4596-a6b8-eacdf2d08e99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028485369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1028485369
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3919974235
Short name T27
Test name
Test status
Simulation time 862846123 ps
CPU time 1.3 seconds
Started Mar 12 12:49:04 PM PDT 24
Finished Mar 12 12:49:06 PM PDT 24
Peak memory 195560 kb
Host smart-085b693d-f8f8-458e-b59e-920e492ecfa1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919974235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3919974235
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2786411331
Short name T533
Test name
Test status
Simulation time 137749886 ps
CPU time 0.76 seconds
Started Mar 12 12:49:17 PM PDT 24
Finished Mar 12 12:49:18 PM PDT 24
Peak memory 195176 kb
Host smart-f2c94f37-2b3d-49c9-8f90-928418f920bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786411331 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2786411331
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2658264137
Short name T478
Test name
Test status
Simulation time 60516124 ps
CPU time 0.57 seconds
Started Mar 12 12:49:10 PM PDT 24
Finished Mar 12 12:49:12 PM PDT 24
Peak memory 182980 kb
Host smart-17df0749-a643-4afc-a349-57036b470493
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658264137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2658264137
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3881469454
Short name T577
Test name
Test status
Simulation time 20218309 ps
CPU time 0.5 seconds
Started Mar 12 12:49:20 PM PDT 24
Finished Mar 12 12:49:21 PM PDT 24
Peak memory 182056 kb
Host smart-297b2d1d-ff67-43c7-98e0-f848e4ed8f4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881469454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3881469454
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3883110346
Short name T457
Test name
Test status
Simulation time 283140322 ps
CPU time 1.52 seconds
Started Mar 12 12:49:11 PM PDT 24
Finished Mar 12 12:49:13 PM PDT 24
Peak memory 197920 kb
Host smart-896ce9ac-ae77-426c-96b0-c9449e286558
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883110346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3883110346
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.4202120845
Short name T503
Test name
Test status
Simulation time 366789683 ps
CPU time 1.1 seconds
Started Mar 12 12:49:15 PM PDT 24
Finished Mar 12 12:49:17 PM PDT 24
Peak memory 194408 kb
Host smart-9029124b-dccd-4d3c-b9b2-524be538746e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202120845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.4202120845
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1410444061
Short name T513
Test name
Test status
Simulation time 20227974 ps
CPU time 0.97 seconds
Started Mar 12 12:49:19 PM PDT 24
Finished Mar 12 12:49:20 PM PDT 24
Peak memory 197692 kb
Host smart-5da5c647-2c1e-45c9-acc6-8795e2f4ab0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410444061 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1410444061
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1276134020
Short name T75
Test name
Test status
Simulation time 13170198 ps
CPU time 0.52 seconds
Started Mar 12 12:49:14 PM PDT 24
Finished Mar 12 12:49:15 PM PDT 24
Peak memory 182720 kb
Host smart-6c470c87-473a-4533-990a-0d2ed207fcd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276134020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1276134020
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2836369910
Short name T495
Test name
Test status
Simulation time 14259373 ps
CPU time 0.53 seconds
Started Mar 12 12:49:14 PM PDT 24
Finished Mar 12 12:49:15 PM PDT 24
Peak memory 182872 kb
Host smart-6b4e8b18-c1ca-4185-99c0-713f578d1fbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836369910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2836369910
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1950991202
Short name T90
Test name
Test status
Simulation time 18694250 ps
CPU time 0.64 seconds
Started Mar 12 12:49:12 PM PDT 24
Finished Mar 12 12:49:13 PM PDT 24
Peak memory 192300 kb
Host smart-dee61b01-49ad-40c5-931a-4cad7f84e951
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950991202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.1950991202
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2635193586
Short name T507
Test name
Test status
Simulation time 328832721 ps
CPU time 1.56 seconds
Started Mar 12 12:49:18 PM PDT 24
Finished Mar 12 12:49:20 PM PDT 24
Peak memory 197920 kb
Host smart-bd3f184c-c85b-4355-9b7d-9c270742515b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635193586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2635193586
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2751646243
Short name T480
Test name
Test status
Simulation time 168061283 ps
CPU time 0.76 seconds
Started Mar 12 12:49:13 PM PDT 24
Finished Mar 12 12:49:14 PM PDT 24
Peak memory 183196 kb
Host smart-3d12fe29-2e85-4b77-bd2d-780d5a0efb95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751646243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.2751646243
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.4253998994
Short name T527
Test name
Test status
Simulation time 61802324 ps
CPU time 0.68 seconds
Started Mar 12 12:49:20 PM PDT 24
Finished Mar 12 12:49:21 PM PDT 24
Peak memory 194024 kb
Host smart-080fe9a4-0796-4d1e-a1a5-3936bdc003f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253998994 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.4253998994
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2053055598
Short name T548
Test name
Test status
Simulation time 14581967 ps
CPU time 0.62 seconds
Started Mar 12 12:49:14 PM PDT 24
Finished Mar 12 12:49:15 PM PDT 24
Peak memory 183048 kb
Host smart-01b34f62-2247-48d5-943d-f9af7a0a7f1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053055598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2053055598
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.535285914
Short name T568
Test name
Test status
Simulation time 40930686 ps
CPU time 0.57 seconds
Started Mar 12 12:49:18 PM PDT 24
Finished Mar 12 12:49:19 PM PDT 24
Peak memory 182804 kb
Host smart-55ee770b-7bf6-4915-b966-aa83318621d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535285914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.535285914
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1106828996
Short name T511
Test name
Test status
Simulation time 77607376 ps
CPU time 0.75 seconds
Started Mar 12 12:49:20 PM PDT 24
Finished Mar 12 12:49:21 PM PDT 24
Peak memory 192008 kb
Host smart-edd52fd1-88a0-4b20-aee4-0662adb9746b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106828996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1106828996
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3769520513
Short name T499
Test name
Test status
Simulation time 208657075 ps
CPU time 2.69 seconds
Started Mar 12 12:49:13 PM PDT 24
Finished Mar 12 12:49:16 PM PDT 24
Peak memory 197928 kb
Host smart-385930a3-ad70-4e90-a2ad-226c68639a22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769520513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.3769520513
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1326794047
Short name T29
Test name
Test status
Simulation time 60299538 ps
CPU time 0.83 seconds
Started Mar 12 12:49:20 PM PDT 24
Finished Mar 12 12:49:21 PM PDT 24
Peak memory 193748 kb
Host smart-ca2e145f-c94f-4114-adac-0b7ffd096930
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326794047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.1326794047
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1669850150
Short name T519
Test name
Test status
Simulation time 102104123 ps
CPU time 0.78 seconds
Started Mar 12 12:49:21 PM PDT 24
Finished Mar 12 12:49:22 PM PDT 24
Peak memory 195716 kb
Host smart-809c9d4a-2426-491a-b01a-478165a7e435
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669850150 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.1669850150
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3366944087
Short name T82
Test name
Test status
Simulation time 25919058 ps
CPU time 0.65 seconds
Started Mar 12 12:49:20 PM PDT 24
Finished Mar 12 12:49:20 PM PDT 24
Peak memory 182860 kb
Host smart-cd1f36e8-b5e5-4b31-a00c-8bc390271468
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366944087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3366944087
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2887466191
Short name T468
Test name
Test status
Simulation time 29580381 ps
CPU time 0.62 seconds
Started Mar 12 12:49:20 PM PDT 24
Finished Mar 12 12:49:20 PM PDT 24
Peak memory 182680 kb
Host smart-9e37ee96-c078-40bc-acba-fe4cae15e73a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887466191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2887466191
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3428764316
Short name T72
Test name
Test status
Simulation time 24307422 ps
CPU time 0.66 seconds
Started Mar 12 12:49:11 PM PDT 24
Finished Mar 12 12:49:13 PM PDT 24
Peak memory 192328 kb
Host smart-36f96340-8680-488f-9b9f-7e1c1d00611c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428764316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.3428764316
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.4133476170
Short name T465
Test name
Test status
Simulation time 339018919 ps
CPU time 1.94 seconds
Started Mar 12 12:49:12 PM PDT 24
Finished Mar 12 12:49:14 PM PDT 24
Peak memory 197976 kb
Host smart-fea7217f-0b5d-4e2b-8f0c-902ae2c2a8a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133476170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.4133476170
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2918257321
Short name T532
Test name
Test status
Simulation time 85215455 ps
CPU time 1.09 seconds
Started Mar 12 12:49:11 PM PDT 24
Finished Mar 12 12:49:12 PM PDT 24
Peak memory 195024 kb
Host smart-bbb530ed-64ad-4ead-aebb-02a3290a1377
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918257321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2918257321
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.551728172
Short name T481
Test name
Test status
Simulation time 84050776 ps
CPU time 1.15 seconds
Started Mar 12 12:49:20 PM PDT 24
Finished Mar 12 12:49:21 PM PDT 24
Peak memory 197816 kb
Host smart-dcdc1b5c-4546-47d2-8d44-35b2d43dda59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551728172 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.551728172
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3632112581
Short name T79
Test name
Test status
Simulation time 38053225 ps
CPU time 0.51 seconds
Started Mar 12 12:49:13 PM PDT 24
Finished Mar 12 12:49:14 PM PDT 24
Peak memory 182592 kb
Host smart-f97c0a7f-f21b-4a9b-bf3c-cb1bf1bbec34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632112581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3632112581
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3476159630
Short name T552
Test name
Test status
Simulation time 14321444 ps
CPU time 0.54 seconds
Started Mar 12 12:49:20 PM PDT 24
Finished Mar 12 12:49:20 PM PDT 24
Peak memory 182040 kb
Host smart-f9b33c29-e5b6-4cb7-8b38-f5a419f0880d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476159630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3476159630
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2677131094
Short name T576
Test name
Test status
Simulation time 18742106 ps
CPU time 0.72 seconds
Started Mar 12 12:49:20 PM PDT 24
Finished Mar 12 12:49:21 PM PDT 24
Peak memory 193488 kb
Host smart-8a9e0aa2-5bee-4e32-ba5e-511543fd3614
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677131094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.2677131094
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2048223894
Short name T456
Test name
Test status
Simulation time 606773256 ps
CPU time 2.5 seconds
Started Mar 12 12:49:15 PM PDT 24
Finished Mar 12 12:49:18 PM PDT 24
Peak memory 197952 kb
Host smart-91a87634-9fee-42b1-bfe3-aa93b36f05c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048223894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2048223894
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3429414511
Short name T93
Test name
Test status
Simulation time 306274097 ps
CPU time 1.08 seconds
Started Mar 12 12:49:17 PM PDT 24
Finished Mar 12 12:49:18 PM PDT 24
Peak memory 195424 kb
Host smart-eeb73177-1630-4e1d-9e5d-f16da510bcbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429414511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.3429414511
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1524843395
Short name T508
Test name
Test status
Simulation time 129069976 ps
CPU time 1.17 seconds
Started Mar 12 12:49:17 PM PDT 24
Finished Mar 12 12:49:18 PM PDT 24
Peak memory 197668 kb
Host smart-f7ea2c36-70cc-46a8-bdd3-515218442192
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524843395 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1524843395
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1348611175
Short name T475
Test name
Test status
Simulation time 20674737 ps
CPU time 0.56 seconds
Started Mar 12 12:49:15 PM PDT 24
Finished Mar 12 12:49:16 PM PDT 24
Peak memory 183008 kb
Host smart-676997eb-9abf-4f6a-9818-84a9cbef4aed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348611175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1348611175
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.4163502728
Short name T515
Test name
Test status
Simulation time 13231707 ps
CPU time 0.56 seconds
Started Mar 12 12:49:20 PM PDT 24
Finished Mar 12 12:49:20 PM PDT 24
Peak memory 182708 kb
Host smart-b69f080a-47f1-4c25-bfc2-70611d7961eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163502728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.4163502728
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3340062394
Short name T89
Test name
Test status
Simulation time 190302847 ps
CPU time 0.85 seconds
Started Mar 12 12:49:19 PM PDT 24
Finished Mar 12 12:49:20 PM PDT 24
Peak memory 192016 kb
Host smart-c47d5a0e-bf8e-418b-b347-c4b57ca00273
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340062394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3340062394
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3393248662
Short name T549
Test name
Test status
Simulation time 83998134 ps
CPU time 1.72 seconds
Started Mar 12 12:49:19 PM PDT 24
Finished Mar 12 12:49:21 PM PDT 24
Peak memory 197928 kb
Host smart-dcbed45c-242a-4d80-a067-e1fb712fe196
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393248662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3393248662
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.250737010
Short name T487
Test name
Test status
Simulation time 350172715 ps
CPU time 0.79 seconds
Started Mar 12 12:49:17 PM PDT 24
Finished Mar 12 12:49:18 PM PDT 24
Peak memory 196444 kb
Host smart-d4b28711-be56-4231-989d-947c6d35a16c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250737010 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.250737010
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.325532514
Short name T566
Test name
Test status
Simulation time 20364939 ps
CPU time 0.54 seconds
Started Mar 12 12:49:14 PM PDT 24
Finished Mar 12 12:49:15 PM PDT 24
Peak memory 182980 kb
Host smart-a1bfd418-f92e-4368-9cbe-066204cd2aa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325532514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.325532514
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.625111710
Short name T473
Test name
Test status
Simulation time 53864163 ps
CPU time 0.59 seconds
Started Mar 12 12:49:18 PM PDT 24
Finished Mar 12 12:49:19 PM PDT 24
Peak memory 182804 kb
Host smart-572c811a-d90f-4a73-8991-8b833dedba97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625111710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.625111710
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.189089594
Short name T51
Test name
Test status
Simulation time 521237005 ps
CPU time 0.73 seconds
Started Mar 12 12:49:19 PM PDT 24
Finished Mar 12 12:49:19 PM PDT 24
Peak memory 193220 kb
Host smart-f82de3ac-b0e3-4019-80c1-41f6946d6fb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189089594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_ti
mer_same_csr_outstanding.189089594
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1974078668
Short name T531
Test name
Test status
Simulation time 89553566 ps
CPU time 1.12 seconds
Started Mar 12 12:49:17 PM PDT 24
Finished Mar 12 12:49:19 PM PDT 24
Peak memory 197212 kb
Host smart-f04b56d0-b4f8-445e-930d-42a2c89eb154
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974078668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1974078668
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2118057087
Short name T96
Test name
Test status
Simulation time 92186494 ps
CPU time 1.31 seconds
Started Mar 12 12:49:14 PM PDT 24
Finished Mar 12 12:49:16 PM PDT 24
Peak memory 195608 kb
Host smart-55ba8344-78f5-443b-871b-6a5c47a3b102
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118057087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2118057087
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1686247510
Short name T560
Test name
Test status
Simulation time 29876259 ps
CPU time 1.36 seconds
Started Mar 12 12:49:21 PM PDT 24
Finished Mar 12 12:49:23 PM PDT 24
Peak memory 197964 kb
Host smart-38d7bfc0-ee9e-4862-bc31-780f92d650ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686247510 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1686247510
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2824093712
Short name T561
Test name
Test status
Simulation time 33152554 ps
CPU time 0.5 seconds
Started Mar 12 12:49:18 PM PDT 24
Finished Mar 12 12:49:19 PM PDT 24
Peak memory 182328 kb
Host smart-7c4e4401-91ca-45d5-ab4b-688985a0be42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824093712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2824093712
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3917395484
Short name T525
Test name
Test status
Simulation time 12772412 ps
CPU time 0.57 seconds
Started Mar 12 12:49:16 PM PDT 24
Finished Mar 12 12:49:18 PM PDT 24
Peak memory 182836 kb
Host smart-8cce13c1-f216-4feb-847b-c4f684c0b33f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917395484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3917395484
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.4124797009
Short name T71
Test name
Test status
Simulation time 13857382 ps
CPU time 0.61 seconds
Started Mar 12 12:49:20 PM PDT 24
Finished Mar 12 12:49:21 PM PDT 24
Peak memory 192176 kb
Host smart-f31026ea-8940-4278-963c-5cc34fcb6255
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124797009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.4124797009
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.666653752
Short name T482
Test name
Test status
Simulation time 426523801 ps
CPU time 2.02 seconds
Started Mar 12 12:49:17 PM PDT 24
Finished Mar 12 12:49:19 PM PDT 24
Peak memory 197900 kb
Host smart-bd3393e7-310a-4283-939e-aa3c4767feea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666653752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.666653752
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3637957120
Short name T528
Test name
Test status
Simulation time 230485029 ps
CPU time 1.41 seconds
Started Mar 12 12:49:18 PM PDT 24
Finished Mar 12 12:49:20 PM PDT 24
Peak memory 183620 kb
Host smart-1c92d153-9f1b-485c-8e85-9d6c6101b4a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637957120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3637957120
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2453692237
Short name T553
Test name
Test status
Simulation time 67459054 ps
CPU time 0.87 seconds
Started Mar 12 12:49:19 PM PDT 24
Finished Mar 12 12:49:21 PM PDT 24
Peak memory 197300 kb
Host smart-21da4edd-06e1-4678-a01a-8a4692ed7612
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453692237 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.2453692237
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3520801383
Short name T86
Test name
Test status
Simulation time 31456386 ps
CPU time 0.58 seconds
Started Mar 12 12:49:20 PM PDT 24
Finished Mar 12 12:49:21 PM PDT 24
Peak memory 192216 kb
Host smart-569c0def-31cf-49ac-b3a3-2100dbe7fc3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520801383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3520801383
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.655235998
Short name T476
Test name
Test status
Simulation time 16349980 ps
CPU time 0.56 seconds
Started Mar 12 12:49:18 PM PDT 24
Finished Mar 12 12:49:18 PM PDT 24
Peak memory 182848 kb
Host smart-ee0f5fbb-f57a-437a-b431-03bc195fe23d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655235998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.655235998
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1507278966
Short name T556
Test name
Test status
Simulation time 25428390 ps
CPU time 0.68 seconds
Started Mar 12 12:49:26 PM PDT 24
Finished Mar 12 12:49:29 PM PDT 24
Peak memory 192536 kb
Host smart-5a6c978b-ff21-4ce5-a016-87cab57a0100
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507278966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1507278966
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2125029630
Short name T522
Test name
Test status
Simulation time 84715809 ps
CPU time 1.15 seconds
Started Mar 12 12:49:19 PM PDT 24
Finished Mar 12 12:49:21 PM PDT 24
Peak memory 197708 kb
Host smart-f0d3f7a0-27ad-444f-83e2-5cf69d59a4eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125029630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2125029630
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.4293931100
Short name T95
Test name
Test status
Simulation time 924329026 ps
CPU time 1.23 seconds
Started Mar 12 12:49:25 PM PDT 24
Finished Mar 12 12:49:27 PM PDT 24
Peak memory 195380 kb
Host smart-eef32626-f2ca-4fc0-9c7f-1446281caac2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293931100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.4293931100
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2954644668
Short name T517
Test name
Test status
Simulation time 86112961 ps
CPU time 0.75 seconds
Started Mar 12 12:49:13 PM PDT 24
Finished Mar 12 12:49:14 PM PDT 24
Peak memory 195564 kb
Host smart-6151d77d-ec47-4c06-9e49-2929503e6b64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954644668 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2954644668
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.208464139
Short name T518
Test name
Test status
Simulation time 25027843 ps
CPU time 0.55 seconds
Started Mar 12 12:49:25 PM PDT 24
Finished Mar 12 12:49:28 PM PDT 24
Peak memory 183060 kb
Host smart-5b0f5446-7135-457c-bd07-1fa00753e5ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208464139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.208464139
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.380354501
Short name T557
Test name
Test status
Simulation time 24676384 ps
CPU time 0.53 seconds
Started Mar 12 12:49:21 PM PDT 24
Finished Mar 12 12:49:22 PM PDT 24
Peak memory 182044 kb
Host smart-59a2f464-96d5-4d5d-ba12-4b68dab9dbd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380354501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.380354501
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.12494507
Short name T530
Test name
Test status
Simulation time 71016677 ps
CPU time 0.83 seconds
Started Mar 12 12:49:20 PM PDT 24
Finished Mar 12 12:49:21 PM PDT 24
Peak memory 193648 kb
Host smart-6a00d774-c580-4ee3-8729-b4bbcec0f9c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12494507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_tim
er_same_csr_outstanding.12494507
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.539042257
Short name T512
Test name
Test status
Simulation time 226246471 ps
CPU time 2.23 seconds
Started Mar 12 12:49:25 PM PDT 24
Finished Mar 12 12:49:30 PM PDT 24
Peak memory 197832 kb
Host smart-3ae5db51-af16-4d4a-ab6d-968445d3ecfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539042257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.539042257
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.151729259
Short name T494
Test name
Test status
Simulation time 181642620 ps
CPU time 0.81 seconds
Started Mar 12 12:49:17 PM PDT 24
Finished Mar 12 12:49:18 PM PDT 24
Peak memory 183164 kb
Host smart-73d3e5ae-7e9a-4e76-82b5-7bbcf83125e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151729259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_in
tg_err.151729259
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1686752835
Short name T510
Test name
Test status
Simulation time 15761244 ps
CPU time 0.61 seconds
Started Mar 12 12:49:16 PM PDT 24
Finished Mar 12 12:49:16 PM PDT 24
Peak memory 183052 kb
Host smart-79ca116f-e436-44a2-9312-4c1c7cbf3867
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686752835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1686752835
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.4036779378
Short name T540
Test name
Test status
Simulation time 114412915 ps
CPU time 1.4 seconds
Started Mar 12 12:49:03 PM PDT 24
Finished Mar 12 12:49:04 PM PDT 24
Peak memory 192420 kb
Host smart-da0bab83-b521-4485-af17-f788800a5601
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036779378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.4036779378
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1111633685
Short name T85
Test name
Test status
Simulation time 52588130 ps
CPU time 0.6 seconds
Started Mar 12 12:49:13 PM PDT 24
Finished Mar 12 12:49:13 PM PDT 24
Peak memory 183000 kb
Host smart-2e0ed57d-9c14-41ff-ae66-755bc8281538
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111633685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.1111633685
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1605636276
Short name T537
Test name
Test status
Simulation time 59420805 ps
CPU time 0.75 seconds
Started Mar 12 12:49:02 PM PDT 24
Finished Mar 12 12:49:02 PM PDT 24
Peak memory 195844 kb
Host smart-921eeebb-daae-4b62-b5cc-9845bf568efe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605636276 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1605636276
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2058706875
Short name T524
Test name
Test status
Simulation time 15111755 ps
CPU time 0.58 seconds
Started Mar 12 12:49:09 PM PDT 24
Finished Mar 12 12:49:10 PM PDT 24
Peak memory 183064 kb
Host smart-d3753c26-6e1d-46a3-8bcb-c1ffd8c9250b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058706875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2058706875
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.948424675
Short name T559
Test name
Test status
Simulation time 28161137 ps
CPU time 0.53 seconds
Started Mar 12 12:49:16 PM PDT 24
Finished Mar 12 12:49:17 PM PDT 24
Peak memory 182020 kb
Host smart-cf9b119f-27a2-4160-831a-b1a7251518db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948424675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.948424675
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.228209056
Short name T555
Test name
Test status
Simulation time 48210591 ps
CPU time 0.68 seconds
Started Mar 12 12:49:11 PM PDT 24
Finished Mar 12 12:49:12 PM PDT 24
Peak memory 193356 kb
Host smart-7d76bda2-793e-4336-ae1d-9a3288b120f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228209056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_tim
er_same_csr_outstanding.228209056
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.4127170362
Short name T49
Test name
Test status
Simulation time 164815430 ps
CPU time 2.82 seconds
Started Mar 12 12:49:04 PM PDT 24
Finished Mar 12 12:49:07 PM PDT 24
Peak memory 197888 kb
Host smart-6071da5c-1190-421d-a57d-4cd98a0dae13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127170362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.4127170362
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3290191005
Short name T471
Test name
Test status
Simulation time 140505162 ps
CPU time 1.1 seconds
Started Mar 12 12:49:03 PM PDT 24
Finished Mar 12 12:49:05 PM PDT 24
Peak memory 195276 kb
Host smart-dac4bc83-33dc-4023-8974-6cc135673127
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290191005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.3290191005
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.265595313
Short name T546
Test name
Test status
Simulation time 22743702 ps
CPU time 0.53 seconds
Started Mar 12 12:49:13 PM PDT 24
Finished Mar 12 12:49:14 PM PDT 24
Peak memory 182440 kb
Host smart-e67b2173-faa8-4750-82e3-49ef2fac48a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265595313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.265595313
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3559967703
Short name T489
Test name
Test status
Simulation time 24993000 ps
CPU time 0.59 seconds
Started Mar 12 12:49:20 PM PDT 24
Finished Mar 12 12:49:21 PM PDT 24
Peak memory 182844 kb
Host smart-da3b7aec-c881-49be-a60e-84d62c829f90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559967703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3559967703
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3696425495
Short name T565
Test name
Test status
Simulation time 13734186 ps
CPU time 0.54 seconds
Started Mar 12 12:49:17 PM PDT 24
Finished Mar 12 12:49:17 PM PDT 24
Peak memory 181936 kb
Host smart-800f6001-d50b-47ed-953a-6a556398023d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696425495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3696425495
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.61841704
Short name T551
Test name
Test status
Simulation time 101265434 ps
CPU time 0.52 seconds
Started Mar 12 12:49:15 PM PDT 24
Finished Mar 12 12:49:16 PM PDT 24
Peak memory 182060 kb
Host smart-c9f20795-a3eb-4d35-8304-651cb867867a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61841704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.61841704
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3349537515
Short name T569
Test name
Test status
Simulation time 42457098 ps
CPU time 0.5 seconds
Started Mar 12 12:49:13 PM PDT 24
Finished Mar 12 12:49:13 PM PDT 24
Peak memory 182440 kb
Host smart-22568332-44a1-40a7-b0c7-6839f7ced2ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349537515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3349537515
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2251438651
Short name T453
Test name
Test status
Simulation time 28324449 ps
CPU time 0.56 seconds
Started Mar 12 12:49:13 PM PDT 24
Finished Mar 12 12:49:13 PM PDT 24
Peak memory 182832 kb
Host smart-c182b705-2335-4041-a556-7f2157a504e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251438651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2251438651
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.4211751046
Short name T485
Test name
Test status
Simulation time 11680039 ps
CPU time 0.55 seconds
Started Mar 12 12:49:16 PM PDT 24
Finished Mar 12 12:49:16 PM PDT 24
Peak memory 182416 kb
Host smart-48545b5d-57c0-463b-ab04-6c859a2cc633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211751046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.4211751046
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2360701023
Short name T509
Test name
Test status
Simulation time 12395602 ps
CPU time 0.55 seconds
Started Mar 12 12:49:11 PM PDT 24
Finished Mar 12 12:49:12 PM PDT 24
Peak memory 182836 kb
Host smart-ef292f62-1a8c-4a44-b066-36ca9440b5df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360701023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2360701023
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.370634053
Short name T523
Test name
Test status
Simulation time 32038609 ps
CPU time 0.56 seconds
Started Mar 12 12:49:18 PM PDT 24
Finished Mar 12 12:49:19 PM PDT 24
Peak memory 182904 kb
Host smart-3b367469-2161-49f9-ac4d-4d9a810e6939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370634053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.370634053
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1299547362
Short name T483
Test name
Test status
Simulation time 17222421 ps
CPU time 0.57 seconds
Started Mar 12 12:49:19 PM PDT 24
Finished Mar 12 12:49:20 PM PDT 24
Peak memory 182808 kb
Host smart-6f94ea81-80e1-4ccb-92b7-95c96500aa17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299547362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1299547362
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.191236188
Short name T83
Test name
Test status
Simulation time 49075444 ps
CPU time 0.85 seconds
Started Mar 12 12:49:14 PM PDT 24
Finished Mar 12 12:49:15 PM PDT 24
Peak memory 192228 kb
Host smart-dc207876-4a31-4b0d-88f1-585390600a8d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191236188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias
ing.191236188
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.333910257
Short name T76
Test name
Test status
Simulation time 370871294 ps
CPU time 3.61 seconds
Started Mar 12 12:49:16 PM PDT 24
Finished Mar 12 12:49:19 PM PDT 24
Peak memory 192864 kb
Host smart-c63c2133-7eea-4564-bafb-424577628b62
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333910257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.333910257
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3663942678
Short name T496
Test name
Test status
Simulation time 36275399 ps
CPU time 0.6 seconds
Started Mar 12 12:49:16 PM PDT 24
Finished Mar 12 12:49:17 PM PDT 24
Peak memory 183012 kb
Host smart-2704f6d6-bd54-42ea-9b58-65a34b7d397e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663942678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3663942678
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2457318509
Short name T526
Test name
Test status
Simulation time 47989872 ps
CPU time 1.27 seconds
Started Mar 12 12:49:04 PM PDT 24
Finished Mar 12 12:49:05 PM PDT 24
Peak memory 197932 kb
Host smart-e417494e-3b95-4d45-8b01-d5076aaf2344
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457318509 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2457318509
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1173797967
Short name T574
Test name
Test status
Simulation time 23943534 ps
CPU time 0.55 seconds
Started Mar 12 12:49:10 PM PDT 24
Finished Mar 12 12:49:11 PM PDT 24
Peak memory 182924 kb
Host smart-eb0d99f4-943a-4bcd-890a-0555dedb531a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173797967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1173797967
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1060738717
Short name T564
Test name
Test status
Simulation time 38121648 ps
CPU time 0.52 seconds
Started Mar 12 12:49:08 PM PDT 24
Finished Mar 12 12:49:09 PM PDT 24
Peak memory 182892 kb
Host smart-6b3c8acc-c47f-4c99-ae92-195cfddbea7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060738717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1060738717
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2652054073
Short name T544
Test name
Test status
Simulation time 32372762 ps
CPU time 0.76 seconds
Started Mar 12 12:49:05 PM PDT 24
Finished Mar 12 12:49:06 PM PDT 24
Peak memory 193380 kb
Host smart-e11bc6cd-4560-4525-a224-1d4455acfb88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652054073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.2652054073
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.4091754582
Short name T458
Test name
Test status
Simulation time 164640616 ps
CPU time 1.16 seconds
Started Mar 12 12:49:07 PM PDT 24
Finished Mar 12 12:49:08 PM PDT 24
Peak memory 197568 kb
Host smart-08805be6-6439-43d5-9a16-89e833430afe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091754582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.4091754582
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2301595753
Short name T563
Test name
Test status
Simulation time 319328756 ps
CPU time 1.05 seconds
Started Mar 12 12:49:10 PM PDT 24
Finished Mar 12 12:49:11 PM PDT 24
Peak memory 195312 kb
Host smart-4fe31514-1964-4af8-9fc8-f3bc68740b0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301595753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2301595753
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2758821887
Short name T547
Test name
Test status
Simulation time 15716286 ps
CPU time 0.55 seconds
Started Mar 12 12:49:17 PM PDT 24
Finished Mar 12 12:49:18 PM PDT 24
Peak memory 182836 kb
Host smart-50704843-9277-485a-9e43-2ed70c4fcfe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758821887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2758821887
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3769031987
Short name T541
Test name
Test status
Simulation time 16683628 ps
CPU time 0.53 seconds
Started Mar 12 12:49:24 PM PDT 24
Finished Mar 12 12:49:26 PM PDT 24
Peak memory 182808 kb
Host smart-e8316fc4-fadd-4afd-847d-b4fc6f6b2cf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769031987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3769031987
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2052722034
Short name T506
Test name
Test status
Simulation time 38361854 ps
CPU time 0.52 seconds
Started Mar 12 12:49:25 PM PDT 24
Finished Mar 12 12:49:26 PM PDT 24
Peak memory 182468 kb
Host smart-24889bbc-bc9e-460a-9280-be893c4545ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052722034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.2052722034
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.324628868
Short name T539
Test name
Test status
Simulation time 17569690 ps
CPU time 0.53 seconds
Started Mar 12 12:49:25 PM PDT 24
Finished Mar 12 12:49:27 PM PDT 24
Peak memory 182756 kb
Host smart-ecd0e74a-45c1-4739-b50c-bb3cd3bc0757
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324628868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.324628868
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.975611665
Short name T578
Test name
Test status
Simulation time 87892160 ps
CPU time 0.53 seconds
Started Mar 12 12:49:21 PM PDT 24
Finished Mar 12 12:49:22 PM PDT 24
Peak memory 182876 kb
Host smart-06810147-88a4-44d9-807d-f0bde3b4eec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975611665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.975611665
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2821327767
Short name T462
Test name
Test status
Simulation time 29122756 ps
CPU time 0.58 seconds
Started Mar 12 12:49:20 PM PDT 24
Finished Mar 12 12:49:20 PM PDT 24
Peak memory 182852 kb
Host smart-f2e2e81f-006e-47c9-9c5a-e325af627360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821327767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2821327767
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.4066150170
Short name T470
Test name
Test status
Simulation time 36928444 ps
CPU time 0.54 seconds
Started Mar 12 12:49:22 PM PDT 24
Finished Mar 12 12:49:22 PM PDT 24
Peak memory 182792 kb
Host smart-846aeac2-7047-48ac-86fa-9201e7cac583
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066150170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.4066150170
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.392758378
Short name T516
Test name
Test status
Simulation time 12026420 ps
CPU time 0.59 seconds
Started Mar 12 12:49:25 PM PDT 24
Finished Mar 12 12:49:26 PM PDT 24
Peak memory 182912 kb
Host smart-28849894-49c1-4dfa-b1e1-8fee16b9643e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392758378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.392758378
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2985154775
Short name T571
Test name
Test status
Simulation time 24162767 ps
CPU time 0.54 seconds
Started Mar 12 12:49:26 PM PDT 24
Finished Mar 12 12:49:28 PM PDT 24
Peak memory 182840 kb
Host smart-113c3506-4abe-47e0-836d-31bcc4e8d6a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985154775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2985154775
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3654888086
Short name T474
Test name
Test status
Simulation time 42761906 ps
CPU time 0.53 seconds
Started Mar 12 12:49:24 PM PDT 24
Finished Mar 12 12:49:25 PM PDT 24
Peak memory 182804 kb
Host smart-1d1a54a7-c11e-48ac-813e-67ac97918239
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654888086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3654888086
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2473671305
Short name T74
Test name
Test status
Simulation time 138686858 ps
CPU time 0.7 seconds
Started Mar 12 12:49:13 PM PDT 24
Finished Mar 12 12:49:14 PM PDT 24
Peak memory 192752 kb
Host smart-1a9f0b70-ee3a-4d14-9a3e-e0604e93a47b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473671305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2473671305
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.183246937
Short name T477
Test name
Test status
Simulation time 249475914 ps
CPU time 2.8 seconds
Started Mar 12 12:49:14 PM PDT 24
Finished Mar 12 12:49:18 PM PDT 24
Peak memory 193964 kb
Host smart-43fa4b8d-b19e-4980-9097-45ddea60629a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183246937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_b
ash.183246937
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.669569039
Short name T498
Test name
Test status
Simulation time 14702692 ps
CPU time 0.55 seconds
Started Mar 12 12:49:03 PM PDT 24
Finished Mar 12 12:49:04 PM PDT 24
Peak memory 183052 kb
Host smart-df44a1b4-1371-4091-8167-932418499b52
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669569039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re
set.669569039
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1566050770
Short name T514
Test name
Test status
Simulation time 31814357 ps
CPU time 0.8 seconds
Started Mar 12 12:49:20 PM PDT 24
Finished Mar 12 12:49:21 PM PDT 24
Peak memory 196008 kb
Host smart-3c8c9605-6206-4f5d-82c5-8d2f7c67d132
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566050770 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1566050770
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2923232949
Short name T73
Test name
Test status
Simulation time 42777756 ps
CPU time 0.59 seconds
Started Mar 12 12:49:15 PM PDT 24
Finished Mar 12 12:49:16 PM PDT 24
Peak memory 183036 kb
Host smart-6f13c8b1-d7e8-44b3-922b-e3a45d42b23f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923232949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2923232949
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.721944454
Short name T554
Test name
Test status
Simulation time 48100156 ps
CPU time 0.55 seconds
Started Mar 12 12:49:09 PM PDT 24
Finished Mar 12 12:49:10 PM PDT 24
Peak memory 182072 kb
Host smart-1bb48e79-7de5-4b00-858b-63b1d0625ce9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721944454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.721944454
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.557825796
Short name T520
Test name
Test status
Simulation time 53873136 ps
CPU time 0.77 seconds
Started Mar 12 12:49:17 PM PDT 24
Finished Mar 12 12:49:18 PM PDT 24
Peak memory 193484 kb
Host smart-a9195499-9943-4ab3-b27f-8e04a1c6d0a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557825796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.557825796
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1087464219
Short name T484
Test name
Test status
Simulation time 75751221 ps
CPU time 1.58 seconds
Started Mar 12 12:49:04 PM PDT 24
Finished Mar 12 12:49:06 PM PDT 24
Peak memory 197864 kb
Host smart-496a792a-1e28-4222-a89e-846d4b8ec40d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087464219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1087464219
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2433667459
Short name T500
Test name
Test status
Simulation time 74913819 ps
CPU time 0.81 seconds
Started Mar 12 12:49:18 PM PDT 24
Finished Mar 12 12:49:19 PM PDT 24
Peak memory 183524 kb
Host smart-dbf5e152-0f0c-41da-95ff-8dab81787c1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433667459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2433667459
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3969687962
Short name T570
Test name
Test status
Simulation time 16644498 ps
CPU time 0.56 seconds
Started Mar 12 12:49:20 PM PDT 24
Finished Mar 12 12:49:21 PM PDT 24
Peak memory 182732 kb
Host smart-7de9fe50-c52f-4c50-a508-32e9f4fe4fad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969687962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3969687962
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.616784646
Short name T543
Test name
Test status
Simulation time 18686934 ps
CPU time 0.55 seconds
Started Mar 12 12:49:24 PM PDT 24
Finished Mar 12 12:49:25 PM PDT 24
Peak memory 182872 kb
Host smart-c4076d8a-e85f-4fa0-9fd3-c5f6400c1be2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616784646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.616784646
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2324407492
Short name T461
Test name
Test status
Simulation time 15316905 ps
CPU time 0.56 seconds
Started Mar 12 12:49:19 PM PDT 24
Finished Mar 12 12:49:19 PM PDT 24
Peak memory 182908 kb
Host smart-cac27ff2-326c-4599-9002-aea84f69b433
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324407492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2324407492
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3293257234
Short name T466
Test name
Test status
Simulation time 21919259 ps
CPU time 0.53 seconds
Started Mar 12 12:49:20 PM PDT 24
Finished Mar 12 12:49:20 PM PDT 24
Peak memory 181968 kb
Host smart-2f0fdf19-b473-41a4-a8d0-04a1d80c600b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293257234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3293257234
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3181233398
Short name T454
Test name
Test status
Simulation time 11975586 ps
CPU time 0.57 seconds
Started Mar 12 12:49:20 PM PDT 24
Finished Mar 12 12:49:21 PM PDT 24
Peak memory 182468 kb
Host smart-54d8ffc1-7450-4c4f-866f-84f6f2ab7a68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181233398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3181233398
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1966288324
Short name T479
Test name
Test status
Simulation time 111657751 ps
CPU time 0.55 seconds
Started Mar 12 12:49:21 PM PDT 24
Finished Mar 12 12:49:22 PM PDT 24
Peak memory 182808 kb
Host smart-ffcd6437-bbd3-44cc-8878-6faf57930c5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966288324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1966288324
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1168071531
Short name T451
Test name
Test status
Simulation time 92094750 ps
CPU time 0.52 seconds
Started Mar 12 12:49:24 PM PDT 24
Finished Mar 12 12:49:26 PM PDT 24
Peak memory 182004 kb
Host smart-9a4c5285-7516-44e8-8473-3e13b8733168
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168071531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1168071531
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.640216879
Short name T467
Test name
Test status
Simulation time 11984370 ps
CPU time 0.55 seconds
Started Mar 12 12:49:20 PM PDT 24
Finished Mar 12 12:49:21 PM PDT 24
Peak memory 182788 kb
Host smart-f73c8dbb-b217-44ad-a6aa-a108dbb74e06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640216879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.640216879
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3328939243
Short name T545
Test name
Test status
Simulation time 31471996 ps
CPU time 0.55 seconds
Started Mar 12 12:49:22 PM PDT 24
Finished Mar 12 12:49:23 PM PDT 24
Peak memory 182824 kb
Host smart-b8dc7bc7-6a8b-4add-94b0-3524f7c711a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328939243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3328939243
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1468156672
Short name T452
Test name
Test status
Simulation time 41456178 ps
CPU time 0.51 seconds
Started Mar 12 12:49:19 PM PDT 24
Finished Mar 12 12:49:20 PM PDT 24
Peak memory 182060 kb
Host smart-fc27f5ce-02f1-4445-a718-7de87b546fa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468156672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1468156672
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1447272000
Short name T542
Test name
Test status
Simulation time 60973967 ps
CPU time 0.87 seconds
Started Mar 12 12:49:09 PM PDT 24
Finished Mar 12 12:49:10 PM PDT 24
Peak memory 196660 kb
Host smart-7aa6d0f8-781b-4184-8133-45b769e06d08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447272000 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1447272000
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.22689291
Short name T81
Test name
Test status
Simulation time 27105704 ps
CPU time 0.58 seconds
Started Mar 12 12:49:10 PM PDT 24
Finished Mar 12 12:49:12 PM PDT 24
Peak memory 183044 kb
Host smart-281b6462-fe01-4977-af88-02e689e755a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22689291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.22689291
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.4212437238
Short name T536
Test name
Test status
Simulation time 24188882 ps
CPU time 0.54 seconds
Started Mar 12 12:49:15 PM PDT 24
Finished Mar 12 12:49:16 PM PDT 24
Peak memory 182028 kb
Host smart-62f95599-bfc6-4dca-b75b-f1e37b22d570
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212437238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.4212437238
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1606061102
Short name T550
Test name
Test status
Simulation time 34007113 ps
CPU time 0.59 seconds
Started Mar 12 12:49:12 PM PDT 24
Finished Mar 12 12:49:13 PM PDT 24
Peak memory 191552 kb
Host smart-2b7ce169-4f27-46f3-93d7-9c2f3054bdac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606061102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1606061102
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2798243879
Short name T493
Test name
Test status
Simulation time 45121644 ps
CPU time 1.02 seconds
Started Mar 12 12:49:13 PM PDT 24
Finished Mar 12 12:49:14 PM PDT 24
Peak memory 191560 kb
Host smart-d96f1bac-3651-4ebf-b68f-7cc175f35244
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798243879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2798243879
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1058864360
Short name T92
Test name
Test status
Simulation time 711723348 ps
CPU time 1.28 seconds
Started Mar 12 12:49:10 PM PDT 24
Finished Mar 12 12:49:12 PM PDT 24
Peak memory 195364 kb
Host smart-2ab4348a-ed4a-4903-a134-b4629abe9e52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058864360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1058864360
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2551894127
Short name T50
Test name
Test status
Simulation time 22271699 ps
CPU time 0.66 seconds
Started Mar 12 12:49:14 PM PDT 24
Finished Mar 12 12:49:15 PM PDT 24
Peak memory 194412 kb
Host smart-659d43ed-31f1-47b1-ac8e-b5dfe8f5ef07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551894127 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2551894127
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.798808057
Short name T501
Test name
Test status
Simulation time 15770141 ps
CPU time 0.55 seconds
Started Mar 12 12:49:12 PM PDT 24
Finished Mar 12 12:49:12 PM PDT 24
Peak memory 182612 kb
Host smart-80d774f4-673d-4dd4-9539-422483d8e046
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798808057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.798808057
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3761046088
Short name T497
Test name
Test status
Simulation time 38886997 ps
CPU time 0.5 seconds
Started Mar 12 12:49:18 PM PDT 24
Finished Mar 12 12:49:19 PM PDT 24
Peak memory 182036 kb
Host smart-d0c3f556-25f2-49e5-9b53-10358e70470b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761046088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3761046088
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1747969190
Short name T572
Test name
Test status
Simulation time 20703964 ps
CPU time 0.73 seconds
Started Mar 12 12:49:10 PM PDT 24
Finished Mar 12 12:49:12 PM PDT 24
Peak memory 193360 kb
Host smart-707ff655-81a5-4db4-8135-170b46e0eedf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747969190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1747969190
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1767301380
Short name T459
Test name
Test status
Simulation time 141831297 ps
CPU time 1.48 seconds
Started Mar 12 12:49:12 PM PDT 24
Finished Mar 12 12:49:14 PM PDT 24
Peak memory 197884 kb
Host smart-78410bdf-70f0-4dac-bdaf-1c1c630a5fdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767301380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1767301380
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.703547029
Short name T534
Test name
Test status
Simulation time 45225987 ps
CPU time 0.84 seconds
Started Mar 12 12:49:15 PM PDT 24
Finished Mar 12 12:49:16 PM PDT 24
Peak memory 193780 kb
Host smart-85f3d1ed-6dfd-482d-8a47-2e12f570553d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703547029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.703547029
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3569417070
Short name T504
Test name
Test status
Simulation time 30839145 ps
CPU time 0.78 seconds
Started Mar 12 12:49:10 PM PDT 24
Finished Mar 12 12:49:11 PM PDT 24
Peak memory 195880 kb
Host smart-cddb2581-779e-4f50-b638-9c843c7c86a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569417070 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3569417070
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3378226387
Short name T69
Test name
Test status
Simulation time 54102148 ps
CPU time 0.6 seconds
Started Mar 12 12:49:17 PM PDT 24
Finished Mar 12 12:49:18 PM PDT 24
Peak memory 183060 kb
Host smart-87fb3453-f4d5-4f83-a805-e1da83df3115
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378226387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3378226387
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3064493021
Short name T502
Test name
Test status
Simulation time 14454506 ps
CPU time 0.52 seconds
Started Mar 12 12:49:12 PM PDT 24
Finished Mar 12 12:49:12 PM PDT 24
Peak memory 182468 kb
Host smart-235e431e-a2a6-46c5-9dc3-33be2542631c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064493021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3064493021
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1204206563
Short name T87
Test name
Test status
Simulation time 12515518 ps
CPU time 0.59 seconds
Started Mar 12 12:49:14 PM PDT 24
Finished Mar 12 12:49:16 PM PDT 24
Peak memory 191600 kb
Host smart-6d290665-1afc-4a31-8329-5ddfb0cc525a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204206563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1204206563
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2381165108
Short name T460
Test name
Test status
Simulation time 823273502 ps
CPU time 2.98 seconds
Started Mar 12 12:49:12 PM PDT 24
Finished Mar 12 12:49:15 PM PDT 24
Peak memory 197912 kb
Host smart-50ad48ed-739e-45e3-8a8a-dcc5c27e36b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381165108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2381165108
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.806322779
Short name T492
Test name
Test status
Simulation time 42015573 ps
CPU time 0.88 seconds
Started Mar 12 12:49:09 PM PDT 24
Finished Mar 12 12:49:11 PM PDT 24
Peak memory 183528 kb
Host smart-5b883176-a4dc-4f07-8f37-f3e4657ef119
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806322779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int
g_err.806322779
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.4106675309
Short name T573
Test name
Test status
Simulation time 30304495 ps
CPU time 0.8 seconds
Started Mar 12 12:49:12 PM PDT 24
Finished Mar 12 12:49:13 PM PDT 24
Peak memory 196136 kb
Host smart-bc3826bc-ad2e-4489-89b6-171227db2720
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106675309 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.4106675309
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1087691316
Short name T80
Test name
Test status
Simulation time 12575944 ps
CPU time 0.6 seconds
Started Mar 12 12:49:15 PM PDT 24
Finished Mar 12 12:49:16 PM PDT 24
Peak memory 183036 kb
Host smart-aab66c3e-f0dd-4fc5-9bc2-b368f54dc96f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087691316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1087691316
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3767580596
Short name T472
Test name
Test status
Simulation time 14919933 ps
CPU time 0.57 seconds
Started Mar 12 12:49:16 PM PDT 24
Finished Mar 12 12:49:17 PM PDT 24
Peak memory 182764 kb
Host smart-f426168f-822b-435d-8362-9f6f7d6f61e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767580596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3767580596
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2823537809
Short name T88
Test name
Test status
Simulation time 204701377 ps
CPU time 0.65 seconds
Started Mar 12 12:49:17 PM PDT 24
Finished Mar 12 12:49:18 PM PDT 24
Peak memory 192308 kb
Host smart-9be03d81-bee4-4c8f-ba72-a491e2d5033b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823537809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2823537809
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2213220132
Short name T529
Test name
Test status
Simulation time 83991728 ps
CPU time 1.77 seconds
Started Mar 12 12:49:12 PM PDT 24
Finished Mar 12 12:49:14 PM PDT 24
Peak memory 197924 kb
Host smart-a20f9608-0b46-4d9f-b54b-80df8348744d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213220132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2213220132
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3306167130
Short name T521
Test name
Test status
Simulation time 77869017 ps
CPU time 1.12 seconds
Started Mar 12 12:49:13 PM PDT 24
Finished Mar 12 12:49:15 PM PDT 24
Peak memory 195320 kb
Host smart-31c5f9fb-0203-4660-b35f-d22ee17a430f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306167130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.3306167130
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3464623098
Short name T558
Test name
Test status
Simulation time 28150997 ps
CPU time 1.24 seconds
Started Mar 12 12:49:11 PM PDT 24
Finished Mar 12 12:49:13 PM PDT 24
Peak memory 197904 kb
Host smart-fe206a5d-0be4-49ad-82ef-d7fc8da5663b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464623098 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3464623098
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2074186175
Short name T490
Test name
Test status
Simulation time 245687021 ps
CPU time 0.58 seconds
Started Mar 12 12:49:20 PM PDT 24
Finished Mar 12 12:49:21 PM PDT 24
Peak memory 183024 kb
Host smart-14aeff7c-c4db-4379-b08a-d6b792a5fdbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074186175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2074186175
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1800956743
Short name T464
Test name
Test status
Simulation time 13784770 ps
CPU time 0.52 seconds
Started Mar 12 12:49:15 PM PDT 24
Finished Mar 12 12:49:16 PM PDT 24
Peak memory 181992 kb
Host smart-0fea167b-a091-4979-8595-6614c58845d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800956743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1800956743
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.134092567
Short name T91
Test name
Test status
Simulation time 58047753 ps
CPU time 0.7 seconds
Started Mar 12 12:49:14 PM PDT 24
Finished Mar 12 12:49:16 PM PDT 24
Peak memory 193352 kb
Host smart-656786ec-c281-4520-9933-a041a8135cc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134092567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_tim
er_same_csr_outstanding.134092567
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3762052914
Short name T463
Test name
Test status
Simulation time 227351252 ps
CPU time 1.96 seconds
Started Mar 12 12:49:12 PM PDT 24
Finished Mar 12 12:49:14 PM PDT 24
Peak memory 197920 kb
Host smart-38816e46-f59c-4bcf-aad0-855d1c9c4ca6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762052914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3762052914
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1817420142
Short name T469
Test name
Test status
Simulation time 138100842 ps
CPU time 0.83 seconds
Started Mar 12 12:49:15 PM PDT 24
Finished Mar 12 12:49:16 PM PDT 24
Peak memory 193836 kb
Host smart-880c288b-b667-4c67-aaf6-2d52188f0440
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817420142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1817420142
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2695491052
Short name T396
Test name
Test status
Simulation time 115650165331 ps
CPU time 84.42 seconds
Started Mar 12 12:31:10 PM PDT 24
Finished Mar 12 12:32:34 PM PDT 24
Peak memory 183212 kb
Host smart-258c34bf-f4ee-41a0-9f24-ac2fc55ef3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695491052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2695491052
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.2308851653
Short name T62
Test name
Test status
Simulation time 123473577397 ps
CPU time 1326.04 seconds
Started Mar 12 12:31:12 PM PDT 24
Finished Mar 12 12:53:19 PM PDT 24
Peak memory 191412 kb
Host smart-6641834c-4397-46b5-8239-29593cc04b50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308851653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2308851653
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.217217865
Short name T188
Test name
Test status
Simulation time 2202483745779 ps
CPU time 2721.28 seconds
Started Mar 12 12:31:17 PM PDT 24
Finished Mar 12 01:16:39 PM PDT 24
Peak memory 196172 kb
Host smart-d2f21755-7887-40ba-ba97-c0ef676b83e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217217865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.217217865
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2184266741
Short name T103
Test name
Test status
Simulation time 32943991551 ps
CPU time 56.02 seconds
Started Mar 12 12:31:11 PM PDT 24
Finished Mar 12 12:32:07 PM PDT 24
Peak memory 183272 kb
Host smart-f38e06ea-8d8c-4fb5-a83e-96e27ca929f1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184266741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2184266741
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3353485341
Short name T60
Test name
Test status
Simulation time 718112624216 ps
CPU time 281.13 seconds
Started Mar 12 12:31:10 PM PDT 24
Finished Mar 12 12:35:51 PM PDT 24
Peak memory 183256 kb
Host smart-84d5fa31-5e7f-4e36-9502-d39ffa41a93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353485341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3353485341
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.104835119
Short name T186
Test name
Test status
Simulation time 95214198593 ps
CPU time 267.03 seconds
Started Mar 12 12:31:00 PM PDT 24
Finished Mar 12 12:35:27 PM PDT 24
Peak memory 195268 kb
Host smart-4d0c84a4-0350-43e6-b479-796ff5fcc4be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104835119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.104835119
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3533450844
Short name T344
Test name
Test status
Simulation time 177311384296 ps
CPU time 58.9 seconds
Started Mar 12 12:31:13 PM PDT 24
Finished Mar 12 12:32:12 PM PDT 24
Peak memory 192784 kb
Host smart-ba5a00d2-b85e-46a3-a25c-0efa344fb212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533450844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3533450844
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2576531962
Short name T14
Test name
Test status
Simulation time 37385172 ps
CPU time 0.74 seconds
Started Mar 12 12:31:10 PM PDT 24
Finished Mar 12 12:31:11 PM PDT 24
Peak memory 213544 kb
Host smart-2f414116-c2ac-4b3b-b99c-73d7b2c0a95a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576531962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2576531962
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.1307429793
Short name T256
Test name
Test status
Simulation time 487158951887 ps
CPU time 876.27 seconds
Started Mar 12 12:31:29 PM PDT 24
Finished Mar 12 12:46:05 PM PDT 24
Peak memory 183320 kb
Host smart-0956923a-7850-4fb6-b489-da3dd13ed6e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307429793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.1307429793
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3924903095
Short name T411
Test name
Test status
Simulation time 55457645238 ps
CPU time 19.19 seconds
Started Mar 12 12:31:17 PM PDT 24
Finished Mar 12 12:31:37 PM PDT 24
Peak memory 183256 kb
Host smart-1121b57d-328f-489f-9104-4a3560e73403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924903095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3924903095
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.3618112357
Short name T8
Test name
Test status
Simulation time 493932532520 ps
CPU time 452.41 seconds
Started Mar 12 12:31:17 PM PDT 24
Finished Mar 12 12:38:50 PM PDT 24
Peak memory 191588 kb
Host smart-9891eb71-af98-49b3-98cc-f1b2def72cf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618112357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3618112357
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/100.rv_timer_random.423745495
Short name T343
Test name
Test status
Simulation time 34912394491 ps
CPU time 28.59 seconds
Started Mar 12 12:31:44 PM PDT 24
Finished Mar 12 12:32:14 PM PDT 24
Peak memory 183308 kb
Host smart-5038ce10-2252-44e0-8214-a04f5a42f126
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423745495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.423745495
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.3349911359
Short name T435
Test name
Test status
Simulation time 489335467195 ps
CPU time 184.28 seconds
Started Mar 12 12:32:01 PM PDT 24
Finished Mar 12 12:35:06 PM PDT 24
Peak memory 191512 kb
Host smart-327638d3-6d39-4cd8-8d4d-83a8e62549e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349911359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3349911359
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.200487373
Short name T315
Test name
Test status
Simulation time 164852188926 ps
CPU time 82.55 seconds
Started Mar 12 12:32:00 PM PDT 24
Finished Mar 12 12:33:22 PM PDT 24
Peak memory 183312 kb
Host smart-29dad7f8-1a67-4418-8904-6330de1225af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200487373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.200487373
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.2390864809
Short name T282
Test name
Test status
Simulation time 68352920271 ps
CPU time 131 seconds
Started Mar 12 12:31:42 PM PDT 24
Finished Mar 12 12:33:56 PM PDT 24
Peak memory 191596 kb
Host smart-dd752375-3062-413f-a266-2b9b253c2a4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390864809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2390864809
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2498074548
Short name T65
Test name
Test status
Simulation time 169347135928 ps
CPU time 1031.19 seconds
Started Mar 12 12:31:52 PM PDT 24
Finished Mar 12 12:49:03 PM PDT 24
Peak memory 193960 kb
Host smart-a73a3338-2a6c-462d-acee-97f67b12eb27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498074548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2498074548
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.3322366564
Short name T424
Test name
Test status
Simulation time 306295813287 ps
CPU time 1343.04 seconds
Started Mar 12 12:31:53 PM PDT 24
Finished Mar 12 12:54:16 PM PDT 24
Peak memory 191540 kb
Host smart-97929e56-f577-4b42-b05a-68bcc4e20229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322366564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3322366564
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.3663170050
Short name T247
Test name
Test status
Simulation time 301441837996 ps
CPU time 272.35 seconds
Started Mar 12 12:31:44 PM PDT 24
Finished Mar 12 12:36:17 PM PDT 24
Peak memory 194164 kb
Host smart-43aa121b-fc27-467f-9251-53413782dd53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663170050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3663170050
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.3909509727
Short name T442
Test name
Test status
Simulation time 67769357124 ps
CPU time 111.78 seconds
Started Mar 12 12:31:54 PM PDT 24
Finished Mar 12 12:33:46 PM PDT 24
Peak memory 193516 kb
Host smart-46f87ef0-41d9-44ba-bcf0-46eedc3d2a03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909509727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3909509727
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.1789508237
Short name T348
Test name
Test status
Simulation time 750380313604 ps
CPU time 692.45 seconds
Started Mar 12 12:31:28 PM PDT 24
Finished Mar 12 12:43:00 PM PDT 24
Peak memory 183368 kb
Host smart-27415c51-6216-4936-a0c9-b445473e6f32
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789508237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.1789508237
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.3220062069
Short name T357
Test name
Test status
Simulation time 92989779474 ps
CPU time 69.78 seconds
Started Mar 12 12:31:24 PM PDT 24
Finished Mar 12 12:32:34 PM PDT 24
Peak memory 183264 kb
Host smart-0a99b7d3-bbf4-490a-b415-09bdf9fda4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220062069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.3220062069
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.1487951980
Short name T270
Test name
Test status
Simulation time 1337027427510 ps
CPU time 324.41 seconds
Started Mar 12 12:31:14 PM PDT 24
Finished Mar 12 12:36:38 PM PDT 24
Peak memory 191540 kb
Host smart-569302f1-caf6-4af1-bf9b-31fe82779085
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487951980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1487951980
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.662823161
Short name T273
Test name
Test status
Simulation time 348928322919 ps
CPU time 171.09 seconds
Started Mar 12 12:31:17 PM PDT 24
Finished Mar 12 12:34:09 PM PDT 24
Peak memory 191500 kb
Host smart-6a43533a-f86d-4169-b5c9-b909554e120c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662823161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.662823161
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.2336485930
Short name T205
Test name
Test status
Simulation time 222628853956 ps
CPU time 189.78 seconds
Started Mar 12 12:31:21 PM PDT 24
Finished Mar 12 12:34:31 PM PDT 24
Peak memory 191532 kb
Host smart-83a62829-b19a-464b-8520-cec82b1b6a8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336485930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.2336485930
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/110.rv_timer_random.1241842460
Short name T228
Test name
Test status
Simulation time 421510249803 ps
CPU time 303.7 seconds
Started Mar 12 12:31:54 PM PDT 24
Finished Mar 12 12:36:58 PM PDT 24
Peak memory 191472 kb
Host smart-ab197142-cb12-4b2f-89a6-6e362cb78cb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241842460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1241842460
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.827119927
Short name T399
Test name
Test status
Simulation time 66050075603 ps
CPU time 68.16 seconds
Started Mar 12 12:31:54 PM PDT 24
Finished Mar 12 12:33:02 PM PDT 24
Peak memory 191508 kb
Host smart-fd0cb396-d71e-40da-91ba-34775d341065
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827119927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.827119927
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.1360964517
Short name T248
Test name
Test status
Simulation time 115300171367 ps
CPU time 1163.25 seconds
Started Mar 12 12:31:57 PM PDT 24
Finished Mar 12 12:51:21 PM PDT 24
Peak memory 191508 kb
Host smart-21641b26-c248-4671-9ec4-d4a79a3876f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360964517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1360964517
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.2092377065
Short name T417
Test name
Test status
Simulation time 31880596498 ps
CPU time 57.69 seconds
Started Mar 12 12:31:39 PM PDT 24
Finished Mar 12 12:32:36 PM PDT 24
Peak memory 191636 kb
Host smart-1ab679ba-bced-4018-9ae2-38813dd837a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092377065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2092377065
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.2120837580
Short name T44
Test name
Test status
Simulation time 467572541703 ps
CPU time 432.24 seconds
Started Mar 12 12:32:03 PM PDT 24
Finished Mar 12 12:39:16 PM PDT 24
Peak memory 194624 kb
Host smart-4ccfe13b-4c81-4781-ac0c-786c03cde9c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120837580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2120837580
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.934165057
Short name T324
Test name
Test status
Simulation time 184530130365 ps
CPU time 161.54 seconds
Started Mar 12 12:31:48 PM PDT 24
Finished Mar 12 12:34:29 PM PDT 24
Peak memory 191644 kb
Host smart-c3ba9b71-b3db-4ada-b50f-55a13f45721b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934165057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.934165057
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.1075358623
Short name T174
Test name
Test status
Simulation time 47746632447 ps
CPU time 45.81 seconds
Started Mar 12 12:31:50 PM PDT 24
Finished Mar 12 12:32:36 PM PDT 24
Peak memory 191600 kb
Host smart-50798276-31da-45e9-ad73-7e60bace885b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075358623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1075358623
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.57433691
Short name T192
Test name
Test status
Simulation time 826747485866 ps
CPU time 1459.01 seconds
Started Mar 12 12:31:57 PM PDT 24
Finished Mar 12 12:56:16 PM PDT 24
Peak memory 191516 kb
Host smart-7911a28f-7edc-4305-9af3-8c4bebfef2c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57433691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.57433691
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.876394138
Short name T225
Test name
Test status
Simulation time 10989870296 ps
CPU time 10.78 seconds
Started Mar 12 12:31:15 PM PDT 24
Finished Mar 12 12:31:26 PM PDT 24
Peak memory 183296 kb
Host smart-2b8d7b8b-614b-4a91-89ce-e817d87ad21b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876394138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.rv_timer_cfg_update_on_fly.876394138
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3645571983
Short name T392
Test name
Test status
Simulation time 37442563291 ps
CPU time 28.97 seconds
Started Mar 12 12:31:11 PM PDT 24
Finished Mar 12 12:31:40 PM PDT 24
Peak memory 183316 kb
Host smart-a3f6c654-cdc3-4168-8017-832cc001b18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645571983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3645571983
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1485296047
Short name T410
Test name
Test status
Simulation time 73776219466 ps
CPU time 136.66 seconds
Started Mar 12 12:31:22 PM PDT 24
Finished Mar 12 12:33:39 PM PDT 24
Peak memory 183424 kb
Host smart-3b1fdf74-97eb-458e-badf-a3d4acd5c25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485296047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1485296047
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.3200238449
Short name T211
Test name
Test status
Simulation time 3728740265 ps
CPU time 6.82 seconds
Started Mar 12 12:31:47 PM PDT 24
Finished Mar 12 12:31:54 PM PDT 24
Peak memory 183316 kb
Host smart-1935bc80-8091-40f1-ad20-0df810fbe7dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200238449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3200238449
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.183485744
Short name T230
Test name
Test status
Simulation time 568913288352 ps
CPU time 274.72 seconds
Started Mar 12 12:31:45 PM PDT 24
Finished Mar 12 12:36:20 PM PDT 24
Peak memory 193652 kb
Host smart-dacf9807-3fcc-4ba5-9b43-9827f67add07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183485744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.183485744
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.788331101
Short name T115
Test name
Test status
Simulation time 218276278411 ps
CPU time 108.1 seconds
Started Mar 12 12:31:55 PM PDT 24
Finished Mar 12 12:33:44 PM PDT 24
Peak memory 191500 kb
Host smart-17f117bf-cace-4c26-b334-0328fe1616ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788331101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.788331101
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.2389960713
Short name T234
Test name
Test status
Simulation time 109436849903 ps
CPU time 233.14 seconds
Started Mar 12 12:31:54 PM PDT 24
Finished Mar 12 12:35:47 PM PDT 24
Peak memory 191508 kb
Host smart-75fbf65b-b484-426a-8f0c-e18e4528e913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389960713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2389960713
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2890739514
Short name T445
Test name
Test status
Simulation time 59109745927 ps
CPU time 154.27 seconds
Started Mar 12 12:31:58 PM PDT 24
Finished Mar 12 12:34:32 PM PDT 24
Peak memory 191472 kb
Host smart-a245de4c-f979-4fbc-b9c7-0652849130c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890739514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2890739514
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.4084683458
Short name T309
Test name
Test status
Simulation time 136678597848 ps
CPU time 107.23 seconds
Started Mar 12 12:31:57 PM PDT 24
Finished Mar 12 12:33:44 PM PDT 24
Peak memory 191440 kb
Host smart-d3b1036c-5d00-4c32-90b4-e1d56ef5e022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084683458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.4084683458
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3036608184
Short name T24
Test name
Test status
Simulation time 111908613752 ps
CPU time 189.57 seconds
Started Mar 12 12:31:24 PM PDT 24
Finished Mar 12 12:34:34 PM PDT 24
Peak memory 183316 kb
Host smart-e4068997-b1f3-4242-a067-a0d42044e78d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036608184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.3036608184
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.3553127079
Short name T437
Test name
Test status
Simulation time 63044326483 ps
CPU time 96.21 seconds
Started Mar 12 12:31:17 PM PDT 24
Finished Mar 12 12:32:54 PM PDT 24
Peak memory 183264 kb
Host smart-4a82f20a-da3a-46a1-8dcc-b3f3469f2781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553127079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3553127079
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.1403149718
Short name T313
Test name
Test status
Simulation time 143216188963 ps
CPU time 138.61 seconds
Started Mar 12 12:31:15 PM PDT 24
Finished Mar 12 12:33:33 PM PDT 24
Peak memory 191556 kb
Host smart-f05410ad-35a4-4fee-bc3f-3efbadace344
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403149718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.1403149718
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3404660787
Short name T405
Test name
Test status
Simulation time 43041581229 ps
CPU time 65.59 seconds
Started Mar 12 12:31:16 PM PDT 24
Finished Mar 12 12:32:22 PM PDT 24
Peak memory 183120 kb
Host smart-51888057-d985-4f77-8a4f-ab6784684c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404660787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3404660787
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.1804428947
Short name T347
Test name
Test status
Simulation time 945388862793 ps
CPU time 374.99 seconds
Started Mar 12 12:31:19 PM PDT 24
Finished Mar 12 12:37:35 PM PDT 24
Peak memory 191580 kb
Host smart-e2cf7033-e4b6-4253-8db6-bf99f4a6c094
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804428947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.1804428947
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.2637853485
Short name T233
Test name
Test status
Simulation time 345881617563 ps
CPU time 129.85 seconds
Started Mar 12 12:31:53 PM PDT 24
Finished Mar 12 12:34:03 PM PDT 24
Peak memory 191512 kb
Host smart-06f719bf-8ee3-4d6e-af3c-16c2936869ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637853485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2637853485
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.206145399
Short name T280
Test name
Test status
Simulation time 298387653301 ps
CPU time 1058.96 seconds
Started Mar 12 12:31:59 PM PDT 24
Finished Mar 12 12:49:38 PM PDT 24
Peak memory 191652 kb
Host smart-b8630213-13a2-4e9b-95af-4163fbd3b082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206145399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.206145399
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.3513420503
Short name T263
Test name
Test status
Simulation time 630114465361 ps
CPU time 462.96 seconds
Started Mar 12 12:31:52 PM PDT 24
Finished Mar 12 12:39:35 PM PDT 24
Peak memory 191448 kb
Host smart-75c12954-e31d-4bf9-bbd1-b5b38fcf0b90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513420503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3513420503
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.972698599
Short name T330
Test name
Test status
Simulation time 176528861947 ps
CPU time 309.16 seconds
Started Mar 12 12:31:58 PM PDT 24
Finished Mar 12 12:37:07 PM PDT 24
Peak memory 191428 kb
Host smart-4ffa4e37-18b1-4eff-8f58-39e1332630cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972698599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.972698599
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.632254742
Short name T434
Test name
Test status
Simulation time 124468733168 ps
CPU time 123.18 seconds
Started Mar 12 12:31:50 PM PDT 24
Finished Mar 12 12:33:53 PM PDT 24
Peak memory 192308 kb
Host smart-4c918622-525e-45d9-a9e7-647a30b5d174
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632254742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.632254742
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2127589697
Short name T260
Test name
Test status
Simulation time 141165336992 ps
CPU time 390.48 seconds
Started Mar 12 12:31:59 PM PDT 24
Finished Mar 12 12:38:29 PM PDT 24
Peak memory 191532 kb
Host smart-071ae9ef-c44e-4aa1-80b5-d4f5607232df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127589697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2127589697
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2460058306
Short name T373
Test name
Test status
Simulation time 669646272580 ps
CPU time 296.24 seconds
Started Mar 12 12:31:15 PM PDT 24
Finished Mar 12 12:36:11 PM PDT 24
Peak memory 183256 kb
Host smart-434b0d2a-3bd9-4b61-84b1-5a5ef4c5a585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460058306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2460058306
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.2646133650
Short name T173
Test name
Test status
Simulation time 2590010377767 ps
CPU time 495.25 seconds
Started Mar 12 12:31:14 PM PDT 24
Finished Mar 12 12:39:29 PM PDT 24
Peak memory 191436 kb
Host smart-d06267af-94fe-400a-bd7a-a9d76b278424
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646133650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2646133650
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.2772432438
Short name T219
Test name
Test status
Simulation time 185575521338 ps
CPU time 868.32 seconds
Started Mar 12 12:31:25 PM PDT 24
Finished Mar 12 12:45:53 PM PDT 24
Peak memory 183236 kb
Host smart-286195bb-7a13-4abd-938a-96a72f753490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772432438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2772432438
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/141.rv_timer_random.4188259081
Short name T359
Test name
Test status
Simulation time 2349411321 ps
CPU time 4.29 seconds
Started Mar 12 12:31:54 PM PDT 24
Finished Mar 12 12:31:58 PM PDT 24
Peak memory 183400 kb
Host smart-a64fb047-07db-4d4b-8cdc-ce88d587be4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188259081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.4188259081
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1221304263
Short name T208
Test name
Test status
Simulation time 239674932605 ps
CPU time 171.9 seconds
Started Mar 12 12:32:03 PM PDT 24
Finished Mar 12 12:34:55 PM PDT 24
Peak memory 191196 kb
Host smart-52a881cb-5892-41df-821c-12c3aa077bb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221304263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1221304263
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1946286499
Short name T265
Test name
Test status
Simulation time 200792168569 ps
CPU time 98.09 seconds
Started Mar 12 12:32:00 PM PDT 24
Finished Mar 12 12:33:38 PM PDT 24
Peak memory 183344 kb
Host smart-f773feec-e9c8-40cd-a57e-179e3e1a40c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946286499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1946286499
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3699163575
Short name T386
Test name
Test status
Simulation time 61060894636 ps
CPU time 260.98 seconds
Started Mar 12 12:31:58 PM PDT 24
Finished Mar 12 12:36:19 PM PDT 24
Peak memory 191524 kb
Host smart-d77e6e77-8764-42b5-b339-d5f44e058253
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699163575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3699163575
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3165348159
Short name T206
Test name
Test status
Simulation time 716561702479 ps
CPU time 2116.84 seconds
Started Mar 12 12:32:05 PM PDT 24
Finished Mar 12 01:07:23 PM PDT 24
Peak memory 191456 kb
Host smart-4051fa1b-00ab-475a-842d-fa01d1355e64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165348159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3165348159
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2218313956
Short name T127
Test name
Test status
Simulation time 881639095466 ps
CPU time 849.89 seconds
Started Mar 12 12:31:53 PM PDT 24
Finished Mar 12 12:46:03 PM PDT 24
Peak memory 193744 kb
Host smart-72d1bb5a-49ea-401d-a788-bf4e98933106
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218313956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2218313956
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.903981189
Short name T41
Test name
Test status
Simulation time 376199687686 ps
CPU time 197.13 seconds
Started Mar 12 12:31:26 PM PDT 24
Finished Mar 12 12:34:44 PM PDT 24
Peak memory 183276 kb
Host smart-9e27a9d1-55c8-4d2b-a00c-4774a48a9591
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903981189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.rv_timer_cfg_update_on_fly.903981189
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.157818994
Short name T416
Test name
Test status
Simulation time 139010735891 ps
CPU time 233.18 seconds
Started Mar 12 12:31:29 PM PDT 24
Finished Mar 12 12:35:23 PM PDT 24
Peak memory 183236 kb
Host smart-fb8c4642-4ac6-4087-baa1-44f4886b8b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157818994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.157818994
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.698245969
Short name T187
Test name
Test status
Simulation time 103128872646 ps
CPU time 424.98 seconds
Started Mar 12 12:31:11 PM PDT 24
Finished Mar 12 12:38:16 PM PDT 24
Peak memory 191440 kb
Host smart-ae426fa6-a6a7-44a1-8cc1-6dca7c0462ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698245969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.698245969
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2567385185
Short name T331
Test name
Test status
Simulation time 69300729994 ps
CPU time 124.08 seconds
Started Mar 12 12:31:28 PM PDT 24
Finished Mar 12 12:33:33 PM PDT 24
Peak memory 183264 kb
Host smart-2db61ddb-047a-439f-91c5-82dda73ae332
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567385185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2567385185
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.4170387421
Short name T294
Test name
Test status
Simulation time 1899534772066 ps
CPU time 735.71 seconds
Started Mar 12 12:32:02 PM PDT 24
Finished Mar 12 12:44:18 PM PDT 24
Peak memory 191496 kb
Host smart-828609a8-ef68-4ee7-8e42-3b3e83df760c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170387421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.4170387421
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.3635558870
Short name T42
Test name
Test status
Simulation time 117082837146 ps
CPU time 99.28 seconds
Started Mar 12 12:32:01 PM PDT 24
Finished Mar 12 12:33:40 PM PDT 24
Peak memory 194364 kb
Host smart-3a39179d-ddbb-4d54-b23e-8ade03e7e01d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635558870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3635558870
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.497606302
Short name T238
Test name
Test status
Simulation time 286886605201 ps
CPU time 525.64 seconds
Started Mar 12 12:31:53 PM PDT 24
Finished Mar 12 12:40:38 PM PDT 24
Peak memory 191516 kb
Host smart-3b1352eb-066a-4208-8962-cfb696fed94b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497606302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.497606302
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.615513657
Short name T159
Test name
Test status
Simulation time 25727653432 ps
CPU time 42.78 seconds
Started Mar 12 12:32:02 PM PDT 24
Finished Mar 12 12:32:45 PM PDT 24
Peak memory 183252 kb
Host smart-7599e18b-9c1e-43cc-a839-068b6e3caf86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615513657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.615513657
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.2398522699
Short name T66
Test name
Test status
Simulation time 35289219060 ps
CPU time 65.84 seconds
Started Mar 12 12:31:50 PM PDT 24
Finished Mar 12 12:32:56 PM PDT 24
Peak memory 191480 kb
Host smart-5b608865-d6df-4009-b697-85d48f1e738a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398522699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2398522699
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.536606594
Short name T158
Test name
Test status
Simulation time 1484107013707 ps
CPU time 1836.3 seconds
Started Mar 12 12:31:59 PM PDT 24
Finished Mar 12 01:02:35 PM PDT 24
Peak memory 193644 kb
Host smart-208db332-a6c7-4561-a128-26ae359a434a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536606594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.536606594
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.857294570
Short name T286
Test name
Test status
Simulation time 172303167766 ps
CPU time 2542.02 seconds
Started Mar 12 12:32:01 PM PDT 24
Finished Mar 12 01:14:23 PM PDT 24
Peak memory 191472 kb
Host smart-0bef9d87-9a2d-4c01-b7ab-f506f73152cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857294570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.857294570
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.3260940386
Short name T47
Test name
Test status
Simulation time 125140440584 ps
CPU time 214.23 seconds
Started Mar 12 12:31:59 PM PDT 24
Finished Mar 12 12:35:33 PM PDT 24
Peak memory 191524 kb
Host smart-ee61be77-313c-4643-af94-96e47ec6d226
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260940386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3260940386
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.1975489140
Short name T390
Test name
Test status
Simulation time 6944347820 ps
CPU time 5.61 seconds
Started Mar 12 12:31:57 PM PDT 24
Finished Mar 12 12:32:03 PM PDT 24
Peak memory 183236 kb
Host smart-7c49d079-74f2-42ae-a135-62b9dd9e208f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975489140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1975489140
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1391358701
Short name T19
Test name
Test status
Simulation time 1562776475791 ps
CPU time 1704.94 seconds
Started Mar 12 12:31:32 PM PDT 24
Finished Mar 12 12:59:57 PM PDT 24
Peak memory 183296 kb
Host smart-c8593bab-199a-44cb-9962-3b151e0cc213
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391358701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1391358701
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.697776606
Short name T374
Test name
Test status
Simulation time 183460678965 ps
CPU time 79.17 seconds
Started Mar 12 12:31:27 PM PDT 24
Finished Mar 12 12:32:46 PM PDT 24
Peak memory 183320 kb
Host smart-7103c71f-0233-45eb-85b6-c7cab960041c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697776606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.697776606
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.1332397523
Short name T6
Test name
Test status
Simulation time 313155123535 ps
CPU time 691.51 seconds
Started Mar 12 12:31:15 PM PDT 24
Finished Mar 12 12:42:47 PM PDT 24
Peak memory 194608 kb
Host smart-9c78025b-6831-4d20-ba5f-cb61840afc41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332397523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.1332397523
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.880164890
Short name T121
Test name
Test status
Simulation time 8742001573 ps
CPU time 13.89 seconds
Started Mar 12 12:31:31 PM PDT 24
Finished Mar 12 12:31:45 PM PDT 24
Peak memory 191504 kb
Host smart-bbc876b3-dc12-4ad9-9743-49f5f0a02020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880164890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.880164890
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.1254223560
Short name T277
Test name
Test status
Simulation time 244452218963 ps
CPU time 715.61 seconds
Started Mar 12 12:31:57 PM PDT 24
Finished Mar 12 12:43:53 PM PDT 24
Peak memory 191520 kb
Host smart-0226e70f-19ab-4464-9c6c-7a278ddaf2cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254223560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1254223560
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.189887130
Short name T283
Test name
Test status
Simulation time 447031225315 ps
CPU time 1539.4 seconds
Started Mar 12 12:32:00 PM PDT 24
Finished Mar 12 12:57:40 PM PDT 24
Peak memory 191556 kb
Host smart-57f7ca28-224c-467f-9aa0-2adfdd906208
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189887130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.189887130
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.3106200763
Short name T426
Test name
Test status
Simulation time 29492378520 ps
CPU time 44.35 seconds
Started Mar 12 12:31:52 PM PDT 24
Finished Mar 12 12:32:37 PM PDT 24
Peak memory 192608 kb
Host smart-07b82d51-f84f-4db5-8600-d78fa5e13a5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106200763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3106200763
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3959401229
Short name T440
Test name
Test status
Simulation time 115479230240 ps
CPU time 145 seconds
Started Mar 12 12:32:02 PM PDT 24
Finished Mar 12 12:34:27 PM PDT 24
Peak memory 191476 kb
Host smart-2c19aeab-2ad0-4c28-ad1f-6ce592caf207
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959401229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3959401229
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2759434005
Short name T154
Test name
Test status
Simulation time 96163043499 ps
CPU time 290.41 seconds
Started Mar 12 12:31:55 PM PDT 24
Finished Mar 12 12:36:46 PM PDT 24
Peak memory 191500 kb
Host smart-f2093dd0-117f-4d33-962e-e3d330bd0cb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759434005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2759434005
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.3578944868
Short name T224
Test name
Test status
Simulation time 365894198396 ps
CPU time 669.16 seconds
Started Mar 12 12:32:00 PM PDT 24
Finished Mar 12 12:43:09 PM PDT 24
Peak memory 191516 kb
Host smart-8cf2ad86-b877-4921-9972-f2122fc8a85d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578944868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3578944868
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.3159504653
Short name T196
Test name
Test status
Simulation time 150642527860 ps
CPU time 427.54 seconds
Started Mar 12 12:31:54 PM PDT 24
Finished Mar 12 12:39:02 PM PDT 24
Peak memory 194964 kb
Host smart-8ace8482-7b13-446e-a1e3-fea8fbf5b1fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159504653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3159504653
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.2563223566
Short name T226
Test name
Test status
Simulation time 130665415681 ps
CPU time 1225.47 seconds
Started Mar 12 12:32:02 PM PDT 24
Finished Mar 12 12:52:27 PM PDT 24
Peak memory 194896 kb
Host smart-bf204b3c-cf96-48c9-9cc4-e44a1baf1d0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563223566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2563223566
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1280225934
Short name T335
Test name
Test status
Simulation time 117482665656 ps
CPU time 179.62 seconds
Started Mar 12 12:31:11 PM PDT 24
Finished Mar 12 12:34:11 PM PDT 24
Peak memory 183340 kb
Host smart-9cce484c-1bdb-4208-a2b1-08a7f39ca031
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280225934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1280225934
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.2252130591
Short name T40
Test name
Test status
Simulation time 220571775512 ps
CPU time 371.39 seconds
Started Mar 12 12:31:15 PM PDT 24
Finished Mar 12 12:37:26 PM PDT 24
Peak memory 183260 kb
Host smart-8f6bd767-8798-4efa-b09b-41b67a385f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252130591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2252130591
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.4215546028
Short name T447
Test name
Test status
Simulation time 503939817424 ps
CPU time 321.69 seconds
Started Mar 12 12:31:16 PM PDT 24
Finished Mar 12 12:36:38 PM PDT 24
Peak memory 191456 kb
Host smart-9495360a-95d0-4788-93ea-8760af49712b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215546028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.4215546028
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3172364812
Short name T358
Test name
Test status
Simulation time 15254510 ps
CPU time 0.52 seconds
Started Mar 12 12:31:27 PM PDT 24
Finished Mar 12 12:31:28 PM PDT 24
Peak memory 183012 kb
Host smart-df3b7396-8164-499d-b802-e3764081b885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172364812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3172364812
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.2558842058
Short name T257
Test name
Test status
Simulation time 31485590701 ps
CPU time 18.29 seconds
Started Mar 12 12:31:58 PM PDT 24
Finished Mar 12 12:32:16 PM PDT 24
Peak memory 183276 kb
Host smart-2afb7724-9c65-4b90-a876-38647c56a162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558842058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2558842058
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.1596818616
Short name T350
Test name
Test status
Simulation time 153739361674 ps
CPU time 242.74 seconds
Started Mar 12 12:31:59 PM PDT 24
Finished Mar 12 12:36:02 PM PDT 24
Peak memory 193648 kb
Host smart-d068f1cf-8e6a-43f2-a4b9-ad6ece06a60a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596818616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1596818616
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3371966118
Short name T124
Test name
Test status
Simulation time 570664193639 ps
CPU time 310.03 seconds
Started Mar 12 12:32:02 PM PDT 24
Finished Mar 12 12:37:12 PM PDT 24
Peak memory 191524 kb
Host smart-697391af-e14e-40c3-83c4-9840c4960283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371966118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3371966118
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.1580562620
Short name T423
Test name
Test status
Simulation time 89910980146 ps
CPU time 80.24 seconds
Started Mar 12 12:31:58 PM PDT 24
Finished Mar 12 12:33:18 PM PDT 24
Peak memory 191524 kb
Host smart-9a86a61d-518d-439f-b45d-1bd270e40869
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580562620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1580562620
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.2818516822
Short name T264
Test name
Test status
Simulation time 127984959295 ps
CPU time 216.1 seconds
Started Mar 12 12:32:04 PM PDT 24
Finished Mar 12 12:35:40 PM PDT 24
Peak memory 191508 kb
Host smart-c739b153-29e3-4e17-bf4c-ab390c240617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818516822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2818516822
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.1556656106
Short name T216
Test name
Test status
Simulation time 16420720034 ps
CPU time 67.03 seconds
Started Mar 12 12:31:58 PM PDT 24
Finished Mar 12 12:33:06 PM PDT 24
Peak memory 183324 kb
Host smart-9dea6953-5046-497e-9838-577afe8ad6b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556656106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1556656106
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2239882176
Short name T116
Test name
Test status
Simulation time 82685145060 ps
CPU time 289.79 seconds
Started Mar 12 12:31:58 PM PDT 24
Finished Mar 12 12:36:48 PM PDT 24
Peak memory 191392 kb
Host smart-cb5626d8-7c87-467b-b986-735a4e78d667
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239882176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2239882176
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.2622162916
Short name T110
Test name
Test status
Simulation time 241230316313 ps
CPU time 101.6 seconds
Started Mar 12 12:32:01 PM PDT 24
Finished Mar 12 12:33:43 PM PDT 24
Peak memory 191504 kb
Host smart-6c261f1e-9056-42e0-8826-a7bf8eb7ef18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622162916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2622162916
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3529308020
Short name T279
Test name
Test status
Simulation time 132715006411 ps
CPU time 250.97 seconds
Started Mar 12 12:31:29 PM PDT 24
Finished Mar 12 12:35:40 PM PDT 24
Peak memory 183316 kb
Host smart-e1ad5a5a-d500-487a-857d-35059f9aeca8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529308020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3529308020
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.637993497
Short name T9
Test name
Test status
Simulation time 99436826036 ps
CPU time 140.06 seconds
Started Mar 12 12:31:23 PM PDT 24
Finished Mar 12 12:33:44 PM PDT 24
Peak memory 183268 kb
Host smart-abb46748-37cc-4e5e-a5be-32abf1644f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637993497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.637993497
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.2026072951
Short name T385
Test name
Test status
Simulation time 89816825751 ps
CPU time 178.01 seconds
Started Mar 12 12:31:11 PM PDT 24
Finished Mar 12 12:34:09 PM PDT 24
Peak memory 191512 kb
Host smart-b68094ca-5fab-4082-a2bb-237bb6a51717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026072951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2026072951
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.648039721
Short name T10
Test name
Test status
Simulation time 53496976 ps
CPU time 0.58 seconds
Started Mar 12 12:31:34 PM PDT 24
Finished Mar 12 12:31:35 PM PDT 24
Peak memory 182988 kb
Host smart-58683ef1-f0f3-4ff9-9f21-33d40357afa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648039721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.
648039721
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.3821826228
Short name T35
Test name
Test status
Simulation time 538958385868 ps
CPU time 953.75 seconds
Started Mar 12 12:31:37 PM PDT 24
Finished Mar 12 12:47:31 PM PDT 24
Peak memory 208612 kb
Host smart-a401c6c5-d04b-4c7e-be96-cd682403f3da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821826228 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.3821826228
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.2547289023
Short name T254
Test name
Test status
Simulation time 167290252208 ps
CPU time 135.74 seconds
Started Mar 12 12:32:02 PM PDT 24
Finished Mar 12 12:34:17 PM PDT 24
Peak memory 194512 kb
Host smart-d379146d-99d0-4fd8-9c6a-889dadb94f65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547289023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.2547289023
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.4150746948
Short name T144
Test name
Test status
Simulation time 67261848623 ps
CPU time 198.76 seconds
Started Mar 12 12:31:52 PM PDT 24
Finished Mar 12 12:35:11 PM PDT 24
Peak memory 191512 kb
Host smart-5feb4ab5-70ce-4ea7-bbed-1583ce147487
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150746948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.4150746948
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.424914455
Short name T433
Test name
Test status
Simulation time 349546869089 ps
CPU time 321.97 seconds
Started Mar 12 12:32:01 PM PDT 24
Finished Mar 12 12:37:23 PM PDT 24
Peak memory 191528 kb
Host smart-76449c7b-54e7-45ae-8341-2f384c14afcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424914455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.424914455
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.4241106967
Short name T151
Test name
Test status
Simulation time 255980944447 ps
CPU time 224.48 seconds
Started Mar 12 12:32:00 PM PDT 24
Finished Mar 12 12:35:44 PM PDT 24
Peak memory 191508 kb
Host smart-0d214707-f709-4585-9607-3b69c4faebf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241106967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.4241106967
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.686067233
Short name T306
Test name
Test status
Simulation time 29628284096 ps
CPU time 304.15 seconds
Started Mar 12 12:32:00 PM PDT 24
Finished Mar 12 12:37:04 PM PDT 24
Peak memory 191488 kb
Host smart-a906a656-d3e1-4fb5-9b45-4b0da30736de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686067233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.686067233
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1575882697
Short name T239
Test name
Test status
Simulation time 102067037387 ps
CPU time 95.73 seconds
Started Mar 12 12:32:00 PM PDT 24
Finished Mar 12 12:33:36 PM PDT 24
Peak memory 191440 kb
Host smart-56d33f4a-013a-4ed8-a9c3-a74c1d030c23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575882697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1575882697
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2959979713
Short name T391
Test name
Test status
Simulation time 354484162821 ps
CPU time 189.97 seconds
Started Mar 12 12:32:03 PM PDT 24
Finished Mar 12 12:35:13 PM PDT 24
Peak memory 191524 kb
Host smart-a488e0ee-84e4-4e85-b189-fd823d8f9b53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959979713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2959979713
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1738845733
Short name T181
Test name
Test status
Simulation time 3081309416 ps
CPU time 6.38 seconds
Started Mar 12 12:31:59 PM PDT 24
Finished Mar 12 12:32:06 PM PDT 24
Peak memory 183284 kb
Host smart-2bdb7bde-5d8f-4567-9bf5-3731e26f52c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738845733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1738845733
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.76018646
Short name T7
Test name
Test status
Simulation time 13692690496 ps
CPU time 22.16 seconds
Started Mar 12 12:32:06 PM PDT 24
Finished Mar 12 12:32:29 PM PDT 24
Peak memory 191500 kb
Host smart-187ff64b-2bf8-428f-b0e2-a5aa72864c3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76018646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.76018646
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3509518083
Short name T341
Test name
Test status
Simulation time 172302718563 ps
CPU time 99.69 seconds
Started Mar 12 12:31:59 PM PDT 24
Finished Mar 12 12:33:39 PM PDT 24
Peak memory 183316 kb
Host smart-19d85cc4-0278-407a-a996-506c2a83fce2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509518083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3509518083
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2485691428
Short name T339
Test name
Test status
Simulation time 91284881651 ps
CPU time 35.66 seconds
Started Mar 12 12:31:31 PM PDT 24
Finished Mar 12 12:32:07 PM PDT 24
Peak memory 183452 kb
Host smart-591ae267-f8a2-4808-8b4a-15ab4fdfecea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485691428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2485691428
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1721873191
Short name T448
Test name
Test status
Simulation time 62308021294 ps
CPU time 48.06 seconds
Started Mar 12 12:31:23 PM PDT 24
Finished Mar 12 12:32:11 PM PDT 24
Peak memory 183312 kb
Host smart-5fb2b5ff-34f0-4747-8434-f4985d8fb6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721873191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1721873191
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3019242986
Short name T398
Test name
Test status
Simulation time 118272897000 ps
CPU time 264.45 seconds
Started Mar 12 12:31:13 PM PDT 24
Finished Mar 12 12:35:38 PM PDT 24
Peak memory 194688 kb
Host smart-e1785cd1-0078-4ba7-8daf-ff88ce367615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019242986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3019242986
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.869777342
Short name T419
Test name
Test status
Simulation time 120400910448 ps
CPU time 197.45 seconds
Started Mar 12 12:32:04 PM PDT 24
Finished Mar 12 12:35:22 PM PDT 24
Peak memory 191484 kb
Host smart-fb3aabf4-0291-4fa5-968b-410c4868df9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869777342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.869777342
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.1769622624
Short name T67
Test name
Test status
Simulation time 79348067464 ps
CPU time 160.92 seconds
Started Mar 12 12:32:04 PM PDT 24
Finished Mar 12 12:34:45 PM PDT 24
Peak memory 191512 kb
Host smart-9f9fac99-bc35-447e-a064-e36a622a0099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769622624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1769622624
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.2980373881
Short name T304
Test name
Test status
Simulation time 12395249619 ps
CPU time 174.2 seconds
Started Mar 12 12:32:06 PM PDT 24
Finished Mar 12 12:35:01 PM PDT 24
Peak memory 191456 kb
Host smart-36c56a61-ef3c-489a-b981-8c73d282ddea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980373881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2980373881
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.2043489031
Short name T237
Test name
Test status
Simulation time 406094697064 ps
CPU time 529.38 seconds
Started Mar 12 12:32:01 PM PDT 24
Finished Mar 12 12:40:51 PM PDT 24
Peak memory 191508 kb
Host smart-1fcf80b3-a413-46ac-9dee-daf9468798df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043489031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2043489031
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.265908932
Short name T303
Test name
Test status
Simulation time 47840848666 ps
CPU time 54.37 seconds
Started Mar 12 12:32:03 PM PDT 24
Finished Mar 12 12:32:58 PM PDT 24
Peak memory 183292 kb
Host smart-0239c743-8ae2-4626-bde8-260b36a41ea4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265908932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.265908932
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.796419829
Short name T198
Test name
Test status
Simulation time 49031107909 ps
CPU time 90.06 seconds
Started Mar 12 12:32:00 PM PDT 24
Finished Mar 12 12:33:31 PM PDT 24
Peak memory 193948 kb
Host smart-8173771c-f944-4a31-a2f6-025f9dbec53c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796419829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.796419829
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3199001994
Short name T318
Test name
Test status
Simulation time 91542967682 ps
CPU time 230.07 seconds
Started Mar 12 12:32:04 PM PDT 24
Finished Mar 12 12:35:55 PM PDT 24
Peak memory 194768 kb
Host smart-d334a03e-769e-4598-93f8-7b6b6a5fd4fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199001994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3199001994
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1001083430
Short name T320
Test name
Test status
Simulation time 100556106556 ps
CPU time 98.78 seconds
Started Mar 12 12:31:02 PM PDT 24
Finished Mar 12 12:32:41 PM PDT 24
Peak memory 183320 kb
Host smart-652ae99d-830b-4781-935f-bfb7a4ac84d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001083430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1001083430
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.2060666649
Short name T352
Test name
Test status
Simulation time 123818824301 ps
CPU time 188.68 seconds
Started Mar 12 12:30:55 PM PDT 24
Finished Mar 12 12:34:09 PM PDT 24
Peak memory 183296 kb
Host smart-489b8bf2-68d6-43a3-9836-72355a6a7669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060666649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2060666649
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.409832652
Short name T133
Test name
Test status
Simulation time 542080914261 ps
CPU time 251.57 seconds
Started Mar 12 12:31:08 PM PDT 24
Finished Mar 12 12:35:21 PM PDT 24
Peak memory 193696 kb
Host smart-09dd795c-ab2e-4199-bc89-2e719e16398c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409832652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.409832652
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1625222059
Short name T413
Test name
Test status
Simulation time 24917577127 ps
CPU time 142.43 seconds
Started Mar 12 12:31:06 PM PDT 24
Finished Mar 12 12:33:28 PM PDT 24
Peak memory 191512 kb
Host smart-4af1f62a-0b71-45b8-b704-69281447f496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625222059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1625222059
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3113037034
Short name T15
Test name
Test status
Simulation time 133027904 ps
CPU time 0.74 seconds
Started Mar 12 12:32:01 PM PDT 24
Finished Mar 12 12:32:01 PM PDT 24
Peak memory 213480 kb
Host smart-aa5323ba-15e0-44bf-abb7-f4b42598ca6f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113037034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3113037034
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2391605178
Short name T321
Test name
Test status
Simulation time 170166456868 ps
CPU time 323.21 seconds
Started Mar 12 12:31:34 PM PDT 24
Finished Mar 12 12:36:58 PM PDT 24
Peak memory 183320 kb
Host smart-00e42a57-2a1e-4935-b3a3-b43c1f2c1dc6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391605178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2391605178
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1782378444
Short name T363
Test name
Test status
Simulation time 163642327673 ps
CPU time 126.6 seconds
Started Mar 12 12:31:19 PM PDT 24
Finished Mar 12 12:33:26 PM PDT 24
Peak memory 183328 kb
Host smart-c42d2b9a-66fa-432f-b74e-2f1f7d3d4aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782378444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1782378444
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.2650129080
Short name T326
Test name
Test status
Simulation time 401986058801 ps
CPU time 652.94 seconds
Started Mar 12 12:31:28 PM PDT 24
Finished Mar 12 12:42:21 PM PDT 24
Peak memory 191532 kb
Host smart-1a97596a-bdef-4d2b-9643-920b4a01085d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650129080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2650129080
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3155994884
Short name T325
Test name
Test status
Simulation time 37718145525 ps
CPU time 68.69 seconds
Started Mar 12 12:31:12 PM PDT 24
Finished Mar 12 12:32:21 PM PDT 24
Peak memory 193900 kb
Host smart-ffe956e6-9422-40ea-83cf-cb347abee561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155994884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3155994884
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.3080856928
Short name T55
Test name
Test status
Simulation time 58949566317 ps
CPU time 20.73 seconds
Started Mar 12 12:31:33 PM PDT 24
Finished Mar 12 12:31:53 PM PDT 24
Peak memory 183320 kb
Host smart-6558d3fe-8f94-47d3-82d1-5490a7133690
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080856928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.3080856928
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.181872498
Short name T37
Test name
Test status
Simulation time 81437038612 ps
CPU time 171.67 seconds
Started Mar 12 12:31:15 PM PDT 24
Finished Mar 12 12:34:07 PM PDT 24
Peak memory 206160 kb
Host smart-0f1d1433-58a5-4b16-b45c-3b2bb03c283e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181872498 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.181872498
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1098092670
Short name T349
Test name
Test status
Simulation time 28249723848 ps
CPU time 17.16 seconds
Started Mar 12 12:31:45 PM PDT 24
Finished Mar 12 12:32:02 PM PDT 24
Peak memory 183344 kb
Host smart-eb4d242d-cdf8-4935-8ea8-3cb5fb9f2d50
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098092670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.1098092670
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.2244793364
Short name T388
Test name
Test status
Simulation time 119852500928 ps
CPU time 88.2 seconds
Started Mar 12 12:38:12 PM PDT 24
Finished Mar 12 12:39:40 PM PDT 24
Peak memory 183188 kb
Host smart-c7fcebda-ee2e-4149-bfce-35c9665a184e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244793364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2244793364
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.1595408704
Short name T258
Test name
Test status
Simulation time 454392115132 ps
CPU time 528.78 seconds
Started Mar 12 12:31:35 PM PDT 24
Finished Mar 12 12:40:24 PM PDT 24
Peak memory 191596 kb
Host smart-f29d83da-8421-4fc9-98da-fb9d145c96a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595408704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1595408704
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.4224855774
Short name T164
Test name
Test status
Simulation time 92212543290 ps
CPU time 42.69 seconds
Started Mar 12 12:31:25 PM PDT 24
Finished Mar 12 12:32:07 PM PDT 24
Peak memory 193816 kb
Host smart-47c83941-75a2-4834-97a8-489db557157e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224855774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.4224855774
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.2349260732
Short name T408
Test name
Test status
Simulation time 172009894626 ps
CPU time 254.97 seconds
Started Mar 12 12:31:17 PM PDT 24
Finished Mar 12 12:35:33 PM PDT 24
Peak memory 195100 kb
Host smart-28a0b8a9-960c-4cb6-8cdb-87ba687660d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349260732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.2349260732
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.2477314537
Short name T420
Test name
Test status
Simulation time 17624336061 ps
CPU time 32.67 seconds
Started Mar 12 12:31:16 PM PDT 24
Finished Mar 12 12:31:49 PM PDT 24
Peak memory 183344 kb
Host smart-cf06c2b1-4996-4293-97ac-39f0d6233055
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477314537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.2477314537
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3523044392
Short name T379
Test name
Test status
Simulation time 223804033589 ps
CPU time 199.59 seconds
Started Mar 12 12:31:33 PM PDT 24
Finished Mar 12 12:34:53 PM PDT 24
Peak memory 183216 kb
Host smart-7cc45361-acf7-44dc-a151-85455bdf4788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523044392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3523044392
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.3398711901
Short name T220
Test name
Test status
Simulation time 2164033191480 ps
CPU time 2081.63 seconds
Started Mar 12 12:31:30 PM PDT 24
Finished Mar 12 01:06:12 PM PDT 24
Peak memory 191512 kb
Host smart-cebab7fb-2b13-47f1-bd40-4bf5f8189914
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398711901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3398711901
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.4202711918
Short name T134
Test name
Test status
Simulation time 43984561415 ps
CPU time 64.41 seconds
Started Mar 12 12:31:32 PM PDT 24
Finished Mar 12 12:32:36 PM PDT 24
Peak memory 191504 kb
Host smart-44f9a0cd-fea6-4649-9248-3700370f2e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202711918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.4202711918
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.1459113762
Short name T33
Test name
Test status
Simulation time 53736683426 ps
CPU time 438.04 seconds
Started Mar 12 12:31:31 PM PDT 24
Finished Mar 12 12:38:50 PM PDT 24
Peak memory 206160 kb
Host smart-bd54c98f-4581-4878-86fa-955a041ef1a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459113762 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.1459113762
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.3193744384
Short name T274
Test name
Test status
Simulation time 27667654722 ps
CPU time 40.54 seconds
Started Mar 12 12:31:32 PM PDT 24
Finished Mar 12 12:32:12 PM PDT 24
Peak memory 183320 kb
Host smart-4d563793-6f45-4a0f-9aa0-3d9523972929
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193744384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.3193744384
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2995601938
Short name T45
Test name
Test status
Simulation time 158941401314 ps
CPU time 235.53 seconds
Started Mar 12 12:31:21 PM PDT 24
Finished Mar 12 12:35:17 PM PDT 24
Peak memory 183328 kb
Host smart-f10a3ea6-1eda-4367-879d-b80aeb640bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995601938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2995601938
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.2808231010
Short name T332
Test name
Test status
Simulation time 29624822603 ps
CPU time 51.19 seconds
Started Mar 12 12:31:37 PM PDT 24
Finished Mar 12 12:32:28 PM PDT 24
Peak memory 183276 kb
Host smart-f5751574-e9f5-424e-a6b4-7f5ddd6cb476
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808231010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2808231010
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.1908914445
Short name T334
Test name
Test status
Simulation time 21374551363 ps
CPU time 48.5 seconds
Started Mar 12 12:31:34 PM PDT 24
Finished Mar 12 12:32:23 PM PDT 24
Peak memory 191496 kb
Host smart-2231b3f1-973a-4fd5-915d-55a53d9c28bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908914445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1908914445
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.656381487
Short name T403
Test name
Test status
Simulation time 72284611983 ps
CPU time 37.41 seconds
Started Mar 12 12:31:35 PM PDT 24
Finished Mar 12 12:32:12 PM PDT 24
Peak memory 183684 kb
Host smart-e581cc37-a665-4007-a05a-c2382faf9d94
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656381487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.rv_timer_cfg_update_on_fly.656381487
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.84045974
Short name T64
Test name
Test status
Simulation time 363998545865 ps
CPU time 133.14 seconds
Started Mar 12 12:31:26 PM PDT 24
Finished Mar 12 12:33:39 PM PDT 24
Peak memory 183324 kb
Host smart-919bb043-6c0c-46fb-a8f3-0018fb1d08f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84045974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.84045974
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2760371366
Short name T441
Test name
Test status
Simulation time 24551520880 ps
CPU time 17.71 seconds
Started Mar 12 12:31:37 PM PDT 24
Finished Mar 12 12:31:55 PM PDT 24
Peak memory 195156 kb
Host smart-f83f5bad-e392-4f64-b350-352f8c04df15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760371366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2760371366
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.3340919734
Short name T54
Test name
Test status
Simulation time 100368563931 ps
CPU time 143.88 seconds
Started Mar 12 12:31:34 PM PDT 24
Finished Mar 12 12:33:58 PM PDT 24
Peak memory 183324 kb
Host smart-a35a205a-5ab1-4982-a296-d40d2d137655
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340919734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.3340919734
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.1196871210
Short name T231
Test name
Test status
Simulation time 114018659085 ps
CPU time 109.43 seconds
Started Mar 12 12:31:32 PM PDT 24
Finished Mar 12 12:33:22 PM PDT 24
Peak memory 183324 kb
Host smart-40dd2e1c-b93c-4d20-a9c4-8fe23c6ed2c8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196871210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.1196871210
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.3428911192
Short name T406
Test name
Test status
Simulation time 115975906715 ps
CPU time 184.43 seconds
Started Mar 12 12:31:28 PM PDT 24
Finished Mar 12 12:34:33 PM PDT 24
Peak memory 183284 kb
Host smart-1e8faf71-8d4e-4724-bee5-dddc9cedadc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428911192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3428911192
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.2318171838
Short name T418
Test name
Test status
Simulation time 96127804703 ps
CPU time 140.74 seconds
Started Mar 12 12:31:35 PM PDT 24
Finished Mar 12 12:33:56 PM PDT 24
Peak memory 194036 kb
Host smart-7d894cad-da16-4b13-94ce-cba779fa48de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318171838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2318171838
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1825323817
Short name T136
Test name
Test status
Simulation time 108769455031 ps
CPU time 102.21 seconds
Started Mar 12 12:31:23 PM PDT 24
Finished Mar 12 12:33:05 PM PDT 24
Peak memory 183320 kb
Host smart-dea7f5c7-060e-4700-8412-4293fb9a13f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825323817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1825323817
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.441878614
Short name T245
Test name
Test status
Simulation time 28691788741 ps
CPU time 45.34 seconds
Started Mar 12 12:31:23 PM PDT 24
Finished Mar 12 12:32:09 PM PDT 24
Peak memory 183328 kb
Host smart-24b64efa-1bf9-44f7-87cd-f063d659db08
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441878614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.441878614
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.767823191
Short name T427
Test name
Test status
Simulation time 181032364026 ps
CPU time 81.82 seconds
Started Mar 12 12:31:32 PM PDT 24
Finished Mar 12 12:32:54 PM PDT 24
Peak memory 183312 kb
Host smart-7446ea5c-2585-4d18-b9bb-7a7b198d960d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767823191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.767823191
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.1458693867
Short name T98
Test name
Test status
Simulation time 139315627833 ps
CPU time 550.5 seconds
Started Mar 12 12:31:34 PM PDT 24
Finished Mar 12 12:40:44 PM PDT 24
Peak memory 191500 kb
Host smart-d769cede-b668-4617-8d0c-ec409c7fb5c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458693867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1458693867
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2466721073
Short name T450
Test name
Test status
Simulation time 1033512483 ps
CPU time 0.9 seconds
Started Mar 12 12:38:10 PM PDT 24
Finished Mar 12 12:38:12 PM PDT 24
Peak memory 191284 kb
Host smart-150593a5-ec09-4644-b79f-0830d22b7b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466721073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2466721073
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1543607826
Short name T438
Test name
Test status
Simulation time 1268412136663 ps
CPU time 619.86 seconds
Started Mar 12 12:31:31 PM PDT 24
Finished Mar 12 12:41:51 PM PDT 24
Peak memory 191472 kb
Host smart-47083dd5-7259-4b03-8bca-747d234d305d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543607826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1543607826
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.2920773541
Short name T38
Test name
Test status
Simulation time 62139254597 ps
CPU time 451.44 seconds
Started Mar 12 12:31:34 PM PDT 24
Finished Mar 12 12:39:06 PM PDT 24
Peak memory 206184 kb
Host smart-fa732ebd-0dc0-4c40-aff3-e5146daafbd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920773541 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.2920773541
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2906380623
Short name T118
Test name
Test status
Simulation time 114322708160 ps
CPU time 210.71 seconds
Started Mar 12 12:31:24 PM PDT 24
Finished Mar 12 12:34:55 PM PDT 24
Peak memory 183416 kb
Host smart-fe9ac343-3521-4957-9c6e-95254b61432d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906380623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.2906380623
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.3182728724
Short name T368
Test name
Test status
Simulation time 68188810476 ps
CPU time 92.51 seconds
Started Mar 12 12:31:26 PM PDT 24
Finished Mar 12 12:32:59 PM PDT 24
Peak memory 183292 kb
Host smart-c1df8cc6-3e02-47ea-9d1d-66f6a688adc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182728724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3182728724
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.2503138617
Short name T108
Test name
Test status
Simulation time 119384663844 ps
CPU time 178.94 seconds
Started Mar 12 12:31:41 PM PDT 24
Finished Mar 12 12:34:40 PM PDT 24
Peak memory 191528 kb
Host smart-c57abfaf-3737-45a5-8c76-dd8ad766f578
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503138617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2503138617
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.4091552795
Short name T259
Test name
Test status
Simulation time 9631149447 ps
CPU time 16.88 seconds
Started Mar 12 12:38:11 PM PDT 24
Finished Mar 12 12:38:29 PM PDT 24
Peak memory 191380 kb
Host smart-eea0b2cd-098b-4e10-bfea-9ac1240bee10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091552795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.4091552795
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3640855782
Short name T102
Test name
Test status
Simulation time 91530620922 ps
CPU time 86.93 seconds
Started Mar 12 12:32:31 PM PDT 24
Finished Mar 12 12:34:00 PM PDT 24
Peak memory 182452 kb
Host smart-acd18905-75af-4538-bcd4-8acb2c02b6da
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640855782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.3640855782
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.772976241
Short name T372
Test name
Test status
Simulation time 524336199469 ps
CPU time 264.59 seconds
Started Mar 12 12:31:31 PM PDT 24
Finished Mar 12 12:35:55 PM PDT 24
Peak memory 183304 kb
Host smart-d46c0b2f-1767-4808-9ee2-3b06323a89f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772976241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.772976241
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.2172903373
Short name T323
Test name
Test status
Simulation time 164378018283 ps
CPU time 105.4 seconds
Started Mar 12 12:31:27 PM PDT 24
Finished Mar 12 12:33:13 PM PDT 24
Peak memory 183308 kb
Host smart-cdfcb142-ed4c-44a4-94d0-d801b7bbd328
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172903373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2172903373
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1980983694
Short name T2
Test name
Test status
Simulation time 48830759732 ps
CPU time 87.43 seconds
Started Mar 12 12:31:35 PM PDT 24
Finished Mar 12 12:33:03 PM PDT 24
Peak memory 191416 kb
Host smart-15e54c26-6b31-43fb-a487-9e283a627f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980983694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1980983694
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.2682457710
Short name T13
Test name
Test status
Simulation time 36573146377 ps
CPU time 276.45 seconds
Started Mar 12 12:31:33 PM PDT 24
Finished Mar 12 12:36:09 PM PDT 24
Peak memory 206064 kb
Host smart-d716f940-b0d2-443c-8794-5ff14010e27b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682457710 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.2682457710
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3263848604
Short name T30
Test name
Test status
Simulation time 97423037372 ps
CPU time 51.69 seconds
Started Mar 12 12:38:11 PM PDT 24
Finished Mar 12 12:39:04 PM PDT 24
Peak memory 183164 kb
Host smart-0f5f7e02-0b75-4b17-a201-78ea864c31a3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263848604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.3263848604
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2838156064
Short name T397
Test name
Test status
Simulation time 227932429132 ps
CPU time 89.06 seconds
Started Mar 12 12:31:29 PM PDT 24
Finished Mar 12 12:32:58 PM PDT 24
Peak memory 183212 kb
Host smart-24bce118-f10b-4f42-8060-e7f69a01c668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838156064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2838156064
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.3113395683
Short name T317
Test name
Test status
Simulation time 133453583176 ps
CPU time 40.51 seconds
Started Mar 12 12:31:12 PM PDT 24
Finished Mar 12 12:31:53 PM PDT 24
Peak memory 183268 kb
Host smart-5ae8bf94-5409-490a-b4b5-65b9c3dc0080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113395683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3113395683
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1474996276
Short name T365
Test name
Test status
Simulation time 412247451 ps
CPU time 1.34 seconds
Started Mar 12 12:31:37 PM PDT 24
Finished Mar 12 12:31:38 PM PDT 24
Peak memory 194044 kb
Host smart-4744cb70-8aae-422d-b53d-b2144c9925e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474996276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1474996276
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.220040510
Short name T407
Test name
Test status
Simulation time 33964752056 ps
CPU time 17.68 seconds
Started Mar 12 12:31:03 PM PDT 24
Finished Mar 12 12:31:21 PM PDT 24
Peak memory 183304 kb
Host smart-aff747f9-b764-4855-9f35-e2938981905b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220040510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.220040510
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.3565577000
Short name T356
Test name
Test status
Simulation time 136454116646 ps
CPU time 214.65 seconds
Started Mar 12 12:31:00 PM PDT 24
Finished Mar 12 12:34:35 PM PDT 24
Peak memory 183392 kb
Host smart-2ae7121e-c997-40ff-9e39-9b5b1f2fdc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565577000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3565577000
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.426924371
Short name T168
Test name
Test status
Simulation time 187316134638 ps
CPU time 79.76 seconds
Started Mar 12 12:31:17 PM PDT 24
Finished Mar 12 12:32:37 PM PDT 24
Peak memory 193716 kb
Host smart-91b10205-4dc7-49a6-9611-11111bfd7556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426924371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.426924371
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2560102200
Short name T17
Test name
Test status
Simulation time 271909951 ps
CPU time 0.85 seconds
Started Mar 12 12:31:11 PM PDT 24
Finished Mar 12 12:31:12 PM PDT 24
Peak memory 213600 kb
Host smart-49d7da92-fbc1-4fd6-ad3a-19158780ad21
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560102200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2560102200
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2928169352
Short name T336
Test name
Test status
Simulation time 40457888867 ps
CPU time 73.39 seconds
Started Mar 12 12:31:35 PM PDT 24
Finished Mar 12 12:32:48 PM PDT 24
Peak memory 183292 kb
Host smart-b137c0a5-9c61-41d4-8061-2b46751f9bd6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928169352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2928169352
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.519968678
Short name T370
Test name
Test status
Simulation time 54187462902 ps
CPU time 76.48 seconds
Started Mar 12 12:31:12 PM PDT 24
Finished Mar 12 12:32:28 PM PDT 24
Peak memory 183316 kb
Host smart-edf4786a-27cd-46b8-82a0-7155a3623ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519968678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.519968678
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2594546126
Short name T327
Test name
Test status
Simulation time 19053515827 ps
CPU time 35.92 seconds
Started Mar 12 12:31:35 PM PDT 24
Finished Mar 12 12:32:11 PM PDT 24
Peak memory 191492 kb
Host smart-6b7e9ce9-d384-49b4-8ec5-e0ce584c6186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594546126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2594546126
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1308664147
Short name T351
Test name
Test status
Simulation time 93125004868 ps
CPU time 138.83 seconds
Started Mar 12 12:31:38 PM PDT 24
Finished Mar 12 12:33:57 PM PDT 24
Peak memory 194116 kb
Host smart-18e95adc-71ed-4f57-89f7-181d07ae5be5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308664147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1308664147
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2746633038
Short name T288
Test name
Test status
Simulation time 248999248070 ps
CPU time 125.82 seconds
Started Mar 12 12:31:34 PM PDT 24
Finished Mar 12 12:33:40 PM PDT 24
Peak memory 183304 kb
Host smart-1870d9bd-a884-4717-9730-aae4695f1297
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746633038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2746633038
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3438947142
Short name T353
Test name
Test status
Simulation time 164518472597 ps
CPU time 254.84 seconds
Started Mar 12 12:31:38 PM PDT 24
Finished Mar 12 12:35:53 PM PDT 24
Peak memory 183316 kb
Host smart-0e1f2ba3-2521-43a6-96cf-31b3321cbea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438947142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3438947142
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.1232251384
Short name T218
Test name
Test status
Simulation time 176643947308 ps
CPU time 214.29 seconds
Started Mar 12 12:31:36 PM PDT 24
Finished Mar 12 12:35:11 PM PDT 24
Peak memory 191512 kb
Host smart-c73496ae-fc59-455e-8189-062c754a7a53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232251384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1232251384
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2370687372
Short name T179
Test name
Test status
Simulation time 105504252973 ps
CPU time 96.37 seconds
Started Mar 12 12:31:36 PM PDT 24
Finished Mar 12 12:33:12 PM PDT 24
Peak memory 191512 kb
Host smart-cb6e7cf9-a001-43a4-b78a-b7506163be1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370687372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2370687372
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2753210150
Short name T394
Test name
Test status
Simulation time 340325987251 ps
CPU time 124.01 seconds
Started Mar 12 12:31:26 PM PDT 24
Finished Mar 12 12:33:31 PM PDT 24
Peak memory 183308 kb
Host smart-6a4734eb-67a7-4005-b74e-281905573be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753210150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2753210150
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.862928587
Short name T137
Test name
Test status
Simulation time 29572397152 ps
CPU time 50.27 seconds
Started Mar 12 12:31:29 PM PDT 24
Finished Mar 12 12:32:19 PM PDT 24
Peak memory 191528 kb
Host smart-145dda37-8b01-4fb2-9e85-6552399968d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862928587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.862928587
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.2169064518
Short name T428
Test name
Test status
Simulation time 117444828745 ps
CPU time 114.41 seconds
Started Mar 12 12:31:36 PM PDT 24
Finished Mar 12 12:33:31 PM PDT 24
Peak memory 194576 kb
Host smart-4cc187bc-66d2-4359-8db5-af43537b1dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169064518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2169064518
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3656655945
Short name T360
Test name
Test status
Simulation time 240251825313 ps
CPU time 154.82 seconds
Started Mar 12 12:31:38 PM PDT 24
Finished Mar 12 12:34:13 PM PDT 24
Peak memory 183344 kb
Host smart-bb3bbeb2-87ec-42a4-b373-c5ed9128d289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656655945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3656655945
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.142819390
Short name T22
Test name
Test status
Simulation time 130407669873 ps
CPU time 77.04 seconds
Started Mar 12 12:31:46 PM PDT 24
Finished Mar 12 12:33:03 PM PDT 24
Peak memory 183308 kb
Host smart-501d064c-69cc-43eb-b925-ed75175be6e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142819390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.142819390
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.354464074
Short name T378
Test name
Test status
Simulation time 573276642 ps
CPU time 0.83 seconds
Started Mar 12 12:31:37 PM PDT 24
Finished Mar 12 12:31:38 PM PDT 24
Peak memory 183092 kb
Host smart-acc8af0a-6764-47c2-b7c5-b24639311dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354464074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.354464074
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3709716429
Short name T56
Test name
Test status
Simulation time 1510195182415 ps
CPU time 357.35 seconds
Started Mar 12 12:31:36 PM PDT 24
Finished Mar 12 12:37:34 PM PDT 24
Peak memory 195804 kb
Host smart-270b27f7-6c61-4ff3-acac-e523e92c27d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709716429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3709716429
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3532790034
Short name T296
Test name
Test status
Simulation time 374114637494 ps
CPU time 691.19 seconds
Started Mar 12 12:31:43 PM PDT 24
Finished Mar 12 12:43:14 PM PDT 24
Peak memory 183284 kb
Host smart-b53b90bf-dcda-4f61-8ac1-e0b400db017c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532790034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3532790034
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3957296501
Short name T387
Test name
Test status
Simulation time 98288308679 ps
CPU time 136.49 seconds
Started Mar 12 12:31:36 PM PDT 24
Finished Mar 12 12:33:53 PM PDT 24
Peak memory 183260 kb
Host smart-47b77cd0-7b93-4ebc-aac3-fac87cbdc2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957296501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3957296501
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.520100542
Short name T432
Test name
Test status
Simulation time 164004622352 ps
CPU time 167.25 seconds
Started Mar 12 12:31:33 PM PDT 24
Finished Mar 12 12:34:21 PM PDT 24
Peak memory 191508 kb
Host smart-9cd85ba3-51c2-4d37-8f32-4ed7e2e98b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520100542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.520100542
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.639826005
Short name T34
Test name
Test status
Simulation time 232370863124 ps
CPU time 326.66 seconds
Started Mar 12 12:31:33 PM PDT 24
Finished Mar 12 12:36:59 PM PDT 24
Peak memory 206148 kb
Host smart-7ce89161-c18f-42f3-afbc-32b025a7be6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639826005 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.639826005
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2576362392
Short name T213
Test name
Test status
Simulation time 15056633710 ps
CPU time 15.09 seconds
Started Mar 12 12:31:29 PM PDT 24
Finished Mar 12 12:31:44 PM PDT 24
Peak memory 183344 kb
Host smart-344819b4-afdd-445b-aea6-d1ca117065d5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576362392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2576362392
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1974142140
Short name T383
Test name
Test status
Simulation time 133626931223 ps
CPU time 214.93 seconds
Started Mar 12 12:31:34 PM PDT 24
Finished Mar 12 12:35:09 PM PDT 24
Peak memory 183308 kb
Host smart-5e57e88d-13d0-4417-9ab6-48419caf3d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974142140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1974142140
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.428931982
Short name T182
Test name
Test status
Simulation time 135575088049 ps
CPU time 54.56 seconds
Started Mar 12 12:31:41 PM PDT 24
Finished Mar 12 12:32:36 PM PDT 24
Peak memory 183296 kb
Host smart-74670f2b-f79b-4006-974c-0837405a6c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428931982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.428931982
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2594020268
Short name T152
Test name
Test status
Simulation time 705708779313 ps
CPU time 1494.81 seconds
Started Mar 12 12:31:35 PM PDT 24
Finished Mar 12 12:56:30 PM PDT 24
Peak memory 191472 kb
Host smart-0846c172-1372-45e7-8e9d-9863bd9df328
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594020268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2594020268
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.659663244
Short name T364
Test name
Test status
Simulation time 148299268924 ps
CPU time 118.79 seconds
Started Mar 12 12:31:37 PM PDT 24
Finished Mar 12 12:33:36 PM PDT 24
Peak memory 183320 kb
Host smart-1f05b118-75ce-4ab7-973c-5d7006e27da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659663244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.659663244
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3890963554
Short name T243
Test name
Test status
Simulation time 449181913539 ps
CPU time 441.81 seconds
Started Mar 12 12:31:42 PM PDT 24
Finished Mar 12 12:39:04 PM PDT 24
Peak memory 191444 kb
Host smart-8ce61023-d2df-4f84-9067-d0b35d08a5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890963554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3890963554
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.362995546
Short name T176
Test name
Test status
Simulation time 1229899720931 ps
CPU time 638.94 seconds
Started Mar 12 12:31:26 PM PDT 24
Finished Mar 12 12:42:05 PM PDT 24
Peak memory 183284 kb
Host smart-12ba7ec2-274d-46e1-b5d9-07f5708f26a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362995546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.362995546
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.3774858711
Short name T367
Test name
Test status
Simulation time 21597817548 ps
CPU time 29.77 seconds
Started Mar 12 12:31:36 PM PDT 24
Finished Mar 12 12:32:06 PM PDT 24
Peak memory 183296 kb
Host smart-e6b5bff7-a265-415a-af56-4f948e3ae598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774858711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3774858711
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.798239849
Short name T250
Test name
Test status
Simulation time 133591218359 ps
CPU time 618.33 seconds
Started Mar 12 12:31:38 PM PDT 24
Finished Mar 12 12:41:57 PM PDT 24
Peak memory 191496 kb
Host smart-0c817640-5748-4fd2-b191-505842cf6987
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798239849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.798239849
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2883509945
Short name T43
Test name
Test status
Simulation time 112435393811 ps
CPU time 121.64 seconds
Started Mar 12 12:31:36 PM PDT 24
Finished Mar 12 12:33:38 PM PDT 24
Peak memory 191496 kb
Host smart-7e3119b5-e908-475d-b16a-56abbfb68b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883509945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2883509945
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_random.207155628
Short name T346
Test name
Test status
Simulation time 727682720999 ps
CPU time 838.26 seconds
Started Mar 12 12:31:32 PM PDT 24
Finished Mar 12 12:45:30 PM PDT 24
Peak memory 194616 kb
Host smart-f8d8b857-4980-4949-8f30-d5210efd9727
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207155628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.207155628
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.3408096872
Short name T143
Test name
Test status
Simulation time 118338855091 ps
CPU time 185.64 seconds
Started Mar 12 12:31:35 PM PDT 24
Finished Mar 12 12:34:41 PM PDT 24
Peak memory 191516 kb
Host smart-04108433-3caa-4cae-991c-6af33406ad0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408096872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.3408096872
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3949730688
Short name T342
Test name
Test status
Simulation time 508960289040 ps
CPU time 308.31 seconds
Started Mar 12 12:31:37 PM PDT 24
Finished Mar 12 12:36:46 PM PDT 24
Peak memory 183272 kb
Host smart-44009351-9c39-4d5b-9475-c6d10c85bc23
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949730688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3949730688
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3062508524
Short name T429
Test name
Test status
Simulation time 326162398873 ps
CPU time 140.01 seconds
Started Mar 12 12:31:40 PM PDT 24
Finished Mar 12 12:34:00 PM PDT 24
Peak memory 183272 kb
Host smart-7ea42515-de67-4abe-b114-d7d298e89c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062508524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3062508524
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.2998123460
Short name T338
Test name
Test status
Simulation time 89249319793 ps
CPU time 309.11 seconds
Started Mar 12 12:31:41 PM PDT 24
Finished Mar 12 12:36:51 PM PDT 24
Peak memory 191492 kb
Host smart-1e9c54e5-f2fe-47e2-b82f-a601ffa4f5e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998123460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2998123460
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.4217170554
Short name T275
Test name
Test status
Simulation time 35674987871 ps
CPU time 249.33 seconds
Started Mar 12 12:31:40 PM PDT 24
Finished Mar 12 12:35:50 PM PDT 24
Peak memory 191456 kb
Host smart-734bca0a-da58-4a20-94df-1dccb33b5792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217170554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.4217170554
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2855870260
Short name T345
Test name
Test status
Simulation time 51066293350 ps
CPU time 31.31 seconds
Started Mar 12 12:31:09 PM PDT 24
Finished Mar 12 12:31:41 PM PDT 24
Peak memory 183320 kb
Host smart-99a687e4-948c-439b-9fe5-f9648a4dffcd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855870260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.2855870260
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3481927180
Short name T381
Test name
Test status
Simulation time 259687897148 ps
CPU time 113.61 seconds
Started Mar 12 12:31:05 PM PDT 24
Finished Mar 12 12:32:59 PM PDT 24
Peak memory 183408 kb
Host smart-3fa7e8dc-b092-4b89-ac98-069061b92fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481927180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3481927180
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.1133256148
Short name T210
Test name
Test status
Simulation time 512680575378 ps
CPU time 2302.51 seconds
Started Mar 12 12:31:09 PM PDT 24
Finished Mar 12 01:09:32 PM PDT 24
Peak memory 191504 kb
Host smart-88f280b5-a46e-4b27-86a3-360a40be896d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133256148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.1133256148
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.4095445810
Short name T337
Test name
Test status
Simulation time 146351762527 ps
CPU time 85.77 seconds
Started Mar 12 12:31:11 PM PDT 24
Finished Mar 12 12:32:37 PM PDT 24
Peak memory 192960 kb
Host smart-3bc7085b-a99c-4e50-b420-455ef23790ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095445810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.4095445810
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2710150041
Short name T16
Test name
Test status
Simulation time 62866846 ps
CPU time 0.72 seconds
Started Mar 12 12:31:21 PM PDT 24
Finished Mar 12 12:31:22 PM PDT 24
Peak memory 213544 kb
Host smart-ad43b147-68f5-4427-8571-ec923d5c69d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710150041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2710150041
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1260476892
Short name T261
Test name
Test status
Simulation time 2962967687296 ps
CPU time 608.51 seconds
Started Mar 12 12:31:03 PM PDT 24
Finished Mar 12 12:41:12 PM PDT 24
Peak memory 196200 kb
Host smart-45776c1c-be84-4695-b857-ba24abe19466
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260476892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1260476892
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.1764463216
Short name T409
Test name
Test status
Simulation time 182094712050 ps
CPU time 152.24 seconds
Started Mar 12 12:31:36 PM PDT 24
Finished Mar 12 12:34:08 PM PDT 24
Peak memory 183392 kb
Host smart-2c4854ee-4afb-4b3a-8bec-f9fb5ff22d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764463216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1764463216
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3558319700
Short name T253
Test name
Test status
Simulation time 102883921852 ps
CPU time 686.29 seconds
Started Mar 12 12:31:46 PM PDT 24
Finished Mar 12 12:43:13 PM PDT 24
Peak memory 191468 kb
Host smart-96bbe3d8-352d-4de5-947a-250a892192c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558319700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3558319700
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.3795315025
Short name T150
Test name
Test status
Simulation time 114135927092 ps
CPU time 81.47 seconds
Started Mar 12 12:31:33 PM PDT 24
Finished Mar 12 12:32:55 PM PDT 24
Peak memory 183384 kb
Host smart-55f01147-f503-4e16-9121-e2620a4d6e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795315025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3795315025
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.946567456
Short name T404
Test name
Test status
Simulation time 174188449840 ps
CPU time 313.19 seconds
Started Mar 12 12:32:39 PM PDT 24
Finished Mar 12 12:37:52 PM PDT 24
Peak memory 183004 kb
Host smart-82228e6b-5bf8-4fc2-abfa-ee29ea12baed
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946567456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.rv_timer_cfg_update_on_fly.946567456
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.187203124
Short name T376
Test name
Test status
Simulation time 58879800426 ps
CPU time 63.2 seconds
Started Mar 12 12:32:39 PM PDT 24
Finished Mar 12 12:33:42 PM PDT 24
Peak memory 182920 kb
Host smart-5183aa4f-6971-496a-819d-97a2662e0c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187203124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.187203124
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.318268558
Short name T57
Test name
Test status
Simulation time 902576688630 ps
CPU time 399.02 seconds
Started Mar 12 12:32:39 PM PDT 24
Finished Mar 12 12:39:18 PM PDT 24
Peak memory 195480 kb
Host smart-92ceef6c-2992-44c0-a0d8-97742a5da8cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318268558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.
318268558
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2926798819
Short name T203
Test name
Test status
Simulation time 411631834557 ps
CPU time 323.94 seconds
Started Mar 12 12:31:39 PM PDT 24
Finished Mar 12 12:37:03 PM PDT 24
Peak memory 183452 kb
Host smart-2e1f9468-f998-4901-9124-177d3df82736
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926798819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2926798819
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.517511986
Short name T401
Test name
Test status
Simulation time 172533727956 ps
CPU time 248.33 seconds
Started Mar 12 12:31:36 PM PDT 24
Finished Mar 12 12:35:44 PM PDT 24
Peak memory 183316 kb
Host smart-4ed71a7d-380b-44e1-a084-f0217d1d63fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517511986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.517511986
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.3361862828
Short name T443
Test name
Test status
Simulation time 36467952001 ps
CPU time 18.95 seconds
Started Mar 12 12:31:29 PM PDT 24
Finished Mar 12 12:31:48 PM PDT 24
Peak memory 194476 kb
Host smart-bc167fa9-a468-47e5-a348-445299d9cb5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361862828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.3361862828
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.26132952
Short name T195
Test name
Test status
Simulation time 36346960506 ps
CPU time 44.25 seconds
Started Mar 12 12:31:31 PM PDT 24
Finished Mar 12 12:32:16 PM PDT 24
Peak memory 183316 kb
Host smart-3eb4e722-806f-45da-95ff-cda9fd438256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26132952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.26132952
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.775757299
Short name T389
Test name
Test status
Simulation time 34593768 ps
CPU time 0.51 seconds
Started Mar 12 12:31:40 PM PDT 24
Finished Mar 12 12:31:41 PM PDT 24
Peak memory 182140 kb
Host smart-14f77e5f-0a23-4fb2-80fc-025e20854311
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775757299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
775757299
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.1951701201
Short name T12
Test name
Test status
Simulation time 30356738080 ps
CPU time 320.75 seconds
Started Mar 12 12:31:53 PM PDT 24
Finished Mar 12 12:37:14 PM PDT 24
Peak memory 197996 kb
Host smart-c796efde-6b59-43c0-93c2-dc8c7b0fe54d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951701201 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.1951701201
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2324005280
Short name T297
Test name
Test status
Simulation time 1309641155505 ps
CPU time 588.49 seconds
Started Mar 12 12:31:47 PM PDT 24
Finished Mar 12 12:41:36 PM PDT 24
Peak memory 183356 kb
Host smart-9c2e72b7-8550-471c-8c0a-a262cf134d29
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324005280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2324005280
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3309661531
Short name T375
Test name
Test status
Simulation time 574191860408 ps
CPU time 241.86 seconds
Started Mar 12 12:31:34 PM PDT 24
Finished Mar 12 12:35:36 PM PDT 24
Peak memory 183332 kb
Host smart-401f9699-93d0-4b4f-83f1-f02d397b2396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309661531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3309661531
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.116977838
Short name T300
Test name
Test status
Simulation time 84070849679 ps
CPU time 1278.54 seconds
Started Mar 12 12:31:47 PM PDT 24
Finished Mar 12 12:53:06 PM PDT 24
Peak memory 193676 kb
Host smart-8401a660-a507-4351-913b-0d0b7744e50f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116977838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.116977838
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.1126364976
Short name T269
Test name
Test status
Simulation time 777669041593 ps
CPU time 620.57 seconds
Started Mar 12 12:31:38 PM PDT 24
Finished Mar 12 12:41:59 PM PDT 24
Peak memory 191508 kb
Host smart-44adcfe1-13f9-4304-b615-7720fada9854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126364976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1126364976
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1695942207
Short name T290
Test name
Test status
Simulation time 187464738335 ps
CPU time 337.62 seconds
Started Mar 12 12:31:36 PM PDT 24
Finished Mar 12 12:37:14 PM PDT 24
Peak memory 183268 kb
Host smart-8160f745-1680-42dc-9a3e-c6e0105c16d2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695942207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1695942207
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3191475952
Short name T59
Test name
Test status
Simulation time 21184393447 ps
CPU time 30.27 seconds
Started Mar 12 12:31:38 PM PDT 24
Finished Mar 12 12:32:08 PM PDT 24
Peak memory 183264 kb
Host smart-60c5f78c-d1d6-4234-9608-19acf7b1ecdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191475952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3191475952
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.2700203910
Short name T129
Test name
Test status
Simulation time 93708235184 ps
CPU time 150.38 seconds
Started Mar 12 12:31:55 PM PDT 24
Finished Mar 12 12:34:26 PM PDT 24
Peak memory 191456 kb
Host smart-18ef55e6-bdb4-4dd2-9c0b-c4eb87f77d93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700203910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2700203910
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.308256470
Short name T193
Test name
Test status
Simulation time 154894269634 ps
CPU time 711.51 seconds
Started Mar 12 12:31:52 PM PDT 24
Finished Mar 12 12:43:44 PM PDT 24
Peak memory 183212 kb
Host smart-f34fb59a-adb9-4483-bd68-a6c41034202d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308256470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.308256470
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1045094071
Short name T175
Test name
Test status
Simulation time 1139854985653 ps
CPU time 1897.44 seconds
Started Mar 12 12:31:36 PM PDT 24
Finished Mar 12 01:03:14 PM PDT 24
Peak memory 191508 kb
Host smart-76256553-c9fc-4dfd-8b62-f3caf4ca1120
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045094071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1045094071
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.280694805
Short name T310
Test name
Test status
Simulation time 790308846491 ps
CPU time 700.06 seconds
Started Mar 12 12:31:50 PM PDT 24
Finished Mar 12 12:43:30 PM PDT 24
Peak memory 183284 kb
Host smart-002d252f-883d-43f6-8bc2-988bb43e5097
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280694805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.280694805
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.4120976492
Short name T377
Test name
Test status
Simulation time 101809605973 ps
CPU time 153.96 seconds
Started Mar 12 12:31:41 PM PDT 24
Finished Mar 12 12:34:15 PM PDT 24
Peak memory 183308 kb
Host smart-f6552f50-42fd-474d-9f39-dabeb366b8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120976492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.4120976492
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.2573999650
Short name T105
Test name
Test status
Simulation time 112312988372 ps
CPU time 202.84 seconds
Started Mar 12 12:31:41 PM PDT 24
Finished Mar 12 12:35:04 PM PDT 24
Peak memory 191456 kb
Host smart-79983732-ed3e-40f7-9b91-72fe87c604aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573999650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2573999650
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3370792973
Short name T421
Test name
Test status
Simulation time 258467376492 ps
CPU time 91.99 seconds
Started Mar 12 12:31:51 PM PDT 24
Finished Mar 12 12:33:23 PM PDT 24
Peak memory 183324 kb
Host smart-ea0e40d7-6b72-4575-93b9-04307c519646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370792973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3370792973
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.323962062
Short name T251
Test name
Test status
Simulation time 755163199298 ps
CPU time 457.6 seconds
Started Mar 12 12:31:37 PM PDT 24
Finished Mar 12 12:39:15 PM PDT 24
Peak memory 191632 kb
Host smart-68e2b4e8-8724-43e2-b99e-6df0ad328a36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323962062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.
323962062
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.1813378357
Short name T36
Test name
Test status
Simulation time 31829610863 ps
CPU time 252.63 seconds
Started Mar 12 12:31:39 PM PDT 24
Finished Mar 12 12:35:51 PM PDT 24
Peak memory 206124 kb
Host smart-6c25cf7a-aa8b-4644-ad57-a3b92e36cc77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813378357 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.1813378357
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3724238737
Short name T380
Test name
Test status
Simulation time 1384015584405 ps
CPU time 340.3 seconds
Started Mar 12 12:31:40 PM PDT 24
Finished Mar 12 12:37:20 PM PDT 24
Peak memory 183288 kb
Host smart-5ea6d34d-18e9-4a74-9dd8-e2c38cf118fc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724238737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3724238737
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.2844861375
Short name T355
Test name
Test status
Simulation time 59504885232 ps
CPU time 86.47 seconds
Started Mar 12 12:31:38 PM PDT 24
Finished Mar 12 12:33:05 PM PDT 24
Peak memory 183264 kb
Host smart-16ab8a4a-b8f6-40de-9264-6b330e3de176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844861375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2844861375
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.863212123
Short name T305
Test name
Test status
Simulation time 606066011819 ps
CPU time 310.48 seconds
Started Mar 12 12:31:47 PM PDT 24
Finished Mar 12 12:36:58 PM PDT 24
Peak memory 191508 kb
Host smart-94a5a18f-1e65-4fce-aa5e-8d1f49922a92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863212123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.863212123
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2324528746
Short name T140
Test name
Test status
Simulation time 210149786950 ps
CPU time 215.29 seconds
Started Mar 12 12:31:59 PM PDT 24
Finished Mar 12 12:35:34 PM PDT 24
Peak memory 191644 kb
Host smart-e002c141-730d-400e-9215-4fcf75f4f5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324528746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2324528746
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.1612535358
Short name T26
Test name
Test status
Simulation time 827791462466 ps
CPU time 762.08 seconds
Started Mar 12 12:31:55 PM PDT 24
Finished Mar 12 12:44:37 PM PDT 24
Peak memory 191464 kb
Host smart-ebd874a1-e6d4-4c08-8a1f-f877cc5b381f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612535358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.1612535358
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.532175035
Short name T141
Test name
Test status
Simulation time 18931831191 ps
CPU time 10.2 seconds
Started Mar 12 12:31:35 PM PDT 24
Finished Mar 12 12:31:45 PM PDT 24
Peak memory 183404 kb
Host smart-2f1aaaa7-e28d-41b1-9935-f81af17cfd02
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532175035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.rv_timer_cfg_update_on_fly.532175035
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2236658847
Short name T366
Test name
Test status
Simulation time 468067948035 ps
CPU time 195.8 seconds
Started Mar 12 12:31:40 PM PDT 24
Finished Mar 12 12:34:56 PM PDT 24
Peak memory 183332 kb
Host smart-a43c2753-e5a6-411a-a2b5-f881bbeac679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236658847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2236658847
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.41891216
Short name T384
Test name
Test status
Simulation time 3179114682 ps
CPU time 6.39 seconds
Started Mar 12 12:31:48 PM PDT 24
Finished Mar 12 12:31:55 PM PDT 24
Peak memory 191444 kb
Host smart-6bf897b9-86a9-47fa-813d-6358d720a621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41891216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.41891216
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3014828900
Short name T209
Test name
Test status
Simulation time 970961866701 ps
CPU time 572.48 seconds
Started Mar 12 12:31:52 PM PDT 24
Finished Mar 12 12:41:25 PM PDT 24
Peak memory 191440 kb
Host smart-6802e76d-26f0-4b75-85de-05c9745311d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014828900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3014828900
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1886535813
Short name T246
Test name
Test status
Simulation time 1075144001000 ps
CPU time 493.08 seconds
Started Mar 12 12:31:48 PM PDT 24
Finished Mar 12 12:40:02 PM PDT 24
Peak memory 183288 kb
Host smart-1a19ee16-b005-4494-85ff-79dd8dd7c777
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886535813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.1886535813
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1543973946
Short name T436
Test name
Test status
Simulation time 263968519393 ps
CPU time 202.09 seconds
Started Mar 12 12:32:53 PM PDT 24
Finished Mar 12 12:36:15 PM PDT 24
Peak memory 182992 kb
Host smart-6b8bdbef-1079-4252-a093-176741099746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543973946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1543973946
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2448883504
Short name T402
Test name
Test status
Simulation time 75420345 ps
CPU time 0.6 seconds
Started Mar 12 12:31:51 PM PDT 24
Finished Mar 12 12:31:52 PM PDT 24
Peak memory 182744 kb
Host smart-c13361b0-cf5d-432f-b1fd-9d2c06058790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448883504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2448883504
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2644302401
Short name T53
Test name
Test status
Simulation time 841870396135 ps
CPU time 403.24 seconds
Started Mar 12 12:31:40 PM PDT 24
Finished Mar 12 12:38:23 PM PDT 24
Peak memory 191504 kb
Host smart-00fa29e3-63d4-432e-bf12-3df3a714a416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644302401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2644302401
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.3439438702
Short name T39
Test name
Test status
Simulation time 80972764429 ps
CPU time 482.91 seconds
Started Mar 12 12:31:51 PM PDT 24
Finished Mar 12 12:39:54 PM PDT 24
Peak memory 206076 kb
Host smart-d1a35714-29e5-481b-9d31-bf52edbeb605
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439438702 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.3439438702
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3064785045
Short name T382
Test name
Test status
Simulation time 68749977385 ps
CPU time 96.59 seconds
Started Mar 12 12:31:40 PM PDT 24
Finished Mar 12 12:33:17 PM PDT 24
Peak memory 183328 kb
Host smart-6ea8bd76-4786-4405-b5ea-2c4253bda36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064785045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3064785045
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.2841730557
Short name T204
Test name
Test status
Simulation time 318354965035 ps
CPU time 398.33 seconds
Started Mar 12 12:31:39 PM PDT 24
Finished Mar 12 12:38:17 PM PDT 24
Peak memory 191488 kb
Host smart-df183ef7-142c-4ef6-999c-a217bc7f4da2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841730557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2841730557
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1441141273
Short name T425
Test name
Test status
Simulation time 70119152675 ps
CPU time 70.3 seconds
Started Mar 12 12:31:40 PM PDT 24
Finished Mar 12 12:32:50 PM PDT 24
Peak memory 183308 kb
Host smart-742110ee-9b6e-42cf-92b0-7f44c3601303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441141273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1441141273
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.2152844918
Short name T400
Test name
Test status
Simulation time 1258093191013 ps
CPU time 507.26 seconds
Started Mar 12 12:32:00 PM PDT 24
Finished Mar 12 12:40:27 PM PDT 24
Peak memory 195176 kb
Host smart-d9fb8117-da83-4406-b366-1bf28d14e451
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152844918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.2152844918
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.723183833
Short name T120
Test name
Test status
Simulation time 30982775255 ps
CPU time 16.57 seconds
Started Mar 12 12:30:59 PM PDT 24
Finished Mar 12 12:31:16 PM PDT 24
Peak memory 183296 kb
Host smart-612729f2-6217-448b-a7a5-a4a76ca6567a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723183833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.rv_timer_cfg_update_on_fly.723183833
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_random.3812424708
Short name T278
Test name
Test status
Simulation time 103954509946 ps
CPU time 216.1 seconds
Started Mar 12 12:31:13 PM PDT 24
Finished Mar 12 12:34:49 PM PDT 24
Peak memory 191460 kb
Host smart-609545d4-e527-41ce-bc67-cec7c11a96cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812424708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3812424708
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.288069662
Short name T354
Test name
Test status
Simulation time 16451079983 ps
CPU time 12.74 seconds
Started Mar 12 12:31:08 PM PDT 24
Finished Mar 12 12:31:21 PM PDT 24
Peak memory 183432 kb
Host smart-7ef6c7d7-c4ee-4f23-9d72-7f3d6ac6946b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288069662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.288069662
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3226142303
Short name T262
Test name
Test status
Simulation time 257995591666 ps
CPU time 271.17 seconds
Started Mar 12 12:32:14 PM PDT 24
Finished Mar 12 12:36:45 PM PDT 24
Peak memory 191160 kb
Host smart-0643d8a4-8759-4ce6-ba2e-ddecb119d9b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226142303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3226142303
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.2023167854
Short name T395
Test name
Test status
Simulation time 8567890706 ps
CPU time 15.91 seconds
Started Mar 12 12:31:45 PM PDT 24
Finished Mar 12 12:32:01 PM PDT 24
Peak memory 183312 kb
Host smart-bb71491c-76e0-449a-ab72-2f4639884cec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023167854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2023167854
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.1377103396
Short name T183
Test name
Test status
Simulation time 98554775759 ps
CPU time 165.34 seconds
Started Mar 12 12:31:38 PM PDT 24
Finished Mar 12 12:34:24 PM PDT 24
Peak memory 191520 kb
Host smart-a025b9bf-d318-4f1a-b2c0-881a01325569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377103396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1377103396
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.3392194651
Short name T106
Test name
Test status
Simulation time 163618115292 ps
CPU time 2059.21 seconds
Started Mar 12 12:31:46 PM PDT 24
Finished Mar 12 01:06:05 PM PDT 24
Peak memory 193672 kb
Host smart-ef2f066c-ee2a-41b3-8cfb-9dcb510b65cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392194651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3392194651
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.3922058569
Short name T268
Test name
Test status
Simulation time 33517641664 ps
CPU time 66.42 seconds
Started Mar 12 12:31:52 PM PDT 24
Finished Mar 12 12:32:59 PM PDT 24
Peak memory 183312 kb
Host smart-aac202ac-c099-4907-b097-6aa78a192887
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922058569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3922058569
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.2367494720
Short name T371
Test name
Test status
Simulation time 177207734691 ps
CPU time 251.34 seconds
Started Mar 12 12:31:42 PM PDT 24
Finished Mar 12 12:35:54 PM PDT 24
Peak memory 191500 kb
Host smart-f2170f8c-7e24-4aa4-a3ef-91f90c2144b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367494720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2367494720
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.486574942
Short name T299
Test name
Test status
Simulation time 47846639611 ps
CPU time 31.19 seconds
Started Mar 12 12:31:44 PM PDT 24
Finished Mar 12 12:32:15 PM PDT 24
Peak memory 183312 kb
Host smart-2fca6091-6af8-4544-bd33-9e405532d649
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486574942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.486574942
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.251492631
Short name T227
Test name
Test status
Simulation time 82491376964 ps
CPU time 227.86 seconds
Started Mar 12 12:31:37 PM PDT 24
Finished Mar 12 12:35:25 PM PDT 24
Peak memory 191584 kb
Host smart-fa419893-f64b-48b1-89b5-734f0603da2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251492631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.251492631
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.117105986
Short name T232
Test name
Test status
Simulation time 156531405143 ps
CPU time 337.67 seconds
Started Mar 12 12:31:46 PM PDT 24
Finished Mar 12 12:37:24 PM PDT 24
Peak memory 191512 kb
Host smart-d1eba490-4a49-4d87-9c77-652c87fe7b3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117105986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.117105986
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.250141714
Short name T333
Test name
Test status
Simulation time 1613552699959 ps
CPU time 919.76 seconds
Started Mar 12 12:31:12 PM PDT 24
Finished Mar 12 12:46:33 PM PDT 24
Peak memory 183276 kb
Host smart-e869c03b-5c5b-41b5-bca0-58badc8130cd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250141714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.250141714
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.1873458498
Short name T362
Test name
Test status
Simulation time 100598757891 ps
CPU time 136.89 seconds
Started Mar 12 12:31:13 PM PDT 24
Finished Mar 12 12:33:30 PM PDT 24
Peak memory 183344 kb
Host smart-81331441-c38e-4803-ae0f-70bf9d0f9811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873458498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1873458498
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.1916962058
Short name T48
Test name
Test status
Simulation time 70620087376 ps
CPU time 152.55 seconds
Started Mar 12 12:31:06 PM PDT 24
Finished Mar 12 12:33:39 PM PDT 24
Peak memory 191512 kb
Host smart-90c85086-f2b7-467b-8183-04af0aa32774
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916962058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1916962058
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2673313482
Short name T276
Test name
Test status
Simulation time 91266803032 ps
CPU time 35.5 seconds
Started Mar 12 12:31:10 PM PDT 24
Finished Mar 12 12:31:45 PM PDT 24
Peak memory 192908 kb
Host smart-7398426f-dd7b-4b57-bf50-1c607fabe3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673313482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2673313482
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1984523105
Short name T393
Test name
Test status
Simulation time 619425598005 ps
CPU time 475.38 seconds
Started Mar 12 12:32:08 PM PDT 24
Finished Mar 12 12:40:05 PM PDT 24
Peak memory 190360 kb
Host smart-3eaafc70-0b4f-4f40-b060-70f0e1d882c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984523105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1984523105
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.2682351155
Short name T130
Test name
Test status
Simulation time 36770361879 ps
CPU time 215.16 seconds
Started Mar 12 12:31:53 PM PDT 24
Finished Mar 12 12:35:28 PM PDT 24
Peak memory 183356 kb
Host smart-df438888-f485-4380-8cb6-cb1e28620599
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682351155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2682351155
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.4286067156
Short name T135
Test name
Test status
Simulation time 530233560562 ps
CPU time 310.31 seconds
Started Mar 12 12:31:41 PM PDT 24
Finished Mar 12 12:36:52 PM PDT 24
Peak memory 191496 kb
Host smart-e4ab44b7-4ed8-492f-b356-8ff7cf2e151c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286067156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.4286067156
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.2680197751
Short name T1
Test name
Test status
Simulation time 68259333712 ps
CPU time 299.2 seconds
Started Mar 12 12:31:37 PM PDT 24
Finished Mar 12 12:36:36 PM PDT 24
Peak memory 191504 kb
Host smart-321b58fa-c349-4ad9-8f53-6507c3ca55fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680197751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2680197751
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.3010336451
Short name T444
Test name
Test status
Simulation time 698638294690 ps
CPU time 211.61 seconds
Started Mar 12 12:31:46 PM PDT 24
Finished Mar 12 12:35:18 PM PDT 24
Peak memory 191428 kb
Host smart-0bbed7ee-1266-457f-a124-937840559cf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010336451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.3010336451
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1434438024
Short name T298
Test name
Test status
Simulation time 247851097535 ps
CPU time 142.59 seconds
Started Mar 12 12:31:40 PM PDT 24
Finished Mar 12 12:34:03 PM PDT 24
Peak memory 193748 kb
Host smart-4f43f569-63d4-4718-82bb-4bbb5c7738b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434438024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1434438024
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3339899738
Short name T119
Test name
Test status
Simulation time 481906708537 ps
CPU time 1048.93 seconds
Started Mar 12 12:31:37 PM PDT 24
Finished Mar 12 12:49:06 PM PDT 24
Peak memory 191504 kb
Host smart-f4a6d107-8db9-42b9-9b63-d65b7f41610e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339899738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3339899738
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.2483216461
Short name T23
Test name
Test status
Simulation time 1393372790104 ps
CPU time 708.09 seconds
Started Mar 12 12:31:16 PM PDT 24
Finished Mar 12 12:43:05 PM PDT 24
Peak memory 183256 kb
Host smart-96963e6f-04a0-4572-bb82-3c42a46393a1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483216461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.2483216461
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3966713612
Short name T46
Test name
Test status
Simulation time 418261407649 ps
CPU time 77.52 seconds
Started Mar 12 12:32:08 PM PDT 24
Finished Mar 12 12:33:27 PM PDT 24
Peak memory 182124 kb
Host smart-840a769b-edd1-463d-8d0f-460281876a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966713612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3966713612
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.1581953090
Short name T308
Test name
Test status
Simulation time 42416279132 ps
CPU time 38.93 seconds
Started Mar 12 12:31:11 PM PDT 24
Finished Mar 12 12:31:50 PM PDT 24
Peak memory 183352 kb
Host smart-367937af-f404-44e8-ad4f-6258a558246c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581953090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1581953090
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.3000506026
Short name T249
Test name
Test status
Simulation time 255168571106 ps
CPU time 204.14 seconds
Started Mar 12 12:31:21 PM PDT 24
Finished Mar 12 12:34:45 PM PDT 24
Peak memory 191548 kb
Host smart-1d5bdfad-9c21-4418-a314-9562387ed50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000506026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3000506026
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.2737099911
Short name T267
Test name
Test status
Simulation time 205070461075 ps
CPU time 391.32 seconds
Started Mar 12 12:31:37 PM PDT 24
Finished Mar 12 12:38:08 PM PDT 24
Peak memory 191508 kb
Host smart-33a799cd-9edf-48aa-8c1f-6487e8bc9c6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737099911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.2737099911
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.3123762312
Short name T169
Test name
Test status
Simulation time 97396861136 ps
CPU time 85.21 seconds
Started Mar 12 12:31:42 PM PDT 24
Finished Mar 12 12:33:07 PM PDT 24
Peak memory 191584 kb
Host smart-28ef657e-c4f0-4745-abff-66eee7b893a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123762312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3123762312
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.3489153085
Short name T99
Test name
Test status
Simulation time 313507108108 ps
CPU time 619.25 seconds
Started Mar 12 12:31:47 PM PDT 24
Finished Mar 12 12:42:06 PM PDT 24
Peak memory 191424 kb
Host smart-b755d575-568e-4755-8941-dc95548b2db1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489153085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3489153085
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.595615999
Short name T156
Test name
Test status
Simulation time 93791731409 ps
CPU time 183.58 seconds
Started Mar 12 12:31:39 PM PDT 24
Finished Mar 12 12:34:43 PM PDT 24
Peak memory 191504 kb
Host smart-afb70b14-b46a-4629-9c96-a50f6190d5ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595615999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.595615999
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3757931360
Short name T21
Test name
Test status
Simulation time 81154106026 ps
CPU time 106.99 seconds
Started Mar 12 12:31:51 PM PDT 24
Finished Mar 12 12:33:38 PM PDT 24
Peak memory 191508 kb
Host smart-653c68c1-8b40-4f53-b17c-4358f268cab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757931360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3757931360
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.2733639078
Short name T446
Test name
Test status
Simulation time 48335133994 ps
CPU time 48.78 seconds
Started Mar 12 12:31:37 PM PDT 24
Finished Mar 12 12:32:26 PM PDT 24
Peak memory 191512 kb
Host smart-9ea8c4ea-bb48-4281-8c5e-a814808d2828
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733639078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.2733639078
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3772614788
Short name T162
Test name
Test status
Simulation time 139385016844 ps
CPU time 841.98 seconds
Started Mar 12 12:31:47 PM PDT 24
Finished Mar 12 12:45:50 PM PDT 24
Peak memory 191628 kb
Host smart-d37a3bd9-47d4-422d-8b67-7ee0f9a72e8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772614788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3772614788
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3146317450
Short name T191
Test name
Test status
Simulation time 236637575850 ps
CPU time 630.66 seconds
Started Mar 12 12:31:45 PM PDT 24
Finished Mar 12 12:42:16 PM PDT 24
Peak memory 183328 kb
Host smart-6bf2f2d9-e235-455e-99ec-f1c7e14188df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146317450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3146317450
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.727377895
Short name T422
Test name
Test status
Simulation time 214661489303 ps
CPU time 251.43 seconds
Started Mar 12 12:31:53 PM PDT 24
Finished Mar 12 12:36:05 PM PDT 24
Peak memory 191524 kb
Host smart-942f3fe8-dc7f-486d-b4f3-562d38295573
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727377895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.727377895
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.987547036
Short name T212
Test name
Test status
Simulation time 509620982990 ps
CPU time 308.71 seconds
Started Mar 12 12:31:13 PM PDT 24
Finished Mar 12 12:36:22 PM PDT 24
Peak memory 183276 kb
Host smart-88b1136b-5b33-423d-b855-6c0bc089f8e6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987547036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.rv_timer_cfg_update_on_fly.987547036
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.1366952628
Short name T415
Test name
Test status
Simulation time 30306295230 ps
CPU time 42.79 seconds
Started Mar 12 12:31:10 PM PDT 24
Finished Mar 12 12:31:53 PM PDT 24
Peak memory 183260 kb
Host smart-6d90316f-9913-4338-b569-590f1e2b46e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366952628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.1366952628
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3711883238
Short name T329
Test name
Test status
Simulation time 140675213780 ps
CPU time 594.62 seconds
Started Mar 12 12:30:59 PM PDT 24
Finished Mar 12 12:40:54 PM PDT 24
Peak memory 191528 kb
Host smart-9c98d922-da3d-437b-a52b-db184b91d470
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711883238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3711883238
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.2375728230
Short name T217
Test name
Test status
Simulation time 103951935503 ps
CPU time 211.43 seconds
Started Mar 12 12:32:14 PM PDT 24
Finished Mar 12 12:35:45 PM PDT 24
Peak memory 191148 kb
Host smart-b49db7fe-f9f2-46b9-86f1-75f6b5938907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375728230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2375728230
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2402839800
Short name T190
Test name
Test status
Simulation time 670815376699 ps
CPU time 394.34 seconds
Started Mar 12 12:31:09 PM PDT 24
Finished Mar 12 12:37:44 PM PDT 24
Peak memory 191456 kb
Host smart-15729d2f-224f-413d-a613-457be536cdc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402839800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2402839800
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.1942146815
Short name T131
Test name
Test status
Simulation time 32550760828 ps
CPU time 35.89 seconds
Started Mar 12 12:31:51 PM PDT 24
Finished Mar 12 12:32:27 PM PDT 24
Peak memory 183232 kb
Host smart-2ffbff20-4d51-4334-a98e-a3c6762beca9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942146815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.1942146815
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1110456051
Short name T112
Test name
Test status
Simulation time 30439445539 ps
CPU time 44.64 seconds
Started Mar 12 12:31:58 PM PDT 24
Finished Mar 12 12:32:43 PM PDT 24
Peak memory 191436 kb
Host smart-fc8ebe9b-b835-44f2-96f6-ab3875b502ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110456051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1110456051
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1683621898
Short name T139
Test name
Test status
Simulation time 424310183370 ps
CPU time 663.04 seconds
Started Mar 12 12:31:54 PM PDT 24
Finished Mar 12 12:42:58 PM PDT 24
Peak memory 191528 kb
Host smart-8664f071-c5ad-4945-8c8b-cf58ca7e4de0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683621898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1683621898
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1799165113
Short name T293
Test name
Test status
Simulation time 32798877321 ps
CPU time 83.71 seconds
Started Mar 12 12:31:45 PM PDT 24
Finished Mar 12 12:33:08 PM PDT 24
Peak memory 183384 kb
Host smart-853e974d-af8a-4618-a786-dc432c115124
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799165113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1799165113
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2764269623
Short name T319
Test name
Test status
Simulation time 243365839630 ps
CPU time 457.28 seconds
Started Mar 12 12:31:44 PM PDT 24
Finished Mar 12 12:39:21 PM PDT 24
Peak memory 191500 kb
Host smart-a855332c-c1b2-47c1-aee5-0a60a95960cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764269623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2764269623
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.186871478
Short name T291
Test name
Test status
Simulation time 200051536016 ps
CPU time 386.92 seconds
Started Mar 12 12:32:03 PM PDT 24
Finished Mar 12 12:38:30 PM PDT 24
Peak memory 193704 kb
Host smart-403afc17-6bac-4d09-884a-89f46cc74150
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186871478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.186871478
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.430082322
Short name T202
Test name
Test status
Simulation time 218018661626 ps
CPU time 455.94 seconds
Started Mar 12 12:31:40 PM PDT 24
Finished Mar 12 12:39:16 PM PDT 24
Peak memory 194668 kb
Host smart-0a81438f-2ba8-4e17-a17b-5b64df45399b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430082322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.430082322
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.112794325
Short name T165
Test name
Test status
Simulation time 48268667100 ps
CPU time 104.32 seconds
Started Mar 12 12:32:08 PM PDT 24
Finished Mar 12 12:33:53 PM PDT 24
Peak memory 191492 kb
Host smart-29431a4f-2a49-4242-8c7d-a85526becb81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112794325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.112794325
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.3466356999
Short name T316
Test name
Test status
Simulation time 280183320819 ps
CPU time 582.35 seconds
Started Mar 12 12:32:06 PM PDT 24
Finished Mar 12 12:41:49 PM PDT 24
Peak memory 192632 kb
Host smart-4ef9e3e4-aa2b-4bd2-a7a1-300e4ab42a37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466356999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3466356999
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.778534183
Short name T266
Test name
Test status
Simulation time 573899499291 ps
CPU time 357.98 seconds
Started Mar 12 12:31:18 PM PDT 24
Finished Mar 12 12:37:16 PM PDT 24
Peak memory 183344 kb
Host smart-732311db-a6e0-4dc4-840c-8871e91defb4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778534183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.rv_timer_cfg_update_on_fly.778534183
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.3400125443
Short name T369
Test name
Test status
Simulation time 320536729019 ps
CPU time 167.97 seconds
Started Mar 12 12:31:14 PM PDT 24
Finished Mar 12 12:34:02 PM PDT 24
Peak memory 183320 kb
Host smart-a0d9fe31-6e54-4163-a59a-d630ddaa7cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400125443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.3400125443
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2697864256
Short name T361
Test name
Test status
Simulation time 126057647 ps
CPU time 0.73 seconds
Started Mar 12 12:31:13 PM PDT 24
Finished Mar 12 12:31:14 PM PDT 24
Peak memory 182964 kb
Host smart-749ad328-bf98-4fa6-9b39-de5553d8924f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697864256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2697864256
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3123093690
Short name T180
Test name
Test status
Simulation time 273632618395 ps
CPU time 398.72 seconds
Started Mar 12 12:31:08 PM PDT 24
Finished Mar 12 12:37:48 PM PDT 24
Peak memory 195184 kb
Host smart-957fbaf4-fcb8-42f9-9767-b2e2873c8fd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123093690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3123093690
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.4274838599
Short name T200
Test name
Test status
Simulation time 123734451359 ps
CPU time 349.04 seconds
Started Mar 12 12:31:49 PM PDT 24
Finished Mar 12 12:37:38 PM PDT 24
Peak memory 191508 kb
Host smart-9b76af29-a476-4e28-bf57-71e8f225a766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274838599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.4274838599
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1413641470
Short name T287
Test name
Test status
Simulation time 80554808503 ps
CPU time 28.99 seconds
Started Mar 12 12:31:53 PM PDT 24
Finished Mar 12 12:32:22 PM PDT 24
Peak memory 183116 kb
Host smart-11bde3c8-b162-475d-a028-b43f54e92acb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413641470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1413641470
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.2939703952
Short name T449
Test name
Test status
Simulation time 1705032969743 ps
CPU time 630.49 seconds
Started Mar 12 12:31:49 PM PDT 24
Finished Mar 12 12:42:20 PM PDT 24
Peak memory 191588 kb
Host smart-24ecd1d1-1d85-4091-b1d5-25c5e60aa9bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939703952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2939703952
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1019219490
Short name T412
Test name
Test status
Simulation time 34966470202 ps
CPU time 52.74 seconds
Started Mar 12 12:31:58 PM PDT 24
Finished Mar 12 12:32:51 PM PDT 24
Peak memory 183308 kb
Host smart-e7c3a461-e8d6-4d69-b86a-ae442a50bf17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019219490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1019219490
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.2884205766
Short name T201
Test name
Test status
Simulation time 176017983804 ps
CPU time 218.72 seconds
Started Mar 12 12:31:56 PM PDT 24
Finished Mar 12 12:35:35 PM PDT 24
Peak memory 191500 kb
Host smart-0bcf8811-a3ab-4d94-9f87-c01e6ebe087a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884205766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.2884205766
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.2632426278
Short name T439
Test name
Test status
Simulation time 26228941365 ps
CPU time 29.1 seconds
Started Mar 12 12:31:50 PM PDT 24
Finished Mar 12 12:32:20 PM PDT 24
Peak memory 183300 kb
Host smart-57513fc2-90fb-45eb-9a1b-3e640a69c9b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632426278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2632426278
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.3387940940
Short name T104
Test name
Test status
Simulation time 38781391815 ps
CPU time 66.63 seconds
Started Mar 12 12:31:50 PM PDT 24
Finished Mar 12 12:32:57 PM PDT 24
Peak memory 183444 kb
Host smart-8eb90402-93de-4394-b961-ce96480cd361
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387940940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3387940940
Directory /workspace/97.rv_timer_random/latest
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