Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 574
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T509 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2364598395 Mar 14 12:26:49 PM PDT 24 Mar 14 12:26:50 PM PDT 24 134230941 ps
T510 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1409144063 Mar 14 12:26:29 PM PDT 24 Mar 14 12:26:29 PM PDT 24 42602380 ps
T511 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3323450634 Mar 14 12:26:45 PM PDT 24 Mar 14 12:26:46 PM PDT 24 14317164 ps
T512 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.503089439 Mar 14 12:26:32 PM PDT 24 Mar 14 12:26:32 PM PDT 24 12701794 ps
T513 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3255373838 Mar 14 12:23:18 PM PDT 24 Mar 14 12:23:20 PM PDT 24 144236131 ps
T514 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3139658159 Mar 14 12:26:41 PM PDT 24 Mar 14 12:26:42 PM PDT 24 91202259 ps
T515 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1678322090 Mar 14 12:26:51 PM PDT 24 Mar 14 12:26:53 PM PDT 24 178098780 ps
T516 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2922311257 Mar 14 12:26:07 PM PDT 24 Mar 14 12:26:08 PM PDT 24 92931880 ps
T517 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3091630174 Mar 14 12:26:32 PM PDT 24 Mar 14 12:26:32 PM PDT 24 14467226 ps
T518 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3524838357 Mar 14 12:26:33 PM PDT 24 Mar 14 12:26:35 PM PDT 24 17227713 ps
T519 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3012779725 Mar 14 12:26:24 PM PDT 24 Mar 14 12:26:26 PM PDT 24 98230961 ps
T520 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.4256765537 Mar 14 12:26:22 PM PDT 24 Mar 14 12:26:23 PM PDT 24 90825563 ps
T101 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3475234402 Mar 14 12:26:16 PM PDT 24 Mar 14 12:26:18 PM PDT 24 26085179 ps
T521 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3572929878 Mar 14 12:26:23 PM PDT 24 Mar 14 12:26:24 PM PDT 24 417453536 ps
T522 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2837487177 Mar 14 12:26:27 PM PDT 24 Mar 14 12:26:28 PM PDT 24 89886733 ps
T523 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3182540992 Mar 14 12:26:34 PM PDT 24 Mar 14 12:26:35 PM PDT 24 24201965 ps
T524 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1588017032 Mar 14 12:26:53 PM PDT 24 Mar 14 12:26:53 PM PDT 24 31734125 ps
T525 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1138013803 Mar 14 12:26:25 PM PDT 24 Mar 14 12:26:28 PM PDT 24 49121551 ps
T526 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2544497453 Mar 14 12:26:45 PM PDT 24 Mar 14 12:26:46 PM PDT 24 21734291 ps
T527 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2335486426 Mar 14 12:26:44 PM PDT 24 Mar 14 12:26:45 PM PDT 24 70035931 ps
T528 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3796779589 Mar 14 12:26:34 PM PDT 24 Mar 14 12:26:35 PM PDT 24 54050372 ps
T529 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.783386608 Mar 14 12:26:32 PM PDT 24 Mar 14 12:26:33 PM PDT 24 17501609 ps
T530 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3210355199 Mar 14 12:26:44 PM PDT 24 Mar 14 12:26:45 PM PDT 24 17370244 ps
T531 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.4168874162 Mar 14 12:26:34 PM PDT 24 Mar 14 12:26:36 PM PDT 24 14975655 ps
T532 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3063209890 Mar 14 12:26:19 PM PDT 24 Mar 14 12:26:20 PM PDT 24 23426152 ps
T533 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2629578921 Mar 14 12:26:42 PM PDT 24 Mar 14 12:26:42 PM PDT 24 34208688 ps
T103 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1309566174 Mar 14 12:26:19 PM PDT 24 Mar 14 12:26:21 PM PDT 24 121772022 ps
T102 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.4191563373 Mar 14 12:26:19 PM PDT 24 Mar 14 12:26:20 PM PDT 24 32454395 ps
T534 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1072074154 Mar 14 12:26:43 PM PDT 24 Mar 14 12:26:47 PM PDT 24 282787199 ps
T535 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1631282020 Mar 14 12:26:24 PM PDT 24 Mar 14 12:26:26 PM PDT 24 362056423 ps
T536 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1283476339 Mar 14 12:26:30 PM PDT 24 Mar 14 12:26:31 PM PDT 24 79506292 ps
T537 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.450598688 Mar 14 12:26:24 PM PDT 24 Mar 14 12:26:25 PM PDT 24 189031566 ps
T104 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.4053613338 Mar 14 12:26:41 PM PDT 24 Mar 14 12:26:41 PM PDT 24 17338286 ps
T538 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.936852854 Mar 14 12:26:38 PM PDT 24 Mar 14 12:26:41 PM PDT 24 711934547 ps
T539 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.441608355 Mar 14 12:26:31 PM PDT 24 Mar 14 12:26:32 PM PDT 24 194242451 ps
T540 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3478489345 Mar 14 12:26:40 PM PDT 24 Mar 14 12:26:41 PM PDT 24 305731825 ps
T541 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3226685156 Mar 14 12:26:28 PM PDT 24 Mar 14 12:26:28 PM PDT 24 143875620 ps
T542 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.570252569 Mar 14 12:26:54 PM PDT 24 Mar 14 12:26:55 PM PDT 24 83883483 ps
T543 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2301720320 Mar 14 12:26:29 PM PDT 24 Mar 14 12:26:30 PM PDT 24 26767790 ps
T544 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3820404141 Mar 14 12:26:29 PM PDT 24 Mar 14 12:26:30 PM PDT 24 55325725 ps
T545 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.746130430 Mar 14 12:26:26 PM PDT 24 Mar 14 12:26:28 PM PDT 24 66060890 ps
T546 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1116335948 Mar 14 12:26:16 PM PDT 24 Mar 14 12:26:16 PM PDT 24 13245361 ps
T547 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2449099805 Mar 14 12:26:47 PM PDT 24 Mar 14 12:26:48 PM PDT 24 164844276 ps
T548 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2645906241 Mar 14 12:26:53 PM PDT 24 Mar 14 12:26:53 PM PDT 24 30538298 ps
T549 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2151709810 Mar 14 12:26:31 PM PDT 24 Mar 14 12:26:32 PM PDT 24 25560729 ps
T550 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2992912665 Mar 14 12:26:30 PM PDT 24 Mar 14 12:26:31 PM PDT 24 299901926 ps
T551 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1271496198 Mar 14 12:26:21 PM PDT 24 Mar 14 12:26:23 PM PDT 24 426164266 ps
T552 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.334483100 Mar 14 12:26:25 PM PDT 24 Mar 14 12:26:25 PM PDT 24 35827121 ps
T553 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.257298815 Mar 14 12:26:35 PM PDT 24 Mar 14 12:26:37 PM PDT 24 43684010 ps
T554 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2675972438 Mar 14 12:26:31 PM PDT 24 Mar 14 12:26:32 PM PDT 24 76140720 ps
T555 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.977969510 Mar 14 12:26:34 PM PDT 24 Mar 14 12:26:36 PM PDT 24 60937644 ps
T556 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1829232548 Mar 14 12:26:46 PM PDT 24 Mar 14 12:26:47 PM PDT 24 22349908 ps
T557 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1069055406 Mar 14 12:26:37 PM PDT 24 Mar 14 12:26:38 PM PDT 24 51994303 ps
T558 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3916507778 Mar 14 12:26:23 PM PDT 24 Mar 14 12:26:24 PM PDT 24 89343733 ps
T559 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2638882224 Mar 14 12:26:47 PM PDT 24 Mar 14 12:26:48 PM PDT 24 16665922 ps
T560 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.12562547 Mar 14 12:26:21 PM PDT 24 Mar 14 12:26:23 PM PDT 24 90989699 ps
T561 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.908913853 Mar 14 12:26:32 PM PDT 24 Mar 14 12:26:33 PM PDT 24 25877598 ps
T562 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2494014447 Mar 14 12:26:05 PM PDT 24 Mar 14 12:26:05 PM PDT 24 11524073 ps
T563 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1873905742 Mar 14 12:26:23 PM PDT 24 Mar 14 12:26:24 PM PDT 24 13607151 ps
T564 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2849710346 Mar 14 12:26:47 PM PDT 24 Mar 14 12:26:49 PM PDT 24 2059436315 ps
T565 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1183505019 Mar 14 12:26:19 PM PDT 24 Mar 14 12:26:20 PM PDT 24 65402955 ps
T566 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1514080065 Mar 14 12:26:28 PM PDT 24 Mar 14 12:26:30 PM PDT 24 99956233 ps
T105 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3513323001 Mar 14 12:26:22 PM PDT 24 Mar 14 12:26:23 PM PDT 24 26513667 ps
T567 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1590262619 Mar 14 12:26:19 PM PDT 24 Mar 14 12:26:20 PM PDT 24 15231715 ps
T568 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2804962598 Mar 14 12:26:53 PM PDT 24 Mar 14 12:26:53 PM PDT 24 15642245 ps
T569 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.390243309 Mar 14 12:26:29 PM PDT 24 Mar 14 12:26:29 PM PDT 24 13083580 ps
T570 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1936081402 Mar 14 12:26:32 PM PDT 24 Mar 14 12:26:33 PM PDT 24 24573125 ps
T571 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.608258806 Mar 14 12:26:54 PM PDT 24 Mar 14 12:26:55 PM PDT 24 14466311 ps
T572 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1000783393 Mar 14 12:26:30 PM PDT 24 Mar 14 12:26:31 PM PDT 24 25290640 ps
T573 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2577765065 Mar 14 12:26:19 PM PDT 24 Mar 14 12:26:20 PM PDT 24 26429429 ps
T106 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2945306333 Mar 14 12:26:01 PM PDT 24 Mar 14 12:26:02 PM PDT 24 56212022 ps
T107 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.725949014 Mar 14 12:26:23 PM PDT 24 Mar 14 12:26:24 PM PDT 24 56252030 ps
T574 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1023183925 Mar 14 12:26:24 PM PDT 24 Mar 14 12:26:25 PM PDT 24 108751602 ps
T108 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2765938800 Mar 14 12:26:38 PM PDT 24 Mar 14 12:26:39 PM PDT 24 13106623 ps

Test location /workspace/coverage/default/123.rv_timer_random.1306275983
Short name T1
Test name
Test status
Simulation time 451564437605 ps
CPU time 531.97 seconds
Started Mar 14 12:33:59 PM PDT 24
Finished Mar 14 12:42:51 PM PDT 24
Peak memory 191132 kb
Host smart-331f933d-1ae8-425e-b353-0b6943c93783
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306275983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1306275983
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.1607966598
Short name T13
Test name
Test status
Simulation time 101628241221 ps
CPU time 910.46 seconds
Started Mar 14 12:33:25 PM PDT 24
Finished Mar 14 12:48:36 PM PDT 24
Peak memory 208404 kb
Host smart-abbe693c-cc3e-45ed-ac99-2dc771a09b1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607966598 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.1607966598
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1073771024
Short name T33
Test name
Test status
Simulation time 357887191315 ps
CPU time 997.58 seconds
Started Mar 14 12:33:15 PM PDT 24
Finished Mar 14 12:49:53 PM PDT 24
Peak memory 191204 kb
Host smart-be9da9e8-4eef-49a9-a3b8-b2e80716344c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073771024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1073771024
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.51030470
Short name T30
Test name
Test status
Simulation time 128407076 ps
CPU time 1.36 seconds
Started Mar 14 12:26:43 PM PDT 24
Finished Mar 14 12:26:44 PM PDT 24
Peak memory 194280 kb
Host smart-e9eab78b-6c0a-492b-9f7d-e9aff7e5b925
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51030470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_int
g_err.51030470
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.4278182656
Short name T172
Test name
Test status
Simulation time 1320902735111 ps
CPU time 2496.31 seconds
Started Mar 14 12:33:29 PM PDT 24
Finished Mar 14 01:15:06 PM PDT 24
Peak memory 195388 kb
Host smart-14527906-59e4-4728-8fc1-e11c8801a2f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278182656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.4278182656
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.182637873
Short name T70
Test name
Test status
Simulation time 1129757132430 ps
CPU time 1720.48 seconds
Started Mar 14 12:33:11 PM PDT 24
Finished Mar 14 01:01:54 PM PDT 24
Peak memory 195932 kb
Host smart-8671c030-27e6-450e-9ac9-aa149c27bbc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182637873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.182637873
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3899740236
Short name T151
Test name
Test status
Simulation time 3006327923897 ps
CPU time 2694.96 seconds
Started Mar 14 12:33:42 PM PDT 24
Finished Mar 14 01:18:38 PM PDT 24
Peak memory 191072 kb
Host smart-a7cd0f27-48f9-49da-b011-13aa41f90c8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899740236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3899740236
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.950328764
Short name T117
Test name
Test status
Simulation time 3019456951504 ps
CPU time 1532.44 seconds
Started Mar 14 12:33:42 PM PDT 24
Finished Mar 14 12:59:15 PM PDT 24
Peak memory 191196 kb
Host smart-06b382ba-df71-4b27-b41c-972c2cd41754
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950328764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
950328764
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3177369756
Short name T166
Test name
Test status
Simulation time 584341756580 ps
CPU time 2499.51 seconds
Started Mar 14 12:33:10 PM PDT 24
Finished Mar 14 01:14:50 PM PDT 24
Peak memory 191184 kb
Host smart-f5d278da-8f14-4237-b08b-70eaefff7a41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177369756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3177369756
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.3135459445
Short name T73
Test name
Test status
Simulation time 2238360756554 ps
CPU time 1502.64 seconds
Started Mar 14 12:33:34 PM PDT 24
Finished Mar 14 12:58:39 PM PDT 24
Peak memory 191164 kb
Host smart-d3f1befb-569d-4d7b-9982-f725aeae5b81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135459445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.3135459445
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1185112704
Short name T80
Test name
Test status
Simulation time 1326038860144 ps
CPU time 1545.47 seconds
Started Mar 14 12:33:26 PM PDT 24
Finished Mar 14 12:59:12 PM PDT 24
Peak memory 194380 kb
Host smart-f89725e9-a6b1-4306-b739-ef8a9ef0b72f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185112704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1185112704
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1171489029
Short name T55
Test name
Test status
Simulation time 28062976 ps
CPU time 0.58 seconds
Started Mar 14 12:26:38 PM PDT 24
Finished Mar 14 12:26:38 PM PDT 24
Peak memory 182504 kb
Host smart-2b4235da-ad55-433f-ae7f-9563993a46f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171489029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1171489029
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.2711936337
Short name T119
Test name
Test status
Simulation time 319187146141 ps
CPU time 1035.63 seconds
Started Mar 14 12:33:42 PM PDT 24
Finished Mar 14 12:50:58 PM PDT 24
Peak memory 191048 kb
Host smart-5bd34589-dfe4-411e-b6d7-03ac0c4ae846
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711936337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.2711936337
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.3577156523
Short name T69
Test name
Test status
Simulation time 1517490624336 ps
CPU time 1024.96 seconds
Started Mar 14 12:33:34 PM PDT 24
Finished Mar 14 12:50:41 PM PDT 24
Peak memory 196060 kb
Host smart-69403d98-5744-4f67-8131-548745e83dd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577156523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.3577156523
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2291544127
Short name T17
Test name
Test status
Simulation time 57080274 ps
CPU time 0.76 seconds
Started Mar 14 12:32:48 PM PDT 24
Finished Mar 14 12:32:49 PM PDT 24
Peak memory 213168 kb
Host smart-a580539c-8cda-4fd2-9643-90e49c07e798
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291544127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2291544127
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.79542581
Short name T90
Test name
Test status
Simulation time 6820795886319 ps
CPU time 2424.66 seconds
Started Mar 14 12:33:24 PM PDT 24
Finished Mar 14 01:13:50 PM PDT 24
Peak memory 191164 kb
Host smart-5f12a552-f54d-472c-bc9b-9c68973616c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79542581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.79542581
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_random.3684498303
Short name T74
Test name
Test status
Simulation time 145610927829 ps
CPU time 392.55 seconds
Started Mar 14 12:33:11 PM PDT 24
Finished Mar 14 12:39:45 PM PDT 24
Peak memory 191156 kb
Host smart-41060f68-2397-4e77-bccc-a84403678376
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684498303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3684498303
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.1553483808
Short name T346
Test name
Test status
Simulation time 509850421300 ps
CPU time 1170.62 seconds
Started Mar 14 12:33:36 PM PDT 24
Finished Mar 14 12:53:12 PM PDT 24
Peak memory 191160 kb
Host smart-c418a2a0-eeb2-4238-9f2b-7ba1d3c5e4ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553483808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.1553483808
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.1622757788
Short name T437
Test name
Test status
Simulation time 2108131544652 ps
CPU time 1047.87 seconds
Started Mar 14 12:33:19 PM PDT 24
Finished Mar 14 12:50:48 PM PDT 24
Peak memory 191184 kb
Host smart-5eea9c58-c77f-4845-b4ea-bc902f138ef1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622757788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.1622757788
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.4134905705
Short name T12
Test name
Test status
Simulation time 466453788715 ps
CPU time 1737.25 seconds
Started Mar 14 12:33:10 PM PDT 24
Finished Mar 14 01:02:09 PM PDT 24
Peak memory 194924 kb
Host smart-41571b1e-9a3b-4877-9150-a8b945ec08df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134905705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
4134905705
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.736646980
Short name T144
Test name
Test status
Simulation time 281740867319 ps
CPU time 508.43 seconds
Started Mar 14 12:33:36 PM PDT 24
Finished Mar 14 12:42:06 PM PDT 24
Peak memory 191164 kb
Host smart-6505c901-9cec-4bab-9f15-fb741e76a149
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736646980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.
736646980
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.222991513
Short name T217
Test name
Test status
Simulation time 4109840709354 ps
CPU time 2072.58 seconds
Started Mar 14 12:33:12 PM PDT 24
Finished Mar 14 01:07:46 PM PDT 24
Peak memory 196652 kb
Host smart-ebcbb01b-4f6a-401c-a27e-ab19fcb87b72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222991513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.
222991513
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/142.rv_timer_random.1313640036
Short name T164
Test name
Test status
Simulation time 1382630510098 ps
CPU time 730.09 seconds
Started Mar 14 12:33:58 PM PDT 24
Finished Mar 14 12:46:08 PM PDT 24
Peak memory 193692 kb
Host smart-6ca7b981-f977-4d0e-a59e-b5e1d1f08b16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313640036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1313640036
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random.2654766857
Short name T122
Test name
Test status
Simulation time 2180964210924 ps
CPU time 548.35 seconds
Started Mar 14 12:33:12 PM PDT 24
Finished Mar 14 12:42:22 PM PDT 24
Peak memory 191216 kb
Host smart-d757a68f-6c5c-473d-bc18-cade3d35950e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654766857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2654766857
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.3315685860
Short name T71
Test name
Test status
Simulation time 620388564827 ps
CPU time 1236.88 seconds
Started Mar 14 12:33:44 PM PDT 24
Finished Mar 14 12:54:21 PM PDT 24
Peak memory 191164 kb
Host smart-1584221b-c30a-46bb-82de-c92e6883e17d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315685860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.3315685860
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/73.rv_timer_random.2341767178
Short name T124
Test name
Test status
Simulation time 99652118193 ps
CPU time 581.4 seconds
Started Mar 14 12:33:58 PM PDT 24
Finished Mar 14 12:43:39 PM PDT 24
Peak memory 191216 kb
Host smart-22b21b76-e826-449e-860d-6d0d1370aef9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341767178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2341767178
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random.3190424913
Short name T49
Test name
Test status
Simulation time 961074953813 ps
CPU time 462.22 seconds
Started Mar 14 12:33:10 PM PDT 24
Finished Mar 14 12:40:53 PM PDT 24
Peak memory 191180 kb
Host smart-6b580c67-6732-414f-89d0-70a0ea50a259
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190424913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3190424913
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.4109945353
Short name T196
Test name
Test status
Simulation time 3668015338116 ps
CPU time 1824.04 seconds
Started Mar 14 12:33:11 PM PDT 24
Finished Mar 14 01:03:38 PM PDT 24
Peak memory 195252 kb
Host smart-b39191d1-7c27-4234-855d-567302d8e22e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109945353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.4109945353
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1968039434
Short name T209
Test name
Test status
Simulation time 440505823992 ps
CPU time 739.42 seconds
Started Mar 14 12:33:41 PM PDT 24
Finished Mar 14 12:46:01 PM PDT 24
Peak memory 191116 kb
Host smart-1ff167dc-ab40-459e-9ea2-2f8e9573637e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968039434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1968039434
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/132.rv_timer_random.1091336488
Short name T227
Test name
Test status
Simulation time 156889791311 ps
CPU time 291.65 seconds
Started Mar 14 12:33:54 PM PDT 24
Finished Mar 14 12:38:46 PM PDT 24
Peak memory 191156 kb
Host smart-72dccfef-c163-4e16-98a3-f2058c42b168
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091336488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1091336488
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.3481080721
Short name T8
Test name
Test status
Simulation time 708439696120 ps
CPU time 677.68 seconds
Started Mar 14 12:33:10 PM PDT 24
Finished Mar 14 12:44:29 PM PDT 24
Peak memory 191192 kb
Host smart-b568abbe-87eb-4627-916f-a30d1e64947f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481080721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.3481080721
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/172.rv_timer_random.2790995758
Short name T211
Test name
Test status
Simulation time 529837178339 ps
CPU time 281.63 seconds
Started Mar 14 12:33:56 PM PDT 24
Finished Mar 14 12:38:38 PM PDT 24
Peak memory 191092 kb
Host smart-a17b8a17-120a-4ae0-a4cc-3f3a63a6864a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790995758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2790995758
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.678485922
Short name T290
Test name
Test status
Simulation time 135163584194 ps
CPU time 262.3 seconds
Started Mar 14 12:33:58 PM PDT 24
Finished Mar 14 12:38:21 PM PDT 24
Peak memory 191212 kb
Host smart-8c920ceb-61e6-4718-826d-01193bdb3042
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678485922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.678485922
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1994359666
Short name T123
Test name
Test status
Simulation time 2770249838763 ps
CPU time 751.58 seconds
Started Mar 14 12:33:20 PM PDT 24
Finished Mar 14 12:45:52 PM PDT 24
Peak memory 182860 kb
Host smart-41009943-fb5e-4e4e-b270-ad3345def1f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994359666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1994359666
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_random.314438930
Short name T89
Test name
Test status
Simulation time 252158731514 ps
CPU time 593.98 seconds
Started Mar 14 12:33:31 PM PDT 24
Finished Mar 14 12:43:25 PM PDT 24
Peak memory 193208 kb
Host smart-2404aa18-b12e-4e4e-b0ce-0e48deeb2d49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314438930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.314438930
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.207550169
Short name T356
Test name
Test status
Simulation time 571930532318 ps
CPU time 456.38 seconds
Started Mar 14 12:34:05 PM PDT 24
Finished Mar 14 12:41:41 PM PDT 24
Peak memory 191112 kb
Host smart-3234ebc5-8737-4a69-a359-fba2646b4aa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207550169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.207550169
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.675498187
Short name T315
Test name
Test status
Simulation time 699414714232 ps
CPU time 661.27 seconds
Started Mar 14 12:34:02 PM PDT 24
Finished Mar 14 12:45:03 PM PDT 24
Peak memory 191192 kb
Host smart-b719c9ef-4c74-4331-922e-9f784a61d7f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675498187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.675498187
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.722481973
Short name T276
Test name
Test status
Simulation time 706306870551 ps
CPU time 912.7 seconds
Started Mar 14 12:33:26 PM PDT 24
Finished Mar 14 12:48:38 PM PDT 24
Peak memory 195836 kb
Host smart-8976dd6c-8044-4df2-ad83-73f32449a93e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722481973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.
722481973
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/187.rv_timer_random.2677287473
Short name T197
Test name
Test status
Simulation time 152034845220 ps
CPU time 341.19 seconds
Started Mar 14 12:33:55 PM PDT 24
Finished Mar 14 12:39:36 PM PDT 24
Peak memory 191448 kb
Host smart-d8a781b8-4f48-44ad-9523-c32990f028ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677287473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2677287473
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random.2653735520
Short name T261
Test name
Test status
Simulation time 105348041342 ps
CPU time 209.98 seconds
Started Mar 14 12:33:28 PM PDT 24
Finished Mar 14 12:36:58 PM PDT 24
Peak memory 194464 kb
Host smart-c320c858-5a19-4eca-8428-0daba7f32a78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653735520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2653735520
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3500919655
Short name T223
Test name
Test status
Simulation time 122180154731 ps
CPU time 185.19 seconds
Started Mar 14 12:34:01 PM PDT 24
Finished Mar 14 12:37:07 PM PDT 24
Peak memory 190924 kb
Host smart-e5bc6ea8-0534-40f1-be86-1fa8b05a6dad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500919655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3500919655
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random.777170078
Short name T271
Test name
Test status
Simulation time 150940688097 ps
CPU time 318.62 seconds
Started Mar 14 12:33:32 PM PDT 24
Finished Mar 14 12:38:51 PM PDT 24
Peak memory 191160 kb
Host smart-f87dbfd7-97d1-4962-b6c8-4153729b1ff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777170078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.777170078
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.4144027756
Short name T173
Test name
Test status
Simulation time 2434571376894 ps
CPU time 835.9 seconds
Started Mar 14 12:33:41 PM PDT 24
Finished Mar 14 12:47:38 PM PDT 24
Peak memory 194516 kb
Host smart-41cee698-fd1c-48bd-84dd-f200a78990dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144027756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.4144027756
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2344429233
Short name T308
Test name
Test status
Simulation time 303168656818 ps
CPU time 417.86 seconds
Started Mar 14 12:33:43 PM PDT 24
Finished Mar 14 12:40:41 PM PDT 24
Peak memory 193412 kb
Host smart-feb49dcb-747b-46a7-814e-b26a53253260
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344429233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2344429233
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.2774871814
Short name T309
Test name
Test status
Simulation time 612427258063 ps
CPU time 1594 seconds
Started Mar 14 12:34:03 PM PDT 24
Finished Mar 14 01:00:38 PM PDT 24
Peak memory 191120 kb
Host smart-2c8d1b1c-53c4-4d34-9b71-d8d80cb35173
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774871814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2774871814
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3141052985
Short name T185
Test name
Test status
Simulation time 395066839436 ps
CPU time 67.97 seconds
Started Mar 14 12:34:03 PM PDT 24
Finished Mar 14 12:35:11 PM PDT 24
Peak memory 191012 kb
Host smart-910b62dc-aa80-48c6-99aa-4acc0afa0917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141052985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3141052985
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1448454167
Short name T142
Test name
Test status
Simulation time 274977075983 ps
CPU time 513.68 seconds
Started Mar 14 12:33:14 PM PDT 24
Finished Mar 14 12:41:48 PM PDT 24
Peak memory 182832 kb
Host smart-b6f3e20f-843b-45cb-85fb-fcdef7946a8b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448454167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.1448454167
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.828175821
Short name T163
Test name
Test status
Simulation time 6876822469826 ps
CPU time 1563.27 seconds
Started Mar 14 12:33:48 PM PDT 24
Finished Mar 14 12:59:52 PM PDT 24
Peak memory 182868 kb
Host smart-db4ddf7b-8c25-472f-aec9-408b5a6aac64
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828175821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.828175821
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_random.1409668548
Short name T316
Test name
Test status
Simulation time 115178593127 ps
CPU time 218.6 seconds
Started Mar 14 12:33:21 PM PDT 24
Finished Mar 14 12:37:00 PM PDT 24
Peak memory 194172 kb
Host smart-891ee1a3-5647-4089-8c68-0bb2a31d491f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409668548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1409668548
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random.2098754155
Short name T128
Test name
Test status
Simulation time 134418624043 ps
CPU time 1478.63 seconds
Started Mar 14 12:33:14 PM PDT 24
Finished Mar 14 12:57:53 PM PDT 24
Peak memory 191184 kb
Host smart-af9504d9-e33f-4303-b6d8-7d6496649bf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098754155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2098754155
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.3344362148
Short name T206
Test name
Test status
Simulation time 526233041928 ps
CPU time 1363.77 seconds
Started Mar 14 12:33:40 PM PDT 24
Finished Mar 14 12:56:24 PM PDT 24
Peak memory 195592 kb
Host smart-c23432a3-bb13-4fb0-a817-9dd736713f86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344362148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.3344362148
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.2388578067
Short name T347
Test name
Test status
Simulation time 2181869897801 ps
CPU time 442.57 seconds
Started Mar 14 12:33:31 PM PDT 24
Finished Mar 14 12:40:54 PM PDT 24
Peak memory 191192 kb
Host smart-f0e462a6-8eef-4200-8909-2dc17da7988b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388578067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.2388578067
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_random.1420557505
Short name T188
Test name
Test status
Simulation time 354291485851 ps
CPU time 1797.88 seconds
Started Mar 14 12:33:43 PM PDT 24
Finished Mar 14 01:03:41 PM PDT 24
Peak memory 191044 kb
Host smart-dfa8737f-eff7-4767-8504-0ae14b08b61f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420557505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1420557505
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2621249282
Short name T99
Test name
Test status
Simulation time 13841927 ps
CPU time 0.64 seconds
Started Mar 14 12:23:27 PM PDT 24
Finished Mar 14 12:23:28 PM PDT 24
Peak memory 182560 kb
Host smart-3a2138a8-28f0-4edd-9f9f-80f83192cf6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621249282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.2621249282
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3774885047
Short name T118
Test name
Test status
Simulation time 399099101968 ps
CPU time 736.42 seconds
Started Mar 14 12:33:07 PM PDT 24
Finished Mar 14 12:45:23 PM PDT 24
Peak memory 182984 kb
Host smart-86fd4be1-95f5-4bee-bc89-59dfc8a63dc6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774885047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.3774885047
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_random.2028808297
Short name T129
Test name
Test status
Simulation time 129172348877 ps
CPU time 63.7 seconds
Started Mar 14 12:33:34 PM PDT 24
Finished Mar 14 12:34:40 PM PDT 24
Peak memory 191252 kb
Host smart-6621e85f-824b-4df5-ad04-9323de46248a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028808297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2028808297
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.719080414
Short name T125
Test name
Test status
Simulation time 129360501605 ps
CPU time 1733.87 seconds
Started Mar 14 12:33:59 PM PDT 24
Finished Mar 14 01:02:53 PM PDT 24
Peak memory 194944 kb
Host smart-f12db021-ebd7-492a-9af6-2c36061809ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719080414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.719080414
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3058679661
Short name T323
Test name
Test status
Simulation time 204532689642 ps
CPU time 192.39 seconds
Started Mar 14 12:34:01 PM PDT 24
Finished Mar 14 12:37:14 PM PDT 24
Peak memory 194632 kb
Host smart-f4714075-3d1f-4b84-a0ba-d223d86db319
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058679661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3058679661
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.350338267
Short name T243
Test name
Test status
Simulation time 193607800804 ps
CPU time 440.41 seconds
Started Mar 14 12:34:00 PM PDT 24
Finished Mar 14 12:41:21 PM PDT 24
Peak memory 191116 kb
Host smart-1fa9023e-a051-453a-99b2-1c2d89ce48ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350338267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.350338267
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.687263849
Short name T192
Test name
Test status
Simulation time 207101879692 ps
CPU time 102.44 seconds
Started Mar 14 12:34:09 PM PDT 24
Finished Mar 14 12:35:52 PM PDT 24
Peak memory 191176 kb
Host smart-d3d410f6-5315-4661-8648-09e758e2191d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687263849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.687263849
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.2523916908
Short name T263
Test name
Test status
Simulation time 454812784585 ps
CPU time 138.99 seconds
Started Mar 14 12:34:10 PM PDT 24
Finished Mar 14 12:36:29 PM PDT 24
Peak memory 191104 kb
Host smart-4ea7160f-12fc-4383-b416-11fab008696f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523916908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.2523916908
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.3053590452
Short name T175
Test name
Test status
Simulation time 1211384176006 ps
CPU time 378.74 seconds
Started Mar 14 12:34:16 PM PDT 24
Finished Mar 14 12:40:36 PM PDT 24
Peak memory 191060 kb
Host smart-d1221f04-0bb8-453e-b8eb-9ecd08ae755e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053590452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3053590452
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.286004662
Short name T354
Test name
Test status
Simulation time 232046625895 ps
CPU time 109.22 seconds
Started Mar 14 12:34:02 PM PDT 24
Finished Mar 14 12:35:51 PM PDT 24
Peak memory 191080 kb
Host smart-4066d7c9-76e7-4881-8d35-91ef6495a8e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286004662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.286004662
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random.507159936
Short name T171
Test name
Test status
Simulation time 169223845230 ps
CPU time 2143.08 seconds
Started Mar 14 12:33:35 PM PDT 24
Finished Mar 14 01:09:19 PM PDT 24
Peak memory 191132 kb
Host smart-c01e877a-890d-498c-b510-26c8e643e275
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507159936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.507159936
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random.4279965214
Short name T149
Test name
Test status
Simulation time 530647588385 ps
CPU time 953.12 seconds
Started Mar 14 12:33:43 PM PDT 24
Finished Mar 14 12:49:36 PM PDT 24
Peak memory 191180 kb
Host smart-646fc7b9-9447-4b83-ab9f-b075b9ce6e55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279965214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.4279965214
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1488242810
Short name T26
Test name
Test status
Simulation time 55028406941 ps
CPU time 89.46 seconds
Started Mar 14 12:33:43 PM PDT 24
Finished Mar 14 12:35:14 PM PDT 24
Peak memory 193472 kb
Host smart-3cd9d7bf-5ff8-4e33-aa07-1911e942b087
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488242810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1488242810
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1679498533
Short name T155
Test name
Test status
Simulation time 34511502259 ps
CPU time 151.71 seconds
Started Mar 14 12:33:46 PM PDT 24
Finished Mar 14 12:36:18 PM PDT 24
Peak memory 191140 kb
Host smart-ef8cd447-5ad7-4a03-a32b-58828019be8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679498533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1679498533
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/90.rv_timer_random.2275349801
Short name T258
Test name
Test status
Simulation time 123277157620 ps
CPU time 228.54 seconds
Started Mar 14 12:33:59 PM PDT 24
Finished Mar 14 12:37:48 PM PDT 24
Peak memory 191148 kb
Host smart-5dde8ea2-3044-4bbc-b713-1f4b2513764a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275349801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2275349801
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.3784497183
Short name T207
Test name
Test status
Simulation time 183772935305 ps
CPU time 861.87 seconds
Started Mar 14 12:32:56 PM PDT 24
Finished Mar 14 12:47:18 PM PDT 24
Peak memory 191172 kb
Host smart-b2a37c02-fba5-4084-bea8-5dccb2c2fa1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784497183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3784497183
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.43166581
Short name T77
Test name
Test status
Simulation time 127388228808 ps
CPU time 230.16 seconds
Started Mar 14 12:33:46 PM PDT 24
Finished Mar 14 12:37:37 PM PDT 24
Peak memory 191064 kb
Host smart-7d5ebf66-dbc1-4a24-b4bd-91627e2f324b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43166581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.43166581
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.1745507880
Short name T329
Test name
Test status
Simulation time 70147009739 ps
CPU time 114.71 seconds
Started Mar 14 12:33:45 PM PDT 24
Finished Mar 14 12:35:40 PM PDT 24
Peak memory 182996 kb
Host smart-c0f42e50-c8d9-412b-a3bb-447c1d9735ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745507880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1745507880
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.2333620045
Short name T296
Test name
Test status
Simulation time 345304883643 ps
CPU time 126.36 seconds
Started Mar 14 12:33:57 PM PDT 24
Finished Mar 14 12:36:03 PM PDT 24
Peak memory 191192 kb
Host smart-02d25ee3-f3a9-4c30-965b-458df4a02e3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333620045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2333620045
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.1380450051
Short name T322
Test name
Test status
Simulation time 68253082229 ps
CPU time 125.79 seconds
Started Mar 14 12:33:15 PM PDT 24
Finished Mar 14 12:35:26 PM PDT 24
Peak memory 191172 kb
Host smart-12873781-46f0-4b6a-972e-00bd26a2e479
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380450051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1380450051
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.650361519
Short name T202
Test name
Test status
Simulation time 60832231228 ps
CPU time 133.81 seconds
Started Mar 14 12:33:58 PM PDT 24
Finished Mar 14 12:36:12 PM PDT 24
Peak memory 191088 kb
Host smart-7ecc345e-84be-4c8f-89e8-c1abc81ed839
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650361519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.650361519
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.278687675
Short name T76
Test name
Test status
Simulation time 63823834221 ps
CPU time 115.66 seconds
Started Mar 14 12:34:02 PM PDT 24
Finished Mar 14 12:35:58 PM PDT 24
Peak memory 190996 kb
Host smart-66ef02c0-6343-4cc6-99b9-01824a231917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278687675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.278687675
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1255609787
Short name T332
Test name
Test status
Simulation time 152532203266 ps
CPU time 395.99 seconds
Started Mar 14 12:34:05 PM PDT 24
Finished Mar 14 12:40:41 PM PDT 24
Peak memory 191144 kb
Host smart-5934e900-7407-4691-82c7-0c2d925a20fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255609787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1255609787
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.9214771
Short name T221
Test name
Test status
Simulation time 327662985832 ps
CPU time 145 seconds
Started Mar 14 12:34:01 PM PDT 24
Finished Mar 14 12:36:26 PM PDT 24
Peak memory 190992 kb
Host smart-4ddc4ec9-59e5-457c-979e-b5d851ef7e28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9214771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.9214771
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3235032959
Short name T186
Test name
Test status
Simulation time 25909002114 ps
CPU time 91.58 seconds
Started Mar 14 12:33:18 PM PDT 24
Finished Mar 14 12:34:50 PM PDT 24
Peak memory 191132 kb
Host smart-43b8ae5c-0c69-4478-865c-909a4d0db270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235032959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3235032959
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/137.rv_timer_random.2173739397
Short name T327
Test name
Test status
Simulation time 362688731239 ps
CPU time 665.41 seconds
Started Mar 14 12:33:54 PM PDT 24
Finished Mar 14 12:45:00 PM PDT 24
Peak memory 191068 kb
Host smart-6db4bb02-41a7-4b09-9621-fd274cec2c37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173739397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2173739397
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1427267523
Short name T143
Test name
Test status
Simulation time 183428105879 ps
CPU time 2280.58 seconds
Started Mar 14 12:33:58 PM PDT 24
Finished Mar 14 01:11:59 PM PDT 24
Peak memory 191172 kb
Host smart-2631763d-6744-4147-85aa-f737f97d91e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427267523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1427267523
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.1288354438
Short name T266
Test name
Test status
Simulation time 164243502948 ps
CPU time 418.38 seconds
Started Mar 14 12:33:56 PM PDT 24
Finished Mar 14 12:40:55 PM PDT 24
Peak memory 191184 kb
Host smart-4c2040e0-3621-436c-9ea8-a12bd93d8ff3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288354438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1288354438
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.3170941652
Short name T212
Test name
Test status
Simulation time 978598543565 ps
CPU time 426.96 seconds
Started Mar 14 12:33:51 PM PDT 24
Finished Mar 14 12:40:59 PM PDT 24
Peak memory 191116 kb
Host smart-c8977b5f-4bcf-4721-9088-25d79e137bda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170941652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3170941652
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3581201050
Short name T248
Test name
Test status
Simulation time 159480142244 ps
CPU time 300.11 seconds
Started Mar 14 12:34:00 PM PDT 24
Finished Mar 14 12:39:00 PM PDT 24
Peak memory 194492 kb
Host smart-fd3820d0-6b66-4a7b-a890-9f24bab43263
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581201050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3581201050
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.3341419116
Short name T303
Test name
Test status
Simulation time 267239199015 ps
CPU time 372.69 seconds
Started Mar 14 12:34:00 PM PDT 24
Finished Mar 14 12:40:13 PM PDT 24
Peak memory 191076 kb
Host smart-fbe6ea78-7cf5-48f5-a677-28d51f8c4506
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341419116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3341419116
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.1843538015
Short name T274
Test name
Test status
Simulation time 589393276507 ps
CPU time 1621.45 seconds
Started Mar 14 12:34:01 PM PDT 24
Finished Mar 14 01:01:03 PM PDT 24
Peak memory 191180 kb
Host smart-06a0baa3-d436-4f0f-8954-70c4ad6d623f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843538015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1843538015
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.3007539253
Short name T25
Test name
Test status
Simulation time 418250878185 ps
CPU time 253.5 seconds
Started Mar 14 12:33:58 PM PDT 24
Finished Mar 14 12:38:11 PM PDT 24
Peak memory 191172 kb
Host smart-f2f68403-34ee-41d5-b43f-0d29f1e44130
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007539253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.3007539253
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.816140207
Short name T249
Test name
Test status
Simulation time 42971733995 ps
CPU time 354.14 seconds
Started Mar 14 12:33:57 PM PDT 24
Finished Mar 14 12:39:51 PM PDT 24
Peak memory 192324 kb
Host smart-001ca409-4742-4b18-98e8-7ce99c32f5dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816140207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.816140207
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2659135057
Short name T220
Test name
Test status
Simulation time 139410176518 ps
CPU time 127.4 seconds
Started Mar 14 12:34:04 PM PDT 24
Finished Mar 14 12:36:12 PM PDT 24
Peak memory 194732 kb
Host smart-d903847e-03bf-459e-bfc3-50958dc7c840
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659135057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2659135057
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.1667315491
Short name T138
Test name
Test status
Simulation time 225602901846 ps
CPU time 100.7 seconds
Started Mar 14 12:33:59 PM PDT 24
Finished Mar 14 12:35:40 PM PDT 24
Peak memory 191076 kb
Host smart-52953927-2c43-410d-9020-6b9d1ae5d410
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667315491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1667315491
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3555128226
Short name T359
Test name
Test status
Simulation time 42230611325 ps
CPU time 89.13 seconds
Started Mar 14 12:33:32 PM PDT 24
Finished Mar 14 12:35:02 PM PDT 24
Peak memory 182960 kb
Host smart-2daa921c-3255-4bac-bf6d-654c3e81e253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555128226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3555128226
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_random.3600183409
Short name T262
Test name
Test status
Simulation time 37768966886 ps
CPU time 51.92 seconds
Started Mar 14 12:33:25 PM PDT 24
Finished Mar 14 12:34:17 PM PDT 24
Peak memory 182740 kb
Host smart-1a86ba79-e6a9-4abb-9ae1-5174825d7c6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600183409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3600183409
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2276518558
Short name T257
Test name
Test status
Simulation time 65293535347 ps
CPU time 118.27 seconds
Started Mar 14 12:33:10 PM PDT 24
Finished Mar 14 12:35:10 PM PDT 24
Peak memory 195736 kb
Host smart-4c2df8dc-4a35-4eed-b90a-6d3da9d0c522
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276518558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2276518558
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_random.686894336
Short name T334
Test name
Test status
Simulation time 31991821857 ps
CPU time 68.38 seconds
Started Mar 14 12:33:31 PM PDT 24
Finished Mar 14 12:34:40 PM PDT 24
Peak memory 191076 kb
Host smart-4c029f1a-ba12-4b6e-bf49-f7ad67f3958d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686894336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.686894336
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.19506591
Short name T268
Test name
Test status
Simulation time 33045342457 ps
CPU time 19.34 seconds
Started Mar 14 12:33:33 PM PDT 24
Finished Mar 14 12:33:53 PM PDT 24
Peak memory 182964 kb
Host smart-6902cf76-234c-4c97-80a8-d427f5c989a0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19506591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.rv_timer_cfg_update_on_fly.19506591
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1189243525
Short name T269
Test name
Test status
Simulation time 1026598295029 ps
CPU time 553.37 seconds
Started Mar 14 12:33:36 PM PDT 24
Finished Mar 14 12:42:52 PM PDT 24
Peak memory 182952 kb
Host smart-5767c9e2-da31-4bcf-81fe-ad45ded636c5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189243525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1189243525
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2336272435
Short name T311
Test name
Test status
Simulation time 331746328871 ps
CPU time 330.01 seconds
Started Mar 14 12:33:14 PM PDT 24
Finished Mar 14 12:38:44 PM PDT 24
Peak memory 182996 kb
Host smart-b7798e12-c38a-4a6b-9c18-d5dd1217abcb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336272435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.2336272435
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_random.1854278758
Short name T222
Test name
Test status
Simulation time 367602133247 ps
CPU time 671.12 seconds
Started Mar 14 12:33:46 PM PDT 24
Finished Mar 14 12:44:58 PM PDT 24
Peak memory 194328 kb
Host smart-b34c612b-f1eb-42a3-a4d4-9050cdb4f9d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854278758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1854278758
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.1885612333
Short name T179
Test name
Test status
Simulation time 61918182145 ps
CPU time 48.75 seconds
Started Mar 14 12:33:56 PM PDT 24
Finished Mar 14 12:34:45 PM PDT 24
Peak memory 182952 kb
Host smart-18f46bc0-1e65-4da7-9a3d-8abc1350803c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885612333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.1885612333
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.725949014
Short name T107
Test name
Test status
Simulation time 56252030 ps
CPU time 0.7 seconds
Started Mar 14 12:26:23 PM PDT 24
Finished Mar 14 12:26:24 PM PDT 24
Peak memory 192384 kb
Host smart-9bd7970d-09a6-431c-91ef-ae4ddaafcb21
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725949014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alias
ing.725949014
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1309566174
Short name T103
Test name
Test status
Simulation time 121772022 ps
CPU time 2.33 seconds
Started Mar 14 12:26:19 PM PDT 24
Finished Mar 14 12:26:21 PM PDT 24
Peak memory 190928 kb
Host smart-fba257e2-08e1-4c24-a7f9-dc9bed73e801
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309566174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.1309566174
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2263134239
Short name T98
Test name
Test status
Simulation time 11742198 ps
CPU time 0.52 seconds
Started Mar 14 12:26:23 PM PDT 24
Finished Mar 14 12:26:24 PM PDT 24
Peak memory 182156 kb
Host smart-b9ae1f1b-04f3-4fc7-bfb1-520e47a79de8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263134239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2263134239
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3255373838
Short name T513
Test name
Test status
Simulation time 144236131 ps
CPU time 0.81 seconds
Started Mar 14 12:23:18 PM PDT 24
Finished Mar 14 12:23:20 PM PDT 24
Peak memory 193456 kb
Host smart-cf884ca0-ceac-4b0b-aa0d-7f61cef00002
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255373838 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3255373838
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2577765065
Short name T573
Test name
Test status
Simulation time 26429429 ps
CPU time 0.51 seconds
Started Mar 14 12:26:19 PM PDT 24
Finished Mar 14 12:26:20 PM PDT 24
Peak memory 181848 kb
Host smart-dc6ffa7f-cc82-4fdf-bf22-c6acc20fe846
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577765065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2577765065
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3009085731
Short name T491
Test name
Test status
Simulation time 43530364 ps
CPU time 0.69 seconds
Started Mar 14 12:26:03 PM PDT 24
Finished Mar 14 12:26:04 PM PDT 24
Peak memory 191484 kb
Host smart-0e84f08a-ac94-41f8-a735-4684cfb98aad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009085731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.3009085731
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3407798387
Short name T465
Test name
Test status
Simulation time 247037831 ps
CPU time 2.3 seconds
Started Mar 14 12:26:34 PM PDT 24
Finished Mar 14 12:26:36 PM PDT 24
Peak memory 197416 kb
Host smart-c7ab2c7b-a5a1-4359-976c-803aab959f10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407798387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3407798387
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2849710346
Short name T564
Test name
Test status
Simulation time 2059436315 ps
CPU time 1.28 seconds
Started Mar 14 12:26:47 PM PDT 24
Finished Mar 14 12:26:49 PM PDT 24
Peak memory 195228 kb
Host smart-0a62ff35-4d81-407b-bcbc-478bfccde6c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849710346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2849710346
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3475234402
Short name T101
Test name
Test status
Simulation time 26085179 ps
CPU time 0.75 seconds
Started Mar 14 12:26:16 PM PDT 24
Finished Mar 14 12:26:18 PM PDT 24
Peak memory 182528 kb
Host smart-69dfd5e1-b120-4848-9197-286f2f378230
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475234402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3475234402
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3580576382
Short name T484
Test name
Test status
Simulation time 100529809 ps
CPU time 1.55 seconds
Started Mar 14 12:26:24 PM PDT 24
Finished Mar 14 12:26:26 PM PDT 24
Peak memory 190848 kb
Host smart-8cd35522-9ce3-4a21-8f2f-7ed9a8d6a5b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580576382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.3580576382
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3513323001
Short name T105
Test name
Test status
Simulation time 26513667 ps
CPU time 0.54 seconds
Started Mar 14 12:26:22 PM PDT 24
Finished Mar 14 12:26:23 PM PDT 24
Peak memory 182068 kb
Host smart-03d535ed-5441-4dad-a4fc-d1c6a584faf3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513323001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3513323001
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1023183925
Short name T574
Test name
Test status
Simulation time 108751602 ps
CPU time 0.67 seconds
Started Mar 14 12:26:24 PM PDT 24
Finished Mar 14 12:26:25 PM PDT 24
Peak memory 194112 kb
Host smart-2dda9aad-769f-4de0-995c-a5d58c91f02a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023183925 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.1023183925
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2494014447
Short name T562
Test name
Test status
Simulation time 11524073 ps
CPU time 0.56 seconds
Started Mar 14 12:26:05 PM PDT 24
Finished Mar 14 12:26:05 PM PDT 24
Peak memory 182504 kb
Host smart-0becb5a1-3a73-42a6-9301-e97e8b8673ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494014447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2494014447
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2201325883
Short name T480
Test name
Test status
Simulation time 37516723 ps
CPU time 0.53 seconds
Started Mar 14 12:26:00 PM PDT 24
Finished Mar 14 12:26:00 PM PDT 24
Peak memory 182488 kb
Host smart-7b5ee8cb-9326-494c-b840-96a83f458bc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201325883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2201325883
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1590262619
Short name T567
Test name
Test status
Simulation time 15231715 ps
CPU time 0.6 seconds
Started Mar 14 12:26:19 PM PDT 24
Finished Mar 14 12:26:20 PM PDT 24
Peak memory 191468 kb
Host smart-15a853b9-757f-4cb1-a9f4-2ea0417d4082
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590262619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.1590262619
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3016230878
Short name T497
Test name
Test status
Simulation time 29776211 ps
CPU time 1.39 seconds
Started Mar 14 12:26:22 PM PDT 24
Finished Mar 14 12:26:24 PM PDT 24
Peak memory 197408 kb
Host smart-98555ed9-ec5b-4290-9a8a-286869d4d856
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016230878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3016230878
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.12562547
Short name T560
Test name
Test status
Simulation time 90989699 ps
CPU time 1.1 seconds
Started Mar 14 12:26:21 PM PDT 24
Finished Mar 14 12:26:23 PM PDT 24
Peak memory 182952 kb
Host smart-602db7a6-395f-4c73-9db0-bb31ee78e23a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12562547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_intg
_err.12562547
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.533428355
Short name T506
Test name
Test status
Simulation time 64846151 ps
CPU time 0.8 seconds
Started Mar 14 12:26:28 PM PDT 24
Finished Mar 14 12:26:29 PM PDT 24
Peak memory 195904 kb
Host smart-656c161d-6a57-4bcb-9235-8d370bc265f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533428355 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.533428355
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.503089439
Short name T512
Test name
Test status
Simulation time 12701794 ps
CPU time 0.52 seconds
Started Mar 14 12:26:32 PM PDT 24
Finished Mar 14 12:26:32 PM PDT 24
Peak memory 182140 kb
Host smart-42ac28c5-0b27-47d4-9567-ce77baa7112a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503089439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.503089439
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2449099805
Short name T547
Test name
Test status
Simulation time 164844276 ps
CPU time 0.61 seconds
Started Mar 14 12:26:47 PM PDT 24
Finished Mar 14 12:26:48 PM PDT 24
Peak memory 191948 kb
Host smart-6cd5a121-d202-4d79-b90e-0f5438a2103a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449099805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2449099805
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1047616929
Short name T498
Test name
Test status
Simulation time 226264009 ps
CPU time 1.38 seconds
Started Mar 14 12:26:38 PM PDT 24
Finished Mar 14 12:26:39 PM PDT 24
Peak memory 197312 kb
Host smart-dfc8f747-966d-41c4-b3f0-7584630f0345
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047616929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1047616929
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3076277839
Short name T31
Test name
Test status
Simulation time 215030982 ps
CPU time 0.79 seconds
Started Mar 14 12:26:32 PM PDT 24
Finished Mar 14 12:26:33 PM PDT 24
Peak memory 183084 kb
Host smart-4f40dacb-ffa2-4c77-86e6-7af7ce2e1d62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076277839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.3076277839
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3478489345
Short name T540
Test name
Test status
Simulation time 305731825 ps
CPU time 0.89 seconds
Started Mar 14 12:26:40 PM PDT 24
Finished Mar 14 12:26:41 PM PDT 24
Peak memory 197060 kb
Host smart-9ac63307-37e0-4165-8bf2-61bd9c990b55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478489345 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.3478489345
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.790005783
Short name T474
Test name
Test status
Simulation time 32420416 ps
CPU time 0.62 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:26:53 PM PDT 24
Peak memory 182564 kb
Host smart-58dc04f4-debc-4223-81a8-2f71ceed7a77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790005783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.790005783
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.600649611
Short name T451
Test name
Test status
Simulation time 58792308 ps
CPU time 0.54 seconds
Started Mar 14 12:26:44 PM PDT 24
Finished Mar 14 12:26:44 PM PDT 24
Peak memory 182096 kb
Host smart-fba68328-5302-474e-83ac-49c21430e653
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600649611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.600649611
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.23946802
Short name T34
Test name
Test status
Simulation time 51906178 ps
CPU time 0.69 seconds
Started Mar 14 12:26:50 PM PDT 24
Finished Mar 14 12:26:51 PM PDT 24
Peak memory 191404 kb
Host smart-284baa7f-4d43-4263-8b59-701daeaa4c8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23946802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_tim
er_same_csr_outstanding.23946802
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2384230891
Short name T40
Test name
Test status
Simulation time 52740590 ps
CPU time 1.27 seconds
Started Mar 14 12:26:50 PM PDT 24
Finished Mar 14 12:26:52 PM PDT 24
Peak memory 197408 kb
Host smart-e3adf351-9ecf-4f78-9817-8a6a0920cc3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384230891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2384230891
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1955917292
Short name T115
Test name
Test status
Simulation time 361491936 ps
CPU time 1.03 seconds
Started Mar 14 12:26:36 PM PDT 24
Finished Mar 14 12:26:38 PM PDT 24
Peak memory 194788 kb
Host smart-45494cc4-207e-418b-bc54-7acbcb3f768f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955917292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.1955917292
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.570252569
Short name T542
Test name
Test status
Simulation time 83883483 ps
CPU time 0.73 seconds
Started Mar 14 12:26:54 PM PDT 24
Finished Mar 14 12:26:55 PM PDT 24
Peak memory 194924 kb
Host smart-8fa818e1-43ca-486c-a52e-22489c37acd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570252569 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.570252569
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.3752062926
Short name T100
Test name
Test status
Simulation time 110243071 ps
CPU time 0.56 seconds
Started Mar 14 12:26:26 PM PDT 24
Finished Mar 14 12:26:26 PM PDT 24
Peak memory 182560 kb
Host smart-6e70357e-84cd-47a2-9bc4-2b357afec90d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752062926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.3752062926
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1873905742
Short name T563
Test name
Test status
Simulation time 13607151 ps
CPU time 0.51 seconds
Started Mar 14 12:26:23 PM PDT 24
Finished Mar 14 12:26:24 PM PDT 24
Peak memory 181936 kb
Host smart-ea768217-444f-4bac-8610-1dcf30ac407c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873905742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1873905742
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2837487177
Short name T522
Test name
Test status
Simulation time 89886733 ps
CPU time 0.61 seconds
Started Mar 14 12:26:27 PM PDT 24
Finished Mar 14 12:26:28 PM PDT 24
Peak memory 191868 kb
Host smart-fae7a5f4-678b-49d1-9e9f-386c95121600
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837487177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.2837487177
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.501346602
Short name T466
Test name
Test status
Simulation time 198419937 ps
CPU time 2.42 seconds
Started Mar 14 12:26:28 PM PDT 24
Finished Mar 14 12:26:30 PM PDT 24
Peak memory 197428 kb
Host smart-38c048d9-437b-44b4-b02b-888283707f35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501346602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.501346602
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2287600923
Short name T116
Test name
Test status
Simulation time 154291303 ps
CPU time 0.83 seconds
Started Mar 14 12:26:44 PM PDT 24
Finished Mar 14 12:26:45 PM PDT 24
Peak memory 192620 kb
Host smart-ddf51ff4-7c5a-4ce8-ad4e-6ec1c3efbe16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287600923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2287600923
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3282439602
Short name T477
Test name
Test status
Simulation time 50738917 ps
CPU time 0.78 seconds
Started Mar 14 12:26:44 PM PDT 24
Finished Mar 14 12:26:45 PM PDT 24
Peak memory 195268 kb
Host smart-6e4c6386-f192-4cd1-ac2c-489022eafa6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282439602 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3282439602
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2765938800
Short name T108
Test name
Test status
Simulation time 13106623 ps
CPU time 0.57 seconds
Started Mar 14 12:26:38 PM PDT 24
Finished Mar 14 12:26:39 PM PDT 24
Peak memory 182372 kb
Host smart-3e9c6ea0-edc4-46a0-88b9-03929d2030d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765938800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2765938800
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3091630174
Short name T517
Test name
Test status
Simulation time 14467226 ps
CPU time 0.53 seconds
Started Mar 14 12:26:32 PM PDT 24
Finished Mar 14 12:26:32 PM PDT 24
Peak memory 181920 kb
Host smart-4874b7dc-b02f-4adc-8e2d-c359f3f5abc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091630174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3091630174
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.589456034
Short name T109
Test name
Test status
Simulation time 47971372 ps
CPU time 0.68 seconds
Started Mar 14 12:26:24 PM PDT 24
Finished Mar 14 12:26:36 PM PDT 24
Peak memory 191656 kb
Host smart-de3f50f5-cc49-41d5-98cd-4c2165ce9b71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589456034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti
mer_same_csr_outstanding.589456034
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.936852854
Short name T538
Test name
Test status
Simulation time 711934547 ps
CPU time 2.81 seconds
Started Mar 14 12:26:38 PM PDT 24
Finished Mar 14 12:26:41 PM PDT 24
Peak memory 197476 kb
Host smart-87b87ce8-b2d7-4938-8157-6737619192d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936852854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.936852854
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.184930156
Short name T51
Test name
Test status
Simulation time 102336326 ps
CPU time 1.05 seconds
Started Mar 14 12:26:24 PM PDT 24
Finished Mar 14 12:26:25 PM PDT 24
Peak memory 195092 kb
Host smart-88c469a4-458a-489b-96f2-916b8cd2bb5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184930156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_in
tg_err.184930156
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1892270385
Short name T454
Test name
Test status
Simulation time 212704758 ps
CPU time 0.69 seconds
Started Mar 14 12:26:24 PM PDT 24
Finished Mar 14 12:26:25 PM PDT 24
Peak memory 195112 kb
Host smart-b853b413-0a55-4b2c-9a79-4900a8258d44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892270385 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.1892270385
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3079511903
Short name T113
Test name
Test status
Simulation time 11987926 ps
CPU time 0.53 seconds
Started Mar 14 12:26:50 PM PDT 24
Finished Mar 14 12:26:50 PM PDT 24
Peak memory 182576 kb
Host smart-324775e1-cd59-4260-a60c-988473c247c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079511903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3079511903
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1116335948
Short name T546
Test name
Test status
Simulation time 13245361 ps
CPU time 0.56 seconds
Started Mar 14 12:26:16 PM PDT 24
Finished Mar 14 12:26:16 PM PDT 24
Peak memory 182500 kb
Host smart-d3c5337e-ef2a-4d00-9732-1a00a42a7e15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116335948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1116335948
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3336609479
Short name T111
Test name
Test status
Simulation time 19487990 ps
CPU time 0.71 seconds
Started Mar 14 12:26:26 PM PDT 24
Finished Mar 14 12:26:27 PM PDT 24
Peak memory 193056 kb
Host smart-77764b6b-bc95-4960-a711-eca1dd72022b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336609479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3336609479
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1631282020
Short name T535
Test name
Test status
Simulation time 362056423 ps
CPU time 1.84 seconds
Started Mar 14 12:26:24 PM PDT 24
Finished Mar 14 12:26:26 PM PDT 24
Peak memory 191088 kb
Host smart-1f125abd-86a5-4f15-bb4d-e266b26ea8c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631282020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1631282020
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1271496198
Short name T551
Test name
Test status
Simulation time 426164266 ps
CPU time 1.4 seconds
Started Mar 14 12:26:21 PM PDT 24
Finished Mar 14 12:26:23 PM PDT 24
Peak memory 195492 kb
Host smart-2adfabb5-ead7-40d8-a8cb-ed34b2469b82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271496198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1271496198
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.123899267
Short name T479
Test name
Test status
Simulation time 179341103 ps
CPU time 0.66 seconds
Started Mar 14 12:26:19 PM PDT 24
Finished Mar 14 12:26:20 PM PDT 24
Peak memory 194144 kb
Host smart-0a7ec767-6647-4a0d-a011-086f3de1ad02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123899267 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.123899267
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.813274552
Short name T475
Test name
Test status
Simulation time 14560201 ps
CPU time 0.57 seconds
Started Mar 14 12:26:24 PM PDT 24
Finished Mar 14 12:26:25 PM PDT 24
Peak memory 182660 kb
Host smart-a174e6e6-0529-43e6-93d8-0b2edfa81090
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813274552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.813274552
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.397453279
Short name T472
Test name
Test status
Simulation time 13959663 ps
CPU time 0.53 seconds
Started Mar 14 12:26:28 PM PDT 24
Finished Mar 14 12:26:29 PM PDT 24
Peak memory 181968 kb
Host smart-957b69f5-15a6-465d-9319-57ff40f9746e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397453279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.397453279
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.4256765537
Short name T520
Test name
Test status
Simulation time 90825563 ps
CPU time 0.59 seconds
Started Mar 14 12:26:22 PM PDT 24
Finished Mar 14 12:26:23 PM PDT 24
Peak memory 191412 kb
Host smart-de4c8247-374c-4c00-a1a8-d37468ad8c17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256765537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.4256765537
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1678322090
Short name T515
Test name
Test status
Simulation time 178098780 ps
CPU time 1.74 seconds
Started Mar 14 12:26:51 PM PDT 24
Finished Mar 14 12:26:53 PM PDT 24
Peak memory 197428 kb
Host smart-21197979-5f58-49f7-81b4-c856ade6c541
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678322090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1678322090
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3817962362
Short name T460
Test name
Test status
Simulation time 111850608 ps
CPU time 0.79 seconds
Started Mar 14 12:26:44 PM PDT 24
Finished Mar 14 12:26:45 PM PDT 24
Peak memory 193464 kb
Host smart-b938f134-6b54-414b-a9f2-c32988357089
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817962362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3817962362
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3371708603
Short name T494
Test name
Test status
Simulation time 19482545 ps
CPU time 0.9 seconds
Started Mar 14 12:26:31 PM PDT 24
Finished Mar 14 12:26:32 PM PDT 24
Peak memory 196932 kb
Host smart-04e9eec4-b66a-48c7-9ad3-0265228855c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371708603 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3371708603
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.4191563373
Short name T102
Test name
Test status
Simulation time 32454395 ps
CPU time 0.58 seconds
Started Mar 14 12:26:19 PM PDT 24
Finished Mar 14 12:26:20 PM PDT 24
Peak memory 182640 kb
Host smart-3ea16cbe-427e-43ef-95f7-aeb5c89f03e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191563373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.4191563373
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.231700500
Short name T487
Test name
Test status
Simulation time 12575732 ps
CPU time 0.51 seconds
Started Mar 14 12:26:23 PM PDT 24
Finished Mar 14 12:26:24 PM PDT 24
Peak memory 182144 kb
Host smart-fb46a87a-1f8d-4463-aa03-13b03f04b82f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231700500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.231700500
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2513607068
Short name T490
Test name
Test status
Simulation time 33459213 ps
CPU time 0.59 seconds
Started Mar 14 12:26:39 PM PDT 24
Finished Mar 14 12:26:39 PM PDT 24
Peak memory 191332 kb
Host smart-78cae8be-85f4-4b46-8b4b-dedc495cfb9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513607068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2513607068
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3012779725
Short name T519
Test name
Test status
Simulation time 98230961 ps
CPU time 1.99 seconds
Started Mar 14 12:26:24 PM PDT 24
Finished Mar 14 12:26:26 PM PDT 24
Peak memory 197520 kb
Host smart-1523dbf5-f46d-45a7-b184-7843ede5647c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012779725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3012779725
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1030409378
Short name T65
Test name
Test status
Simulation time 161837550 ps
CPU time 1.06 seconds
Started Mar 14 12:26:34 PM PDT 24
Finished Mar 14 12:26:36 PM PDT 24
Peak memory 194812 kb
Host smart-1b04ffbe-1e2b-4d5f-95b2-4739f691ab93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030409378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.1030409378
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.908913853
Short name T561
Test name
Test status
Simulation time 25877598 ps
CPU time 1.11 seconds
Started Mar 14 12:26:32 PM PDT 24
Finished Mar 14 12:26:33 PM PDT 24
Peak memory 197404 kb
Host smart-4138643c-b5f9-4b53-92db-0fe85590a9b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908913853 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.908913853
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.237178547
Short name T97
Test name
Test status
Simulation time 37768062 ps
CPU time 0.57 seconds
Started Mar 14 12:26:28 PM PDT 24
Finished Mar 14 12:26:34 PM PDT 24
Peak memory 182600 kb
Host smart-ec6ab19c-792a-42f7-8f72-752257c9d283
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237178547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.237178547
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.955370702
Short name T461
Test name
Test status
Simulation time 16929853 ps
CPU time 0.54 seconds
Started Mar 14 12:26:32 PM PDT 24
Finished Mar 14 12:26:32 PM PDT 24
Peak memory 182516 kb
Host smart-80a065d7-f851-42f6-948e-e504b6bfc5b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955370702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.955370702
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2364598395
Short name T509
Test name
Test status
Simulation time 134230941 ps
CPU time 0.77 seconds
Started Mar 14 12:26:49 PM PDT 24
Finished Mar 14 12:26:50 PM PDT 24
Peak memory 193280 kb
Host smart-837d5a9f-bfbf-42ce-af68-88a54f8651a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364598395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2364598395
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2160229275
Short name T449
Test name
Test status
Simulation time 68656289 ps
CPU time 1.6 seconds
Started Mar 14 12:26:27 PM PDT 24
Finished Mar 14 12:26:29 PM PDT 24
Peak memory 197540 kb
Host smart-c29d21dd-5250-49f0-b9f3-2b305de22ada
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160229275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2160229275
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1676305875
Short name T32
Test name
Test status
Simulation time 268427110 ps
CPU time 1.08 seconds
Started Mar 14 12:26:35 PM PDT 24
Finished Mar 14 12:26:37 PM PDT 24
Peak memory 195052 kb
Host smart-ba64e69d-967b-4a21-9464-987ac3b90d27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676305875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1676305875
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3498860630
Short name T50
Test name
Test status
Simulation time 40495313 ps
CPU time 0.6 seconds
Started Mar 14 12:26:37 PM PDT 24
Finished Mar 14 12:26:38 PM PDT 24
Peak memory 192552 kb
Host smart-07492f78-07b3-46e7-b9d0-4a0b0e4f82de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498860630 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3498860630
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1970528447
Short name T96
Test name
Test status
Simulation time 24994032 ps
CPU time 0.55 seconds
Started Mar 14 12:26:29 PM PDT 24
Finished Mar 14 12:26:29 PM PDT 24
Peak memory 182512 kb
Host smart-a070dc2f-9e42-403a-a215-211c05b5d03b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970528447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1970528447
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.616792668
Short name T503
Test name
Test status
Simulation time 19138214 ps
CPU time 0.55 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:26:54 PM PDT 24
Peak memory 182504 kb
Host smart-07ce9057-fee4-499d-af34-3c356471e276
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616792668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.616792668
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2301720320
Short name T543
Test name
Test status
Simulation time 26767790 ps
CPU time 0.6 seconds
Started Mar 14 12:26:29 PM PDT 24
Finished Mar 14 12:26:30 PM PDT 24
Peak memory 192052 kb
Host smart-fb03d46b-f146-4606-8751-1e33a0646ad9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301720320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.2301720320
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1514080065
Short name T566
Test name
Test status
Simulation time 99956233 ps
CPU time 1.58 seconds
Started Mar 14 12:26:28 PM PDT 24
Finished Mar 14 12:26:30 PM PDT 24
Peak memory 197488 kb
Host smart-47808641-c788-4319-ad38-e3c234066a74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514080065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1514080065
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3139658159
Short name T514
Test name
Test status
Simulation time 91202259 ps
CPU time 1.05 seconds
Started Mar 14 12:26:41 PM PDT 24
Finished Mar 14 12:26:42 PM PDT 24
Peak memory 195008 kb
Host smart-fbcc12b3-46ee-48f3-bfb6-13be42a43898
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139658159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.3139658159
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3457629129
Short name T478
Test name
Test status
Simulation time 91066703 ps
CPU time 0.79 seconds
Started Mar 14 12:26:19 PM PDT 24
Finished Mar 14 12:26:20 PM PDT 24
Peak memory 196884 kb
Host smart-71d752b3-575c-40b1-b617-cf9708d58b74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457629129 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3457629129
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.224203409
Short name T54
Test name
Test status
Simulation time 17952775 ps
CPU time 0.57 seconds
Started Mar 14 12:26:47 PM PDT 24
Finished Mar 14 12:26:48 PM PDT 24
Peak memory 182596 kb
Host smart-5318c4c7-941b-4516-a3f4-68429907d4a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224203409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.224203409
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3526594410
Short name T488
Test name
Test status
Simulation time 86316172 ps
CPU time 0.54 seconds
Started Mar 14 12:26:37 PM PDT 24
Finished Mar 14 12:26:38 PM PDT 24
Peak memory 182456 kb
Host smart-ce2acf06-dbba-4eeb-a28d-873428d3df6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526594410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3526594410
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2757278376
Short name T482
Test name
Test status
Simulation time 30600072 ps
CPU time 0.66 seconds
Started Mar 14 12:26:50 PM PDT 24
Finished Mar 14 12:26:51 PM PDT 24
Peak memory 191952 kb
Host smart-4c6b1dcd-0a18-4b56-a965-d5dbc1fe7f39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757278376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2757278376
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2151709810
Short name T549
Test name
Test status
Simulation time 25560729 ps
CPU time 1.03 seconds
Started Mar 14 12:26:31 PM PDT 24
Finished Mar 14 12:26:32 PM PDT 24
Peak memory 197276 kb
Host smart-3cc12426-ca7a-48c9-9d75-d271155904bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151709810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2151709810
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2945306333
Short name T106
Test name
Test status
Simulation time 56212022 ps
CPU time 0.64 seconds
Started Mar 14 12:26:01 PM PDT 24
Finished Mar 14 12:26:02 PM PDT 24
Peak memory 182544 kb
Host smart-b8c2671c-40b1-43b6-ae2b-f0ce5f575b43
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945306333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.2945306333
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3925865249
Short name T114
Test name
Test status
Simulation time 87964396 ps
CPU time 2.25 seconds
Started Mar 14 12:26:38 PM PDT 24
Finished Mar 14 12:26:45 PM PDT 24
Peak memory 182716 kb
Host smart-02cf28ea-1a9b-4f97-a6df-e0d3638a72db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925865249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.3925865249
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.450598688
Short name T537
Test name
Test status
Simulation time 189031566 ps
CPU time 0.55 seconds
Started Mar 14 12:26:24 PM PDT 24
Finished Mar 14 12:26:25 PM PDT 24
Peak memory 182564 kb
Host smart-0598121b-6e5c-40d3-8f8c-29a548ed88cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450598688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.450598688
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3063209890
Short name T532
Test name
Test status
Simulation time 23426152 ps
CPU time 0.7 seconds
Started Mar 14 12:26:19 PM PDT 24
Finished Mar 14 12:26:20 PM PDT 24
Peak memory 194096 kb
Host smart-6e6e9541-9350-4e38-af60-1a6fce1470d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063209890 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3063209890
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1936081402
Short name T570
Test name
Test status
Simulation time 24573125 ps
CPU time 0.55 seconds
Started Mar 14 12:26:32 PM PDT 24
Finished Mar 14 12:26:33 PM PDT 24
Peak memory 182296 kb
Host smart-da3c3ff6-6850-495e-b545-5c47da2ace86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936081402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1936081402
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1183505019
Short name T565
Test name
Test status
Simulation time 65402955 ps
CPU time 0.54 seconds
Started Mar 14 12:26:19 PM PDT 24
Finished Mar 14 12:26:20 PM PDT 24
Peak memory 182456 kb
Host smart-8f440598-db03-48da-9c51-e45eeb76ba42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183505019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1183505019
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1517721936
Short name T92
Test name
Test status
Simulation time 14950828 ps
CPU time 0.67 seconds
Started Mar 14 12:26:31 PM PDT 24
Finished Mar 14 12:26:32 PM PDT 24
Peak memory 191472 kb
Host smart-e613f3d7-af31-4385-a8cf-00d07d97064a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517721936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.1517721936
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2023427811
Short name T459
Test name
Test status
Simulation time 67118348 ps
CPU time 1.63 seconds
Started Mar 14 12:26:19 PM PDT 24
Finished Mar 14 12:26:21 PM PDT 24
Peak memory 197456 kb
Host smart-a13b8b9c-82f4-4238-8e72-9fb2d3bfdee9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023427811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2023427811
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3572929878
Short name T521
Test name
Test status
Simulation time 417453536 ps
CPU time 1.23 seconds
Started Mar 14 12:26:23 PM PDT 24
Finished Mar 14 12:26:24 PM PDT 24
Peak memory 195008 kb
Host smart-2b212969-1051-4ac3-b976-e1cb7c510ca8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572929878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.3572929878
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3524838357
Short name T518
Test name
Test status
Simulation time 17227713 ps
CPU time 0.53 seconds
Started Mar 14 12:26:33 PM PDT 24
Finished Mar 14 12:26:35 PM PDT 24
Peak memory 181896 kb
Host smart-309a1d39-839e-4e09-96c9-a899eb0c74ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524838357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3524838357
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3535200836
Short name T458
Test name
Test status
Simulation time 24496526 ps
CPU time 0.54 seconds
Started Mar 14 12:26:47 PM PDT 24
Finished Mar 14 12:26:49 PM PDT 24
Peak memory 182528 kb
Host smart-dc6a747d-9984-4aba-bed1-b842341ccb27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535200836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3535200836
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.257298815
Short name T553
Test name
Test status
Simulation time 43684010 ps
CPU time 0.56 seconds
Started Mar 14 12:26:35 PM PDT 24
Finished Mar 14 12:26:37 PM PDT 24
Peak memory 181888 kb
Host smart-5f82c1b3-166e-4769-9e31-7336ec7f4188
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257298815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.257298815
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2638882224
Short name T559
Test name
Test status
Simulation time 16665922 ps
CPU time 0.55 seconds
Started Mar 14 12:26:47 PM PDT 24
Finished Mar 14 12:26:48 PM PDT 24
Peak memory 182532 kb
Host smart-7c2e9226-af81-44eb-8550-01f71115c80f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638882224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2638882224
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1550451885
Short name T502
Test name
Test status
Simulation time 85743682 ps
CPU time 0.5 seconds
Started Mar 14 12:26:52 PM PDT 24
Finished Mar 14 12:26:58 PM PDT 24
Peak memory 181868 kb
Host smart-00670c80-485c-48c4-ac02-db21e5076226
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550451885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1550451885
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2608424546
Short name T507
Test name
Test status
Simulation time 14074612 ps
CPU time 0.53 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:26:53 PM PDT 24
Peak memory 182428 kb
Host smart-fad71105-9a99-4428-9f1d-766bda93ac7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608424546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2608424546
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2629578921
Short name T533
Test name
Test status
Simulation time 34208688 ps
CPU time 0.53 seconds
Started Mar 14 12:26:42 PM PDT 24
Finished Mar 14 12:26:42 PM PDT 24
Peak memory 182404 kb
Host smart-1712e29f-b1a0-41cc-adcd-ace0693fc2cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629578921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2629578921
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3210355199
Short name T530
Test name
Test status
Simulation time 17370244 ps
CPU time 0.56 seconds
Started Mar 14 12:26:44 PM PDT 24
Finished Mar 14 12:26:45 PM PDT 24
Peak memory 182444 kb
Host smart-395567b4-02e8-42af-a253-8b457da1bec5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210355199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3210355199
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3626243172
Short name T453
Test name
Test status
Simulation time 44199135 ps
CPU time 0.54 seconds
Started Mar 14 12:26:52 PM PDT 24
Finished Mar 14 12:26:53 PM PDT 24
Peak memory 182532 kb
Host smart-24084b6b-8ee2-46b0-854e-6b22bd11dcbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626243172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3626243172
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3386806860
Short name T500
Test name
Test status
Simulation time 14082631 ps
CPU time 0.55 seconds
Started Mar 14 12:26:43 PM PDT 24
Finished Mar 14 12:26:44 PM PDT 24
Peak memory 181968 kb
Host smart-a64e4bb0-73ab-4b51-88e5-68f393d81d8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386806860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3386806860
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2915155173
Short name T489
Test name
Test status
Simulation time 16323932 ps
CPU time 0.59 seconds
Started Mar 14 12:26:26 PM PDT 24
Finished Mar 14 12:26:27 PM PDT 24
Peak memory 182576 kb
Host smart-24ba0180-ec33-4a75-85c7-94a9c8e598f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915155173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.2915155173
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1072074154
Short name T534
Test name
Test status
Simulation time 282787199 ps
CPU time 3.76 seconds
Started Mar 14 12:26:43 PM PDT 24
Finished Mar 14 12:26:47 PM PDT 24
Peak memory 191060 kb
Host smart-73009356-be66-43c7-bf53-c386df2f5215
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072074154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.1072074154
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.469324583
Short name T94
Test name
Test status
Simulation time 25472179 ps
CPU time 0.54 seconds
Started Mar 14 12:26:28 PM PDT 24
Finished Mar 14 12:26:29 PM PDT 24
Peak memory 182020 kb
Host smart-97cb302e-5822-496f-afe7-04745b6a07a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469324583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_re
set.469324583
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2335486426
Short name T527
Test name
Test status
Simulation time 70035931 ps
CPU time 0.81 seconds
Started Mar 14 12:26:44 PM PDT 24
Finished Mar 14 12:26:45 PM PDT 24
Peak memory 195664 kb
Host smart-6fb9c0db-faaf-49a1-9346-ae346beb6b0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335486426 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2335486426
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3055743950
Short name T483
Test name
Test status
Simulation time 12294658 ps
CPU time 0.54 seconds
Started Mar 14 12:26:25 PM PDT 24
Finished Mar 14 12:26:25 PM PDT 24
Peak memory 182508 kb
Host smart-532369b0-cabd-4264-802e-126f4b7310f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055743950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3055743950
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1742928906
Short name T468
Test name
Test status
Simulation time 13537593 ps
CPU time 0.53 seconds
Started Mar 14 12:26:24 PM PDT 24
Finished Mar 14 12:26:25 PM PDT 24
Peak memory 182232 kb
Host smart-838af16d-6f25-4c7b-8600-5975a475e12a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742928906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1742928906
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2390898624
Short name T110
Test name
Test status
Simulation time 19946442 ps
CPU time 0.78 seconds
Started Mar 14 12:26:26 PM PDT 24
Finished Mar 14 12:26:27 PM PDT 24
Peak memory 193444 kb
Host smart-5791c8b0-a1f1-437b-9099-4b54e06c0848
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390898624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.2390898624
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3352154600
Short name T53
Test name
Test status
Simulation time 350185781 ps
CPU time 2.22 seconds
Started Mar 14 12:26:31 PM PDT 24
Finished Mar 14 12:26:33 PM PDT 24
Peak memory 197428 kb
Host smart-3ead00c6-fec4-460b-8a60-639f057dd170
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352154600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3352154600
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2922311257
Short name T516
Test name
Test status
Simulation time 92931880 ps
CPU time 1.03 seconds
Started Mar 14 12:26:07 PM PDT 24
Finished Mar 14 12:26:08 PM PDT 24
Peak memory 194608 kb
Host smart-27645bef-730f-4991-94a0-ca6d13c51a4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922311257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2922311257
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3796779589
Short name T528
Test name
Test status
Simulation time 54050372 ps
CPU time 0.52 seconds
Started Mar 14 12:26:34 PM PDT 24
Finished Mar 14 12:26:35 PM PDT 24
Peak memory 182060 kb
Host smart-ccee461e-8fc0-4075-bbab-fe9e40632cb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796779589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3796779589
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3399170309
Short name T462
Test name
Test status
Simulation time 12019512 ps
CPU time 0.51 seconds
Started Mar 14 12:26:44 PM PDT 24
Finished Mar 14 12:26:44 PM PDT 24
Peak memory 182064 kb
Host smart-85558f22-9a39-4749-8a9e-1246467ca6f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399170309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3399170309
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1393123628
Short name T492
Test name
Test status
Simulation time 34224731 ps
CPU time 0.54 seconds
Started Mar 14 12:26:54 PM PDT 24
Finished Mar 14 12:26:55 PM PDT 24
Peak memory 182456 kb
Host smart-46e51887-6982-4609-9bf9-5f08de8d4599
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393123628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1393123628
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.650586402
Short name T450
Test name
Test status
Simulation time 118926437 ps
CPU time 0.56 seconds
Started Mar 14 12:26:46 PM PDT 24
Finished Mar 14 12:26:46 PM PDT 24
Peak memory 182404 kb
Host smart-2a81c2f7-2f80-4a9d-9c94-6091b81942fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650586402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.650586402
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.608258806
Short name T571
Test name
Test status
Simulation time 14466311 ps
CPU time 0.55 seconds
Started Mar 14 12:26:54 PM PDT 24
Finished Mar 14 12:26:55 PM PDT 24
Peak memory 182476 kb
Host smart-8eb9ed72-b2cc-4208-9e5b-bb9d58745b55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608258806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.608258806
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.390243309
Short name T569
Test name
Test status
Simulation time 13083580 ps
CPU time 0.51 seconds
Started Mar 14 12:26:29 PM PDT 24
Finished Mar 14 12:26:29 PM PDT 24
Peak memory 181836 kb
Host smart-7b96c2f7-1926-4db8-866c-2a372e327949
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390243309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.390243309
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2544497453
Short name T526
Test name
Test status
Simulation time 21734291 ps
CPU time 0.54 seconds
Started Mar 14 12:26:45 PM PDT 24
Finished Mar 14 12:26:46 PM PDT 24
Peak memory 182564 kb
Host smart-72c521c8-bae9-4b8b-a2f3-3571e7ee2f27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544497453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2544497453
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.280934730
Short name T496
Test name
Test status
Simulation time 25939474 ps
CPU time 0.56 seconds
Started Mar 14 12:26:50 PM PDT 24
Finished Mar 14 12:26:50 PM PDT 24
Peak memory 182544 kb
Host smart-9720bc9c-bb47-4e0a-92d3-f094cafc4c33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280934730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.280934730
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1613394833
Short name T456
Test name
Test status
Simulation time 13035796 ps
CPU time 0.53 seconds
Started Mar 14 12:26:52 PM PDT 24
Finished Mar 14 12:26:53 PM PDT 24
Peak memory 182388 kb
Host smart-85082491-6411-42fa-8a71-ce61c21d08b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613394833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1613394833
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2804962598
Short name T568
Test name
Test status
Simulation time 15642245 ps
CPU time 0.53 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:26:53 PM PDT 24
Peak memory 182300 kb
Host smart-b4b54800-668e-4311-a533-145c94b5861b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804962598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2804962598
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1389103562
Short name T457
Test name
Test status
Simulation time 41574813 ps
CPU time 0.59 seconds
Started Mar 14 12:26:28 PM PDT 24
Finished Mar 14 12:26:29 PM PDT 24
Peak memory 182564 kb
Host smart-d15d0cc8-743a-4a69-bc7b-9c183f2e9337
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389103562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1389103562
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2675972438
Short name T554
Test name
Test status
Simulation time 76140720 ps
CPU time 1.37 seconds
Started Mar 14 12:26:31 PM PDT 24
Finished Mar 14 12:26:32 PM PDT 24
Peak memory 193308 kb
Host smart-0bdaa481-f005-4d7d-8d62-923ec16cbeb2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675972438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2675972438
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2050084305
Short name T467
Test name
Test status
Simulation time 16804662 ps
CPU time 0.57 seconds
Started Mar 14 12:26:23 PM PDT 24
Finished Mar 14 12:26:24 PM PDT 24
Peak memory 182584 kb
Host smart-b209aba7-2b1f-46ac-8fe9-9a415ae98478
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050084305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2050084305
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.199876016
Short name T499
Test name
Test status
Simulation time 23890164 ps
CPU time 0.75 seconds
Started Mar 14 12:26:15 PM PDT 24
Finished Mar 14 12:26:16 PM PDT 24
Peak memory 195692 kb
Host smart-3fb0d965-e7ec-411b-837d-88bb313286ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199876016 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.199876016
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2533843023
Short name T91
Test name
Test status
Simulation time 24484987 ps
CPU time 0.57 seconds
Started Mar 14 12:26:22 PM PDT 24
Finished Mar 14 12:26:23 PM PDT 24
Peak memory 182520 kb
Host smart-2d95c86a-5350-448a-803d-1a6f5fb73ec1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533843023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2533843023
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1479657608
Short name T501
Test name
Test status
Simulation time 34040842 ps
CPU time 0.56 seconds
Started Mar 14 12:26:21 PM PDT 24
Finished Mar 14 12:26:22 PM PDT 24
Peak memory 182424 kb
Host smart-dbb93fd7-de52-4e9c-b844-b42d1cef7aa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479657608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1479657608
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.989557452
Short name T112
Test name
Test status
Simulation time 181002615 ps
CPU time 0.83 seconds
Started Mar 14 12:26:23 PM PDT 24
Finished Mar 14 12:26:24 PM PDT 24
Peak memory 191612 kb
Host smart-7dfa57c2-618b-4907-9b68-a43a72093475
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989557452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.989557452
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1138013803
Short name T525
Test name
Test status
Simulation time 49121551 ps
CPU time 2.41 seconds
Started Mar 14 12:26:25 PM PDT 24
Finished Mar 14 12:26:28 PM PDT 24
Peak memory 197400 kb
Host smart-86a81b58-35e9-44db-883e-4eaff8f94fb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138013803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1138013803
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3226685156
Short name T541
Test name
Test status
Simulation time 143875620 ps
CPU time 0.79 seconds
Started Mar 14 12:26:28 PM PDT 24
Finished Mar 14 12:26:28 PM PDT 24
Peak memory 193536 kb
Host smart-ace58c7b-190d-451e-8b5e-2d77f4a94462
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226685156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.3226685156
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.353665756
Short name T448
Test name
Test status
Simulation time 28350384 ps
CPU time 0.54 seconds
Started Mar 14 12:26:42 PM PDT 24
Finished Mar 14 12:26:43 PM PDT 24
Peak memory 182484 kb
Host smart-6e18ab7c-6a81-4605-b38a-6edea0a29bb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353665756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.353665756
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3323450634
Short name T511
Test name
Test status
Simulation time 14317164 ps
CPU time 0.52 seconds
Started Mar 14 12:26:45 PM PDT 24
Finished Mar 14 12:26:46 PM PDT 24
Peak memory 182500 kb
Host smart-80391fb5-125b-4ce8-81b7-4320cfa58450
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323450634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3323450634
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3535335181
Short name T471
Test name
Test status
Simulation time 12455856 ps
CPU time 0.52 seconds
Started Mar 14 12:26:47 PM PDT 24
Finished Mar 14 12:26:47 PM PDT 24
Peak memory 181936 kb
Host smart-f3c9d5c2-13d6-4e35-b285-d76f9af2be1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535335181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3535335181
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2918372382
Short name T476
Test name
Test status
Simulation time 39648008 ps
CPU time 0.49 seconds
Started Mar 14 12:26:46 PM PDT 24
Finished Mar 14 12:26:47 PM PDT 24
Peak memory 181920 kb
Host smart-c77b4b30-0b8b-429e-8003-d23de490b471
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918372382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2918372382
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3276992158
Short name T493
Test name
Test status
Simulation time 38491960 ps
CPU time 0.52 seconds
Started Mar 14 12:26:50 PM PDT 24
Finished Mar 14 12:26:51 PM PDT 24
Peak memory 181992 kb
Host smart-3ecdd38a-a46e-4815-8ba6-d3da1174e2b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276992158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3276992158
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.4246421139
Short name T463
Test name
Test status
Simulation time 64258815 ps
CPU time 0.52 seconds
Started Mar 14 12:26:51 PM PDT 24
Finished Mar 14 12:26:52 PM PDT 24
Peak memory 181864 kb
Host smart-f7fbf275-aebf-4485-b423-6da2d7e3e18e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246421139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.4246421139
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.914126465
Short name T485
Test name
Test status
Simulation time 51315246 ps
CPU time 0.58 seconds
Started Mar 14 12:26:42 PM PDT 24
Finished Mar 14 12:26:42 PM PDT 24
Peak memory 182404 kb
Host smart-32d4c7b5-a2fe-47cc-9676-77e3870a205e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914126465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.914126465
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1829232548
Short name T556
Test name
Test status
Simulation time 22349908 ps
CPU time 0.5 seconds
Started Mar 14 12:26:46 PM PDT 24
Finished Mar 14 12:26:47 PM PDT 24
Peak memory 181884 kb
Host smart-cc04390f-2e0d-41d7-aacf-9b46ca40e8db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829232548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1829232548
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2645906241
Short name T548
Test name
Test status
Simulation time 30538298 ps
CPU time 0.51 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:26:53 PM PDT 24
Peak memory 181804 kb
Host smart-a31e8dac-c416-4369-babe-ef78f25cb0f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645906241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.2645906241
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2702777131
Short name T495
Test name
Test status
Simulation time 12958416 ps
CPU time 0.51 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:26:54 PM PDT 24
Peak memory 182184 kb
Host smart-28e03c4d-38e8-4fb5-88b0-b6687c466952
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702777131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2702777131
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1000783393
Short name T572
Test name
Test status
Simulation time 25290640 ps
CPU time 0.72 seconds
Started Mar 14 12:26:30 PM PDT 24
Finished Mar 14 12:26:31 PM PDT 24
Peak memory 194784 kb
Host smart-fb5a6186-f6f7-4e5d-be2c-1cf7ab651ea5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000783393 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1000783393
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.4053613338
Short name T104
Test name
Test status
Simulation time 17338286 ps
CPU time 0.7 seconds
Started Mar 14 12:26:41 PM PDT 24
Finished Mar 14 12:26:41 PM PDT 24
Peak memory 182572 kb
Host smart-c1d5c120-277b-4d48-bf5a-1bff3f467d5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053613338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.4053613338
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2843024574
Short name T464
Test name
Test status
Simulation time 16751391 ps
CPU time 0.55 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:26:54 PM PDT 24
Peak memory 182456 kb
Host smart-2897bfa2-a907-4a98-af64-e2d8bda3a6ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843024574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2843024574
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3344528667
Short name T508
Test name
Test status
Simulation time 17667628 ps
CPU time 0.64 seconds
Started Mar 14 12:26:30 PM PDT 24
Finished Mar 14 12:26:31 PM PDT 24
Peak memory 191880 kb
Host smart-8e9102f5-af04-4635-9156-6290a7ed79df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344528667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3344528667
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3227990068
Short name T470
Test name
Test status
Simulation time 143936565 ps
CPU time 1.96 seconds
Started Mar 14 12:27:00 PM PDT 24
Finished Mar 14 12:27:02 PM PDT 24
Peak memory 197356 kb
Host smart-a989f740-9544-4f5c-9eb9-dd47cc229e4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227990068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3227990068
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1283476339
Short name T536
Test name
Test status
Simulation time 79506292 ps
CPU time 0.81 seconds
Started Mar 14 12:26:30 PM PDT 24
Finished Mar 14 12:26:31 PM PDT 24
Peak memory 193704 kb
Host smart-f03ac813-852e-4f02-99d2-05a59200c506
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283476339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1283476339
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.240688476
Short name T52
Test name
Test status
Simulation time 21076630 ps
CPU time 0.65 seconds
Started Mar 14 12:26:15 PM PDT 24
Finished Mar 14 12:26:16 PM PDT 24
Peak memory 194448 kb
Host smart-9fd9c1d5-dcce-45ba-997b-58208af122c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240688476 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.240688476
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1409144063
Short name T510
Test name
Test status
Simulation time 42602380 ps
CPU time 0.56 seconds
Started Mar 14 12:26:29 PM PDT 24
Finished Mar 14 12:26:29 PM PDT 24
Peak memory 182552 kb
Host smart-10421e6b-5642-4482-af25-8e0932bfbbd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409144063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1409144063
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2178376785
Short name T481
Test name
Test status
Simulation time 13242901 ps
CPU time 0.54 seconds
Started Mar 14 12:26:40 PM PDT 24
Finished Mar 14 12:26:40 PM PDT 24
Peak memory 182216 kb
Host smart-177cc485-07be-488a-b9e0-44ac3f07cb69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178376785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2178376785
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.334483100
Short name T552
Test name
Test status
Simulation time 35827121 ps
CPU time 0.64 seconds
Started Mar 14 12:26:25 PM PDT 24
Finished Mar 14 12:26:25 PM PDT 24
Peak memory 191528 kb
Host smart-6a7fff5e-becc-4f6f-b56d-728c913dbaf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334483100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.334483100
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.441608355
Short name T539
Test name
Test status
Simulation time 194242451 ps
CPU time 1.09 seconds
Started Mar 14 12:26:31 PM PDT 24
Finished Mar 14 12:26:32 PM PDT 24
Peak memory 197380 kb
Host smart-3146694d-c676-49fd-b7a9-342040ed4a14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441608355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.441608355
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1069055406
Short name T557
Test name
Test status
Simulation time 51994303 ps
CPU time 0.84 seconds
Started Mar 14 12:26:37 PM PDT 24
Finished Mar 14 12:26:38 PM PDT 24
Peak memory 193504 kb
Host smart-13088fcb-6f5b-42a6-8e5c-94449b18d4b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069055406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.1069055406
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.783386608
Short name T529
Test name
Test status
Simulation time 17501609 ps
CPU time 0.57 seconds
Started Mar 14 12:26:32 PM PDT 24
Finished Mar 14 12:26:33 PM PDT 24
Peak memory 192848 kb
Host smart-f1fe96a7-6de4-4474-8780-45650f656c57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783386608 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.783386608
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1777635552
Short name T504
Test name
Test status
Simulation time 20976451 ps
CPU time 0.58 seconds
Started Mar 14 12:26:22 PM PDT 24
Finished Mar 14 12:26:23 PM PDT 24
Peak memory 182584 kb
Host smart-cf2d1500-efb9-4f46-8d57-0f4e0765d338
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777635552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1777635552
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3895368157
Short name T473
Test name
Test status
Simulation time 15884156 ps
CPU time 0.56 seconds
Started Mar 14 12:26:44 PM PDT 24
Finished Mar 14 12:26:45 PM PDT 24
Peak memory 182396 kb
Host smart-4d050ae9-110a-4dd3-b44d-264db3ad50e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895368157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3895368157
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3718624318
Short name T95
Test name
Test status
Simulation time 141963194 ps
CPU time 0.77 seconds
Started Mar 14 12:26:25 PM PDT 24
Finished Mar 14 12:26:31 PM PDT 24
Peak memory 193316 kb
Host smart-a8836780-60d4-4cd0-959a-3847c015684f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718624318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3718624318
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.746130430
Short name T545
Test name
Test status
Simulation time 66060890 ps
CPU time 1.43 seconds
Started Mar 14 12:26:26 PM PDT 24
Finished Mar 14 12:26:28 PM PDT 24
Peak memory 197380 kb
Host smart-94b1fa30-ff8b-4c64-a660-4b01cceb7b0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746130430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.746130430
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3916507778
Short name T558
Test name
Test status
Simulation time 89343733 ps
CPU time 0.82 seconds
Started Mar 14 12:26:23 PM PDT 24
Finished Mar 14 12:26:24 PM PDT 24
Peak memory 193572 kb
Host smart-60caa92d-06ac-4a61-a7ef-d760f7002789
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916507778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3916507778
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3820404141
Short name T544
Test name
Test status
Simulation time 55325725 ps
CPU time 0.79 seconds
Started Mar 14 12:26:29 PM PDT 24
Finished Mar 14 12:26:30 PM PDT 24
Peak memory 195380 kb
Host smart-10029665-c184-4ca9-9e16-d2319f2f721c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820404141 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3820404141
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1588017032
Short name T524
Test name
Test status
Simulation time 31734125 ps
CPU time 0.57 seconds
Started Mar 14 12:26:53 PM PDT 24
Finished Mar 14 12:26:53 PM PDT 24
Peak memory 182380 kb
Host smart-d155f9b3-cc84-4d8b-be72-b22911e2a108
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588017032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1588017032
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.4068187784
Short name T469
Test name
Test status
Simulation time 12276549 ps
CPU time 0.53 seconds
Started Mar 14 12:26:48 PM PDT 24
Finished Mar 14 12:26:49 PM PDT 24
Peak memory 181916 kb
Host smart-80d5ddb3-644b-44fa-8a60-8818ab733795
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068187784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.4068187784
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2992912665
Short name T550
Test name
Test status
Simulation time 299901926 ps
CPU time 0.72 seconds
Started Mar 14 12:26:30 PM PDT 24
Finished Mar 14 12:26:31 PM PDT 24
Peak memory 193028 kb
Host smart-fe596d2f-21c8-4d61-828d-5b96731d9eb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992912665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2992912665
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2890607725
Short name T486
Test name
Test status
Simulation time 148185002 ps
CPU time 1.86 seconds
Started Mar 14 12:26:24 PM PDT 24
Finished Mar 14 12:26:26 PM PDT 24
Peak memory 197476 kb
Host smart-4110c910-a0fa-41b0-ae3d-61e9aa29cb0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890607725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2890607725
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1094692595
Short name T452
Test name
Test status
Simulation time 856287711 ps
CPU time 1.29 seconds
Started Mar 14 12:26:27 PM PDT 24
Finished Mar 14 12:26:28 PM PDT 24
Peak memory 194488 kb
Host smart-d825cee6-a64d-42db-9572-1bd89f994cf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094692595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1094692595
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1343167958
Short name T505
Test name
Test status
Simulation time 50355017 ps
CPU time 0.71 seconds
Started Mar 14 12:26:33 PM PDT 24
Finished Mar 14 12:26:35 PM PDT 24
Peak memory 194752 kb
Host smart-ec53c2a1-60b6-4572-9ca5-2011d90900d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343167958 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1343167958
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3182540992
Short name T523
Test name
Test status
Simulation time 24201965 ps
CPU time 0.57 seconds
Started Mar 14 12:26:34 PM PDT 24
Finished Mar 14 12:26:35 PM PDT 24
Peak memory 182560 kb
Host smart-844b2da7-550e-46dc-9dd4-f2ddcf8157fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182540992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3182540992
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.4168874162
Short name T531
Test name
Test status
Simulation time 14975655 ps
CPU time 0.52 seconds
Started Mar 14 12:26:34 PM PDT 24
Finished Mar 14 12:26:36 PM PDT 24
Peak memory 181960 kb
Host smart-f39e793a-b367-4831-bcc1-b640eadfe506
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168874162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.4168874162
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2205882047
Short name T93
Test name
Test status
Simulation time 132152694 ps
CPU time 0.63 seconds
Started Mar 14 12:26:23 PM PDT 24
Finished Mar 14 12:26:24 PM PDT 24
Peak memory 191852 kb
Host smart-9ffd690f-d530-441f-8121-08b7ce298e11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205882047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2205882047
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.977969510
Short name T555
Test name
Test status
Simulation time 60937644 ps
CPU time 1.03 seconds
Started Mar 14 12:26:34 PM PDT 24
Finished Mar 14 12:26:36 PM PDT 24
Peak memory 196568 kb
Host smart-6233aeb9-f8e7-4750-86a4-8652bb83635f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977969510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.977969510
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.807609668
Short name T455
Test name
Test status
Simulation time 257336515 ps
CPU time 1.08 seconds
Started Mar 14 12:26:44 PM PDT 24
Finished Mar 14 12:26:45 PM PDT 24
Peak memory 183180 kb
Host smart-5e7ca7c0-93cf-43f5-81c1-87d15b1bc44a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807609668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_int
g_err.807609668
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.4257730057
Short name T391
Test name
Test status
Simulation time 387214687272 ps
CPU time 162.1 seconds
Started Mar 14 12:32:50 PM PDT 24
Finished Mar 14 12:35:32 PM PDT 24
Peak memory 182960 kb
Host smart-5251c7e0-0f75-40c4-90f1-be2c6d35478f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257730057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.4257730057
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.2103967531
Short name T377
Test name
Test status
Simulation time 363365967 ps
CPU time 0.6 seconds
Started Mar 14 12:33:16 PM PDT 24
Finished Mar 14 12:33:16 PM PDT 24
Peak memory 182656 kb
Host smart-e75e1a93-d0dc-4bcb-83f2-b2775361680a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103967531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2103967531
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3224727964
Short name T383
Test name
Test status
Simulation time 3020905084 ps
CPU time 4.03 seconds
Started Mar 14 12:33:11 PM PDT 24
Finished Mar 14 12:33:16 PM PDT 24
Peak memory 182760 kb
Host smart-12e9f5ec-386d-4676-a047-fba24eaf8259
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224727964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3224727964
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.371861298
Short name T418
Test name
Test status
Simulation time 341323767383 ps
CPU time 137.85 seconds
Started Mar 14 12:33:05 PM PDT 24
Finished Mar 14 12:35:23 PM PDT 24
Peak memory 182916 kb
Host smart-2e860106-7455-4dbd-b904-a3b7d56b9b76
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371861298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rv_timer_cfg_update_on_fly.371861298
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3508056988
Short name T373
Test name
Test status
Simulation time 150526528049 ps
CPU time 134.2 seconds
Started Mar 14 12:33:08 PM PDT 24
Finished Mar 14 12:35:23 PM PDT 24
Peak memory 182988 kb
Host smart-40dbf82c-01f3-432b-be0d-41e479bbfae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508056988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3508056988
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.372796734
Short name T363
Test name
Test status
Simulation time 639967339 ps
CPU time 1.32 seconds
Started Mar 14 12:33:14 PM PDT 24
Finished Mar 14 12:33:16 PM PDT 24
Peak memory 182676 kb
Host smart-5a4e4e7b-71d9-4ca2-a7b1-9e5546a843a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372796734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.372796734
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2508539765
Short name T19
Test name
Test status
Simulation time 90088153 ps
CPU time 0.85 seconds
Started Mar 14 12:33:03 PM PDT 24
Finished Mar 14 12:33:04 PM PDT 24
Peak memory 214348 kb
Host smart-0d106d63-fb8c-4a78-b050-d06828c280f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508539765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2508539765
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1544786055
Short name T430
Test name
Test status
Simulation time 116405536383 ps
CPU time 177.34 seconds
Started Mar 14 12:33:17 PM PDT 24
Finished Mar 14 12:36:14 PM PDT 24
Peak memory 194744 kb
Host smart-6c44cc70-f198-4add-85a6-de485e73037c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544786055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1544786055
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3563364606
Short name T236
Test name
Test status
Simulation time 2765672756463 ps
CPU time 1240.14 seconds
Started Mar 14 12:33:41 PM PDT 24
Finished Mar 14 12:54:22 PM PDT 24
Peak memory 182984 kb
Host smart-4447389e-5800-40f9-8878-297299d64fd4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563364606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3563364606
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.4043692141
Short name T365
Test name
Test status
Simulation time 303260855990 ps
CPU time 232.56 seconds
Started Mar 14 12:33:11 PM PDT 24
Finished Mar 14 12:37:05 PM PDT 24
Peak memory 182912 kb
Host smart-6d2e36ed-2c9c-41d6-927a-6e4bbac9f676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043692141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.4043692141
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2884422277
Short name T408
Test name
Test status
Simulation time 119503035739 ps
CPU time 23.74 seconds
Started Mar 14 12:33:15 PM PDT 24
Finished Mar 14 12:33:39 PM PDT 24
Peak memory 194680 kb
Host smart-7d8d2580-3e20-4834-8f29-11079a487454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884422277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2884422277
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3986118678
Short name T366
Test name
Test status
Simulation time 94762354871 ps
CPU time 62.33 seconds
Started Mar 14 12:33:21 PM PDT 24
Finished Mar 14 12:34:24 PM PDT 24
Peak memory 182976 kb
Host smart-2d8ea562-ea9a-4358-9032-a0756188a0db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986118678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3986118678
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/100.rv_timer_random.492718665
Short name T48
Test name
Test status
Simulation time 50820342778 ps
CPU time 98.82 seconds
Started Mar 14 12:33:51 PM PDT 24
Finished Mar 14 12:35:31 PM PDT 24
Peak memory 191220 kb
Host smart-a5e4ea02-9c71-4c51-a332-8908e490ec94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492718665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.492718665
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.1561185936
Short name T283
Test name
Test status
Simulation time 146584745109 ps
CPU time 517.92 seconds
Started Mar 14 12:33:44 PM PDT 24
Finished Mar 14 12:42:23 PM PDT 24
Peak memory 191140 kb
Host smart-6fcd44dc-520d-4f59-a0d3-527ef8038820
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561185936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1561185936
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.271007220
Short name T191
Test name
Test status
Simulation time 19447196401 ps
CPU time 140.39 seconds
Started Mar 14 12:33:45 PM PDT 24
Finished Mar 14 12:36:06 PM PDT 24
Peak memory 182892 kb
Host smart-c22572b6-734a-4a6e-bb76-b7eff53b716d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271007220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.271007220
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3472022677
Short name T127
Test name
Test status
Simulation time 59909928091 ps
CPU time 110.29 seconds
Started Mar 14 12:33:47 PM PDT 24
Finished Mar 14 12:35:37 PM PDT 24
Peak memory 191076 kb
Host smart-6ed58edb-811f-49be-b19a-2220e0c8b31b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472022677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3472022677
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1310094061
Short name T246
Test name
Test status
Simulation time 309208820945 ps
CPU time 254.4 seconds
Started Mar 14 12:33:44 PM PDT 24
Finished Mar 14 12:37:59 PM PDT 24
Peak memory 193496 kb
Host smart-d4055aa1-5075-426e-b2bb-70d4d54e7838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310094061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1310094061
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.4104231643
Short name T255
Test name
Test status
Simulation time 127902376214 ps
CPU time 1380.45 seconds
Started Mar 14 12:34:01 PM PDT 24
Finished Mar 14 12:57:02 PM PDT 24
Peak memory 190932 kb
Host smart-3fee2eb0-1434-4273-982a-d3f048c3ebdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104231643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.4104231643
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3762553673
Short name T60
Test name
Test status
Simulation time 151296143517 ps
CPU time 228.46 seconds
Started Mar 14 12:33:14 PM PDT 24
Finished Mar 14 12:37:03 PM PDT 24
Peak memory 182844 kb
Host smart-fc78cec0-e902-4746-91a1-ef78218bcf98
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762553673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3762553673
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.928055485
Short name T360
Test name
Test status
Simulation time 242148519656 ps
CPU time 110.98 seconds
Started Mar 14 12:33:10 PM PDT 24
Finished Mar 14 12:35:01 PM PDT 24
Peak memory 182996 kb
Host smart-4936f8a9-66c4-455a-b9fd-374ed523b632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928055485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.928055485
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.3142557914
Short name T398
Test name
Test status
Simulation time 3629297870 ps
CPU time 6.48 seconds
Started Mar 14 12:33:09 PM PDT 24
Finished Mar 14 12:33:16 PM PDT 24
Peak memory 191128 kb
Host smart-949c84af-16fe-4d24-9509-597f138c32b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142557914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.3142557914
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.1614339388
Short name T37
Test name
Test status
Simulation time 96335241245 ps
CPU time 768.4 seconds
Started Mar 14 12:33:07 PM PDT 24
Finished Mar 14 12:45:56 PM PDT 24
Peak memory 205816 kb
Host smart-5b92ed26-3f18-4b36-816c-bcb22ad0fe51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614339388 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.1614339388
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.rv_timer_random.1680875718
Short name T229
Test name
Test status
Simulation time 64450912411 ps
CPU time 308.33 seconds
Started Mar 14 12:34:03 PM PDT 24
Finished Mar 14 12:39:12 PM PDT 24
Peak memory 191120 kb
Host smart-a8055999-55a7-4205-a853-671c0762d467
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680875718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1680875718
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.2081346964
Short name T178
Test name
Test status
Simulation time 206443938447 ps
CPU time 1007.36 seconds
Started Mar 14 12:34:01 PM PDT 24
Finished Mar 14 12:50:49 PM PDT 24
Peak memory 193304 kb
Host smart-29c95346-38b7-4d00-b38c-a30dead5e9d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081346964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2081346964
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.680377329
Short name T203
Test name
Test status
Simulation time 160412100654 ps
CPU time 95.43 seconds
Started Mar 14 12:34:09 PM PDT 24
Finished Mar 14 12:35:44 PM PDT 24
Peak memory 182940 kb
Host smart-9d85dd57-eada-4b49-bec0-961c8f025356
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680377329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.680377329
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.354032499
Short name T245
Test name
Test status
Simulation time 21158983259 ps
CPU time 538.97 seconds
Started Mar 14 12:34:00 PM PDT 24
Finished Mar 14 12:42:59 PM PDT 24
Peak memory 194504 kb
Host smart-d54e08b5-91f1-47c9-a923-58902a72a5ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354032499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.354032499
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.459002584
Short name T6
Test name
Test status
Simulation time 272307571225 ps
CPU time 505.26 seconds
Started Mar 14 12:34:04 PM PDT 24
Finished Mar 14 12:42:29 PM PDT 24
Peak memory 191220 kb
Host smart-53e3c77a-4379-4a93-aba4-2e744a1fa6e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459002584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.459002584
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.1529050836
Short name T225
Test name
Test status
Simulation time 123165759077 ps
CPU time 222.63 seconds
Started Mar 14 12:33:59 PM PDT 24
Finished Mar 14 12:37:42 PM PDT 24
Peak memory 191048 kb
Host smart-9e2493bc-a898-4254-9f40-5493f7363560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529050836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1529050836
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.3671933562
Short name T160
Test name
Test status
Simulation time 348250863869 ps
CPU time 469.5 seconds
Started Mar 14 12:33:55 PM PDT 24
Finished Mar 14 12:41:44 PM PDT 24
Peak memory 191192 kb
Host smart-96eccf2b-d0a5-46d8-a0a8-8f88a109baaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671933562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3671933562
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3198721009
Short name T306
Test name
Test status
Simulation time 511088163928 ps
CPU time 908.08 seconds
Started Mar 14 12:33:21 PM PDT 24
Finished Mar 14 12:48:29 PM PDT 24
Peak memory 182848 kb
Host smart-4ecc5d6a-ff72-418e-b6f1-f6224f5138eb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198721009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3198721009
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1601605570
Short name T11
Test name
Test status
Simulation time 565985707400 ps
CPU time 200.77 seconds
Started Mar 14 12:33:24 PM PDT 24
Finished Mar 14 12:36:46 PM PDT 24
Peak memory 182960 kb
Host smart-2c358aee-6eaa-49b3-9563-91cdd824d15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601605570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1601605570
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.718128872
Short name T79
Test name
Test status
Simulation time 166343614860 ps
CPU time 248.28 seconds
Started Mar 14 12:33:07 PM PDT 24
Finished Mar 14 12:37:15 PM PDT 24
Peak memory 191112 kb
Host smart-0ef1752f-95ef-4d24-ab7b-acbea9ac9a02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718128872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.718128872
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2334325011
Short name T150
Test name
Test status
Simulation time 51660678024 ps
CPU time 45.36 seconds
Started Mar 14 12:32:55 PM PDT 24
Finished Mar 14 12:33:40 PM PDT 24
Peak memory 191016 kb
Host smart-e1e9eca5-d79f-40f8-bdb0-5153e482964f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334325011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2334325011
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.1401703078
Short name T395
Test name
Test status
Simulation time 55579893966 ps
CPU time 220.48 seconds
Started Mar 14 12:34:01 PM PDT 24
Finished Mar 14 12:37:41 PM PDT 24
Peak memory 191080 kb
Host smart-88007c4c-01e9-46ff-80aa-55b6586661eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401703078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1401703078
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3841398914
Short name T254
Test name
Test status
Simulation time 52942191172 ps
CPU time 86.66 seconds
Started Mar 14 12:33:51 PM PDT 24
Finished Mar 14 12:35:18 PM PDT 24
Peak memory 191152 kb
Host smart-a28f6fb3-a4bc-4681-a38e-accb02f31d2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841398914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3841398914
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3683365974
Short name T297
Test name
Test status
Simulation time 38632769908 ps
CPU time 14.47 seconds
Started Mar 14 12:34:06 PM PDT 24
Finished Mar 14 12:34:21 PM PDT 24
Peak memory 182804 kb
Host smart-f7c47de5-2c5e-4389-8b76-3e1978eb0024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683365974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3683365974
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3045559562
Short name T43
Test name
Test status
Simulation time 215237716357 ps
CPU time 258.33 seconds
Started Mar 14 12:34:00 PM PDT 24
Finished Mar 14 12:38:19 PM PDT 24
Peak memory 194436 kb
Host smart-51c875ff-fdca-4e60-9aec-08f7f3a5c7c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045559562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3045559562
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.2633956637
Short name T291
Test name
Test status
Simulation time 76967689490 ps
CPU time 444.01 seconds
Started Mar 14 12:34:03 PM PDT 24
Finished Mar 14 12:41:28 PM PDT 24
Peak memory 191188 kb
Host smart-4f390022-9c80-420b-8cbd-a316c6227be0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633956637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2633956637
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1211920650
Short name T46
Test name
Test status
Simulation time 37601295520 ps
CPU time 43.16 seconds
Started Mar 14 12:33:14 PM PDT 24
Finished Mar 14 12:33:57 PM PDT 24
Peak memory 182988 kb
Host smart-21b0281f-d382-43d0-b35c-77a54b1f9cc8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211920650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1211920650
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.3446101193
Short name T420
Test name
Test status
Simulation time 498792668469 ps
CPU time 156.36 seconds
Started Mar 14 12:33:16 PM PDT 24
Finished Mar 14 12:35:53 PM PDT 24
Peak memory 182904 kb
Host smart-d722cee0-6c32-4aec-ab20-07716dce5777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446101193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3446101193
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.2475921378
Short name T312
Test name
Test status
Simulation time 177068918398 ps
CPU time 416.97 seconds
Started Mar 14 12:33:13 PM PDT 24
Finished Mar 14 12:40:11 PM PDT 24
Peak memory 191140 kb
Host smart-d3f13e8f-a01a-4e01-8e77-f91096dfa689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475921378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2475921378
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.315485346
Short name T66
Test name
Test status
Simulation time 44313239 ps
CPU time 0.6 seconds
Started Mar 14 12:33:09 PM PDT 24
Finished Mar 14 12:33:10 PM PDT 24
Peak memory 182612 kb
Host smart-1a07902d-63a5-44dc-8ada-a0f2086566b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315485346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.
315485346
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.1622326251
Short name T176
Test name
Test status
Simulation time 556794499036 ps
CPU time 186.91 seconds
Started Mar 14 12:34:04 PM PDT 24
Finished Mar 14 12:37:11 PM PDT 24
Peak memory 191160 kb
Host smart-257f8bfb-578f-42ff-83ba-047cffff5207
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622326251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1622326251
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2688545664
Short name T177
Test name
Test status
Simulation time 151961146532 ps
CPU time 364.3 seconds
Started Mar 14 12:33:55 PM PDT 24
Finished Mar 14 12:39:59 PM PDT 24
Peak memory 191124 kb
Host smart-511d1084-96fd-4d17-9bd9-717efc47cde0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688545664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2688545664
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.2825273548
Short name T158
Test name
Test status
Simulation time 669422584962 ps
CPU time 363.21 seconds
Started Mar 14 12:34:01 PM PDT 24
Finished Mar 14 12:40:05 PM PDT 24
Peak memory 190996 kb
Host smart-dc889aa3-866f-4222-b8ca-060f7a44ff16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825273548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.2825273548
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.1398238108
Short name T281
Test name
Test status
Simulation time 329225565793 ps
CPU time 476.61 seconds
Started Mar 14 12:34:03 PM PDT 24
Finished Mar 14 12:41:59 PM PDT 24
Peak memory 191168 kb
Host smart-3f7514b1-95e3-409f-aa6b-41ae0bfb3500
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398238108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1398238108
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.4132853664
Short name T381
Test name
Test status
Simulation time 165633547085 ps
CPU time 125.15 seconds
Started Mar 14 12:33:59 PM PDT 24
Finished Mar 14 12:36:04 PM PDT 24
Peak memory 191204 kb
Host smart-c7b8cbc5-f9e9-40a3-84d2-7591262608cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132853664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.4132853664
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.866698238
Short name T301
Test name
Test status
Simulation time 2923303268 ps
CPU time 5.08 seconds
Started Mar 14 12:34:07 PM PDT 24
Finished Mar 14 12:34:12 PM PDT 24
Peak memory 182796 kb
Host smart-cd5b7c1c-3eb2-4d53-bed4-97c99cf09e66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866698238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.866698238
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.953723060
Short name T318
Test name
Test status
Simulation time 368447944867 ps
CPU time 586.83 seconds
Started Mar 14 12:33:09 PM PDT 24
Finished Mar 14 12:42:57 PM PDT 24
Peak memory 182896 kb
Host smart-ae3a3e1b-bb56-4f25-89c6-6d26578e0cad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953723060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.953723060
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2478067534
Short name T380
Test name
Test status
Simulation time 255136102299 ps
CPU time 164.76 seconds
Started Mar 14 12:33:08 PM PDT 24
Finished Mar 14 12:35:58 PM PDT 24
Peak memory 182888 kb
Host smart-24b0dcdd-587d-4782-b0e0-18a502cd4f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478067534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2478067534
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.3870375262
Short name T181
Test name
Test status
Simulation time 478416268968 ps
CPU time 126.36 seconds
Started Mar 14 12:33:14 PM PDT 24
Finished Mar 14 12:35:21 PM PDT 24
Peak memory 191152 kb
Host smart-be199379-04b7-4ad3-923a-ae852eadd1b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870375262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3870375262
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.110179393
Short name T10
Test name
Test status
Simulation time 25448649853 ps
CPU time 34.13 seconds
Started Mar 14 12:33:15 PM PDT 24
Finished Mar 14 12:33:50 PM PDT 24
Peak memory 183008 kb
Host smart-8ab4f75b-4cc2-4d8e-8cf6-278f1e886931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110179393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.110179393
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.458899842
Short name T22
Test name
Test status
Simulation time 159854822265 ps
CPU time 243.11 seconds
Started Mar 14 12:33:30 PM PDT 24
Finished Mar 14 12:37:33 PM PDT 24
Peak memory 182924 kb
Host smart-c5a80273-f2e7-482a-abe4-842fa62bd540
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458899842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.
458899842
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.3868438330
Short name T353
Test name
Test status
Simulation time 134340410029 ps
CPU time 72.31 seconds
Started Mar 14 12:34:08 PM PDT 24
Finished Mar 14 12:35:20 PM PDT 24
Peak memory 182952 kb
Host smart-2c76ae3c-9c7c-4675-bff3-9e71eb3ab4c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868438330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3868438330
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.2647264596
Short name T198
Test name
Test status
Simulation time 147538053172 ps
CPU time 571.89 seconds
Started Mar 14 12:34:03 PM PDT 24
Finished Mar 14 12:43:35 PM PDT 24
Peak memory 191192 kb
Host smart-9280925c-aa52-4918-a605-2d764209b98b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647264596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2647264596
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.2634819509
Short name T201
Test name
Test status
Simulation time 129156970794 ps
CPU time 228.97 seconds
Started Mar 14 12:33:58 PM PDT 24
Finished Mar 14 12:37:47 PM PDT 24
Peak memory 191172 kb
Host smart-6393b3f8-15d7-40ae-9963-17a14a077877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634819509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2634819509
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3916363108
Short name T208
Test name
Test status
Simulation time 248636567886 ps
CPU time 92.59 seconds
Started Mar 14 12:33:59 PM PDT 24
Finished Mar 14 12:35:32 PM PDT 24
Peak memory 191164 kb
Host smart-d75b4cd4-85da-42f3-b27b-df5dd4d06865
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916363108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3916363108
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1168794552
Short name T228
Test name
Test status
Simulation time 126583323321 ps
CPU time 551.16 seconds
Started Mar 14 12:33:59 PM PDT 24
Finished Mar 14 12:43:10 PM PDT 24
Peak memory 191172 kb
Host smart-ca138f9b-ff0f-4188-987f-34b5aee27841
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168794552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1168794552
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.2327261366
Short name T433
Test name
Test status
Simulation time 79079136857 ps
CPU time 628.24 seconds
Started Mar 14 12:33:58 PM PDT 24
Finished Mar 14 12:44:26 PM PDT 24
Peak memory 182996 kb
Host smart-bbe1a2a6-dce6-4fcc-aa56-478ef8f53293
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327261366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2327261366
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.562664960
Short name T295
Test name
Test status
Simulation time 538374206069 ps
CPU time 527.45 seconds
Started Mar 14 12:33:08 PM PDT 24
Finished Mar 14 12:41:56 PM PDT 24
Peak memory 182948 kb
Host smart-efceb85f-b067-47a1-99cf-7eb3febdf4b6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562664960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.rv_timer_cfg_update_on_fly.562664960
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2905715897
Short name T400
Test name
Test status
Simulation time 367167971438 ps
CPU time 131.02 seconds
Started Mar 14 12:33:27 PM PDT 24
Finished Mar 14 12:35:38 PM PDT 24
Peak memory 183016 kb
Host smart-4dc35dfe-891e-4218-9131-2621c3ef203b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905715897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2905715897
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.3120073961
Short name T136
Test name
Test status
Simulation time 436070988348 ps
CPU time 258.25 seconds
Started Mar 14 12:33:25 PM PDT 24
Finished Mar 14 12:37:43 PM PDT 24
Peak memory 191184 kb
Host smart-9edb827a-68e5-42c6-a901-594400ad6009
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120073961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3120073961
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3042835966
Short name T429
Test name
Test status
Simulation time 20293452 ps
CPU time 0.53 seconds
Started Mar 14 12:33:18 PM PDT 24
Finished Mar 14 12:33:19 PM PDT 24
Peak memory 182736 kb
Host smart-efb9e9a3-6200-478d-be78-37e447b9ff28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042835966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3042835966
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.2744558440
Short name T145
Test name
Test status
Simulation time 1136475391701 ps
CPU time 1806.12 seconds
Started Mar 14 12:34:02 PM PDT 24
Finished Mar 14 01:04:09 PM PDT 24
Peak memory 191164 kb
Host smart-bd9e8f09-d5fa-42c1-bc70-abb3b08522de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744558440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.2744558440
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.3801386800
Short name T219
Test name
Test status
Simulation time 126497295193 ps
CPU time 218.64 seconds
Started Mar 14 12:33:58 PM PDT 24
Finished Mar 14 12:37:36 PM PDT 24
Peak memory 191172 kb
Host smart-6a3fc669-82bf-4b03-8f4f-de355a09b81b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801386800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3801386800
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.769108432
Short name T289
Test name
Test status
Simulation time 73634938156 ps
CPU time 244.94 seconds
Started Mar 14 12:33:56 PM PDT 24
Finished Mar 14 12:38:01 PM PDT 24
Peak memory 191204 kb
Host smart-811efcfc-6662-4932-bf35-7fcae6942f8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769108432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.769108432
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.65417221
Short name T169
Test name
Test status
Simulation time 80507084848 ps
CPU time 677.07 seconds
Started Mar 14 12:34:04 PM PDT 24
Finished Mar 14 12:45:21 PM PDT 24
Peak memory 191188 kb
Host smart-f6ea89bb-d58b-444b-8746-f17cc9c6bcb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65417221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.65417221
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.2146948612
Short name T328
Test name
Test status
Simulation time 50762118388 ps
CPU time 84.61 seconds
Started Mar 14 12:33:58 PM PDT 24
Finished Mar 14 12:35:23 PM PDT 24
Peak memory 191204 kb
Host smart-65725eb3-3aef-4a1c-889e-243aa457aac8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146948612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2146948612
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3336703642
Short name T240
Test name
Test status
Simulation time 48788287827 ps
CPU time 44.2 seconds
Started Mar 14 12:33:14 PM PDT 24
Finished Mar 14 12:33:59 PM PDT 24
Peak memory 182992 kb
Host smart-7f361c67-9a41-438f-8f0a-cc3e2011d84c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336703642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.3336703642
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.4047133040
Short name T411
Test name
Test status
Simulation time 14623321994 ps
CPU time 12.01 seconds
Started Mar 14 12:33:15 PM PDT 24
Finished Mar 14 12:33:27 PM PDT 24
Peak memory 182996 kb
Host smart-c94edda0-afa1-425b-8a7b-32f9d5088644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047133040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.4047133040
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.57260203
Short name T81
Test name
Test status
Simulation time 1189367552603 ps
CPU time 317.89 seconds
Started Mar 14 12:33:27 PM PDT 24
Finished Mar 14 12:38:45 PM PDT 24
Peak memory 191208 kb
Host smart-563c952c-6f29-4dce-a18b-398e4aaafcaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57260203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.57260203
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2202670135
Short name T132
Test name
Test status
Simulation time 132865749817 ps
CPU time 259.76 seconds
Started Mar 14 12:33:09 PM PDT 24
Finished Mar 14 12:37:29 PM PDT 24
Peak memory 191088 kb
Host smart-42bb72b8-1bc6-4089-a8ea-ee6677552643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202670135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2202670135
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.1309768346
Short name T440
Test name
Test status
Simulation time 121376812746 ps
CPU time 350 seconds
Started Mar 14 12:34:14 PM PDT 24
Finished Mar 14 12:40:04 PM PDT 24
Peak memory 191120 kb
Host smart-c733c51f-9f84-444e-a99f-d163e08acf90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309768346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1309768346
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.2200973838
Short name T336
Test name
Test status
Simulation time 148663917394 ps
CPU time 257.4 seconds
Started Mar 14 12:34:12 PM PDT 24
Finished Mar 14 12:38:30 PM PDT 24
Peak memory 191120 kb
Host smart-b7ebfa8a-f05c-4a21-ab50-8fd64bfae55c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200973838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2200973838
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.1561844811
Short name T264
Test name
Test status
Simulation time 72148037768 ps
CPU time 76.8 seconds
Started Mar 14 12:33:57 PM PDT 24
Finished Mar 14 12:35:13 PM PDT 24
Peak memory 191208 kb
Host smart-fc796a98-5ccb-4676-83e7-0e2e61c234d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561844811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1561844811
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.2634369754
Short name T313
Test name
Test status
Simulation time 34863067357 ps
CPU time 115.69 seconds
Started Mar 14 12:33:58 PM PDT 24
Finished Mar 14 12:35:53 PM PDT 24
Peak memory 191160 kb
Host smart-b211e6a1-dc0c-4a86-8f41-93caa5235bcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634369754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2634369754
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.1143081493
Short name T280
Test name
Test status
Simulation time 596293385139 ps
CPU time 387.5 seconds
Started Mar 14 12:33:59 PM PDT 24
Finished Mar 14 12:40:27 PM PDT 24
Peak memory 191164 kb
Host smart-8ba77e24-e4fe-4146-a7ef-b80430f31bfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143081493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1143081493
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2133414872
Short name T204
Test name
Test status
Simulation time 219011308467 ps
CPU time 308.64 seconds
Started Mar 14 12:34:02 PM PDT 24
Finished Mar 14 12:39:11 PM PDT 24
Peak memory 191148 kb
Host smart-1277b618-717c-424b-bb2d-be4300af64be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133414872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2133414872
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.3609495542
Short name T250
Test name
Test status
Simulation time 325515044997 ps
CPU time 759.66 seconds
Started Mar 14 12:33:52 PM PDT 24
Finished Mar 14 12:46:33 PM PDT 24
Peak memory 193976 kb
Host smart-1c23d274-da66-4d23-b7ef-a24b26f4e23e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609495542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3609495542
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.4258273067
Short name T252
Test name
Test status
Simulation time 108042652446 ps
CPU time 654.58 seconds
Started Mar 14 12:34:16 PM PDT 24
Finished Mar 14 12:45:11 PM PDT 24
Peak memory 191192 kb
Host smart-d16cdf0a-5745-44bc-aded-bd5746e3a08d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258273067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.4258273067
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.2096522976
Short name T182
Test name
Test status
Simulation time 374485591158 ps
CPU time 348.8 seconds
Started Mar 14 12:33:56 PM PDT 24
Finished Mar 14 12:39:45 PM PDT 24
Peak memory 191152 kb
Host smart-4e20e039-0c69-4c1e-955d-6b8d1e95b725
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096522976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2096522976
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1923059728
Short name T224
Test name
Test status
Simulation time 10722544017 ps
CPU time 14.99 seconds
Started Mar 14 12:33:10 PM PDT 24
Finished Mar 14 12:33:25 PM PDT 24
Peak memory 182872 kb
Host smart-724f1ec6-e83b-4233-bbfd-db171f5b46e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923059728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1923059728
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.225979994
Short name T369
Test name
Test status
Simulation time 600604509479 ps
CPU time 234.43 seconds
Started Mar 14 12:33:11 PM PDT 24
Finished Mar 14 12:37:08 PM PDT 24
Peak memory 182868 kb
Host smart-28d5190f-eeec-4ff4-8e22-8254f9470cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225979994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.225979994
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.3408332440
Short name T45
Test name
Test status
Simulation time 161963028289 ps
CPU time 163.47 seconds
Started Mar 14 12:33:26 PM PDT 24
Finished Mar 14 12:36:10 PM PDT 24
Peak memory 191200 kb
Host smart-631d2127-aa1c-4e9f-a359-cdf4884abd5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408332440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3408332440
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.4267548293
Short name T4
Test name
Test status
Simulation time 436476872 ps
CPU time 0.59 seconds
Started Mar 14 12:33:09 PM PDT 24
Finished Mar 14 12:33:10 PM PDT 24
Peak memory 182656 kb
Host smart-2ebac1c2-4e4e-46b1-8bfb-ea37b5639c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267548293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.4267548293
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.3028971663
Short name T154
Test name
Test status
Simulation time 129191591240 ps
CPU time 1447.11 seconds
Started Mar 14 12:34:14 PM PDT 24
Finished Mar 14 12:58:22 PM PDT 24
Peak memory 191148 kb
Host smart-bfdf0674-eedc-4cd1-a5ec-1fbe167df689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028971663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3028971663
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.3440611000
Short name T300
Test name
Test status
Simulation time 106618022712 ps
CPU time 140.7 seconds
Started Mar 14 12:33:53 PM PDT 24
Finished Mar 14 12:36:14 PM PDT 24
Peak memory 191140 kb
Host smart-de8c6cfc-6407-42dc-95ca-b9555cd1cc0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440611000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3440611000
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.886823886
Short name T284
Test name
Test status
Simulation time 58405370979 ps
CPU time 58.69 seconds
Started Mar 14 12:34:01 PM PDT 24
Finished Mar 14 12:35:00 PM PDT 24
Peak memory 182944 kb
Host smart-65e1e2ef-7c0e-4733-986e-9915deba491f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886823886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.886823886
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.1943349228
Short name T348
Test name
Test status
Simulation time 48934452747 ps
CPU time 83.84 seconds
Started Mar 14 12:33:57 PM PDT 24
Finished Mar 14 12:35:21 PM PDT 24
Peak memory 191104 kb
Host smart-6f072d97-c5d8-43b8-bf4f-c768537b0012
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943349228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1943349228
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.227328892
Short name T235
Test name
Test status
Simulation time 188042560078 ps
CPU time 2106.43 seconds
Started Mar 14 12:34:02 PM PDT 24
Finished Mar 14 01:09:09 PM PDT 24
Peak memory 191092 kb
Host smart-b78c3be8-dd61-47ff-b806-1e4a62b3b2f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227328892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.227328892
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3988443928
Short name T416
Test name
Test status
Simulation time 863072480356 ps
CPU time 485.35 seconds
Started Mar 14 12:33:11 PM PDT 24
Finished Mar 14 12:41:17 PM PDT 24
Peak memory 182960 kb
Host smart-738ba2bd-68bd-499b-9818-9ae963245331
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988443928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3988443928
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.3191181809
Short name T382
Test name
Test status
Simulation time 742522580621 ps
CPU time 94.79 seconds
Started Mar 14 12:33:08 PM PDT 24
Finished Mar 14 12:34:53 PM PDT 24
Peak memory 183056 kb
Host smart-4fa475fb-37b0-448d-928e-fca6002cc7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191181809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3191181809
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.2013690028
Short name T330
Test name
Test status
Simulation time 181963606139 ps
CPU time 185.92 seconds
Started Mar 14 12:33:11 PM PDT 24
Finished Mar 14 12:36:18 PM PDT 24
Peak memory 191212 kb
Host smart-d40c722f-c52e-401c-adc9-68cc48215b5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013690028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2013690028
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.2993804676
Short name T238
Test name
Test status
Simulation time 13404729539 ps
CPU time 8.72 seconds
Started Mar 14 12:33:19 PM PDT 24
Finished Mar 14 12:33:28 PM PDT 24
Peak memory 191120 kb
Host smart-b8c8c0d6-8607-49e8-bc42-a09f2b68764d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993804676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2993804676
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3495246220
Short name T441
Test name
Test status
Simulation time 1314003497252 ps
CPU time 274.95 seconds
Started Mar 14 12:33:11 PM PDT 24
Finished Mar 14 12:37:48 PM PDT 24
Peak memory 191208 kb
Host smart-76601fd5-24d3-4835-8105-214b5535e249
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495246220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3495246220
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/181.rv_timer_random.1209268681
Short name T409
Test name
Test status
Simulation time 136828882484 ps
CPU time 98.34 seconds
Started Mar 14 12:33:58 PM PDT 24
Finished Mar 14 12:35:37 PM PDT 24
Peak memory 191120 kb
Host smart-f61faa80-695e-4a87-a93e-e38f3a63dacc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209268681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1209268681
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.3490374469
Short name T141
Test name
Test status
Simulation time 537017484531 ps
CPU time 400.84 seconds
Started Mar 14 12:34:00 PM PDT 24
Finished Mar 14 12:40:41 PM PDT 24
Peak memory 191140 kb
Host smart-b6635b35-2495-4345-867c-3b19a93b80c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490374469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3490374469
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.760472555
Short name T438
Test name
Test status
Simulation time 142920206434 ps
CPU time 2349.6 seconds
Started Mar 14 12:34:10 PM PDT 24
Finished Mar 14 01:13:20 PM PDT 24
Peak memory 191084 kb
Host smart-80b5264e-d0c8-4750-82df-2976d0b0948a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760472555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.760472555
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2006939497
Short name T140
Test name
Test status
Simulation time 359526169056 ps
CPU time 184.97 seconds
Started Mar 14 12:34:04 PM PDT 24
Finished Mar 14 12:37:09 PM PDT 24
Peak memory 191080 kb
Host smart-15be8db4-8a9b-4269-a651-dde83fb733d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006939497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2006939497
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1861855053
Short name T439
Test name
Test status
Simulation time 5888472944 ps
CPU time 48.36 seconds
Started Mar 14 12:34:02 PM PDT 24
Finished Mar 14 12:34:50 PM PDT 24
Peak memory 182912 kb
Host smart-6c3301ed-139f-46e1-9527-4d4b42e9926c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861855053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1861855053
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1321886224
Short name T47
Test name
Test status
Simulation time 437518126358 ps
CPU time 341.78 seconds
Started Mar 14 12:34:05 PM PDT 24
Finished Mar 14 12:39:47 PM PDT 24
Peak memory 191148 kb
Host smart-1d9f479a-990a-485d-9e15-adb3690c9edd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321886224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1321886224
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.2124799039
Short name T232
Test name
Test status
Simulation time 17910168287 ps
CPU time 33.79 seconds
Started Mar 14 12:34:14 PM PDT 24
Finished Mar 14 12:34:48 PM PDT 24
Peak memory 182928 kb
Host smart-1354f96f-e21a-43d9-8c5f-83fdf381cd6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124799039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2124799039
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.555736973
Short name T187
Test name
Test status
Simulation time 314094674188 ps
CPU time 535.18 seconds
Started Mar 14 12:33:35 PM PDT 24
Finished Mar 14 12:42:33 PM PDT 24
Peak memory 182964 kb
Host smart-e3e1d214-3f35-43bf-b46c-df77a93fb1e7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555736973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.555736973
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3364258401
Short name T387
Test name
Test status
Simulation time 62361217365 ps
CPU time 105.22 seconds
Started Mar 14 12:33:19 PM PDT 24
Finished Mar 14 12:35:04 PM PDT 24
Peak memory 182992 kb
Host smart-e6fb98d1-096a-463e-9a07-427c8995306a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364258401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3364258401
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.2352423809
Short name T446
Test name
Test status
Simulation time 690111237 ps
CPU time 1.28 seconds
Started Mar 14 12:33:14 PM PDT 24
Finished Mar 14 12:33:16 PM PDT 24
Peak memory 182892 kb
Host smart-1a1cea7c-4f8b-4558-8a85-a3c926f5067e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352423809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2352423809
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1401941716
Short name T67
Test name
Test status
Simulation time 267980128722 ps
CPU time 179.74 seconds
Started Mar 14 12:33:12 PM PDT 24
Finished Mar 14 12:36:13 PM PDT 24
Peak memory 191208 kb
Host smart-6e011460-7166-4573-977c-7a3bcf498d2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401941716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1401941716
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/191.rv_timer_random.825817290
Short name T174
Test name
Test status
Simulation time 33479711833 ps
CPU time 45.57 seconds
Started Mar 14 12:34:01 PM PDT 24
Finished Mar 14 12:34:47 PM PDT 24
Peak memory 191036 kb
Host smart-b6d66a30-a0cc-4729-83a9-aa951016e8ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825817290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.825817290
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.2535063724
Short name T349
Test name
Test status
Simulation time 72903856474 ps
CPU time 421.47 seconds
Started Mar 14 12:34:04 PM PDT 24
Finished Mar 14 12:41:06 PM PDT 24
Peak memory 191188 kb
Host smart-df2be43d-1d59-4e6a-9754-aa9b4b8741f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535063724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2535063724
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3733952486
Short name T216
Test name
Test status
Simulation time 623295016734 ps
CPU time 1052.66 seconds
Started Mar 14 12:34:12 PM PDT 24
Finished Mar 14 12:51:45 PM PDT 24
Peak memory 191184 kb
Host smart-820d742d-9bdb-4d63-ae88-91c290950ff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733952486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3733952486
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.3028866063
Short name T345
Test name
Test status
Simulation time 76370199667 ps
CPU time 56.68 seconds
Started Mar 14 12:33:55 PM PDT 24
Finished Mar 14 12:34:52 PM PDT 24
Peak memory 191172 kb
Host smart-fbad20f2-d33a-4337-95cc-ee5e54273c0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028866063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3028866063
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3632935772
Short name T286
Test name
Test status
Simulation time 99870771419 ps
CPU time 190.34 seconds
Started Mar 14 12:34:15 PM PDT 24
Finished Mar 14 12:37:26 PM PDT 24
Peak memory 191048 kb
Host smart-c2df2592-3d8a-4bec-966a-533dc63f7b0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632935772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3632935772
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.382516669
Short name T59
Test name
Test status
Simulation time 92763505972 ps
CPU time 38.22 seconds
Started Mar 14 12:34:01 PM PDT 24
Finished Mar 14 12:34:39 PM PDT 24
Peak memory 182892 kb
Host smart-a518aa46-790c-4220-9be4-415d9c0ceb3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382516669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.382516669
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.4254814092
Short name T331
Test name
Test status
Simulation time 50778029764 ps
CPU time 43.6 seconds
Started Mar 14 12:34:08 PM PDT 24
Finished Mar 14 12:34:52 PM PDT 24
Peak memory 182984 kb
Host smart-9545db53-b8e8-4d97-951c-4f16867d3bcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254814092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.4254814092
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.613449835
Short name T344
Test name
Test status
Simulation time 34165554125 ps
CPU time 29.14 seconds
Started Mar 14 12:33:08 PM PDT 24
Finished Mar 14 12:33:38 PM PDT 24
Peak memory 182940 kb
Host smart-51655bb8-8592-44df-90e0-990d7ba7bb02
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613449835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.rv_timer_cfg_update_on_fly.613449835
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.2918554310
Short name T379
Test name
Test status
Simulation time 161772150143 ps
CPU time 151.3 seconds
Started Mar 14 12:33:12 PM PDT 24
Finished Mar 14 12:35:45 PM PDT 24
Peak memory 183012 kb
Host smart-14dbf750-0317-42c5-960d-119009cf06cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918554310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2918554310
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1137139604
Short name T256
Test name
Test status
Simulation time 120248082544 ps
CPU time 143.6 seconds
Started Mar 14 12:33:20 PM PDT 24
Finished Mar 14 12:35:44 PM PDT 24
Peak memory 194728 kb
Host smart-86210f3c-6677-4009-898b-e4c50b3a27cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137139604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1137139604
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.990863548
Short name T62
Test name
Test status
Simulation time 14818963368 ps
CPU time 8.24 seconds
Started Mar 14 12:33:04 PM PDT 24
Finished Mar 14 12:33:13 PM PDT 24
Peak memory 182988 kb
Host smart-8a693ecd-f7b5-439d-aa58-4eb836b8ef78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990863548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.990863548
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.117433166
Short name T20
Test name
Test status
Simulation time 36951506 ps
CPU time 0.74 seconds
Started Mar 14 12:33:21 PM PDT 24
Finished Mar 14 12:33:22 PM PDT 24
Peak memory 213228 kb
Host smart-a5a840ac-643f-4491-b8d1-4175ffc399dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117433166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.117433166
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.849923176
Short name T376
Test name
Test status
Simulation time 273736066045 ps
CPU time 469.05 seconds
Started Mar 14 12:33:14 PM PDT 24
Finished Mar 14 12:41:04 PM PDT 24
Peak memory 191208 kb
Host smart-fea368a3-c27d-438a-bb8e-69f0021c152f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849923176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.849923176
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.968202537
Short name T434
Test name
Test status
Simulation time 521528370516 ps
CPU time 516.48 seconds
Started Mar 14 12:33:21 PM PDT 24
Finished Mar 14 12:41:58 PM PDT 24
Peak memory 182928 kb
Host smart-351f6615-9896-43c7-bdc1-7800c8d6836e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968202537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.rv_timer_cfg_update_on_fly.968202537
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.3486614016
Short name T415
Test name
Test status
Simulation time 141613248498 ps
CPU time 210.46 seconds
Started Mar 14 12:33:30 PM PDT 24
Finished Mar 14 12:37:01 PM PDT 24
Peak memory 182952 kb
Host smart-46fd8e88-4189-4649-8833-d4d941543785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486614016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3486614016
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.2102674565
Short name T275
Test name
Test status
Simulation time 177494999736 ps
CPU time 318.45 seconds
Started Mar 14 12:33:11 PM PDT 24
Finished Mar 14 12:38:30 PM PDT 24
Peak memory 194800 kb
Host smart-c5bab9b0-00fe-4c40-a4d8-35cf6b55d120
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102674565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2102674565
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.334575594
Short name T374
Test name
Test status
Simulation time 208688441271 ps
CPU time 159.19 seconds
Started Mar 14 12:33:24 PM PDT 24
Finished Mar 14 12:36:03 PM PDT 24
Peak memory 182964 kb
Host smart-afa0b367-364e-4314-a6c5-cb277dde92bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334575594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.334575594
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.2254947875
Short name T139
Test name
Test status
Simulation time 190244181863 ps
CPU time 439.7 seconds
Started Mar 14 12:33:10 PM PDT 24
Finished Mar 14 12:40:31 PM PDT 24
Peak memory 191180 kb
Host smart-78101336-849a-43bf-be69-1d7dce9e9eb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254947875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2254947875
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.2715201317
Short name T233
Test name
Test status
Simulation time 96689616594 ps
CPU time 267.64 seconds
Started Mar 14 12:33:30 PM PDT 24
Finished Mar 14 12:37:58 PM PDT 24
Peak memory 191160 kb
Host smart-9ded4f05-2087-4d29-9c3d-71be714b9e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715201317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2715201317
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.955456967
Short name T135
Test name
Test status
Simulation time 489195750690 ps
CPU time 1177.36 seconds
Started Mar 14 12:33:26 PM PDT 24
Finished Mar 14 12:53:03 PM PDT 24
Peak memory 195524 kb
Host smart-15f19ab0-4473-4f13-9064-4dc57d1803af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955456967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.
955456967
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.2383801969
Short name T350
Test name
Test status
Simulation time 548685417818 ps
CPU time 285.84 seconds
Started Mar 14 12:33:35 PM PDT 24
Finished Mar 14 12:38:24 PM PDT 24
Peak memory 182964 kb
Host smart-6a4071fb-4ffb-4c85-8b77-c66ecc482031
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383801969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.2383801969
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.639338853
Short name T23
Test name
Test status
Simulation time 803390057352 ps
CPU time 335.81 seconds
Started Mar 14 12:33:22 PM PDT 24
Finished Mar 14 12:38:58 PM PDT 24
Peak memory 182904 kb
Host smart-cf2620b9-ff10-4770-9ca3-6d667a9745bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639338853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.639338853
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2419388182
Short name T326
Test name
Test status
Simulation time 409961145684 ps
CPU time 546.65 seconds
Started Mar 14 12:33:22 PM PDT 24
Finished Mar 14 12:42:29 PM PDT 24
Peak memory 182860 kb
Host smart-b65cbb2b-9208-44c8-b274-b6f1696f68b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419388182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2419388182
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.704311248
Short name T321
Test name
Test status
Simulation time 242280182480 ps
CPU time 412.2 seconds
Started Mar 14 12:33:27 PM PDT 24
Finished Mar 14 12:40:19 PM PDT 24
Peak memory 182872 kb
Host smart-e30325c8-5d03-4ab8-84ae-b140634a39f2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704311248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.704311248
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.144476711
Short name T21
Test name
Test status
Simulation time 446299194932 ps
CPU time 188.3 seconds
Started Mar 14 12:33:31 PM PDT 24
Finished Mar 14 12:36:40 PM PDT 24
Peak memory 182860 kb
Host smart-2aee4afc-a401-42c7-88fd-2da1e6e989a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144476711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.144476711
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.574943973
Short name T75
Test name
Test status
Simulation time 209432450655 ps
CPU time 552.46 seconds
Started Mar 14 12:33:33 PM PDT 24
Finished Mar 14 12:42:46 PM PDT 24
Peak memory 191184 kb
Host smart-3589b360-82e7-4795-8fc4-1e36af97c431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574943973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.574943973
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3760864417
Short name T304
Test name
Test status
Simulation time 447584152278 ps
CPU time 225.95 seconds
Started Mar 14 12:33:29 PM PDT 24
Finished Mar 14 12:37:15 PM PDT 24
Peak memory 191068 kb
Host smart-6039d0fb-7e3b-48df-8874-7c17dd66e975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760864417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3760864417
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.4224635680
Short name T417
Test name
Test status
Simulation time 64990158 ps
CPU time 0.54 seconds
Started Mar 14 12:33:22 PM PDT 24
Finished Mar 14 12:33:22 PM PDT 24
Peak memory 182696 kb
Host smart-61e359a9-d457-4187-9d9a-6a33d571f182
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224635680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.4224635680
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3674531633
Short name T237
Test name
Test status
Simulation time 950803886655 ps
CPU time 488.4 seconds
Started Mar 14 12:33:34 PM PDT 24
Finished Mar 14 12:41:45 PM PDT 24
Peak memory 182980 kb
Host smart-46a9a92f-77fd-477a-ab0f-50449f4e825c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674531633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3674531633
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.1755960820
Short name T444
Test name
Test status
Simulation time 61187211857 ps
CPU time 84.51 seconds
Started Mar 14 12:33:37 PM PDT 24
Finished Mar 14 12:35:04 PM PDT 24
Peak memory 182992 kb
Host smart-cb484d45-5385-4f47-ae38-9ccd77e6ca2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755960820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.1755960820
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.3441132760
Short name T298
Test name
Test status
Simulation time 217991722378 ps
CPU time 427.62 seconds
Started Mar 14 12:33:10 PM PDT 24
Finished Mar 14 12:40:19 PM PDT 24
Peak memory 191208 kb
Host smart-3e073639-68a5-42c5-8211-fb797f8602f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441132760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3441132760
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2942430241
Short name T7
Test name
Test status
Simulation time 29389195 ps
CPU time 0.57 seconds
Started Mar 14 12:33:34 PM PDT 24
Finished Mar 14 12:33:36 PM PDT 24
Peak memory 182660 kb
Host smart-49a618a6-d485-4c68-94f5-41207fa82ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942430241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2942430241
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.3620199827
Short name T88
Test name
Test status
Simulation time 65306502 ps
CPU time 0.51 seconds
Started Mar 14 12:33:44 PM PDT 24
Finished Mar 14 12:33:45 PM PDT 24
Peak memory 182256 kb
Host smart-4db41225-0ced-488c-93cb-70f7e515f8da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620199827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.3620199827
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.3607815308
Short name T389
Test name
Test status
Simulation time 178212430886 ps
CPU time 214.34 seconds
Started Mar 14 12:33:13 PM PDT 24
Finished Mar 14 12:36:49 PM PDT 24
Peak memory 182968 kb
Host smart-0acb7817-1e07-494f-b994-3124ce95003b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607815308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3607815308
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.896813683
Short name T133
Test name
Test status
Simulation time 215499616706 ps
CPU time 313.66 seconds
Started Mar 14 12:33:37 PM PDT 24
Finished Mar 14 12:38:52 PM PDT 24
Peak memory 191152 kb
Host smart-b7df84ea-ce8e-4a41-bf8a-59643e7dc96d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896813683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.896813683
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1711042904
Short name T307
Test name
Test status
Simulation time 38620428419 ps
CPU time 67.29 seconds
Started Mar 14 12:33:47 PM PDT 24
Finished Mar 14 12:34:54 PM PDT 24
Peak memory 182848 kb
Host smart-db4290b1-ebf2-4cd4-93e2-b4a3b2e2ec30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711042904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1711042904
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2593588845
Short name T194
Test name
Test status
Simulation time 364453865476 ps
CPU time 610 seconds
Started Mar 14 12:33:12 PM PDT 24
Finished Mar 14 12:43:24 PM PDT 24
Peak memory 191192 kb
Host smart-f29198ba-f065-477a-ae75-ef6b38b17cdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593588845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2593588845
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.2305004162
Short name T170
Test name
Test status
Simulation time 307027080036 ps
CPU time 517.01 seconds
Started Mar 14 12:33:46 PM PDT 24
Finished Mar 14 12:42:24 PM PDT 24
Peak memory 182904 kb
Host smart-2fbbd557-f393-4cee-9924-ce374f50d3ea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305004162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.2305004162
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.3024861316
Short name T394
Test name
Test status
Simulation time 327770933400 ps
CPU time 128.48 seconds
Started Mar 14 12:33:21 PM PDT 24
Finished Mar 14 12:35:30 PM PDT 24
Peak memory 182984 kb
Host smart-00424dca-4c4b-4425-aab2-f79c08be0907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024861316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3024861316
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.3363054187
Short name T431
Test name
Test status
Simulation time 351790552097 ps
CPU time 247.96 seconds
Started Mar 14 12:33:39 PM PDT 24
Finished Mar 14 12:37:48 PM PDT 24
Peak memory 191164 kb
Host smart-9f1b42f8-5a05-4449-84c4-e09e28df43f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363054187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3363054187
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2646037956
Short name T244
Test name
Test status
Simulation time 717988956230 ps
CPU time 163.58 seconds
Started Mar 14 12:33:27 PM PDT 24
Finished Mar 14 12:36:11 PM PDT 24
Peak memory 191056 kb
Host smart-bf52e09a-6e5a-4119-a214-243efe1d65dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646037956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2646037956
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.258130923
Short name T87
Test name
Test status
Simulation time 730124831154 ps
CPU time 271.56 seconds
Started Mar 14 12:33:32 PM PDT 24
Finished Mar 14 12:38:03 PM PDT 24
Peak memory 183004 kb
Host smart-a8d5a13a-e417-4276-b0c9-e2b25148da2c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258130923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.258130923
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.4071430750
Short name T368
Test name
Test status
Simulation time 39981196982 ps
CPU time 52.01 seconds
Started Mar 14 12:33:12 PM PDT 24
Finished Mar 14 12:34:10 PM PDT 24
Peak memory 182980 kb
Host smart-955d8936-f209-4aef-af5a-05ba6b00e431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071430750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.4071430750
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.1762988847
Short name T9
Test name
Test status
Simulation time 248868140 ps
CPU time 0.99 seconds
Started Mar 14 12:33:42 PM PDT 24
Finished Mar 14 12:33:43 PM PDT 24
Peak memory 182604 kb
Host smart-6bcfc463-e798-48df-9aa5-d10f7d4149e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762988847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1762988847
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.1961925724
Short name T78
Test name
Test status
Simulation time 18468258 ps
CPU time 0.53 seconds
Started Mar 14 12:33:31 PM PDT 24
Finished Mar 14 12:33:32 PM PDT 24
Peak memory 182600 kb
Host smart-b1f2b687-f471-45b3-8cd6-653025c1b6cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961925724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.1961925724
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.2619442034
Short name T29
Test name
Test status
Simulation time 11906941493 ps
CPU time 17.04 seconds
Started Mar 14 12:33:44 PM PDT 24
Finished Mar 14 12:34:01 PM PDT 24
Peak memory 182828 kb
Host smart-d1fd3474-69dc-4c90-8543-785cc5e0c514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619442034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2619442034
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.120456199
Short name T272
Test name
Test status
Simulation time 297183681579 ps
CPU time 514.58 seconds
Started Mar 14 12:33:46 PM PDT 24
Finished Mar 14 12:42:21 PM PDT 24
Peak memory 191156 kb
Host smart-8b99197a-eaa6-4432-9c52-558a45a140cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120456199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.120456199
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1795973398
Short name T234
Test name
Test status
Simulation time 657537107870 ps
CPU time 676.18 seconds
Started Mar 14 12:33:34 PM PDT 24
Finished Mar 14 12:44:51 PM PDT 24
Peak memory 182960 kb
Host smart-da63c5b9-460a-4cd2-b0f6-07ee1bf7beb1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795973398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1795973398
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2638518322
Short name T362
Test name
Test status
Simulation time 80255294744 ps
CPU time 133.75 seconds
Started Mar 14 12:33:21 PM PDT 24
Finished Mar 14 12:35:35 PM PDT 24
Peak memory 182524 kb
Host smart-781f3e16-c81d-4e3b-bedc-4df0a2065a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638518322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2638518322
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.2527528883
Short name T288
Test name
Test status
Simulation time 122174618730 ps
CPU time 375.79 seconds
Started Mar 14 12:33:26 PM PDT 24
Finished Mar 14 12:39:42 PM PDT 24
Peak memory 191200 kb
Host smart-badc1b2f-f772-47c3-b6e9-0be93f005294
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527528883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2527528883
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1792305519
Short name T414
Test name
Test status
Simulation time 24130927910 ps
CPU time 17.24 seconds
Started Mar 14 12:33:28 PM PDT 24
Finished Mar 14 12:33:45 PM PDT 24
Peak memory 191172 kb
Host smart-21333610-a505-4d80-bc28-376e8ea1bd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792305519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1792305519
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.3617123048
Short name T39
Test name
Test status
Simulation time 94542920110 ps
CPU time 521.11 seconds
Started Mar 14 12:33:38 PM PDT 24
Finished Mar 14 12:42:20 PM PDT 24
Peak memory 205860 kb
Host smart-7aecbec5-e42c-43bc-876e-6f387856b34c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617123048 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.3617123048
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2696363002
Short name T285
Test name
Test status
Simulation time 85368782064 ps
CPU time 35.94 seconds
Started Mar 14 12:33:16 PM PDT 24
Finished Mar 14 12:33:54 PM PDT 24
Peak memory 183028 kb
Host smart-f0edfa0b-54c7-45d7-ae32-d95201457286
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696363002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2696363002
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.736262705
Short name T407
Test name
Test status
Simulation time 73347891802 ps
CPU time 65.62 seconds
Started Mar 14 12:33:08 PM PDT 24
Finished Mar 14 12:34:15 PM PDT 24
Peak memory 182892 kb
Host smart-44ceb27a-c939-45b6-bac7-ab0ed750a65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736262705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.736262705
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.1252752828
Short name T320
Test name
Test status
Simulation time 24754646978 ps
CPU time 21.22 seconds
Started Mar 14 12:33:16 PM PDT 24
Finished Mar 14 12:33:37 PM PDT 24
Peak memory 182824 kb
Host smart-57874eaa-e928-492b-8b58-35714a7aa30e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252752828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1252752828
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3239248024
Short name T370
Test name
Test status
Simulation time 391086742 ps
CPU time 0.67 seconds
Started Mar 14 12:33:17 PM PDT 24
Finished Mar 14 12:33:18 PM PDT 24
Peak memory 182716 kb
Host smart-da324223-a95a-4918-b4fd-5303b3b0fc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239248024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3239248024
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.4165501215
Short name T16
Test name
Test status
Simulation time 451760537 ps
CPU time 0.8 seconds
Started Mar 14 12:33:07 PM PDT 24
Finished Mar 14 12:33:08 PM PDT 24
Peak memory 213224 kb
Host smart-efa388d2-6308-447e-9522-e82a3e517ca6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165501215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.4165501215
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.1925820485
Short name T61
Test name
Test status
Simulation time 596413217271 ps
CPU time 981.26 seconds
Started Mar 14 12:33:07 PM PDT 24
Finished Mar 14 12:49:28 PM PDT 24
Peak memory 191164 kb
Host smart-18c202a1-c1e0-41a9-b57a-45994ccead93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925820485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
1925820485
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.1668061257
Short name T443
Test name
Test status
Simulation time 158442942360 ps
CPU time 270.57 seconds
Started Mar 14 12:33:30 PM PDT 24
Finished Mar 14 12:38:01 PM PDT 24
Peak memory 182996 kb
Host smart-56c8bbcd-b6e6-49d1-b3dc-c44d235f094a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668061257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.1668061257
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.4046411228
Short name T393
Test name
Test status
Simulation time 143335395726 ps
CPU time 205.39 seconds
Started Mar 14 12:33:33 PM PDT 24
Finished Mar 14 12:36:58 PM PDT 24
Peak memory 183012 kb
Host smart-29f0cada-1768-4c2c-8c71-a6c600b07158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046411228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.4046411228
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.1495193993
Short name T162
Test name
Test status
Simulation time 157246981892 ps
CPU time 382.58 seconds
Started Mar 14 12:33:11 PM PDT 24
Finished Mar 14 12:39:35 PM PDT 24
Peak memory 194832 kb
Host smart-11b12e5f-f9a1-462c-b5f2-82d252874060
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495193993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1495193993
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1972453893
Short name T428
Test name
Test status
Simulation time 441372742935 ps
CPU time 3157.87 seconds
Started Mar 14 12:33:10 PM PDT 24
Finished Mar 14 01:25:50 PM PDT 24
Peak memory 191092 kb
Host smart-5de39f25-f8dc-4522-8c21-5ac66810d9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972453893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1972453893
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.450722075
Short name T193
Test name
Test status
Simulation time 705150130788 ps
CPU time 648.79 seconds
Started Mar 14 12:33:13 PM PDT 24
Finished Mar 14 12:44:03 PM PDT 24
Peak memory 191068 kb
Host smart-bdd39e8c-ce38-4016-a338-1cf0efd1f010
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450722075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
450722075
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.750529538
Short name T38
Test name
Test status
Simulation time 40494582655 ps
CPU time 323.31 seconds
Started Mar 14 12:33:19 PM PDT 24
Finished Mar 14 12:38:43 PM PDT 24
Peak memory 205776 kb
Host smart-8a1fc397-4ee4-49a8-95c0-b5b0fc29bb54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750529538 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.750529538
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1350345830
Short name T2
Test name
Test status
Simulation time 485672609401 ps
CPU time 264.91 seconds
Started Mar 14 12:33:13 PM PDT 24
Finished Mar 14 12:37:39 PM PDT 24
Peak memory 182828 kb
Host smart-af2a64de-3509-4a58-aac2-7d892f950840
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350345830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1350345830
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3207489466
Short name T364
Test name
Test status
Simulation time 281682541638 ps
CPU time 149.24 seconds
Started Mar 14 12:33:10 PM PDT 24
Finished Mar 14 12:35:41 PM PDT 24
Peak memory 182916 kb
Host smart-2a92079b-703f-4713-b5cd-684d290f5de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207489466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3207489466
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.37376467
Short name T357
Test name
Test status
Simulation time 55723084428 ps
CPU time 46.93 seconds
Started Mar 14 12:33:07 PM PDT 24
Finished Mar 14 12:33:54 PM PDT 24
Peak memory 191064 kb
Host smart-5b8e9e2e-d911-43eb-98e6-07f466e91c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37376467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.37376467
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.318454581
Short name T358
Test name
Test status
Simulation time 399708731160 ps
CPU time 129.51 seconds
Started Mar 14 12:33:25 PM PDT 24
Finished Mar 14 12:35:35 PM PDT 24
Peak memory 191116 kb
Host smart-592af56d-7648-489c-a6f5-4e3e686924b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318454581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.
318454581
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2162999367
Short name T161
Test name
Test status
Simulation time 14221943739 ps
CPU time 13.94 seconds
Started Mar 14 12:33:27 PM PDT 24
Finished Mar 14 12:33:41 PM PDT 24
Peak memory 182960 kb
Host smart-8043e8d6-deeb-4822-8c9f-f869706127e6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162999367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2162999367
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3697996393
Short name T423
Test name
Test status
Simulation time 70760647869 ps
CPU time 115.36 seconds
Started Mar 14 12:33:35 PM PDT 24
Finished Mar 14 12:35:32 PM PDT 24
Peak memory 182944 kb
Host smart-6adc0cd1-a1c8-4195-9a70-d9749c3e5899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697996393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3697996393
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1954232852
Short name T342
Test name
Test status
Simulation time 71483721238 ps
CPU time 336.04 seconds
Started Mar 14 12:33:32 PM PDT 24
Finished Mar 14 12:39:08 PM PDT 24
Peak memory 191124 kb
Host smart-5e3359b6-ee16-4580-ae94-5579834bba8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954232852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1954232852
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1565327663
Short name T146
Test name
Test status
Simulation time 2442465675092 ps
CPU time 625.64 seconds
Started Mar 14 12:33:14 PM PDT 24
Finished Mar 14 12:43:40 PM PDT 24
Peak memory 182876 kb
Host smart-6f4c06d4-bf18-4f51-880e-8235879d7372
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565327663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.1565327663
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.2658004290
Short name T367
Test name
Test status
Simulation time 308911235937 ps
CPU time 129.31 seconds
Started Mar 14 12:33:10 PM PDT 24
Finished Mar 14 12:35:20 PM PDT 24
Peak memory 183008 kb
Host smart-4853a85c-6ebd-4f4d-bab1-91d30ebc5616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658004290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2658004290
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.2112765151
Short name T260
Test name
Test status
Simulation time 167344144217 ps
CPU time 169.11 seconds
Started Mar 14 12:33:37 PM PDT 24
Finished Mar 14 12:36:27 PM PDT 24
Peak memory 191164 kb
Host smart-275814d6-55fa-4e57-88e7-4afb1bf36dd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112765151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2112765151
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3385925068
Short name T421
Test name
Test status
Simulation time 77149191041 ps
CPU time 138.59 seconds
Started Mar 14 12:33:26 PM PDT 24
Finished Mar 14 12:35:45 PM PDT 24
Peak memory 191096 kb
Host smart-7dcac956-d8e9-4132-9d41-9af625f710d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385925068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3385925068
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3160287457
Short name T384
Test name
Test status
Simulation time 37266818423 ps
CPU time 46.61 seconds
Started Mar 14 12:33:39 PM PDT 24
Finished Mar 14 12:34:27 PM PDT 24
Peak memory 194704 kb
Host smart-881714b7-8cfc-44a7-be75-4291fef21047
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160287457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3160287457
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3328021114
Short name T57
Test name
Test status
Simulation time 1493089596070 ps
CPU time 747.32 seconds
Started Mar 14 12:33:40 PM PDT 24
Finished Mar 14 12:46:08 PM PDT 24
Peak memory 182948 kb
Host smart-69397416-1eaa-4d1a-9a7a-a83f106367da
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328021114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3328021114
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.2323619447
Short name T412
Test name
Test status
Simulation time 121042297603 ps
CPU time 192.48 seconds
Started Mar 14 12:33:43 PM PDT 24
Finished Mar 14 12:36:56 PM PDT 24
Peak memory 182988 kb
Host smart-fe594a6b-1f36-42f6-9c46-2381b3579d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323619447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2323619447
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.65218479
Short name T27
Test name
Test status
Simulation time 99428703787 ps
CPU time 187.68 seconds
Started Mar 14 12:33:31 PM PDT 24
Finished Mar 14 12:36:39 PM PDT 24
Peak memory 191172 kb
Host smart-8df9231b-cb2d-4839-b6d2-645e6933ded8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65218479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.65218479
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.716942393
Short name T199
Test name
Test status
Simulation time 53457650667 ps
CPU time 89.78 seconds
Started Mar 14 12:33:43 PM PDT 24
Finished Mar 14 12:35:14 PM PDT 24
Peak memory 191208 kb
Host smart-abe5b2ab-90cb-42a2-a21d-1a5345a0149d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716942393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.716942393
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3287541737
Short name T156
Test name
Test status
Simulation time 1823703741903 ps
CPU time 1001.04 seconds
Started Mar 14 12:33:16 PM PDT 24
Finished Mar 14 12:50:07 PM PDT 24
Peak memory 191216 kb
Host smart-3c15639e-90e1-4061-886c-4e27c246da14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287541737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3287541737
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3681176304
Short name T424
Test name
Test status
Simulation time 86731612012 ps
CPU time 49.1 seconds
Started Mar 14 12:33:38 PM PDT 24
Finished Mar 14 12:34:28 PM PDT 24
Peak memory 182928 kb
Host smart-178ae4a5-672f-427e-8206-1e213eb4e6d1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681176304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3681176304
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1599300233
Short name T375
Test name
Test status
Simulation time 302804951773 ps
CPU time 246.16 seconds
Started Mar 14 12:33:12 PM PDT 24
Finished Mar 14 12:37:20 PM PDT 24
Peak memory 182772 kb
Host smart-ef017745-7dab-4fcb-a08d-ca1f7b81e454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599300233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1599300233
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.3658914299
Short name T259
Test name
Test status
Simulation time 44338756030 ps
CPU time 78.07 seconds
Started Mar 14 12:33:39 PM PDT 24
Finished Mar 14 12:34:58 PM PDT 24
Peak memory 183052 kb
Host smart-e253b53b-534d-480c-a178-b577e6f74ce7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658914299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3658914299
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3829339723
Short name T442
Test name
Test status
Simulation time 14712826164 ps
CPU time 10.71 seconds
Started Mar 14 12:33:35 PM PDT 24
Finished Mar 14 12:33:48 PM PDT 24
Peak memory 182944 kb
Host smart-eecb25c6-9c97-4253-9db2-abb79f3e922b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829339723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3829339723
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.976090869
Short name T292
Test name
Test status
Simulation time 65144118125 ps
CPU time 102.17 seconds
Started Mar 14 12:33:34 PM PDT 24
Finished Mar 14 12:35:18 PM PDT 24
Peak memory 191176 kb
Host smart-6d4163e1-6b71-43d6-906e-c9aa41088588
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976090869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.976090869
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.262970319
Short name T390
Test name
Test status
Simulation time 160873247 ps
CPU time 0.83 seconds
Started Mar 14 12:33:40 PM PDT 24
Finished Mar 14 12:33:41 PM PDT 24
Peak memory 182728 kb
Host smart-432ebef5-06f3-4a77-8e7a-8aedf577e0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262970319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.262970319
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.2519810984
Short name T445
Test name
Test status
Simulation time 362158257551 ps
CPU time 279.63 seconds
Started Mar 14 12:33:43 PM PDT 24
Finished Mar 14 12:38:23 PM PDT 24
Peak memory 195504 kb
Host smart-8f79265f-8568-4652-a02f-0063f2227fb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519810984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.2519810984
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1393578898
Short name T378
Test name
Test status
Simulation time 202927337797 ps
CPU time 89.33 seconds
Started Mar 14 12:33:46 PM PDT 24
Finished Mar 14 12:35:16 PM PDT 24
Peak memory 182964 kb
Host smart-17758554-acb1-433b-ba4c-4063ebcda5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393578898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1393578898
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2315225283
Short name T319
Test name
Test status
Simulation time 105612814289 ps
CPU time 1992.92 seconds
Started Mar 14 12:33:34 PM PDT 24
Finished Mar 14 01:06:49 PM PDT 24
Peak memory 191156 kb
Host smart-81268379-0303-4dba-886b-e803250b4d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315225283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2315225283
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3847205250
Short name T436
Test name
Test status
Simulation time 213912391134 ps
CPU time 322 seconds
Started Mar 14 12:33:31 PM PDT 24
Finished Mar 14 12:38:53 PM PDT 24
Peak memory 191064 kb
Host smart-259c5e9f-2c4a-4cbb-ad1b-c2b797fffdd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847205250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3847205250
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3909361246
Short name T282
Test name
Test status
Simulation time 815511764112 ps
CPU time 813.91 seconds
Started Mar 14 12:33:43 PM PDT 24
Finished Mar 14 12:47:17 PM PDT 24
Peak memory 182868 kb
Host smart-e38d0732-7242-4c76-bd7a-bf23c225f21f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909361246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3909361246
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.4247316647
Short name T406
Test name
Test status
Simulation time 382803846710 ps
CPU time 143.81 seconds
Started Mar 14 12:33:38 PM PDT 24
Finished Mar 14 12:36:04 PM PDT 24
Peak memory 182960 kb
Host smart-0cc00862-4d1e-4913-a869-2e4b6c76a2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247316647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.4247316647
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.1434959666
Short name T137
Test name
Test status
Simulation time 168696548839 ps
CPU time 658.85 seconds
Started Mar 14 12:33:41 PM PDT 24
Finished Mar 14 12:44:41 PM PDT 24
Peak memory 191192 kb
Host smart-312b9417-19f7-4caa-88d6-ee9d869461cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434959666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1434959666
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1012228026
Short name T333
Test name
Test status
Simulation time 1365848006 ps
CPU time 2.58 seconds
Started Mar 14 12:33:14 PM PDT 24
Finished Mar 14 12:33:17 PM PDT 24
Peak memory 182748 kb
Host smart-bc5c8e03-67a2-4136-b392-606efe6c2d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012228026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1012228026
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.2855324823
Short name T72
Test name
Test status
Simulation time 300699663575 ps
CPU time 390.22 seconds
Started Mar 14 12:33:26 PM PDT 24
Finished Mar 14 12:39:57 PM PDT 24
Peak memory 182916 kb
Host smart-9ae06901-ef62-418d-b36b-f7304d7fc15b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855324823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.2855324823
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.993910007
Short name T183
Test name
Test status
Simulation time 1712061897109 ps
CPU time 873.07 seconds
Started Mar 14 12:33:32 PM PDT 24
Finished Mar 14 12:48:06 PM PDT 24
Peak memory 182996 kb
Host smart-7e930484-413c-43d7-bf07-5f034375037a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993910007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.rv_timer_cfg_update_on_fly.993910007
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.551646530
Short name T278
Test name
Test status
Simulation time 25486284915 ps
CPU time 41.36 seconds
Started Mar 14 12:33:28 PM PDT 24
Finished Mar 14 12:34:10 PM PDT 24
Peak memory 191196 kb
Host smart-532823e3-3fbd-42cc-886d-dd7e3eceda79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551646530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.551646530
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2364244535
Short name T401
Test name
Test status
Simulation time 101971650984 ps
CPU time 159.47 seconds
Started Mar 14 12:33:11 PM PDT 24
Finished Mar 14 12:35:52 PM PDT 24
Peak memory 182964 kb
Host smart-c2a258eb-15d6-40d4-ab57-7cd5a99b7e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364244535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2364244535
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.1584611157
Short name T231
Test name
Test status
Simulation time 170599631284 ps
CPU time 438.12 seconds
Started Mar 14 12:33:13 PM PDT 24
Finished Mar 14 12:40:32 PM PDT 24
Peak memory 194080 kb
Host smart-9dba4b7c-b180-475c-a670-222230c565a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584611157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.1584611157
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2212173149
Short name T84
Test name
Test status
Simulation time 13778837215 ps
CPU time 13.09 seconds
Started Mar 14 12:32:56 PM PDT 24
Finished Mar 14 12:33:09 PM PDT 24
Peak memory 191156 kb
Host smart-570fa1e7-e748-4107-b862-2a7322e30377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212173149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2212173149
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2277016019
Short name T18
Test name
Test status
Simulation time 146198328 ps
CPU time 0.83 seconds
Started Mar 14 12:33:12 PM PDT 24
Finished Mar 14 12:33:15 PM PDT 24
Peak memory 213276 kb
Host smart-c0fbc75f-0e7c-499d-b356-1863769862dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277016019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2277016019
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.129223366
Short name T68
Test name
Test status
Simulation time 1246247738713 ps
CPU time 988.72 seconds
Started Mar 14 12:33:34 PM PDT 24
Finished Mar 14 12:50:05 PM PDT 24
Peak memory 191172 kb
Host smart-d2949174-c835-42da-ac57-6cb3d94066a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129223366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.129223366
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.825883800
Short name T432
Test name
Test status
Simulation time 80935109729 ps
CPU time 137.83 seconds
Started Mar 14 12:33:31 PM PDT 24
Finished Mar 14 12:35:49 PM PDT 24
Peak memory 182992 kb
Host smart-74effe83-f9f2-436f-ba6f-c182187e7d9a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825883800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.rv_timer_cfg_update_on_fly.825883800
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2041481984
Short name T5
Test name
Test status
Simulation time 371438602410 ps
CPU time 306.97 seconds
Started Mar 14 12:33:21 PM PDT 24
Finished Mar 14 12:38:34 PM PDT 24
Peak memory 182948 kb
Host smart-5b290dd7-0d4a-41ef-a49e-ed9e984f7d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041481984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2041481984
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.508464930
Short name T130
Test name
Test status
Simulation time 187208750690 ps
CPU time 2134.38 seconds
Started Mar 14 12:33:33 PM PDT 24
Finished Mar 14 01:09:08 PM PDT 24
Peak memory 191156 kb
Host smart-17509d8c-4500-49f3-8f33-11a460d5d471
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508464930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.508464930
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1606740192
Short name T213
Test name
Test status
Simulation time 182328803584 ps
CPU time 349.53 seconds
Started Mar 14 12:33:38 PM PDT 24
Finished Mar 14 12:39:29 PM PDT 24
Peak memory 191160 kb
Host smart-f2a39317-c3df-4388-929d-a13734230edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606740192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1606740192
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1155254183
Short name T340
Test name
Test status
Simulation time 1805669076146 ps
CPU time 735.59 seconds
Started Mar 14 12:33:47 PM PDT 24
Finished Mar 14 12:46:03 PM PDT 24
Peak memory 182996 kb
Host smart-800ade7e-2c57-4f7f-ad3d-57acf86d5eab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155254183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1155254183
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3319314394
Short name T403
Test name
Test status
Simulation time 49673793481 ps
CPU time 81.69 seconds
Started Mar 14 12:33:44 PM PDT 24
Finished Mar 14 12:35:06 PM PDT 24
Peak memory 182984 kb
Host smart-7e724818-7c90-42d2-9044-1b7a80f149be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319314394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3319314394
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3554136916
Short name T355
Test name
Test status
Simulation time 23527577008 ps
CPU time 320.19 seconds
Started Mar 14 12:33:38 PM PDT 24
Finished Mar 14 12:39:00 PM PDT 24
Peak memory 182944 kb
Host smart-c87af4cc-9fd5-47a2-9e3f-7832499c1f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554136916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3554136916
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.4159392739
Short name T338
Test name
Test status
Simulation time 282559428841 ps
CPU time 506.35 seconds
Started Mar 14 12:33:36 PM PDT 24
Finished Mar 14 12:42:05 PM PDT 24
Peak memory 183048 kb
Host smart-9187c913-744c-4432-949c-a4021cae84da
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159392739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.4159392739
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1190882614
Short name T399
Test name
Test status
Simulation time 60910868829 ps
CPU time 92.01 seconds
Started Mar 14 12:33:46 PM PDT 24
Finished Mar 14 12:35:19 PM PDT 24
Peak memory 182852 kb
Host smart-ace2d69c-45a0-4406-a262-16e9f2e890cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190882614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1190882614
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.3502667925
Short name T335
Test name
Test status
Simulation time 71325156056 ps
CPU time 85.48 seconds
Started Mar 14 12:33:31 PM PDT 24
Finished Mar 14 12:34:56 PM PDT 24
Peak memory 191064 kb
Host smart-84998e41-0f6d-4518-8461-f757714e5dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502667925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.3502667925
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.3393067655
Short name T15
Test name
Test status
Simulation time 57957021038 ps
CPU time 307.56 seconds
Started Mar 14 12:33:40 PM PDT 24
Finished Mar 14 12:38:48 PM PDT 24
Peak memory 205592 kb
Host smart-24b7c822-46fa-4358-a496-12f0232d9f94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393067655 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.3393067655
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1535641208
Short name T324
Test name
Test status
Simulation time 12811852227 ps
CPU time 21.67 seconds
Started Mar 14 12:33:49 PM PDT 24
Finished Mar 14 12:34:11 PM PDT 24
Peak memory 183004 kb
Host smart-c11f3614-59e2-4025-be1e-dae60d5fb743
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535641208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1535641208
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3443404970
Short name T404
Test name
Test status
Simulation time 506414514982 ps
CPU time 204.12 seconds
Started Mar 14 12:33:43 PM PDT 24
Finished Mar 14 12:37:08 PM PDT 24
Peak memory 182972 kb
Host smart-84e39e3d-687b-49a1-94bb-8d22f3b2c1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443404970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3443404970
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.1258496557
Short name T148
Test name
Test status
Simulation time 146123954644 ps
CPU time 290.65 seconds
Started Mar 14 12:33:43 PM PDT 24
Finished Mar 14 12:38:34 PM PDT 24
Peak memory 182952 kb
Host smart-7468085e-673d-46e6-b903-7a536f1eeb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258496557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1258496557
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.4128665818
Short name T56
Test name
Test status
Simulation time 287098448054 ps
CPU time 420.55 seconds
Started Mar 14 12:33:41 PM PDT 24
Finished Mar 14 12:40:43 PM PDT 24
Peak memory 195072 kb
Host smart-e48c3837-924b-4ce0-945b-00b253601e75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128665818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.4128665818
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.2499784604
Short name T14
Test name
Test status
Simulation time 89491068952 ps
CPU time 153.63 seconds
Started Mar 14 12:33:46 PM PDT 24
Finished Mar 14 12:36:20 PM PDT 24
Peak memory 205736 kb
Host smart-ac69e5ec-1848-4e58-a4cb-b1609c7dfb0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499784604 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.2499784604
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3061705485
Short name T267
Test name
Test status
Simulation time 605520208945 ps
CPU time 292.31 seconds
Started Mar 14 12:33:37 PM PDT 24
Finished Mar 14 12:38:31 PM PDT 24
Peak memory 182952 kb
Host smart-a60902a7-001a-438f-ac3c-eeae8c7e5d58
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061705485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3061705485
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3978964349
Short name T386
Test name
Test status
Simulation time 251924745674 ps
CPU time 70.64 seconds
Started Mar 14 12:33:34 PM PDT 24
Finished Mar 14 12:34:47 PM PDT 24
Peak memory 182900 kb
Host smart-6e8063c0-c5ca-443b-9c00-cd2fa41172bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978964349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3978964349
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1634786084
Short name T242
Test name
Test status
Simulation time 400673030882 ps
CPU time 517.03 seconds
Started Mar 14 12:33:38 PM PDT 24
Finished Mar 14 12:42:16 PM PDT 24
Peak memory 191056 kb
Host smart-8580ed51-bce3-4243-a95e-7cdc7960e114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634786084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1634786084
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1525826496
Short name T337
Test name
Test status
Simulation time 36608046427 ps
CPU time 1362.9 seconds
Started Mar 14 12:33:37 PM PDT 24
Finished Mar 14 12:56:22 PM PDT 24
Peak memory 191176 kb
Host smart-d9a305cb-15d0-476c-9cc7-60009aa53299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525826496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1525826496
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.554226646
Short name T42
Test name
Test status
Simulation time 748902124597 ps
CPU time 416.56 seconds
Started Mar 14 12:33:46 PM PDT 24
Finished Mar 14 12:40:43 PM PDT 24
Peak memory 182872 kb
Host smart-59eff57d-0104-4c03-a27f-0beac6832a56
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554226646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.554226646
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2171186354
Short name T385
Test name
Test status
Simulation time 115528090453 ps
CPU time 52.17 seconds
Started Mar 14 12:33:36 PM PDT 24
Finished Mar 14 12:34:30 PM PDT 24
Peak memory 182904 kb
Host smart-ce04451d-5b41-42b0-a114-e4fe7dac57f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171186354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2171186354
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2882304911
Short name T392
Test name
Test status
Simulation time 9435117459 ps
CPU time 17.39 seconds
Started Mar 14 12:33:45 PM PDT 24
Finished Mar 14 12:34:02 PM PDT 24
Peak memory 182956 kb
Host smart-b27234f4-be65-4e55-893e-e13d001aae57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882304911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2882304911
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3744819078
Short name T317
Test name
Test status
Simulation time 227117358780 ps
CPU time 412.59 seconds
Started Mar 14 12:33:45 PM PDT 24
Finished Mar 14 12:40:37 PM PDT 24
Peak memory 182972 kb
Host smart-f07e8d45-e4f0-4c83-9cde-368092c78148
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744819078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3744819078
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3949522431
Short name T425
Test name
Test status
Simulation time 26762289739 ps
CPU time 39.83 seconds
Started Mar 14 12:33:40 PM PDT 24
Finished Mar 14 12:34:20 PM PDT 24
Peak memory 182960 kb
Host smart-2731a4c0-71ec-44ca-a493-934e699f47e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949522431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3949522431
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2810953306
Short name T215
Test name
Test status
Simulation time 77939249402 ps
CPU time 229.85 seconds
Started Mar 14 12:33:43 PM PDT 24
Finished Mar 14 12:37:33 PM PDT 24
Peak memory 191204 kb
Host smart-647bb208-8f9c-4c56-8079-bd98cbd3ef00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810953306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2810953306
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2793270472
Short name T134
Test name
Test status
Simulation time 993349707151 ps
CPU time 506.58 seconds
Started Mar 14 12:33:42 PM PDT 24
Finished Mar 14 12:42:09 PM PDT 24
Peak memory 182876 kb
Host smart-c466b05f-8bf8-4aef-b6d1-4676cce33f3e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793270472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2793270472
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.900263961
Short name T402
Test name
Test status
Simulation time 47741983762 ps
CPU time 72.87 seconds
Started Mar 14 12:33:36 PM PDT 24
Finished Mar 14 12:34:51 PM PDT 24
Peak memory 182992 kb
Host smart-390a6e79-8bea-4f86-9127-67abbc186684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900263961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.900263961
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.3150270336
Short name T253
Test name
Test status
Simulation time 89870057007 ps
CPU time 51.08 seconds
Started Mar 14 12:33:44 PM PDT 24
Finished Mar 14 12:34:35 PM PDT 24
Peak memory 191148 kb
Host smart-b84929bb-cdb4-4e4b-bdff-069be4c9018f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150270336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3150270336
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3161192641
Short name T3
Test name
Test status
Simulation time 309023316346 ps
CPU time 534.83 seconds
Started Mar 14 12:33:43 PM PDT 24
Finished Mar 14 12:42:38 PM PDT 24
Peak memory 182876 kb
Host smart-6e619730-0518-45d1-9e3e-9d2b8e01dd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161192641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3161192641
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.2347190303
Short name T86
Test name
Test status
Simulation time 680449711121 ps
CPU time 338.58 seconds
Started Mar 14 12:33:41 PM PDT 24
Finished Mar 14 12:39:20 PM PDT 24
Peak memory 182912 kb
Host smart-58690830-c6f7-425b-b8d2-6091c0f7d4f9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347190303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.2347190303
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1783220306
Short name T361
Test name
Test status
Simulation time 86289199049 ps
CPU time 95.14 seconds
Started Mar 14 12:33:37 PM PDT 24
Finished Mar 14 12:35:13 PM PDT 24
Peak memory 182952 kb
Host smart-7f524e7c-4fed-460f-a0f5-623da19e7811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783220306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1783220306
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.4037464984
Short name T165
Test name
Test status
Simulation time 1209115339687 ps
CPU time 290.58 seconds
Started Mar 14 12:33:44 PM PDT 24
Finished Mar 14 12:38:35 PM PDT 24
Peak memory 191168 kb
Host smart-e8e74f91-4617-4386-8cc7-b2f5cdaedf3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037464984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.4037464984
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2845662319
Short name T405
Test name
Test status
Simulation time 12333478293 ps
CPU time 10.16 seconds
Started Mar 14 12:33:45 PM PDT 24
Finished Mar 14 12:33:55 PM PDT 24
Peak memory 182964 kb
Host smart-5c20b06f-42ba-4569-92b7-a9adc18256ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845662319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2845662319
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.765736945
Short name T195
Test name
Test status
Simulation time 284374582190 ps
CPU time 608.68 seconds
Started Mar 14 12:33:38 PM PDT 24
Finished Mar 14 12:43:48 PM PDT 24
Peak memory 191092 kb
Host smart-51fa0a2c-8e16-4b63-bf72-9a76c33655b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765736945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.
765736945
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2220521657
Short name T397
Test name
Test status
Simulation time 1277541980207 ps
CPU time 944.46 seconds
Started Mar 14 12:33:46 PM PDT 24
Finished Mar 14 12:49:30 PM PDT 24
Peak memory 182952 kb
Host smart-8777d787-f399-42b7-9d4c-a75510bf0316
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220521657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2220521657
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3400844296
Short name T427
Test name
Test status
Simulation time 189914546845 ps
CPU time 161.9 seconds
Started Mar 14 12:33:46 PM PDT 24
Finished Mar 14 12:36:29 PM PDT 24
Peak memory 182968 kb
Host smart-e3e40449-2c59-48e8-a1c7-60cb5166fd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400844296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3400844296
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.4050845340
Short name T351
Test name
Test status
Simulation time 314494828103 ps
CPU time 242.22 seconds
Started Mar 14 12:33:41 PM PDT 24
Finished Mar 14 12:37:44 PM PDT 24
Peak memory 191092 kb
Host smart-a3ff0d3e-38b5-4e0e-b038-568a2d7f50c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050845340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.4050845340
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1677108683
Short name T82
Test name
Test status
Simulation time 798953738960 ps
CPU time 743.84 seconds
Started Mar 14 12:33:36 PM PDT 24
Finished Mar 14 12:46:01 PM PDT 24
Peak memory 191132 kb
Host smart-cafbb344-bbc6-48dc-99d6-e10ab85886cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677108683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1677108683
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1973190226
Short name T167
Test name
Test status
Simulation time 171081592669 ps
CPU time 68.76 seconds
Started Mar 14 12:33:11 PM PDT 24
Finished Mar 14 12:34:21 PM PDT 24
Peak memory 182980 kb
Host smart-679cda58-221e-464b-916c-bc3ab7a6453c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973190226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1973190226
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.2512760908
Short name T371
Test name
Test status
Simulation time 25939449712 ps
CPU time 37.25 seconds
Started Mar 14 12:33:19 PM PDT 24
Finished Mar 14 12:33:56 PM PDT 24
Peak memory 182808 kb
Host smart-791475df-9678-4b6e-a7e2-ad9492522495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512760908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2512760908
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.1392375802
Short name T277
Test name
Test status
Simulation time 122944561201 ps
CPU time 352.52 seconds
Started Mar 14 12:33:16 PM PDT 24
Finished Mar 14 12:39:11 PM PDT 24
Peak memory 191116 kb
Host smart-fc74a490-ec3a-4dad-bd83-9c5c4b236911
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392375802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1392375802
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.169506016
Short name T24
Test name
Test status
Simulation time 279223027497 ps
CPU time 191.42 seconds
Started Mar 14 12:33:10 PM PDT 24
Finished Mar 14 12:36:23 PM PDT 24
Peak memory 191184 kb
Host smart-f299f9da-c125-486b-8447-d5ec3b1b2d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169506016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.169506016
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1208863547
Short name T131
Test name
Test status
Simulation time 7006225378612 ps
CPU time 2655.85 seconds
Started Mar 14 12:33:10 PM PDT 24
Finished Mar 14 01:17:28 PM PDT 24
Peak memory 191104 kb
Host smart-2ca5468a-b24f-45a2-962e-91b9f2d224cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208863547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1208863547
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.2013077619
Short name T36
Test name
Test status
Simulation time 82484521024 ps
CPU time 880.38 seconds
Started Mar 14 12:33:09 PM PDT 24
Finished Mar 14 12:47:50 PM PDT 24
Peak memory 210396 kb
Host smart-c19e8cdc-42eb-48f3-8bb2-351b81c18d5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013077619 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.2013077619
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.1510872512
Short name T343
Test name
Test status
Simulation time 169520391448 ps
CPU time 163.89 seconds
Started Mar 14 12:33:41 PM PDT 24
Finished Mar 14 12:36:25 PM PDT 24
Peak memory 191108 kb
Host smart-e437761a-455c-4077-8bb7-183dd6aabc31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510872512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1510872512
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.1074733954
Short name T341
Test name
Test status
Simulation time 51680120993 ps
CPU time 81.28 seconds
Started Mar 14 12:33:38 PM PDT 24
Finished Mar 14 12:35:00 PM PDT 24
Peak memory 191148 kb
Host smart-ae9cf5a1-fea3-4615-a640-5a75cc320034
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074733954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1074733954
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.3656380186
Short name T147
Test name
Test status
Simulation time 256892909213 ps
CPU time 331.89 seconds
Started Mar 14 12:33:46 PM PDT 24
Finished Mar 14 12:39:19 PM PDT 24
Peak memory 191060 kb
Host smart-d88f142e-569c-4e10-af9a-1fd160539b0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656380186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3656380186
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.2622817424
Short name T310
Test name
Test status
Simulation time 340198492139 ps
CPU time 525.72 seconds
Started Mar 14 12:33:52 PM PDT 24
Finished Mar 14 12:42:38 PM PDT 24
Peak memory 191140 kb
Host smart-8be6b6f2-ee18-4d57-b1b9-809bb9ae7ffa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622817424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2622817424
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.3665719498
Short name T28
Test name
Test status
Simulation time 438764620087 ps
CPU time 1295.5 seconds
Started Mar 14 12:33:43 PM PDT 24
Finished Mar 14 12:55:19 PM PDT 24
Peak memory 191168 kb
Host smart-a1e3c285-ab34-424e-9010-4257286d896f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665719498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3665719498
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3061516062
Short name T159
Test name
Test status
Simulation time 124293814919 ps
CPU time 181.75 seconds
Started Mar 14 12:33:50 PM PDT 24
Finished Mar 14 12:36:52 PM PDT 24
Peak memory 191204 kb
Host smart-d18bf2a2-770d-4e44-8def-eafd56ca1910
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061516062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3061516062
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.3193947880
Short name T302
Test name
Test status
Simulation time 533966174276 ps
CPU time 956.38 seconds
Started Mar 14 12:33:43 PM PDT 24
Finished Mar 14 12:49:40 PM PDT 24
Peak memory 191104 kb
Host smart-90b771c5-f36e-4684-b0b7-01222d0fedeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193947880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3193947880
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.2808750639
Short name T287
Test name
Test status
Simulation time 224993917648 ps
CPU time 530.16 seconds
Started Mar 14 12:33:51 PM PDT 24
Finished Mar 14 12:42:42 PM PDT 24
Peak memory 191196 kb
Host smart-bef4021b-d14c-4832-8ccb-c8f10905abfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808750639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.2808750639
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1979359603
Short name T339
Test name
Test status
Simulation time 174568785950 ps
CPU time 775.58 seconds
Started Mar 14 12:33:45 PM PDT 24
Finished Mar 14 12:46:41 PM PDT 24
Peak memory 194056 kb
Host smart-e95a0d44-ac7e-4bc5-a1ed-8a47f42e7e4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979359603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1979359603
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.4040226525
Short name T293
Test name
Test status
Simulation time 626729075951 ps
CPU time 567.47 seconds
Started Mar 14 12:33:12 PM PDT 24
Finished Mar 14 12:42:42 PM PDT 24
Peak memory 182996 kb
Host smart-d9ccab9b-f2fe-44c1-8955-fa3f36247a03
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040226525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.4040226525
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.39673685
Short name T58
Test name
Test status
Simulation time 220244409911 ps
CPU time 63.19 seconds
Started Mar 14 12:33:09 PM PDT 24
Finished Mar 14 12:34:13 PM PDT 24
Peak memory 182964 kb
Host smart-77ec27b3-3444-40e9-8849-0deea5633814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39673685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.39673685
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.96014332
Short name T210
Test name
Test status
Simulation time 96370081295 ps
CPU time 173.79 seconds
Started Mar 14 12:33:16 PM PDT 24
Finished Mar 14 12:36:09 PM PDT 24
Peak memory 191200 kb
Host smart-d4baed09-eb15-42b0-86db-ff383885d22a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96014332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.96014332
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1176581553
Short name T372
Test name
Test status
Simulation time 486784371 ps
CPU time 1.18 seconds
Started Mar 14 12:33:26 PM PDT 24
Finished Mar 14 12:33:27 PM PDT 24
Peak memory 182720 kb
Host smart-e4e50932-371a-4c32-8e7d-48df6b41302f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176581553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1176581553
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.3976540132
Short name T153
Test name
Test status
Simulation time 301574042281 ps
CPU time 509.01 seconds
Started Mar 14 12:33:47 PM PDT 24
Finished Mar 14 12:42:16 PM PDT 24
Peak memory 191132 kb
Host smart-7bd84024-d7a8-4dd5-88dc-f3ac026c5d1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976540132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3976540132
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.3264918855
Short name T41
Test name
Test status
Simulation time 78189065424 ps
CPU time 63.27 seconds
Started Mar 14 12:33:55 PM PDT 24
Finished Mar 14 12:34:59 PM PDT 24
Peak memory 182996 kb
Host smart-566b649d-f278-4a4d-8876-1b25e653398e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264918855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3264918855
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.3085836636
Short name T270
Test name
Test status
Simulation time 669987285966 ps
CPU time 198.16 seconds
Started Mar 14 12:34:00 PM PDT 24
Finished Mar 14 12:37:18 PM PDT 24
Peak memory 191088 kb
Host smart-54735b60-73de-4ae6-a8a5-abf5d6ce7586
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085836636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3085836636
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.4166279549
Short name T218
Test name
Test status
Simulation time 112556378526 ps
CPU time 447.78 seconds
Started Mar 14 12:33:51 PM PDT 24
Finished Mar 14 12:41:18 PM PDT 24
Peak memory 191160 kb
Host smart-2393197a-7aa2-4177-8142-a4b177367785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166279549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.4166279549
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.3973220466
Short name T168
Test name
Test status
Simulation time 178177988617 ps
CPU time 318.03 seconds
Started Mar 14 12:33:58 PM PDT 24
Finished Mar 14 12:39:16 PM PDT 24
Peak memory 191216 kb
Host smart-e0a77bcf-f015-4357-854d-d71d82d029c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973220466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3973220466
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.2995186223
Short name T279
Test name
Test status
Simulation time 2817237152337 ps
CPU time 753.02 seconds
Started Mar 14 12:33:41 PM PDT 24
Finished Mar 14 12:46:15 PM PDT 24
Peak memory 191184 kb
Host smart-9a28b9ef-6015-4155-97e2-d7771132f0a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995186223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2995186223
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.474803005
Short name T305
Test name
Test status
Simulation time 67569111090 ps
CPU time 562.93 seconds
Started Mar 14 12:33:54 PM PDT 24
Finished Mar 14 12:43:17 PM PDT 24
Peak memory 191172 kb
Host smart-e38973bb-fa65-4795-ab2e-58d3894284d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474803005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.474803005
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3117247496
Short name T251
Test name
Test status
Simulation time 89848769028 ps
CPU time 132.08 seconds
Started Mar 14 12:33:54 PM PDT 24
Finished Mar 14 12:36:06 PM PDT 24
Peak memory 191076 kb
Host smart-c56fc5f4-c059-4dfc-be81-16c12af0fa6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117247496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3117247496
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1134419822
Short name T299
Test name
Test status
Simulation time 238351728753 ps
CPU time 393.09 seconds
Started Mar 14 12:33:19 PM PDT 24
Finished Mar 14 12:39:52 PM PDT 24
Peak memory 182820 kb
Host smart-aaf44721-9d52-4abf-93ab-47bc9e193a6b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134419822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1134419822
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.2424810091
Short name T388
Test name
Test status
Simulation time 164123425179 ps
CPU time 228.61 seconds
Started Mar 14 12:33:10 PM PDT 24
Finished Mar 14 12:37:01 PM PDT 24
Peak memory 182908 kb
Host smart-b7db06ed-b87f-4eaf-849c-f430c24225ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424810091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.2424810091
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.2794264819
Short name T126
Test name
Test status
Simulation time 297272539420 ps
CPU time 818.15 seconds
Started Mar 14 12:33:02 PM PDT 24
Finished Mar 14 12:46:40 PM PDT 24
Peak memory 191152 kb
Host smart-922bd11c-2dc4-4907-9aa4-09216e0a4c94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794264819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2794264819
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.3018946239
Short name T44
Test name
Test status
Simulation time 28626933154 ps
CPU time 37.78 seconds
Started Mar 14 12:33:17 PM PDT 24
Finished Mar 14 12:33:55 PM PDT 24
Peak memory 194928 kb
Host smart-8e6236cd-abe5-4616-a652-bc4609597220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018946239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3018946239
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.918594470
Short name T120
Test name
Test status
Simulation time 106201324585 ps
CPU time 100.41 seconds
Started Mar 14 12:33:47 PM PDT 24
Finished Mar 14 12:35:28 PM PDT 24
Peak memory 191156 kb
Host smart-5d24d541-42a7-4bd0-8343-e98eddf5dc7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918594470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.918594470
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.546168326
Short name T152
Test name
Test status
Simulation time 27392005662 ps
CPU time 48.76 seconds
Started Mar 14 12:33:50 PM PDT 24
Finished Mar 14 12:34:39 PM PDT 24
Peak memory 191208 kb
Host smart-09c3919a-242b-4abf-9bd6-cd518c86a921
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546168326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.546168326
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.4218589892
Short name T214
Test name
Test status
Simulation time 288861691268 ps
CPU time 160.13 seconds
Started Mar 14 12:33:50 PM PDT 24
Finished Mar 14 12:36:30 PM PDT 24
Peak memory 191144 kb
Host smart-12757ee1-a34e-4768-934f-38efecec05bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218589892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.4218589892
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.4153820716
Short name T265
Test name
Test status
Simulation time 212975288888 ps
CPU time 199.38 seconds
Started Mar 14 12:33:43 PM PDT 24
Finished Mar 14 12:37:03 PM PDT 24
Peak memory 191184 kb
Host smart-b0a85676-1f9d-4898-9b3e-b5b08f099d07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153820716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.4153820716
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3425472080
Short name T426
Test name
Test status
Simulation time 167030124110 ps
CPU time 83.09 seconds
Started Mar 14 12:33:41 PM PDT 24
Finished Mar 14 12:35:06 PM PDT 24
Peak memory 182984 kb
Host smart-50ec2178-7703-4cfb-967a-c934b8d60e68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425472080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3425472080
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.1847518632
Short name T422
Test name
Test status
Simulation time 137903273631 ps
CPU time 208.73 seconds
Started Mar 14 12:33:50 PM PDT 24
Finished Mar 14 12:37:19 PM PDT 24
Peak memory 191140 kb
Host smart-aa83dcc3-ad74-4101-bbab-4552745e615c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847518632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1847518632
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.468902350
Short name T294
Test name
Test status
Simulation time 188478480224 ps
CPU time 157.62 seconds
Started Mar 14 12:33:42 PM PDT 24
Finished Mar 14 12:36:20 PM PDT 24
Peak memory 191092 kb
Host smart-e48679ef-b048-4030-90d1-c41ce284f97a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468902350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.468902350
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.724756501
Short name T189
Test name
Test status
Simulation time 1822032270695 ps
CPU time 2635.71 seconds
Started Mar 14 12:33:46 PM PDT 24
Finished Mar 14 01:17:43 PM PDT 24
Peak memory 191060 kb
Host smart-dde8c3d0-7bd5-45d0-b30d-fead9dd79e3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724756501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.724756501
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3405280825
Short name T63
Test name
Test status
Simulation time 3326256761252 ps
CPU time 981.63 seconds
Started Mar 14 12:33:22 PM PDT 24
Finished Mar 14 12:49:43 PM PDT 24
Peak memory 182984 kb
Host smart-b12e3daf-9dee-410c-a767-5a250ba79875
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405280825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3405280825
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.1147033891
Short name T419
Test name
Test status
Simulation time 81096299400 ps
CPU time 90.33 seconds
Started Mar 14 12:33:20 PM PDT 24
Finished Mar 14 12:34:51 PM PDT 24
Peak memory 182964 kb
Host smart-82a91ee8-d9ea-4869-aa0d-17104c9420e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147033891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.1147033891
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.1159634774
Short name T230
Test name
Test status
Simulation time 446406963978 ps
CPU time 288.61 seconds
Started Mar 14 12:32:55 PM PDT 24
Finished Mar 14 12:37:44 PM PDT 24
Peak memory 191192 kb
Host smart-d116abb1-3993-4653-945f-5497b11e0987
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159634774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1159634774
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.688855522
Short name T435
Test name
Test status
Simulation time 16400786516 ps
CPU time 23.76 seconds
Started Mar 14 12:33:28 PM PDT 24
Finished Mar 14 12:33:52 PM PDT 24
Peak memory 194080 kb
Host smart-21909c13-bab4-4da1-beeb-cd2200d6bc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688855522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.688855522
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.354952397
Short name T205
Test name
Test status
Simulation time 507916371613 ps
CPU time 404.3 seconds
Started Mar 14 12:33:48 PM PDT 24
Finished Mar 14 12:40:32 PM PDT 24
Peak memory 192924 kb
Host smart-50a5ef84-3020-4f2c-abac-ce21dc7e61d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354952397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.354952397
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.2807462192
Short name T226
Test name
Test status
Simulation time 229647878178 ps
CPU time 269.2 seconds
Started Mar 14 12:33:44 PM PDT 24
Finished Mar 14 12:38:14 PM PDT 24
Peak memory 191200 kb
Host smart-d1cc69ad-337c-4e08-99d8-91055da8e23a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807462192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2807462192
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1434566792
Short name T273
Test name
Test status
Simulation time 51637038244 ps
CPU time 85.01 seconds
Started Mar 14 12:33:49 PM PDT 24
Finished Mar 14 12:35:14 PM PDT 24
Peak memory 193820 kb
Host smart-d95d96d1-9b7c-44fe-8225-2be79fcf0507
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434566792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1434566792
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3588288576
Short name T200
Test name
Test status
Simulation time 72441691901 ps
CPU time 117.65 seconds
Started Mar 14 12:34:01 PM PDT 24
Finished Mar 14 12:35:59 PM PDT 24
Peak memory 191168 kb
Host smart-0cfdf4bb-f960-4ae2-9c8c-04fba5108d6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588288576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3588288576
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.419125225
Short name T157
Test name
Test status
Simulation time 272679478239 ps
CPU time 186.88 seconds
Started Mar 14 12:33:44 PM PDT 24
Finished Mar 14 12:36:51 PM PDT 24
Peak memory 191164 kb
Host smart-fe352b6a-a21f-4853-8ad6-7028e716a476
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419125225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.419125225
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.3265500232
Short name T396
Test name
Test status
Simulation time 28641513853 ps
CPU time 52.82 seconds
Started Mar 14 12:33:50 PM PDT 24
Finished Mar 14 12:34:43 PM PDT 24
Peak memory 182988 kb
Host smart-3fde0d35-8dbd-4a3f-b5b3-a564de248b54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265500232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3265500232
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.459348913
Short name T239
Test name
Test status
Simulation time 630938144982 ps
CPU time 397.39 seconds
Started Mar 14 12:33:57 PM PDT 24
Finished Mar 14 12:40:35 PM PDT 24
Peak memory 191148 kb
Host smart-54f55734-87dd-4af3-97eb-8debe248aa4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459348913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.459348913
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3435323557
Short name T325
Test name
Test status
Simulation time 68389894351 ps
CPU time 265.34 seconds
Started Mar 14 12:33:42 PM PDT 24
Finished Mar 14 12:38:08 PM PDT 24
Peak memory 191140 kb
Host smart-09464f7a-8b2a-4992-8e79-d1970aec7287
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435323557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3435323557
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.967640943
Short name T241
Test name
Test status
Simulation time 122826917635 ps
CPU time 200.65 seconds
Started Mar 14 12:33:52 PM PDT 24
Finished Mar 14 12:37:13 PM PDT 24
Peak memory 191160 kb
Host smart-f4ae08c6-424a-4a57-ba37-46603e187c90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967640943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.967640943
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2924154825
Short name T83
Test name
Test status
Simulation time 357322839194 ps
CPU time 335.71 seconds
Started Mar 14 12:33:02 PM PDT 24
Finished Mar 14 12:38:37 PM PDT 24
Peak memory 182976 kb
Host smart-4647b70b-dea1-410b-9e81-517dce55a88f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924154825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2924154825
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.870247423
Short name T410
Test name
Test status
Simulation time 108763345302 ps
CPU time 50.06 seconds
Started Mar 14 12:33:15 PM PDT 24
Finished Mar 14 12:34:06 PM PDT 24
Peak memory 182892 kb
Host smart-ba86cbeb-ad2d-483c-a130-6d410f505847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870247423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.870247423
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.2477031550
Short name T413
Test name
Test status
Simulation time 8513938296 ps
CPU time 15.56 seconds
Started Mar 14 12:33:12 PM PDT 24
Finished Mar 14 12:33:30 PM PDT 24
Peak memory 182760 kb
Host smart-09bb73cf-f504-4fc4-acd4-99290446581c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477031550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2477031550
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1191426490
Short name T447
Test name
Test status
Simulation time 42969820231 ps
CPU time 75.45 seconds
Started Mar 14 12:33:06 PM PDT 24
Finished Mar 14 12:34:22 PM PDT 24
Peak memory 191060 kb
Host smart-f996de8b-1807-44c0-b660-9f05bb7b5d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191426490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1191426490
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.968372686
Short name T35
Test name
Test status
Simulation time 791582684588 ps
CPU time 107.91 seconds
Started Mar 14 12:33:09 PM PDT 24
Finished Mar 14 12:34:58 PM PDT 24
Peak memory 182952 kb
Host smart-d0a50baf-c1d2-4eed-90b3-1f51f6852096
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968372686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.968372686
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/91.rv_timer_random.2105464845
Short name T314
Test name
Test status
Simulation time 78681282362 ps
CPU time 197.1 seconds
Started Mar 14 12:33:46 PM PDT 24
Finished Mar 14 12:37:03 PM PDT 24
Peak memory 191156 kb
Host smart-7f248404-e507-43b9-8a43-96ca6f430dc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105464845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2105464845
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1441153887
Short name T121
Test name
Test status
Simulation time 182740977672 ps
CPU time 128.55 seconds
Started Mar 14 12:33:49 PM PDT 24
Finished Mar 14 12:35:58 PM PDT 24
Peak memory 182872 kb
Host smart-a4539b09-41d3-414e-87a6-23d77bcf65e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441153887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1441153887
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3700584916
Short name T184
Test name
Test status
Simulation time 85802208381 ps
CPU time 107.41 seconds
Started Mar 14 12:33:55 PM PDT 24
Finished Mar 14 12:35:43 PM PDT 24
Peak memory 191184 kb
Host smart-9cf347d8-6a4f-47c9-8bb8-c4c8362b851f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700584916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3700584916
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2926877770
Short name T247
Test name
Test status
Simulation time 43211410654 ps
CPU time 222.84 seconds
Started Mar 14 12:33:44 PM PDT 24
Finished Mar 14 12:37:27 PM PDT 24
Peak memory 191192 kb
Host smart-e12e4936-c73a-4ac2-a89b-a55baeb3eb9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926877770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2926877770
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.1975011912
Short name T180
Test name
Test status
Simulation time 40281439343 ps
CPU time 73.51 seconds
Started Mar 14 12:33:44 PM PDT 24
Finished Mar 14 12:34:58 PM PDT 24
Peak memory 191076 kb
Host smart-a5462e4f-1276-4541-ab48-02ca7936e93f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975011912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1975011912
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.228356306
Short name T64
Test name
Test status
Simulation time 79272464128 ps
CPU time 144.38 seconds
Started Mar 14 12:33:46 PM PDT 24
Finished Mar 14 12:36:11 PM PDT 24
Peak memory 191132 kb
Host smart-3ed4b2f8-171d-416a-8969-f233c63e8f73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228356306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.228356306
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2494627226
Short name T352
Test name
Test status
Simulation time 179267750907 ps
CPU time 156.76 seconds
Started Mar 14 12:33:59 PM PDT 24
Finished Mar 14 12:36:36 PM PDT 24
Peak memory 191188 kb
Host smart-ea72e268-7b63-470d-adbf-c82182bc87e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494627226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2494627226
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.802805488
Short name T190
Test name
Test status
Simulation time 144380904893 ps
CPU time 573.04 seconds
Started Mar 14 12:33:47 PM PDT 24
Finished Mar 14 12:43:20 PM PDT 24
Peak memory 191180 kb
Host smart-2aea086b-67f1-4740-a0b5-b6554692acf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802805488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.802805488
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2111203664
Short name T85
Test name
Test status
Simulation time 22986714408 ps
CPU time 666.09 seconds
Started Mar 14 12:33:41 PM PDT 24
Finished Mar 14 12:44:48 PM PDT 24
Peak memory 191164 kb
Host smart-5cb14f4c-6c04-4b63-aecc-edd6357c13eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111203664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2111203664
Directory /workspace/99.rv_timer_random/latest
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