Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.62 99.36 98.73 100.00 100.00 100.00 99.66


Total test records in report: 581
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T513 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1394465047 Mar 17 01:03:19 PM PDT 24 Mar 17 01:03:21 PM PDT 24 107699690 ps
T98 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.946835051 Mar 17 01:03:02 PM PDT 24 Mar 17 01:03:03 PM PDT 24 168697784 ps
T514 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1941930219 Mar 17 01:03:20 PM PDT 24 Mar 17 01:03:23 PM PDT 24 97182011 ps
T515 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.4069411847 Mar 17 01:03:43 PM PDT 24 Mar 17 01:03:43 PM PDT 24 14383277 ps
T516 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2798090788 Mar 17 01:03:10 PM PDT 24 Mar 17 01:03:11 PM PDT 24 26899332 ps
T517 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3069853678 Mar 17 01:03:16 PM PDT 24 Mar 17 01:03:17 PM PDT 24 15891254 ps
T518 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1722401976 Mar 17 01:03:03 PM PDT 24 Mar 17 01:03:04 PM PDT 24 59608108 ps
T99 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.42040839 Mar 17 01:03:28 PM PDT 24 Mar 17 01:03:30 PM PDT 24 61240296 ps
T85 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3009640313 Mar 17 01:03:34 PM PDT 24 Mar 17 01:03:35 PM PDT 24 29560055 ps
T100 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1742724340 Mar 17 01:03:16 PM PDT 24 Mar 17 01:03:17 PM PDT 24 168528899 ps
T107 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2623600384 Mar 17 01:03:10 PM PDT 24 Mar 17 01:03:12 PM PDT 24 454554016 ps
T86 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1444997595 Mar 17 01:03:16 PM PDT 24 Mar 17 01:03:17 PM PDT 24 64916308 ps
T519 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2979375335 Mar 17 01:03:42 PM PDT 24 Mar 17 01:03:43 PM PDT 24 29248980 ps
T520 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2590878059 Mar 17 01:03:28 PM PDT 24 Mar 17 01:03:31 PM PDT 24 35682686 ps
T521 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2394647578 Mar 17 01:03:38 PM PDT 24 Mar 17 01:03:39 PM PDT 24 129773367 ps
T522 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1367717164 Mar 17 01:03:44 PM PDT 24 Mar 17 01:03:44 PM PDT 24 26817223 ps
T523 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2929823685 Mar 17 01:03:32 PM PDT 24 Mar 17 01:03:32 PM PDT 24 67669024 ps
T524 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.147347600 Mar 17 01:03:25 PM PDT 24 Mar 17 01:03:26 PM PDT 24 159570744 ps
T525 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.734233138 Mar 17 01:03:10 PM PDT 24 Mar 17 01:03:11 PM PDT 24 138007389 ps
T87 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1944611536 Mar 17 01:03:18 PM PDT 24 Mar 17 01:03:21 PM PDT 24 14439953 ps
T88 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1782586657 Mar 17 01:03:04 PM PDT 24 Mar 17 01:03:04 PM PDT 24 54812029 ps
T526 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3438379850 Mar 17 01:03:15 PM PDT 24 Mar 17 01:03:16 PM PDT 24 37136144 ps
T527 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3746026669 Mar 17 01:03:10 PM PDT 24 Mar 17 01:03:11 PM PDT 24 64829396 ps
T528 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.877592559 Mar 17 01:03:01 PM PDT 24 Mar 17 01:03:04 PM PDT 24 89284763 ps
T529 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2236455666 Mar 17 01:03:39 PM PDT 24 Mar 17 01:03:40 PM PDT 24 18815102 ps
T530 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1025785002 Mar 17 01:03:19 PM PDT 24 Mar 17 01:03:21 PM PDT 24 51269367 ps
T531 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.26539514 Mar 17 01:03:42 PM PDT 24 Mar 17 01:03:42 PM PDT 24 16797944 ps
T532 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.983551146 Mar 17 01:03:38 PM PDT 24 Mar 17 01:03:39 PM PDT 24 35364352 ps
T533 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1540637468 Mar 17 01:03:02 PM PDT 24 Mar 17 01:03:03 PM PDT 24 46096369 ps
T534 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2387635640 Mar 17 01:03:23 PM PDT 24 Mar 17 01:03:26 PM PDT 24 46418265 ps
T535 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2218311603 Mar 17 01:03:15 PM PDT 24 Mar 17 01:03:17 PM PDT 24 275651039 ps
T536 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.520900748 Mar 17 01:03:26 PM PDT 24 Mar 17 01:03:27 PM PDT 24 153989363 ps
T537 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3868394996 Mar 17 01:03:02 PM PDT 24 Mar 17 01:03:04 PM PDT 24 75236979 ps
T538 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.522799641 Mar 17 01:03:42 PM PDT 24 Mar 17 01:03:43 PM PDT 24 14785321 ps
T539 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1088348705 Mar 17 01:03:15 PM PDT 24 Mar 17 01:03:16 PM PDT 24 46085899 ps
T540 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1695759293 Mar 17 01:03:10 PM PDT 24 Mar 17 01:03:11 PM PDT 24 16178543 ps
T541 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.734619133 Mar 17 01:03:42 PM PDT 24 Mar 17 01:03:44 PM PDT 24 1028921628 ps
T108 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3284515961 Mar 17 01:03:22 PM PDT 24 Mar 17 01:03:26 PM PDT 24 69369296 ps
T542 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3429049299 Mar 17 01:03:28 PM PDT 24 Mar 17 01:03:30 PM PDT 24 114178683 ps
T543 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2836639385 Mar 17 01:03:31 PM PDT 24 Mar 17 01:03:33 PM PDT 24 51111257 ps
T544 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2029837221 Mar 17 01:03:40 PM PDT 24 Mar 17 01:03:40 PM PDT 24 13010313 ps
T545 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.819087977 Mar 17 01:03:38 PM PDT 24 Mar 17 01:03:39 PM PDT 24 99749548 ps
T89 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1965495397 Mar 17 01:03:09 PM PDT 24 Mar 17 01:03:11 PM PDT 24 17666950 ps
T546 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.4185231733 Mar 17 01:03:16 PM PDT 24 Mar 17 01:03:18 PM PDT 24 30052624 ps
T547 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3642990221 Mar 17 01:03:47 PM PDT 24 Mar 17 01:03:48 PM PDT 24 12263076 ps
T548 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.770850757 Mar 17 01:03:39 PM PDT 24 Mar 17 01:03:40 PM PDT 24 14594489 ps
T549 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3730435358 Mar 17 01:03:15 PM PDT 24 Mar 17 01:03:16 PM PDT 24 55631780 ps
T91 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1897094242 Mar 17 01:03:28 PM PDT 24 Mar 17 01:03:30 PM PDT 24 18507594 ps
T550 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.455077865 Mar 17 01:03:38 PM PDT 24 Mar 17 01:03:38 PM PDT 24 22037308 ps
T551 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2265868839 Mar 17 01:03:12 PM PDT 24 Mar 17 01:03:14 PM PDT 24 25479499 ps
T552 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3103461018 Mar 17 01:03:41 PM PDT 24 Mar 17 01:03:42 PM PDT 24 28273602 ps
T553 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.4122235366 Mar 17 01:03:15 PM PDT 24 Mar 17 01:03:16 PM PDT 24 349264033 ps
T554 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3400466333 Mar 17 01:03:19 PM PDT 24 Mar 17 01:03:21 PM PDT 24 28119596 ps
T555 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.620493961 Mar 17 01:03:34 PM PDT 24 Mar 17 01:03:35 PM PDT 24 24487015 ps
T556 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2659058231 Mar 17 01:03:10 PM PDT 24 Mar 17 01:03:11 PM PDT 24 42730051 ps
T557 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3913487328 Mar 17 01:03:27 PM PDT 24 Mar 17 01:03:28 PM PDT 24 54701986 ps
T558 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3017206148 Mar 17 01:03:25 PM PDT 24 Mar 17 01:03:26 PM PDT 24 279157171 ps
T559 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3476633716 Mar 17 01:03:29 PM PDT 24 Mar 17 01:03:30 PM PDT 24 14116011 ps
T560 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3506041100 Mar 17 01:03:44 PM PDT 24 Mar 17 01:03:45 PM PDT 24 18690532 ps
T90 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1514000252 Mar 17 01:03:10 PM PDT 24 Mar 17 01:03:11 PM PDT 24 48570102 ps
T561 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2177957957 Mar 17 01:03:38 PM PDT 24 Mar 17 01:03:39 PM PDT 24 105486302 ps
T562 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1604554905 Mar 17 01:03:26 PM PDT 24 Mar 17 01:03:27 PM PDT 24 30711246 ps
T563 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1259619078 Mar 17 01:03:17 PM PDT 24 Mar 17 01:03:18 PM PDT 24 61007558 ps
T564 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.919068196 Mar 17 01:03:42 PM PDT 24 Mar 17 01:03:42 PM PDT 24 34351719 ps
T565 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.547568806 Mar 17 01:03:18 PM PDT 24 Mar 17 01:03:21 PM PDT 24 27650780 ps
T566 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2176112229 Mar 17 01:03:15 PM PDT 24 Mar 17 01:03:16 PM PDT 24 14918127 ps
T567 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3557721940 Mar 17 01:03:17 PM PDT 24 Mar 17 01:03:18 PM PDT 24 21691414 ps
T568 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2765440143 Mar 17 01:03:24 PM PDT 24 Mar 17 01:03:25 PM PDT 24 14562091 ps
T569 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.102439645 Mar 17 01:03:28 PM PDT 24 Mar 17 01:03:30 PM PDT 24 80399965 ps
T570 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3117006321 Mar 17 01:03:44 PM PDT 24 Mar 17 01:03:45 PM PDT 24 33398355 ps
T571 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1777536962 Mar 17 01:03:39 PM PDT 24 Mar 17 01:03:40 PM PDT 24 243220267 ps
T572 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2847661494 Mar 17 01:03:12 PM PDT 24 Mar 17 01:03:13 PM PDT 24 364775468 ps
T573 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2312858292 Mar 17 01:03:33 PM PDT 24 Mar 17 01:03:34 PM PDT 24 40025941 ps
T574 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1860625811 Mar 17 01:03:48 PM PDT 24 Mar 17 01:03:49 PM PDT 24 448959354 ps
T575 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3679383366 Mar 17 01:04:04 PM PDT 24 Mar 17 01:04:04 PM PDT 24 84269442 ps
T576 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3696419528 Mar 17 01:03:03 PM PDT 24 Mar 17 01:03:04 PM PDT 24 106842054 ps
T577 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2107713504 Mar 17 01:03:44 PM PDT 24 Mar 17 01:03:45 PM PDT 24 26555184 ps
T578 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2942560865 Mar 17 01:03:22 PM PDT 24 Mar 17 01:03:25 PM PDT 24 36634459 ps
T579 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3859563900 Mar 17 01:03:15 PM PDT 24 Mar 17 01:03:16 PM PDT 24 14359703 ps
T580 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3470651484 Mar 17 01:03:41 PM PDT 24 Mar 17 01:03:42 PM PDT 24 48615369 ps
T581 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1712718533 Mar 17 01:03:38 PM PDT 24 Mar 17 01:03:39 PM PDT 24 154701796 ps

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.371043005
Short name T1
Test name
Test status
Simulation time 128242139824 ps
CPU time 860.67 seconds
Started Mar 17 12:29:56 PM PDT 24
Finished Mar 17 12:44:17 PM PDT 24
Peak memory 213472 kb
Host smart-0109a51a-ce4e-4b94-ba6d-50e48b055f1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371043005 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.371043005
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.2854331179
Short name T12
Test name
Test status
Simulation time 729495968456 ps
CPU time 1128.31 seconds
Started Mar 17 12:31:34 PM PDT 24
Finished Mar 17 12:50:23 PM PDT 24
Peak memory 192768 kb
Host smart-55c5ea7e-b733-40bf-9d26-02033627d892
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854331179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.2854331179
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.952594080
Short name T62
Test name
Test status
Simulation time 9747749244950 ps
CPU time 2457.59 seconds
Started Mar 17 12:29:55 PM PDT 24
Finished Mar 17 01:10:53 PM PDT 24
Peak memory 190760 kb
Host smart-0d547a78-851a-4dad-984d-726bd85007c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952594080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
952594080
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3641209097
Short name T30
Test name
Test status
Simulation time 185788696 ps
CPU time 1.36 seconds
Started Mar 17 01:03:10 PM PDT 24
Finished Mar 17 01:03:12 PM PDT 24
Peak memory 194976 kb
Host smart-7459dffa-b2eb-43b6-8681-efbd1dc9f19a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641209097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3641209097
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.424416290
Short name T11
Test name
Test status
Simulation time 403816123296 ps
CPU time 2904.51 seconds
Started Mar 17 12:29:48 PM PDT 24
Finished Mar 17 01:18:13 PM PDT 24
Peak memory 190740 kb
Host smart-15f414e2-947a-4214-87a0-5ebd4023da49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424416290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
424416290
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.1634687380
Short name T186
Test name
Test status
Simulation time 781351240212 ps
CPU time 5805.48 seconds
Started Mar 17 12:28:05 PM PDT 24
Finished Mar 17 02:04:51 PM PDT 24
Peak memory 190416 kb
Host smart-f9f29583-e9d8-4378-a5bc-93585b75dd4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634687380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
1634687380
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/197.rv_timer_random.3582261854
Short name T13
Test name
Test status
Simulation time 616686296002 ps
CPU time 689.11 seconds
Started Mar 17 12:32:40 PM PDT 24
Finished Mar 17 12:44:09 PM PDT 24
Peak memory 190732 kb
Host smart-fc392e0e-82fe-45a1-a565-78711f8ba037
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582261854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3582261854
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.1025181466
Short name T218
Test name
Test status
Simulation time 685895128266 ps
CPU time 1890.64 seconds
Started Mar 17 12:29:23 PM PDT 24
Finished Mar 17 01:00:54 PM PDT 24
Peak memory 195284 kb
Host smart-ebaa12f8-4273-4858-b314-b406e91afc67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025181466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.1025181466
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.57261412
Short name T44
Test name
Test status
Simulation time 44924352 ps
CPU time 0.55 seconds
Started Mar 17 01:03:38 PM PDT 24
Finished Mar 17 01:03:39 PM PDT 24
Peak memory 182668 kb
Host smart-b213cd0c-2ca0-46d5-b58d-48d96265b48a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57261412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.57261412
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2944976028
Short name T153
Test name
Test status
Simulation time 668660409680 ps
CPU time 852.93 seconds
Started Mar 17 12:29:35 PM PDT 24
Finished Mar 17 12:43:48 PM PDT 24
Peak memory 195392 kb
Host smart-70fa6e6c-b3cd-4144-8e5c-8441e4e0144d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944976028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2944976028
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.525438510
Short name T124
Test name
Test status
Simulation time 6553751195547 ps
CPU time 2782.28 seconds
Started Mar 17 12:29:39 PM PDT 24
Finished Mar 17 01:16:02 PM PDT 24
Peak memory 190744 kb
Host smart-c554f36f-f297-4d37-907e-323398b5fd9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525438510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.
525438510
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.651705596
Short name T216
Test name
Test status
Simulation time 433600925194 ps
CPU time 739.16 seconds
Started Mar 17 12:24:20 PM PDT 24
Finished Mar 17 12:36:40 PM PDT 24
Peak memory 190772 kb
Host smart-cc5827ec-3666-4e38-8181-919cf0965119
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651705596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.651705596
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2789182172
Short name T58
Test name
Test status
Simulation time 1380998518980 ps
CPU time 977.78 seconds
Started Mar 17 12:29:09 PM PDT 24
Finished Mar 17 12:45:27 PM PDT 24
Peak memory 190716 kb
Host smart-783fb7e3-8db1-489f-a2c0-944bca273ffd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789182172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2789182172
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1952647317
Short name T154
Test name
Test status
Simulation time 1007298586490 ps
CPU time 1208.97 seconds
Started Mar 17 12:26:08 PM PDT 24
Finished Mar 17 12:46:18 PM PDT 24
Peak memory 195164 kb
Host smart-71a71042-d274-4a74-af66-3e49761e99ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952647317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1952647317
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.318081158
Short name T16
Test name
Test status
Simulation time 62084004 ps
CPU time 0.84 seconds
Started Mar 17 12:23:37 PM PDT 24
Finished Mar 17 12:23:38 PM PDT 24
Peak memory 213584 kb
Host smart-ecd51e90-7f7c-4afd-b54d-6727511e2e76
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318081158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.318081158
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.51151923
Short name T172
Test name
Test status
Simulation time 1101380740154 ps
CPU time 1279.31 seconds
Started Mar 17 12:29:53 PM PDT 24
Finished Mar 17 12:51:13 PM PDT 24
Peak memory 195748 kb
Host smart-fe14488d-ce7a-458d-9b49-4e547a9dc9fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51151923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.51151923
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.1769996495
Short name T57
Test name
Test status
Simulation time 844581698567 ps
CPU time 1379.6 seconds
Started Mar 17 12:29:14 PM PDT 24
Finished Mar 17 12:52:14 PM PDT 24
Peak memory 195308 kb
Host smart-5a1a1f8b-b20f-41ac-b9c2-452232b19dec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769996495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.1769996495
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.3545345658
Short name T446
Test name
Test status
Simulation time 380564449372 ps
CPU time 1718.86 seconds
Started Mar 17 12:31:34 PM PDT 24
Finished Mar 17 01:00:13 PM PDT 24
Peak memory 188468 kb
Host smart-ef4b4f27-8db2-4cc9-a8e6-abf64eddfdfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545345658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.3545345658
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/152.rv_timer_random.4064384606
Short name T177
Test name
Test status
Simulation time 171629409709 ps
CPU time 280.71 seconds
Started Mar 17 12:31:56 PM PDT 24
Finished Mar 17 12:36:37 PM PDT 24
Peak memory 190684 kb
Host smart-73c3b334-764a-448b-8af1-876705d41447
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064384606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.4064384606
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.701440222
Short name T302
Test name
Test status
Simulation time 333517657281 ps
CPU time 898.52 seconds
Started Mar 17 12:31:02 PM PDT 24
Finished Mar 17 12:46:00 PM PDT 24
Peak memory 190836 kb
Host smart-fcb6e3bc-d2f6-401f-9687-434ca6d16ad1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701440222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
701440222
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/172.rv_timer_random.3913069705
Short name T129
Test name
Test status
Simulation time 105431840853 ps
CPU time 318.54 seconds
Started Mar 17 12:32:19 PM PDT 24
Finished Mar 17 12:37:39 PM PDT 24
Peak memory 190736 kb
Host smart-ca5e7272-f34b-4add-b7e4-59e995555972
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913069705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3913069705
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/130.rv_timer_random.1269243135
Short name T274
Test name
Test status
Simulation time 786016321198 ps
CPU time 411.36 seconds
Started Mar 17 12:31:56 PM PDT 24
Finished Mar 17 12:38:47 PM PDT 24
Peak memory 190656 kb
Host smart-3a3d1daf-03d4-4b3b-b1df-7572d4879761
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269243135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1269243135
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.2662921219
Short name T50
Test name
Test status
Simulation time 719295031661 ps
CPU time 2610.3 seconds
Started Mar 17 12:31:52 PM PDT 24
Finished Mar 17 01:15:23 PM PDT 24
Peak memory 190780 kb
Host smart-d11d05d4-a78c-4860-bf38-135849815c3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662921219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2662921219
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.4208629083
Short name T9
Test name
Test status
Simulation time 91362797910 ps
CPU time 275.58 seconds
Started Mar 17 12:31:54 PM PDT 24
Finished Mar 17 12:36:29 PM PDT 24
Peak memory 190768 kb
Host smart-58ec90bb-1973-453a-b672-abcffa14a819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208629083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.4208629083
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.2104102264
Short name T205
Test name
Test status
Simulation time 482745170608 ps
CPU time 968.61 seconds
Started Mar 17 12:31:50 PM PDT 24
Finished Mar 17 12:47:59 PM PDT 24
Peak memory 190780 kb
Host smart-dfb879e3-7cf7-4dda-a806-7fdc4c6b6bc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104102264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2104102264
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.1870862570
Short name T248
Test name
Test status
Simulation time 287661291223 ps
CPU time 2100.09 seconds
Started Mar 17 12:32:33 PM PDT 24
Finished Mar 17 01:07:34 PM PDT 24
Peak memory 190696 kb
Host smart-710ac385-9e78-494f-967a-d0a0c0b5178e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870862570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1870862570
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.2953774855
Short name T187
Test name
Test status
Simulation time 1435428180898 ps
CPU time 1676.91 seconds
Started Mar 17 12:30:52 PM PDT 24
Finished Mar 17 12:58:49 PM PDT 24
Peak memory 191136 kb
Host smart-bd5e543d-4541-49ba-96a8-f9638a7cc874
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953774855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.2953774855
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/71.rv_timer_random.3996687786
Short name T251
Test name
Test status
Simulation time 130735724216 ps
CPU time 369.95 seconds
Started Mar 17 12:31:14 PM PDT 24
Finished Mar 17 12:37:24 PM PDT 24
Peak memory 190796 kb
Host smart-2b4a8743-7ebb-4306-ba8d-a85478fee688
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996687786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3996687786
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.1317318035
Short name T160
Test name
Test status
Simulation time 1847875206496 ps
CPU time 1265.18 seconds
Started Mar 17 12:31:45 PM PDT 24
Finished Mar 17 12:52:51 PM PDT 24
Peak memory 190764 kb
Host smart-30c6cb35-1b31-4fe6-a483-16a42804c37c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317318035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1317318035
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.4235030820
Short name T286
Test name
Test status
Simulation time 695792251017 ps
CPU time 352.4 seconds
Started Mar 17 12:31:44 PM PDT 24
Finished Mar 17 12:37:36 PM PDT 24
Peak memory 190808 kb
Host smart-205f2652-56e6-4de3-9da7-0085c96b48dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235030820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.4235030820
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.2810989019
Short name T240
Test name
Test status
Simulation time 348156674355 ps
CPU time 200.68 seconds
Started Mar 17 12:32:00 PM PDT 24
Finished Mar 17 12:35:20 PM PDT 24
Peak memory 190740 kb
Host smart-6ae1543b-850c-4af6-a563-dee388dfaa20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810989019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2810989019
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.3171720190
Short name T358
Test name
Test status
Simulation time 134644772414 ps
CPU time 574.73 seconds
Started Mar 17 12:32:06 PM PDT 24
Finished Mar 17 12:41:41 PM PDT 24
Peak memory 190748 kb
Host smart-317cf3c5-ec28-497e-be1f-275f723eac87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171720190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3171720190
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1965495397
Short name T89
Test name
Test status
Simulation time 17666950 ps
CPU time 0.79 seconds
Started Mar 17 01:03:09 PM PDT 24
Finished Mar 17 01:03:11 PM PDT 24
Peak memory 192568 kb
Host smart-7b08312d-7504-429b-9300-13d669ce41de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965495397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1965495397
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/118.rv_timer_random.49630176
Short name T260
Test name
Test status
Simulation time 128897696138 ps
CPU time 229.86 seconds
Started Mar 17 12:31:45 PM PDT 24
Finished Mar 17 12:35:35 PM PDT 24
Peak memory 190764 kb
Host smart-866213aa-b9ba-4286-8d70-ea5e1083e7fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49630176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.49630176
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2508179828
Short name T140
Test name
Test status
Simulation time 426652647564 ps
CPU time 370.73 seconds
Started Mar 17 12:29:30 PM PDT 24
Finished Mar 17 12:35:42 PM PDT 24
Peak memory 182612 kb
Host smart-e2e23600-08fe-41f3-8a03-bd317def838e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508179828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2508179828
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3225112208
Short name T63
Test name
Test status
Simulation time 352342295669 ps
CPU time 479.04 seconds
Started Mar 17 12:29:30 PM PDT 24
Finished Mar 17 12:37:30 PM PDT 24
Peak memory 190772 kb
Host smart-0ecd7807-ac37-4011-be48-d2bd9a7c90e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225112208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3225112208
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/174.rv_timer_random.477912067
Short name T64
Test name
Test status
Simulation time 68797662018 ps
CPU time 298.02 seconds
Started Mar 17 12:32:20 PM PDT 24
Finished Mar 17 12:37:18 PM PDT 24
Peak memory 190728 kb
Host smart-968a9ebf-15c8-4460-bfd4-97a8a1a95355
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477912067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.477912067
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random.3593005712
Short name T212
Test name
Test status
Simulation time 154871459816 ps
CPU time 149.37 seconds
Started Mar 17 12:30:17 PM PDT 24
Finished Mar 17 12:32:47 PM PDT 24
Peak memory 190772 kb
Host smart-55d976e8-c814-486c-93cd-424ed16adff0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593005712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3593005712
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random.1313950036
Short name T173
Test name
Test status
Simulation time 407296050468 ps
CPU time 851 seconds
Started Mar 17 12:29:11 PM PDT 24
Finished Mar 17 12:43:22 PM PDT 24
Peak memory 190784 kb
Host smart-2f9dd918-6949-4ae9-b95b-e626f5da3ad2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313950036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1313950036
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random.1227040654
Short name T75
Test name
Test status
Simulation time 478511414033 ps
CPU time 226.56 seconds
Started Mar 17 12:29:41 PM PDT 24
Finished Mar 17 12:33:28 PM PDT 24
Peak memory 190740 kb
Host smart-34557176-56d5-4e7f-9f9e-9c16d53303bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227040654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1227040654
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random.3145226749
Short name T29
Test name
Test status
Simulation time 422608167871 ps
CPU time 1067.53 seconds
Started Mar 17 12:29:53 PM PDT 24
Finished Mar 17 12:47:40 PM PDT 24
Peak memory 190736 kb
Host smart-d80bd468-80b4-4be6-b18e-dbf168b5b069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145226749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3145226749
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random.3358359779
Short name T250
Test name
Test status
Simulation time 111703164709 ps
CPU time 794.21 seconds
Started Mar 17 12:25:59 PM PDT 24
Finished Mar 17 12:39:14 PM PDT 24
Peak memory 193056 kb
Host smart-f41e0e9d-9712-4273-b453-f3af009422da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358359779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3358359779
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1711096524
Short name T246
Test name
Test status
Simulation time 335755449124 ps
CPU time 389.97 seconds
Started Mar 17 12:31:06 PM PDT 24
Finished Mar 17 12:37:36 PM PDT 24
Peak memory 190752 kb
Host smart-e02c27df-2808-48ff-b34c-a924c03dc6cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711096524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1711096524
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random.2414965913
Short name T233
Test name
Test status
Simulation time 87620914043 ps
CPU time 62.39 seconds
Started Mar 17 12:29:12 PM PDT 24
Finished Mar 17 12:30:15 PM PDT 24
Peak memory 190740 kb
Host smart-6c08f427-1aee-44c6-b5f8-c660d81e2643
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414965913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2414965913
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3003393978
Short name T310
Test name
Test status
Simulation time 933777518651 ps
CPU time 443.49 seconds
Started Mar 17 12:31:28 PM PDT 24
Finished Mar 17 12:38:53 PM PDT 24
Peak memory 190824 kb
Host smart-d39c3abe-23a5-4b93-bf26-be66828ff85a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003393978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3003393978
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.520298947
Short name T209
Test name
Test status
Simulation time 452241831437 ps
CPU time 392.69 seconds
Started Mar 17 12:29:07 PM PDT 24
Finished Mar 17 12:35:40 PM PDT 24
Peak memory 182556 kb
Host smart-874a46e2-1907-48bb-a7b0-32c5f370e62b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520298947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.520298947
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/113.rv_timer_random.1277812945
Short name T180
Test name
Test status
Simulation time 424652501669 ps
CPU time 567.59 seconds
Started Mar 17 12:31:43 PM PDT 24
Finished Mar 17 12:41:11 PM PDT 24
Peak memory 190724 kb
Host smart-9610b9c2-e2ac-4555-a4ca-08ee50f7c745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277812945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1277812945
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.1637560734
Short name T206
Test name
Test status
Simulation time 100502761991 ps
CPU time 118.84 seconds
Started Mar 17 12:31:51 PM PDT 24
Finished Mar 17 12:33:50 PM PDT 24
Peak memory 190680 kb
Host smart-a3ff03f1-178d-491e-9d2d-79183251bc70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637560734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1637560734
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.840303165
Short name T114
Test name
Test status
Simulation time 186951062431 ps
CPU time 443.03 seconds
Started Mar 17 12:31:53 PM PDT 24
Finished Mar 17 12:39:16 PM PDT 24
Peak memory 190740 kb
Host smart-76727c5a-79bb-43c1-b795-97cd41141047
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840303165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.840303165
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.969933166
Short name T80
Test name
Test status
Simulation time 346971025027 ps
CPU time 647.1 seconds
Started Mar 17 12:32:12 PM PDT 24
Finished Mar 17 12:43:00 PM PDT 24
Peak memory 190740 kb
Host smart-bd1a8c01-6eb6-4bc0-b2ff-31fccbe34fbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969933166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.969933166
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.315543061
Short name T315
Test name
Test status
Simulation time 7260986772 ps
CPU time 13.05 seconds
Started Mar 17 12:32:13 PM PDT 24
Finished Mar 17 12:32:26 PM PDT 24
Peak memory 194388 kb
Host smart-45472af5-e191-4500-9726-ae15f31009af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315543061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.315543061
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1179830494
Short name T197
Test name
Test status
Simulation time 149978017191 ps
CPU time 1081.16 seconds
Started Mar 17 12:32:27 PM PDT 24
Finished Mar 17 12:50:28 PM PDT 24
Peak memory 190760 kb
Host smart-3306d1a9-7739-46a4-aa48-e45c84f9d2ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179830494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1179830494
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.2132500022
Short name T247
Test name
Test status
Simulation time 905910916151 ps
CPU time 1282.04 seconds
Started Mar 17 12:32:34 PM PDT 24
Finished Mar 17 12:53:56 PM PDT 24
Peak memory 190840 kb
Host smart-6a037eea-3f27-4ef4-9864-b8aa01aa8faf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132500022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2132500022
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random.3550276268
Short name T202
Test name
Test status
Simulation time 116958726884 ps
CPU time 1097.94 seconds
Started Mar 17 12:29:35 PM PDT 24
Finished Mar 17 12:47:53 PM PDT 24
Peak memory 193380 kb
Host smart-2e82dd00-f8d2-4abc-8f8f-4ccf1a0cffac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550276268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3550276268
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random.4140315153
Short name T312
Test name
Test status
Simulation time 226769360774 ps
CPU time 214.98 seconds
Started Mar 17 12:29:54 PM PDT 24
Finished Mar 17 12:33:30 PM PDT 24
Peak memory 190724 kb
Host smart-e1efce3d-db93-45a7-a054-b3341d0eaa88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140315153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.4140315153
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.3284457588
Short name T175
Test name
Test status
Simulation time 144385960290 ps
CPU time 77.41 seconds
Started Mar 17 12:29:50 PM PDT 24
Finished Mar 17 12:31:08 PM PDT 24
Peak memory 190676 kb
Host smart-083eabb6-da95-4179-9c84-697db416a0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284457588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.3284457588
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/73.rv_timer_random.3881938314
Short name T26
Test name
Test status
Simulation time 425261131681 ps
CPU time 446.92 seconds
Started Mar 17 12:31:14 PM PDT 24
Finished Mar 17 12:38:41 PM PDT 24
Peak memory 190692 kb
Host smart-e1bb9359-2aed-471b-aee4-f71368ffcd0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881938314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3881938314
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2264830239
Short name T321
Test name
Test status
Simulation time 57939138275 ps
CPU time 410.22 seconds
Started Mar 17 12:31:23 PM PDT 24
Finished Mar 17 12:38:14 PM PDT 24
Peak memory 190724 kb
Host smart-fd9122f1-fdde-46fa-86a5-5074dd88cf69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264830239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2264830239
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.946835051
Short name T98
Test name
Test status
Simulation time 168697784 ps
CPU time 0.71 seconds
Started Mar 17 01:03:02 PM PDT 24
Finished Mar 17 01:03:03 PM PDT 24
Peak memory 193140 kb
Host smart-550251ff-ab8e-451e-9872-f8b8caf97f1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946835051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.946835051
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1777536962
Short name T571
Test name
Test status
Simulation time 243220267 ps
CPU time 1.03 seconds
Started Mar 17 01:03:39 PM PDT 24
Finished Mar 17 01:03:40 PM PDT 24
Peak memory 195272 kb
Host smart-059f3503-7502-44bf-ab65-5163f0b740cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777536962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.1777536962
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_random.2301321570
Short name T193
Test name
Test status
Simulation time 80564099781 ps
CPU time 786.7 seconds
Started Mar 17 12:24:20 PM PDT 24
Finished Mar 17 12:37:28 PM PDT 24
Peak memory 190728 kb
Host smart-62857993-445e-429b-bfda-e3a44d6d0fe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301321570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2301321570
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random.2282186090
Short name T136
Test name
Test status
Simulation time 78527035699 ps
CPU time 134.56 seconds
Started Mar 17 12:23:55 PM PDT 24
Finished Mar 17 12:26:10 PM PDT 24
Peak memory 191152 kb
Host smart-c8d3a223-3665-442e-8aee-67c537e874ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282186090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2282186090
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.68787422
Short name T221
Test name
Test status
Simulation time 116595531219 ps
CPU time 148.3 seconds
Started Mar 17 12:29:45 PM PDT 24
Finished Mar 17 12:32:14 PM PDT 24
Peak memory 195012 kb
Host smart-c281a4e2-fe6c-46af-9c2a-4680da9f545d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68787422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.68787422
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/124.rv_timer_random.255968387
Short name T243
Test name
Test status
Simulation time 685078456133 ps
CPU time 401.07 seconds
Started Mar 17 12:31:51 PM PDT 24
Finished Mar 17 12:38:32 PM PDT 24
Peak memory 190748 kb
Host smart-fada6382-e3d8-4b05-936f-d15e10f8dc3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255968387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.255968387
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.4081258574
Short name T271
Test name
Test status
Simulation time 208927675505 ps
CPU time 640.54 seconds
Started Mar 17 12:31:51 PM PDT 24
Finished Mar 17 12:42:31 PM PDT 24
Peak memory 190824 kb
Host smart-6ded6136-de9a-4b28-a2bf-8804e8dffdba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081258574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.4081258574
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3960915418
Short name T200
Test name
Test status
Simulation time 267010584164 ps
CPU time 447.87 seconds
Started Mar 17 12:29:16 PM PDT 24
Finished Mar 17 12:36:44 PM PDT 24
Peak memory 182512 kb
Host smart-7a62a881-77cf-4540-a534-b29b3a0dcb9b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960915418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3960915418
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/154.rv_timer_random.2908559728
Short name T71
Test name
Test status
Simulation time 743079514468 ps
CPU time 351.62 seconds
Started Mar 17 12:32:04 PM PDT 24
Finished Mar 17 12:37:56 PM PDT 24
Peak memory 190756 kb
Host smart-b00f0813-628c-4972-874b-f9cfde89d2d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908559728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2908559728
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.1029450523
Short name T297
Test name
Test status
Simulation time 92954355382 ps
CPU time 1479.67 seconds
Started Mar 17 12:32:13 PM PDT 24
Finished Mar 17 12:56:53 PM PDT 24
Peak memory 190728 kb
Host smart-3086de00-0ba1-41e4-9974-106125b89871
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029450523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1029450523
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.1621347160
Short name T228
Test name
Test status
Simulation time 169439661839 ps
CPU time 91.49 seconds
Started Mar 17 12:32:18 PM PDT 24
Finished Mar 17 12:33:51 PM PDT 24
Peak memory 182540 kb
Host smart-05301468-2df9-4488-81c4-8cfafbca30e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621347160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1621347160
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random.3313861719
Short name T165
Test name
Test status
Simulation time 214350339203 ps
CPU time 132.92 seconds
Started Mar 17 12:29:40 PM PDT 24
Finished Mar 17 12:31:53 PM PDT 24
Peak memory 190704 kb
Host smart-2ade7697-70b7-4174-828b-c34d5910f429
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313861719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3313861719
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random.2145185324
Short name T10
Test name
Test status
Simulation time 453993943741 ps
CPU time 1090.32 seconds
Started Mar 17 12:30:15 PM PDT 24
Finished Mar 17 12:48:25 PM PDT 24
Peak memory 190740 kb
Host smart-025af713-8b96-4fbd-8466-9ebe6e51b092
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145185324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2145185324
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3916155756
Short name T242
Test name
Test status
Simulation time 132157817852 ps
CPU time 113.03 seconds
Started Mar 17 12:30:10 PM PDT 24
Finished Mar 17 12:32:04 PM PDT 24
Peak memory 190724 kb
Host smart-87cd5f7c-98c1-4f17-9a47-e0d3b9b0f086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916155756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3916155756
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.4096681049
Short name T361
Test name
Test status
Simulation time 101531719508 ps
CPU time 154.11 seconds
Started Mar 17 12:29:55 PM PDT 24
Finished Mar 17 12:32:30 PM PDT 24
Peak memory 194928 kb
Host smart-3dae2c00-4fab-4442-abcc-7ecf5ec6d0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096681049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.4096681049
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.188594340
Short name T162
Test name
Test status
Simulation time 339321647786 ps
CPU time 629.24 seconds
Started Mar 17 12:30:32 PM PDT 24
Finished Mar 17 12:41:01 PM PDT 24
Peak memory 195184 kb
Host smart-95fa25c3-ec92-4dea-a871-26fdbc0a2ac4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188594340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
188594340
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_random.3697290868
Short name T188
Test name
Test status
Simulation time 101061197523 ps
CPU time 212.05 seconds
Started Mar 17 12:30:31 PM PDT 24
Finished Mar 17 12:34:03 PM PDT 24
Peak memory 190760 kb
Host smart-3aa449fc-a123-4105-9ae6-3a129123e854
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697290868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3697290868
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.3485635285
Short name T78
Test name
Test status
Simulation time 1703502565281 ps
CPU time 1879.98 seconds
Started Mar 17 12:31:27 PM PDT 24
Finished Mar 17 01:02:48 PM PDT 24
Peak memory 190676 kb
Host smart-1bd5ddf0-f107-457d-97d9-0e157c7c40b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485635285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3485635285
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.3777172103
Short name T168
Test name
Test status
Simulation time 249941118429 ps
CPU time 475.48 seconds
Started Mar 17 12:31:22 PM PDT 24
Finished Mar 17 12:39:18 PM PDT 24
Peak memory 190736 kb
Host smart-172a9b05-de96-43a2-9a1d-c566e338da3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777172103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3777172103
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.2985661632
Short name T232
Test name
Test status
Simulation time 102310145263 ps
CPU time 171.03 seconds
Started Mar 17 12:28:00 PM PDT 24
Finished Mar 17 12:30:52 PM PDT 24
Peak memory 190412 kb
Host smart-65a3ef84-a221-4afb-acc1-bef2b20b692e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985661632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2985661632
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1399849249
Short name T353
Test name
Test status
Simulation time 194875875996 ps
CPU time 80.44 seconds
Started Mar 17 12:29:10 PM PDT 24
Finished Mar 17 12:30:30 PM PDT 24
Peak memory 193252 kb
Host smart-9637a334-94d7-472a-9630-0324a7dbaa68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399849249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1399849249
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.3925666313
Short name T278
Test name
Test status
Simulation time 160632844507 ps
CPU time 245.25 seconds
Started Mar 17 12:31:29 PM PDT 24
Finished Mar 17 12:35:35 PM PDT 24
Peak memory 190768 kb
Host smart-5c4e7db6-4b16-42f7-a30b-4abfd32f0c7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925666313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3925666313
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.4240654413
Short name T329
Test name
Test status
Simulation time 102962357525 ps
CPU time 187.33 seconds
Started Mar 17 12:31:28 PM PDT 24
Finished Mar 17 12:34:37 PM PDT 24
Peak memory 191792 kb
Host smart-499d0a86-f5a1-452b-8c4f-ef12defd8ff6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240654413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.4240654413
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.3237717312
Short name T355
Test name
Test status
Simulation time 68432207425 ps
CPU time 308.33 seconds
Started Mar 17 12:31:37 PM PDT 24
Finished Mar 17 12:36:45 PM PDT 24
Peak memory 182468 kb
Host smart-f839f4a0-6cad-48a7-aed6-e891c55b51e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237717312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3237717312
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.227195676
Short name T346
Test name
Test status
Simulation time 52678762523 ps
CPU time 158.8 seconds
Started Mar 17 12:31:38 PM PDT 24
Finished Mar 17 12:34:17 PM PDT 24
Peak memory 190708 kb
Host smart-6fbd4cba-cbf4-4c25-a105-7e74cd4d94c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227195676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.227195676
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1145514601
Short name T295
Test name
Test status
Simulation time 9728087877 ps
CPU time 16.68 seconds
Started Mar 17 12:29:20 PM PDT 24
Finished Mar 17 12:29:37 PM PDT 24
Peak memory 182484 kb
Host smart-4ddc117e-e51d-4b2d-a69b-c85437bc804f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145514601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1145514601
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/127.rv_timer_random.3689543517
Short name T298
Test name
Test status
Simulation time 554724655017 ps
CPU time 261.07 seconds
Started Mar 17 12:31:53 PM PDT 24
Finished Mar 17 12:36:14 PM PDT 24
Peak memory 190708 kb
Host smart-462fc6ad-edeb-48c8-ab94-785225621bf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689543517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3689543517
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1100327512
Short name T214
Test name
Test status
Simulation time 231605008431 ps
CPU time 376.77 seconds
Started Mar 17 12:29:24 PM PDT 24
Finished Mar 17 12:35:41 PM PDT 24
Peak memory 182644 kb
Host smart-bc7fef2c-6ccd-4918-8bd3-e866ca436a48
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100327512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1100327512
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.2879158543
Short name T325
Test name
Test status
Simulation time 114172976151 ps
CPU time 94.48 seconds
Started Mar 17 12:29:15 PM PDT 24
Finished Mar 17 12:30:50 PM PDT 24
Peak memory 182552 kb
Host smart-416c27b3-512a-46d5-a7e3-4d78f5eec081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879158543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2879158543
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/143.rv_timer_random.3684348798
Short name T227
Test name
Test status
Simulation time 140467364937 ps
CPU time 2116.61 seconds
Started Mar 17 12:31:51 PM PDT 24
Finished Mar 17 01:07:08 PM PDT 24
Peak memory 190808 kb
Host smart-9b7d7a26-986e-471f-a515-6d6b831ee549
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684348798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3684348798
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3764994940
Short name T157
Test name
Test status
Simulation time 180360227406 ps
CPU time 409.37 seconds
Started Mar 17 12:31:05 PM PDT 24
Finished Mar 17 12:37:55 PM PDT 24
Peak memory 180792 kb
Host smart-8ca58456-3281-420f-a8c2-5a36f2fb559e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764994940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3764994940
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/153.rv_timer_random.879201245
Short name T259
Test name
Test status
Simulation time 78218761839 ps
CPU time 124.36 seconds
Started Mar 17 12:32:05 PM PDT 24
Finished Mar 17 12:34:09 PM PDT 24
Peak memory 190692 kb
Host smart-cf35ec97-83fd-42ba-a7d6-88f377b1772f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879201245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.879201245
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.768589216
Short name T328
Test name
Test status
Simulation time 63059800496 ps
CPU time 110.26 seconds
Started Mar 17 12:32:24 PM PDT 24
Finished Mar 17 12:34:16 PM PDT 24
Peak memory 190828 kb
Host smart-623175cb-c8c7-4814-95e7-3f39c38b67da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768589216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.768589216
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.3568028866
Short name T181
Test name
Test status
Simulation time 40703058243 ps
CPU time 202.11 seconds
Started Mar 17 12:32:26 PM PDT 24
Finished Mar 17 12:35:49 PM PDT 24
Peak memory 190740 kb
Host smart-f4e177a8-bf78-47e1-9811-07b4d44cdd91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568028866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3568028866
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.3818953569
Short name T102
Test name
Test status
Simulation time 255558855364 ps
CPU time 702.19 seconds
Started Mar 17 12:32:25 PM PDT 24
Finished Mar 17 12:44:08 PM PDT 24
Peak memory 190752 kb
Host smart-ac57fe37-b2a1-41fa-9ff4-e637cce6907c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818953569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3818953569
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.818844158
Short name T322
Test name
Test status
Simulation time 48389409870 ps
CPU time 99.94 seconds
Started Mar 17 12:29:34 PM PDT 24
Finished Mar 17 12:31:14 PM PDT 24
Peak memory 182536 kb
Host smart-c1594c46-2367-46bb-8968-a2dcde828997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818844158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.818844158
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/194.rv_timer_random.3065439540
Short name T264
Test name
Test status
Simulation time 125236011908 ps
CPU time 818.24 seconds
Started Mar 17 12:32:33 PM PDT 24
Finished Mar 17 12:46:11 PM PDT 24
Peak memory 194616 kb
Host smart-c77507e3-cb41-49e7-8045-26c739c60647
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065439540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3065439540
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.2961025391
Short name T333
Test name
Test status
Simulation time 577307141146 ps
CPU time 371.13 seconds
Started Mar 17 12:32:33 PM PDT 24
Finished Mar 17 12:38:44 PM PDT 24
Peak memory 190804 kb
Host smart-80c5f9fb-7259-4a2e-adaa-e03d615e64e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961025391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2961025391
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2374093219
Short name T77
Test name
Test status
Simulation time 24089749119 ps
CPU time 7.95 seconds
Started Mar 17 12:29:31 PM PDT 24
Finished Mar 17 12:29:39 PM PDT 24
Peak memory 182580 kb
Host smart-88a7eaf6-c16f-438b-ba14-07b68fe1ffa4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374093219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2374093219
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1214797320
Short name T226
Test name
Test status
Simulation time 1483303584358 ps
CPU time 1093.45 seconds
Started Mar 17 12:29:48 PM PDT 24
Finished Mar 17 12:48:02 PM PDT 24
Peak memory 193180 kb
Host smart-5d25e6b2-308a-4662-9493-09dfcaf9a7cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214797320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1214797320
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1955795321
Short name T267
Test name
Test status
Simulation time 110972985133 ps
CPU time 188.17 seconds
Started Mar 17 12:29:42 PM PDT 24
Finished Mar 17 12:32:50 PM PDT 24
Peak memory 182512 kb
Host smart-e6a9147a-d17c-4388-903a-3df785460afb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955795321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1955795321
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2638076339
Short name T335
Test name
Test status
Simulation time 239300932105 ps
CPU time 429.28 seconds
Started Mar 17 12:29:49 PM PDT 24
Finished Mar 17 12:36:59 PM PDT 24
Peak memory 182592 kb
Host smart-b94bc0e6-b60b-4f8e-bd24-ed4b4e398f65
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638076339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2638076339
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.4241561078
Short name T119
Test name
Test status
Simulation time 501829321257 ps
CPU time 222.38 seconds
Started Mar 17 12:30:14 PM PDT 24
Finished Mar 17 12:33:56 PM PDT 24
Peak memory 194572 kb
Host smart-af235e6e-2e3f-4653-81a4-3a75ba0df7ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241561078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.4241561078
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2930420814
Short name T330
Test name
Test status
Simulation time 2216775918866 ps
CPU time 1268.62 seconds
Started Mar 17 12:30:10 PM PDT 24
Finished Mar 17 12:51:19 PM PDT 24
Peak memory 182812 kb
Host smart-75f68676-f207-4e75-b55f-d7596cbf237e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930420814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2930420814
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_random.1593032895
Short name T305
Test name
Test status
Simulation time 43511797979 ps
CPU time 363.78 seconds
Started Mar 17 12:30:02 PM PDT 24
Finished Mar 17 12:36:08 PM PDT 24
Peak memory 182628 kb
Host smart-a4e97cf1-42f6-4404-8025-63115737dec8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593032895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1593032895
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.93028341
Short name T359
Test name
Test status
Simulation time 81162777829 ps
CPU time 74.6 seconds
Started Mar 17 12:31:54 PM PDT 24
Finished Mar 17 12:33:08 PM PDT 24
Peak memory 190404 kb
Host smart-858b30ec-7485-4c21-b18f-9119474b3774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93028341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.93028341
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1549762781
Short name T223
Test name
Test status
Simulation time 142354545053 ps
CPU time 123.55 seconds
Started Mar 17 12:31:54 PM PDT 24
Finished Mar 17 12:33:58 PM PDT 24
Peak memory 182244 kb
Host smart-0fde4037-b0db-4356-9280-3865b63b34db
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549762781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1549762781
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/97.rv_timer_random.1509358421
Short name T345
Test name
Test status
Simulation time 69170441401 ps
CPU time 30.98 seconds
Started Mar 17 12:31:29 PM PDT 24
Finished Mar 17 12:32:01 PM PDT 24
Peak memory 182596 kb
Host smart-92e7ab84-fd61-4563-bc70-35a4cd56e2c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509358421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1509358421
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3696419528
Short name T576
Test name
Test status
Simulation time 106842054 ps
CPU time 0.83 seconds
Started Mar 17 01:03:03 PM PDT 24
Finished Mar 17 01:03:04 PM PDT 24
Peak memory 182676 kb
Host smart-2b6e906c-7930-443b-8388-e01da68fe1fd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696419528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3696419528
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.877592559
Short name T528
Test name
Test status
Simulation time 89284763 ps
CPU time 3.19 seconds
Started Mar 17 01:03:01 PM PDT 24
Finished Mar 17 01:03:04 PM PDT 24
Peak memory 193624 kb
Host smart-2d53e762-662c-4a3b-8001-b0ef321df519
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877592559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.877592559
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1540637468
Short name T533
Test name
Test status
Simulation time 46096369 ps
CPU time 0.61 seconds
Started Mar 17 01:03:02 PM PDT 24
Finished Mar 17 01:03:03 PM PDT 24
Peak memory 182736 kb
Host smart-268a2010-5c83-41de-821a-53dcd635831c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540637468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.1540637468
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.4262930620
Short name T45
Test name
Test status
Simulation time 67237852 ps
CPU time 0.67 seconds
Started Mar 17 01:03:04 PM PDT 24
Finished Mar 17 01:03:05 PM PDT 24
Peak memory 194140 kb
Host smart-d8443349-06b0-4021-a139-e8dcfde72b65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262930620 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.4262930620
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2798090788
Short name T516
Test name
Test status
Simulation time 26899332 ps
CPU time 0.6 seconds
Started Mar 17 01:03:10 PM PDT 24
Finished Mar 17 01:03:11 PM PDT 24
Peak memory 182676 kb
Host smart-23763849-1ba6-4a21-b8e7-d0eed3f14a02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798090788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.2798090788
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1722401976
Short name T518
Test name
Test status
Simulation time 59608108 ps
CPU time 0.57 seconds
Started Mar 17 01:03:03 PM PDT 24
Finished Mar 17 01:03:04 PM PDT 24
Peak memory 182488 kb
Host smart-8b2744c4-dbab-4910-80ee-e3ef81a0f59b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722401976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1722401976
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3868394996
Short name T537
Test name
Test status
Simulation time 75236979 ps
CPU time 1.41 seconds
Started Mar 17 01:03:02 PM PDT 24
Finished Mar 17 01:03:04 PM PDT 24
Peak memory 197604 kb
Host smart-7294abe4-6bfa-4d75-b545-b6076ca71e78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868394996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3868394996
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2623600384
Short name T107
Test name
Test status
Simulation time 454554016 ps
CPU time 1.35 seconds
Started Mar 17 01:03:10 PM PDT 24
Finished Mar 17 01:03:12 PM PDT 24
Peak memory 195380 kb
Host smart-16e23751-7fd4-46fa-91eb-f23e511f33c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623600384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2623600384
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2079703676
Short name T473
Test name
Test status
Simulation time 120511703 ps
CPU time 1.48 seconds
Started Mar 17 01:03:04 PM PDT 24
Finished Mar 17 01:03:06 PM PDT 24
Peak memory 191128 kb
Host smart-934d73f2-64e5-4e64-8448-53a0a5f4da75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079703676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2079703676
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1782586657
Short name T88
Test name
Test status
Simulation time 54812029 ps
CPU time 0.59 seconds
Started Mar 17 01:03:04 PM PDT 24
Finished Mar 17 01:03:04 PM PDT 24
Peak memory 182736 kb
Host smart-38e2240d-65ba-4d58-b5e6-f5759a53b784
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782586657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1782586657
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2653239541
Short name T502
Test name
Test status
Simulation time 18215304 ps
CPU time 0.85 seconds
Started Mar 17 01:03:16 PM PDT 24
Finished Mar 17 01:03:17 PM PDT 24
Peak memory 196588 kb
Host smart-dcfd154b-1dd7-4614-8001-705624a4858b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653239541 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2653239541
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1833977574
Short name T465
Test name
Test status
Simulation time 16439137 ps
CPU time 0.67 seconds
Started Mar 17 01:03:03 PM PDT 24
Finished Mar 17 01:03:03 PM PDT 24
Peak memory 182608 kb
Host smart-1ad3c0c3-acc8-40ca-9de8-501f357172ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833977574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1833977574
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3927271920
Short name T467
Test name
Test status
Simulation time 23085314 ps
CPU time 0.55 seconds
Started Mar 17 01:03:01 PM PDT 24
Finished Mar 17 01:03:02 PM PDT 24
Peak memory 182644 kb
Host smart-a5326288-153b-48cd-84f3-30d6754f82f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927271920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3927271920
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3746026669
Short name T527
Test name
Test status
Simulation time 64829396 ps
CPU time 0.71 seconds
Started Mar 17 01:03:10 PM PDT 24
Finished Mar 17 01:03:11 PM PDT 24
Peak memory 191748 kb
Host smart-8a7f4143-51bc-4949-96b3-2435def6715e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746026669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.3746026669
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.424763677
Short name T479
Test name
Test status
Simulation time 152367297 ps
CPU time 0.99 seconds
Started Mar 17 01:03:02 PM PDT 24
Finished Mar 17 01:03:03 PM PDT 24
Peak memory 196756 kb
Host smart-61a0af18-e6ee-40ea-a628-9d30aef8dbed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424763677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.424763677
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1544828250
Short name T104
Test name
Test status
Simulation time 1062233327 ps
CPU time 1.36 seconds
Started Mar 17 01:03:04 PM PDT 24
Finished Mar 17 01:03:06 PM PDT 24
Peak memory 195400 kb
Host smart-e5af1ef8-9318-4ceb-8d2b-0c130a007fbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544828250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1544828250
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.102439645
Short name T569
Test name
Test status
Simulation time 80399965 ps
CPU time 0.72 seconds
Started Mar 17 01:03:28 PM PDT 24
Finished Mar 17 01:03:30 PM PDT 24
Peak memory 195064 kb
Host smart-40656591-7c65-4629-a0e1-cdab263400e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102439645 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.102439645
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1897094242
Short name T91
Test name
Test status
Simulation time 18507594 ps
CPU time 0.62 seconds
Started Mar 17 01:03:28 PM PDT 24
Finished Mar 17 01:03:30 PM PDT 24
Peak memory 182776 kb
Host smart-ca8642d3-7c07-4c45-986d-c71751f16385
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897094242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1897094242
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3859563900
Short name T579
Test name
Test status
Simulation time 14359703 ps
CPU time 0.54 seconds
Started Mar 17 01:03:15 PM PDT 24
Finished Mar 17 01:03:16 PM PDT 24
Peak memory 182512 kb
Host smart-2b9bf528-d263-448e-a96c-31ebc69a2992
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859563900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3859563900
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1259619078
Short name T563
Test name
Test status
Simulation time 61007558 ps
CPU time 0.71 seconds
Started Mar 17 01:03:17 PM PDT 24
Finished Mar 17 01:03:18 PM PDT 24
Peak memory 193232 kb
Host smart-4f46c8b0-a242-430e-8a79-8296e8e8c0c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259619078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.1259619078
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.977619003
Short name T486
Test name
Test status
Simulation time 210010530 ps
CPU time 1.09 seconds
Started Mar 17 01:03:17 PM PDT 24
Finished Mar 17 01:03:18 PM PDT 24
Peak memory 197456 kb
Host smart-6aa33927-dd16-4971-8ab3-29d9a782c169
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977619003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.977619003
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2846709976
Short name T31
Test name
Test status
Simulation time 83125537 ps
CPU time 0.86 seconds
Started Mar 17 01:03:19 PM PDT 24
Finished Mar 17 01:03:21 PM PDT 24
Peak memory 193664 kb
Host smart-ace72ce6-ad98-46d5-802b-da2cf408db2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846709976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.2846709976
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2387635640
Short name T534
Test name
Test status
Simulation time 46418265 ps
CPU time 1.01 seconds
Started Mar 17 01:03:23 PM PDT 24
Finished Mar 17 01:03:26 PM PDT 24
Peak memory 197560 kb
Host smart-904dc072-654b-4ab7-ab5d-9f69cee8a4f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387635640 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2387635640
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.620493961
Short name T555
Test name
Test status
Simulation time 24487015 ps
CPU time 0.54 seconds
Started Mar 17 01:03:34 PM PDT 24
Finished Mar 17 01:03:35 PM PDT 24
Peak memory 182720 kb
Host smart-9bb23cca-157b-4234-952b-e24729910b0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620493961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.620493961
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1290527767
Short name T455
Test name
Test status
Simulation time 13610475 ps
CPU time 0.58 seconds
Started Mar 17 01:03:26 PM PDT 24
Finished Mar 17 01:03:27 PM PDT 24
Peak memory 182680 kb
Host smart-2d4ccb34-142a-4884-a2bd-a8c4c434e910
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290527767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.1290527767
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1500294660
Short name T92
Test name
Test status
Simulation time 41883524 ps
CPU time 0.81 seconds
Started Mar 17 01:03:27 PM PDT 24
Finished Mar 17 01:03:28 PM PDT 24
Peak memory 193476 kb
Host smart-79a8ea5d-4fff-4c61-9cb3-59c26bd26911
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500294660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.1500294660
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2263336830
Short name T468
Test name
Test status
Simulation time 69350242 ps
CPU time 1.85 seconds
Started Mar 17 01:03:17 PM PDT 24
Finished Mar 17 01:03:19 PM PDT 24
Peak memory 197532 kb
Host smart-68ea863f-2e73-4429-a775-da331428034a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263336830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2263336830
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2929823685
Short name T523
Test name
Test status
Simulation time 67669024 ps
CPU time 0.68 seconds
Started Mar 17 01:03:32 PM PDT 24
Finished Mar 17 01:03:32 PM PDT 24
Peak memory 194424 kb
Host smart-ce15ec0c-2b7e-4a26-804c-1b39b17445eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929823685 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2929823685
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2765440143
Short name T568
Test name
Test status
Simulation time 14562091 ps
CPU time 0.71 seconds
Started Mar 17 01:03:24 PM PDT 24
Finished Mar 17 01:03:25 PM PDT 24
Peak memory 182772 kb
Host smart-cc82d395-e823-4b46-97d2-bf8568065707
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765440143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2765440143
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.147347600
Short name T524
Test name
Test status
Simulation time 159570744 ps
CPU time 0.55 seconds
Started Mar 17 01:03:25 PM PDT 24
Finished Mar 17 01:03:26 PM PDT 24
Peak memory 182220 kb
Host smart-307d76fc-df26-4cbf-9bfb-bb7d30016d17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147347600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.147347600
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3913487328
Short name T557
Test name
Test status
Simulation time 54701986 ps
CPU time 0.6 seconds
Started Mar 17 01:03:27 PM PDT 24
Finished Mar 17 01:03:28 PM PDT 24
Peak memory 191468 kb
Host smart-e8c9ba43-e5c1-42f4-87f7-12b5b101429a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913487328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3913487328
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3840614263
Short name T460
Test name
Test status
Simulation time 211638358 ps
CPU time 2.66 seconds
Started Mar 17 01:03:27 PM PDT 24
Finished Mar 17 01:03:30 PM PDT 24
Peak memory 197576 kb
Host smart-6d65c171-f841-4347-b5c1-4662721fafce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840614263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.3840614263
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3915385301
Short name T103
Test name
Test status
Simulation time 127555076 ps
CPU time 1.1 seconds
Started Mar 17 01:03:37 PM PDT 24
Finished Mar 17 01:03:39 PM PDT 24
Peak memory 194808 kb
Host smart-d02e0c21-0fd5-4439-b3d6-cd79b7287e98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915385301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3915385301
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.4200933481
Short name T499
Test name
Test status
Simulation time 26819736 ps
CPU time 0.86 seconds
Started Mar 17 01:03:28 PM PDT 24
Finished Mar 17 01:03:30 PM PDT 24
Peak memory 195420 kb
Host smart-69792bcd-ced8-44cb-a337-93c8e53cff27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200933481 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.4200933481
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3009640313
Short name T85
Test name
Test status
Simulation time 29560055 ps
CPU time 0.57 seconds
Started Mar 17 01:03:34 PM PDT 24
Finished Mar 17 01:03:35 PM PDT 24
Peak memory 182716 kb
Host smart-08f78b77-7e1b-4bae-a677-e0e13c83704e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009640313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3009640313
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1841255699
Short name T509
Test name
Test status
Simulation time 12893386 ps
CPU time 0.52 seconds
Started Mar 17 01:03:37 PM PDT 24
Finished Mar 17 01:03:37 PM PDT 24
Peak memory 182012 kb
Host smart-9a0cb2ad-9271-4104-ab2f-466aa005f047
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841255699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1841255699
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1604554905
Short name T562
Test name
Test status
Simulation time 30711246 ps
CPU time 0.75 seconds
Started Mar 17 01:03:26 PM PDT 24
Finished Mar 17 01:03:27 PM PDT 24
Peak memory 193400 kb
Host smart-5cec617d-ad18-49cc-97d0-01ffa74ed86c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604554905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1604554905
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2705813916
Short name T506
Test name
Test status
Simulation time 200277048 ps
CPU time 1 seconds
Started Mar 17 01:03:26 PM PDT 24
Finished Mar 17 01:03:27 PM PDT 24
Peak memory 195132 kb
Host smart-c327e656-9a58-4c44-bed1-c6d6474bc697
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705813916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2705813916
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3429049299
Short name T542
Test name
Test status
Simulation time 114178683 ps
CPU time 0.87 seconds
Started Mar 17 01:03:28 PM PDT 24
Finished Mar 17 01:03:30 PM PDT 24
Peak memory 193488 kb
Host smart-cfc7f926-af25-4fd9-a473-30b953bc6ed9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429049299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3429049299
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.4005679703
Short name T504
Test name
Test status
Simulation time 120218838 ps
CPU time 0.86 seconds
Started Mar 17 01:03:36 PM PDT 24
Finished Mar 17 01:03:37 PM PDT 24
Peak memory 196772 kb
Host smart-4e99a1de-ddfa-44bc-bd2a-6cac1fca5b9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005679703 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.4005679703
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3476633716
Short name T559
Test name
Test status
Simulation time 14116011 ps
CPU time 0.55 seconds
Started Mar 17 01:03:29 PM PDT 24
Finished Mar 17 01:03:30 PM PDT 24
Peak memory 182368 kb
Host smart-c8716067-8673-4b04-a472-e378c88a035e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476633716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3476633716
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.4266627718
Short name T481
Test name
Test status
Simulation time 41777662 ps
CPU time 0.51 seconds
Started Mar 17 01:03:39 PM PDT 24
Finished Mar 17 01:03:39 PM PDT 24
Peak memory 182004 kb
Host smart-d67438f0-7ee3-4515-b4d6-b05f1f0f7f62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266627718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.4266627718
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2496557333
Short name T73
Test name
Test status
Simulation time 38455311 ps
CPU time 0.81 seconds
Started Mar 17 01:03:28 PM PDT 24
Finished Mar 17 01:03:30 PM PDT 24
Peak memory 193592 kb
Host smart-87795193-042f-44fb-aecb-1a6ecf69cd0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496557333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.2496557333
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3338316115
Short name T497
Test name
Test status
Simulation time 330732585 ps
CPU time 2.23 seconds
Started Mar 17 01:03:39 PM PDT 24
Finished Mar 17 01:03:41 PM PDT 24
Peak memory 197520 kb
Host smart-db93c395-f7ca-4283-814f-0665ecce58e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338316115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3338316115
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3835664236
Short name T106
Test name
Test status
Simulation time 154597398 ps
CPU time 1.42 seconds
Started Mar 17 01:03:25 PM PDT 24
Finished Mar 17 01:03:27 PM PDT 24
Peak memory 195288 kb
Host smart-f1d2c3aa-cb06-4d3c-9a3b-7493c6910c91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835664236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.3835664236
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3648998106
Short name T478
Test name
Test status
Simulation time 61883784 ps
CPU time 0.79 seconds
Started Mar 17 01:03:34 PM PDT 24
Finished Mar 17 01:03:35 PM PDT 24
Peak memory 195552 kb
Host smart-0e380699-8951-4c7a-8c6c-fffd95786cf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648998106 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3648998106
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.978897866
Short name T82
Test name
Test status
Simulation time 29595526 ps
CPU time 0.6 seconds
Started Mar 17 01:03:35 PM PDT 24
Finished Mar 17 01:03:36 PM PDT 24
Peak memory 182676 kb
Host smart-3ae64798-c5c2-4d9d-a3cb-edb5f80bc50a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978897866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.978897866
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3861537829
Short name T464
Test name
Test status
Simulation time 12445731 ps
CPU time 0.54 seconds
Started Mar 17 01:03:26 PM PDT 24
Finished Mar 17 01:03:27 PM PDT 24
Peak memory 182132 kb
Host smart-792ae473-aa43-493c-b7b3-b7163a8da559
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861537829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3861537829
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.42040839
Short name T99
Test name
Test status
Simulation time 61240296 ps
CPU time 0.81 seconds
Started Mar 17 01:03:28 PM PDT 24
Finished Mar 17 01:03:30 PM PDT 24
Peak memory 191700 kb
Host smart-9fd5ea15-bdc4-4a0f-a2e7-d5e325bb55ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42040839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_tim
er_same_csr_outstanding.42040839
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1712718533
Short name T581
Test name
Test status
Simulation time 154701796 ps
CPU time 1.01 seconds
Started Mar 17 01:03:38 PM PDT 24
Finished Mar 17 01:03:39 PM PDT 24
Peak memory 191064 kb
Host smart-4bda9e3b-86be-4511-8b21-0e2db38b2536
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712718533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1712718533
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.520900748
Short name T536
Test name
Test status
Simulation time 153989363 ps
CPU time 1.25 seconds
Started Mar 17 01:03:26 PM PDT 24
Finished Mar 17 01:03:27 PM PDT 24
Peak memory 183264 kb
Host smart-bfd6f73d-31b0-437c-93d8-91b0d9f7d44a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520900748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_in
tg_err.520900748
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2403828792
Short name T484
Test name
Test status
Simulation time 22882027 ps
CPU time 0.79 seconds
Started Mar 17 01:03:39 PM PDT 24
Finished Mar 17 01:03:45 PM PDT 24
Peak memory 194980 kb
Host smart-c3db7227-46fc-42f7-94ef-98e349682fde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403828792 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2403828792
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.677303077
Short name T46
Test name
Test status
Simulation time 37949764 ps
CPU time 0.56 seconds
Started Mar 17 01:03:25 PM PDT 24
Finished Mar 17 01:03:26 PM PDT 24
Peak memory 182480 kb
Host smart-cb665b1d-c4a5-45e0-a569-6061c1112367
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677303077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.677303077
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1201486543
Short name T453
Test name
Test status
Simulation time 84891148 ps
CPU time 0.55 seconds
Started Mar 17 01:03:25 PM PDT 24
Finished Mar 17 01:03:26 PM PDT 24
Peak memory 182060 kb
Host smart-c5b1ad3b-1531-4ae9-b82c-d91c53d5c0e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201486543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1201486543
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2312858292
Short name T573
Test name
Test status
Simulation time 40025941 ps
CPU time 0.84 seconds
Started Mar 17 01:03:33 PM PDT 24
Finished Mar 17 01:03:34 PM PDT 24
Peak memory 192744 kb
Host smart-e1a151db-63eb-4693-bc6b-7d1e111abfc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312858292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2312858292
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2836639385
Short name T543
Test name
Test status
Simulation time 51111257 ps
CPU time 2.49 seconds
Started Mar 17 01:03:31 PM PDT 24
Finished Mar 17 01:03:33 PM PDT 24
Peak memory 197680 kb
Host smart-2f1eeaac-1be2-4140-88fd-9bc3288b5795
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836639385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2836639385
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3017206148
Short name T558
Test name
Test status
Simulation time 279157171 ps
CPU time 1.15 seconds
Started Mar 17 01:03:25 PM PDT 24
Finished Mar 17 01:03:26 PM PDT 24
Peak memory 183360 kb
Host smart-f8d7320a-126f-4108-8c3b-b8d3f88cc08f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017206148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3017206148
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3506041100
Short name T560
Test name
Test status
Simulation time 18690532 ps
CPU time 0.81 seconds
Started Mar 17 01:03:44 PM PDT 24
Finished Mar 17 01:03:45 PM PDT 24
Peak memory 196644 kb
Host smart-1a212e74-1fd4-413c-8cc8-3e7cab89ea02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506041100 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3506041100
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.819087977
Short name T545
Test name
Test status
Simulation time 99749548 ps
CPU time 0.54 seconds
Started Mar 17 01:03:38 PM PDT 24
Finished Mar 17 01:03:39 PM PDT 24
Peak memory 182460 kb
Host smart-88583781-5fdf-41b8-ae0c-4cdd181782b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819087977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.819087977
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2458295484
Short name T512
Test name
Test status
Simulation time 23515499 ps
CPU time 0.54 seconds
Started Mar 17 01:03:48 PM PDT 24
Finished Mar 17 01:03:49 PM PDT 24
Peak memory 182532 kb
Host smart-16c70586-bc9d-4a13-b127-a51affc2116d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458295484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.2458295484
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2622097979
Short name T97
Test name
Test status
Simulation time 160700942 ps
CPU time 0.62 seconds
Started Mar 17 01:03:39 PM PDT 24
Finished Mar 17 01:03:40 PM PDT 24
Peak memory 191940 kb
Host smart-d5f88fc5-1291-470c-9c58-2bf7a9c00d28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622097979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2622097979
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3668110249
Short name T458
Test name
Test status
Simulation time 125908034 ps
CPU time 1.72 seconds
Started Mar 17 01:03:33 PM PDT 24
Finished Mar 17 01:03:35 PM PDT 24
Peak memory 197648 kb
Host smart-073ca54d-f9b2-472b-9aa9-700f7d72375d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668110249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3668110249
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1790357671
Short name T489
Test name
Test status
Simulation time 51735997 ps
CPU time 0.83 seconds
Started Mar 17 01:03:40 PM PDT 24
Finished Mar 17 01:03:41 PM PDT 24
Peak memory 193600 kb
Host smart-28715320-bf28-4830-807f-91841e0387e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790357671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1790357671
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.4060502995
Short name T510
Test name
Test status
Simulation time 259677049 ps
CPU time 1.03 seconds
Started Mar 17 01:03:41 PM PDT 24
Finished Mar 17 01:03:42 PM PDT 24
Peak memory 197424 kb
Host smart-e2934314-0953-4616-8059-a602103dcc72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060502995 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.4060502995
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3679383366
Short name T575
Test name
Test status
Simulation time 84269442 ps
CPU time 0.52 seconds
Started Mar 17 01:04:04 PM PDT 24
Finished Mar 17 01:04:04 PM PDT 24
Peak memory 182048 kb
Host smart-4bae73ab-95a2-4d22-9caf-dcf7c8912235
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679383366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3679383366
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1860625811
Short name T574
Test name
Test status
Simulation time 448959354 ps
CPU time 0.79 seconds
Started Mar 17 01:03:48 PM PDT 24
Finished Mar 17 01:03:49 PM PDT 24
Peak memory 193484 kb
Host smart-5ed54435-10ee-4f8d-966a-2ad8f0423684
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860625811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1860625811
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.734619133
Short name T541
Test name
Test status
Simulation time 1028921628 ps
CPU time 1.56 seconds
Started Mar 17 01:03:42 PM PDT 24
Finished Mar 17 01:03:44 PM PDT 24
Peak memory 197536 kb
Host smart-cc598ef5-4100-4e72-a9df-2614069f0955
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734619133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.734619133
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1241748774
Short name T105
Test name
Test status
Simulation time 595936383 ps
CPU time 1.13 seconds
Started Mar 17 01:03:38 PM PDT 24
Finished Mar 17 01:03:39 PM PDT 24
Peak memory 195060 kb
Host smart-8d4b3cc9-64f7-4469-86f5-4b7a7f8471c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241748774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1241748774
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1768773118
Short name T466
Test name
Test status
Simulation time 137505168 ps
CPU time 1.19 seconds
Started Mar 17 01:03:42 PM PDT 24
Finished Mar 17 01:03:43 PM PDT 24
Peak memory 197644 kb
Host smart-49c42212-6137-4b30-b6a8-3773021587fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768773118 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1768773118
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.336423420
Short name T81
Test name
Test status
Simulation time 13340062 ps
CPU time 0.57 seconds
Started Mar 17 01:03:38 PM PDT 24
Finished Mar 17 01:03:39 PM PDT 24
Peak memory 182704 kb
Host smart-e85ff1a9-4505-434f-9559-6d891152e6da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336423420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.336423420
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2107713504
Short name T577
Test name
Test status
Simulation time 26555184 ps
CPU time 0.58 seconds
Started Mar 17 01:03:44 PM PDT 24
Finished Mar 17 01:03:45 PM PDT 24
Peak memory 182684 kb
Host smart-852f3dc8-37cc-4235-a5b5-67b871e6bbe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107713504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2107713504
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3117006321
Short name T570
Test name
Test status
Simulation time 33398355 ps
CPU time 0.61 seconds
Started Mar 17 01:03:44 PM PDT 24
Finished Mar 17 01:03:45 PM PDT 24
Peak memory 191488 kb
Host smart-5785463c-e9dd-4c1e-af56-243eeee09910
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117006321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3117006321
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2054767424
Short name T461
Test name
Test status
Simulation time 188545978 ps
CPU time 2.53 seconds
Started Mar 17 01:03:43 PM PDT 24
Finished Mar 17 01:03:46 PM PDT 24
Peak memory 197564 kb
Host smart-daf48a3e-2994-4103-84bd-2f866f99ecb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054767424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2054767424
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2394647578
Short name T521
Test name
Test status
Simulation time 129773367 ps
CPU time 1.03 seconds
Started Mar 17 01:03:38 PM PDT 24
Finished Mar 17 01:03:39 PM PDT 24
Peak memory 194364 kb
Host smart-a1e46ba9-a465-40ff-aab9-6fdd7bfc186f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394647578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2394647578
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2201478709
Short name T492
Test name
Test status
Simulation time 188257377 ps
CPU time 0.62 seconds
Started Mar 17 01:03:08 PM PDT 24
Finished Mar 17 01:03:09 PM PDT 24
Peak memory 182668 kb
Host smart-2aada1d9-2c84-464b-b4af-0e803a36956f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201478709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.2201478709
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.35299023
Short name T505
Test name
Test status
Simulation time 1023982164 ps
CPU time 2.55 seconds
Started Mar 17 01:03:09 PM PDT 24
Finished Mar 17 01:03:13 PM PDT 24
Peak memory 192280 kb
Host smart-8270214f-df2c-4cda-8078-662eb9027433
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35299023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_ba
sh.35299023
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2890269868
Short name T498
Test name
Test status
Simulation time 14072453 ps
CPU time 0.54 seconds
Started Mar 17 01:03:10 PM PDT 24
Finished Mar 17 01:03:11 PM PDT 24
Peak memory 182352 kb
Host smart-492043b8-be45-4565-8f65-322153e784a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890269868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2890269868
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1644106959
Short name T459
Test name
Test status
Simulation time 42496250 ps
CPU time 1.84 seconds
Started Mar 17 01:03:15 PM PDT 24
Finished Mar 17 01:03:16 PM PDT 24
Peak memory 197592 kb
Host smart-e0369939-b847-49d0-b61c-c8449ef92599
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644106959 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1644106959
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2740353748
Short name T503
Test name
Test status
Simulation time 14644493 ps
CPU time 0.6 seconds
Started Mar 17 01:03:17 PM PDT 24
Finished Mar 17 01:03:20 PM PDT 24
Peak memory 182676 kb
Host smart-e90ce2cc-1603-48a9-85ee-2a882774bf90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740353748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2740353748
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2659058231
Short name T556
Test name
Test status
Simulation time 42730051 ps
CPU time 0.54 seconds
Started Mar 17 01:03:10 PM PDT 24
Finished Mar 17 01:03:11 PM PDT 24
Peak memory 182632 kb
Host smart-7425d0e9-795b-4868-b1db-0ab38acd5c84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659058231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2659058231
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1240672574
Short name T94
Test name
Test status
Simulation time 73999618 ps
CPU time 0.61 seconds
Started Mar 17 01:03:17 PM PDT 24
Finished Mar 17 01:03:18 PM PDT 24
Peak memory 191988 kb
Host smart-f0eb7ead-12bf-4ebf-9d7f-633a3183bb20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240672574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.1240672574
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1937455390
Short name T476
Test name
Test status
Simulation time 342781323 ps
CPU time 1.48 seconds
Started Mar 17 01:03:11 PM PDT 24
Finished Mar 17 01:03:13 PM PDT 24
Peak memory 197560 kb
Host smart-231933cc-cebc-4f5c-a4df-73d5abb14290
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937455390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1937455390
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.734233138
Short name T525
Test name
Test status
Simulation time 138007389 ps
CPU time 1 seconds
Started Mar 17 01:03:10 PM PDT 24
Finished Mar 17 01:03:11 PM PDT 24
Peak memory 195216 kb
Host smart-da654cc5-88de-4d1e-b623-13f154ceb588
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734233138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_int
g_err.734233138
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.4069411847
Short name T515
Test name
Test status
Simulation time 14383277 ps
CPU time 0.57 seconds
Started Mar 17 01:03:43 PM PDT 24
Finished Mar 17 01:03:43 PM PDT 24
Peak memory 182608 kb
Host smart-ff6b2230-6786-4505-b587-d3d08aa2f7a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069411847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.4069411847
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2996936124
Short name T480
Test name
Test status
Simulation time 12842254 ps
CPU time 0.58 seconds
Started Mar 17 01:03:42 PM PDT 24
Finished Mar 17 01:03:42 PM PDT 24
Peak memory 182212 kb
Host smart-798462ab-b2d1-4b39-83a5-12f10c22013c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996936124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.2996936124
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.26539514
Short name T531
Test name
Test status
Simulation time 16797944 ps
CPU time 0.53 seconds
Started Mar 17 01:03:42 PM PDT 24
Finished Mar 17 01:03:42 PM PDT 24
Peak memory 182552 kb
Host smart-5ad7d89c-9995-4272-8fe7-dfb587ee1a9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26539514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.26539514
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3103461018
Short name T552
Test name
Test status
Simulation time 28273602 ps
CPU time 0.58 seconds
Started Mar 17 01:03:41 PM PDT 24
Finished Mar 17 01:03:42 PM PDT 24
Peak memory 182612 kb
Host smart-b2788527-706d-4b24-92af-c5ad19712b61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103461018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3103461018
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3642990221
Short name T547
Test name
Test status
Simulation time 12263076 ps
CPU time 0.55 seconds
Started Mar 17 01:03:47 PM PDT 24
Finished Mar 17 01:03:48 PM PDT 24
Peak memory 182208 kb
Host smart-98f8c312-e826-4d05-b19f-e1569cf31e55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642990221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3642990221
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.770850757
Short name T548
Test name
Test status
Simulation time 14594489 ps
CPU time 0.54 seconds
Started Mar 17 01:03:39 PM PDT 24
Finished Mar 17 01:03:40 PM PDT 24
Peak memory 182612 kb
Host smart-ebb5c35a-d194-4f5f-b141-7b7d272e9c01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770850757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.770850757
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3632415927
Short name T485
Test name
Test status
Simulation time 48586578 ps
CPU time 0.57 seconds
Started Mar 17 01:03:43 PM PDT 24
Finished Mar 17 01:03:44 PM PDT 24
Peak memory 182564 kb
Host smart-67383070-0c81-4fa0-a4bd-7dd14751f4b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632415927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.3632415927
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2029837221
Short name T544
Test name
Test status
Simulation time 13010313 ps
CPU time 0.56 seconds
Started Mar 17 01:03:40 PM PDT 24
Finished Mar 17 01:03:40 PM PDT 24
Peak memory 182584 kb
Host smart-4c39d581-cadf-44c1-b79b-689985c1e99a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029837221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2029837221
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1667060521
Short name T456
Test name
Test status
Simulation time 40559190 ps
CPU time 0.55 seconds
Started Mar 17 01:03:39 PM PDT 24
Finished Mar 17 01:03:40 PM PDT 24
Peak memory 182040 kb
Host smart-dfbf5beb-9d6a-4a42-8148-72cd29ef6b77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667060521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1667060521
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.455077865
Short name T550
Test name
Test status
Simulation time 22037308 ps
CPU time 0.54 seconds
Started Mar 17 01:03:38 PM PDT 24
Finished Mar 17 01:03:38 PM PDT 24
Peak memory 182608 kb
Host smart-f1e35fcf-31a5-4b6b-912a-de3445944058
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455077865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.455077865
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1795063095
Short name T84
Test name
Test status
Simulation time 26055692 ps
CPU time 0.75 seconds
Started Mar 17 01:03:14 PM PDT 24
Finished Mar 17 01:03:15 PM PDT 24
Peak memory 182736 kb
Host smart-7d0095e5-bc31-4608-ada0-eebfae43a6e8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795063095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.1795063095
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.296074510
Short name T74
Test name
Test status
Simulation time 356202031 ps
CPU time 3.72 seconds
Started Mar 17 01:03:08 PM PDT 24
Finished Mar 17 01:03:12 PM PDT 24
Peak memory 194100 kb
Host smart-e17d2324-c13a-4971-8427-16e82efab5b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296074510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.296074510
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1695759293
Short name T540
Test name
Test status
Simulation time 16178543 ps
CPU time 0.56 seconds
Started Mar 17 01:03:10 PM PDT 24
Finished Mar 17 01:03:11 PM PDT 24
Peak memory 182672 kb
Host smart-958056d6-cff3-4a40-8ab2-4926c3ffb5ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695759293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.1695759293
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1254926563
Short name T500
Test name
Test status
Simulation time 72163792 ps
CPU time 0.67 seconds
Started Mar 17 01:03:10 PM PDT 24
Finished Mar 17 01:03:11 PM PDT 24
Peak memory 194160 kb
Host smart-2e07f055-5fae-4a51-a3e2-ae0a487a3590
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254926563 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1254926563
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1514000252
Short name T90
Test name
Test status
Simulation time 48570102 ps
CPU time 0.64 seconds
Started Mar 17 01:03:10 PM PDT 24
Finished Mar 17 01:03:11 PM PDT 24
Peak memory 182740 kb
Host smart-089b5cb8-78b2-414d-af7c-abc1aa3e3349
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514000252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1514000252
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.709357736
Short name T507
Test name
Test status
Simulation time 40750246 ps
CPU time 0.54 seconds
Started Mar 17 01:03:18 PM PDT 24
Finished Mar 17 01:03:21 PM PDT 24
Peak memory 182616 kb
Host smart-98de610d-e6f6-4c63-a8ba-da3be47ef5e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709357736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.709357736
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3557721940
Short name T567
Test name
Test status
Simulation time 21691414 ps
CPU time 0.73 seconds
Started Mar 17 01:03:17 PM PDT 24
Finished Mar 17 01:03:18 PM PDT 24
Peak memory 193308 kb
Host smart-3249ae6d-692b-4053-a6e0-1c6c0a7a93ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557721940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3557721940
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2536911138
Short name T501
Test name
Test status
Simulation time 132043046 ps
CPU time 2.13 seconds
Started Mar 17 01:03:12 PM PDT 24
Finished Mar 17 01:03:15 PM PDT 24
Peak memory 197596 kb
Host smart-bf4f083e-bb67-4d7e-a2e2-ff6aefa12a01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536911138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2536911138
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.638707969
Short name T511
Test name
Test status
Simulation time 60392385 ps
CPU time 0.57 seconds
Started Mar 17 01:03:39 PM PDT 24
Finished Mar 17 01:03:39 PM PDT 24
Peak memory 182596 kb
Host smart-ec291e90-66f8-4f95-a6a4-eb6d424c297b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638707969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.638707969
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2305179196
Short name T463
Test name
Test status
Simulation time 11260995 ps
CPU time 0.51 seconds
Started Mar 17 01:03:51 PM PDT 24
Finished Mar 17 01:03:52 PM PDT 24
Peak memory 181964 kb
Host smart-ca0a85fc-3b2a-4711-b206-65890a5c3e69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305179196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2305179196
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2010482318
Short name T495
Test name
Test status
Simulation time 22115444 ps
CPU time 0.54 seconds
Started Mar 17 01:03:40 PM PDT 24
Finished Mar 17 01:03:41 PM PDT 24
Peak memory 182580 kb
Host smart-bd7ccadb-1795-4910-8c0b-4141e3be4064
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010482318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.2010482318
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1575323458
Short name T491
Test name
Test status
Simulation time 56350074 ps
CPU time 0.59 seconds
Started Mar 17 01:03:38 PM PDT 24
Finished Mar 17 01:03:39 PM PDT 24
Peak memory 182664 kb
Host smart-74599411-7fe1-4d34-9008-cc0dbe567dbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575323458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1575323458
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1098335942
Short name T494
Test name
Test status
Simulation time 19468538 ps
CPU time 0.53 seconds
Started Mar 17 01:03:39 PM PDT 24
Finished Mar 17 01:03:39 PM PDT 24
Peak memory 182256 kb
Host smart-b1014632-1f76-44ab-813e-ec1d4f633c8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098335942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.1098335942
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2979375335
Short name T519
Test name
Test status
Simulation time 29248980 ps
CPU time 0.56 seconds
Started Mar 17 01:03:42 PM PDT 24
Finished Mar 17 01:03:43 PM PDT 24
Peak memory 182492 kb
Host smart-73a71ede-342e-4448-9eeb-da1d8b4ea591
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979375335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2979375335
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3958572063
Short name T477
Test name
Test status
Simulation time 157037035 ps
CPU time 0.53 seconds
Started Mar 17 01:03:54 PM PDT 24
Finished Mar 17 01:03:55 PM PDT 24
Peak memory 182508 kb
Host smart-c56d9bb2-3194-4364-a2c3-e392d64a7002
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958572063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3958572063
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1285985052
Short name T508
Test name
Test status
Simulation time 31972436 ps
CPU time 0.52 seconds
Started Mar 17 01:03:47 PM PDT 24
Finished Mar 17 01:03:48 PM PDT 24
Peak memory 181992 kb
Host smart-6315d2f8-1529-47a2-852e-cdce202ae966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285985052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1285985052
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.983551146
Short name T532
Test name
Test status
Simulation time 35364352 ps
CPU time 0.56 seconds
Started Mar 17 01:03:38 PM PDT 24
Finished Mar 17 01:03:39 PM PDT 24
Peak memory 182180 kb
Host smart-e789bbb0-4e1f-4e2d-b1bf-83c525bfea84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983551146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.983551146
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2177957957
Short name T561
Test name
Test status
Simulation time 105486302 ps
CPU time 0.52 seconds
Started Mar 17 01:03:38 PM PDT 24
Finished Mar 17 01:03:39 PM PDT 24
Peak memory 182096 kb
Host smart-1c8d360f-b052-4810-aaa9-1a42c5ba85e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177957957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2177957957
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1444997595
Short name T86
Test name
Test status
Simulation time 64916308 ps
CPU time 0.8 seconds
Started Mar 17 01:03:16 PM PDT 24
Finished Mar 17 01:03:17 PM PDT 24
Peak memory 192560 kb
Host smart-50700f03-8e12-457a-829a-c135871baff8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444997595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1444997595
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2518866438
Short name T83
Test name
Test status
Simulation time 545326525 ps
CPU time 2.75 seconds
Started Mar 17 01:03:19 PM PDT 24
Finished Mar 17 01:03:23 PM PDT 24
Peak memory 191140 kb
Host smart-5829850b-791f-48f4-abdb-46c97ebd6377
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518866438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2518866438
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.954056777
Short name T33
Test name
Test status
Simulation time 47824043 ps
CPU time 0.59 seconds
Started Mar 17 01:03:19 PM PDT 24
Finished Mar 17 01:03:21 PM PDT 24
Peak memory 182732 kb
Host smart-139c0df4-462e-4a01-9476-412d001bbfbb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954056777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re
set.954056777
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.4185231733
Short name T546
Test name
Test status
Simulation time 30052624 ps
CPU time 0.76 seconds
Started Mar 17 01:03:16 PM PDT 24
Finished Mar 17 01:03:18 PM PDT 24
Peak memory 195256 kb
Host smart-6f894b08-8711-44a0-9511-32a4c566e235
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185231733 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.4185231733
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2176112229
Short name T566
Test name
Test status
Simulation time 14918127 ps
CPU time 0.64 seconds
Started Mar 17 01:03:15 PM PDT 24
Finished Mar 17 01:03:16 PM PDT 24
Peak memory 182628 kb
Host smart-7503d60a-6d79-4f92-b715-25aa4d0192a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176112229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2176112229
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1660974908
Short name T475
Test name
Test status
Simulation time 19698794 ps
CPU time 0.52 seconds
Started Mar 17 01:03:10 PM PDT 24
Finished Mar 17 01:03:11 PM PDT 24
Peak memory 182376 kb
Host smart-f5884d41-b5f8-4408-89ee-396ddbf3109f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660974908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1660974908
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1093064116
Short name T95
Test name
Test status
Simulation time 21468945 ps
CPU time 0.66 seconds
Started Mar 17 01:03:17 PM PDT 24
Finished Mar 17 01:03:18 PM PDT 24
Peak memory 191620 kb
Host smart-9acadd6d-ecb1-4bba-8329-2eedd5423f6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093064116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.1093064116
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2265868839
Short name T551
Test name
Test status
Simulation time 25479499 ps
CPU time 1.16 seconds
Started Mar 17 01:03:12 PM PDT 24
Finished Mar 17 01:03:14 PM PDT 24
Peak memory 197572 kb
Host smart-a82478a0-e6bb-4d6f-bd15-e9642786d002
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265868839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2265868839
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2847661494
Short name T572
Test name
Test status
Simulation time 364775468 ps
CPU time 1.35 seconds
Started Mar 17 01:03:12 PM PDT 24
Finished Mar 17 01:03:13 PM PDT 24
Peak memory 183456 kb
Host smart-cd1480e3-8b46-4acc-80b1-97e485835338
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847661494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2847661494
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.522799641
Short name T538
Test name
Test status
Simulation time 14785321 ps
CPU time 0.55 seconds
Started Mar 17 01:03:42 PM PDT 24
Finished Mar 17 01:03:43 PM PDT 24
Peak memory 182684 kb
Host smart-af587d9e-252c-4b00-996a-e0ccf6d14fa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522799641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.522799641
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3470651484
Short name T580
Test name
Test status
Simulation time 48615369 ps
CPU time 0.54 seconds
Started Mar 17 01:03:41 PM PDT 24
Finished Mar 17 01:03:42 PM PDT 24
Peak memory 182080 kb
Host smart-62f966be-9b28-47cb-894c-3ac9477aede2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470651484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3470651484
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.919068196
Short name T564
Test name
Test status
Simulation time 34351719 ps
CPU time 0.54 seconds
Started Mar 17 01:03:42 PM PDT 24
Finished Mar 17 01:03:42 PM PDT 24
Peak memory 182484 kb
Host smart-c7f4d859-e39e-4a43-a5fc-30477016757c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919068196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.919068196
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2646211267
Short name T454
Test name
Test status
Simulation time 112553994 ps
CPU time 0.53 seconds
Started Mar 17 01:03:42 PM PDT 24
Finished Mar 17 01:03:43 PM PDT 24
Peak memory 182596 kb
Host smart-2921d075-d7fb-484b-9c15-3851ced5e7c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646211267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2646211267
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2236455666
Short name T529
Test name
Test status
Simulation time 18815102 ps
CPU time 0.66 seconds
Started Mar 17 01:03:39 PM PDT 24
Finished Mar 17 01:03:40 PM PDT 24
Peak memory 182624 kb
Host smart-2dd4e81f-728e-415c-afda-0be7c0265ac6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236455666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2236455666
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2240489234
Short name T474
Test name
Test status
Simulation time 13062986 ps
CPU time 0.55 seconds
Started Mar 17 01:03:40 PM PDT 24
Finished Mar 17 01:03:41 PM PDT 24
Peak memory 182096 kb
Host smart-a3042e87-a405-4002-aea4-92031c8b9b15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240489234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2240489234
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3954962447
Short name T493
Test name
Test status
Simulation time 16209626 ps
CPU time 0.54 seconds
Started Mar 17 01:03:43 PM PDT 24
Finished Mar 17 01:03:43 PM PDT 24
Peak memory 182100 kb
Host smart-010a5f6f-f2a3-478a-98f4-a098249a737b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954962447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3954962447
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3031936319
Short name T496
Test name
Test status
Simulation time 33818025 ps
CPU time 0.53 seconds
Started Mar 17 01:03:46 PM PDT 24
Finished Mar 17 01:03:46 PM PDT 24
Peak memory 182084 kb
Host smart-ef5366c0-2855-4b4a-b15d-1735ba280a69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031936319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3031936319
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1367717164
Short name T522
Test name
Test status
Simulation time 26817223 ps
CPU time 0.57 seconds
Started Mar 17 01:03:44 PM PDT 24
Finished Mar 17 01:03:44 PM PDT 24
Peak memory 182540 kb
Host smart-c4682993-f930-4ce1-933f-6cf397793411
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367717164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1367717164
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3174579738
Short name T472
Test name
Test status
Simulation time 16004446 ps
CPU time 0.56 seconds
Started Mar 17 01:03:44 PM PDT 24
Finished Mar 17 01:03:45 PM PDT 24
Peak memory 182604 kb
Host smart-4aa7238d-059e-4fa2-8c53-5a9dba8cd195
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174579738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3174579738
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2942560865
Short name T578
Test name
Test status
Simulation time 36634459 ps
CPU time 0.82 seconds
Started Mar 17 01:03:22 PM PDT 24
Finished Mar 17 01:03:25 PM PDT 24
Peak memory 196684 kb
Host smart-fd2c0c14-6aa5-4c37-b1df-489dee4abc7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942560865 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2942560865
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1088348705
Short name T539
Test name
Test status
Simulation time 46085899 ps
CPU time 0.5 seconds
Started Mar 17 01:03:15 PM PDT 24
Finished Mar 17 01:03:16 PM PDT 24
Peak memory 182500 kb
Host smart-b20b832f-5f4b-48cc-a83c-a32c8a64a904
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088348705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1088348705
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.980294653
Short name T457
Test name
Test status
Simulation time 26839725 ps
CPU time 0.57 seconds
Started Mar 17 01:03:22 PM PDT 24
Finished Mar 17 01:03:25 PM PDT 24
Peak memory 182216 kb
Host smart-87ef563e-5250-4b9b-82db-dc43d06aea42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980294653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.980294653
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1742724340
Short name T100
Test name
Test status
Simulation time 168528899 ps
CPU time 0.78 seconds
Started Mar 17 01:03:16 PM PDT 24
Finished Mar 17 01:03:17 PM PDT 24
Peak memory 193440 kb
Host smart-f3a8aae7-8525-43e8-8869-ca26c8b9e500
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742724340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1742724340
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1941930219
Short name T514
Test name
Test status
Simulation time 97182011 ps
CPU time 2.34 seconds
Started Mar 17 01:03:20 PM PDT 24
Finished Mar 17 01:03:23 PM PDT 24
Peak memory 197644 kb
Host smart-461516f1-9114-4187-ab1e-51f115581041
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941930219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1941930219
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1651057413
Short name T488
Test name
Test status
Simulation time 90777697 ps
CPU time 1.1 seconds
Started Mar 17 01:03:19 PM PDT 24
Finished Mar 17 01:03:22 PM PDT 24
Peak memory 195128 kb
Host smart-4bdfc673-12b4-4f1b-a42c-432ec4ae265a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651057413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1651057413
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1025785002
Short name T530
Test name
Test status
Simulation time 51269367 ps
CPU time 0.66 seconds
Started Mar 17 01:03:19 PM PDT 24
Finished Mar 17 01:03:21 PM PDT 24
Peak memory 193424 kb
Host smart-48c10fd0-acbd-4e8f-a1db-1c7c19e68a6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025785002 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1025785002
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1944611536
Short name T87
Test name
Test status
Simulation time 14439953 ps
CPU time 0.55 seconds
Started Mar 17 01:03:18 PM PDT 24
Finished Mar 17 01:03:21 PM PDT 24
Peak memory 182648 kb
Host smart-d873965e-4c14-40ec-bff5-a4a7f9c0177c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944611536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1944611536
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.328866792
Short name T471
Test name
Test status
Simulation time 40162495 ps
CPU time 0.55 seconds
Started Mar 17 01:03:23 PM PDT 24
Finished Mar 17 01:03:25 PM PDT 24
Peak memory 181948 kb
Host smart-62ec71a3-bca2-482a-aafd-e3cf321c89fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328866792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.328866792
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.547568806
Short name T565
Test name
Test status
Simulation time 27650780 ps
CPU time 0.78 seconds
Started Mar 17 01:03:18 PM PDT 24
Finished Mar 17 01:03:21 PM PDT 24
Peak memory 193104 kb
Host smart-83074b53-3fe2-4b18-b0d9-9825be1a8b05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547568806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.547568806
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2034911766
Short name T469
Test name
Test status
Simulation time 66571469 ps
CPU time 1.5 seconds
Started Mar 17 01:03:16 PM PDT 24
Finished Mar 17 01:03:18 PM PDT 24
Peak memory 197604 kb
Host smart-6600500d-94d4-4cc1-a7b4-aea1affe717a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034911766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2034911766
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3284515961
Short name T108
Test name
Test status
Simulation time 69369296 ps
CPU time 1.1 seconds
Started Mar 17 01:03:22 PM PDT 24
Finished Mar 17 01:03:26 PM PDT 24
Peak memory 183460 kb
Host smart-5ae62c95-98c9-41f0-b4d2-0a6125f67ce5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284515961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.3284515961
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3438379850
Short name T526
Test name
Test status
Simulation time 37136144 ps
CPU time 0.96 seconds
Started Mar 17 01:03:15 PM PDT 24
Finished Mar 17 01:03:16 PM PDT 24
Peak memory 197228 kb
Host smart-50630d83-2dc5-45d9-bedb-982e2d87e67d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438379850 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3438379850
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.616248442
Short name T101
Test name
Test status
Simulation time 12714840 ps
CPU time 0.59 seconds
Started Mar 17 01:03:19 PM PDT 24
Finished Mar 17 01:03:21 PM PDT 24
Peak memory 182728 kb
Host smart-ade8374f-579c-4aa4-aec2-16dd5e3c768e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616248442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.616248442
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3273877136
Short name T490
Test name
Test status
Simulation time 14476659 ps
CPU time 0.54 seconds
Started Mar 17 01:03:17 PM PDT 24
Finished Mar 17 01:03:21 PM PDT 24
Peak memory 182100 kb
Host smart-30021fb3-b773-4360-82ac-79795edee7bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273877136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3273877136
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3646143233
Short name T96
Test name
Test status
Simulation time 44293360 ps
CPU time 0.69 seconds
Started Mar 17 01:03:17 PM PDT 24
Finished Mar 17 01:03:20 PM PDT 24
Peak memory 191728 kb
Host smart-539669ef-6251-43d8-8096-d1bbb7292dd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646143233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3646143233
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2039307725
Short name T462
Test name
Test status
Simulation time 44721189 ps
CPU time 1.04 seconds
Started Mar 17 01:03:15 PM PDT 24
Finished Mar 17 01:03:16 PM PDT 24
Peak memory 196412 kb
Host smart-acc97e90-8a41-480b-9300-94e2d6415111
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039307725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2039307725
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.346439184
Short name T32
Test name
Test status
Simulation time 107461126 ps
CPU time 0.83 seconds
Started Mar 17 01:03:19 PM PDT 24
Finished Mar 17 01:03:21 PM PDT 24
Peak memory 193872 kb
Host smart-a4013794-93ec-4d00-a8f9-03ac83b03a63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346439184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int
g_err.346439184
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2315054450
Short name T487
Test name
Test status
Simulation time 83511369 ps
CPU time 1 seconds
Started Mar 17 01:03:20 PM PDT 24
Finished Mar 17 01:03:22 PM PDT 24
Peak memory 197124 kb
Host smart-c2c033f8-7df5-4b49-b39e-ffd2caba080e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315054450 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2315054450
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3344829999
Short name T483
Test name
Test status
Simulation time 16360375 ps
CPU time 0.57 seconds
Started Mar 17 01:03:19 PM PDT 24
Finished Mar 17 01:03:21 PM PDT 24
Peak memory 182668 kb
Host smart-302e5196-772b-4726-97da-c759f3272af9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344829999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3344829999
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2008361010
Short name T470
Test name
Test status
Simulation time 12993637 ps
CPU time 0.55 seconds
Started Mar 17 01:03:16 PM PDT 24
Finished Mar 17 01:03:17 PM PDT 24
Peak memory 182720 kb
Host smart-b6aaf465-cabb-4505-a7b2-2669cc4149a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008361010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2008361010
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3730435358
Short name T549
Test name
Test status
Simulation time 55631780 ps
CPU time 0.66 seconds
Started Mar 17 01:03:15 PM PDT 24
Finished Mar 17 01:03:16 PM PDT 24
Peak memory 193216 kb
Host smart-86b22d4f-460b-4b22-855f-3cfa851ee8fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730435358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.3730435358
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2218311603
Short name T535
Test name
Test status
Simulation time 275651039 ps
CPU time 1.63 seconds
Started Mar 17 01:03:15 PM PDT 24
Finished Mar 17 01:03:17 PM PDT 24
Peak memory 197616 kb
Host smart-b0d99092-cac0-4d4c-ade1-bdfaa780d574
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218311603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2218311603
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1394465047
Short name T513
Test name
Test status
Simulation time 107699690 ps
CPU time 0.83 seconds
Started Mar 17 01:03:19 PM PDT 24
Finished Mar 17 01:03:21 PM PDT 24
Peak memory 191136 kb
Host smart-e62ae081-e585-4fc5-89e1-60e8770c4917
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394465047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1394465047
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3400466333
Short name T554
Test name
Test status
Simulation time 28119596 ps
CPU time 0.74 seconds
Started Mar 17 01:03:19 PM PDT 24
Finished Mar 17 01:03:21 PM PDT 24
Peak memory 194640 kb
Host smart-47d8f311-03dc-4dc1-8ccb-954c28205079
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400466333 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3400466333
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1874705506
Short name T482
Test name
Test status
Simulation time 13127056 ps
CPU time 0.61 seconds
Started Mar 17 01:03:18 PM PDT 24
Finished Mar 17 01:03:21 PM PDT 24
Peak memory 182676 kb
Host smart-f7c8fd61-e012-4d53-92c9-e2f08cb18e8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874705506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1874705506
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3069853678
Short name T517
Test name
Test status
Simulation time 15891254 ps
CPU time 0.55 seconds
Started Mar 17 01:03:16 PM PDT 24
Finished Mar 17 01:03:17 PM PDT 24
Peak memory 182524 kb
Host smart-ce2bfe47-1c80-4f69-a7a6-d76757eaeb87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069853678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3069853678
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.771325841
Short name T93
Test name
Test status
Simulation time 12447788 ps
CPU time 0.61 seconds
Started Mar 17 01:03:20 PM PDT 24
Finished Mar 17 01:03:21 PM PDT 24
Peak memory 191948 kb
Host smart-46bbe7b1-95f7-463d-a54a-bbe18086d2c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771325841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_tim
er_same_csr_outstanding.771325841
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2590878059
Short name T520
Test name
Test status
Simulation time 35682686 ps
CPU time 1.08 seconds
Started Mar 17 01:03:28 PM PDT 24
Finished Mar 17 01:03:31 PM PDT 24
Peak memory 197392 kb
Host smart-dc163566-c0a0-4877-ae83-0e8ed8e0476a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590878059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2590878059
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.4122235366
Short name T553
Test name
Test status
Simulation time 349264033 ps
CPU time 0.75 seconds
Started Mar 17 01:03:15 PM PDT 24
Finished Mar 17 01:03:16 PM PDT 24
Peak memory 182880 kb
Host smart-0d21a260-123e-4e71-8dd5-57c088945294
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122235366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.4122235366
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1291722337
Short name T287
Test name
Test status
Simulation time 280312405774 ps
CPU time 469.53 seconds
Started Mar 17 12:27:57 PM PDT 24
Finished Mar 17 12:35:48 PM PDT 24
Peak memory 182168 kb
Host smart-968e262c-0037-4837-8948-b19880869d43
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291722337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1291722337
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3343984213
Short name T21
Test name
Test status
Simulation time 248955034573 ps
CPU time 191.3 seconds
Started Mar 17 12:27:31 PM PDT 24
Finished Mar 17 12:30:43 PM PDT 24
Peak memory 182460 kb
Host smart-a3610f9c-c5cd-44e2-beec-6659b4a3c0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343984213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3343984213
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2175909431
Short name T408
Test name
Test status
Simulation time 7845499070 ps
CPU time 16.18 seconds
Started Mar 17 12:23:59 PM PDT 24
Finished Mar 17 12:24:15 PM PDT 24
Peak memory 182644 kb
Host smart-ebdd0808-0740-48c9-a208-223634c7093e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175909431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2175909431
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.421466064
Short name T384
Test name
Test status
Simulation time 147034915973 ps
CPU time 152.9 seconds
Started Mar 17 12:23:57 PM PDT 24
Finished Mar 17 12:26:30 PM PDT 24
Peak memory 182564 kb
Host smart-9807722f-29c6-4646-8c7a-07715f2bcc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421466064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.421466064
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.4224814517
Short name T217
Test name
Test status
Simulation time 18158790643 ps
CPU time 95.83 seconds
Started Mar 17 12:26:06 PM PDT 24
Finished Mar 17 12:27:42 PM PDT 24
Peak memory 182520 kb
Host smart-6f34c5b4-845d-4490-83dd-81166486ff7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224814517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.4224814517
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.374018056
Short name T18
Test name
Test status
Simulation time 323504094 ps
CPU time 0.99 seconds
Started Mar 17 12:24:23 PM PDT 24
Finished Mar 17 12:24:25 PM PDT 24
Peak memory 214084 kb
Host smart-b4c65d42-0057-4276-937c-968cf46f558c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374018056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.374018056
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1520622493
Short name T416
Test name
Test status
Simulation time 780083585078 ps
CPU time 625.96 seconds
Started Mar 17 12:26:53 PM PDT 24
Finished Mar 17 12:37:19 PM PDT 24
Peak memory 189492 kb
Host smart-7b213505-0655-4f3a-9cab-1ebdc3bd5fd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520622493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1520622493
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.4236357801
Short name T412
Test name
Test status
Simulation time 53414289207 ps
CPU time 31.71 seconds
Started Mar 17 12:29:09 PM PDT 24
Finished Mar 17 12:29:41 PM PDT 24
Peak memory 182656 kb
Host smart-124a6bb1-2c0e-482b-8017-dc07b9536692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236357801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.4236357801
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.418441751
Short name T155
Test name
Test status
Simulation time 46939165053 ps
CPU time 148.91 seconds
Started Mar 17 12:29:13 PM PDT 24
Finished Mar 17 12:31:42 PM PDT 24
Peak memory 190672 kb
Host smart-fb12f3dc-b15e-4389-8590-e399e27ae8a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418441751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.418441751
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1118505548
Short name T449
Test name
Test status
Simulation time 42724799 ps
CPU time 0.55 seconds
Started Mar 17 12:29:09 PM PDT 24
Finished Mar 17 12:29:09 PM PDT 24
Peak memory 182340 kb
Host smart-c3dcfc3a-febc-4562-8225-7795643afa08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118505548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1118505548
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.2111526421
Short name T37
Test name
Test status
Simulation time 18491752042 ps
CPU time 135.41 seconds
Started Mar 17 12:29:12 PM PDT 24
Finished Mar 17 12:31:28 PM PDT 24
Peak memory 197180 kb
Host smart-3d8240da-e6d5-4c3c-a264-4c96b1daef49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111526421 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.2111526421
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/102.rv_timer_random.4247887571
Short name T450
Test name
Test status
Simulation time 333424689170 ps
CPU time 1097.95 seconds
Started Mar 17 12:31:37 PM PDT 24
Finished Mar 17 12:49:55 PM PDT 24
Peak memory 190668 kb
Host smart-f8b2c50f-77a0-4705-9f66-3a08f67a5a49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247887571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.4247887571
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.1512593349
Short name T192
Test name
Test status
Simulation time 412663323021 ps
CPU time 499.75 seconds
Started Mar 17 12:31:28 PM PDT 24
Finished Mar 17 12:39:49 PM PDT 24
Peak memory 190748 kb
Host smart-7d658f53-fe81-4123-8916-ec3a63a1c30b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512593349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1512593349
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.210052723
Short name T276
Test name
Test status
Simulation time 237792354923 ps
CPU time 91.19 seconds
Started Mar 17 12:31:28 PM PDT 24
Finished Mar 17 12:33:01 PM PDT 24
Peak memory 193984 kb
Host smart-f57bfe87-5f0f-4b1f-9f46-2356269815df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210052723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.210052723
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2569604129
Short name T279
Test name
Test status
Simulation time 68673817323 ps
CPU time 192.88 seconds
Started Mar 17 12:31:29 PM PDT 24
Finished Mar 17 12:34:43 PM PDT 24
Peak memory 182484 kb
Host smart-f2c6a67d-5208-4513-b677-686be2e9ed11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569604129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2569604129
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1084008197
Short name T5
Test name
Test status
Simulation time 76350032718 ps
CPU time 157.5 seconds
Started Mar 17 12:31:37 PM PDT 24
Finished Mar 17 12:34:14 PM PDT 24
Peak memory 190724 kb
Host smart-72b9a9c7-5edf-442b-8aa4-1fdd6ab6a6a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084008197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1084008197
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.3496229276
Short name T357
Test name
Test status
Simulation time 128735075943 ps
CPU time 132.22 seconds
Started Mar 17 12:31:38 PM PDT 24
Finished Mar 17 12:33:50 PM PDT 24
Peak memory 182460 kb
Host smart-7108c51a-e91f-4127-998b-cdb8f8909d48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496229276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3496229276
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2855190422
Short name T296
Test name
Test status
Simulation time 642005630735 ps
CPU time 489.03 seconds
Started Mar 17 12:29:12 PM PDT 24
Finished Mar 17 12:37:21 PM PDT 24
Peak memory 182504 kb
Host smart-b2edcfa0-48d8-4f4f-92e9-3c02958f1f8c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855190422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2855190422
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.970732447
Short name T374
Test name
Test status
Simulation time 46713978033 ps
CPU time 37.21 seconds
Started Mar 17 12:29:09 PM PDT 24
Finished Mar 17 12:29:46 PM PDT 24
Peak memory 182476 kb
Host smart-bd9f126b-a285-49b9-9ff2-9ebcddbfcf0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970732447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.970732447
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.933884131
Short name T122
Test name
Test status
Simulation time 135492117152 ps
CPU time 95.55 seconds
Started Mar 17 12:29:08 PM PDT 24
Finished Mar 17 12:30:43 PM PDT 24
Peak memory 182504 kb
Host smart-9de76db4-c6ac-4270-8c5b-b7c404291bd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933884131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.933884131
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1265348859
Short name T210
Test name
Test status
Simulation time 197414947041 ps
CPU time 85.23 seconds
Started Mar 17 12:29:11 PM PDT 24
Finished Mar 17 12:30:36 PM PDT 24
Peak memory 182500 kb
Host smart-323dd341-9d2f-4ca4-a117-43f1e1095bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265348859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1265348859
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.1982493968
Short name T115
Test name
Test status
Simulation time 461540401076 ps
CPU time 929.97 seconds
Started Mar 17 12:31:43 PM PDT 24
Finished Mar 17 12:47:13 PM PDT 24
Peak memory 193140 kb
Host smart-59540261-accf-4cb7-8627-4978101fefc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982493968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1982493968
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.2460492627
Short name T109
Test name
Test status
Simulation time 487202447970 ps
CPU time 232.86 seconds
Started Mar 17 12:31:45 PM PDT 24
Finished Mar 17 12:35:38 PM PDT 24
Peak memory 190740 kb
Host smart-9b47f7ea-7fdd-411f-b60b-91b0c22d7c7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460492627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2460492627
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3559326245
Short name T303
Test name
Test status
Simulation time 840558655889 ps
CPU time 2123.16 seconds
Started Mar 17 12:31:45 PM PDT 24
Finished Mar 17 01:07:08 PM PDT 24
Peak memory 190776 kb
Host smart-8f28bf06-1790-4145-817a-491326dee64c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559326245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3559326245
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1871972678
Short name T253
Test name
Test status
Simulation time 336446663756 ps
CPU time 333.71 seconds
Started Mar 17 12:31:45 PM PDT 24
Finished Mar 17 12:37:19 PM PDT 24
Peak memory 190740 kb
Host smart-0fcbef56-c57a-44cf-a86e-12d1cfa24e8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871972678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1871972678
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.2043929163
Short name T263
Test name
Test status
Simulation time 56106032399 ps
CPU time 99.43 seconds
Started Mar 17 12:31:44 PM PDT 24
Finished Mar 17 12:33:24 PM PDT 24
Peak memory 190748 kb
Host smart-8a38365f-6415-4ab3-8e06-c5738e62ace3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043929163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2043929163
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.2070218242
Short name T339
Test name
Test status
Simulation time 82397261650 ps
CPU time 114.73 seconds
Started Mar 17 12:29:16 PM PDT 24
Finished Mar 17 12:31:10 PM PDT 24
Peak memory 182556 kb
Host smart-20546be5-da3b-4a9b-b7d0-f89d46995aaa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070218242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.2070218242
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3335546929
Short name T390
Test name
Test status
Simulation time 105207280477 ps
CPU time 161.73 seconds
Started Mar 17 12:29:16 PM PDT 24
Finished Mar 17 12:31:58 PM PDT 24
Peak memory 182540 kb
Host smart-29fe56ac-2d60-4051-9747-fddc69f5a1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335546929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3335546929
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.1742519471
Short name T61
Test name
Test status
Simulation time 42204578679 ps
CPU time 28.97 seconds
Started Mar 17 12:29:35 PM PDT 24
Finished Mar 17 12:30:04 PM PDT 24
Peak memory 182416 kb
Host smart-54bbdb4b-ef41-4e39-ab43-65888050c1be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742519471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1742519471
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.3843376604
Short name T340
Test name
Test status
Simulation time 31912638986 ps
CPU time 225.16 seconds
Started Mar 17 12:29:15 PM PDT 24
Finished Mar 17 12:33:00 PM PDT 24
Peak memory 197204 kb
Host smart-2470d492-155c-4a72-bd3b-9387789bc0d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843376604 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.3843376604
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.1779421505
Short name T143
Test name
Test status
Simulation time 13261194225 ps
CPU time 6.98 seconds
Started Mar 17 12:31:44 PM PDT 24
Finished Mar 17 12:31:51 PM PDT 24
Peak memory 182624 kb
Host smart-cf973555-42eb-43cf-9255-1fa0ab58aabb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779421505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1779421505
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.3504237281
Short name T156
Test name
Test status
Simulation time 128997125395 ps
CPU time 329.34 seconds
Started Mar 17 12:31:46 PM PDT 24
Finished Mar 17 12:37:15 PM PDT 24
Peak memory 194168 kb
Host smart-a501407e-f362-4b7b-926d-1b770d88de4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504237281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3504237281
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.81949314
Short name T146
Test name
Test status
Simulation time 397910229723 ps
CPU time 186.28 seconds
Started Mar 17 12:31:45 PM PDT 24
Finished Mar 17 12:34:52 PM PDT 24
Peak memory 190780 kb
Host smart-d4c03983-0546-4180-bf4f-ba3b12a8e63e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81949314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.81949314
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.993832916
Short name T283
Test name
Test status
Simulation time 125729426591 ps
CPU time 136.49 seconds
Started Mar 17 12:31:51 PM PDT 24
Finished Mar 17 12:34:07 PM PDT 24
Peak memory 190772 kb
Host smart-34390be3-90a9-4c90-968b-daa54a9a7e77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993832916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.993832916
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.1460460128
Short name T317
Test name
Test status
Simulation time 53036701079 ps
CPU time 120.26 seconds
Started Mar 17 12:31:50 PM PDT 24
Finished Mar 17 12:33:50 PM PDT 24
Peak memory 190752 kb
Host smart-7ed39578-f40d-41be-a0dd-627425dc745b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460460128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1460460128
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3175444262
Short name T125
Test name
Test status
Simulation time 1249930170494 ps
CPU time 463.21 seconds
Started Mar 17 12:31:52 PM PDT 24
Finished Mar 17 12:39:35 PM PDT 24
Peak memory 190748 kb
Host smart-65740813-2e15-4a2d-b329-21dade69bcc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175444262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3175444262
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1597557612
Short name T111
Test name
Test status
Simulation time 52550124039 ps
CPU time 90.87 seconds
Started Mar 17 12:31:52 PM PDT 24
Finished Mar 17 12:33:23 PM PDT 24
Peak memory 182600 kb
Host smart-3d602877-4af9-4cec-9bf1-a3ef8fde2f45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597557612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1597557612
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.2530507310
Short name T185
Test name
Test status
Simulation time 84267203684 ps
CPU time 137.84 seconds
Started Mar 17 12:31:51 PM PDT 24
Finished Mar 17 12:34:09 PM PDT 24
Peak memory 190716 kb
Host smart-2d2c3991-20d0-49c4-88d9-424d477111ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530507310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2530507310
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2878852540
Short name T389
Test name
Test status
Simulation time 30359856988 ps
CPU time 10.53 seconds
Started Mar 17 12:29:24 PM PDT 24
Finished Mar 17 12:29:35 PM PDT 24
Peak memory 182524 kb
Host smart-794c7729-62c2-4a21-ac8a-0d22dcfecf94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878852540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2878852540
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.614107289
Short name T294
Test name
Test status
Simulation time 347577387698 ps
CPU time 169.13 seconds
Started Mar 17 12:29:15 PM PDT 24
Finished Mar 17 12:32:04 PM PDT 24
Peak memory 190652 kb
Host smart-dd419d5e-167c-4ad5-bead-32e5194033fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614107289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.614107289
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2156624332
Short name T426
Test name
Test status
Simulation time 35396981778 ps
CPU time 318.73 seconds
Started Mar 17 12:29:24 PM PDT 24
Finished Mar 17 12:34:43 PM PDT 24
Peak memory 182508 kb
Host smart-fdfa7a55-7f18-4441-9731-14b9e944e5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156624332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2156624332
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.2327357063
Short name T163
Test name
Test status
Simulation time 502787226527 ps
CPU time 406.5 seconds
Started Mar 17 12:29:15 PM PDT 24
Finished Mar 17 12:36:01 PM PDT 24
Peak memory 190752 kb
Host smart-59a0672d-7652-4401-a980-74643d763ac7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327357063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.2327357063
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/131.rv_timer_random.2207822821
Short name T266
Test name
Test status
Simulation time 115484934238 ps
CPU time 771.63 seconds
Started Mar 17 12:31:51 PM PDT 24
Finished Mar 17 12:44:42 PM PDT 24
Peak memory 190752 kb
Host smart-11a0c80e-aeee-4eba-bd15-505d0154a917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207822821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2207822821
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.3469833541
Short name T291
Test name
Test status
Simulation time 109281996716 ps
CPU time 282.48 seconds
Started Mar 17 12:31:51 PM PDT 24
Finished Mar 17 12:36:34 PM PDT 24
Peak memory 190668 kb
Host smart-e6831257-b3eb-4b48-9995-2e300a2baac4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469833541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3469833541
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3495765656
Short name T174
Test name
Test status
Simulation time 91424718036 ps
CPU time 2328.95 seconds
Started Mar 17 12:31:56 PM PDT 24
Finished Mar 17 01:10:45 PM PDT 24
Peak memory 190676 kb
Host smart-a9ddc9f9-4cf8-4d9d-92a8-4f5cbe0753e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495765656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3495765656
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.2770106865
Short name T201
Test name
Test status
Simulation time 108639828950 ps
CPU time 163.01 seconds
Started Mar 17 12:31:51 PM PDT 24
Finished Mar 17 12:34:34 PM PDT 24
Peak memory 190716 kb
Host smart-44170f70-701d-4629-9a73-28e0b7a259a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770106865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.2770106865
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.686172237
Short name T332
Test name
Test status
Simulation time 392886704805 ps
CPU time 373.56 seconds
Started Mar 17 12:31:52 PM PDT 24
Finished Mar 17 12:38:06 PM PDT 24
Peak memory 190764 kb
Host smart-31998b6c-dd95-414c-b3e6-4416d700bf49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686172237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.686172237
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1284613283
Short name T314
Test name
Test status
Simulation time 31799230414 ps
CPU time 70.36 seconds
Started Mar 17 12:31:51 PM PDT 24
Finished Mar 17 12:33:02 PM PDT 24
Peak memory 190704 kb
Host smart-a4182b9b-1921-4c2b-b163-e585d37decd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284613283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1284613283
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.247852753
Short name T354
Test name
Test status
Simulation time 48599257053 ps
CPU time 492.34 seconds
Started Mar 17 12:31:51 PM PDT 24
Finished Mar 17 12:40:03 PM PDT 24
Peak memory 191788 kb
Host smart-7f6002a0-458c-4551-82b8-8575ba7398d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247852753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.247852753
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.300164645
Short name T373
Test name
Test status
Simulation time 81054213114 ps
CPU time 122.59 seconds
Started Mar 17 12:29:15 PM PDT 24
Finished Mar 17 12:31:18 PM PDT 24
Peak memory 182560 kb
Host smart-143020a4-f811-4fba-bd15-dde8ef148f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300164645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.300164645
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.3181023414
Short name T415
Test name
Test status
Simulation time 77157678025 ps
CPU time 40.17 seconds
Started Mar 17 12:29:17 PM PDT 24
Finished Mar 17 12:29:58 PM PDT 24
Peak memory 182608 kb
Host smart-4a482dc4-bbc6-4a96-960d-3865ceffd35b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181023414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3181023414
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3812088611
Short name T300
Test name
Test status
Simulation time 769375726219 ps
CPU time 232.2 seconds
Started Mar 17 12:31:57 PM PDT 24
Finished Mar 17 12:35:50 PM PDT 24
Peak memory 190736 kb
Host smart-352aa546-6205-4e21-9174-1db49dd4f8d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812088611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3812088611
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.731033606
Short name T169
Test name
Test status
Simulation time 120127467309 ps
CPU time 329.06 seconds
Started Mar 17 12:31:57 PM PDT 24
Finished Mar 17 12:37:26 PM PDT 24
Peak memory 190652 kb
Host smart-dd432d92-d3d0-4ee3-ba40-a0820ffd0fda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731033606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.731033606
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3288224252
Short name T65
Test name
Test status
Simulation time 113918915186 ps
CPU time 408.51 seconds
Started Mar 17 12:31:59 PM PDT 24
Finished Mar 17 12:38:48 PM PDT 24
Peak memory 194104 kb
Host smart-65dbf3a7-276e-47af-b98c-019df9d349b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288224252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3288224252
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.919582294
Short name T362
Test name
Test status
Simulation time 6823933699 ps
CPU time 5.63 seconds
Started Mar 17 12:31:56 PM PDT 24
Finished Mar 17 12:32:02 PM PDT 24
Peak memory 182540 kb
Host smart-0ed2c888-24e6-40fc-a4d4-50cd75495c7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919582294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.919582294
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.90214952
Short name T348
Test name
Test status
Simulation time 1025482965117 ps
CPU time 515.84 seconds
Started Mar 17 12:29:31 PM PDT 24
Finished Mar 17 12:38:07 PM PDT 24
Peak memory 182556 kb
Host smart-bae2c84d-f1c0-4515-8ff9-e1b95bb121b4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90214952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.rv_timer_cfg_update_on_fly.90214952
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_random.3408986294
Short name T215
Test name
Test status
Simulation time 120995926933 ps
CPU time 1776.5 seconds
Started Mar 17 12:29:15 PM PDT 24
Finished Mar 17 12:58:52 PM PDT 24
Peak memory 193048 kb
Host smart-7765cb6e-95a9-4e0e-aa6a-528a6e75d23a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408986294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3408986294
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.3039704230
Short name T341
Test name
Test status
Simulation time 21495668108 ps
CPU time 36.41 seconds
Started Mar 17 12:32:00 PM PDT 24
Finished Mar 17 12:32:36 PM PDT 24
Peak memory 192704 kb
Host smart-58de792f-86ee-4aa3-a5fd-514b2d67109a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039704230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3039704230
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.1440941832
Short name T7
Test name
Test status
Simulation time 81457732718 ps
CPU time 52.39 seconds
Started Mar 17 12:31:59 PM PDT 24
Finished Mar 17 12:32:52 PM PDT 24
Peak memory 182556 kb
Host smart-cef13d76-383e-45ef-b4d5-16b8d87dfb1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440941832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1440941832
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.1319348488
Short name T452
Test name
Test status
Simulation time 629907152192 ps
CPU time 178.93 seconds
Started Mar 17 12:32:06 PM PDT 24
Finished Mar 17 12:35:05 PM PDT 24
Peak memory 190756 kb
Host smart-53c20192-c1a0-4aed-9e83-ad718796bc4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319348488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1319348488
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1466400508
Short name T151
Test name
Test status
Simulation time 118984235732 ps
CPU time 207.27 seconds
Started Mar 17 12:32:06 PM PDT 24
Finished Mar 17 12:35:33 PM PDT 24
Peak memory 182508 kb
Host smart-773ce073-7cd0-49cb-b8b9-c8985496f367
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466400508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1466400508
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3864401302
Short name T69
Test name
Test status
Simulation time 53950387659 ps
CPU time 109.54 seconds
Started Mar 17 12:32:04 PM PDT 24
Finished Mar 17 12:33:53 PM PDT 24
Peak memory 190780 kb
Host smart-6c18b082-9d8a-4dd6-8ebb-0f88bf4e8d13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864401302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3864401302
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3923298329
Short name T285
Test name
Test status
Simulation time 205254003814 ps
CPU time 274.58 seconds
Started Mar 17 12:32:04 PM PDT 24
Finished Mar 17 12:36:39 PM PDT 24
Peak memory 190764 kb
Host smart-72468e6b-9f51-42ca-a912-8c31883accd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923298329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3923298329
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2686889935
Short name T414
Test name
Test status
Simulation time 121285081603 ps
CPU time 167.18 seconds
Started Mar 17 12:29:32 PM PDT 24
Finished Mar 17 12:32:19 PM PDT 24
Peak memory 182544 kb
Host smart-ebcc6a6c-9318-45d4-bf96-425ac283d889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686889935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2686889935
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.3039446534
Short name T442
Test name
Test status
Simulation time 77350389692 ps
CPU time 66.27 seconds
Started Mar 17 12:29:29 PM PDT 24
Finished Mar 17 12:30:36 PM PDT 24
Peak memory 182536 kb
Host smart-3631a83e-f972-4257-b893-48533ca5988a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039446534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3039446534
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.3047710177
Short name T211
Test name
Test status
Simulation time 560445745054 ps
CPU time 168.3 seconds
Started Mar 17 12:29:36 PM PDT 24
Finished Mar 17 12:32:25 PM PDT 24
Peak memory 190652 kb
Host smart-91208ef6-8934-45fe-9179-c0f65b526767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047710177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.3047710177
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.3274220869
Short name T23
Test name
Test status
Simulation time 41924799475 ps
CPU time 401.65 seconds
Started Mar 17 12:29:26 PM PDT 24
Finished Mar 17 12:36:08 PM PDT 24
Peak memory 197216 kb
Host smart-84aa7a1c-d1c6-4218-a970-b09096ae7090
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274220869 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.3274220869
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.2197241515
Short name T292
Test name
Test status
Simulation time 9578290874 ps
CPU time 14.67 seconds
Started Mar 17 12:32:05 PM PDT 24
Finished Mar 17 12:32:20 PM PDT 24
Peak memory 182528 kb
Host smart-0a3c6adb-a476-4f20-b8fe-7f44f7009f7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197241515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.2197241515
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.1509815207
Short name T152
Test name
Test status
Simulation time 531769887892 ps
CPU time 488.79 seconds
Started Mar 17 12:32:06 PM PDT 24
Finished Mar 17 12:40:15 PM PDT 24
Peak memory 190644 kb
Host smart-c9d75692-3101-4799-b90d-5be35a6d2ee3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509815207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1509815207
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.3493042708
Short name T238
Test name
Test status
Simulation time 219883713262 ps
CPU time 108.9 seconds
Started Mar 17 12:32:12 PM PDT 24
Finished Mar 17 12:34:01 PM PDT 24
Peak memory 182524 kb
Host smart-cbc26dab-3a51-47f7-9148-decd172830a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493042708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3493042708
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.2080935104
Short name T307
Test name
Test status
Simulation time 165728313711 ps
CPU time 393.55 seconds
Started Mar 17 12:32:11 PM PDT 24
Finished Mar 17 12:38:45 PM PDT 24
Peak memory 190668 kb
Host smart-8880d0d0-606d-486b-afa7-97cfa737589a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080935104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2080935104
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.888602234
Short name T66
Test name
Test status
Simulation time 680976191692 ps
CPU time 231.01 seconds
Started Mar 17 12:32:13 PM PDT 24
Finished Mar 17 12:36:04 PM PDT 24
Peak memory 190740 kb
Host smart-10d425d0-fc56-4651-a00c-8e6378323f2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888602234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.888602234
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2919905841
Short name T191
Test name
Test status
Simulation time 42332137861 ps
CPU time 65.57 seconds
Started Mar 17 12:32:10 PM PDT 24
Finished Mar 17 12:33:16 PM PDT 24
Peak memory 193664 kb
Host smart-d9930569-2520-44dc-aeed-8007909c0785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919905841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2919905841
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.2715085654
Short name T147
Test name
Test status
Simulation time 527590512509 ps
CPU time 628.69 seconds
Started Mar 17 12:32:13 PM PDT 24
Finished Mar 17 12:42:42 PM PDT 24
Peak memory 194568 kb
Host smart-c076841a-d07f-4ad5-baf1-7bfeb1addac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715085654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2715085654
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.2577802468
Short name T256
Test name
Test status
Simulation time 436950983668 ps
CPU time 1591.16 seconds
Started Mar 17 12:32:11 PM PDT 24
Finished Mar 17 12:58:43 PM PDT 24
Peak memory 193272 kb
Host smart-05a6dcb1-5d17-4cb6-8389-a39d41914562
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577802468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2577802468
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3829457409
Short name T272
Test name
Test status
Simulation time 511219812361 ps
CPU time 228.27 seconds
Started Mar 17 12:29:29 PM PDT 24
Finished Mar 17 12:33:18 PM PDT 24
Peak memory 182476 kb
Host smart-6cadf0c3-7049-44ce-a37a-5ac2f3b9766a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829457409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3829457409
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.509952767
Short name T378
Test name
Test status
Simulation time 37976145263 ps
CPU time 50.69 seconds
Started Mar 17 12:30:03 PM PDT 24
Finished Mar 17 12:30:55 PM PDT 24
Peak memory 182564 kb
Host smart-1828e9e0-1935-4a26-86f2-5bdc6e783437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509952767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.509952767
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.4000939017
Short name T293
Test name
Test status
Simulation time 1283958200509 ps
CPU time 1165.28 seconds
Started Mar 17 12:31:34 PM PDT 24
Finished Mar 17 12:51:00 PM PDT 24
Peak memory 190396 kb
Host smart-18290327-0f36-4c81-985c-3590f2b60e9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000939017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.4000939017
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.2727537004
Short name T407
Test name
Test status
Simulation time 306844253 ps
CPU time 0.98 seconds
Started Mar 17 12:29:29 PM PDT 24
Finished Mar 17 12:29:31 PM PDT 24
Peak memory 190964 kb
Host smart-f5096a22-9887-4afb-ac4c-5eb065d808d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727537004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2727537004
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/171.rv_timer_random.923124785
Short name T277
Test name
Test status
Simulation time 413932909414 ps
CPU time 1222.96 seconds
Started Mar 17 12:32:18 PM PDT 24
Finished Mar 17 12:52:41 PM PDT 24
Peak memory 190672 kb
Host smart-fdacaf41-308b-4e6f-b15b-42ebc3599dd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923124785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.923124785
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.433167781
Short name T138
Test name
Test status
Simulation time 82681388755 ps
CPU time 288.61 seconds
Started Mar 17 12:32:18 PM PDT 24
Finished Mar 17 12:37:08 PM PDT 24
Peak memory 191896 kb
Host smart-040b5463-c5b7-4a18-b462-1574b0e6fb26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433167781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.433167781
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.50275994
Short name T337
Test name
Test status
Simulation time 86457711683 ps
CPU time 558.93 seconds
Started Mar 17 12:32:18 PM PDT 24
Finished Mar 17 12:41:38 PM PDT 24
Peak memory 182484 kb
Host smart-8c5e7f62-b9d6-4e3e-b985-000d6f4b895c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50275994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.50275994
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2416722148
Short name T167
Test name
Test status
Simulation time 102881616972 ps
CPU time 673.97 seconds
Started Mar 17 12:32:19 PM PDT 24
Finished Mar 17 12:43:33 PM PDT 24
Peak memory 190728 kb
Host smart-ab11efcd-f457-4a6f-bae0-03e571810105
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416722148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2416722148
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.707967852
Short name T127
Test name
Test status
Simulation time 74215940613 ps
CPU time 70.18 seconds
Started Mar 17 12:32:24 PM PDT 24
Finished Mar 17 12:33:36 PM PDT 24
Peak memory 190768 kb
Host smart-8ba9feb2-9981-4412-b7f9-12e585febad9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707967852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.707967852
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.1176011367
Short name T324
Test name
Test status
Simulation time 1218531037182 ps
CPU time 455.79 seconds
Started Mar 17 12:29:23 PM PDT 24
Finished Mar 17 12:36:59 PM PDT 24
Peak memory 182476 kb
Host smart-e28836b5-5a59-4d49-8b06-8dc1dbbb085b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176011367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.1176011367
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1327596194
Short name T392
Test name
Test status
Simulation time 182345095016 ps
CPU time 72.59 seconds
Started Mar 17 12:29:31 PM PDT 24
Finished Mar 17 12:30:44 PM PDT 24
Peak memory 182592 kb
Host smart-3c3ef1ab-0868-41a7-8e4d-153cb4e8b40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327596194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1327596194
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.1656015841
Short name T284
Test name
Test status
Simulation time 1566033337100 ps
CPU time 1006.38 seconds
Started Mar 17 12:29:28 PM PDT 24
Finished Mar 17 12:46:15 PM PDT 24
Peak memory 190724 kb
Host smart-33a995bf-dc42-4d75-af57-3cf6e3954605
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656015841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1656015841
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1315341341
Short name T289
Test name
Test status
Simulation time 3152109316 ps
CPU time 2.25 seconds
Started Mar 17 12:31:05 PM PDT 24
Finished Mar 17 12:31:08 PM PDT 24
Peak memory 180352 kb
Host smart-423e3eb4-71c2-4241-8662-7fcadaddc446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315341341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1315341341
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1222955656
Short name T60
Test name
Test status
Simulation time 137956899657 ps
CPU time 256.61 seconds
Started Mar 17 12:29:35 PM PDT 24
Finished Mar 17 12:33:52 PM PDT 24
Peak memory 190688 kb
Host smart-42779830-46d5-40d4-b997-fd557e6f6405
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222955656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1222955656
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.756477204
Short name T14
Test name
Test status
Simulation time 80515853728 ps
CPU time 659.9 seconds
Started Mar 17 12:29:22 PM PDT 24
Finished Mar 17 12:40:23 PM PDT 24
Peak memory 206656 kb
Host smart-0ab69a60-ec09-4276-950d-601ce06e1010
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756477204 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.756477204
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/182.rv_timer_random.462674945
Short name T135
Test name
Test status
Simulation time 241147679592 ps
CPU time 117.87 seconds
Started Mar 17 12:32:26 PM PDT 24
Finished Mar 17 12:34:24 PM PDT 24
Peak memory 190716 kb
Host smart-85ce5c44-4968-4e59-a2cf-96eea87be2fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462674945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.462674945
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3612070462
Short name T224
Test name
Test status
Simulation time 172587638083 ps
CPU time 601.79 seconds
Started Mar 17 12:32:24 PM PDT 24
Finished Mar 17 12:42:28 PM PDT 24
Peak memory 190828 kb
Host smart-3533963b-5adc-4f7a-be9e-a54f2f875f13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612070462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3612070462
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.3886386704
Short name T399
Test name
Test status
Simulation time 344652166556 ps
CPU time 1070.19 seconds
Started Mar 17 12:32:25 PM PDT 24
Finished Mar 17 12:50:16 PM PDT 24
Peak memory 190736 kb
Host smart-7f2ecf19-5582-4a7a-ba65-3197dcd273cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886386704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3886386704
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2670247806
Short name T79
Test name
Test status
Simulation time 25115534860 ps
CPU time 46.61 seconds
Started Mar 17 12:32:25 PM PDT 24
Finished Mar 17 12:33:13 PM PDT 24
Peak memory 190640 kb
Host smart-6f7eeb44-914f-45e1-87f3-7f46c74cec4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670247806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2670247806
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3762312831
Short name T299
Test name
Test status
Simulation time 218589672733 ps
CPU time 58.82 seconds
Started Mar 17 12:32:28 PM PDT 24
Finished Mar 17 12:33:27 PM PDT 24
Peak memory 182548 kb
Host smart-b68bf101-5281-4378-9816-471e9e0364d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762312831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3762312831
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2208944433
Short name T269
Test name
Test status
Simulation time 249855721646 ps
CPU time 280.49 seconds
Started Mar 17 12:32:33 PM PDT 24
Finished Mar 17 12:37:13 PM PDT 24
Peak memory 182540 kb
Host smart-f79a5c2a-ea25-4ec4-a912-336c74440f79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208944433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2208944433
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2209185331
Short name T137
Test name
Test status
Simulation time 217167789978 ps
CPU time 387.99 seconds
Started Mar 17 12:29:36 PM PDT 24
Finished Mar 17 12:36:04 PM PDT 24
Peak memory 182560 kb
Host smart-be2b0389-74bb-4d7c-9380-0af4d2e80e2a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209185331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2209185331
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.164651299
Short name T429
Test name
Test status
Simulation time 69391154375 ps
CPU time 10.22 seconds
Started Mar 17 12:29:35 PM PDT 24
Finished Mar 17 12:29:46 PM PDT 24
Peak memory 182576 kb
Host smart-8fa9a730-9b86-416c-afe7-d6997fdc0654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164651299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.164651299
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.1287735294
Short name T179
Test name
Test status
Simulation time 1005943982461 ps
CPU time 517.37 seconds
Started Mar 17 12:29:32 PM PDT 24
Finished Mar 17 12:38:09 PM PDT 24
Peak memory 190764 kb
Host smart-61a245b0-401f-4558-8f52-eee49ebf1a6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287735294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1287735294
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3951314122
Short name T395
Test name
Test status
Simulation time 845558167813 ps
CPU time 278.2 seconds
Started Mar 17 12:29:36 PM PDT 24
Finished Mar 17 12:34:14 PM PDT 24
Peak memory 195124 kb
Host smart-981a701d-6639-4c31-980f-d5178d14d689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951314122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3951314122
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.2898926397
Short name T268
Test name
Test status
Simulation time 342085795312 ps
CPU time 783.86 seconds
Started Mar 17 12:32:32 PM PDT 24
Finished Mar 17 12:45:36 PM PDT 24
Peak memory 190788 kb
Host smart-f477a457-7e32-4319-8977-0fe39681b47f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898926397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2898926397
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.202140596
Short name T113
Test name
Test status
Simulation time 78920618139 ps
CPU time 50.37 seconds
Started Mar 17 12:32:32 PM PDT 24
Finished Mar 17 12:33:23 PM PDT 24
Peak memory 182540 kb
Host smart-0b72acdd-41cb-4760-86f4-709a5de75dea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202140596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.202140596
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.4196925713
Short name T171
Test name
Test status
Simulation time 128532630972 ps
CPU time 1407.73 seconds
Started Mar 17 12:32:34 PM PDT 24
Finished Mar 17 12:56:02 PM PDT 24
Peak memory 190724 kb
Host smart-069d6017-0f81-47d6-b016-57af348e8afa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196925713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.4196925713
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.2447802455
Short name T347
Test name
Test status
Simulation time 185818977889 ps
CPU time 145.78 seconds
Started Mar 17 12:32:40 PM PDT 24
Finished Mar 17 12:35:07 PM PDT 24
Peak memory 190680 kb
Host smart-de739c03-8e43-423e-8260-b96f67ace03a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447802455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2447802455
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.1506664215
Short name T231
Test name
Test status
Simulation time 217153024524 ps
CPU time 89.96 seconds
Started Mar 17 12:32:41 PM PDT 24
Finished Mar 17 12:34:11 PM PDT 24
Peak memory 192944 kb
Host smart-35081e07-4f83-4a06-8266-0be14030bc01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506664215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1506664215
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3196899197
Short name T213
Test name
Test status
Simulation time 333504916639 ps
CPU time 465.88 seconds
Started Mar 17 12:32:41 PM PDT 24
Finished Mar 17 12:40:27 PM PDT 24
Peak memory 190756 kb
Host smart-69946ae1-3284-4449-bd37-72737b57796d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196899197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3196899197
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3397956763
Short name T195
Test name
Test status
Simulation time 219976615739 ps
CPU time 367.36 seconds
Started Mar 17 12:27:53 PM PDT 24
Finished Mar 17 12:34:01 PM PDT 24
Peak memory 182220 kb
Host smart-4990c8af-16c3-47c1-b52d-076427814ed2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397956763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3397956763
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1085556086
Short name T438
Test name
Test status
Simulation time 469994484493 ps
CPU time 182.46 seconds
Started Mar 17 12:24:35 PM PDT 24
Finished Mar 17 12:27:37 PM PDT 24
Peak memory 182524 kb
Host smart-752b2fe7-4df2-450a-ab82-1d9824668422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085556086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1085556086
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1481544618
Short name T203
Test name
Test status
Simulation time 342666677738 ps
CPU time 199.7 seconds
Started Mar 17 12:28:01 PM PDT 24
Finished Mar 17 12:31:21 PM PDT 24
Peak memory 190748 kb
Host smart-45926f7d-2293-4296-a70a-f3d6715985cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481544618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1481544618
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.357596873
Short name T391
Test name
Test status
Simulation time 27263792529 ps
CPU time 189.15 seconds
Started Mar 17 12:24:29 PM PDT 24
Finished Mar 17 12:27:39 PM PDT 24
Peak memory 182620 kb
Host smart-30480c25-0d96-48ba-9e08-cb576352c6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357596873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.357596873
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.766818023
Short name T20
Test name
Test status
Simulation time 65348740 ps
CPU time 0.86 seconds
Started Mar 17 12:28:30 PM PDT 24
Finished Mar 17 12:28:31 PM PDT 24
Peak memory 212988 kb
Host smart-66793d7b-505b-4cf0-9ac5-160b2d308852
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766818023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.766818023
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2383295137
Short name T241
Test name
Test status
Simulation time 576459363370 ps
CPU time 288.33 seconds
Started Mar 17 12:24:45 PM PDT 24
Finished Mar 17 12:29:33 PM PDT 24
Peak memory 195288 kb
Host smart-bd62a376-2b75-42cb-a8c8-f390c5d952fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383295137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2383295137
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.1810778871
Short name T39
Test name
Test status
Simulation time 69404552370 ps
CPU time 347.66 seconds
Started Mar 17 12:27:45 PM PDT 24
Finished Mar 17 12:33:33 PM PDT 24
Peak memory 204580 kb
Host smart-c1b38b5d-7bdd-40f1-bc70-0ec356e6001e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810778871 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.1810778871
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.305353061
Short name T367
Test name
Test status
Simulation time 133528391755 ps
CPU time 172.21 seconds
Started Mar 17 12:29:36 PM PDT 24
Finished Mar 17 12:32:28 PM PDT 24
Peak memory 182460 kb
Host smart-3273f01f-094e-4d7a-acf1-a59de6658ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305353061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.305353061
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.919764349
Short name T364
Test name
Test status
Simulation time 1890686421 ps
CPU time 2.17 seconds
Started Mar 17 12:29:41 PM PDT 24
Finished Mar 17 12:29:43 PM PDT 24
Peak memory 191688 kb
Host smart-7eb15c0b-a94e-4d7e-87d2-2f4b54ba4ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919764349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.919764349
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.549103234
Short name T262
Test name
Test status
Simulation time 3817429905957 ps
CPU time 721.15 seconds
Started Mar 17 12:29:35 PM PDT 24
Finished Mar 17 12:41:37 PM PDT 24
Peak memory 190752 kb
Host smart-c52a4336-3df5-422d-ac27-eef7a4c91214
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549103234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.
549103234
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.3766450866
Short name T36
Test name
Test status
Simulation time 9399557686 ps
CPU time 101.2 seconds
Started Mar 17 12:29:30 PM PDT 24
Finished Mar 17 12:31:12 PM PDT 24
Peak memory 194452 kb
Host smart-148852fc-5263-4576-8245-d46312a683b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766450866 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.3766450866
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3108555584
Short name T336
Test name
Test status
Simulation time 10226358602 ps
CPU time 18.2 seconds
Started Mar 17 12:29:44 PM PDT 24
Finished Mar 17 12:30:03 PM PDT 24
Peak memory 182560 kb
Host smart-49ff013f-8d7a-4e8b-b85d-beae0e7080c7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108555584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.3108555584
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.4219958871
Short name T439
Test name
Test status
Simulation time 19920664849 ps
CPU time 30.62 seconds
Started Mar 17 12:29:38 PM PDT 24
Finished Mar 17 12:30:09 PM PDT 24
Peak memory 182552 kb
Host smart-c790a47c-16a1-4ce3-8e7c-acd86a89673e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219958871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.4219958871
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.1237648497
Short name T280
Test name
Test status
Simulation time 749599961504 ps
CPU time 409.66 seconds
Started Mar 17 12:31:05 PM PDT 24
Finished Mar 17 12:37:55 PM PDT 24
Peak memory 188644 kb
Host smart-b0de7d10-c562-41d4-9009-37e86562e274
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237648497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1237648497
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3786046245
Short name T190
Test name
Test status
Simulation time 40874879097 ps
CPU time 64.14 seconds
Started Mar 17 12:29:42 PM PDT 24
Finished Mar 17 12:30:46 PM PDT 24
Peak memory 182500 kb
Host smart-f0453e09-49e4-4be8-8a67-a35a786dbe83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786046245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3786046245
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.888415544
Short name T42
Test name
Test status
Simulation time 93320638171 ps
CPU time 332.2 seconds
Started Mar 17 12:31:05 PM PDT 24
Finished Mar 17 12:36:37 PM PDT 24
Peak memory 203192 kb
Host smart-4343f966-9c7d-4f6e-ba40-6d133cb213b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888415544 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.888415544
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1910931206
Short name T261
Test name
Test status
Simulation time 29293305440 ps
CPU time 12.86 seconds
Started Mar 17 12:29:42 PM PDT 24
Finished Mar 17 12:29:55 PM PDT 24
Peak memory 182572 kb
Host smart-593b7971-8ace-4cef-a761-cc067270b66f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910931206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1910931206
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.1691952971
Short name T409
Test name
Test status
Simulation time 569044604135 ps
CPU time 197.57 seconds
Started Mar 17 12:31:05 PM PDT 24
Finished Mar 17 12:34:23 PM PDT 24
Peak memory 182244 kb
Host smart-70744dae-e465-4b69-829f-f81f1ed08995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691952971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1691952971
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.3506639656
Short name T252
Test name
Test status
Simulation time 588756013658 ps
CPU time 288.71 seconds
Started Mar 17 12:29:44 PM PDT 24
Finished Mar 17 12:34:33 PM PDT 24
Peak memory 192988 kb
Host smart-af78bdf6-ab3e-4611-89c1-52ee6c42fdce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506639656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3506639656
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2716707644
Short name T311
Test name
Test status
Simulation time 189493203691 ps
CPU time 91.94 seconds
Started Mar 17 12:29:39 PM PDT 24
Finished Mar 17 12:31:12 PM PDT 24
Peak memory 182492 kb
Host smart-7ce2be37-caa3-485c-a9cc-2e713b514213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716707644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2716707644
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2688422318
Short name T351
Test name
Test status
Simulation time 45176304187 ps
CPU time 75.66 seconds
Started Mar 17 12:29:48 PM PDT 24
Finished Mar 17 12:31:04 PM PDT 24
Peak memory 182588 kb
Host smart-29bb03a4-61d5-424a-8443-3e65d2483db0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688422318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2688422318
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.4243749497
Short name T40
Test name
Test status
Simulation time 10659546525 ps
CPU time 17.12 seconds
Started Mar 17 12:29:48 PM PDT 24
Finished Mar 17 12:30:06 PM PDT 24
Peak memory 197172 kb
Host smart-d3a89968-7dfd-492e-ac91-bbe1015b77a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243749497 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.4243749497
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.958807218
Short name T370
Test name
Test status
Simulation time 33449079391 ps
CPU time 49.37 seconds
Started Mar 17 12:29:49 PM PDT 24
Finished Mar 17 12:30:38 PM PDT 24
Peak memory 182496 kb
Host smart-cfdba292-d7dc-42f3-924b-17e7890146df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958807218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.958807218
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3249137734
Short name T368
Test name
Test status
Simulation time 10486697636 ps
CPU time 11.19 seconds
Started Mar 17 12:29:41 PM PDT 24
Finished Mar 17 12:29:52 PM PDT 24
Peak memory 192384 kb
Host smart-6e4c707e-3606-44f4-bcb6-75f2f7048574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249137734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3249137734
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2056449652
Short name T182
Test name
Test status
Simulation time 98676895565 ps
CPU time 161.37 seconds
Started Mar 17 12:31:20 PM PDT 24
Finished Mar 17 12:34:01 PM PDT 24
Peak memory 182540 kb
Host smart-11db2f21-144f-40cf-9545-6b4a8878c608
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056449652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2056449652
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_random.1385567494
Short name T350
Test name
Test status
Simulation time 146966921566 ps
CPU time 249.94 seconds
Started Mar 17 12:29:41 PM PDT 24
Finished Mar 17 12:33:51 PM PDT 24
Peak memory 182560 kb
Host smart-7d9bf427-eb83-456c-aff4-820267200147
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385567494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.1385567494
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2663595392
Short name T413
Test name
Test status
Simulation time 136784536 ps
CPU time 0.52 seconds
Started Mar 17 12:29:39 PM PDT 24
Finished Mar 17 12:29:40 PM PDT 24
Peak memory 182292 kb
Host smart-face6349-c1fd-40d4-8c89-85cc851bd8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663595392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2663595392
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2272305964
Short name T3
Test name
Test status
Simulation time 40341594617 ps
CPU time 21.58 seconds
Started Mar 17 12:31:19 PM PDT 24
Finished Mar 17 12:31:41 PM PDT 24
Peak memory 182304 kb
Host smart-52c15e4b-086a-46e3-a24d-8d77a26d9d22
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272305964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2272305964
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.1804786292
Short name T381
Test name
Test status
Simulation time 40165961163 ps
CPU time 27.37 seconds
Started Mar 17 12:29:40 PM PDT 24
Finished Mar 17 12:30:08 PM PDT 24
Peak memory 182544 kb
Host smart-dcaa8916-687c-41e1-aca9-c127b99fe628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804786292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1804786292
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1904705662
Short name T67
Test name
Test status
Simulation time 486664176 ps
CPU time 1.14 seconds
Started Mar 17 12:29:42 PM PDT 24
Finished Mar 17 12:29:43 PM PDT 24
Peak memory 182312 kb
Host smart-033c436b-d50d-435e-a7d9-73a827ba0447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904705662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1904705662
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3753677798
Short name T418
Test name
Test status
Simulation time 140379000176 ps
CPU time 74.62 seconds
Started Mar 17 12:29:42 PM PDT 24
Finished Mar 17 12:30:56 PM PDT 24
Peak memory 193900 kb
Host smart-74c5cbe7-c1b3-4db7-8255-b2dea27bdc50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753677798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3753677798
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.268769782
Short name T145
Test name
Test status
Simulation time 483101542313 ps
CPU time 448.97 seconds
Started Mar 17 12:31:19 PM PDT 24
Finished Mar 17 12:38:49 PM PDT 24
Peak memory 182276 kb
Host smart-60ae8ba7-e2df-44bb-a701-2afacf8700dc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268769782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.268769782
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_random.1710018647
Short name T290
Test name
Test status
Simulation time 954654798113 ps
CPU time 1606.75 seconds
Started Mar 17 12:31:05 PM PDT 24
Finished Mar 17 12:57:52 PM PDT 24
Peak memory 188612 kb
Host smart-4b626b9d-9e4d-4620-a6d3-e76d5248f2ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710018647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1710018647
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.213151349
Short name T427
Test name
Test status
Simulation time 584326469 ps
CPU time 0.81 seconds
Started Mar 17 12:29:39 PM PDT 24
Finished Mar 17 12:29:41 PM PDT 24
Peak memory 182336 kb
Host smart-9837dbb1-6a21-4ab5-b0a0-d48f77064937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213151349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.213151349
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3625521833
Short name T118
Test name
Test status
Simulation time 269593993825 ps
CPU time 235.75 seconds
Started Mar 17 12:29:41 PM PDT 24
Finished Mar 17 12:33:37 PM PDT 24
Peak memory 190704 kb
Host smart-126ac1f5-8679-4274-9895-d37d7278c682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625521833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3625521833
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3045264757
Short name T331
Test name
Test status
Simulation time 18337088984 ps
CPU time 17.18 seconds
Started Mar 17 12:30:16 PM PDT 24
Finished Mar 17 12:30:34 PM PDT 24
Peak memory 182528 kb
Host smart-1827bcd6-6a0f-4f44-9a94-9a4c2a47feea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045264757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3045264757
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1354490487
Short name T405
Test name
Test status
Simulation time 197050414615 ps
CPU time 71.28 seconds
Started Mar 17 12:29:50 PM PDT 24
Finished Mar 17 12:31:02 PM PDT 24
Peak memory 182536 kb
Host smart-e71b6384-085b-485f-933b-8d75fc12d44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354490487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1354490487
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2715136539
Short name T148
Test name
Test status
Simulation time 160519218081 ps
CPU time 73.68 seconds
Started Mar 17 12:30:05 PM PDT 24
Finished Mar 17 12:31:19 PM PDT 24
Peak memory 182428 kb
Host smart-bad3164e-bf45-48d0-86e5-683a93b37ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715136539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2715136539
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2462037278
Short name T51
Test name
Test status
Simulation time 1784220646623 ps
CPU time 513.95 seconds
Started Mar 17 12:29:48 PM PDT 24
Finished Mar 17 12:38:22 PM PDT 24
Peak memory 190816 kb
Host smart-5e893aeb-62b1-49f7-816e-28ad30a3a6a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462037278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2462037278
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.333549196
Short name T430
Test name
Test status
Simulation time 8938099751 ps
CPU time 14.65 seconds
Started Mar 17 12:30:04 PM PDT 24
Finished Mar 17 12:30:20 PM PDT 24
Peak memory 182596 kb
Host smart-4afab4d1-132b-4d12-b25b-38c137c05c9a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333549196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.rv_timer_cfg_update_on_fly.333549196
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2129720762
Short name T377
Test name
Test status
Simulation time 138963490143 ps
CPU time 212.81 seconds
Started Mar 17 12:29:47 PM PDT 24
Finished Mar 17 12:33:20 PM PDT 24
Peak memory 182556 kb
Host smart-cd2efd40-ac55-453e-9bce-55db5be40e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129720762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2129720762
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1263866558
Short name T225
Test name
Test status
Simulation time 114904505768 ps
CPU time 46.74 seconds
Started Mar 17 12:30:05 PM PDT 24
Finished Mar 17 12:30:52 PM PDT 24
Peak memory 194576 kb
Host smart-587c4726-71fb-4a81-9168-abbacd08f733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263866558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1263866558
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3991217390
Short name T116
Test name
Test status
Simulation time 621975337763 ps
CPU time 564.82 seconds
Started Mar 17 12:27:56 PM PDT 24
Finished Mar 17 12:37:21 PM PDT 24
Peak memory 181172 kb
Host smart-f8bcb226-8695-4316-ba18-601216aa4a7a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991217390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.3991217390
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1992619558
Short name T28
Test name
Test status
Simulation time 561821633262 ps
CPU time 216.8 seconds
Started Mar 17 12:23:32 PM PDT 24
Finished Mar 17 12:27:09 PM PDT 24
Peak memory 182472 kb
Host smart-b50dd385-ecd8-4215-a322-a64415d6fb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992619558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1992619558
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.3995363504
Short name T139
Test name
Test status
Simulation time 228593053745 ps
CPU time 1146 seconds
Started Mar 17 12:26:17 PM PDT 24
Finished Mar 17 12:45:23 PM PDT 24
Peak memory 190732 kb
Host smart-704e997d-ac3f-46c0-8afb-ae30a42f0d29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995363504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3995363504
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2904712522
Short name T318
Test name
Test status
Simulation time 79818997111 ps
CPU time 1010.92 seconds
Started Mar 17 12:28:16 PM PDT 24
Finished Mar 17 12:45:07 PM PDT 24
Peak memory 182272 kb
Host smart-bd825e7e-c06d-4df8-8f35-aba0aada75cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904712522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2904712522
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3415170481
Short name T17
Test name
Test status
Simulation time 39166143 ps
CPU time 0.76 seconds
Started Mar 17 12:22:55 PM PDT 24
Finished Mar 17 12:22:56 PM PDT 24
Peak memory 212828 kb
Host smart-bc083305-c0a4-48a1-9d88-6bac6a769ce1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415170481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3415170481
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.3184562604
Short name T43
Test name
Test status
Simulation time 180303628533 ps
CPU time 349.17 seconds
Started Mar 17 12:28:05 PM PDT 24
Finished Mar 17 12:33:54 PM PDT 24
Peak memory 205084 kb
Host smart-fa603d0b-1c73-4953-b1be-b1955442ad33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184562604 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.3184562604
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3012873571
Short name T342
Test name
Test status
Simulation time 14321634895 ps
CPU time 22.38 seconds
Started Mar 17 12:29:58 PM PDT 24
Finished Mar 17 12:30:21 PM PDT 24
Peak memory 182584 kb
Host smart-328a5146-0478-4744-b667-3108f4107972
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012873571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3012873571
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3961116899
Short name T397
Test name
Test status
Simulation time 284176544699 ps
CPU time 188.66 seconds
Started Mar 17 12:29:54 PM PDT 24
Finished Mar 17 12:33:02 PM PDT 24
Peak memory 182552 kb
Host smart-b18270be-faff-4e18-b9bc-b7c55b9d8d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961116899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3961116899
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.4223607221
Short name T184
Test name
Test status
Simulation time 100063922766 ps
CPU time 159.76 seconds
Started Mar 17 12:29:53 PM PDT 24
Finished Mar 17 12:32:32 PM PDT 24
Peak memory 190748 kb
Host smart-c015fba4-98cc-4f2b-a568-fe545bdaedb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223607221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.4223607221
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.2896050116
Short name T15
Test name
Test status
Simulation time 16223072308 ps
CPU time 168.26 seconds
Started Mar 17 12:29:56 PM PDT 24
Finished Mar 17 12:32:45 PM PDT 24
Peak memory 197008 kb
Host smart-b2a483c1-6236-4293-a483-914458a54256
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896050116 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.2896050116
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2182919370
Short name T270
Test name
Test status
Simulation time 77679567727 ps
CPU time 116.85 seconds
Started Mar 17 12:31:34 PM PDT 24
Finished Mar 17 12:33:31 PM PDT 24
Peak memory 182208 kb
Host smart-81123493-e695-42dc-8774-d340657277d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182919370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2182919370
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1934971827
Short name T376
Test name
Test status
Simulation time 253675439469 ps
CPU time 212.62 seconds
Started Mar 17 12:29:55 PM PDT 24
Finished Mar 17 12:33:29 PM PDT 24
Peak memory 182480 kb
Host smart-f2446aaf-48c8-4a0b-ad1d-1c039c11811b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934971827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1934971827
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.4263924011
Short name T419
Test name
Test status
Simulation time 47175159433 ps
CPU time 148.59 seconds
Started Mar 17 12:29:56 PM PDT 24
Finished Mar 17 12:32:25 PM PDT 24
Peak memory 182548 kb
Host smart-b5b404cd-c5c9-4efc-b54f-756f2cde7720
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263924011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.4263924011
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.3136983179
Short name T204
Test name
Test status
Simulation time 259809413846 ps
CPU time 391.3 seconds
Started Mar 17 12:30:04 PM PDT 24
Finished Mar 17 12:36:35 PM PDT 24
Peak memory 190720 kb
Host smart-57b5cdd5-2152-4317-a813-5215e4ac3175
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136983179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.3136983179
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2732263534
Short name T380
Test name
Test status
Simulation time 2992447979 ps
CPU time 2.45 seconds
Started Mar 17 12:31:35 PM PDT 24
Finished Mar 17 12:31:38 PM PDT 24
Peak memory 182056 kb
Host smart-557f24cf-4ee3-47d1-a0d9-3065998ea790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732263534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2732263534
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.541707582
Short name T306
Test name
Test status
Simulation time 54421327866 ps
CPU time 98.23 seconds
Started Mar 17 12:30:17 PM PDT 24
Finished Mar 17 12:31:56 PM PDT 24
Peak memory 190696 kb
Host smart-8e615ac1-bfb4-433f-8a17-10e1f4651e32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541707582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.541707582
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.3100535032
Short name T334
Test name
Test status
Simulation time 40664120849 ps
CPU time 67.63 seconds
Started Mar 17 12:30:04 PM PDT 24
Finished Mar 17 12:31:12 PM PDT 24
Peak memory 194396 kb
Host smart-e45261ff-a32e-49fa-89b0-5bc6c3fadc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100535032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3100535032
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3065808319
Short name T394
Test name
Test status
Simulation time 1382937864772 ps
CPU time 586.2 seconds
Started Mar 17 12:30:06 PM PDT 24
Finished Mar 17 12:39:53 PM PDT 24
Peak memory 193976 kb
Host smart-15155ce2-4985-4742-a581-872e2a4597eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065808319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3065808319
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.349826580
Short name T149
Test name
Test status
Simulation time 784131187038 ps
CPU time 348.58 seconds
Started Mar 17 12:30:20 PM PDT 24
Finished Mar 17 12:36:08 PM PDT 24
Peak memory 182508 kb
Host smart-5b7f8044-384e-4d7b-97a2-af1f9f1b22fa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349826580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.349826580
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3851922240
Short name T406
Test name
Test status
Simulation time 373137538896 ps
CPU time 277.04 seconds
Started Mar 17 12:30:02 PM PDT 24
Finished Mar 17 12:34:41 PM PDT 24
Peak memory 182500 kb
Host smart-b7d69570-7d07-4de1-bd45-530135f58a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851922240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3851922240
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2926635623
Short name T301
Test name
Test status
Simulation time 61493391704 ps
CPU time 37.94 seconds
Started Mar 17 12:31:34 PM PDT 24
Finished Mar 17 12:32:12 PM PDT 24
Peak memory 188436 kb
Host smart-ce1c43a9-a7cc-4caf-a23f-8a303e0c02a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926635623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2926635623
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.209600757
Short name T230
Test name
Test status
Simulation time 1367121473706 ps
CPU time 1151.81 seconds
Started Mar 17 12:31:34 PM PDT 24
Finished Mar 17 12:50:46 PM PDT 24
Peak memory 188316 kb
Host smart-87bdfd7f-a502-46b8-b74b-e15f6bca8bcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209600757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.
209600757
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.556007697
Short name T275
Test name
Test status
Simulation time 276020962063 ps
CPU time 485.41 seconds
Started Mar 17 12:30:08 PM PDT 24
Finished Mar 17 12:38:14 PM PDT 24
Peak memory 182564 kb
Host smart-4d952326-3836-4a21-854e-36e0b2b43751
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556007697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.rv_timer_cfg_update_on_fly.556007697
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.2039698289
Short name T437
Test name
Test status
Simulation time 141869197224 ps
CPU time 189.86 seconds
Started Mar 17 12:30:12 PM PDT 24
Finished Mar 17 12:33:22 PM PDT 24
Peak memory 182524 kb
Host smart-bf2fa0be-2eae-449d-b756-6d8ebc6a1bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039698289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2039698289
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.3025816209
Short name T194
Test name
Test status
Simulation time 217954981235 ps
CPU time 191.3 seconds
Started Mar 17 12:31:34 PM PDT 24
Finished Mar 17 12:34:45 PM PDT 24
Peak memory 190212 kb
Host smart-3a55605d-874e-4301-b579-56286609d81c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025816209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3025816209
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.19579466
Short name T431
Test name
Test status
Simulation time 40299806667 ps
CPU time 34.94 seconds
Started Mar 17 12:30:14 PM PDT 24
Finished Mar 17 12:30:49 PM PDT 24
Peak memory 190696 kb
Host smart-bbc70c3f-0829-40c9-9415-619f9a451a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19579466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.19579466
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.550403696
Short name T387
Test name
Test status
Simulation time 22270799 ps
CPU time 0.53 seconds
Started Mar 17 12:30:12 PM PDT 24
Finished Mar 17 12:30:12 PM PDT 24
Peak memory 182300 kb
Host smart-f287df85-cfe6-42e1-a7ef-4114364642f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550403696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.
550403696
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3376299269
Short name T144
Test name
Test status
Simulation time 347475944394 ps
CPU time 544.96 seconds
Started Mar 17 12:30:10 PM PDT 24
Finished Mar 17 12:39:15 PM PDT 24
Peak memory 182504 kb
Host smart-79a64b7c-d3bf-4d3c-a2b6-e06f8a457317
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376299269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3376299269
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.550440017
Short name T402
Test name
Test status
Simulation time 922522482400 ps
CPU time 200.32 seconds
Started Mar 17 12:30:10 PM PDT 24
Finished Mar 17 12:33:30 PM PDT 24
Peak memory 182584 kb
Host smart-44f95eb4-b8f4-484e-86b4-fe3869b37a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550440017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.550440017
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.1927847016
Short name T121
Test name
Test status
Simulation time 70235798953 ps
CPU time 128.02 seconds
Started Mar 17 12:30:07 PM PDT 24
Finished Mar 17 12:32:15 PM PDT 24
Peak memory 190740 kb
Host smart-6b9b5cf0-4c95-40cf-b418-8a837519c627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927847016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1927847016
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.4028592215
Short name T424
Test name
Test status
Simulation time 26883449646 ps
CPU time 51.82 seconds
Started Mar 17 12:30:12 PM PDT 24
Finished Mar 17 12:31:04 PM PDT 24
Peak memory 182564 kb
Host smart-e2b70bc5-f490-42a4-b2bf-1f8c880750c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028592215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.4028592215
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1375856933
Short name T432
Test name
Test status
Simulation time 122424281 ps
CPU time 0.54 seconds
Started Mar 17 12:30:10 PM PDT 24
Finished Mar 17 12:30:10 PM PDT 24
Peak memory 182324 kb
Host smart-4b9fd1fb-e153-46f2-8b61-246999aea055
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375856933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1375856933
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.3378892581
Short name T6
Test name
Test status
Simulation time 44711623658 ps
CPU time 78.5 seconds
Started Mar 17 12:30:12 PM PDT 24
Finished Mar 17 12:31:30 PM PDT 24
Peak memory 182536 kb
Host smart-d9599d25-39ef-4b73-868b-5ba6a91766e7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378892581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.3378892581
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1245654989
Short name T369
Test name
Test status
Simulation time 602042490744 ps
CPU time 228.89 seconds
Started Mar 17 12:30:08 PM PDT 24
Finished Mar 17 12:33:58 PM PDT 24
Peak memory 182436 kb
Host smart-f62c4afb-56c1-49b8-9476-0e67ea7df38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245654989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1245654989
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.497346640
Short name T219
Test name
Test status
Simulation time 677333965108 ps
CPU time 368.21 seconds
Started Mar 17 12:30:09 PM PDT 24
Finished Mar 17 12:36:17 PM PDT 24
Peak memory 190748 kb
Host smart-07864a41-6c31-4aa0-ad8f-5bab78f6bb19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497346640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.497346640
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.1079363598
Short name T421
Test name
Test status
Simulation time 197882579 ps
CPU time 1.29 seconds
Started Mar 17 12:30:10 PM PDT 24
Finished Mar 17 12:30:11 PM PDT 24
Peak memory 193372 kb
Host smart-dba7f03f-ac26-44bc-a37f-b9e482d82ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079363598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.1079363598
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.2975493372
Short name T123
Test name
Test status
Simulation time 9632062903577 ps
CPU time 4330.49 seconds
Started Mar 17 12:30:09 PM PDT 24
Finished Mar 17 01:42:20 PM PDT 24
Peak memory 190760 kb
Host smart-494dda19-a538-4c97-b5b9-5767ad2a6310
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975493372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.2975493372
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.1990937077
Short name T38
Test name
Test status
Simulation time 57597971231 ps
CPU time 504.08 seconds
Started Mar 17 12:30:10 PM PDT 24
Finished Mar 17 12:38:34 PM PDT 24
Peak memory 205604 kb
Host smart-3bd59f88-d213-44a4-9adb-0981902cd1c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990937077 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.1990937077
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.4252327721
Short name T133
Test name
Test status
Simulation time 1370484151394 ps
CPU time 662.95 seconds
Started Mar 17 12:30:17 PM PDT 24
Finished Mar 17 12:41:20 PM PDT 24
Peak memory 182528 kb
Host smart-59448e37-7c6f-4480-8b92-4be5d042c3f2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252327721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.4252327721
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1804676590
Short name T411
Test name
Test status
Simulation time 586957571574 ps
CPU time 213.1 seconds
Started Mar 17 12:30:16 PM PDT 24
Finished Mar 17 12:33:49 PM PDT 24
Peak memory 182548 kb
Host smart-9707fa0c-8590-4fee-998c-bd3713b27806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804676590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1804676590
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2269052608
Short name T170
Test name
Test status
Simulation time 146681005712 ps
CPU time 129.68 seconds
Started Mar 17 12:30:19 PM PDT 24
Finished Mar 17 12:32:29 PM PDT 24
Peak memory 182496 kb
Host smart-ea1e60d6-c537-4b2a-af1e-9f3ea7135326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269052608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2269052608
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.908623490
Short name T55
Test name
Test status
Simulation time 752826860311 ps
CPU time 594.62 seconds
Started Mar 17 12:30:18 PM PDT 24
Finished Mar 17 12:40:13 PM PDT 24
Peak memory 195532 kb
Host smart-ddc3160f-e3c4-4938-8cc1-f1087cf8be30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908623490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.
908623490
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.2585515133
Short name T41
Test name
Test status
Simulation time 13296344654 ps
CPU time 93.02 seconds
Started Mar 17 12:30:18 PM PDT 24
Finished Mar 17 12:31:51 PM PDT 24
Peak memory 197276 kb
Host smart-165e23c4-89c0-4e5b-8445-2f1b48c236b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585515133 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.2585515133
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.4100528783
Short name T440
Test name
Test status
Simulation time 283138170211 ps
CPU time 334.04 seconds
Started Mar 17 12:30:18 PM PDT 24
Finished Mar 17 12:35:52 PM PDT 24
Peak memory 182508 kb
Host smart-267dea99-b35b-426a-9566-f0a50c053bcb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100528783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.4100528783
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.1134615668
Short name T386
Test name
Test status
Simulation time 632606196876 ps
CPU time 241.91 seconds
Started Mar 17 12:30:17 PM PDT 24
Finished Mar 17 12:34:19 PM PDT 24
Peak memory 182568 kb
Host smart-eb578759-4b6c-4a50-96ed-3c495a736458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134615668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1134615668
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2247370456
Short name T319
Test name
Test status
Simulation time 65177741475 ps
CPU time 36.54 seconds
Started Mar 17 12:31:34 PM PDT 24
Finished Mar 17 12:32:11 PM PDT 24
Peak memory 181272 kb
Host smart-124be2ad-e5bb-4e6b-a58a-4763f35eb250
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247370456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2247370456
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.735203897
Short name T22
Test name
Test status
Simulation time 95550412122 ps
CPU time 83.61 seconds
Started Mar 17 12:30:17 PM PDT 24
Finished Mar 17 12:31:41 PM PDT 24
Peak memory 182628 kb
Host smart-fcbddde3-15bd-4857-97ff-8ecbe98d9b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735203897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.735203897
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.991263570
Short name T308
Test name
Test status
Simulation time 513257986356 ps
CPU time 250.52 seconds
Started Mar 17 12:30:19 PM PDT 24
Finished Mar 17 12:34:30 PM PDT 24
Peak memory 182512 kb
Host smart-c31a066f-01d3-404a-aede-b1c7780029d2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991263570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.rv_timer_cfg_update_on_fly.991263570
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.629577266
Short name T448
Test name
Test status
Simulation time 77909864632 ps
CPU time 129.65 seconds
Started Mar 17 12:30:16 PM PDT 24
Finished Mar 17 12:32:26 PM PDT 24
Peak memory 182572 kb
Host smart-c48781df-c09f-49eb-992d-3a2e71274663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629577266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.629577266
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.2114525845
Short name T134
Test name
Test status
Simulation time 90737663790 ps
CPU time 185.2 seconds
Started Mar 17 12:30:16 PM PDT 24
Finished Mar 17 12:33:21 PM PDT 24
Peak memory 190756 kb
Host smart-2d27d500-6306-40ef-abf7-544fcd39ff37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114525845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2114525845
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1307938960
Short name T164
Test name
Test status
Simulation time 71569217243 ps
CPU time 115.61 seconds
Started Mar 17 12:30:19 PM PDT 24
Finished Mar 17 12:32:15 PM PDT 24
Peak memory 190684 kb
Host smart-f4b7db4a-8d2c-4b69-ab4e-724aa30670d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307938960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1307938960
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.2374604850
Short name T199
Test name
Test status
Simulation time 247114550727 ps
CPU time 650.83 seconds
Started Mar 17 12:30:25 PM PDT 24
Finished Mar 17 12:41:16 PM PDT 24
Peak memory 190684 kb
Host smart-a110243d-e089-45fa-9ca4-9fb401ed572d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374604850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.2374604850
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2622790281
Short name T48
Test name
Test status
Simulation time 637144081595 ps
CPU time 549.38 seconds
Started Mar 17 12:22:55 PM PDT 24
Finished Mar 17 12:32:05 PM PDT 24
Peak memory 182488 kb
Host smart-3b25b216-bc00-45b5-9e3c-044f3b980c99
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622790281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.2622790281
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3058743890
Short name T396
Test name
Test status
Simulation time 99704444690 ps
CPU time 85.43 seconds
Started Mar 17 12:28:04 PM PDT 24
Finished Mar 17 12:29:30 PM PDT 24
Peak memory 181796 kb
Host smart-7de4eaba-66af-465e-aaa6-d3912b69dd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058743890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3058743890
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3764340278
Short name T375
Test name
Test status
Simulation time 9738998934 ps
CPU time 97.3 seconds
Started Mar 17 12:28:13 PM PDT 24
Finished Mar 17 12:29:50 PM PDT 24
Peak memory 182528 kb
Host smart-6deee1ba-23b4-484e-bfa4-d3d65029e53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764340278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3764340278
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.3868422006
Short name T19
Test name
Test status
Simulation time 1209897859 ps
CPU time 0.84 seconds
Started Mar 17 12:26:07 PM PDT 24
Finished Mar 17 12:26:08 PM PDT 24
Peak memory 212876 kb
Host smart-8c3a2d54-2f02-477b-b403-d31ff874afe1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868422006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3868422006
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.2565135360
Short name T393
Test name
Test status
Simulation time 446558418479 ps
CPU time 121.36 seconds
Started Mar 17 12:24:42 PM PDT 24
Finished Mar 17 12:26:44 PM PDT 24
Peak memory 182548 kb
Host smart-4d2c1b58-b773-40ac-a70b-dae74c363d33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565135360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
2565135360
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3649580795
Short name T344
Test name
Test status
Simulation time 1178517504683 ps
CPU time 482.47 seconds
Started Mar 17 12:30:17 PM PDT 24
Finished Mar 17 12:38:19 PM PDT 24
Peak memory 182564 kb
Host smart-4ee4040e-f969-49ba-bb60-ce67cd5ea1f0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649580795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3649580795
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2985209708
Short name T371
Test name
Test status
Simulation time 317434904812 ps
CPU time 131.11 seconds
Started Mar 17 12:30:25 PM PDT 24
Finished Mar 17 12:32:36 PM PDT 24
Peak memory 182528 kb
Host smart-e5fab814-cf29-423d-9a16-82c085886694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985209708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2985209708
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.2421581365
Short name T70
Test name
Test status
Simulation time 338286544502 ps
CPU time 179.26 seconds
Started Mar 17 12:30:18 PM PDT 24
Finished Mar 17 12:33:17 PM PDT 24
Peak memory 190784 kb
Host smart-8dab686f-f8ec-4b4d-ba0f-41061c3a6da0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421581365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2421581365
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1189746403
Short name T404
Test name
Test status
Simulation time 563984679 ps
CPU time 0.98 seconds
Started Mar 17 12:30:16 PM PDT 24
Finished Mar 17 12:30:17 PM PDT 24
Peak memory 191772 kb
Host smart-ad6d6614-24e3-4ca5-9bbb-a34940613f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189746403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1189746403
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2420873674
Short name T176
Test name
Test status
Simulation time 743531563280 ps
CPU time 2017.43 seconds
Started Mar 17 12:30:25 PM PDT 24
Finished Mar 17 01:04:03 PM PDT 24
Peak memory 195668 kb
Host smart-71898ee0-c462-4084-9397-e546a8d86aa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420873674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2420873674
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.4078146709
Short name T249
Test name
Test status
Simulation time 307022894510 ps
CPU time 528.28 seconds
Started Mar 17 12:31:47 PM PDT 24
Finished Mar 17 12:40:36 PM PDT 24
Peak memory 181364 kb
Host smart-9cfcd5d4-efed-45ee-a9de-b4b3f6f622af
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078146709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.4078146709
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2545630050
Short name T451
Test name
Test status
Simulation time 110426048898 ps
CPU time 155.71 seconds
Started Mar 17 12:31:47 PM PDT 24
Finished Mar 17 12:34:23 PM PDT 24
Peak memory 181344 kb
Host smart-71878d57-7781-4e1a-b9f8-6e7d3e0e4426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545630050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2545630050
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1388445258
Short name T420
Test name
Test status
Simulation time 1228988515729 ps
CPU time 229.67 seconds
Started Mar 17 12:30:24 PM PDT 24
Finished Mar 17 12:34:14 PM PDT 24
Peak memory 190832 kb
Host smart-207c69de-792d-4d7e-ad65-95dcf941912e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388445258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1388445258
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.1491575576
Short name T56
Test name
Test status
Simulation time 531769654821 ps
CPU time 525.02 seconds
Started Mar 17 12:30:25 PM PDT 24
Finished Mar 17 12:39:10 PM PDT 24
Peak memory 190768 kb
Host smart-eaf4fc75-f790-479d-bc17-65ddcbf271c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491575576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.1491575576
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.469770829
Short name T235
Test name
Test status
Simulation time 1512291258856 ps
CPU time 565.28 seconds
Started Mar 17 12:30:30 PM PDT 24
Finished Mar 17 12:39:56 PM PDT 24
Peak memory 182568 kb
Host smart-8f821c13-8645-4aa5-97aa-3178feb05eb3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469770829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.469770829
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2319936130
Short name T445
Test name
Test status
Simulation time 364018604584 ps
CPU time 153.03 seconds
Started Mar 17 12:30:29 PM PDT 24
Finished Mar 17 12:33:02 PM PDT 24
Peak memory 182524 kb
Host smart-ac91f879-576b-49b3-8492-a64157d49657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319936130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2319936130
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.2611226505
Short name T433
Test name
Test status
Simulation time 33286779268 ps
CPU time 46.16 seconds
Started Mar 17 12:30:29 PM PDT 24
Finished Mar 17 12:31:15 PM PDT 24
Peak memory 182372 kb
Host smart-a72930fe-d1e3-43d8-98ea-5e2a5aee92b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611226505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2611226505
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.3892431549
Short name T356
Test name
Test status
Simulation time 86148536818 ps
CPU time 42.85 seconds
Started Mar 17 12:30:32 PM PDT 24
Finished Mar 17 12:31:15 PM PDT 24
Peak memory 182520 kb
Host smart-549e38ce-e69b-4168-a8d2-713c86755560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892431549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.3892431549
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3176310945
Short name T382
Test name
Test status
Simulation time 23803466083 ps
CPU time 35.54 seconds
Started Mar 17 12:30:31 PM PDT 24
Finished Mar 17 12:31:06 PM PDT 24
Peak memory 182476 kb
Host smart-bff43991-777e-46b7-8a4b-75c245877894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176310945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3176310945
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.4267370126
Short name T338
Test name
Test status
Simulation time 90141055535 ps
CPU time 185.3 seconds
Started Mar 17 12:30:30 PM PDT 24
Finished Mar 17 12:33:36 PM PDT 24
Peak memory 190764 kb
Host smart-192c695e-8d85-465f-9c87-1da808390af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267370126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.4267370126
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2418890631
Short name T24
Test name
Test status
Simulation time 340816256858 ps
CPU time 272.95 seconds
Started Mar 17 12:30:32 PM PDT 24
Finished Mar 17 12:35:06 PM PDT 24
Peak memory 190720 kb
Host smart-40cbfb96-bda5-442c-ae56-4d8f6f5a654c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418890631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2418890631
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.2997361819
Short name T35
Test name
Test status
Simulation time 56555282091 ps
CPU time 223.84 seconds
Started Mar 17 12:30:32 PM PDT 24
Finished Mar 17 12:34:16 PM PDT 24
Peak memory 205348 kb
Host smart-36fd173c-c59f-4178-9314-8b7c6e3f4877
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997361819 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.2997361819
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1558720962
Short name T166
Test name
Test status
Simulation time 531996698 ps
CPU time 1.01 seconds
Started Mar 17 12:30:37 PM PDT 24
Finished Mar 17 12:30:38 PM PDT 24
Peak memory 182384 kb
Host smart-d13ba4e5-3dc2-4684-a2d8-9c8a30c1667a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558720962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1558720962
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_random.406689162
Short name T158
Test name
Test status
Simulation time 536817704803 ps
CPU time 448.34 seconds
Started Mar 17 12:30:37 PM PDT 24
Finished Mar 17 12:38:06 PM PDT 24
Peak memory 190712 kb
Host smart-f80c774d-1b76-43e4-8b73-e62e6e0ec2d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406689162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.406689162
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1796071638
Short name T178
Test name
Test status
Simulation time 248760308829 ps
CPU time 60.7 seconds
Started Mar 17 12:30:41 PM PDT 24
Finished Mar 17 12:31:42 PM PDT 24
Peak memory 190684 kb
Host smart-3ad7888a-a2c3-4b0c-aa54-a1f98d347068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796071638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1796071638
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.128095976
Short name T388
Test name
Test status
Simulation time 345870957505 ps
CPU time 143 seconds
Started Mar 17 12:30:37 PM PDT 24
Finished Mar 17 12:33:00 PM PDT 24
Peak memory 182460 kb
Host smart-5aeafdf0-2491-447a-a7a5-d3058fd35a7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128095976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
128095976
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.2823156091
Short name T222
Test name
Test status
Simulation time 3694676533454 ps
CPU time 1308.9 seconds
Started Mar 17 12:30:36 PM PDT 24
Finished Mar 17 12:52:25 PM PDT 24
Peak memory 182560 kb
Host smart-e3085664-5480-41a4-90c5-fc1e06360f28
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823156091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.2823156091
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2148919966
Short name T398
Test name
Test status
Simulation time 344128897164 ps
CPU time 51.97 seconds
Started Mar 17 12:30:41 PM PDT 24
Finished Mar 17 12:31:33 PM PDT 24
Peak memory 182524 kb
Host smart-102316c3-562c-4df7-bc73-70e8157eb054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148919966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2148919966
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.970536577
Short name T352
Test name
Test status
Simulation time 49171885012 ps
CPU time 79.86 seconds
Started Mar 17 12:30:39 PM PDT 24
Finished Mar 17 12:31:59 PM PDT 24
Peak memory 190712 kb
Host smart-e011b763-8de4-4b02-97ac-c13b4e9879b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970536577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.970536577
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2474849146
Short name T126
Test name
Test status
Simulation time 76269981698 ps
CPU time 83.97 seconds
Started Mar 17 12:30:45 PM PDT 24
Finished Mar 17 12:32:10 PM PDT 24
Peak memory 190780 kb
Host smart-84d1fb88-bfb7-44ff-bed3-03e6c696c3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474849146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2474849146
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.46553519
Short name T379
Test name
Test status
Simulation time 224495888763 ps
CPU time 167.5 seconds
Started Mar 17 12:30:45 PM PDT 24
Finished Mar 17 12:33:33 PM PDT 24
Peak memory 182588 kb
Host smart-d1600ccf-3f41-4c57-9f33-9d56c62c80b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46553519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.46553519
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3169408848
Short name T196
Test name
Test status
Simulation time 372149839174 ps
CPU time 664.22 seconds
Started Mar 17 12:30:44 PM PDT 24
Finished Mar 17 12:41:49 PM PDT 24
Peak memory 182528 kb
Host smart-8e0acecf-fdce-4feb-b281-fad91d6ffc1c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169408848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3169408848
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.4118807464
Short name T52
Test name
Test status
Simulation time 91869293636 ps
CPU time 130.45 seconds
Started Mar 17 12:30:45 PM PDT 24
Finished Mar 17 12:32:56 PM PDT 24
Peak memory 182524 kb
Host smart-1f023eaa-3d5d-41b1-b904-e8c469deebd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118807464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.4118807464
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.4078692972
Short name T273
Test name
Test status
Simulation time 648237996108 ps
CPU time 336.69 seconds
Started Mar 17 12:30:44 PM PDT 24
Finished Mar 17 12:36:21 PM PDT 24
Peak memory 190708 kb
Host smart-769f4dcf-b579-400d-bd03-a4329791a33a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078692972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.4078692972
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.196776557
Short name T422
Test name
Test status
Simulation time 156890991 ps
CPU time 1.1 seconds
Started Mar 17 12:30:45 PM PDT 24
Finished Mar 17 12:30:47 PM PDT 24
Peak memory 182436 kb
Host smart-fac71ad6-0080-44ae-9e38-0d1ea8bc0ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196776557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.196776557
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3239560163
Short name T343
Test name
Test status
Simulation time 616473839492 ps
CPU time 1579.37 seconds
Started Mar 17 12:30:44 PM PDT 24
Finished Mar 17 12:57:03 PM PDT 24
Peak memory 190780 kb
Host smart-99b40c64-a60a-4c35-ac07-9b65cb29471d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239560163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3239560163
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.3774387697
Short name T403
Test name
Test status
Simulation time 13384154284 ps
CPU time 23.51 seconds
Started Mar 17 12:30:44 PM PDT 24
Finished Mar 17 12:31:08 PM PDT 24
Peak memory 182572 kb
Host smart-e153f628-dd5b-4e84-9273-cc7bfa9e853f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774387697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.3774387697
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.649270521
Short name T385
Test name
Test status
Simulation time 657827459795 ps
CPU time 274.63 seconds
Started Mar 17 12:30:43 PM PDT 24
Finished Mar 17 12:35:17 PM PDT 24
Peak memory 182532 kb
Host smart-975014f0-80a6-4287-9ddc-6f647dd78351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649270521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.649270521
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.187662592
Short name T131
Test name
Test status
Simulation time 347235603178 ps
CPU time 389.81 seconds
Started Mar 17 12:30:45 PM PDT 24
Finished Mar 17 12:37:15 PM PDT 24
Peak memory 190776 kb
Host smart-4a916ea8-3148-42ab-a39a-e4a2fdf0ab75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187662592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.187662592
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2026218009
Short name T444
Test name
Test status
Simulation time 160791708889 ps
CPU time 48 seconds
Started Mar 17 12:30:54 PM PDT 24
Finished Mar 17 12:31:43 PM PDT 24
Peak memory 182324 kb
Host smart-6cd2102c-2de6-4aa9-9020-a02bc157f7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026218009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2026218009
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3984315572
Short name T150
Test name
Test status
Simulation time 3124554392816 ps
CPU time 839.71 seconds
Started Mar 17 12:30:52 PM PDT 24
Finished Mar 17 12:44:52 PM PDT 24
Peak memory 182576 kb
Host smart-298e23f5-2604-44b6-9ac9-e1f392434a8f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984315572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3984315572
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.3695514432
Short name T401
Test name
Test status
Simulation time 44602430561 ps
CPU time 68.64 seconds
Started Mar 17 12:30:52 PM PDT 24
Finished Mar 17 12:32:01 PM PDT 24
Peak memory 182532 kb
Host smart-57286cea-1537-4e95-a42a-24c9815564ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695514432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3695514432
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.3691606437
Short name T141
Test name
Test status
Simulation time 1188421439430 ps
CPU time 531.65 seconds
Started Mar 17 12:30:54 PM PDT 24
Finished Mar 17 12:39:47 PM PDT 24
Peak memory 190728 kb
Host smart-53bda684-5ed7-4552-825c-671a063f2c24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691606437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3691606437
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3928724811
Short name T366
Test name
Test status
Simulation time 191549805 ps
CPU time 0.66 seconds
Started Mar 17 12:30:53 PM PDT 24
Finished Mar 17 12:30:54 PM PDT 24
Peak memory 182256 kb
Host smart-497bbcb4-22d1-49e7-b420-07de58682906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928724811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3928724811
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.590211348
Short name T428
Test name
Test status
Simulation time 93269765516 ps
CPU time 103.26 seconds
Started Mar 17 12:30:51 PM PDT 24
Finished Mar 17 12:32:35 PM PDT 24
Peak memory 182548 kb
Host smart-8bb9e8b2-e5cc-408d-9f83-b4db63fc00c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590211348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.
590211348
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3636299814
Short name T53
Test name
Test status
Simulation time 1430193434052 ps
CPU time 682.47 seconds
Started Mar 17 12:30:52 PM PDT 24
Finished Mar 17 12:42:15 PM PDT 24
Peak memory 182812 kb
Host smart-31620e10-f458-4916-946f-60def5bcabcc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636299814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3636299814
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.2387033503
Short name T443
Test name
Test status
Simulation time 162498462544 ps
CPU time 69.48 seconds
Started Mar 17 12:30:55 PM PDT 24
Finished Mar 17 12:32:05 PM PDT 24
Peak memory 182472 kb
Host smart-fbd51370-1d75-4caa-a00d-6b4d99d6b666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387033503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.2387033503
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.1748011562
Short name T220
Test name
Test status
Simulation time 935145077454 ps
CPU time 260.01 seconds
Started Mar 17 12:30:52 PM PDT 24
Finished Mar 17 12:35:13 PM PDT 24
Peak memory 190848 kb
Host smart-d230b3f6-2978-435e-9000-a32479e5e3ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748011562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1748011562
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3291046295
Short name T142
Test name
Test status
Simulation time 43235338640 ps
CPU time 70.54 seconds
Started Mar 17 12:30:59 PM PDT 24
Finished Mar 17 12:32:11 PM PDT 24
Peak memory 194260 kb
Host smart-8b783262-e980-429b-845e-249c7f8b847c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291046295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3291046295
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3723168979
Short name T208
Test name
Test status
Simulation time 21647837647 ps
CPU time 19.15 seconds
Started Mar 17 12:22:55 PM PDT 24
Finished Mar 17 12:23:15 PM PDT 24
Peak memory 182500 kb
Host smart-8f0170c1-2718-4e54-8f6c-5b54e3a0a187
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723168979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3723168979
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.2586973088
Short name T383
Test name
Test status
Simulation time 608572669152 ps
CPU time 137.82 seconds
Started Mar 17 12:28:32 PM PDT 24
Finished Mar 17 12:30:51 PM PDT 24
Peak memory 180892 kb
Host smart-9360f591-4a89-4b55-9f2f-cf72f25a2d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586973088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2586973088
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.3299810294
Short name T189
Test name
Test status
Simulation time 37469540894 ps
CPU time 63.04 seconds
Started Mar 17 12:23:39 PM PDT 24
Finished Mar 17 12:24:43 PM PDT 24
Peak memory 190732 kb
Host smart-0896f4df-1cb5-413f-b9cd-f0d3999a9600
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299810294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3299810294
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2302541146
Short name T435
Test name
Test status
Simulation time 263138071 ps
CPU time 0.63 seconds
Started Mar 17 12:28:33 PM PDT 24
Finished Mar 17 12:28:34 PM PDT 24
Peak memory 182332 kb
Host smart-d24e8176-f42e-4b5a-9918-8031d0afe91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302541146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2302541146
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.1280100209
Short name T72
Test name
Test status
Simulation time 116118487005 ps
CPU time 937.28 seconds
Started Mar 17 12:28:48 PM PDT 24
Finished Mar 17 12:44:26 PM PDT 24
Peak memory 213444 kb
Host smart-ff07a62c-98f2-4e1f-b0b0-4110be24c125
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280100209 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.1280100209
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.1232868723
Short name T282
Test name
Test status
Simulation time 132697751937 ps
CPU time 210.08 seconds
Started Mar 17 12:31:01 PM PDT 24
Finished Mar 17 12:34:32 PM PDT 24
Peak memory 182532 kb
Host smart-a7e94d56-5cb3-43c5-894d-ad6c97ad24e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232868723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1232868723
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.1604334144
Short name T257
Test name
Test status
Simulation time 304842685221 ps
CPU time 143.41 seconds
Started Mar 17 12:31:01 PM PDT 24
Finished Mar 17 12:33:25 PM PDT 24
Peak memory 190724 kb
Host smart-8f175122-8544-4fdb-84aa-f9480c57671d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604334144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1604334144
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.1261894058
Short name T441
Test name
Test status
Simulation time 126414729844 ps
CPU time 95.37 seconds
Started Mar 17 12:31:00 PM PDT 24
Finished Mar 17 12:32:35 PM PDT 24
Peak memory 190728 kb
Host smart-0c8b0eb6-cdd7-4b51-ac54-98254822183e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261894058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1261894058
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.3103253004
Short name T4
Test name
Test status
Simulation time 148303568495 ps
CPU time 164.65 seconds
Started Mar 17 12:31:01 PM PDT 24
Finished Mar 17 12:33:45 PM PDT 24
Peak memory 190808 kb
Host smart-b1afc133-a0b1-4d53-ac45-45e2422f828e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103253004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3103253004
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2595580569
Short name T49
Test name
Test status
Simulation time 163653811184 ps
CPU time 611.99 seconds
Started Mar 17 12:31:07 PM PDT 24
Finished Mar 17 12:41:19 PM PDT 24
Peak memory 190728 kb
Host smart-77519540-7b0d-40a1-84b6-c4668417b5ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595580569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2595580569
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.4164095391
Short name T316
Test name
Test status
Simulation time 759733029015 ps
CPU time 940.91 seconds
Started Mar 17 12:31:07 PM PDT 24
Finished Mar 17 12:46:49 PM PDT 24
Peak memory 190716 kb
Host smart-a7878e1f-b197-4160-9d5b-faf640f7deaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164095391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.4164095391
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3223048006
Short name T68
Test name
Test status
Simulation time 88339059411 ps
CPU time 155.08 seconds
Started Mar 17 12:31:06 PM PDT 24
Finished Mar 17 12:33:41 PM PDT 24
Peak memory 190756 kb
Host smart-f1a8392e-820a-4a18-85fa-e9e568ea631f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223048006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3223048006
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.127298735
Short name T130
Test name
Test status
Simulation time 485093222187 ps
CPU time 501.21 seconds
Started Mar 17 12:31:07 PM PDT 24
Finished Mar 17 12:39:29 PM PDT 24
Peak memory 190752 kb
Host smart-9dbe0d5c-ed29-4971-911f-43d275ebec9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127298735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.127298735
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3019111127
Short name T326
Test name
Test status
Simulation time 191265508338 ps
CPU time 277.34 seconds
Started Mar 17 12:31:06 PM PDT 24
Finished Mar 17 12:35:43 PM PDT 24
Peak memory 190752 kb
Host smart-ace22078-e0f0-40e6-a77a-0068929bc948
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019111127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3019111127
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1443213738
Short name T47
Test name
Test status
Simulation time 5954430775 ps
CPU time 10.71 seconds
Started Mar 17 12:31:06 PM PDT 24
Finished Mar 17 12:31:17 PM PDT 24
Peak memory 182508 kb
Host smart-62992f46-550e-44af-b81c-87fea8c33fba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443213738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1443213738
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.2901392930
Short name T436
Test name
Test status
Simulation time 20429744637 ps
CPU time 13.53 seconds
Started Mar 17 12:29:04 PM PDT 24
Finished Mar 17 12:29:18 PM PDT 24
Peak memory 182572 kb
Host smart-b9177caa-6125-4216-bc73-402fc753be1b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901392930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.2901392930
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.2189492578
Short name T372
Test name
Test status
Simulation time 290579283073 ps
CPU time 116.15 seconds
Started Mar 17 12:29:19 PM PDT 24
Finished Mar 17 12:31:16 PM PDT 24
Peak memory 182528 kb
Host smart-5af11f5c-ff8a-4a88-9aa3-56f0595a2a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189492578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2189492578
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.2862533559
Short name T2
Test name
Test status
Simulation time 60654428284 ps
CPU time 32.04 seconds
Started Mar 17 12:28:40 PM PDT 24
Finished Mar 17 12:29:14 PM PDT 24
Peak memory 182520 kb
Host smart-53571082-cc03-4f38-ad12-17e06147d11e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862533559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2862533559
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.3729943890
Short name T425
Test name
Test status
Simulation time 42346337405 ps
CPU time 36.41 seconds
Started Mar 17 12:29:01 PM PDT 24
Finished Mar 17 12:29:38 PM PDT 24
Peak memory 190652 kb
Host smart-b4d63063-e417-4d42-99a4-d20bd21b8ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729943890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3729943890
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3086152521
Short name T236
Test name
Test status
Simulation time 202586183690 ps
CPU time 834.08 seconds
Started Mar 17 12:29:57 PM PDT 24
Finished Mar 17 12:43:52 PM PDT 24
Peak memory 194380 kb
Host smart-a962b903-53e5-4500-8b12-f83478d31895
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086152521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3086152521
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.3564383769
Short name T410
Test name
Test status
Simulation time 68374876819 ps
CPU time 713.75 seconds
Started Mar 17 12:30:06 PM PDT 24
Finished Mar 17 12:42:00 PM PDT 24
Peak memory 208100 kb
Host smart-9d6d4eb6-0ae4-467b-9b59-42ea762179e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564383769 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.3564383769
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.1605178594
Short name T237
Test name
Test status
Simulation time 138288023328 ps
CPU time 63.64 seconds
Started Mar 17 12:31:09 PM PDT 24
Finished Mar 17 12:32:13 PM PDT 24
Peak memory 182520 kb
Host smart-a7691162-9355-4331-b732-048bc986a491
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605178594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.1605178594
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2184038166
Short name T265
Test name
Test status
Simulation time 486566172822 ps
CPU time 1034.46 seconds
Started Mar 17 12:31:06 PM PDT 24
Finished Mar 17 12:48:21 PM PDT 24
Peak memory 190692 kb
Host smart-9566d0a3-ab19-4ae9-ad99-e089d29ae857
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184038166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2184038166
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.330631361
Short name T76
Test name
Test status
Simulation time 359865434753 ps
CPU time 382.75 seconds
Started Mar 17 12:31:06 PM PDT 24
Finished Mar 17 12:37:29 PM PDT 24
Peak memory 190712 kb
Host smart-1cb9a16a-dbed-4e48-a610-5a6c7f5746ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330631361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.330631361
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.718506524
Short name T183
Test name
Test status
Simulation time 234035332813 ps
CPU time 127.29 seconds
Started Mar 17 12:31:08 PM PDT 24
Finished Mar 17 12:33:16 PM PDT 24
Peak memory 190748 kb
Host smart-bd4d95a2-d83c-4190-b375-d21835d1ffa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718506524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.718506524
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1249788598
Short name T288
Test name
Test status
Simulation time 68384825368 ps
CPU time 380.97 seconds
Started Mar 17 12:31:07 PM PDT 24
Finished Mar 17 12:37:28 PM PDT 24
Peak memory 182528 kb
Host smart-8daca3b5-71a7-4c2d-b42d-419da6840df0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249788598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1249788598
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.2954386578
Short name T54
Test name
Test status
Simulation time 16260198534 ps
CPU time 23.96 seconds
Started Mar 17 12:31:15 PM PDT 24
Finished Mar 17 12:31:39 PM PDT 24
Peak memory 182528 kb
Host smart-920dd204-787c-4864-93f5-946a7554d6ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954386578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2954386578
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.3815061363
Short name T254
Test name
Test status
Simulation time 375011592200 ps
CPU time 202.26 seconds
Started Mar 17 12:31:13 PM PDT 24
Finished Mar 17 12:34:35 PM PDT 24
Peak memory 190752 kb
Host smart-83ac191e-86db-49aa-85ca-70f900604bee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815061363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3815061363
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.4138932221
Short name T281
Test name
Test status
Simulation time 2088405245912 ps
CPU time 621.63 seconds
Started Mar 17 12:31:19 PM PDT 24
Finished Mar 17 12:41:41 PM PDT 24
Peak memory 192836 kb
Host smart-f7439094-fb08-4de6-b61d-66b8acc1a3a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138932221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.4138932221
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.1380778780
Short name T110
Test name
Test status
Simulation time 241818780874 ps
CPU time 806.86 seconds
Started Mar 17 12:31:19 PM PDT 24
Finished Mar 17 12:44:46 PM PDT 24
Peak memory 190656 kb
Host smart-f5ae1406-3730-40d9-97d6-05e1426955bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380778780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1380778780
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3274460523
Short name T323
Test name
Test status
Simulation time 801830423251 ps
CPU time 450.81 seconds
Started Mar 17 12:30:05 PM PDT 24
Finished Mar 17 12:37:36 PM PDT 24
Peak memory 182504 kb
Host smart-c91b8a1c-b0e6-47ee-9d80-575495bb6d43
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274460523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3274460523
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1991827497
Short name T447
Test name
Test status
Simulation time 84117888342 ps
CPU time 32.73 seconds
Started Mar 17 12:29:12 PM PDT 24
Finished Mar 17 12:29:45 PM PDT 24
Peak memory 182512 kb
Host smart-5f63c7df-f77b-44d0-9006-3e6bfd96313e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991827497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1991827497
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.1009796590
Short name T320
Test name
Test status
Simulation time 184325412305 ps
CPU time 168.29 seconds
Started Mar 17 12:29:35 PM PDT 24
Finished Mar 17 12:32:24 PM PDT 24
Peak memory 190732 kb
Host smart-d5e6bbb9-0eae-4803-8a22-a385b4dff0e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009796590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1009796590
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.3769694162
Short name T365
Test name
Test status
Simulation time 72635992516 ps
CPU time 136 seconds
Started Mar 17 12:29:07 PM PDT 24
Finished Mar 17 12:31:23 PM PDT 24
Peak memory 190628 kb
Host smart-50193ab2-e2e0-4d36-a3a0-aa02f4f0f224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769694162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3769694162
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.3100203457
Short name T59
Test name
Test status
Simulation time 90718684560 ps
CPU time 443.95 seconds
Started Mar 17 12:29:49 PM PDT 24
Finished Mar 17 12:37:14 PM PDT 24
Peak memory 194320 kb
Host smart-1a87f441-ed12-4f1e-b034-eaffd29c9bb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100203457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
3100203457
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.1403998759
Short name T229
Test name
Test status
Simulation time 63655249766 ps
CPU time 86.09 seconds
Started Mar 17 12:31:14 PM PDT 24
Finished Mar 17 12:32:40 PM PDT 24
Peak memory 190736 kb
Host smart-ee27bc24-1358-4a1f-ac19-c8f24f8b8394
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403998759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.1403998759
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3812214427
Short name T327
Test name
Test status
Simulation time 311007124634 ps
CPU time 154.52 seconds
Started Mar 17 12:31:15 PM PDT 24
Finished Mar 17 12:33:50 PM PDT 24
Peak memory 190740 kb
Host smart-1a06789f-71fb-48d2-a148-88b0518adba2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812214427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3812214427
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.614228650
Short name T117
Test name
Test status
Simulation time 120975282119 ps
CPU time 188.77 seconds
Started Mar 17 12:31:14 PM PDT 24
Finished Mar 17 12:34:23 PM PDT 24
Peak memory 190752 kb
Host smart-29877b1c-e196-4f36-8dde-0a7d76df09b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614228650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.614228650
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3098947834
Short name T239
Test name
Test status
Simulation time 889914686052 ps
CPU time 840.99 seconds
Started Mar 17 12:31:14 PM PDT 24
Finished Mar 17 12:45:15 PM PDT 24
Peak memory 190836 kb
Host smart-ec25219e-c927-4329-9e2c-0dfa8f8784a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098947834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3098947834
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.4026760168
Short name T27
Test name
Test status
Simulation time 60245361906 ps
CPU time 83.02 seconds
Started Mar 17 12:31:15 PM PDT 24
Finished Mar 17 12:32:38 PM PDT 24
Peak memory 194260 kb
Host smart-a7127672-e4c2-45dd-8860-2e8e9dc8e407
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026760168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.4026760168
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.4079760928
Short name T423
Test name
Test status
Simulation time 32213164516 ps
CPU time 16.07 seconds
Started Mar 17 12:31:13 PM PDT 24
Finished Mar 17 12:31:29 PM PDT 24
Peak memory 194392 kb
Host smart-0e3ae180-b54c-440e-8486-3e593ebe2d84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079760928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.4079760928
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.747359038
Short name T25
Test name
Test status
Simulation time 1365611676176 ps
CPU time 357.63 seconds
Started Mar 17 12:31:13 PM PDT 24
Finished Mar 17 12:37:11 PM PDT 24
Peak memory 190740 kb
Host smart-63ee886a-2b3a-40ee-a29d-1147b79b2818
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747359038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.747359038
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2399803516
Short name T309
Test name
Test status
Simulation time 185037150283 ps
CPU time 89.82 seconds
Started Mar 17 12:31:13 PM PDT 24
Finished Mar 17 12:32:43 PM PDT 24
Peak memory 190820 kb
Host smart-48ff2e72-724e-445e-ac02-d588e12815e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399803516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2399803516
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3337436430
Short name T360
Test name
Test status
Simulation time 717131527095 ps
CPU time 1145.27 seconds
Started Mar 17 12:29:16 PM PDT 24
Finished Mar 17 12:48:22 PM PDT 24
Peak memory 182548 kb
Host smart-b736c0d8-4aec-4272-93c7-16674f085afa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337436430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3337436430
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.4020656066
Short name T400
Test name
Test status
Simulation time 581685066250 ps
CPU time 198.31 seconds
Started Mar 17 12:29:13 PM PDT 24
Finished Mar 17 12:32:32 PM PDT 24
Peak memory 182488 kb
Host smart-feae125f-840a-4241-8ea0-6e9ac9595b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020656066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.4020656066
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1832918272
Short name T234
Test name
Test status
Simulation time 101914831555 ps
CPU time 61.96 seconds
Started Mar 17 12:29:35 PM PDT 24
Finished Mar 17 12:30:37 PM PDT 24
Peak memory 192232 kb
Host smart-f71e161f-8c81-4a47-8752-a91cba7e8ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832918272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1832918272
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.1951537546
Short name T245
Test name
Test status
Simulation time 173522390497 ps
CPU time 131.7 seconds
Started Mar 17 12:31:15 PM PDT 24
Finished Mar 17 12:33:26 PM PDT 24
Peak memory 190744 kb
Host smart-57472700-5502-4ddb-b9a6-15378feb16c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951537546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.1951537546
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1485348032
Short name T161
Test name
Test status
Simulation time 303718432465 ps
CPU time 277.6 seconds
Started Mar 17 12:31:22 PM PDT 24
Finished Mar 17 12:36:00 PM PDT 24
Peak memory 190752 kb
Host smart-fbc74d38-5cb6-4878-8240-e5f6cb26435b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485348032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1485348032
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.824553277
Short name T417
Test name
Test status
Simulation time 33302127424 ps
CPU time 34.76 seconds
Started Mar 17 12:31:27 PM PDT 24
Finished Mar 17 12:32:03 PM PDT 24
Peak memory 182456 kb
Host smart-ad5a69be-5f12-4acb-9de7-fffef8910f71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824553277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.824553277
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.1991640682
Short name T258
Test name
Test status
Simulation time 46141557098 ps
CPU time 76.39 seconds
Started Mar 17 12:31:22 PM PDT 24
Finished Mar 17 12:32:39 PM PDT 24
Peak memory 190728 kb
Host smart-c04bd429-6020-4239-92ef-0b68fefc2a60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991640682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1991640682
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.2072965788
Short name T255
Test name
Test status
Simulation time 96160448713 ps
CPU time 346.47 seconds
Started Mar 17 12:31:22 PM PDT 24
Finished Mar 17 12:37:09 PM PDT 24
Peak memory 191880 kb
Host smart-61b05fdd-526f-4902-94d5-43fcec422fe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072965788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2072965788
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.616434051
Short name T128
Test name
Test status
Simulation time 30765537194 ps
CPU time 43.16 seconds
Started Mar 17 12:31:22 PM PDT 24
Finished Mar 17 12:32:06 PM PDT 24
Peak memory 182400 kb
Host smart-ca0d76ae-bf8f-4f23-9e15-b30a980496b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616434051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.616434051
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.235920739
Short name T363
Test name
Test status
Simulation time 719744740248 ps
CPU time 202.58 seconds
Started Mar 17 12:31:22 PM PDT 24
Finished Mar 17 12:34:45 PM PDT 24
Peak memory 190712 kb
Host smart-439c7104-b46b-46cb-bc50-41a43f5eb42e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235920739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.235920739
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.259247795
Short name T313
Test name
Test status
Simulation time 1058507876967 ps
CPU time 580.69 seconds
Started Mar 17 12:29:08 PM PDT 24
Finished Mar 17 12:38:49 PM PDT 24
Peak memory 182568 kb
Host smart-f5805c28-b714-4530-b65f-7cc45fc81e4b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259247795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.rv_timer_cfg_update_on_fly.259247795
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.3376867063
Short name T434
Test name
Test status
Simulation time 32164922424 ps
CPU time 50.01 seconds
Started Mar 17 12:29:47 PM PDT 24
Finished Mar 17 12:30:37 PM PDT 24
Peak memory 182532 kb
Host smart-974c8edc-280a-4201-a7db-f89be752008f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376867063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.3376867063
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1314872892
Short name T207
Test name
Test status
Simulation time 98228094886 ps
CPU time 79.71 seconds
Started Mar 17 12:29:06 PM PDT 24
Finished Mar 17 12:30:26 PM PDT 24
Peak memory 182460 kb
Host smart-54293048-1445-46cc-9357-30fe910fabeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314872892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1314872892
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.67764530
Short name T304
Test name
Test status
Simulation time 1401019515325 ps
CPU time 707.73 seconds
Started Mar 17 12:29:08 PM PDT 24
Finished Mar 17 12:40:56 PM PDT 24
Peak memory 190768 kb
Host smart-0df7b311-4f0e-4a16-ad78-a668f4bd8e35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67764530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.67764530
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.528372750
Short name T34
Test name
Test status
Simulation time 317637107015 ps
CPU time 399.13 seconds
Started Mar 17 12:29:35 PM PDT 24
Finished Mar 17 12:36:14 PM PDT 24
Peak memory 205380 kb
Host smart-b5a8d049-7faa-46ea-a341-58ba52bd0312
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528372750 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.528372750
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.90803313
Short name T120
Test name
Test status
Simulation time 191328892385 ps
CPU time 173.61 seconds
Started Mar 17 12:31:23 PM PDT 24
Finished Mar 17 12:34:18 PM PDT 24
Peak memory 190688 kb
Host smart-0be1449e-0897-4280-a755-895907472ae0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90803313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.90803313
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3968050130
Short name T349
Test name
Test status
Simulation time 216901171265 ps
CPU time 193.37 seconds
Started Mar 17 12:31:21 PM PDT 24
Finished Mar 17 12:34:35 PM PDT 24
Peak memory 190732 kb
Host smart-e3991232-54cc-442e-a26f-0e1590b49ffc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968050130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3968050130
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.372337689
Short name T244
Test name
Test status
Simulation time 396352594902 ps
CPU time 269.14 seconds
Started Mar 17 12:31:29 PM PDT 24
Finished Mar 17 12:36:00 PM PDT 24
Peak memory 190724 kb
Host smart-6ed25586-8a67-4f41-8b06-da2388d25597
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372337689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.372337689
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.1961864126
Short name T132
Test name
Test status
Simulation time 70475495235 ps
CPU time 128.11 seconds
Started Mar 17 12:31:30 PM PDT 24
Finished Mar 17 12:33:39 PM PDT 24
Peak memory 190828 kb
Host smart-1198e858-9d47-4d2e-8b25-6f2261f06768
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961864126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1961864126
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1880474531
Short name T159
Test name
Test status
Simulation time 884735477301 ps
CPU time 364.5 seconds
Started Mar 17 12:31:28 PM PDT 24
Finished Mar 17 12:37:34 PM PDT 24
Peak memory 190732 kb
Host smart-ec72c5e9-330b-4332-b78d-709cdf250887
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880474531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1880474531
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.1154561940
Short name T8
Test name
Test status
Simulation time 287067760442 ps
CPU time 298.5 seconds
Started Mar 17 12:31:29 PM PDT 24
Finished Mar 17 12:36:28 PM PDT 24
Peak memory 190772 kb
Host smart-cb803a4b-9b16-4ec9-942f-f4b511d1becf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154561940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1154561940
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2259700178
Short name T198
Test name
Test status
Simulation time 331054802437 ps
CPU time 232.19 seconds
Started Mar 17 12:31:37 PM PDT 24
Finished Mar 17 12:35:29 PM PDT 24
Peak memory 190668 kb
Host smart-eb98588b-b881-493e-9945-fa8c33ee8af1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259700178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2259700178
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.948945903
Short name T112
Test name
Test status
Simulation time 2618503916185 ps
CPU time 1646.76 seconds
Started Mar 17 12:31:28 PM PDT 24
Finished Mar 17 12:58:57 PM PDT 24
Peak memory 190688 kb
Host smart-b44eccb7-c8d5-4a72-9a47-191647903758
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948945903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.948945903
Directory /workspace/99.rv_timer_random/latest
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