Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.57 99.36 98.73 100.00 100.00 100.00 99.32


Total test records in report: 579
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T97 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1636211337 Mar 19 12:36:05 PM PDT 24 Mar 19 12:36:06 PM PDT 24 17955242 ps
T505 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.749720730 Mar 19 12:36:04 PM PDT 24 Mar 19 12:36:05 PM PDT 24 152836888 ps
T506 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2586791638 Mar 19 12:35:54 PM PDT 24 Mar 19 12:35:55 PM PDT 24 40623979 ps
T507 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3588344592 Mar 19 12:36:01 PM PDT 24 Mar 19 12:36:02 PM PDT 24 51398633 ps
T508 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.4013393875 Mar 19 12:35:49 PM PDT 24 Mar 19 12:35:51 PM PDT 24 84206473 ps
T509 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2579950312 Mar 19 12:35:49 PM PDT 24 Mar 19 12:35:51 PM PDT 24 194183964 ps
T510 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3898678642 Mar 19 12:35:57 PM PDT 24 Mar 19 12:35:57 PM PDT 24 90859861 ps
T511 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.86647013 Mar 19 12:35:52 PM PDT 24 Mar 19 12:35:54 PM PDT 24 204510493 ps
T512 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1438634020 Mar 19 12:35:56 PM PDT 24 Mar 19 12:35:57 PM PDT 24 24252255 ps
T98 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2934512591 Mar 19 12:35:51 PM PDT 24 Mar 19 12:35:52 PM PDT 24 15420723 ps
T513 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.4191134199 Mar 19 12:35:49 PM PDT 24 Mar 19 12:35:50 PM PDT 24 104949461 ps
T514 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1171888143 Mar 19 12:36:05 PM PDT 24 Mar 19 12:36:05 PM PDT 24 66194568 ps
T515 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.804616154 Mar 19 12:36:12 PM PDT 24 Mar 19 12:36:13 PM PDT 24 79076580 ps
T516 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.318932983 Mar 19 12:36:06 PM PDT 24 Mar 19 12:36:06 PM PDT 24 28153667 ps
T517 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1742582118 Mar 19 12:36:03 PM PDT 24 Mar 19 12:36:03 PM PDT 24 30083723 ps
T518 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3606347280 Mar 19 12:36:04 PM PDT 24 Mar 19 12:36:06 PM PDT 24 70860140 ps
T519 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1384039746 Mar 19 12:36:00 PM PDT 24 Mar 19 12:36:00 PM PDT 24 37631689 ps
T520 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.392740272 Mar 19 12:36:04 PM PDT 24 Mar 19 12:36:05 PM PDT 24 62471085 ps
T521 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1249129230 Mar 19 12:35:49 PM PDT 24 Mar 19 12:35:51 PM PDT 24 143479777 ps
T522 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.413531222 Mar 19 12:35:59 PM PDT 24 Mar 19 12:36:02 PM PDT 24 125756195 ps
T523 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.291653412 Mar 19 12:36:17 PM PDT 24 Mar 19 12:36:17 PM PDT 24 13234643 ps
T524 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2186650843 Mar 19 12:36:03 PM PDT 24 Mar 19 12:36:05 PM PDT 24 96771107 ps
T525 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.130437423 Mar 19 12:36:03 PM PDT 24 Mar 19 12:36:04 PM PDT 24 39324122 ps
T526 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3792559816 Mar 19 12:35:49 PM PDT 24 Mar 19 12:35:50 PM PDT 24 37547221 ps
T527 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3036509943 Mar 19 12:36:06 PM PDT 24 Mar 19 12:36:07 PM PDT 24 13246073 ps
T528 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1414455625 Mar 19 12:35:58 PM PDT 24 Mar 19 12:35:59 PM PDT 24 175426335 ps
T529 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2601120767 Mar 19 12:35:48 PM PDT 24 Mar 19 12:35:49 PM PDT 24 140234433 ps
T530 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.4070386781 Mar 19 12:36:17 PM PDT 24 Mar 19 12:36:17 PM PDT 24 22084843 ps
T531 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3473793552 Mar 19 12:35:50 PM PDT 24 Mar 19 12:35:51 PM PDT 24 26346814 ps
T532 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2819434463 Mar 19 12:35:57 PM PDT 24 Mar 19 12:35:57 PM PDT 24 17237422 ps
T533 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.130546922 Mar 19 12:36:13 PM PDT 24 Mar 19 12:36:13 PM PDT 24 75429066 ps
T534 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2168345901 Mar 19 12:35:48 PM PDT 24 Mar 19 12:35:49 PM PDT 24 36609467 ps
T535 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.672015490 Mar 19 12:35:50 PM PDT 24 Mar 19 12:35:51 PM PDT 24 13204338 ps
T536 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.878873360 Mar 19 12:36:09 PM PDT 24 Mar 19 12:36:10 PM PDT 24 37834863 ps
T537 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2933866675 Mar 19 12:35:52 PM PDT 24 Mar 19 12:35:55 PM PDT 24 788025447 ps
T538 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1417263832 Mar 19 12:36:13 PM PDT 24 Mar 19 12:36:15 PM PDT 24 162350822 ps
T539 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.214352628 Mar 19 12:36:13 PM PDT 24 Mar 19 12:36:14 PM PDT 24 33068217 ps
T540 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1161742271 Mar 19 12:36:07 PM PDT 24 Mar 19 12:36:08 PM PDT 24 104431469 ps
T541 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2614612802 Mar 19 12:35:49 PM PDT 24 Mar 19 12:35:50 PM PDT 24 83959852 ps
T542 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1712205755 Mar 19 12:35:51 PM PDT 24 Mar 19 12:35:53 PM PDT 24 59119017 ps
T543 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1170991394 Mar 19 12:36:12 PM PDT 24 Mar 19 12:36:13 PM PDT 24 79904526 ps
T544 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3208185360 Mar 19 12:36:01 PM PDT 24 Mar 19 12:36:01 PM PDT 24 56766013 ps
T545 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.536775940 Mar 19 12:35:50 PM PDT 24 Mar 19 12:35:51 PM PDT 24 32764940 ps
T546 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1312502697 Mar 19 12:35:51 PM PDT 24 Mar 19 12:35:52 PM PDT 24 124158649 ps
T547 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.135602866 Mar 19 12:36:01 PM PDT 24 Mar 19 12:36:02 PM PDT 24 221193765 ps
T548 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1529623091 Mar 19 12:36:03 PM PDT 24 Mar 19 12:36:04 PM PDT 24 263631304 ps
T549 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1061415740 Mar 19 12:36:22 PM PDT 24 Mar 19 12:36:23 PM PDT 24 12864204 ps
T550 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.653365768 Mar 19 12:35:55 PM PDT 24 Mar 19 12:35:57 PM PDT 24 555497579 ps
T551 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1529131895 Mar 19 12:36:12 PM PDT 24 Mar 19 12:36:13 PM PDT 24 15592284 ps
T552 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3974742714 Mar 19 12:36:10 PM PDT 24 Mar 19 12:36:11 PM PDT 24 14987247 ps
T553 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2881311672 Mar 19 12:36:11 PM PDT 24 Mar 19 12:36:12 PM PDT 24 15057434 ps
T554 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2898530565 Mar 19 12:36:12 PM PDT 24 Mar 19 12:36:13 PM PDT 24 116647237 ps
T555 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2847192984 Mar 19 12:35:49 PM PDT 24 Mar 19 12:35:50 PM PDT 24 15168266 ps
T556 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2728192854 Mar 19 12:35:51 PM PDT 24 Mar 19 12:35:53 PM PDT 24 39704871 ps
T557 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3125855788 Mar 19 12:35:57 PM PDT 24 Mar 19 12:35:57 PM PDT 24 191978137 ps
T558 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.905482487 Mar 19 12:35:56 PM PDT 24 Mar 19 12:35:59 PM PDT 24 476925791 ps
T559 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1347687953 Mar 19 12:35:49 PM PDT 24 Mar 19 12:35:50 PM PDT 24 97605967 ps
T560 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3555639536 Mar 19 12:36:07 PM PDT 24 Mar 19 12:36:08 PM PDT 24 55879228 ps
T561 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2975337358 Mar 19 12:36:10 PM PDT 24 Mar 19 12:36:10 PM PDT 24 12402397 ps
T562 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3857558804 Mar 19 12:35:56 PM PDT 24 Mar 19 12:35:58 PM PDT 24 69338023 ps
T563 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.4053000853 Mar 19 12:35:57 PM PDT 24 Mar 19 12:35:57 PM PDT 24 76095188 ps
T564 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2486898176 Mar 19 12:35:51 PM PDT 24 Mar 19 12:35:51 PM PDT 24 39928774 ps
T565 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1892035309 Mar 19 12:36:13 PM PDT 24 Mar 19 12:36:13 PM PDT 24 15921835 ps
T566 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.46011986 Mar 19 12:35:48 PM PDT 24 Mar 19 12:35:49 PM PDT 24 17806887 ps
T567 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.422766725 Mar 19 12:36:10 PM PDT 24 Mar 19 12:36:11 PM PDT 24 15701677 ps
T568 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3557591554 Mar 19 12:36:02 PM PDT 24 Mar 19 12:36:05 PM PDT 24 128690464 ps
T569 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2677020383 Mar 19 12:36:02 PM PDT 24 Mar 19 12:36:05 PM PDT 24 198955548 ps
T570 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2778206492 Mar 19 12:36:10 PM PDT 24 Mar 19 12:36:11 PM PDT 24 19373494 ps
T571 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2878753306 Mar 19 12:35:55 PM PDT 24 Mar 19 12:35:56 PM PDT 24 42805057 ps
T99 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1883792937 Mar 19 12:36:04 PM PDT 24 Mar 19 12:36:05 PM PDT 24 13194113 ps
T572 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3274992734 Mar 19 12:36:24 PM PDT 24 Mar 19 12:36:25 PM PDT 24 53763309 ps
T573 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3841229202 Mar 19 12:35:55 PM PDT 24 Mar 19 12:35:56 PM PDT 24 20941845 ps
T574 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1058130855 Mar 19 12:35:56 PM PDT 24 Mar 19 12:35:57 PM PDT 24 22966265 ps
T100 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1813807031 Mar 19 12:36:03 PM PDT 24 Mar 19 12:36:04 PM PDT 24 45560407 ps
T575 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.242500885 Mar 19 12:35:57 PM PDT 24 Mar 19 12:35:58 PM PDT 24 43137879 ps
T576 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2258643143 Mar 19 12:36:00 PM PDT 24 Mar 19 12:36:01 PM PDT 24 65753074 ps
T577 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1959151772 Mar 19 12:35:49 PM PDT 24 Mar 19 12:35:49 PM PDT 24 24212230 ps
T578 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1760898917 Mar 19 12:35:48 PM PDT 24 Mar 19 12:35:48 PM PDT 24 82586884 ps
T579 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3531280287 Mar 19 12:36:22 PM PDT 24 Mar 19 12:36:23 PM PDT 24 122810059 ps

Test location /workspace/coverage/default/12.rv_timer_random.2134955000
Short name T5
Test name
Test status
Simulation time 425042821391 ps
CPU time 335.81 seconds
Started Mar 19 12:38:36 PM PDT 24
Finished Mar 19 12:44:12 PM PDT 24
Peak memory 190732 kb
Host smart-fce7a376-c219-4f30-ae6a-f0eaa385b684
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134955000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2134955000
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.2367708382
Short name T13
Test name
Test status
Simulation time 67217875809 ps
CPU time 544.28 seconds
Started Mar 19 12:38:40 PM PDT 24
Finished Mar 19 12:47:45 PM PDT 24
Peak memory 205428 kb
Host smart-46636d9b-1e26-4cf5-bbeb-c8dfbe7d4ae7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367708382 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.2367708382
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.672774007
Short name T23
Test name
Test status
Simulation time 1087820118168 ps
CPU time 2280.93 seconds
Started Mar 19 12:38:42 PM PDT 24
Finished Mar 19 01:16:44 PM PDT 24
Peak memory 195360 kb
Host smart-e6d43f9e-12a4-4b01-a488-a5931b19395f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672774007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.
672774007
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2804840346
Short name T31
Test name
Test status
Simulation time 960468999 ps
CPU time 1.31 seconds
Started Mar 19 12:35:58 PM PDT 24
Finished Mar 19 12:36:00 PM PDT 24
Peak memory 195252 kb
Host smart-fca7c7c5-faf4-48a6-8cfd-0f60bc63ecc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804840346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.2804840346
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.884320264
Short name T69
Test name
Test status
Simulation time 1129302726439 ps
CPU time 1375.93 seconds
Started Mar 19 12:38:26 PM PDT 24
Finished Mar 19 01:01:22 PM PDT 24
Peak memory 196080 kb
Host smart-eeedcb98-dbe5-4b8a-b253-50ef896b84b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884320264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.884320264
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3123545305
Short name T12
Test name
Test status
Simulation time 2871285354373 ps
CPU time 1490.18 seconds
Started Mar 19 12:39:00 PM PDT 24
Finished Mar 19 01:03:51 PM PDT 24
Peak memory 194132 kb
Host smart-07d143fc-36d9-4c20-86a8-26ae00faf7e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123545305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3123545305
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3458877215
Short name T196
Test name
Test status
Simulation time 8977910728151 ps
CPU time 3794.7 seconds
Started Mar 19 12:39:05 PM PDT 24
Finished Mar 19 01:42:20 PM PDT 24
Peak memory 195468 kb
Host smart-ce799550-eed8-43c6-af9d-ed91eb748827
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458877215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3458877215
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1436690505
Short name T56
Test name
Test status
Simulation time 61798833 ps
CPU time 0.57 seconds
Started Mar 19 12:35:47 PM PDT 24
Finished Mar 19 12:35:48 PM PDT 24
Peak memory 182636 kb
Host smart-9c99bb0f-890d-4db3-a551-87c3c293fadc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436690505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.1436690505
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1290085103
Short name T35
Test name
Test status
Simulation time 2850685670073 ps
CPU time 1736.34 seconds
Started Mar 19 12:38:56 PM PDT 24
Finished Mar 19 01:07:52 PM PDT 24
Peak memory 190816 kb
Host smart-382819a4-0ec4-4469-ac08-6b305972acbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290085103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1290085103
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.1279183915
Short name T67
Test name
Test status
Simulation time 1328622943140 ps
CPU time 1540.17 seconds
Started Mar 19 12:38:57 PM PDT 24
Finished Mar 19 01:04:37 PM PDT 24
Peak memory 190768 kb
Host smart-603ceaec-7f5c-4b98-a04f-954a0bd94177
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279183915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.1279183915
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1846350786
Short name T158
Test name
Test status
Simulation time 1308942657286 ps
CPU time 637.14 seconds
Started Mar 19 12:38:57 PM PDT 24
Finished Mar 19 12:49:34 PM PDT 24
Peak memory 195128 kb
Host smart-e3563d9d-e828-440a-82d5-0cabfb313717
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846350786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1846350786
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.290037344
Short name T20
Test name
Test status
Simulation time 52637313 ps
CPU time 0.77 seconds
Started Mar 19 12:38:26 PM PDT 24
Finished Mar 19 12:38:27 PM PDT 24
Peak memory 212880 kb
Host smart-2b07bbef-9de6-4100-bb7b-248ffc0736f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290037344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.290037344
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/84.rv_timer_random.147342404
Short name T184
Test name
Test status
Simulation time 168998680826 ps
CPU time 743.05 seconds
Started Mar 19 12:39:14 PM PDT 24
Finished Mar 19 12:51:37 PM PDT 24
Peak memory 190732 kb
Host smart-28760d63-2c2e-4402-8dd1-418801130d15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147342404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.147342404
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.3731997189
Short name T87
Test name
Test status
Simulation time 323454030262 ps
CPU time 1038.22 seconds
Started Mar 19 12:39:09 PM PDT 24
Finished Mar 19 12:56:28 PM PDT 24
Peak memory 190796 kb
Host smart-383f2dba-7a76-41ef-8751-43c54aa108b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731997189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3731997189
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2066452183
Short name T224
Test name
Test status
Simulation time 521242338663 ps
CPU time 1452.48 seconds
Started Mar 19 12:39:24 PM PDT 24
Finished Mar 19 01:03:37 PM PDT 24
Peak memory 190756 kb
Host smart-3e635c2f-66ce-4e03-87d1-73067c400be5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066452183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2066452183
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3264396463
Short name T159
Test name
Test status
Simulation time 390812508951 ps
CPU time 646.88 seconds
Started Mar 19 12:38:45 PM PDT 24
Finished Mar 19 12:49:32 PM PDT 24
Peak memory 190712 kb
Host smart-31b7f6ea-1870-4975-af53-9bf8ba02de72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264396463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3264396463
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.1293231577
Short name T164
Test name
Test status
Simulation time 418938692661 ps
CPU time 800.71 seconds
Started Mar 19 12:38:57 PM PDT 24
Finished Mar 19 12:52:18 PM PDT 24
Peak memory 190792 kb
Host smart-92e8dc65-d08b-40d4-8ec8-5807ece24987
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293231577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.1293231577
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/115.rv_timer_random.4030147030
Short name T176
Test name
Test status
Simulation time 240545633146 ps
CPU time 728.65 seconds
Started Mar 19 12:39:30 PM PDT 24
Finished Mar 19 12:51:39 PM PDT 24
Peak memory 190744 kb
Host smart-36f4b8fb-664e-40e8-8209-a7ee81c8eb13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030147030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.4030147030
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.2105334313
Short name T307
Test name
Test status
Simulation time 78689692368 ps
CPU time 152.94 seconds
Started Mar 19 12:39:26 PM PDT 24
Finished Mar 19 12:41:59 PM PDT 24
Peak memory 190776 kb
Host smart-bc4b6e7d-fe99-4cf2-88ce-69f13a8bc0fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105334313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2105334313
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.1578833435
Short name T207
Test name
Test status
Simulation time 243766410861 ps
CPU time 548.73 seconds
Started Mar 19 12:38:34 PM PDT 24
Finished Mar 19 12:47:43 PM PDT 24
Peak memory 190692 kb
Host smart-78c11af7-bb57-481e-a819-e9be5eadab9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578833435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.1578833435
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/74.rv_timer_random.2388071534
Short name T130
Test name
Test status
Simulation time 177704848070 ps
CPU time 304.27 seconds
Started Mar 19 12:39:09 PM PDT 24
Finished Mar 19 12:44:14 PM PDT 24
Peak memory 193212 kb
Host smart-80b94345-70c1-4aa6-9487-e90a9e20b850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388071534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2388071534
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1891881831
Short name T156
Test name
Test status
Simulation time 607568676623 ps
CPU time 568.98 seconds
Started Mar 19 12:38:27 PM PDT 24
Finished Mar 19 12:47:56 PM PDT 24
Peak memory 182504 kb
Host smart-86149671-dd02-40c3-be19-895368b88360
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891881831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1891881831
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/171.rv_timer_random.3795581601
Short name T83
Test name
Test status
Simulation time 2547775122927 ps
CPU time 554.4 seconds
Started Mar 19 12:39:47 PM PDT 24
Finished Mar 19 12:49:01 PM PDT 24
Peak memory 190784 kb
Host smart-6fffef50-3c04-4bbb-b18a-99f9c96f0042
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795581601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.3795581601
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.4254713599
Short name T247
Test name
Test status
Simulation time 1899551966627 ps
CPU time 587.62 seconds
Started Mar 19 12:38:44 PM PDT 24
Finished Mar 19 12:48:32 PM PDT 24
Peak memory 190760 kb
Host smart-b8173cee-10b2-4848-80da-e970f3c1af88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254713599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.4254713599
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.2510443398
Short name T261
Test name
Test status
Simulation time 167570115048 ps
CPU time 916.56 seconds
Started Mar 19 12:39:52 PM PDT 24
Finished Mar 19 12:55:10 PM PDT 24
Peak memory 190760 kb
Host smart-b324cf6d-8be4-400a-abb9-e317af8a1f81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510443398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2510443398
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1307891658
Short name T79
Test name
Test status
Simulation time 392043865693 ps
CPU time 793.3 seconds
Started Mar 19 12:39:09 PM PDT 24
Finished Mar 19 12:52:23 PM PDT 24
Peak memory 190732 kb
Host smart-f3b869f9-8c5d-407c-bb58-e9c73469937e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307891658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1307891658
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.3791842983
Short name T181
Test name
Test status
Simulation time 417638627996 ps
CPU time 197.3 seconds
Started Mar 19 12:39:11 PM PDT 24
Finished Mar 19 12:42:29 PM PDT 24
Peak memory 190784 kb
Host smart-e3e5af84-89bb-44e1-8ee4-5c47cfd6989d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791842983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3791842983
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.1100052927
Short name T221
Test name
Test status
Simulation time 183240834610 ps
CPU time 816.25 seconds
Started Mar 19 12:39:09 PM PDT 24
Finished Mar 19 12:52:46 PM PDT 24
Peak memory 191160 kb
Host smart-9a93231f-224b-401a-86d4-7c269d2844c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100052927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1100052927
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1237722579
Short name T272
Test name
Test status
Simulation time 2030014939417 ps
CPU time 520.77 seconds
Started Mar 19 12:38:26 PM PDT 24
Finished Mar 19 12:47:07 PM PDT 24
Peak memory 190728 kb
Host smart-f0de9749-71c4-447e-a75e-da20336b0e03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237722579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1237722579
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/151.rv_timer_random.1583888439
Short name T350
Test name
Test status
Simulation time 1587862688083 ps
CPU time 470.15 seconds
Started Mar 19 12:39:44 PM PDT 24
Finished Mar 19 12:47:34 PM PDT 24
Peak memory 190736 kb
Host smart-34790fbe-c6aa-487b-bd36-695be899d97d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583888439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1583888439
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.3990524352
Short name T173
Test name
Test status
Simulation time 124149624257 ps
CPU time 240.97 seconds
Started Mar 19 12:39:45 PM PDT 24
Finished Mar 19 12:43:46 PM PDT 24
Peak memory 190748 kb
Host smart-11fe4683-8403-42a5-9e58-f943ec9d0766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990524352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3990524352
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.99075376
Short name T199
Test name
Test status
Simulation time 100168318106 ps
CPU time 90.71 seconds
Started Mar 19 12:38:45 PM PDT 24
Finished Mar 19 12:40:15 PM PDT 24
Peak memory 182608 kb
Host smart-ac3016fe-ce61-4961-a62c-223d818c1645
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99075376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.rv_timer_cfg_update_on_fly.99075376
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/166.rv_timer_random.2378386634
Short name T135
Test name
Test status
Simulation time 125049594495 ps
CPU time 98.79 seconds
Started Mar 19 12:39:42 PM PDT 24
Finished Mar 19 12:41:21 PM PDT 24
Peak memory 190728 kb
Host smart-1e32ead2-5f45-4848-998e-c837944cf375
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378386634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2378386634
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2572989697
Short name T161
Test name
Test status
Simulation time 2001655903716 ps
CPU time 544.72 seconds
Started Mar 19 12:38:41 PM PDT 24
Finished Mar 19 12:47:46 PM PDT 24
Peak memory 182540 kb
Host smart-88fbdd97-eee1-47b3-91f0-83aea2e30678
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572989697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2572989697
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3765465565
Short name T216
Test name
Test status
Simulation time 669391435423 ps
CPU time 1506.76 seconds
Started Mar 19 12:38:49 PM PDT 24
Finished Mar 19 01:03:56 PM PDT 24
Peak memory 195328 kb
Host smart-3d12e1db-5107-404f-be92-35091cd2e34e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765465565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3765465565
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_random.1934573200
Short name T72
Test name
Test status
Simulation time 193136259824 ps
CPU time 642.92 seconds
Started Mar 19 12:38:49 PM PDT 24
Finished Mar 19 12:49:32 PM PDT 24
Peak memory 192960 kb
Host smart-854f4d4e-075e-4975-9745-9b139ae2c6e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934573200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1934573200
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3930040009
Short name T90
Test name
Test status
Simulation time 26414882 ps
CPU time 0.56 seconds
Started Mar 19 12:35:49 PM PDT 24
Finished Mar 19 12:35:49 PM PDT 24
Peak memory 182536 kb
Host smart-4d4a28ce-516d-4676-a52c-6d08988b2072
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930040009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3930040009
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.1522237756
Short name T292
Test name
Test status
Simulation time 726330848524 ps
CPU time 1558.73 seconds
Started Mar 19 12:39:13 PM PDT 24
Finished Mar 19 01:05:12 PM PDT 24
Peak memory 190740 kb
Host smart-0781a642-4fb3-4d4e-b838-fad44cdf76f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522237756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1522237756
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3660609216
Short name T318
Test name
Test status
Simulation time 42511261348 ps
CPU time 57.87 seconds
Started Mar 19 12:38:56 PM PDT 24
Finished Mar 19 12:39:53 PM PDT 24
Peak memory 182568 kb
Host smart-29a0d521-cb59-4322-ae6d-e1bc01af499e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660609216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3660609216
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.131156002
Short name T315
Test name
Test status
Simulation time 141767273830 ps
CPU time 53.05 seconds
Started Mar 19 12:39:03 PM PDT 24
Finished Mar 19 12:39:56 PM PDT 24
Peak memory 182540 kb
Host smart-ee18f056-7c4a-4627-b91d-d27f42029843
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131156002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.131156002
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/56.rv_timer_random.1915782688
Short name T182
Test name
Test status
Simulation time 616657519214 ps
CPU time 291.15 seconds
Started Mar 19 12:39:07 PM PDT 24
Finished Mar 19 12:43:59 PM PDT 24
Peak memory 190788 kb
Host smart-46dc814e-06e7-4dc0-a52e-a5e40e9352d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915782688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.1915782688
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1316965088
Short name T290
Test name
Test status
Simulation time 325996371249 ps
CPU time 230.65 seconds
Started Mar 19 12:39:16 PM PDT 24
Finished Mar 19 12:43:08 PM PDT 24
Peak memory 190700 kb
Host smart-6fc43718-1d9e-427f-ae0d-0d22f3a88b80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316965088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1316965088
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.202118291
Short name T244
Test name
Test status
Simulation time 272191494349 ps
CPU time 354.46 seconds
Started Mar 19 12:39:25 PM PDT 24
Finished Mar 19 12:45:20 PM PDT 24
Peak memory 190772 kb
Host smart-4f83a900-2f09-4ab5-9ffc-90fa34364135
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202118291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.202118291
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.269116570
Short name T230
Test name
Test status
Simulation time 2039793151723 ps
CPU time 931.93 seconds
Started Mar 19 12:39:40 PM PDT 24
Finished Mar 19 12:55:12 PM PDT 24
Peak memory 190764 kb
Host smart-e8422fbb-75dc-4fd6-a07b-54975e55f758
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269116570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.269116570
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.693947864
Short name T140
Test name
Test status
Simulation time 3058688942547 ps
CPU time 788.96 seconds
Started Mar 19 12:39:42 PM PDT 24
Finished Mar 19 12:52:52 PM PDT 24
Peak memory 190736 kb
Host smart-6620ffad-8121-40bb-a51e-c9336fda2d20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693947864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.693947864
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2016335392
Short name T49
Test name
Test status
Simulation time 312323708150 ps
CPU time 277.27 seconds
Started Mar 19 12:39:45 PM PDT 24
Finished Mar 19 12:44:22 PM PDT 24
Peak memory 190744 kb
Host smart-dc1ca486-bcb4-4a94-addd-86d0b81af23a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016335392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2016335392
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random.2002600775
Short name T249
Test name
Test status
Simulation time 131826148110 ps
CPU time 231.37 seconds
Started Mar 19 12:38:49 PM PDT 24
Finished Mar 19 12:42:40 PM PDT 24
Peak memory 190752 kb
Host smart-cee357cc-83c3-437e-b5ec-b85e382c260e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002600775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2002600775
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random.433400431
Short name T270
Test name
Test status
Simulation time 113820886268 ps
CPU time 182.6 seconds
Started Mar 19 12:38:57 PM PDT 24
Finished Mar 19 12:42:00 PM PDT 24
Peak memory 190808 kb
Host smart-e5962803-62ff-4591-a92c-b3a8da2f2324
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433400431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.433400431
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/60.rv_timer_random.2418361307
Short name T328
Test name
Test status
Simulation time 110381301820 ps
CPU time 67.52 seconds
Started Mar 19 12:39:08 PM PDT 24
Finished Mar 19 12:40:15 PM PDT 24
Peak memory 194636 kb
Host smart-8c27d62a-af57-449c-8d89-e3e70e2332fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418361307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2418361307
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.3773551760
Short name T273
Test name
Test status
Simulation time 580558721922 ps
CPU time 579.24 seconds
Started Mar 19 12:39:13 PM PDT 24
Finished Mar 19 12:48:52 PM PDT 24
Peak memory 190720 kb
Host smart-ff7499e3-4591-497d-8eaa-291739c450e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773551760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3773551760
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.1517552118
Short name T128
Test name
Test status
Simulation time 209210796816 ps
CPU time 214.21 seconds
Started Mar 19 12:39:25 PM PDT 24
Finished Mar 19 12:42:59 PM PDT 24
Peak memory 190736 kb
Host smart-6ff42c21-f376-4ffd-9f25-f998bddc969c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517552118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1517552118
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.2467925686
Short name T166
Test name
Test status
Simulation time 269938481856 ps
CPU time 1600.18 seconds
Started Mar 19 12:39:34 PM PDT 24
Finished Mar 19 01:06:15 PM PDT 24
Peak memory 190788 kb
Host smart-7e30dc28-f836-4ed3-8c60-241fa2d8ca67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467925686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2467925686
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.740335043
Short name T183
Test name
Test status
Simulation time 63400860260 ps
CPU time 122.05 seconds
Started Mar 19 12:39:35 PM PDT 24
Finished Mar 19 12:41:38 PM PDT 24
Peak memory 190752 kb
Host smart-d032e0c0-88a0-40d3-8c27-cd0ad0e405d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740335043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.740335043
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.3987894842
Short name T169
Test name
Test status
Simulation time 716165907447 ps
CPU time 1164.38 seconds
Started Mar 19 12:39:37 PM PDT 24
Finished Mar 19 12:59:02 PM PDT 24
Peak memory 190752 kb
Host smart-6f381cdf-73a3-4b67-8d0e-9eca0a7616ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987894842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3987894842
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.4169700025
Short name T245
Test name
Test status
Simulation time 481562751295 ps
CPU time 623.1 seconds
Started Mar 19 12:39:39 PM PDT 24
Finished Mar 19 12:50:02 PM PDT 24
Peak memory 190756 kb
Host smart-1dbe1b28-578b-42e7-a207-67443d56a955
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169700025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.4169700025
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.996827898
Short name T154
Test name
Test status
Simulation time 1272176545856 ps
CPU time 942.46 seconds
Started Mar 19 12:38:45 PM PDT 24
Finished Mar 19 12:54:28 PM PDT 24
Peak memory 190736 kb
Host smart-98c2e5aa-0148-4d28-9c54-a87ad8e52ae4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996827898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.
996827898
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_random.725415470
Short name T353
Test name
Test status
Simulation time 20047761281 ps
CPU time 582.51 seconds
Started Mar 19 12:38:48 PM PDT 24
Finished Mar 19 12:48:31 PM PDT 24
Peak memory 190752 kb
Host smart-71a70486-dde8-443a-abcc-761e1ee9a0d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725415470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.725415470
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random.2062070380
Short name T274
Test name
Test status
Simulation time 616464341737 ps
CPU time 2133.55 seconds
Started Mar 19 12:38:58 PM PDT 24
Finished Mar 19 01:14:32 PM PDT 24
Peak memory 190744 kb
Host smart-5ac225fa-a1a4-4d8b-a407-63ee65df8704
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062070380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2062070380
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.951069597
Short name T192
Test name
Test status
Simulation time 136105938016 ps
CPU time 561.92 seconds
Started Mar 19 12:39:08 PM PDT 24
Finished Mar 19 12:48:31 PM PDT 24
Peak memory 190736 kb
Host smart-1f09bd5a-513f-46d1-b344-cc2ee2080f23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951069597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.951069597
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.895281395
Short name T208
Test name
Test status
Simulation time 466776579658 ps
CPU time 656.74 seconds
Started Mar 19 12:38:40 PM PDT 24
Finished Mar 19 12:49:37 PM PDT 24
Peak memory 190748 kb
Host smart-2feb24b5-7134-47c5-aa47-bb1d9f0ca5f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895281395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.895281395
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2090535961
Short name T103
Test name
Test status
Simulation time 38798163 ps
CPU time 0.86 seconds
Started Mar 19 12:35:51 PM PDT 24
Finished Mar 19 12:35:52 PM PDT 24
Peak memory 191640 kb
Host smart-86d7e771-7db2-4f45-9d6f-afdd5c63a81f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090535961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2090535961
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_timer_random.143126784
Short name T234
Test name
Test status
Simulation time 623628192261 ps
CPU time 1457.74 seconds
Started Mar 19 12:38:27 PM PDT 24
Finished Mar 19 01:02:44 PM PDT 24
Peak memory 190712 kb
Host smart-025b8cda-38a7-49e2-ba9e-98026aff8d6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143126784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.143126784
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.757043026
Short name T40
Test name
Test status
Simulation time 62334162669 ps
CPU time 701.87 seconds
Started Mar 19 12:38:33 PM PDT 24
Finished Mar 19 12:50:15 PM PDT 24
Peak memory 205444 kb
Host smart-004e4fcb-d25f-4390-8b3a-72f4e7953b0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757043026 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.757043026
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/135.rv_timer_random.1119174762
Short name T282
Test name
Test status
Simulation time 228406258594 ps
CPU time 263.34 seconds
Started Mar 19 12:39:34 PM PDT 24
Finished Mar 19 12:43:57 PM PDT 24
Peak memory 190736 kb
Host smart-c7f0c1a9-fce2-44ca-9bf8-043aae5fc2e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119174762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1119174762
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3765111560
Short name T306
Test name
Test status
Simulation time 128525082076 ps
CPU time 51.95 seconds
Started Mar 19 12:38:42 PM PDT 24
Finished Mar 19 12:39:34 PM PDT 24
Peak memory 194268 kb
Host smart-ff132564-9d25-4e6a-b6e2-121ac66bee1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765111560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3765111560
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/148.rv_timer_random.676145717
Short name T309
Test name
Test status
Simulation time 184991624811 ps
CPU time 91.29 seconds
Started Mar 19 12:39:39 PM PDT 24
Finished Mar 19 12:41:10 PM PDT 24
Peak memory 190732 kb
Host smart-940962e3-714e-4da0-8f29-aae2eca44345
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676145717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.676145717
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.301346703
Short name T145
Test name
Test status
Simulation time 230005566501 ps
CPU time 405.91 seconds
Started Mar 19 12:38:43 PM PDT 24
Finished Mar 19 12:45:29 PM PDT 24
Peak memory 182576 kb
Host smart-6976deb5-5a58-4f27-8e86-13e94a41cea8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301346703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.rv_timer_cfg_update_on_fly.301346703
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/170.rv_timer_random.1543136933
Short name T202
Test name
Test status
Simulation time 3271784838875 ps
CPU time 622.54 seconds
Started Mar 19 12:39:47 PM PDT 24
Finished Mar 19 12:50:10 PM PDT 24
Peak memory 190740 kb
Host smart-0c290d78-c3e4-4417-9966-b51c3cf94a17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543136933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1543136933
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.658328612
Short name T212
Test name
Test status
Simulation time 57597252963 ps
CPU time 107.16 seconds
Started Mar 19 12:38:44 PM PDT 24
Finished Mar 19 12:40:31 PM PDT 24
Peak memory 194336 kb
Host smart-127facdc-1fe3-49f2-aae9-6838385bd126
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658328612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.
658328612
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/187.rv_timer_random.1316805760
Short name T293
Test name
Test status
Simulation time 853257090299 ps
CPU time 2729.73 seconds
Started Mar 19 12:39:56 PM PDT 24
Finished Mar 19 01:25:26 PM PDT 24
Peak memory 190740 kb
Host smart-6e234f78-3308-4389-afa0-621e9290b517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316805760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1316805760
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.3422764436
Short name T170
Test name
Test status
Simulation time 875381735616 ps
CPU time 322 seconds
Started Mar 19 12:39:53 PM PDT 24
Finished Mar 19 12:45:16 PM PDT 24
Peak memory 190748 kb
Host smart-747f1c94-5751-47ed-9a38-dcb4d5866c60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422764436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3422764436
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.2853708540
Short name T345
Test name
Test status
Simulation time 39816422623 ps
CPU time 74.73 seconds
Started Mar 19 12:39:54 PM PDT 24
Finished Mar 19 12:41:09 PM PDT 24
Peak memory 190768 kb
Host smart-86329d53-beb4-4f06-b90d-df6b70c377ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853708540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2853708540
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.990582835
Short name T124
Test name
Test status
Simulation time 332940014752 ps
CPU time 404.99 seconds
Started Mar 19 12:38:48 PM PDT 24
Finished Mar 19 12:45:33 PM PDT 24
Peak memory 190784 kb
Host smart-8ef04c18-96d7-47d6-ab99-f97263352226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990582835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.990582835
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.277364273
Short name T239
Test name
Test status
Simulation time 76103997589 ps
CPU time 59.66 seconds
Started Mar 19 12:38:49 PM PDT 24
Finished Mar 19 12:39:49 PM PDT 24
Peak memory 190752 kb
Host smart-33d37946-2360-46f1-a8b7-61f875677afb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277364273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.
277364273
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3044905231
Short name T296
Test name
Test status
Simulation time 97331075467 ps
CPU time 613.74 seconds
Started Mar 19 12:38:50 PM PDT 24
Finished Mar 19 12:49:03 PM PDT 24
Peak memory 194304 kb
Host smart-34cb1717-79d7-468d-a1a6-3ed82a98e0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044905231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3044905231
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2270115565
Short name T213
Test name
Test status
Simulation time 570581499597 ps
CPU time 3129.61 seconds
Started Mar 19 12:38:46 PM PDT 24
Finished Mar 19 01:30:56 PM PDT 24
Peak memory 190748 kb
Host smart-41424c3b-d3a2-4d54-9336-b20e98bc0491
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270115565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2270115565
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_random.580707736
Short name T71
Test name
Test status
Simulation time 149357640810 ps
CPU time 254.5 seconds
Started Mar 19 12:38:48 PM PDT 24
Finished Mar 19 12:43:03 PM PDT 24
Peak memory 190720 kb
Host smart-8cb188c4-2894-44f1-b962-4acad427e46f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580707736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.580707736
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random.1864848599
Short name T332
Test name
Test status
Simulation time 147238913786 ps
CPU time 358.7 seconds
Started Mar 19 12:39:02 PM PDT 24
Finished Mar 19 12:45:01 PM PDT 24
Peak memory 190848 kb
Host smart-3c7b7b5e-41e1-4027-b39a-8ac8cc02fc00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864848599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1864848599
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3611980308
Short name T122
Test name
Test status
Simulation time 44412252 ps
CPU time 0.81 seconds
Started Mar 19 12:35:50 PM PDT 24
Finished Mar 19 12:35:51 PM PDT 24
Peak memory 193560 kb
Host smart-8ff9ff1c-56e3-4951-9971-bd8afe376f20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611980308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3611980308
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2102324342
Short name T82
Test name
Test status
Simulation time 133299396439 ps
CPU time 127.34 seconds
Started Mar 19 12:38:25 PM PDT 24
Finished Mar 19 12:40:32 PM PDT 24
Peak memory 182552 kb
Host smart-6cfbf83e-c1a2-4223-8e0a-1b774800c166
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102324342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2102324342
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/101.rv_timer_random.998782574
Short name T325
Test name
Test status
Simulation time 9316681666 ps
CPU time 16.66 seconds
Started Mar 19 12:39:15 PM PDT 24
Finished Mar 19 12:39:32 PM PDT 24
Peak memory 182640 kb
Host smart-6c1ac752-2309-42e8-b554-3d47bb10d186
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998782574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.998782574
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1057888918
Short name T275
Test name
Test status
Simulation time 499429633056 ps
CPU time 334.04 seconds
Started Mar 19 12:39:22 PM PDT 24
Finished Mar 19 12:44:56 PM PDT 24
Peak memory 192988 kb
Host smart-7e1b25fa-fb60-4ba6-b3f1-70dabb4d0b1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057888918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1057888918
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.339849602
Short name T167
Test name
Test status
Simulation time 501406754141 ps
CPU time 277.22 seconds
Started Mar 19 12:38:34 PM PDT 24
Finished Mar 19 12:43:11 PM PDT 24
Peak memory 182556 kb
Host smart-c411d2b1-bd32-4a6d-a5ae-0ae9d3dd4a39
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339849602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.rv_timer_cfg_update_on_fly.339849602
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.892865017
Short name T311
Test name
Test status
Simulation time 29114342456 ps
CPU time 222.59 seconds
Started Mar 19 12:38:34 PM PDT 24
Finished Mar 19 12:42:16 PM PDT 24
Peak memory 182596 kb
Host smart-917f4c90-4ac6-4956-85d2-28e0f9a3d9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892865017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.892865017
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.2361194279
Short name T227
Test name
Test status
Simulation time 255297085453 ps
CPU time 404.89 seconds
Started Mar 19 12:38:36 PM PDT 24
Finished Mar 19 12:45:21 PM PDT 24
Peak memory 182552 kb
Host smart-01147bad-f8cf-4e6b-b7d1-278efc6eac83
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361194279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.2361194279
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/120.rv_timer_random.2115993094
Short name T180
Test name
Test status
Simulation time 79096599752 ps
CPU time 137.25 seconds
Started Mar 19 12:39:27 PM PDT 24
Finished Mar 19 12:41:45 PM PDT 24
Peak memory 190740 kb
Host smart-63558cd9-dee7-4bdc-ba00-50fa43a5574c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115993094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2115993094
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.2823220356
Short name T215
Test name
Test status
Simulation time 128764720332 ps
CPU time 191.72 seconds
Started Mar 19 12:39:33 PM PDT 24
Finished Mar 19 12:42:45 PM PDT 24
Peak memory 190800 kb
Host smart-d9a8f296-8d58-4cae-92b8-53f64716f34d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823220356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2823220356
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.1838749768
Short name T285
Test name
Test status
Simulation time 18536247025 ps
CPU time 17.99 seconds
Started Mar 19 12:39:37 PM PDT 24
Finished Mar 19 12:39:55 PM PDT 24
Peak memory 182532 kb
Host smart-1eeb97cc-cbfb-48bd-983a-8f0c5360999e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838749768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1838749768
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2576108245
Short name T178
Test name
Test status
Simulation time 56057045423 ps
CPU time 14.91 seconds
Started Mar 19 12:39:46 PM PDT 24
Finished Mar 19 12:40:01 PM PDT 24
Peak memory 182492 kb
Host smart-b87bd586-f189-4234-891a-2b58596689f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576108245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2576108245
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1896482109
Short name T327
Test name
Test status
Simulation time 215886709975 ps
CPU time 205.98 seconds
Started Mar 19 12:39:47 PM PDT 24
Finished Mar 19 12:43:13 PM PDT 24
Peak memory 190760 kb
Host smart-ccf5746c-a2eb-4c72-a601-6b7bdc9c0147
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896482109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1896482109
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.4244412546
Short name T175
Test name
Test status
Simulation time 344474254590 ps
CPU time 316.03 seconds
Started Mar 19 12:39:59 PM PDT 24
Finished Mar 19 12:45:16 PM PDT 24
Peak memory 190780 kb
Host smart-93205b0c-b0b0-4df3-8f57-effe11af2214
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244412546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.4244412546
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1882573345
Short name T44
Test name
Test status
Simulation time 70668412012 ps
CPU time 87.36 seconds
Started Mar 19 12:39:55 PM PDT 24
Finished Mar 19 12:41:23 PM PDT 24
Peak memory 182488 kb
Host smart-dd3fcdb9-1cea-46b1-a170-706da7970a81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882573345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1882573345
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.2213515761
Short name T189
Test name
Test status
Simulation time 18636130885 ps
CPU time 145.58 seconds
Started Mar 19 12:38:48 PM PDT 24
Finished Mar 19 12:41:14 PM PDT 24
Peak memory 182544 kb
Host smart-f4afba57-8353-4d7e-98ea-694e25d199ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213515761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2213515761
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.1313424430
Short name T110
Test name
Test status
Simulation time 64221830321 ps
CPU time 99.99 seconds
Started Mar 19 12:39:53 PM PDT 24
Finished Mar 19 12:41:34 PM PDT 24
Peak memory 194352 kb
Host smart-50b8c1b2-f2ad-4ad7-bf72-3290fca51b5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313424430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.1313424430
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random.4159634863
Short name T344
Test name
Test status
Simulation time 34776621384 ps
CPU time 242.43 seconds
Started Mar 19 12:38:28 PM PDT 24
Finished Mar 19 12:42:31 PM PDT 24
Peak memory 194068 kb
Host smart-3d45d639-48c6-4ec8-9d1d-2954dcf705dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159634863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.4159634863
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random.1762191651
Short name T151
Test name
Test status
Simulation time 1054768188616 ps
CPU time 380.2 seconds
Started Mar 19 12:38:43 PM PDT 24
Finished Mar 19 12:45:04 PM PDT 24
Peak memory 190776 kb
Host smart-725a188e-ed7c-4feb-bfe7-3bd2dd8f3be8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762191651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1762191651
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random.1899122666
Short name T223
Test name
Test status
Simulation time 1624146372957 ps
CPU time 581.97 seconds
Started Mar 19 12:38:44 PM PDT 24
Finished Mar 19 12:48:27 PM PDT 24
Peak memory 190736 kb
Host smart-755cdba5-51d3-41f3-a756-94c6edad7694
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899122666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1899122666
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1480858997
Short name T265
Test name
Test status
Simulation time 1453975939014 ps
CPU time 752.3 seconds
Started Mar 19 12:38:49 PM PDT 24
Finished Mar 19 12:51:22 PM PDT 24
Peak memory 182612 kb
Host smart-76696a78-2af5-4e04-96d1-e0846ebcfda2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480858997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1480858997
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_random.475343308
Short name T253
Test name
Test status
Simulation time 304037985062 ps
CPU time 443.04 seconds
Started Mar 19 12:38:49 PM PDT 24
Finished Mar 19 12:46:12 PM PDT 24
Peak memory 192864 kb
Host smart-0f2e0861-e19f-4e03-a482-2e7dc44f4328
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475343308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.475343308
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.303442762
Short name T334
Test name
Test status
Simulation time 264390516673 ps
CPU time 642.39 seconds
Started Mar 19 12:38:49 PM PDT 24
Finished Mar 19 12:49:31 PM PDT 24
Peak memory 190752 kb
Host smart-b428f0d6-13ac-4638-9d85-f92cfb5f3a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303442762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.303442762
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.2455884981
Short name T257
Test name
Test status
Simulation time 920236890851 ps
CPU time 396.45 seconds
Started Mar 19 12:38:51 PM PDT 24
Finished Mar 19 12:45:27 PM PDT 24
Peak memory 182532 kb
Host smart-03ed7850-b075-408f-a276-58b02399f412
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455884981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.2455884981
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2211100518
Short name T279
Test name
Test status
Simulation time 1379853323709 ps
CPU time 707.68 seconds
Started Mar 19 12:38:55 PM PDT 24
Finished Mar 19 12:50:43 PM PDT 24
Peak memory 182560 kb
Host smart-58156869-f721-4d10-afb0-379a4c1be0ed
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211100518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2211100518
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.2858297785
Short name T252
Test name
Test status
Simulation time 3770336876046 ps
CPU time 1144.81 seconds
Started Mar 19 12:38:54 PM PDT 24
Finished Mar 19 12:57:59 PM PDT 24
Peak memory 190752 kb
Host smart-4485e013-9bae-415a-aa84-2f3f745ce38a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858297785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.2858297785
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_random.2240840760
Short name T323
Test name
Test status
Simulation time 195103094981 ps
CPU time 91.89 seconds
Started Mar 19 12:38:26 PM PDT 24
Finished Mar 19 12:39:58 PM PDT 24
Peak memory 190728 kb
Host smart-64f742c3-e60a-4536-8de1-c62df397d983
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240840760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2240840760
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.1339387480
Short name T11
Test name
Test status
Simulation time 68746150322 ps
CPU time 704.45 seconds
Started Mar 19 12:39:00 PM PDT 24
Finished Mar 19 12:50:45 PM PDT 24
Peak memory 182596 kb
Host smart-e407ea37-cdee-4136-a529-daeda396fddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339387480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1339387480
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_random.4013542494
Short name T186
Test name
Test status
Simulation time 188631055512 ps
CPU time 554.52 seconds
Started Mar 19 12:39:04 PM PDT 24
Finished Mar 19 12:48:19 PM PDT 24
Peak memory 190732 kb
Host smart-adb438cb-c614-443a-a9ac-bffd8e4f0bac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013542494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.4013542494
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2724735812
Short name T153
Test name
Test status
Simulation time 913478970295 ps
CPU time 434.49 seconds
Started Mar 19 12:39:06 PM PDT 24
Finished Mar 19 12:46:21 PM PDT 24
Peak memory 194964 kb
Host smart-471581c4-8748-4dfc-90aa-b78705486a30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724735812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2724735812
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/65.rv_timer_random.4135906714
Short name T50
Test name
Test status
Simulation time 361680905368 ps
CPU time 2062.86 seconds
Started Mar 19 12:39:10 PM PDT 24
Finished Mar 19 01:13:34 PM PDT 24
Peak memory 190796 kb
Host smart-2d7fe3c2-b70b-4434-a480-2e9c7f5deb8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135906714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.4135906714
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random.3622667725
Short name T260
Test name
Test status
Simulation time 141042831699 ps
CPU time 144.25 seconds
Started Mar 19 12:38:36 PM PDT 24
Finished Mar 19 12:41:00 PM PDT 24
Peak memory 190696 kb
Host smart-d8a068e9-5267-411a-948f-c1b2f297b4fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622667725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3622667725
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.904200834
Short name T43
Test name
Test status
Simulation time 119366967215 ps
CPU time 359.85 seconds
Started Mar 19 12:39:13 PM PDT 24
Finished Mar 19 12:45:13 PM PDT 24
Peak memory 190772 kb
Host smart-e227fbbe-0308-41ce-9e0c-d930dfdad304
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904200834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.904200834
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random.2392663232
Short name T226
Test name
Test status
Simulation time 498192764496 ps
CPU time 366.29 seconds
Started Mar 19 12:38:39 PM PDT 24
Finished Mar 19 12:44:45 PM PDT 24
Peak memory 190732 kb
Host smart-0f2c6e28-4772-4553-8056-e34b876263a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392663232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2392663232
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2483915110
Short name T283
Test name
Test status
Simulation time 136763986876 ps
CPU time 1940.85 seconds
Started Mar 19 12:39:13 PM PDT 24
Finished Mar 19 01:11:34 PM PDT 24
Peak memory 190740 kb
Host smart-661bb872-8b45-49e9-9c4a-77f38a500536
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483915110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2483915110
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2934512591
Short name T98
Test name
Test status
Simulation time 15420723 ps
CPU time 0.67 seconds
Started Mar 19 12:35:51 PM PDT 24
Finished Mar 19 12:35:52 PM PDT 24
Peak memory 182648 kb
Host smart-8f0730df-dc32-4650-af52-c185204126ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934512591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.2934512591
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2453301051
Short name T467
Test name
Test status
Simulation time 1196111786 ps
CPU time 3.67 seconds
Started Mar 19 12:35:51 PM PDT 24
Finished Mar 19 12:35:55 PM PDT 24
Peak memory 191056 kb
Host smart-dfebb639-8d00-4da5-a5c7-82f334aa217a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453301051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.2453301051
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1760898917
Short name T578
Test name
Test status
Simulation time 82586884 ps
CPU time 0.71 seconds
Started Mar 19 12:35:48 PM PDT 24
Finished Mar 19 12:35:48 PM PDT 24
Peak memory 195636 kb
Host smart-2cec5c2a-d7c8-4664-a96a-d545a1c7c23a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760898917 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.1760898917
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.653464897
Short name T80
Test name
Test status
Simulation time 27856977 ps
CPU time 0.59 seconds
Started Mar 19 12:35:53 PM PDT 24
Finished Mar 19 12:35:54 PM PDT 24
Peak memory 191864 kb
Host smart-eb5d40af-1b78-4d06-a2c2-89a0138994c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653464897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.653464897
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3571795278
Short name T476
Test name
Test status
Simulation time 27029745 ps
CPU time 0.53 seconds
Started Mar 19 12:35:50 PM PDT 24
Finished Mar 19 12:35:50 PM PDT 24
Peak memory 182192 kb
Host smart-e6a1fdc4-0c98-49cd-9ce6-4204e565ecdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571795278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3571795278
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2728192854
Short name T556
Test name
Test status
Simulation time 39704871 ps
CPU time 2.01 seconds
Started Mar 19 12:35:51 PM PDT 24
Finished Mar 19 12:35:53 PM PDT 24
Peak memory 197500 kb
Host smart-7f3957c8-4be8-4625-92b2-3eb2168ca1e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728192854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2728192854
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.4191134199
Short name T513
Test name
Test status
Simulation time 104949461 ps
CPU time 1.08 seconds
Started Mar 19 12:35:49 PM PDT 24
Finished Mar 19 12:35:50 PM PDT 24
Peak memory 195164 kb
Host smart-6eaea6ff-63cd-4887-81aa-0607c50c42c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191134199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.4191134199
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.536775940
Short name T545
Test name
Test status
Simulation time 32764940 ps
CPU time 0.74 seconds
Started Mar 19 12:35:50 PM PDT 24
Finished Mar 19 12:35:51 PM PDT 24
Peak memory 192432 kb
Host smart-79723791-653c-493f-bb25-3d45582c8692
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536775940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.536775940
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.313561303
Short name T117
Test name
Test status
Simulation time 383763008 ps
CPU time 2.81 seconds
Started Mar 19 12:35:49 PM PDT 24
Finished Mar 19 12:35:52 PM PDT 24
Peak memory 182756 kb
Host smart-5b68a26b-77bf-47fd-8592-2e15c30a9e88
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313561303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_b
ash.313561303
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1712205755
Short name T542
Test name
Test status
Simulation time 59119017 ps
CPU time 1.07 seconds
Started Mar 19 12:35:51 PM PDT 24
Finished Mar 19 12:35:53 PM PDT 24
Peak memory 197364 kb
Host smart-68dd2c49-e0dc-41d7-a9ec-eae21e3ed00e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712205755 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.1712205755
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1959151772
Short name T577
Test name
Test status
Simulation time 24212230 ps
CPU time 0.57 seconds
Started Mar 19 12:35:49 PM PDT 24
Finished Mar 19 12:35:49 PM PDT 24
Peak memory 182612 kb
Host smart-5c41d840-3f15-414b-a593-02315e80c572
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959151772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1959151772
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.672015490
Short name T535
Test name
Test status
Simulation time 13204338 ps
CPU time 0.55 seconds
Started Mar 19 12:35:50 PM PDT 24
Finished Mar 19 12:35:51 PM PDT 24
Peak memory 182504 kb
Host smart-416cad24-2296-4c34-b8f9-bdd9bdd982fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672015490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.672015490
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.46011986
Short name T566
Test name
Test status
Simulation time 17806887 ps
CPU time 0.75 seconds
Started Mar 19 12:35:48 PM PDT 24
Finished Mar 19 12:35:49 PM PDT 24
Peak memory 193120 kb
Host smart-20c330e6-9933-4981-a701-fa49e87c2f7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46011986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_time
r_same_csr_outstanding.46011986
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2579950312
Short name T509
Test name
Test status
Simulation time 194183964 ps
CPU time 2.01 seconds
Started Mar 19 12:35:49 PM PDT 24
Finished Mar 19 12:35:51 PM PDT 24
Peak memory 197540 kb
Host smart-b1287cf9-db6d-40dc-b10a-3fee7d56aaf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579950312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2579950312
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3857558804
Short name T562
Test name
Test status
Simulation time 69338023 ps
CPU time 1.04 seconds
Started Mar 19 12:35:56 PM PDT 24
Finished Mar 19 12:35:58 PM PDT 24
Peak memory 197328 kb
Host smart-1507858c-7c47-40c0-a932-33fc6ab44a0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857558804 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3857558804
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3841229202
Short name T573
Test name
Test status
Simulation time 20941845 ps
CPU time 0.6 seconds
Started Mar 19 12:35:55 PM PDT 24
Finished Mar 19 12:35:56 PM PDT 24
Peak memory 191932 kb
Host smart-a6b13851-0656-47a6-9dff-8e81d9383666
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841229202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3841229202
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2878753306
Short name T571
Test name
Test status
Simulation time 42805057 ps
CPU time 0.58 seconds
Started Mar 19 12:35:55 PM PDT 24
Finished Mar 19 12:35:56 PM PDT 24
Peak memory 182584 kb
Host smart-5a507a5b-855c-4c94-8511-205f0038b955
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878753306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2878753306
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3644417802
Short name T102
Test name
Test status
Simulation time 48721932 ps
CPU time 0.69 seconds
Started Mar 19 12:35:56 PM PDT 24
Finished Mar 19 12:35:57 PM PDT 24
Peak memory 191676 kb
Host smart-7998b9c9-83a7-450a-a3df-7f558367b95e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644417802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3644417802
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.4144655331
Short name T473
Test name
Test status
Simulation time 308710525 ps
CPU time 1.42 seconds
Started Mar 19 12:35:53 PM PDT 24
Finished Mar 19 12:35:55 PM PDT 24
Peak memory 197272 kb
Host smart-c1dd7bc4-38dd-4d9f-ab05-1177d15bbbcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144655331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.4144655331
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2586791638
Short name T506
Test name
Test status
Simulation time 40623979 ps
CPU time 0.68 seconds
Started Mar 19 12:35:54 PM PDT 24
Finished Mar 19 12:35:55 PM PDT 24
Peak memory 193532 kb
Host smart-ce3a36ed-913e-4445-94ca-1f48d7f6e3d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586791638 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2586791638
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3996274804
Short name T53
Test name
Test status
Simulation time 13957050 ps
CPU time 0.57 seconds
Started Mar 19 12:35:56 PM PDT 24
Finished Mar 19 12:35:57 PM PDT 24
Peak memory 182364 kb
Host smart-f10ec140-014e-464a-acf0-185a5518c320
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996274804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3996274804
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2109157335
Short name T480
Test name
Test status
Simulation time 37559215 ps
CPU time 0.54 seconds
Started Mar 19 12:35:56 PM PDT 24
Finished Mar 19 12:35:57 PM PDT 24
Peak memory 182484 kb
Host smart-f229da2b-29d6-44d5-87a0-4bc683ae622b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109157335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2109157335
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.4053000853
Short name T563
Test name
Test status
Simulation time 76095188 ps
CPU time 0.68 seconds
Started Mar 19 12:35:57 PM PDT 24
Finished Mar 19 12:35:57 PM PDT 24
Peak memory 191996 kb
Host smart-e9afd571-f1f3-482b-be6c-15d3a8e8c49d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053000853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.4053000853
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3358233597
Short name T492
Test name
Test status
Simulation time 241924299 ps
CPU time 1.41 seconds
Started Mar 19 12:35:54 PM PDT 24
Finished Mar 19 12:35:56 PM PDT 24
Peak memory 197592 kb
Host smart-7c2eb746-e4aa-4d90-a907-74130ddbae12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358233597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3358233597
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1384436128
Short name T468
Test name
Test status
Simulation time 67393887 ps
CPU time 0.82 seconds
Started Mar 19 12:35:55 PM PDT 24
Finished Mar 19 12:35:57 PM PDT 24
Peak memory 182896 kb
Host smart-67764994-85a6-4e26-a083-988213b08da2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384436128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.1384436128
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.192434356
Short name T472
Test name
Test status
Simulation time 35400213 ps
CPU time 1.67 seconds
Started Mar 19 12:36:04 PM PDT 24
Finished Mar 19 12:36:06 PM PDT 24
Peak memory 197536 kb
Host smart-604d6831-1300-4865-b69b-bec10e53e63e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192434356 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.192434356
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.223059868
Short name T92
Test name
Test status
Simulation time 17389092 ps
CPU time 0.54 seconds
Started Mar 19 12:35:54 PM PDT 24
Finished Mar 19 12:35:55 PM PDT 24
Peak memory 182636 kb
Host smart-62eea4b9-da4b-434e-9911-4750b37edfe8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223059868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.223059868
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1438634020
Short name T512
Test name
Test status
Simulation time 24252255 ps
CPU time 0.52 seconds
Started Mar 19 12:35:56 PM PDT 24
Finished Mar 19 12:35:57 PM PDT 24
Peak memory 181972 kb
Host smart-aed299e7-f2c2-4535-afe8-0181d3a5afd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438634020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1438634020
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1742582118
Short name T517
Test name
Test status
Simulation time 30083723 ps
CPU time 0.69 seconds
Started Mar 19 12:36:03 PM PDT 24
Finished Mar 19 12:36:03 PM PDT 24
Peak memory 191616 kb
Host smart-d553fc7b-6c8e-4fd7-aaff-a5ecc72d2341
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742582118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1742582118
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.413531222
Short name T522
Test name
Test status
Simulation time 125756195 ps
CPU time 2.59 seconds
Started Mar 19 12:35:59 PM PDT 24
Finished Mar 19 12:36:02 PM PDT 24
Peak memory 197492 kb
Host smart-223730cd-9100-4e68-95df-78e90992032e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413531222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.413531222
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.270284510
Short name T32
Test name
Test status
Simulation time 374461604 ps
CPU time 1.33 seconds
Started Mar 19 12:35:56 PM PDT 24
Finished Mar 19 12:35:58 PM PDT 24
Peak memory 195420 kb
Host smart-1b3b0b68-0f72-4cf8-9353-889e805d7f5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270284510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_in
tg_err.270284510
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.4070386781
Short name T530
Test name
Test status
Simulation time 22084843 ps
CPU time 0.67 seconds
Started Mar 19 12:36:17 PM PDT 24
Finished Mar 19 12:36:17 PM PDT 24
Peak memory 193912 kb
Host smart-e156337a-56ca-4e9d-85ba-c155955456e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070386781 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.4070386781
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1813807031
Short name T100
Test name
Test status
Simulation time 45560407 ps
CPU time 0.61 seconds
Started Mar 19 12:36:03 PM PDT 24
Finished Mar 19 12:36:04 PM PDT 24
Peak memory 191836 kb
Host smart-58c3e366-85ad-4d54-adb7-eaddb508772a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813807031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1813807031
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.291653412
Short name T523
Test name
Test status
Simulation time 13234643 ps
CPU time 0.57 seconds
Started Mar 19 12:36:17 PM PDT 24
Finished Mar 19 12:36:17 PM PDT 24
Peak memory 182564 kb
Host smart-0af7ce61-b67c-44ef-b7ce-6a2ac0dee157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291653412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.291653412
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3036509943
Short name T527
Test name
Test status
Simulation time 13246073 ps
CPU time 0.62 seconds
Started Mar 19 12:36:06 PM PDT 24
Finished Mar 19 12:36:07 PM PDT 24
Peak memory 191904 kb
Host smart-1858f5b9-9e80-467a-8622-f201a6349fb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036509943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.3036509943
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3674324757
Short name T479
Test name
Test status
Simulation time 24363584 ps
CPU time 1.16 seconds
Started Mar 19 12:36:06 PM PDT 24
Finished Mar 19 12:36:08 PM PDT 24
Peak memory 197328 kb
Host smart-bfd0d526-a002-4883-bca8-b8a40fa1c6d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674324757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3674324757
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1529623091
Short name T548
Test name
Test status
Simulation time 263631304 ps
CPU time 0.9 seconds
Started Mar 19 12:36:03 PM PDT 24
Finished Mar 19 12:36:04 PM PDT 24
Peak memory 193812 kb
Host smart-19edc646-e619-4257-ae77-f3a0dafbe669
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529623091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1529623091
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3208185360
Short name T544
Test name
Test status
Simulation time 56766013 ps
CPU time 0.59 seconds
Started Mar 19 12:36:01 PM PDT 24
Finished Mar 19 12:36:01 PM PDT 24
Peak memory 193424 kb
Host smart-3b9389c7-904b-4688-b7f0-e1657577de30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208185360 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.3208185360
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1883792937
Short name T99
Test name
Test status
Simulation time 13194113 ps
CPU time 0.56 seconds
Started Mar 19 12:36:04 PM PDT 24
Finished Mar 19 12:36:05 PM PDT 24
Peak memory 182692 kb
Host smart-adae8667-0b7a-4d86-94d6-4efb7e458a88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883792937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1883792937
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.671272100
Short name T504
Test name
Test status
Simulation time 34156178 ps
CPU time 0.54 seconds
Started Mar 19 12:36:03 PM PDT 24
Finished Mar 19 12:36:04 PM PDT 24
Peak memory 182516 kb
Host smart-746bee86-1b57-4f76-ae9f-0c47784c3a3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671272100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.671272100
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.535130897
Short name T105
Test name
Test status
Simulation time 261115367 ps
CPU time 0.7 seconds
Started Mar 19 12:36:05 PM PDT 24
Finished Mar 19 12:36:06 PM PDT 24
Peak memory 192084 kb
Host smart-e4a0fdc5-1909-495a-9027-199a8a6d1206
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535130897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.535130897
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3588344592
Short name T507
Test name
Test status
Simulation time 51398633 ps
CPU time 1.03 seconds
Started Mar 19 12:36:01 PM PDT 24
Finished Mar 19 12:36:02 PM PDT 24
Peak memory 197416 kb
Host smart-8a369707-5e6a-4704-9587-91c3e52c542b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588344592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3588344592
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2614079476
Short name T487
Test name
Test status
Simulation time 1519600952 ps
CPU time 1.37 seconds
Started Mar 19 12:36:07 PM PDT 24
Finished Mar 19 12:36:09 PM PDT 24
Peak memory 183076 kb
Host smart-86a8f4a9-22bd-4762-8fed-d6330469a1b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614079476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2614079476
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3606347280
Short name T518
Test name
Test status
Simulation time 70860140 ps
CPU time 0.8 seconds
Started Mar 19 12:36:04 PM PDT 24
Finished Mar 19 12:36:06 PM PDT 24
Peak memory 194780 kb
Host smart-d10bba34-38ff-4291-82fb-497551a8e4f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606347280 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3606347280
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.381116756
Short name T91
Test name
Test status
Simulation time 25629593 ps
CPU time 0.65 seconds
Started Mar 19 12:36:03 PM PDT 24
Finished Mar 19 12:36:04 PM PDT 24
Peak memory 182640 kb
Host smart-362fb198-37be-4a65-a723-4b5a63fe5455
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381116756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.381116756
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1171888143
Short name T514
Test name
Test status
Simulation time 66194568 ps
CPU time 0.57 seconds
Started Mar 19 12:36:05 PM PDT 24
Finished Mar 19 12:36:05 PM PDT 24
Peak memory 182524 kb
Host smart-57fd964e-ccff-44a5-b9d8-e70c22beef57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171888143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1171888143
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.130437423
Short name T525
Test name
Test status
Simulation time 39324122 ps
CPU time 0.77 seconds
Started Mar 19 12:36:03 PM PDT 24
Finished Mar 19 12:36:04 PM PDT 24
Peak memory 193244 kb
Host smart-32635be0-cf3a-4471-aa52-669d6024ffec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130437423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.130437423
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3852718862
Short name T503
Test name
Test status
Simulation time 175914978 ps
CPU time 1.17 seconds
Started Mar 19 12:36:17 PM PDT 24
Finished Mar 19 12:36:18 PM PDT 24
Peak memory 197432 kb
Host smart-f2f1addd-58af-4119-8474-4f9fdb1f32f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852718862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3852718862
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2186650843
Short name T524
Test name
Test status
Simulation time 96771107 ps
CPU time 1.42 seconds
Started Mar 19 12:36:03 PM PDT 24
Finished Mar 19 12:36:05 PM PDT 24
Peak memory 194424 kb
Host smart-10c6b8d0-469b-4ab5-8611-9ac0a00a2405
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186650843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2186650843
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.318932983
Short name T516
Test name
Test status
Simulation time 28153667 ps
CPU time 0.84 seconds
Started Mar 19 12:36:06 PM PDT 24
Finished Mar 19 12:36:06 PM PDT 24
Peak memory 195852 kb
Host smart-3a5b4341-764f-48e5-b2b9-3e5481782e14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318932983 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.318932983
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1636211337
Short name T97
Test name
Test status
Simulation time 17955242 ps
CPU time 0.63 seconds
Started Mar 19 12:36:05 PM PDT 24
Finished Mar 19 12:36:06 PM PDT 24
Peak memory 191916 kb
Host smart-583121e2-81ee-4479-ac71-1f622187208f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636211337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1636211337
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2560911337
Short name T461
Test name
Test status
Simulation time 14654365 ps
CPU time 0.53 seconds
Started Mar 19 12:36:17 PM PDT 24
Finished Mar 19 12:36:17 PM PDT 24
Peak memory 181948 kb
Host smart-42492a12-f451-4746-82e3-ff28e5f68aa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560911337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2560911337
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1161742271
Short name T540
Test name
Test status
Simulation time 104431469 ps
CPU time 0.71 seconds
Started Mar 19 12:36:07 PM PDT 24
Finished Mar 19 12:36:08 PM PDT 24
Peak memory 193236 kb
Host smart-a25a00b2-445f-4fc1-84aa-132102d5e3a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161742271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1161742271
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.135602866
Short name T547
Test name
Test status
Simulation time 221193765 ps
CPU time 1.42 seconds
Started Mar 19 12:36:01 PM PDT 24
Finished Mar 19 12:36:02 PM PDT 24
Peak memory 197544 kb
Host smart-0c25e921-50e1-401c-900e-d41c385801e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135602866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.135602866
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.749720730
Short name T505
Test name
Test status
Simulation time 152836888 ps
CPU time 1.1 seconds
Started Mar 19 12:36:04 PM PDT 24
Finished Mar 19 12:36:05 PM PDT 24
Peak memory 195180 kb
Host smart-e41d1d67-4958-49e2-aef4-3abcf5aed855
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749720730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.749720730
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3555639536
Short name T560
Test name
Test status
Simulation time 55879228 ps
CPU time 0.94 seconds
Started Mar 19 12:36:07 PM PDT 24
Finished Mar 19 12:36:08 PM PDT 24
Peak memory 197296 kb
Host smart-0c627141-d07e-4053-87b6-f181cd8c9d67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555639536 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3555639536
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2459920179
Short name T484
Test name
Test status
Simulation time 13285063 ps
CPU time 0.61 seconds
Started Mar 19 12:36:01 PM PDT 24
Finished Mar 19 12:36:02 PM PDT 24
Peak memory 182656 kb
Host smart-82884a52-3bd6-4042-a845-9293a18f5954
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459920179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2459920179
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1594122875
Short name T452
Test name
Test status
Simulation time 44588847 ps
CPU time 0.57 seconds
Started Mar 19 12:36:04 PM PDT 24
Finished Mar 19 12:36:05 PM PDT 24
Peak memory 181992 kb
Host smart-e0a3aa31-88d5-4180-8ca4-5b1f2493ceb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594122875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1594122875
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.392740272
Short name T520
Test name
Test status
Simulation time 62471085 ps
CPU time 0.77 seconds
Started Mar 19 12:36:04 PM PDT 24
Finished Mar 19 12:36:05 PM PDT 24
Peak memory 193192 kb
Host smart-60acb80a-29a1-45cd-b0c9-7bbebad02480
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392740272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti
mer_same_csr_outstanding.392740272
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3557591554
Short name T568
Test name
Test status
Simulation time 128690464 ps
CPU time 2.23 seconds
Started Mar 19 12:36:02 PM PDT 24
Finished Mar 19 12:36:05 PM PDT 24
Peak memory 197520 kb
Host smart-9b3120c4-6c3e-420a-9bef-7e611ff20df9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557591554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3557591554
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1907270918
Short name T121
Test name
Test status
Simulation time 128106003 ps
CPU time 1.12 seconds
Started Mar 19 12:36:02 PM PDT 24
Finished Mar 19 12:36:04 PM PDT 24
Peak memory 194244 kb
Host smart-5da77bdd-7524-4c7f-a836-e9f57bab56bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907270918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1907270918
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.978990404
Short name T478
Test name
Test status
Simulation time 93659649 ps
CPU time 0.93 seconds
Started Mar 19 12:36:13 PM PDT 24
Finished Mar 19 12:36:14 PM PDT 24
Peak memory 196452 kb
Host smart-fb84f429-80e8-42f4-a7a1-d47d988a415b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978990404 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.978990404
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3156088266
Short name T95
Test name
Test status
Simulation time 25002715 ps
CPU time 0.64 seconds
Started Mar 19 12:36:12 PM PDT 24
Finished Mar 19 12:36:13 PM PDT 24
Peak memory 182712 kb
Host smart-1b903ba9-e8a4-4d2a-9a27-08a5dee18d80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156088266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3156088266
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3641121340
Short name T482
Test name
Test status
Simulation time 19160326 ps
CPU time 0.57 seconds
Started Mar 19 12:36:01 PM PDT 24
Finished Mar 19 12:36:02 PM PDT 24
Peak memory 182452 kb
Host smart-c3832a3a-fc5f-45be-8f34-b5a16886d119
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641121340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3641121340
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1294082950
Short name T104
Test name
Test status
Simulation time 27138675 ps
CPU time 0.59 seconds
Started Mar 19 12:36:17 PM PDT 24
Finished Mar 19 12:36:18 PM PDT 24
Peak memory 191308 kb
Host smart-2fdec851-2763-45b6-b0fe-2a3ec59ded2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294082950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1294082950
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2677020383
Short name T569
Test name
Test status
Simulation time 198955548 ps
CPU time 2.72 seconds
Started Mar 19 12:36:02 PM PDT 24
Finished Mar 19 12:36:05 PM PDT 24
Peak memory 197564 kb
Host smart-778c77e5-01f4-4255-b215-6a00763b2c7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677020383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2677020383
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3885506857
Short name T30
Test name
Test status
Simulation time 46166892 ps
CPU time 0.82 seconds
Started Mar 19 12:36:04 PM PDT 24
Finished Mar 19 12:36:05 PM PDT 24
Peak memory 193352 kb
Host smart-a4d86426-95a0-40f9-be42-b3ea3b9f34fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885506857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.3885506857
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.804616154
Short name T515
Test name
Test status
Simulation time 79076580 ps
CPU time 1.07 seconds
Started Mar 19 12:36:12 PM PDT 24
Finished Mar 19 12:36:13 PM PDT 24
Peak memory 197236 kb
Host smart-9037afc2-81a7-4547-8f21-0bad99d33f6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804616154 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.804616154
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.4084147107
Short name T464
Test name
Test status
Simulation time 96725140 ps
CPU time 0.55 seconds
Started Mar 19 12:36:13 PM PDT 24
Finished Mar 19 12:36:13 PM PDT 24
Peak memory 182332 kb
Host smart-2cc76004-6ad3-4b32-86f7-11e261f0f6ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084147107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.4084147107
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2778206492
Short name T570
Test name
Test status
Simulation time 19373494 ps
CPU time 0.56 seconds
Started Mar 19 12:36:10 PM PDT 24
Finished Mar 19 12:36:11 PM PDT 24
Peak memory 182544 kb
Host smart-5d24b43f-3e27-410c-a9b6-faf750f03074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778206492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2778206492
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.878873360
Short name T536
Test name
Test status
Simulation time 37834863 ps
CPU time 0.77 seconds
Started Mar 19 12:36:09 PM PDT 24
Finished Mar 19 12:36:10 PM PDT 24
Peak memory 193404 kb
Host smart-9ecb1bdd-ddf8-49c0-8bb3-c8febe4d970e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878873360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_ti
mer_same_csr_outstanding.878873360
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1417263832
Short name T538
Test name
Test status
Simulation time 162350822 ps
CPU time 1.73 seconds
Started Mar 19 12:36:13 PM PDT 24
Finished Mar 19 12:36:15 PM PDT 24
Peak memory 197540 kb
Host smart-6a7f997e-fca0-4bb5-875a-83e8d34f2013
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417263832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1417263832
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2898530565
Short name T554
Test name
Test status
Simulation time 116647237 ps
CPU time 1.34 seconds
Started Mar 19 12:36:12 PM PDT 24
Finished Mar 19 12:36:13 PM PDT 24
Peak memory 195132 kb
Host smart-ff418e1a-17da-4133-a963-a9a01e810dbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898530565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2898530565
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1267711150
Short name T490
Test name
Test status
Simulation time 63852762 ps
CPU time 0.61 seconds
Started Mar 19 12:35:51 PM PDT 24
Finished Mar 19 12:35:51 PM PDT 24
Peak memory 182632 kb
Host smart-71390ecd-55c5-4ca1-a474-7ef79ebbb3d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267711150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1267711150
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1249129230
Short name T521
Test name
Test status
Simulation time 143479777 ps
CPU time 1.6 seconds
Started Mar 19 12:35:49 PM PDT 24
Finished Mar 19 12:35:51 PM PDT 24
Peak memory 191056 kb
Host smart-fc1eecf9-bf2a-4ffb-b128-b831eddeb575
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249129230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1249129230
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.242500885
Short name T575
Test name
Test status
Simulation time 43137879 ps
CPU time 0.59 seconds
Started Mar 19 12:35:57 PM PDT 24
Finished Mar 19 12:35:58 PM PDT 24
Peak memory 182764 kb
Host smart-d375743c-7576-4a90-8ce3-756a898a175d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242500885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.242500885
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3792559816
Short name T526
Test name
Test status
Simulation time 37547221 ps
CPU time 0.89 seconds
Started Mar 19 12:35:49 PM PDT 24
Finished Mar 19 12:35:50 PM PDT 24
Peak memory 196444 kb
Host smart-71727342-bf09-4581-ab19-7fcfe53d12c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792559816 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3792559816
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2168345901
Short name T534
Test name
Test status
Simulation time 36609467 ps
CPU time 0.58 seconds
Started Mar 19 12:35:48 PM PDT 24
Finished Mar 19 12:35:49 PM PDT 24
Peak memory 182616 kb
Host smart-61f98f39-97c1-4b42-9e6e-fa971810c8bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168345901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2168345901
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2847192984
Short name T555
Test name
Test status
Simulation time 15168266 ps
CPU time 0.61 seconds
Started Mar 19 12:35:49 PM PDT 24
Finished Mar 19 12:35:50 PM PDT 24
Peak memory 182560 kb
Host smart-478b77d5-bb92-4db1-9ace-2ccb0dd6ab82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847192984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2847192984
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2601120767
Short name T529
Test name
Test status
Simulation time 140234433 ps
CPU time 0.79 seconds
Started Mar 19 12:35:48 PM PDT 24
Finished Mar 19 12:35:49 PM PDT 24
Peak memory 191648 kb
Host smart-5ae227a0-cabc-4ad2-826d-ab91c3a5f149
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601120767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2601120767
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1763490845
Short name T454
Test name
Test status
Simulation time 44026391 ps
CPU time 1.06 seconds
Started Mar 19 12:35:49 PM PDT 24
Finished Mar 19 12:35:50 PM PDT 24
Peak memory 196512 kb
Host smart-2a7b902d-8a63-420f-9946-df08986500dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763490845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1763490845
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1730683944
Short name T120
Test name
Test status
Simulation time 204825920 ps
CPU time 1.42 seconds
Started Mar 19 12:35:49 PM PDT 24
Finished Mar 19 12:35:51 PM PDT 24
Peak memory 195272 kb
Host smart-28974d68-79fa-4c69-b6a9-744635aafd89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730683944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.1730683944
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2170405673
Short name T502
Test name
Test status
Simulation time 46608585 ps
CPU time 0.55 seconds
Started Mar 19 12:36:14 PM PDT 24
Finished Mar 19 12:36:14 PM PDT 24
Peak memory 182552 kb
Host smart-bc439205-12c8-4aec-bb50-77a690873a07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170405673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2170405673
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3974742714
Short name T552
Test name
Test status
Simulation time 14987247 ps
CPU time 0.51 seconds
Started Mar 19 12:36:10 PM PDT 24
Finished Mar 19 12:36:11 PM PDT 24
Peak memory 182196 kb
Host smart-9162d797-f930-4e91-9514-480e464e4f70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974742714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3974742714
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2523327870
Short name T497
Test name
Test status
Simulation time 33760128 ps
CPU time 0.55 seconds
Started Mar 19 12:36:13 PM PDT 24
Finished Mar 19 12:36:13 PM PDT 24
Peak memory 182084 kb
Host smart-7de065a8-5b55-4f8e-9967-6f27cba9e2c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523327870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2523327870
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.563234844
Short name T459
Test name
Test status
Simulation time 21056631 ps
CPU time 0.53 seconds
Started Mar 19 12:36:15 PM PDT 24
Finished Mar 19 12:36:16 PM PDT 24
Peak memory 181992 kb
Host smart-14462cfd-0ee0-4f82-a73e-157b8459b819
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563234844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.563234844
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.910401249
Short name T453
Test name
Test status
Simulation time 20655932 ps
CPU time 0.52 seconds
Started Mar 19 12:36:17 PM PDT 24
Finished Mar 19 12:36:17 PM PDT 24
Peak memory 181944 kb
Host smart-96d7d7cb-b416-4a44-9a7c-921021e99586
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910401249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.910401249
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.953313477
Short name T495
Test name
Test status
Simulation time 25065944 ps
CPU time 0.56 seconds
Started Mar 19 12:36:17 PM PDT 24
Finished Mar 19 12:36:18 PM PDT 24
Peak memory 182200 kb
Host smart-5d211d79-1152-4d50-8863-43ca34962e62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953313477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.953313477
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2881311672
Short name T553
Test name
Test status
Simulation time 15057434 ps
CPU time 0.57 seconds
Started Mar 19 12:36:11 PM PDT 24
Finished Mar 19 12:36:12 PM PDT 24
Peak memory 181580 kb
Host smart-ff60d17e-7093-4000-991c-e334a0a7d3c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881311672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2881311672
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1892035309
Short name T565
Test name
Test status
Simulation time 15921835 ps
CPU time 0.57 seconds
Started Mar 19 12:36:13 PM PDT 24
Finished Mar 19 12:36:13 PM PDT 24
Peak memory 182668 kb
Host smart-94a512e7-343e-487d-bfc5-7d87fe3b0c6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892035309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1892035309
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1171082099
Short name T458
Test name
Test status
Simulation time 47033646 ps
CPU time 0.5 seconds
Started Mar 19 12:36:12 PM PDT 24
Finished Mar 19 12:36:12 PM PDT 24
Peak memory 181828 kb
Host smart-59f2351f-1c1b-4f33-b202-8bccad445bb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171082099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1171082099
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.130546922
Short name T533
Test name
Test status
Simulation time 75429066 ps
CPU time 0.52 seconds
Started Mar 19 12:36:13 PM PDT 24
Finished Mar 19 12:36:13 PM PDT 24
Peak memory 181988 kb
Host smart-5ffdfcef-e3ea-468b-a104-6b9377635d3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130546922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.130546922
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3170406751
Short name T93
Test name
Test status
Simulation time 28088770 ps
CPU time 0.78 seconds
Started Mar 19 12:35:47 PM PDT 24
Finished Mar 19 12:35:48 PM PDT 24
Peak memory 191936 kb
Host smart-d1ff4e89-6e8d-4d98-81fc-98c3fbf31a8e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170406751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3170406751
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2933866675
Short name T537
Test name
Test status
Simulation time 788025447 ps
CPU time 3.54 seconds
Started Mar 19 12:35:52 PM PDT 24
Finished Mar 19 12:35:55 PM PDT 24
Peak memory 182856 kb
Host smart-b07c60da-46cd-408b-8d04-db5d80d84987
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933866675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2933866675
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3898678642
Short name T510
Test name
Test status
Simulation time 90859861 ps
CPU time 0.55 seconds
Started Mar 19 12:35:57 PM PDT 24
Finished Mar 19 12:35:57 PM PDT 24
Peak memory 182768 kb
Host smart-137650c7-e776-41ba-9420-82276559be9f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898678642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3898678642
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.932079089
Short name T485
Test name
Test status
Simulation time 28154069 ps
CPU time 1.21 seconds
Started Mar 19 12:35:51 PM PDT 24
Finished Mar 19 12:35:52 PM PDT 24
Peak memory 197508 kb
Host smart-72c20668-1d0c-49a4-946a-dcf953dce9a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932079089 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.932079089
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3543023221
Short name T94
Test name
Test status
Simulation time 73795273 ps
CPU time 0.54 seconds
Started Mar 19 12:35:51 PM PDT 24
Finished Mar 19 12:35:51 PM PDT 24
Peak memory 182628 kb
Host smart-1052fcc0-df5b-4af7-b0aa-b3879297dd0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543023221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3543023221
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2390494260
Short name T501
Test name
Test status
Simulation time 17501880 ps
CPU time 0.55 seconds
Started Mar 19 12:35:51 PM PDT 24
Finished Mar 19 12:35:52 PM PDT 24
Peak memory 182576 kb
Host smart-35939a03-6382-4fb8-8b8d-062f8cbfa57e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390494260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2390494260
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1146236024
Short name T55
Test name
Test status
Simulation time 32537003 ps
CPU time 0.74 seconds
Started Mar 19 12:36:00 PM PDT 24
Finished Mar 19 12:36:01 PM PDT 24
Peak memory 192488 kb
Host smart-90e9db9b-e382-4f20-a687-816b8f55bde3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146236024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1146236024
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.4013393875
Short name T508
Test name
Test status
Simulation time 84206473 ps
CPU time 1.62 seconds
Started Mar 19 12:35:49 PM PDT 24
Finished Mar 19 12:35:51 PM PDT 24
Peak memory 197556 kb
Host smart-5fbea097-64fb-46fb-9f21-5892e6265240
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013393875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.4013393875
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1347687953
Short name T559
Test name
Test status
Simulation time 97605967 ps
CPU time 1.29 seconds
Started Mar 19 12:35:49 PM PDT 24
Finished Mar 19 12:35:50 PM PDT 24
Peak memory 195492 kb
Host smart-1fcd2d9b-bf88-4b0e-b0d7-6e6347424fc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347687953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.1347687953
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3124358469
Short name T474
Test name
Test status
Simulation time 17205180 ps
CPU time 0.62 seconds
Started Mar 19 12:36:14 PM PDT 24
Finished Mar 19 12:36:14 PM PDT 24
Peak memory 182460 kb
Host smart-85132ff3-1df0-4523-b9fd-fef6c33dc534
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124358469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3124358469
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.4127723886
Short name T489
Test name
Test status
Simulation time 25720460 ps
CPU time 0.51 seconds
Started Mar 19 12:36:13 PM PDT 24
Finished Mar 19 12:36:13 PM PDT 24
Peak memory 181996 kb
Host smart-957becd8-8291-4fd4-b41b-fd2de1bb4e87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127723886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.4127723886
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1710891062
Short name T450
Test name
Test status
Simulation time 23846808 ps
CPU time 0.54 seconds
Started Mar 19 12:36:14 PM PDT 24
Finished Mar 19 12:36:15 PM PDT 24
Peak memory 182080 kb
Host smart-fe9b0a79-81dc-485f-a041-5fac906292dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710891062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1710891062
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2808399797
Short name T455
Test name
Test status
Simulation time 17441790 ps
CPU time 0.56 seconds
Started Mar 19 12:36:14 PM PDT 24
Finished Mar 19 12:36:14 PM PDT 24
Peak memory 182500 kb
Host smart-07f03fa0-9b85-4c5f-b982-ffc99b991012
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808399797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.2808399797
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1339024205
Short name T481
Test name
Test status
Simulation time 15253162 ps
CPU time 0.59 seconds
Started Mar 19 12:36:11 PM PDT 24
Finished Mar 19 12:36:11 PM PDT 24
Peak memory 182104 kb
Host smart-643ccc31-a29c-4b41-a77f-e44807985831
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339024205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.1339024205
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.422766725
Short name T567
Test name
Test status
Simulation time 15701677 ps
CPU time 0.54 seconds
Started Mar 19 12:36:10 PM PDT 24
Finished Mar 19 12:36:11 PM PDT 24
Peak memory 182644 kb
Host smart-085e42af-3af3-4a5a-bb99-9ae3f6241705
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422766725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.422766725
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.4217084553
Short name T462
Test name
Test status
Simulation time 39872553 ps
CPU time 0.57 seconds
Started Mar 19 12:36:11 PM PDT 24
Finished Mar 19 12:36:12 PM PDT 24
Peak memory 182524 kb
Host smart-504d2d36-8079-4242-b4e2-a81c9ecab27e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217084553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.4217084553
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3701421437
Short name T498
Test name
Test status
Simulation time 16312023 ps
CPU time 0.56 seconds
Started Mar 19 12:36:17 PM PDT 24
Finished Mar 19 12:36:18 PM PDT 24
Peak memory 182000 kb
Host smart-857a4af5-b37a-4c73-8c8d-67ca51a41b1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701421437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3701421437
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2975337358
Short name T561
Test name
Test status
Simulation time 12402397 ps
CPU time 0.5 seconds
Started Mar 19 12:36:10 PM PDT 24
Finished Mar 19 12:36:10 PM PDT 24
Peak memory 182004 kb
Host smart-90a3a909-a46c-4e1d-a196-9ccc8a1bbbde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975337358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2975337358
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1977741604
Short name T456
Test name
Test status
Simulation time 53795423 ps
CPU time 0.67 seconds
Started Mar 19 12:36:15 PM PDT 24
Finished Mar 19 12:36:16 PM PDT 24
Peak memory 182484 kb
Host smart-d335fff6-fd4f-4518-928a-44017952f68f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977741604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1977741604
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3473793552
Short name T531
Test name
Test status
Simulation time 26346814 ps
CPU time 0.72 seconds
Started Mar 19 12:35:50 PM PDT 24
Finished Mar 19 12:35:51 PM PDT 24
Peak memory 192268 kb
Host smart-e82aa914-2c1f-4d3e-b1fd-025f7c8585e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473793552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3473793552
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2897420133
Short name T54
Test name
Test status
Simulation time 315559152 ps
CPU time 1.6 seconds
Started Mar 19 12:35:47 PM PDT 24
Finished Mar 19 12:35:49 PM PDT 24
Peak memory 192700 kb
Host smart-42bcd408-a20d-44a0-a4c5-b64b29ba1c8b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897420133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2897420133
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3196661909
Short name T493
Test name
Test status
Simulation time 76422533 ps
CPU time 0.57 seconds
Started Mar 19 12:35:51 PM PDT 24
Finished Mar 19 12:35:52 PM PDT 24
Peak memory 182628 kb
Host smart-49632ed7-d8c6-42e8-a5c4-d090efa26436
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196661909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3196661909
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3125855788
Short name T557
Test name
Test status
Simulation time 191978137 ps
CPU time 0.78 seconds
Started Mar 19 12:35:57 PM PDT 24
Finished Mar 19 12:35:57 PM PDT 24
Peak memory 195340 kb
Host smart-c6f4bbfd-8bd3-41ea-971e-667d18ee33ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125855788 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3125855788
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2486898176
Short name T564
Test name
Test status
Simulation time 39928774 ps
CPU time 0.56 seconds
Started Mar 19 12:35:51 PM PDT 24
Finished Mar 19 12:35:51 PM PDT 24
Peak memory 182628 kb
Host smart-c66cbab0-cae6-4206-8381-6356e6e32d26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486898176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2486898176
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1613945401
Short name T470
Test name
Test status
Simulation time 26624543 ps
CPU time 0.53 seconds
Started Mar 19 12:35:50 PM PDT 24
Finished Mar 19 12:35:50 PM PDT 24
Peak memory 181992 kb
Host smart-bbb4789d-d1c4-48a5-9c05-b00f0b74be11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613945401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1613945401
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1312502697
Short name T546
Test name
Test status
Simulation time 124158649 ps
CPU time 0.66 seconds
Started Mar 19 12:35:51 PM PDT 24
Finished Mar 19 12:35:52 PM PDT 24
Peak memory 192188 kb
Host smart-cc019256-77ce-495b-a0aa-ae6d8590c5c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312502697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.1312502697
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.905482487
Short name T558
Test name
Test status
Simulation time 476925791 ps
CPU time 2.43 seconds
Started Mar 19 12:35:56 PM PDT 24
Finished Mar 19 12:35:59 PM PDT 24
Peak memory 197640 kb
Host smart-12d8e577-24e3-4da8-9fae-ff903a05438a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905482487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.905482487
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2614612802
Short name T541
Test name
Test status
Simulation time 83959852 ps
CPU time 0.84 seconds
Started Mar 19 12:35:49 PM PDT 24
Finished Mar 19 12:35:50 PM PDT 24
Peak memory 193704 kb
Host smart-3b5eee62-65ef-4b38-aadf-b246e17b40ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614612802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2614612802
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1170991394
Short name T543
Test name
Test status
Simulation time 79904526 ps
CPU time 0.57 seconds
Started Mar 19 12:36:12 PM PDT 24
Finished Mar 19 12:36:13 PM PDT 24
Peak memory 182480 kb
Host smart-f0008534-7f0c-4518-b0e1-44d4300bf7bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170991394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1170991394
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.214352628
Short name T539
Test name
Test status
Simulation time 33068217 ps
CPU time 0.56 seconds
Started Mar 19 12:36:13 PM PDT 24
Finished Mar 19 12:36:14 PM PDT 24
Peak memory 181980 kb
Host smart-39e3ba7b-d78e-4463-a2e2-dbf8343e0209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214352628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.214352628
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3325534114
Short name T465
Test name
Test status
Simulation time 27653323 ps
CPU time 0.52 seconds
Started Mar 19 12:36:11 PM PDT 24
Finished Mar 19 12:36:12 PM PDT 24
Peak memory 182144 kb
Host smart-f298f7fa-8146-40a3-9479-8a3d4e26a2a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325534114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3325534114
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1529131895
Short name T551
Test name
Test status
Simulation time 15592284 ps
CPU time 0.55 seconds
Started Mar 19 12:36:12 PM PDT 24
Finished Mar 19 12:36:13 PM PDT 24
Peak memory 181996 kb
Host smart-6495a899-04a1-4050-a2ce-00494f1ebf2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529131895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1529131895
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1761435420
Short name T488
Test name
Test status
Simulation time 18312656 ps
CPU time 0.59 seconds
Started Mar 19 12:36:17 PM PDT 24
Finished Mar 19 12:36:17 PM PDT 24
Peak memory 182488 kb
Host smart-07709684-fdb9-4f66-917b-8a16ca963c34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761435420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1761435420
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3531280287
Short name T579
Test name
Test status
Simulation time 122810059 ps
CPU time 0.57 seconds
Started Mar 19 12:36:22 PM PDT 24
Finished Mar 19 12:36:23 PM PDT 24
Peak memory 182476 kb
Host smart-1240e80e-bf3e-4be4-967f-45deeea16407
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531280287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3531280287
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3274992734
Short name T572
Test name
Test status
Simulation time 53763309 ps
CPU time 0.56 seconds
Started Mar 19 12:36:24 PM PDT 24
Finished Mar 19 12:36:25 PM PDT 24
Peak memory 182524 kb
Host smart-c2b83508-9e99-4eab-8064-d34a9fb289d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274992734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3274992734
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1061415740
Short name T549
Test name
Test status
Simulation time 12864204 ps
CPU time 0.59 seconds
Started Mar 19 12:36:22 PM PDT 24
Finished Mar 19 12:36:23 PM PDT 24
Peak memory 182524 kb
Host smart-8319c1d1-3ddd-4b26-991d-bd93df9642ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061415740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1061415740
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.351446319
Short name T457
Test name
Test status
Simulation time 15049057 ps
CPU time 0.57 seconds
Started Mar 19 12:36:26 PM PDT 24
Finished Mar 19 12:36:27 PM PDT 24
Peak memory 182560 kb
Host smart-f4098d8c-2a43-4f8e-9cfc-dd068c9da705
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351446319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.351446319
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1378033750
Short name T499
Test name
Test status
Simulation time 18611333 ps
CPU time 0.54 seconds
Started Mar 19 12:36:25 PM PDT 24
Finished Mar 19 12:36:26 PM PDT 24
Peak memory 182112 kb
Host smart-dd4c9f31-4caa-49b6-b932-4923fb542a5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378033750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1378033750
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.349009013
Short name T477
Test name
Test status
Simulation time 17910143 ps
CPU time 0.79 seconds
Started Mar 19 12:35:53 PM PDT 24
Finished Mar 19 12:35:54 PM PDT 24
Peak memory 195936 kb
Host smart-d016db03-fbd9-4b0b-8d39-36bd834ca7f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349009013 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.349009013
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1384039746
Short name T519
Test name
Test status
Simulation time 37631689 ps
CPU time 0.6 seconds
Started Mar 19 12:36:00 PM PDT 24
Finished Mar 19 12:36:00 PM PDT 24
Peak memory 182304 kb
Host smart-9921fdfe-12c2-4304-9371-e690292e0c1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384039746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1384039746
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3991412399
Short name T500
Test name
Test status
Simulation time 13406234 ps
CPU time 0.59 seconds
Started Mar 19 12:35:51 PM PDT 24
Finished Mar 19 12:35:52 PM PDT 24
Peak memory 182168 kb
Host smart-f3cf6706-9dac-4a8d-adae-8fe280b64666
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991412399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.3991412399
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2258643143
Short name T576
Test name
Test status
Simulation time 65753074 ps
CPU time 0.88 seconds
Started Mar 19 12:36:00 PM PDT 24
Finished Mar 19 12:36:01 PM PDT 24
Peak memory 193992 kb
Host smart-3a6d2c92-e251-47d8-9adb-9157099f5f32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258643143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2258643143
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.86647013
Short name T511
Test name
Test status
Simulation time 204510493 ps
CPU time 1.32 seconds
Started Mar 19 12:35:52 PM PDT 24
Finished Mar 19 12:35:54 PM PDT 24
Peak memory 197504 kb
Host smart-ed1b4701-791b-4a41-a199-8ea34bf562a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86647013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.86647013
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2267377380
Short name T66
Test name
Test status
Simulation time 460387577 ps
CPU time 1.51 seconds
Started Mar 19 12:35:59 PM PDT 24
Finished Mar 19 12:36:01 PM PDT 24
Peak memory 194272 kb
Host smart-e2d8b936-e95e-47fd-ade8-f8d26fe882f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267377380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.2267377380
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.468690065
Short name T460
Test name
Test status
Simulation time 167090880 ps
CPU time 1.44 seconds
Started Mar 19 12:35:54 PM PDT 24
Finished Mar 19 12:35:56 PM PDT 24
Peak memory 197528 kb
Host smart-27c26b4d-b02c-4a89-8e4d-b2f27b7e5407
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468690065 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.468690065
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.772393789
Short name T491
Test name
Test status
Simulation time 11988249 ps
CPU time 0.52 seconds
Started Mar 19 12:35:53 PM PDT 24
Finished Mar 19 12:35:54 PM PDT 24
Peak memory 182424 kb
Host smart-3ca3181d-c1aa-4e00-a365-a6c513f176bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772393789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.772393789
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.883332438
Short name T469
Test name
Test status
Simulation time 35692465 ps
CPU time 0.57 seconds
Started Mar 19 12:35:56 PM PDT 24
Finished Mar 19 12:35:57 PM PDT 24
Peak memory 182520 kb
Host smart-6c76cc01-cb6f-4d54-bdca-014fcafbaa29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883332438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.883332438
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.510701340
Short name T34
Test name
Test status
Simulation time 19213147 ps
CPU time 0.78 seconds
Started Mar 19 12:35:56 PM PDT 24
Finished Mar 19 12:35:57 PM PDT 24
Peak memory 193240 kb
Host smart-30098379-bb69-41f6-a56e-905987fed2b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510701340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.510701340
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2501102398
Short name T463
Test name
Test status
Simulation time 157121206 ps
CPU time 1.66 seconds
Started Mar 19 12:35:49 PM PDT 24
Finished Mar 19 12:35:50 PM PDT 24
Peak memory 197504 kb
Host smart-9d7efecf-21a6-4d2a-bca2-42bef3ff062c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501102398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2501102398
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.91536545
Short name T494
Test name
Test status
Simulation time 256913444 ps
CPU time 1.11 seconds
Started Mar 19 12:35:51 PM PDT 24
Finished Mar 19 12:35:52 PM PDT 24
Peak memory 183244 kb
Host smart-be6b1c28-5f48-41b7-ac46-13f3f93eca89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91536545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_intg
_err.91536545
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.714394019
Short name T33
Test name
Test status
Simulation time 28411642 ps
CPU time 0.77 seconds
Started Mar 19 12:35:56 PM PDT 24
Finished Mar 19 12:35:57 PM PDT 24
Peak memory 195552 kb
Host smart-a591a18e-9f96-4ec6-bf62-3c17ac02ce24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714394019 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.714394019
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2819434463
Short name T532
Test name
Test status
Simulation time 17237422 ps
CPU time 0.58 seconds
Started Mar 19 12:35:57 PM PDT 24
Finished Mar 19 12:35:57 PM PDT 24
Peak memory 182636 kb
Host smart-fe14c771-927e-4f64-a4b3-2f7f7202e68d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819434463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2819434463
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.451849460
Short name T475
Test name
Test status
Simulation time 134064897 ps
CPU time 0.61 seconds
Started Mar 19 12:35:56 PM PDT 24
Finished Mar 19 12:35:56 PM PDT 24
Peak memory 182636 kb
Host smart-0667d639-1522-4ad6-b011-34d20c4a0491
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451849460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.451849460
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2972041934
Short name T101
Test name
Test status
Simulation time 67005624 ps
CPU time 0.77 seconds
Started Mar 19 12:35:55 PM PDT 24
Finished Mar 19 12:35:56 PM PDT 24
Peak memory 191656 kb
Host smart-5a326345-b6c5-4d71-b968-565dd2d1ebff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972041934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2972041934
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.653365768
Short name T550
Test name
Test status
Simulation time 555497579 ps
CPU time 2.4 seconds
Started Mar 19 12:35:55 PM PDT 24
Finished Mar 19 12:35:57 PM PDT 24
Peak memory 197568 kb
Host smart-f595cd06-2d3d-4346-b613-74a2a5caa3c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653365768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.653365768
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3413205648
Short name T471
Test name
Test status
Simulation time 290478950 ps
CPU time 1.17 seconds
Started Mar 19 12:36:00 PM PDT 24
Finished Mar 19 12:36:01 PM PDT 24
Peak memory 183132 kb
Host smart-475e5784-57c6-45aa-aea4-05b842a548e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413205648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3413205648
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3417570846
Short name T496
Test name
Test status
Simulation time 57321924 ps
CPU time 0.71 seconds
Started Mar 19 12:35:54 PM PDT 24
Finished Mar 19 12:35:55 PM PDT 24
Peak memory 195328 kb
Host smart-adb7a0fc-b834-4002-89e3-e46067744319
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417570846 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3417570846
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2224174707
Short name T486
Test name
Test status
Simulation time 33380345 ps
CPU time 0.55 seconds
Started Mar 19 12:35:57 PM PDT 24
Finished Mar 19 12:35:58 PM PDT 24
Peak memory 182628 kb
Host smart-2ec9025c-e20d-462b-b02e-80b4d97913b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224174707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2224174707
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1058130855
Short name T574
Test name
Test status
Simulation time 22966265 ps
CPU time 0.55 seconds
Started Mar 19 12:35:56 PM PDT 24
Finished Mar 19 12:35:57 PM PDT 24
Peak memory 181988 kb
Host smart-aaaafb9d-e8a4-4cfd-a233-c6e3784e7ad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058130855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1058130855
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2726558090
Short name T106
Test name
Test status
Simulation time 170967875 ps
CPU time 0.8 seconds
Started Mar 19 12:36:00 PM PDT 24
Finished Mar 19 12:36:01 PM PDT 24
Peak memory 192088 kb
Host smart-0f482e24-07c4-4122-b0a8-4f3dda8953f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726558090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2726558090
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3412160153
Short name T483
Test name
Test status
Simulation time 1992150010 ps
CPU time 2.44 seconds
Started Mar 19 12:35:55 PM PDT 24
Finished Mar 19 12:35:57 PM PDT 24
Peak memory 197628 kb
Host smart-166e3964-1eb2-4fff-969e-903df174e711
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412160153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3412160153
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3001952833
Short name T118
Test name
Test status
Simulation time 47637082 ps
CPU time 0.84 seconds
Started Mar 19 12:36:00 PM PDT 24
Finished Mar 19 12:36:01 PM PDT 24
Peak memory 193680 kb
Host smart-c5bd62a7-b032-41bf-873c-a2fcb0542675
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001952833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.3001952833
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1414455625
Short name T528
Test name
Test status
Simulation time 175426335 ps
CPU time 1.24 seconds
Started Mar 19 12:35:58 PM PDT 24
Finished Mar 19 12:35:59 PM PDT 24
Peak memory 197416 kb
Host smart-0658031e-0558-4d31-803f-8c7fefbfceb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414455625 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1414455625
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2086846617
Short name T96
Test name
Test status
Simulation time 37654581 ps
CPU time 0.55 seconds
Started Mar 19 12:35:57 PM PDT 24
Finished Mar 19 12:35:57 PM PDT 24
Peak memory 182632 kb
Host smart-bccc6336-db00-4a3c-a229-c11e6469069e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086846617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2086846617
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.562111401
Short name T466
Test name
Test status
Simulation time 11391367 ps
CPU time 0.56 seconds
Started Mar 19 12:35:55 PM PDT 24
Finished Mar 19 12:35:55 PM PDT 24
Peak memory 182464 kb
Host smart-feaf87c0-919f-4af9-8743-b74b46f91a9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562111401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.562111401
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1093069666
Short name T52
Test name
Test status
Simulation time 116008682 ps
CPU time 0.74 seconds
Started Mar 19 12:35:57 PM PDT 24
Finished Mar 19 12:35:58 PM PDT 24
Peak memory 191720 kb
Host smart-758daa90-3b61-4d50-a961-4880f6e652fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093069666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1093069666
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1732375787
Short name T451
Test name
Test status
Simulation time 52288210 ps
CPU time 1.27 seconds
Started Mar 19 12:35:56 PM PDT 24
Finished Mar 19 12:35:58 PM PDT 24
Peak memory 197212 kb
Host smart-e8d36eec-f2d2-4957-8b9d-033f7745cd7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732375787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1732375787
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.123368482
Short name T119
Test name
Test status
Simulation time 103866529 ps
CPU time 1.34 seconds
Started Mar 19 12:35:56 PM PDT 24
Finished Mar 19 12:35:57 PM PDT 24
Peak memory 195180 kb
Host smart-fac452fb-efea-4e1d-a228-bde7d4c63f67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123368482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_int
g_err.123368482
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.977091673
Short name T449
Test name
Test status
Simulation time 140856237243 ps
CPU time 105.39 seconds
Started Mar 19 12:38:25 PM PDT 24
Finished Mar 19 12:40:10 PM PDT 24
Peak memory 182608 kb
Host smart-eb1bf20f-f4bd-4dd5-81da-dc0ff7ce1000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977091673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.977091673
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3187612867
Short name T278
Test name
Test status
Simulation time 970665812203 ps
CPU time 273.52 seconds
Started Mar 19 12:38:28 PM PDT 24
Finished Mar 19 12:43:02 PM PDT 24
Peak memory 190736 kb
Host smart-3329642f-4c5b-4a8f-b00c-5ffb2851036e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187612867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3187612867
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2103988638
Short name T312
Test name
Test status
Simulation time 1229113837406 ps
CPU time 575.6 seconds
Started Mar 19 12:38:28 PM PDT 24
Finished Mar 19 12:48:04 PM PDT 24
Peak memory 190716 kb
Host smart-c2dad528-70e5-4912-8aaf-2a6820dd03f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103988638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2103988638
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.1005247058
Short name T362
Test name
Test status
Simulation time 813169487747 ps
CPU time 296.53 seconds
Started Mar 19 12:38:27 PM PDT 24
Finished Mar 19 12:43:23 PM PDT 24
Peak memory 182556 kb
Host smart-cd423644-c09f-4d8b-bf6b-1bdb38941c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005247058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1005247058
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.3000138031
Short name T276
Test name
Test status
Simulation time 32516308694 ps
CPU time 49.29 seconds
Started Mar 19 12:38:28 PM PDT 24
Finished Mar 19 12:39:17 PM PDT 24
Peak memory 190816 kb
Host smart-4ab3168b-9f38-4e22-97db-f62ea96e2a5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000138031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3000138031
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2460413578
Short name T397
Test name
Test status
Simulation time 2829013025 ps
CPU time 5.42 seconds
Started Mar 19 12:38:26 PM PDT 24
Finished Mar 19 12:38:31 PM PDT 24
Peak memory 190744 kb
Host smart-ebf61004-de29-431e-8826-9e37b774e199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460413578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2460413578
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2377064758
Short name T18
Test name
Test status
Simulation time 120384712 ps
CPU time 0.81 seconds
Started Mar 19 12:38:23 PM PDT 24
Finished Mar 19 12:38:24 PM PDT 24
Peak memory 213004 kb
Host smart-293bc155-a467-41b9-ac33-e1fefebc1c3b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377064758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2377064758
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3624616093
Short name T172
Test name
Test status
Simulation time 1651872414835 ps
CPU time 398.59 seconds
Started Mar 19 12:38:40 PM PDT 24
Finished Mar 19 12:45:19 PM PDT 24
Peak memory 182572 kb
Host smart-5ff66677-c8a2-4ca9-abd4-f848814dec83
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624616093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3624616093
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.475837393
Short name T428
Test name
Test status
Simulation time 138906843900 ps
CPU time 192.04 seconds
Started Mar 19 12:38:36 PM PDT 24
Finished Mar 19 12:41:48 PM PDT 24
Peak memory 182528 kb
Host smart-b240bd60-399d-4401-bd42-b1ca6eaae917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475837393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.475837393
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.552721560
Short name T138
Test name
Test status
Simulation time 32057952344 ps
CPU time 55.79 seconds
Started Mar 19 12:38:34 PM PDT 24
Finished Mar 19 12:39:30 PM PDT 24
Peak memory 182552 kb
Host smart-520c72c6-7417-4fe0-96bc-f17d3761cc05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552721560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.552721560
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.696926163
Short name T7
Test name
Test status
Simulation time 34345735623 ps
CPU time 17.4 seconds
Started Mar 19 12:38:36 PM PDT 24
Finished Mar 19 12:38:53 PM PDT 24
Peak memory 194028 kb
Host smart-4780c611-767d-4125-b378-7615d694b0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696926163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.696926163
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3593789547
Short name T228
Test name
Test status
Simulation time 305114614134 ps
CPU time 2193.03 seconds
Started Mar 19 12:38:47 PM PDT 24
Finished Mar 19 01:15:21 PM PDT 24
Peak memory 190844 kb
Host smart-ddb7d7c1-9eaf-4614-9a2e-cd8e5b439d3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593789547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3593789547
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/102.rv_timer_random.3048092487
Short name T89
Test name
Test status
Simulation time 735773698847 ps
CPU time 515.63 seconds
Started Mar 19 12:39:17 PM PDT 24
Finished Mar 19 12:47:53 PM PDT 24
Peak memory 190724 kb
Host smart-caabbdca-789c-46be-a778-165fbed77e10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048092487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3048092487
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.690464192
Short name T422
Test name
Test status
Simulation time 147517572193 ps
CPU time 129.8 seconds
Started Mar 19 12:39:14 PM PDT 24
Finished Mar 19 12:41:24 PM PDT 24
Peak memory 182552 kb
Host smart-fd3d48d0-0c24-4e2b-b415-f636035cd30b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690464192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.690464192
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.55836226
Short name T251
Test name
Test status
Simulation time 103384927354 ps
CPU time 211.95 seconds
Started Mar 19 12:39:23 PM PDT 24
Finished Mar 19 12:42:55 PM PDT 24
Peak memory 190732 kb
Host smart-dd21ddd7-e4d3-49d1-ae6b-6d54e0f5898d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55836226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.55836226
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1362545621
Short name T354
Test name
Test status
Simulation time 174260448368 ps
CPU time 80.06 seconds
Started Mar 19 12:39:22 PM PDT 24
Finished Mar 19 12:40:42 PM PDT 24
Peak memory 182504 kb
Host smart-c87379b7-1350-438c-8423-33923e3b37db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362545621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1362545621
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3596481107
Short name T433
Test name
Test status
Simulation time 29264660845 ps
CPU time 231.96 seconds
Started Mar 19 12:39:22 PM PDT 24
Finished Mar 19 12:43:14 PM PDT 24
Peak memory 182508 kb
Host smart-37a5b609-f6b1-4495-aae0-3e52b1bfb442
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596481107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3596481107
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.1234288458
Short name T408
Test name
Test status
Simulation time 7890515750 ps
CPU time 200.71 seconds
Started Mar 19 12:39:24 PM PDT 24
Finished Mar 19 12:42:45 PM PDT 24
Peak memory 182552 kb
Host smart-7ea72ea8-360e-4426-9388-7d23426cb561
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234288458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1234288458
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.460293761
Short name T308
Test name
Test status
Simulation time 34288319223 ps
CPU time 58.24 seconds
Started Mar 19 12:39:23 PM PDT 24
Finished Mar 19 12:40:22 PM PDT 24
Peak memory 182544 kb
Host smart-3cb83cb0-1555-4ab1-aacd-344a56ad64b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460293761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.460293761
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2404057920
Short name T58
Test name
Test status
Simulation time 5139868843 ps
CPU time 4.39 seconds
Started Mar 19 12:38:35 PM PDT 24
Finished Mar 19 12:38:39 PM PDT 24
Peak memory 182560 kb
Host smart-c21a81b3-ab24-4797-b7d9-c24be97fc093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404057920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2404057920
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.2867130498
Short name T45
Test name
Test status
Simulation time 87523957101 ps
CPU time 121.23 seconds
Started Mar 19 12:38:39 PM PDT 24
Finished Mar 19 12:40:41 PM PDT 24
Peak memory 182552 kb
Host smart-f9b54dfd-540c-4c6b-838f-bcbb171e06d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867130498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2867130498
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.2051078870
Short name T200
Test name
Test status
Simulation time 400391813175 ps
CPU time 880.06 seconds
Started Mar 19 12:38:38 PM PDT 24
Finished Mar 19 12:53:18 PM PDT 24
Peak memory 190708 kb
Host smart-2dfb6dd1-8e3d-4aab-86b1-293eef1e6e1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051078870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.2051078870
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/110.rv_timer_random.3536629361
Short name T165
Test name
Test status
Simulation time 183416650198 ps
CPU time 1455.16 seconds
Started Mar 19 12:39:22 PM PDT 24
Finished Mar 19 01:03:37 PM PDT 24
Peak memory 190744 kb
Host smart-2742afcc-d457-4005-95a6-ff00b77f0ce9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536629361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3536629361
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.1582711451
Short name T294
Test name
Test status
Simulation time 317777190770 ps
CPU time 291.02 seconds
Started Mar 19 12:39:23 PM PDT 24
Finished Mar 19 12:44:14 PM PDT 24
Peak memory 190780 kb
Host smart-06bad75b-28f4-4533-8ed9-c20270e005a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582711451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1582711451
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.2678058355
Short name T303
Test name
Test status
Simulation time 128862767961 ps
CPU time 115.55 seconds
Started Mar 19 12:39:22 PM PDT 24
Finished Mar 19 12:41:18 PM PDT 24
Peak memory 190696 kb
Host smart-17386807-223b-4651-8e80-30ee992b1e97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678058355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2678058355
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.3083694035
Short name T349
Test name
Test status
Simulation time 368698292752 ps
CPU time 182.33 seconds
Started Mar 19 12:39:24 PM PDT 24
Finished Mar 19 12:42:27 PM PDT 24
Peak memory 190740 kb
Host smart-158a0731-e200-4f70-b324-356fdf0492b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083694035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3083694035
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1629007089
Short name T391
Test name
Test status
Simulation time 64421519843 ps
CPU time 1397.54 seconds
Started Mar 19 12:39:29 PM PDT 24
Finished Mar 19 01:02:47 PM PDT 24
Peak memory 182592 kb
Host smart-20da3cba-0ae3-4165-bddb-7b32924d1a25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629007089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1629007089
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.1331930506
Short name T204
Test name
Test status
Simulation time 235396815918 ps
CPU time 772.77 seconds
Started Mar 19 12:39:28 PM PDT 24
Finished Mar 19 12:52:21 PM PDT 24
Peak memory 190752 kb
Host smart-db8552b7-b6f4-4b9e-b557-5505907e5b42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331930506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1331930506
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3027984578
Short name T440
Test name
Test status
Simulation time 560415212767 ps
CPU time 211.89 seconds
Started Mar 19 12:38:33 PM PDT 24
Finished Mar 19 12:42:05 PM PDT 24
Peak memory 182568 kb
Host smart-8652ba9d-43ae-4eea-871e-d9b50ab78f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027984578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3027984578
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.3293723073
Short name T384
Test name
Test status
Simulation time 305361263 ps
CPU time 0.96 seconds
Started Mar 19 12:38:34 PM PDT 24
Finished Mar 19 12:38:35 PM PDT 24
Peak memory 182472 kb
Host smart-48cdeda3-0aaa-4273-90ac-bc8fbac07fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293723073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.3293723073
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2967004751
Short name T383
Test name
Test status
Simulation time 1046967501790 ps
CPU time 375.47 seconds
Started Mar 19 12:38:34 PM PDT 24
Finished Mar 19 12:44:49 PM PDT 24
Peak memory 194184 kb
Host smart-56068b94-6a83-4fbb-baa4-02e2d4beb68d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967004751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2967004751
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/121.rv_timer_random.1681461669
Short name T336
Test name
Test status
Simulation time 138027135306 ps
CPU time 227.08 seconds
Started Mar 19 12:39:29 PM PDT 24
Finished Mar 19 12:43:16 PM PDT 24
Peak memory 190764 kb
Host smart-4846b80b-40f5-441d-b4ac-dc913b9d2751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681461669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1681461669
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.2395331028
Short name T133
Test name
Test status
Simulation time 78771991675 ps
CPU time 129.12 seconds
Started Mar 19 12:39:28 PM PDT 24
Finished Mar 19 12:41:37 PM PDT 24
Peak memory 190748 kb
Host smart-eae543ff-fd9d-4f40-8423-549141d575bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395331028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2395331028
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.2118399547
Short name T250
Test name
Test status
Simulation time 74597260948 ps
CPU time 662.6 seconds
Started Mar 19 12:39:29 PM PDT 24
Finished Mar 19 12:50:32 PM PDT 24
Peak memory 190784 kb
Host smart-246232bc-a9d3-42bf-8f9e-4fa9d7fd0bc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118399547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.2118399547
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2484416877
Short name T150
Test name
Test status
Simulation time 161009083823 ps
CPU time 308.62 seconds
Started Mar 19 12:39:30 PM PDT 24
Finished Mar 19 12:44:39 PM PDT 24
Peak memory 182548 kb
Host smart-1bf4ecd4-aad1-4277-a641-49e7a0d2755e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484416877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2484416877
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.1622450184
Short name T139
Test name
Test status
Simulation time 142681905760 ps
CPU time 113.08 seconds
Started Mar 19 12:39:28 PM PDT 24
Finished Mar 19 12:41:21 PM PDT 24
Peak memory 190748 kb
Host smart-100a2db7-9d7e-4483-863c-c82ae33a4a27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622450184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1622450184
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3290894869
Short name T343
Test name
Test status
Simulation time 45370510477 ps
CPU time 77.37 seconds
Started Mar 19 12:39:26 PM PDT 24
Finished Mar 19 12:40:44 PM PDT 24
Peak memory 193656 kb
Host smart-fcd128d8-b539-4ed5-ac81-6b54a6669595
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290894869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3290894869
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1456895842
Short name T299
Test name
Test status
Simulation time 452657082294 ps
CPU time 1792.48 seconds
Started Mar 19 12:39:30 PM PDT 24
Finished Mar 19 01:09:23 PM PDT 24
Peak memory 190752 kb
Host smart-beb43d6c-1c98-40c8-a3a8-e6e3b6419a2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456895842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1456895842
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.2916780715
Short name T444
Test name
Test status
Simulation time 23945227678 ps
CPU time 502.57 seconds
Started Mar 19 12:39:26 PM PDT 24
Finished Mar 19 12:47:49 PM PDT 24
Peak memory 182552 kb
Host smart-35cb732d-bed7-4376-ab2d-42e373642215
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916780715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2916780715
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.328600516
Short name T420
Test name
Test status
Simulation time 204602080398 ps
CPU time 348.86 seconds
Started Mar 19 12:38:35 PM PDT 24
Finished Mar 19 12:44:24 PM PDT 24
Peak memory 182556 kb
Host smart-637eb4b4-cb97-433a-b2cc-c32431db0baf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328600516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.rv_timer_cfg_update_on_fly.328600516
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2105336172
Short name T62
Test name
Test status
Simulation time 176214092572 ps
CPU time 275.76 seconds
Started Mar 19 12:38:35 PM PDT 24
Finished Mar 19 12:43:11 PM PDT 24
Peak memory 182544 kb
Host smart-6fe402df-d8da-4d00-8285-5bfe5b23e928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105336172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2105336172
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.1164459705
Short name T187
Test name
Test status
Simulation time 1124100806126 ps
CPU time 1419.57 seconds
Started Mar 19 12:38:34 PM PDT 24
Finished Mar 19 01:02:14 PM PDT 24
Peak memory 190752 kb
Host smart-c3f3958d-66fc-4637-8705-d1deb790da9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164459705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.1164459705
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.1640324940
Short name T236
Test name
Test status
Simulation time 181333334392 ps
CPU time 112.48 seconds
Started Mar 19 12:38:34 PM PDT 24
Finished Mar 19 12:40:27 PM PDT 24
Peak memory 192932 kb
Host smart-9b0e8f24-e007-4eb6-a69b-254d46608e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640324940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1640324940
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.3292342958
Short name T142
Test name
Test status
Simulation time 103829165889 ps
CPU time 1563.75 seconds
Started Mar 19 12:39:26 PM PDT 24
Finished Mar 19 01:05:30 PM PDT 24
Peak memory 190788 kb
Host smart-85b342a0-2bd3-4561-a8db-65cb0df0afbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292342958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3292342958
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.1051324167
Short name T21
Test name
Test status
Simulation time 59359578957 ps
CPU time 107.59 seconds
Started Mar 19 12:39:28 PM PDT 24
Finished Mar 19 12:41:16 PM PDT 24
Peak memory 190740 kb
Host smart-2f570f67-ef75-4d6f-abb9-6f002b2694a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051324167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1051324167
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.2434307645
Short name T144
Test name
Test status
Simulation time 583055075858 ps
CPU time 295.49 seconds
Started Mar 19 12:39:25 PM PDT 24
Finished Mar 19 12:44:21 PM PDT 24
Peak memory 192980 kb
Host smart-cee8b129-9b23-4ffd-8ffa-0e4c4b7121d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434307645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2434307645
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.2884749472
Short name T219
Test name
Test status
Simulation time 782339811131 ps
CPU time 228.11 seconds
Started Mar 19 12:39:32 PM PDT 24
Finished Mar 19 12:43:21 PM PDT 24
Peak memory 190744 kb
Host smart-69f064c0-e27e-4a70-bfeb-5a6756c49243
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884749472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2884749472
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3353281251
Short name T193
Test name
Test status
Simulation time 63495359874 ps
CPU time 72.68 seconds
Started Mar 19 12:39:34 PM PDT 24
Finished Mar 19 12:40:47 PM PDT 24
Peak memory 190712 kb
Host smart-8daf53df-2e90-4f3f-a804-69377e308095
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353281251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3353281251
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.250337637
Short name T125
Test name
Test status
Simulation time 921933908892 ps
CPU time 817.99 seconds
Started Mar 19 12:39:32 PM PDT 24
Finished Mar 19 12:53:11 PM PDT 24
Peak memory 190780 kb
Host smart-ba668ba2-fe45-4fb9-829f-31667d4029cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250337637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.250337637
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3660511999
Short name T209
Test name
Test status
Simulation time 52118374788 ps
CPU time 269.43 seconds
Started Mar 19 12:39:33 PM PDT 24
Finished Mar 19 12:44:03 PM PDT 24
Peak memory 190704 kb
Host smart-7eb73f48-692b-4514-873b-45b703bfd8be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660511999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3660511999
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.4033041816
Short name T277
Test name
Test status
Simulation time 118348926601 ps
CPU time 203.33 seconds
Started Mar 19 12:39:32 PM PDT 24
Finished Mar 19 12:42:56 PM PDT 24
Peak memory 194376 kb
Host smart-09e791e2-5a81-4844-928c-a109ac80b2c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033041816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.4033041816
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.4255263609
Short name T346
Test name
Test status
Simulation time 4738415887 ps
CPU time 10.24 seconds
Started Mar 19 12:39:34 PM PDT 24
Finished Mar 19 12:39:45 PM PDT 24
Peak memory 182544 kb
Host smart-8d486621-6628-4423-be3d-0c063605e6e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255263609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.4255263609
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.643029425
Short name T443
Test name
Test status
Simulation time 802004122528 ps
CPU time 106.19 seconds
Started Mar 19 12:38:34 PM PDT 24
Finished Mar 19 12:40:21 PM PDT 24
Peak memory 182532 kb
Host smart-5d2399c1-211c-4bac-b810-08a13a858355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643029425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.643029425
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.1688328714
Short name T321
Test name
Test status
Simulation time 94645664150 ps
CPU time 1718.59 seconds
Started Mar 19 12:38:35 PM PDT 24
Finished Mar 19 01:07:14 PM PDT 24
Peak memory 182560 kb
Host smart-17fac81a-8993-4f7e-9361-73bf6a931a7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688328714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1688328714
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.4281388122
Short name T426
Test name
Test status
Simulation time 48520557 ps
CPU time 0.64 seconds
Started Mar 19 12:38:43 PM PDT 24
Finished Mar 19 12:38:43 PM PDT 24
Peak memory 182288 kb
Host smart-1d9db35a-e20f-42dd-9703-680f8bad4f2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281388122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.4281388122
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.881308545
Short name T281
Test name
Test status
Simulation time 82721365170 ps
CPU time 125.75 seconds
Started Mar 19 12:39:35 PM PDT 24
Finished Mar 19 12:41:41 PM PDT 24
Peak memory 190732 kb
Host smart-e00467c6-2c68-485d-aebe-459a78ede0f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881308545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.881308545
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.1108574986
Short name T333
Test name
Test status
Simulation time 187710393191 ps
CPU time 230.15 seconds
Started Mar 19 12:39:34 PM PDT 24
Finished Mar 19 12:43:25 PM PDT 24
Peak memory 190728 kb
Host smart-d57f9954-0411-4b97-8e17-dcce82f7ba56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108574986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1108574986
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.185691310
Short name T88
Test name
Test status
Simulation time 218635950153 ps
CPU time 984.04 seconds
Started Mar 19 12:39:37 PM PDT 24
Finished Mar 19 12:56:02 PM PDT 24
Peak memory 190764 kb
Host smart-c5caf458-0117-487a-bbc9-6b7fd2e9a658
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185691310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.185691310
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.1488620278
Short name T217
Test name
Test status
Simulation time 118436151656 ps
CPU time 284.78 seconds
Started Mar 19 12:39:40 PM PDT 24
Finished Mar 19 12:44:26 PM PDT 24
Peak memory 190740 kb
Host smart-209e549c-de10-4246-9ca9-6dd78270a982
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488620278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1488620278
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3402917609
Short name T269
Test name
Test status
Simulation time 35959023988 ps
CPU time 59.17 seconds
Started Mar 19 12:39:45 PM PDT 24
Finished Mar 19 12:40:45 PM PDT 24
Peak memory 182572 kb
Host smart-c5a860f5-23cc-412c-a00d-3e5a3aa745b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402917609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3402917609
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.3107833538
Short name T191
Test name
Test status
Simulation time 45944855464 ps
CPU time 23.04 seconds
Started Mar 19 12:38:43 PM PDT 24
Finished Mar 19 12:39:06 PM PDT 24
Peak memory 182532 kb
Host smart-4019172f-8c15-438c-ac13-9567b7a0a714
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107833538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.3107833538
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1752014487
Short name T376
Test name
Test status
Simulation time 220112942086 ps
CPU time 87.92 seconds
Started Mar 19 12:38:44 PM PDT 24
Finished Mar 19 12:40:12 PM PDT 24
Peak memory 182504 kb
Host smart-74277cce-69b6-46f3-931b-23d63245c138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752014487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1752014487
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.4290446269
Short name T214
Test name
Test status
Simulation time 55217430755 ps
CPU time 1667.29 seconds
Started Mar 19 12:38:47 PM PDT 24
Finished Mar 19 01:06:35 PM PDT 24
Peak memory 190860 kb
Host smart-77cd0e99-e8f7-4c00-9ce1-f008005ea6e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290446269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.4290446269
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.2519641453
Short name T390
Test name
Test status
Simulation time 38784171897 ps
CPU time 40.18 seconds
Started Mar 19 12:38:46 PM PDT 24
Finished Mar 19 12:39:26 PM PDT 24
Peak memory 182524 kb
Host smart-a62d3345-550d-4a6e-ac98-6b6b89072c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519641453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.2519641453
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.3880596641
Short name T206
Test name
Test status
Simulation time 248709696869 ps
CPU time 1883.5 seconds
Started Mar 19 12:39:45 PM PDT 24
Finished Mar 19 01:11:09 PM PDT 24
Peak memory 190792 kb
Host smart-456de7bb-7592-4870-a275-f1dbc89d540b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880596641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3880596641
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.107138765
Short name T347
Test name
Test status
Simulation time 62983138895 ps
CPU time 37.45 seconds
Started Mar 19 12:39:39 PM PDT 24
Finished Mar 19 12:40:16 PM PDT 24
Peak memory 182544 kb
Host smart-675af627-ff24-4dc8-b5e3-18eff644f648
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107138765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.107138765
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.1688649072
Short name T289
Test name
Test status
Simulation time 693959892826 ps
CPU time 426.8 seconds
Started Mar 19 12:39:47 PM PDT 24
Finished Mar 19 12:46:54 PM PDT 24
Peak memory 190772 kb
Host smart-0778122b-37b8-4d78-8da3-6c6e90be3b3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688649072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1688649072
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3569001984
Short name T77
Test name
Test status
Simulation time 27729034045 ps
CPU time 23.76 seconds
Started Mar 19 12:39:45 PM PDT 24
Finished Mar 19 12:40:09 PM PDT 24
Peak memory 190780 kb
Host smart-30022545-44d2-4034-ab8b-192e37143fc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569001984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3569001984
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.4070967321
Short name T437
Test name
Test status
Simulation time 37049039912 ps
CPU time 114.72 seconds
Started Mar 19 12:39:45 PM PDT 24
Finished Mar 19 12:41:40 PM PDT 24
Peak memory 182576 kb
Host smart-865e5de4-f99c-42b9-aac8-6ac63100e173
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070967321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.4070967321
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2947541203
Short name T137
Test name
Test status
Simulation time 150282432358 ps
CPU time 496.76 seconds
Started Mar 19 12:39:38 PM PDT 24
Finished Mar 19 12:47:56 PM PDT 24
Peak memory 190768 kb
Host smart-5ccde1ae-af82-4c20-be8b-f68296ef2cdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947541203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2947541203
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2103422793
Short name T342
Test name
Test status
Simulation time 2024176534680 ps
CPU time 935.78 seconds
Started Mar 19 12:38:44 PM PDT 24
Finished Mar 19 12:54:20 PM PDT 24
Peak memory 182548 kb
Host smart-bf9a6041-3ea7-4ff6-8f69-7d5dd5426a41
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103422793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2103422793
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2719276806
Short name T410
Test name
Test status
Simulation time 67806414843 ps
CPU time 98.01 seconds
Started Mar 19 12:38:45 PM PDT 24
Finished Mar 19 12:40:23 PM PDT 24
Peak memory 182508 kb
Host smart-53abbb21-9ba9-4393-89b9-1e1daf430ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719276806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2719276806
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.408170957
Short name T126
Test name
Test status
Simulation time 133631871090 ps
CPU time 404.03 seconds
Started Mar 19 12:38:48 PM PDT 24
Finished Mar 19 12:45:32 PM PDT 24
Peak memory 192964 kb
Host smart-5ec4995c-b495-4258-a95c-a8a921c2ed15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408170957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.408170957
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2491799928
Short name T220
Test name
Test status
Simulation time 112969605863 ps
CPU time 66.42 seconds
Started Mar 19 12:38:45 PM PDT 24
Finished Mar 19 12:39:51 PM PDT 24
Peak memory 182588 kb
Host smart-ad5592e0-fd49-4e50-be48-c36db3d1756a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491799928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2491799928
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.148040564
Short name T380
Test name
Test status
Simulation time 2397671209424 ps
CPU time 444.95 seconds
Started Mar 19 12:38:44 PM PDT 24
Finished Mar 19 12:46:09 PM PDT 24
Peak memory 190696 kb
Host smart-c6b1ccba-be17-4ee4-8f3d-6e18b928f05f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148040564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.
148040564
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.1797367737
Short name T59
Test name
Test status
Simulation time 162747170549 ps
CPU time 102.97 seconds
Started Mar 19 12:39:39 PM PDT 24
Finished Mar 19 12:41:23 PM PDT 24
Peak memory 190708 kb
Host smart-ce629b9a-cead-4447-8f2f-8975aab8be8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797367737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1797367737
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.2767234305
Short name T132
Test name
Test status
Simulation time 416822161977 ps
CPU time 174.17 seconds
Started Mar 19 12:39:40 PM PDT 24
Finished Mar 19 12:42:35 PM PDT 24
Peak memory 190732 kb
Host smart-43079b5a-9870-4756-b9ac-ed6ce826b8e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767234305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2767234305
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.3863161681
Short name T287
Test name
Test status
Simulation time 2832973286670 ps
CPU time 1358.89 seconds
Started Mar 19 12:39:38 PM PDT 24
Finished Mar 19 01:02:18 PM PDT 24
Peak memory 190684 kb
Host smart-d5d2455f-1011-46aa-8d70-7319f1f524f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863161681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3863161681
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.2374706296
Short name T338
Test name
Test status
Simulation time 833123011459 ps
CPU time 2614.12 seconds
Started Mar 19 12:39:39 PM PDT 24
Finished Mar 19 01:23:14 PM PDT 24
Peak memory 190744 kb
Host smart-365d587e-ed5e-4145-b830-3cc98f84a1f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374706296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2374706296
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2122985121
Short name T262
Test name
Test status
Simulation time 522782130551 ps
CPU time 461.73 seconds
Started Mar 19 12:39:39 PM PDT 24
Finished Mar 19 12:47:21 PM PDT 24
Peak memory 190748 kb
Host smart-12d7ba5d-dc6c-479f-bb32-1e2c2dfcf0f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122985121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2122985121
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2298552673
Short name T111
Test name
Test status
Simulation time 22720939195 ps
CPU time 36.3 seconds
Started Mar 19 12:39:41 PM PDT 24
Finished Mar 19 12:40:18 PM PDT 24
Peak memory 182540 kb
Host smart-e84b20c7-8890-419c-8243-424196fc2ae1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298552673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2298552673
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.1621852056
Short name T86
Test name
Test status
Simulation time 92515208050 ps
CPU time 470.29 seconds
Started Mar 19 12:39:42 PM PDT 24
Finished Mar 19 12:47:33 PM PDT 24
Peak memory 190728 kb
Host smart-115989e6-b534-49ad-af0a-c8eda1ca0dc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621852056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1621852056
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.1284530330
Short name T174
Test name
Test status
Simulation time 146483099656 ps
CPU time 139.87 seconds
Started Mar 19 12:39:38 PM PDT 24
Finished Mar 19 12:41:59 PM PDT 24
Peak memory 190712 kb
Host smart-86888a6e-67b4-4759-919f-77c723908931
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284530330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.1284530330
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.2966239836
Short name T405
Test name
Test status
Simulation time 150019013411 ps
CPU time 127.71 seconds
Started Mar 19 12:38:44 PM PDT 24
Finished Mar 19 12:40:51 PM PDT 24
Peak memory 182556 kb
Host smart-842d5ed9-4503-4077-b3ab-db45a3e62d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966239836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2966239836
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.4223242245
Short name T248
Test name
Test status
Simulation time 778806600783 ps
CPU time 349.14 seconds
Started Mar 19 12:38:46 PM PDT 24
Finished Mar 19 12:44:36 PM PDT 24
Peak memory 190736 kb
Host smart-0405640f-be3a-4de9-8c55-a1e714637b94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223242245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.4223242245
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.2208822947
Short name T57
Test name
Test status
Simulation time 111254043 ps
CPU time 0.74 seconds
Started Mar 19 12:38:44 PM PDT 24
Finished Mar 19 12:38:45 PM PDT 24
Peak memory 182324 kb
Host smart-098a0508-6162-4759-b7fb-2a1088b3e26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208822947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2208822947
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.1056993703
Short name T64
Test name
Test status
Simulation time 1788121197093 ps
CPU time 761.04 seconds
Started Mar 19 12:38:44 PM PDT 24
Finished Mar 19 12:51:26 PM PDT 24
Peak memory 190752 kb
Host smart-e614439b-99e3-48e4-ac0c-d6a8503fcb1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056993703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.1056993703
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.1593283594
Short name T36
Test name
Test status
Simulation time 93439022179 ps
CPU time 744.93 seconds
Started Mar 19 12:38:44 PM PDT 24
Finished Mar 19 12:51:10 PM PDT 24
Peak memory 207252 kb
Host smart-4f4585b5-2cea-45e5-acf2-2ff2129e28c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593283594 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.1593283594
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/172.rv_timer_random.3885573425
Short name T237
Test name
Test status
Simulation time 8103516355 ps
CPU time 40.85 seconds
Started Mar 19 12:39:47 PM PDT 24
Finished Mar 19 12:40:28 PM PDT 24
Peak memory 182544 kb
Host smart-1a553ad1-cd1b-4124-a480-43eef6c3057a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885573425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3885573425
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.3175856504
Short name T320
Test name
Test status
Simulation time 45103740111 ps
CPU time 76.1 seconds
Started Mar 19 12:39:45 PM PDT 24
Finished Mar 19 12:41:01 PM PDT 24
Peak memory 190736 kb
Host smart-0d812370-1321-42b6-b620-e090c87b3440
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175856504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3175856504
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.4060408528
Short name T218
Test name
Test status
Simulation time 565111122543 ps
CPU time 311.41 seconds
Started Mar 19 12:39:46 PM PDT 24
Finished Mar 19 12:44:58 PM PDT 24
Peak memory 190784 kb
Host smart-2db06cd6-e6e4-4086-b36f-1f267c6f48c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060408528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.4060408528
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2756508334
Short name T131
Test name
Test status
Simulation time 722125101379 ps
CPU time 939.83 seconds
Started Mar 19 12:39:47 PM PDT 24
Finished Mar 19 12:55:27 PM PDT 24
Peak memory 190760 kb
Host smart-da1eb41f-3d71-42fc-8355-b53b97bc86fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756508334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2756508334
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.139176882
Short name T305
Test name
Test status
Simulation time 661522535944 ps
CPU time 337.76 seconds
Started Mar 19 12:39:46 PM PDT 24
Finished Mar 19 12:45:24 PM PDT 24
Peak memory 190752 kb
Host smart-555e69e7-daa0-4406-91d3-cb100f4c93ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139176882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.139176882
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3279052443
Short name T329
Test name
Test status
Simulation time 644026048647 ps
CPU time 345.68 seconds
Started Mar 19 12:38:43 PM PDT 24
Finished Mar 19 12:44:28 PM PDT 24
Peak memory 182556 kb
Host smart-a6c1e5a5-9973-4443-99e6-fec8939cfebf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279052443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3279052443
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.2881510845
Short name T27
Test name
Test status
Simulation time 202692303181 ps
CPU time 298.25 seconds
Started Mar 19 12:38:41 PM PDT 24
Finished Mar 19 12:43:39 PM PDT 24
Peak memory 182540 kb
Host smart-6e0a3ca3-22e7-4b38-8225-d516e47384f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881510845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2881510845
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.845860317
Short name T432
Test name
Test status
Simulation time 71914216698 ps
CPU time 100.21 seconds
Started Mar 19 12:38:44 PM PDT 24
Finished Mar 19 12:40:24 PM PDT 24
Peak memory 190744 kb
Host smart-9a4a71fe-bb7e-4a0f-afac-aa47c0a05528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845860317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.845860317
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/181.rv_timer_random.3144703524
Short name T319
Test name
Test status
Simulation time 116101393283 ps
CPU time 88.79 seconds
Started Mar 19 12:39:46 PM PDT 24
Finished Mar 19 12:41:15 PM PDT 24
Peak memory 182492 kb
Host smart-edcb4185-1922-4039-8ac5-57e0745d5fc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144703524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3144703524
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.3005178195
Short name T141
Test name
Test status
Simulation time 322554416093 ps
CPU time 74.6 seconds
Started Mar 19 12:39:45 PM PDT 24
Finished Mar 19 12:41:00 PM PDT 24
Peak memory 182508 kb
Host smart-676a07d8-29f1-4588-8ea5-5ae8f2c784cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005178195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3005178195
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.127901608
Short name T313
Test name
Test status
Simulation time 657228511303 ps
CPU time 2152.53 seconds
Started Mar 19 12:39:48 PM PDT 24
Finished Mar 19 01:15:41 PM PDT 24
Peak memory 193364 kb
Host smart-e9b1cfd4-43ad-4077-9816-11aeb1b6da5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127901608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.127901608
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2534606588
Short name T271
Test name
Test status
Simulation time 191862199716 ps
CPU time 482.49 seconds
Started Mar 19 12:39:46 PM PDT 24
Finished Mar 19 12:47:49 PM PDT 24
Peak memory 182576 kb
Host smart-7dc73b6a-5e47-42d2-980d-b6bdf3130787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534606588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2534606588
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.656766887
Short name T136
Test name
Test status
Simulation time 105815959324 ps
CPU time 550.88 seconds
Started Mar 19 12:39:53 PM PDT 24
Finished Mar 19 12:49:05 PM PDT 24
Peak memory 190816 kb
Host smart-78ad74fa-4f88-4dea-b863-f1f34e871ca0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656766887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.656766887
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1288514678
Short name T26
Test name
Test status
Simulation time 125393176791 ps
CPU time 1224.46 seconds
Started Mar 19 12:39:52 PM PDT 24
Finished Mar 19 01:00:17 PM PDT 24
Peak memory 190792 kb
Host smart-16007946-ffff-4ba7-9499-e0e8b3a94537
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288514678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1288514678
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.530013047
Short name T240
Test name
Test status
Simulation time 70457592185 ps
CPU time 171.18 seconds
Started Mar 19 12:38:42 PM PDT 24
Finished Mar 19 12:41:33 PM PDT 24
Peak memory 190696 kb
Host smart-163f7708-47a3-4d5f-beb6-f6bb53b7adf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530013047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.530013047
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.2963362040
Short name T38
Test name
Test status
Simulation time 19004688397 ps
CPU time 207.97 seconds
Started Mar 19 12:38:49 PM PDT 24
Finished Mar 19 12:42:17 PM PDT 24
Peak memory 197124 kb
Host smart-de2bea6c-1fd7-481b-b575-e625b750b5c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963362040 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.2963362040
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/191.rv_timer_random.1211608831
Short name T238
Test name
Test status
Simulation time 158728411656 ps
CPU time 148.85 seconds
Started Mar 19 12:39:53 PM PDT 24
Finished Mar 19 12:42:22 PM PDT 24
Peak memory 190732 kb
Host smart-a678be9a-0973-4b5f-84eb-a3ea4e630da8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211608831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1211608831
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.825214345
Short name T264
Test name
Test status
Simulation time 27835743321 ps
CPU time 39.32 seconds
Started Mar 19 12:39:53 PM PDT 24
Finished Mar 19 12:40:33 PM PDT 24
Peak memory 182536 kb
Host smart-f94e62de-48a2-4c38-8cbc-3aa081af7d6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825214345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.825214345
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.66262516
Short name T357
Test name
Test status
Simulation time 92443298987 ps
CPU time 152.06 seconds
Started Mar 19 12:39:54 PM PDT 24
Finished Mar 19 12:42:26 PM PDT 24
Peak memory 194232 kb
Host smart-706d469c-5047-4b4c-82e8-71d2d0901de5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66262516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.66262516
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3732997119
Short name T263
Test name
Test status
Simulation time 406508728633 ps
CPU time 201.55 seconds
Started Mar 19 12:39:53 PM PDT 24
Finished Mar 19 12:43:15 PM PDT 24
Peak memory 190748 kb
Host smart-8b13e4e3-02f5-4a95-af95-63d8491ba551
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732997119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3732997119
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.1193338649
Short name T335
Test name
Test status
Simulation time 103872738084 ps
CPU time 187.32 seconds
Started Mar 19 12:39:51 PM PDT 24
Finished Mar 19 12:42:59 PM PDT 24
Peak memory 190692 kb
Host smart-ee86484c-3a75-4e62-aa66-c5bec9f399a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193338649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1193338649
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.685137504
Short name T149
Test name
Test status
Simulation time 820748553878 ps
CPU time 2383.88 seconds
Started Mar 19 12:39:53 PM PDT 24
Finished Mar 19 01:19:38 PM PDT 24
Peak memory 190756 kb
Host smart-b0e0e3e4-9426-49d3-8137-237a8af4ab7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685137504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.685137504
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2060221785
Short name T340
Test name
Test status
Simulation time 157744674088 ps
CPU time 133.28 seconds
Started Mar 19 12:38:26 PM PDT 24
Finished Mar 19 12:40:39 PM PDT 24
Peak memory 182540 kb
Host smart-651b9855-88f6-469c-8ef3-1a28a8852d88
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060221785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2060221785
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.383939973
Short name T403
Test name
Test status
Simulation time 452578852196 ps
CPU time 205.76 seconds
Started Mar 19 12:38:25 PM PDT 24
Finished Mar 19 12:41:51 PM PDT 24
Peak memory 182608 kb
Host smart-e435be2b-b63b-47de-bf89-2be2024d9b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383939973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.383939973
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3678983104
Short name T417
Test name
Test status
Simulation time 22889150897 ps
CPU time 37.24 seconds
Started Mar 19 12:38:25 PM PDT 24
Finished Mar 19 12:39:02 PM PDT 24
Peak memory 182544 kb
Host smart-3d9e6d51-1748-4c47-b944-ee5961fd7655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678983104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3678983104
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3253652432
Short name T16
Test name
Test status
Simulation time 646669024 ps
CPU time 0.86 seconds
Started Mar 19 12:38:28 PM PDT 24
Finished Mar 19 12:38:29 PM PDT 24
Peak memory 214084 kb
Host smart-5cf9e0e1-97a9-4ccb-b184-7b6ad65742eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253652432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3253652432
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.3616566255
Short name T112
Test name
Test status
Simulation time 1003898822842 ps
CPU time 276.61 seconds
Started Mar 19 12:38:29 PM PDT 24
Finished Mar 19 12:43:06 PM PDT 24
Peak memory 182528 kb
Host smart-c5dbfd61-6413-47f6-a80e-40f43803ca93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616566255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
3616566255
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2833095653
Short name T168
Test name
Test status
Simulation time 3627548363140 ps
CPU time 1326.92 seconds
Started Mar 19 12:38:43 PM PDT 24
Finished Mar 19 01:00:50 PM PDT 24
Peak memory 182616 kb
Host smart-6a0d30c9-631d-4a49-8f59-1329361ca7bb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833095653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2833095653
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.3207763990
Short name T448
Test name
Test status
Simulation time 391348367937 ps
CPU time 143.99 seconds
Started Mar 19 12:38:43 PM PDT 24
Finished Mar 19 12:41:07 PM PDT 24
Peak memory 182596 kb
Host smart-aef50ccb-1866-4f59-a68c-d7278cee6fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207763990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3207763990
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.575111576
Short name T374
Test name
Test status
Simulation time 652115937 ps
CPU time 2.1 seconds
Started Mar 19 12:38:46 PM PDT 24
Finished Mar 19 12:38:48 PM PDT 24
Peak memory 191188 kb
Host smart-33eb7941-448c-4c1a-84b3-6ed3803fe685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575111576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.575111576
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.3265227448
Short name T359
Test name
Test status
Simulation time 1986275484416 ps
CPU time 2834.76 seconds
Started Mar 19 12:38:44 PM PDT 24
Finished Mar 19 01:25:59 PM PDT 24
Peak memory 190760 kb
Host smart-575963d3-e788-4fbb-874a-4c25d47d050b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265227448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.3265227448
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2773287119
Short name T65
Test name
Test status
Simulation time 332885634293 ps
CPU time 167.26 seconds
Started Mar 19 12:38:44 PM PDT 24
Finished Mar 19 12:41:31 PM PDT 24
Peak memory 182552 kb
Host smart-65139b7e-1723-4829-acdd-8816ea2fec58
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773287119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2773287119
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.257332265
Short name T377
Test name
Test status
Simulation time 73816561123 ps
CPU time 92.44 seconds
Started Mar 19 12:38:46 PM PDT 24
Finished Mar 19 12:40:18 PM PDT 24
Peak memory 182540 kb
Host smart-fb26e0b9-4748-471c-86fa-f071f6978f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257332265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.257332265
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3089629087
Short name T255
Test name
Test status
Simulation time 181812923206 ps
CPU time 150.19 seconds
Started Mar 19 12:38:45 PM PDT 24
Finished Mar 19 12:41:15 PM PDT 24
Peak memory 190748 kb
Host smart-c4c455f4-0053-4887-a251-4023023944c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089629087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3089629087
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.3876448615
Short name T70
Test name
Test status
Simulation time 391687651608 ps
CPU time 150.06 seconds
Started Mar 19 12:38:44 PM PDT 24
Finished Mar 19 12:41:14 PM PDT 24
Peak memory 191932 kb
Host smart-732c033f-fe33-4066-a91c-b21e79eea6fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876448615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.3876448615
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3528870758
Short name T75
Test name
Test status
Simulation time 87141963411 ps
CPU time 153.22 seconds
Started Mar 19 12:38:46 PM PDT 24
Finished Mar 19 12:41:19 PM PDT 24
Peak memory 182540 kb
Host smart-b4a49676-104d-4b01-ae6d-25e09c8d97e6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528870758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3528870758
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3069991511
Short name T404
Test name
Test status
Simulation time 387856423137 ps
CPU time 148.78 seconds
Started Mar 19 12:38:47 PM PDT 24
Finished Mar 19 12:41:16 PM PDT 24
Peak memory 182676 kb
Host smart-61b69c2b-ca6d-40eb-9444-d30d3acfd12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069991511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3069991511
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.2785086713
Short name T314
Test name
Test status
Simulation time 58866684769 ps
CPU time 93.87 seconds
Started Mar 19 12:38:46 PM PDT 24
Finished Mar 19 12:40:20 PM PDT 24
Peak memory 190748 kb
Host smart-40e5045c-eefe-423c-920a-8d0e46804102
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785086713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2785086713
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1285861897
Short name T445
Test name
Test status
Simulation time 64686870984 ps
CPU time 1322.54 seconds
Started Mar 19 12:38:44 PM PDT 24
Finished Mar 19 01:00:47 PM PDT 24
Peak memory 182564 kb
Host smart-8c884742-7461-4581-9838-9b6088d089d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285861897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1285861897
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.111108485
Short name T316
Test name
Test status
Simulation time 2098576713096 ps
CPU time 895.72 seconds
Started Mar 19 12:38:50 PM PDT 24
Finished Mar 19 12:53:46 PM PDT 24
Peak memory 182564 kb
Host smart-5037f79c-6999-4798-accc-353b4d9950d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111108485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.111108485
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2762948845
Short name T413
Test name
Test status
Simulation time 107987890293 ps
CPU time 181.04 seconds
Started Mar 19 12:38:48 PM PDT 24
Finished Mar 19 12:41:49 PM PDT 24
Peak memory 182568 kb
Host smart-55e9dab2-9fa5-4d7e-8e3e-b3ac95af9348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762948845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2762948845
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1822741147
Short name T225
Test name
Test status
Simulation time 204658231502 ps
CPU time 294.48 seconds
Started Mar 19 12:38:43 PM PDT 24
Finished Mar 19 12:43:37 PM PDT 24
Peak memory 190748 kb
Host smart-6bcfa565-936c-4234-816d-44013aed1521
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822741147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1822741147
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2125641817
Short name T115
Test name
Test status
Simulation time 30710490472 ps
CPU time 47.18 seconds
Started Mar 19 12:38:49 PM PDT 24
Finished Mar 19 12:39:37 PM PDT 24
Peak memory 182616 kb
Host smart-76cfdaec-802f-48e6-9712-743c61f1e726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125641817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2125641817
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.453959491
Short name T8
Test name
Test status
Simulation time 1428279034437 ps
CPU time 694.58 seconds
Started Mar 19 12:38:51 PM PDT 24
Finished Mar 19 12:50:26 PM PDT 24
Peak memory 182588 kb
Host smart-6497a2b7-5ab7-4f8d-a8f9-0ab8bd88c2c9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453959491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.rv_timer_cfg_update_on_fly.453959491
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.2880778133
Short name T385
Test name
Test status
Simulation time 321113405800 ps
CPU time 134.31 seconds
Started Mar 19 12:38:57 PM PDT 24
Finished Mar 19 12:41:11 PM PDT 24
Peak memory 182572 kb
Host smart-27e91b61-2f20-43b6-828a-f97c36a2e8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880778133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.2880778133
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.76538409
Short name T310
Test name
Test status
Simulation time 41793705123 ps
CPU time 34.09 seconds
Started Mar 19 12:38:57 PM PDT 24
Finished Mar 19 12:39:31 PM PDT 24
Peak memory 182556 kb
Host smart-adc11261-dee9-495a-9d01-c613611a2f9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76538409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.76538409
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.3254438252
Short name T352
Test name
Test status
Simulation time 179387136450 ps
CPU time 79.93 seconds
Started Mar 19 12:38:48 PM PDT 24
Finished Mar 19 12:40:08 PM PDT 24
Peak memory 190732 kb
Host smart-9c8525d6-a7eb-4bbf-9272-fb10c5984aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254438252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.3254438252
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2043805917
Short name T295
Test name
Test status
Simulation time 14531929852 ps
CPU time 22.87 seconds
Started Mar 19 12:38:56 PM PDT 24
Finished Mar 19 12:39:19 PM PDT 24
Peak memory 182560 kb
Host smart-4ece29fb-38f3-4187-a072-0f1e5a9ab3c5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043805917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2043805917
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.1961801205
Short name T411
Test name
Test status
Simulation time 262861811464 ps
CPU time 104.07 seconds
Started Mar 19 12:38:47 PM PDT 24
Finished Mar 19 12:40:31 PM PDT 24
Peak memory 182540 kb
Host smart-b34cf492-3286-40c0-884e-2a6a7991f140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961801205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1961801205
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.3163321126
Short name T395
Test name
Test status
Simulation time 83343477275 ps
CPU time 77.46 seconds
Started Mar 19 12:38:51 PM PDT 24
Finished Mar 19 12:40:09 PM PDT 24
Peak memory 182512 kb
Host smart-6e45af3d-4145-49ce-bcc3-2485f837b5b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163321126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3163321126
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.395406233
Short name T358
Test name
Test status
Simulation time 2892883400 ps
CPU time 4.91 seconds
Started Mar 19 12:38:48 PM PDT 24
Finished Mar 19 12:38:53 PM PDT 24
Peak memory 182636 kb
Host smart-fe178990-843f-45d7-8b0d-bc51d9dc56bc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395406233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.395406233
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.523800047
Short name T364
Test name
Test status
Simulation time 613714670369 ps
CPU time 244.89 seconds
Started Mar 19 12:38:48 PM PDT 24
Finished Mar 19 12:42:53 PM PDT 24
Peak memory 182552 kb
Host smart-95c37f76-6d17-4a33-bcc8-da5cde9577b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523800047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.523800047
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3849348028
Short name T198
Test name
Test status
Simulation time 54904273890 ps
CPU time 51.35 seconds
Started Mar 19 12:38:49 PM PDT 24
Finished Mar 19 12:39:41 PM PDT 24
Peak memory 182608 kb
Host smart-2f3524b0-3623-4c56-a690-5523ed48c1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849348028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3849348028
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.724371410
Short name T407
Test name
Test status
Simulation time 2683699915884 ps
CPU time 1217.99 seconds
Started Mar 19 12:38:49 PM PDT 24
Finished Mar 19 12:59:08 PM PDT 24
Peak memory 190752 kb
Host smart-5a598b96-b510-44ed-bb79-740cca6d0dcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724371410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.
724371410
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3660342559
Short name T337
Test name
Test status
Simulation time 2384779572757 ps
CPU time 1239.79 seconds
Started Mar 19 12:38:50 PM PDT 24
Finished Mar 19 12:59:29 PM PDT 24
Peak memory 182576 kb
Host smart-436620f0-a986-4c09-b701-57045dcce067
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660342559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3660342559
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1949259990
Short name T370
Test name
Test status
Simulation time 261614256702 ps
CPU time 96.95 seconds
Started Mar 19 12:38:51 PM PDT 24
Finished Mar 19 12:40:28 PM PDT 24
Peak memory 182604 kb
Host smart-63e6c6e4-3377-4f34-95de-881af13beb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949259990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1949259990
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.1459516378
Short name T288
Test name
Test status
Simulation time 100576156518 ps
CPU time 162.17 seconds
Started Mar 19 12:38:51 PM PDT 24
Finished Mar 19 12:41:33 PM PDT 24
Peak memory 190740 kb
Host smart-b0594a56-73e7-4199-8167-f3e9406e079a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459516378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1459516378
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2205940327
Short name T109
Test name
Test status
Simulation time 1269959071518 ps
CPU time 477.12 seconds
Started Mar 19 12:38:49 PM PDT 24
Finished Mar 19 12:46:46 PM PDT 24
Peak memory 190756 kb
Host smart-a7614f43-4e42-4929-8750-e22de4363370
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205940327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2205940327
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.81228584
Short name T1
Test name
Test status
Simulation time 39239831561 ps
CPU time 62.53 seconds
Started Mar 19 12:38:47 PM PDT 24
Finished Mar 19 12:39:49 PM PDT 24
Peak memory 182552 kb
Host smart-18f7fec8-23e3-4159-a8a6-ad74c5978f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81228584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.81228584
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.3133569116
Short name T76
Test name
Test status
Simulation time 141287829791 ps
CPU time 437.59 seconds
Started Mar 19 12:38:50 PM PDT 24
Finished Mar 19 12:46:07 PM PDT 24
Peak memory 190740 kb
Host smart-b76f814e-d203-4f80-b981-8c5e72785c69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133569116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3133569116
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.956874525
Short name T298
Test name
Test status
Simulation time 38471579038 ps
CPU time 344.99 seconds
Started Mar 19 12:38:48 PM PDT 24
Finished Mar 19 12:44:34 PM PDT 24
Peak memory 182512 kb
Host smart-b316b125-baeb-415e-ad85-439f865a20df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956874525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.956874525
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.1463195808
Short name T286
Test name
Test status
Simulation time 211897723182 ps
CPU time 228.7 seconds
Started Mar 19 12:38:49 PM PDT 24
Finished Mar 19 12:42:37 PM PDT 24
Peak memory 190800 kb
Host smart-255fd3d6-daf2-4bc7-bf26-86b14935409b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463195808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.1463195808
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3483190795
Short name T256
Test name
Test status
Simulation time 96725351961 ps
CPU time 152.17 seconds
Started Mar 19 12:38:49 PM PDT 24
Finished Mar 19 12:41:21 PM PDT 24
Peak memory 182560 kb
Host smart-9687e12c-abbf-46d2-88de-8c79daa94e3d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483190795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.3483190795
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2833110087
Short name T179
Test name
Test status
Simulation time 28880950858 ps
CPU time 114.73 seconds
Started Mar 19 12:38:51 PM PDT 24
Finished Mar 19 12:40:45 PM PDT 24
Peak memory 190736 kb
Host smart-83618916-ffa9-48e9-903f-3747df0aff80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833110087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2833110087
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.3033836287
Short name T190
Test name
Test status
Simulation time 1057450566979 ps
CPU time 576.69 seconds
Started Mar 19 12:38:51 PM PDT 24
Finished Mar 19 12:48:28 PM PDT 24
Peak memory 194364 kb
Host smart-0f95cfd1-3933-43b6-a5ee-03954f7bb283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033836287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.3033836287
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.1216426513
Short name T324
Test name
Test status
Simulation time 355900009646 ps
CPU time 653.09 seconds
Started Mar 19 12:38:26 PM PDT 24
Finished Mar 19 12:49:19 PM PDT 24
Peak memory 182548 kb
Host smart-4ae5c0a9-94c6-478d-9d35-c17d84b3f5d4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216426513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.1216426513
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1551713564
Short name T398
Test name
Test status
Simulation time 25180726183 ps
CPU time 33.87 seconds
Started Mar 19 12:38:28 PM PDT 24
Finished Mar 19 12:39:02 PM PDT 24
Peak memory 182540 kb
Host smart-31f48dd7-4343-4212-8f1e-9a99b061ec0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551713564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1551713564
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.84078127
Short name T231
Test name
Test status
Simulation time 504976630044 ps
CPU time 489.59 seconds
Started Mar 19 12:38:27 PM PDT 24
Finished Mar 19 12:46:36 PM PDT 24
Peak memory 190744 kb
Host smart-520c071f-4f1e-4cb2-9192-c01f83d3fea1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84078127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.84078127
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.691821148
Short name T441
Test name
Test status
Simulation time 355715654 ps
CPU time 1.26 seconds
Started Mar 19 12:38:27 PM PDT 24
Finished Mar 19 12:38:28 PM PDT 24
Peak memory 190684 kb
Host smart-afbe73a3-dea0-4c97-b2ed-3130424af327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691821148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.691821148
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.787397133
Short name T19
Test name
Test status
Simulation time 82482022 ps
CPU time 0.74 seconds
Started Mar 19 12:38:26 PM PDT 24
Finished Mar 19 12:38:27 PM PDT 24
Peak memory 213668 kb
Host smart-23d4a9e7-dca6-4065-98a4-783b657d3a7c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787397133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.787397133
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.66223686
Short name T61
Test name
Test status
Simulation time 312044542715 ps
CPU time 272.95 seconds
Started Mar 19 12:38:48 PM PDT 24
Finished Mar 19 12:43:22 PM PDT 24
Peak memory 182540 kb
Host smart-f52ef6a3-7fe5-4f93-9796-9db9312744d9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66223686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.rv_timer_cfg_update_on_fly.66223686
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.748818272
Short name T368
Test name
Test status
Simulation time 683853553613 ps
CPU time 182.44 seconds
Started Mar 19 12:38:51 PM PDT 24
Finished Mar 19 12:41:54 PM PDT 24
Peak memory 182496 kb
Host smart-f314f282-d425-4d3c-a3c0-aee5c0775b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748818272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.748818272
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.834982608
Short name T201
Test name
Test status
Simulation time 2638131467 ps
CPU time 4.58 seconds
Started Mar 19 12:38:49 PM PDT 24
Finished Mar 19 12:38:53 PM PDT 24
Peak memory 182568 kb
Host smart-a1aa9b7e-d87e-4244-bfc9-7ac8b42463f6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834982608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.rv_timer_cfg_update_on_fly.834982608
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.4153941508
Short name T365
Test name
Test status
Simulation time 136581679844 ps
CPU time 182.41 seconds
Started Mar 19 12:38:46 PM PDT 24
Finished Mar 19 12:41:48 PM PDT 24
Peak memory 182588 kb
Host smart-5c1c260e-494f-431f-a865-2b11d4fcb366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153941508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.4153941508
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2798134834
Short name T171
Test name
Test status
Simulation time 176474579243 ps
CPU time 116.8 seconds
Started Mar 19 12:38:48 PM PDT 24
Finished Mar 19 12:40:45 PM PDT 24
Peak memory 182572 kb
Host smart-e1e7c0a0-7820-4672-86ed-afa6c584271d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798134834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2798134834
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.3656011951
Short name T37
Test name
Test status
Simulation time 456920847074 ps
CPU time 510.71 seconds
Started Mar 19 12:38:50 PM PDT 24
Finished Mar 19 12:47:20 PM PDT 24
Peak memory 205400 kb
Host smart-2a27bfab-ef6f-4438-b60c-967fddad3da8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656011951 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.3656011951
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3224068704
Short name T351
Test name
Test status
Simulation time 218487373831 ps
CPU time 127.02 seconds
Started Mar 19 12:38:57 PM PDT 24
Finished Mar 19 12:41:04 PM PDT 24
Peak memory 182552 kb
Host smart-9947fa8a-7e84-44d3-9332-58870bbecebb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224068704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3224068704
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.758484660
Short name T363
Test name
Test status
Simulation time 441837993339 ps
CPU time 81.16 seconds
Started Mar 19 12:38:50 PM PDT 24
Finished Mar 19 12:40:11 PM PDT 24
Peak memory 182532 kb
Host smart-4ed3c16a-f840-4535-ad44-92f0369960ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758484660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.758484660
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1232387546
Short name T210
Test name
Test status
Simulation time 253672779656 ps
CPU time 131.14 seconds
Started Mar 19 12:39:02 PM PDT 24
Finished Mar 19 12:41:13 PM PDT 24
Peak memory 190708 kb
Host smart-6130193b-7bd5-4e22-8720-26d2fe1461fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232387546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1232387546
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.1501709038
Short name T412
Test name
Test status
Simulation time 247356112868 ps
CPU time 142.33 seconds
Started Mar 19 12:38:57 PM PDT 24
Finished Mar 19 12:41:19 PM PDT 24
Peak memory 182544 kb
Host smart-8cd9959f-bf58-4797-bba1-d8d9f85a01f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501709038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.1501709038
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.3711331669
Short name T42
Test name
Test status
Simulation time 243047126797 ps
CPU time 414.05 seconds
Started Mar 19 12:38:57 PM PDT 24
Finished Mar 19 12:45:51 PM PDT 24
Peak memory 205432 kb
Host smart-0fcd6bc1-33b9-4fc9-be37-90182aa213c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711331669 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.3711331669
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_random.4228455167
Short name T242
Test name
Test status
Simulation time 204219916031 ps
CPU time 103.26 seconds
Started Mar 19 12:38:58 PM PDT 24
Finished Mar 19 12:40:42 PM PDT 24
Peak memory 190740 kb
Host smart-8f514c6f-062a-4799-a692-5d43aa04f5b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228455167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.4228455167
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.1331549702
Short name T373
Test name
Test status
Simulation time 75972815 ps
CPU time 0.55 seconds
Started Mar 19 12:38:57 PM PDT 24
Finished Mar 19 12:38:58 PM PDT 24
Peak memory 182332 kb
Host smart-829d6065-380c-41eb-8113-043df5bf7899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331549702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1331549702
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.2723753650
Short name T388
Test name
Test status
Simulation time 74215524633 ps
CPU time 62.63 seconds
Started Mar 19 12:38:58 PM PDT 24
Finished Mar 19 12:40:01 PM PDT 24
Peak memory 182548 kb
Host smart-00aca6a4-d1f9-4d90-9e09-66c8fdc8ee02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723753650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2723753650
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.970748479
Short name T25
Test name
Test status
Simulation time 27797476781 ps
CPU time 49.31 seconds
Started Mar 19 12:38:56 PM PDT 24
Finished Mar 19 12:39:46 PM PDT 24
Peak memory 182492 kb
Host smart-ba720441-8154-4264-a51b-672b58e6c93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970748479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.970748479
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3371695753
Short name T341
Test name
Test status
Simulation time 3999858867114 ps
CPU time 1237.19 seconds
Started Mar 19 12:38:57 PM PDT 24
Finished Mar 19 12:59:34 PM PDT 24
Peak memory 182572 kb
Host smart-63d023ee-46d6-4434-8c09-557071a83072
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371695753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3371695753
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3883348344
Short name T389
Test name
Test status
Simulation time 117876487867 ps
CPU time 52.63 seconds
Started Mar 19 12:38:58 PM PDT 24
Finished Mar 19 12:39:50 PM PDT 24
Peak memory 182560 kb
Host smart-46e68cba-b0e3-42ba-9021-ad66a1e6876c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883348344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3883348344
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.882038980
Short name T291
Test name
Test status
Simulation time 34496760695 ps
CPU time 51.95 seconds
Started Mar 19 12:38:57 PM PDT 24
Finished Mar 19 12:39:49 PM PDT 24
Peak memory 190804 kb
Host smart-8dbf7754-4ca3-43f1-92c7-f070116292f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882038980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.882038980
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.381090006
Short name T241
Test name
Test status
Simulation time 75605547972 ps
CPU time 43.77 seconds
Started Mar 19 12:38:58 PM PDT 24
Finished Mar 19 12:39:42 PM PDT 24
Peak memory 182544 kb
Host smart-fe656301-75a1-46c3-8112-abb8173d9a75
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381090006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.rv_timer_cfg_update_on_fly.381090006
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1538081495
Short name T369
Test name
Test status
Simulation time 177535017889 ps
CPU time 67.51 seconds
Started Mar 19 12:38:57 PM PDT 24
Finished Mar 19 12:40:05 PM PDT 24
Peak memory 182568 kb
Host smart-9c2eb27c-9052-43cf-a4bf-e51729a4312e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538081495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1538081495
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.3276801525
Short name T134
Test name
Test status
Simulation time 116499975693 ps
CPU time 169.62 seconds
Started Mar 19 12:38:57 PM PDT 24
Finished Mar 19 12:41:47 PM PDT 24
Peak memory 190760 kb
Host smart-995d388e-acea-484f-818b-ef029f8f8205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276801525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3276801525
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.1144490871
Short name T360
Test name
Test status
Simulation time 498784117 ps
CPU time 3.29 seconds
Started Mar 19 12:38:56 PM PDT 24
Finished Mar 19 12:38:59 PM PDT 24
Peak memory 182448 kb
Host smart-294e539d-b11c-4a75-b9f2-70add0f7923f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144490871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.1144490871
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.4258163138
Short name T438
Test name
Test status
Simulation time 695206276504 ps
CPU time 330.49 seconds
Started Mar 19 12:38:57 PM PDT 24
Finished Mar 19 12:44:28 PM PDT 24
Peak memory 182544 kb
Host smart-065b3618-6d18-47cc-b4e4-8cf6701d79be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258163138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.4258163138
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3235063302
Short name T47
Test name
Test status
Simulation time 165605709192 ps
CPU time 267.68 seconds
Started Mar 19 12:38:59 PM PDT 24
Finished Mar 19 12:43:26 PM PDT 24
Peak memory 182532 kb
Host smart-f558d5e8-94ee-4267-9855-59193e6a3b8a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235063302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.3235063302
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2815482211
Short name T425
Test name
Test status
Simulation time 677075177890 ps
CPU time 229.88 seconds
Started Mar 19 12:38:55 PM PDT 24
Finished Mar 19 12:42:45 PM PDT 24
Peak memory 182556 kb
Host smart-9e0fa875-0403-4124-88da-588f299dbe1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815482211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2815482211
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.183913580
Short name T163
Test name
Test status
Simulation time 249264357026 ps
CPU time 803.23 seconds
Started Mar 19 12:38:57 PM PDT 24
Finished Mar 19 12:52:20 PM PDT 24
Peak memory 190732 kb
Host smart-bcd3a580-235c-473b-93b8-05f9ac4393af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183913580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.183913580
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.754591030
Short name T419
Test name
Test status
Simulation time 60874667137 ps
CPU time 38.95 seconds
Started Mar 19 12:38:58 PM PDT 24
Finished Mar 19 12:39:37 PM PDT 24
Peak memory 190744 kb
Host smart-c30c32ec-f05a-4819-ac72-dba92a24e4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754591030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.754591030
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.4232478654
Short name T418
Test name
Test status
Simulation time 76998530910 ps
CPU time 140.36 seconds
Started Mar 19 12:38:57 PM PDT 24
Finished Mar 19 12:41:17 PM PDT 24
Peak memory 190824 kb
Host smart-c2f51696-50d8-47a3-a5b0-2bcf00e3d65e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232478654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.4232478654
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3194917380
Short name T143
Test name
Test status
Simulation time 118404162155 ps
CPU time 214.84 seconds
Started Mar 19 12:38:57 PM PDT 24
Finished Mar 19 12:42:32 PM PDT 24
Peak memory 182568 kb
Host smart-93dbea0a-8cef-49a4-b56f-288e27bc05c4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194917380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3194917380
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.1912997362
Short name T439
Test name
Test status
Simulation time 32422167271 ps
CPU time 53.4 seconds
Started Mar 19 12:39:02 PM PDT 24
Finished Mar 19 12:39:56 PM PDT 24
Peak memory 182512 kb
Host smart-98303638-b304-4e29-9bd3-e3165582a28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912997362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1912997362
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.697169052
Short name T127
Test name
Test status
Simulation time 59542546995 ps
CPU time 31.73 seconds
Started Mar 19 12:39:00 PM PDT 24
Finished Mar 19 12:39:32 PM PDT 24
Peak memory 182488 kb
Host smart-9f38b74e-27da-4ca6-89ff-5defd7b3a18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697169052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.697169052
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3496050798
Short name T155
Test name
Test status
Simulation time 459029337742 ps
CPU time 712.59 seconds
Started Mar 19 12:38:59 PM PDT 24
Finished Mar 19 12:50:51 PM PDT 24
Peak memory 182552 kb
Host smart-6c1c9b94-79f5-4b82-844c-7f820bce78c4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496050798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3496050798
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.1288714996
Short name T382
Test name
Test status
Simulation time 122959546443 ps
CPU time 195.72 seconds
Started Mar 19 12:38:57 PM PDT 24
Finished Mar 19 12:42:13 PM PDT 24
Peak memory 182508 kb
Host smart-7f898190-04d2-416b-ae27-960029130db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288714996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1288714996
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.4234504793
Short name T48
Test name
Test status
Simulation time 636066515823 ps
CPU time 474.59 seconds
Started Mar 19 12:38:55 PM PDT 24
Finished Mar 19 12:46:50 PM PDT 24
Peak memory 190700 kb
Host smart-38feaece-0987-42b5-aacd-ffe7e9a30090
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234504793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.4234504793
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3728183389
Short name T177
Test name
Test status
Simulation time 68069579463 ps
CPU time 179.79 seconds
Started Mar 19 12:38:58 PM PDT 24
Finished Mar 19 12:41:58 PM PDT 24
Peak memory 182544 kb
Host smart-303fc52e-ad89-49b6-8bc0-e3f55e900aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728183389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3728183389
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.3172255226
Short name T39
Test name
Test status
Simulation time 26389357142 ps
CPU time 228.12 seconds
Started Mar 19 12:38:58 PM PDT 24
Finished Mar 19 12:42:46 PM PDT 24
Peak memory 205400 kb
Host smart-4308e0d9-2ffb-4f69-987f-726bd7bbe055
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172255226 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.3172255226
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3208388976
Short name T222
Test name
Test status
Simulation time 1031785407057 ps
CPU time 610.02 seconds
Started Mar 19 12:38:28 PM PDT 24
Finished Mar 19 12:48:38 PM PDT 24
Peak memory 182552 kb
Host smart-f35cbb01-3ceb-42e4-a6ea-4a8ebfce67de
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208388976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3208388976
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.1939237758
Short name T387
Test name
Test status
Simulation time 257033482988 ps
CPU time 247.68 seconds
Started Mar 19 12:38:29 PM PDT 24
Finished Mar 19 12:42:37 PM PDT 24
Peak memory 182536 kb
Host smart-9011fa01-43f2-425c-acc6-f55a9b3c2846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939237758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1939237758
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.810703738
Short name T326
Test name
Test status
Simulation time 104612170055 ps
CPU time 157.48 seconds
Started Mar 19 12:38:26 PM PDT 24
Finished Mar 19 12:41:03 PM PDT 24
Peak memory 190724 kb
Host smart-4bd58e21-91bb-4d8a-a001-57bfacae99ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810703738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.810703738
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.128263415
Short name T17
Test name
Test status
Simulation time 59396528 ps
CPU time 0.81 seconds
Started Mar 19 12:38:34 PM PDT 24
Finished Mar 19 12:38:34 PM PDT 24
Peak memory 213004 kb
Host smart-9e6265b3-e875-4dd0-92d7-69cec5c07a8d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128263415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.128263415
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1139660293
Short name T375
Test name
Test status
Simulation time 322217703058 ps
CPU time 84.72 seconds
Started Mar 19 12:38:34 PM PDT 24
Finished Mar 19 12:39:58 PM PDT 24
Peak memory 182548 kb
Host smart-26e25102-7633-4882-9e51-2166df9970ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139660293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1139660293
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.2636532728
Short name T235
Test name
Test status
Simulation time 224719295105 ps
CPU time 284.32 seconds
Started Mar 19 12:38:56 PM PDT 24
Finished Mar 19 12:43:41 PM PDT 24
Peak memory 182504 kb
Host smart-2d33fde9-439c-452d-b1f0-d97246d11f43
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636532728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.2636532728
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.1787670674
Short name T429
Test name
Test status
Simulation time 88005938796 ps
CPU time 33.78 seconds
Started Mar 19 12:38:56 PM PDT 24
Finished Mar 19 12:39:30 PM PDT 24
Peak memory 182556 kb
Host smart-fb16361a-21a4-499a-9880-b9e972e08ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787670674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1787670674
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3961952056
Short name T423
Test name
Test status
Simulation time 40743559986 ps
CPU time 171.76 seconds
Started Mar 19 12:38:56 PM PDT 24
Finished Mar 19 12:41:47 PM PDT 24
Peak memory 182544 kb
Host smart-d17263a2-13f6-465b-b4fd-b6d58dce1cb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961952056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3961952056
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.3065976339
Short name T399
Test name
Test status
Simulation time 2834844119 ps
CPU time 3.21 seconds
Started Mar 19 12:38:59 PM PDT 24
Finished Mar 19 12:39:02 PM PDT 24
Peak memory 194028 kb
Host smart-2671d1c5-a57e-4f00-8ff2-46c993b56eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065976339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3065976339
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1589318711
Short name T46
Test name
Test status
Simulation time 88010560691 ps
CPU time 35.04 seconds
Started Mar 19 12:39:03 PM PDT 24
Finished Mar 19 12:39:38 PM PDT 24
Peak memory 182564 kb
Host smart-54e34805-e82c-46a9-8487-24a56ba87ef4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589318711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1589318711
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2900737653
Short name T409
Test name
Test status
Simulation time 181435013512 ps
CPU time 98.01 seconds
Started Mar 19 12:39:07 PM PDT 24
Finished Mar 19 12:40:45 PM PDT 24
Peak memory 182572 kb
Host smart-00cd26df-e09b-4414-bc90-cfff0dba0c63
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900737653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2900737653
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3675262808
Short name T392
Test name
Test status
Simulation time 112997380884 ps
CPU time 99.84 seconds
Started Mar 19 12:39:03 PM PDT 24
Finished Mar 19 12:40:43 PM PDT 24
Peak memory 182580 kb
Host smart-efd07750-79c1-4e8f-9b7f-f5454d3763da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675262808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3675262808
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1805083486
Short name T113
Test name
Test status
Simulation time 560590772335 ps
CPU time 247.59 seconds
Started Mar 19 12:39:02 PM PDT 24
Finished Mar 19 12:43:10 PM PDT 24
Peak memory 190716 kb
Host smart-4819859f-4eca-4357-8a65-80be4d10a276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805083486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1805083486
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2702020628
Short name T393
Test name
Test status
Simulation time 241400565 ps
CPU time 0.75 seconds
Started Mar 19 12:39:00 PM PDT 24
Finished Mar 19 12:39:01 PM PDT 24
Peak memory 182284 kb
Host smart-be0888da-b830-47d7-9a17-072dd2d4ee59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702020628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2702020628
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.1106903731
Short name T434
Test name
Test status
Simulation time 19883540 ps
CPU time 0.54 seconds
Started Mar 19 12:39:02 PM PDT 24
Finished Mar 19 12:39:03 PM PDT 24
Peak memory 181820 kb
Host smart-229c6759-bc26-44c7-b622-ecf7812fa602
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106903731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.1106903731
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2802776801
Short name T160
Test name
Test status
Simulation time 26295099664 ps
CPU time 28.57 seconds
Started Mar 19 12:39:02 PM PDT 24
Finished Mar 19 12:39:30 PM PDT 24
Peak memory 182556 kb
Host smart-54c62617-b2a0-48c2-adb0-89174b79cf96
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802776801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2802776801
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1844728210
Short name T10
Test name
Test status
Simulation time 36395330838 ps
CPU time 29.73 seconds
Started Mar 19 12:39:01 PM PDT 24
Finished Mar 19 12:39:31 PM PDT 24
Peak memory 182560 kb
Host smart-13879d5b-c6c1-4e28-adfc-e5bd20b17540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844728210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1844728210
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.2173195928
Short name T302
Test name
Test status
Simulation time 28091066222 ps
CPU time 13.05 seconds
Started Mar 19 12:39:04 PM PDT 24
Finished Mar 19 12:39:18 PM PDT 24
Peak memory 182548 kb
Host smart-918e7a57-1905-4ce0-8b51-2d381bf4ba5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173195928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2173195928
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.3716952428
Short name T317
Test name
Test status
Simulation time 16160756669 ps
CPU time 27.98 seconds
Started Mar 19 12:39:02 PM PDT 24
Finished Mar 19 12:39:30 PM PDT 24
Peak memory 190724 kb
Host smart-89f62c67-ec80-485d-bb5a-c49737cc4187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716952428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.3716952428
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1699653117
Short name T203
Test name
Test status
Simulation time 2109152303210 ps
CPU time 1102.55 seconds
Started Mar 19 12:39:03 PM PDT 24
Finished Mar 19 12:57:27 PM PDT 24
Peak memory 194776 kb
Host smart-1e6caa72-bb78-4739-86df-460926245026
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699653117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1699653117
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.2687668326
Short name T116
Test name
Test status
Simulation time 121991241319 ps
CPU time 934.61 seconds
Started Mar 19 12:39:03 PM PDT 24
Finished Mar 19 12:54:39 PM PDT 24
Peak memory 213088 kb
Host smart-5a99603b-b621-4ebb-a4d4-9e01b11c5337
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687668326 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.2687668326
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.366951924
Short name T197
Test name
Test status
Simulation time 179064148657 ps
CPU time 303.68 seconds
Started Mar 19 12:39:01 PM PDT 24
Finished Mar 19 12:44:05 PM PDT 24
Peak memory 182580 kb
Host smart-11e82a28-1f9d-4a39-94bf-b59b0875d405
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366951924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.rv_timer_cfg_update_on_fly.366951924
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.525227949
Short name T378
Test name
Test status
Simulation time 89622473854 ps
CPU time 34.85 seconds
Started Mar 19 12:39:05 PM PDT 24
Finished Mar 19 12:39:40 PM PDT 24
Peak memory 182532 kb
Host smart-97f46b67-aa0a-421b-91c5-c23f236d5dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525227949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.525227949
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.3371483609
Short name T3
Test name
Test status
Simulation time 559579966828 ps
CPU time 358.39 seconds
Started Mar 19 12:39:01 PM PDT 24
Finished Mar 19 12:45:00 PM PDT 24
Peak memory 190696 kb
Host smart-bacb1ebc-4cee-4b0f-ad1c-ab22cbf1e28d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371483609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3371483609
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.896587609
Short name T371
Test name
Test status
Simulation time 1055063492763 ps
CPU time 470.07 seconds
Started Mar 19 12:39:06 PM PDT 24
Finished Mar 19 12:46:56 PM PDT 24
Peak memory 182544 kb
Host smart-fee413ff-2e6a-4961-b065-40025098e5bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896587609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
896587609
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2458569547
Short name T147
Test name
Test status
Simulation time 264714701587 ps
CPU time 412.92 seconds
Started Mar 19 12:39:58 PM PDT 24
Finished Mar 19 12:46:51 PM PDT 24
Peak memory 182504 kb
Host smart-dfb81efb-6b8a-4895-a269-d7a81f195249
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458569547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2458569547
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3060770092
Short name T4
Test name
Test status
Simulation time 127653478575 ps
CPU time 94.99 seconds
Started Mar 19 12:39:03 PM PDT 24
Finished Mar 19 12:40:39 PM PDT 24
Peak memory 182532 kb
Host smart-1caac059-5764-4103-bf2d-0570ccc3493a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060770092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3060770092
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.2189078166
Short name T229
Test name
Test status
Simulation time 56008784801 ps
CPU time 1085.16 seconds
Started Mar 19 12:39:00 PM PDT 24
Finished Mar 19 12:57:05 PM PDT 24
Peak memory 182592 kb
Host smart-bcac0542-cde7-4d7b-992c-3a13ea365d8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189078166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2189078166
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.247681373
Short name T301
Test name
Test status
Simulation time 71144150419 ps
CPU time 136.56 seconds
Started Mar 19 12:39:57 PM PDT 24
Finished Mar 19 12:42:14 PM PDT 24
Peak memory 182456 kb
Host smart-06f0f98e-6ae1-4ed3-881d-851f15eba47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247681373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.247681373
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3453090500
Short name T107
Test name
Test status
Simulation time 1212412593838 ps
CPU time 505.56 seconds
Started Mar 19 12:39:03 PM PDT 24
Finished Mar 19 12:47:29 PM PDT 24
Peak memory 190736 kb
Host smart-985dedfa-5c74-4240-a2fb-7c079cb065ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453090500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3453090500
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.4207173367
Short name T280
Test name
Test status
Simulation time 1036859489475 ps
CPU time 367.91 seconds
Started Mar 19 12:39:07 PM PDT 24
Finished Mar 19 12:45:15 PM PDT 24
Peak memory 182604 kb
Host smart-834461ee-8d52-4247-a451-604d63f4d2d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207173367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.4207173367
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1904715290
Short name T396
Test name
Test status
Simulation time 186052762574 ps
CPU time 277.4 seconds
Started Mar 19 12:39:58 PM PDT 24
Finished Mar 19 12:44:35 PM PDT 24
Peak memory 182508 kb
Host smart-b825edc8-8b25-4334-9e51-f64be791a335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904715290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1904715290
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.1568517820
Short name T2
Test name
Test status
Simulation time 114551445789 ps
CPU time 2006.14 seconds
Started Mar 19 12:39:58 PM PDT 24
Finished Mar 19 01:13:25 PM PDT 24
Peak memory 190708 kb
Host smart-db242724-dd2a-4782-931a-2ca04f5b4868
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568517820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1568517820
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.1763733933
Short name T381
Test name
Test status
Simulation time 391646067 ps
CPU time 1.29 seconds
Started Mar 19 12:39:03 PM PDT 24
Finished Mar 19 12:39:04 PM PDT 24
Peak memory 182540 kb
Host smart-5465c333-0c9e-48c9-a0d5-36a63c9464de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763733933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1763733933
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2793660372
Short name T367
Test name
Test status
Simulation time 34252040 ps
CPU time 0.58 seconds
Started Mar 19 12:39:03 PM PDT 24
Finished Mar 19 12:39:03 PM PDT 24
Peak memory 181832 kb
Host smart-c9c33d20-c86f-4756-9bb7-4248feb55646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793660372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2793660372
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3956803297
Short name T108
Test name
Test status
Simulation time 234054980829 ps
CPU time 423.65 seconds
Started Mar 19 12:39:02 PM PDT 24
Finished Mar 19 12:46:06 PM PDT 24
Peak memory 182548 kb
Host smart-3a7826be-4042-43a0-9f05-3c125b14dd9e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956803297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3956803297
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3028299838
Short name T442
Test name
Test status
Simulation time 20313765321 ps
CPU time 31.91 seconds
Started Mar 19 12:39:03 PM PDT 24
Finished Mar 19 12:39:35 PM PDT 24
Peak memory 182064 kb
Host smart-9a9d7bd4-d367-499d-b79a-424c736519e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028299838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3028299838
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3155909966
Short name T372
Test name
Test status
Simulation time 1080492773 ps
CPU time 0.7 seconds
Started Mar 19 12:39:02 PM PDT 24
Finished Mar 19 12:39:03 PM PDT 24
Peak memory 182736 kb
Host smart-6961584a-d4ff-42b7-9689-9e9be92cba7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155909966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3155909966
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1345221477
Short name T401
Test name
Test status
Simulation time 2949390934 ps
CPU time 5.44 seconds
Started Mar 19 12:39:03 PM PDT 24
Finished Mar 19 12:39:09 PM PDT 24
Peak memory 182064 kb
Host smart-8210feaa-5e2e-49a7-8a4d-f58f4274b040
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345221477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1345221477
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.574490596
Short name T361
Test name
Test status
Simulation time 64693930879 ps
CPU time 28.3 seconds
Started Mar 19 12:39:57 PM PDT 24
Finished Mar 19 12:40:25 PM PDT 24
Peak memory 182460 kb
Host smart-eece381a-7f38-42d1-8e4b-3f45c97928b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574490596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.574490596
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.2358182355
Short name T431
Test name
Test status
Simulation time 15574050673 ps
CPU time 538.65 seconds
Started Mar 19 12:39:58 PM PDT 24
Finished Mar 19 12:48:57 PM PDT 24
Peak memory 182508 kb
Host smart-1f84fb1d-ee0f-49ba-8fcb-3deabc42734a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358182355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2358182355
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3781593342
Short name T157
Test name
Test status
Simulation time 65205839839 ps
CPU time 115.9 seconds
Started Mar 19 12:39:04 PM PDT 24
Finished Mar 19 12:41:00 PM PDT 24
Peak memory 194560 kb
Host smart-4f21bd45-4b00-4d6c-87f5-ea4bcf49ded1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781593342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3781593342
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.4084199653
Short name T41
Test name
Test status
Simulation time 18607413077 ps
CPU time 138.11 seconds
Started Mar 19 12:39:02 PM PDT 24
Finished Mar 19 12:41:20 PM PDT 24
Peak memory 197216 kb
Host smart-c126f767-d6cd-4283-a63b-b34689ea0499
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084199653 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.4084199653
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.3970565864
Short name T402
Test name
Test status
Simulation time 548041215496 ps
CPU time 242.19 seconds
Started Mar 19 12:39:04 PM PDT 24
Finished Mar 19 12:43:07 PM PDT 24
Peak memory 182576 kb
Host smart-a038e0b5-7db8-4c28-ac51-6e50b8003085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970565864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3970565864
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.1943664020
Short name T205
Test name
Test status
Simulation time 10550882198 ps
CPU time 17.54 seconds
Started Mar 19 12:39:03 PM PDT 24
Finished Mar 19 12:39:20 PM PDT 24
Peak memory 182604 kb
Host smart-086a654c-c5fc-4d1d-a259-c69ccd1d36c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943664020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1943664020
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.1356356929
Short name T386
Test name
Test status
Simulation time 203191583 ps
CPU time 0.89 seconds
Started Mar 19 12:39:04 PM PDT 24
Finished Mar 19 12:39:05 PM PDT 24
Peak memory 192032 kb
Host smart-c7594d16-a734-4265-bece-0d542cd03980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356356929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1356356929
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1467048918
Short name T406
Test name
Test status
Simulation time 145549099926 ps
CPU time 199.08 seconds
Started Mar 19 12:39:58 PM PDT 24
Finished Mar 19 12:43:17 PM PDT 24
Peak memory 182464 kb
Host smart-dbab637b-b109-4e84-a50d-d6aa8263d65a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467048918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1467048918
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.188551559
Short name T211
Test name
Test status
Simulation time 40024797159 ps
CPU time 15.51 seconds
Started Mar 19 12:39:06 PM PDT 24
Finished Mar 19 12:39:22 PM PDT 24
Peak memory 182556 kb
Host smart-4f8456ff-8fec-4db9-a3f4-f0b3f532666a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188551559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.rv_timer_cfg_update_on_fly.188551559
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3610057692
Short name T74
Test name
Test status
Simulation time 331246741813 ps
CPU time 271.75 seconds
Started Mar 19 12:39:09 PM PDT 24
Finished Mar 19 12:43:41 PM PDT 24
Peak memory 182488 kb
Host smart-5de09bf7-59cd-45c3-8c34-903b4744dc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610057692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3610057692
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.918786545
Short name T268
Test name
Test status
Simulation time 4183255376 ps
CPU time 8.31 seconds
Started Mar 19 12:39:04 PM PDT 24
Finished Mar 19 12:39:13 PM PDT 24
Peak memory 182552 kb
Host smart-86630def-a0cb-4d46-be60-663b5604f66d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918786545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.918786545
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.2920088499
Short name T29
Test name
Test status
Simulation time 2144309874 ps
CPU time 4.55 seconds
Started Mar 19 12:39:10 PM PDT 24
Finished Mar 19 12:39:15 PM PDT 24
Peak memory 192064 kb
Host smart-7f341759-b697-4c9c-8429-1d54b3a89a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920088499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2920088499
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.2431814787
Short name T400
Test name
Test status
Simulation time 197895358043 ps
CPU time 97.16 seconds
Started Mar 19 12:39:10 PM PDT 24
Finished Mar 19 12:40:47 PM PDT 24
Peak memory 194096 kb
Host smart-ad246d81-50b0-4b70-832f-cf3a55708082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431814787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.2431814787
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3502877989
Short name T331
Test name
Test status
Simulation time 174213799166 ps
CPU time 63.42 seconds
Started Mar 19 12:38:37 PM PDT 24
Finished Mar 19 12:39:41 PM PDT 24
Peak memory 182564 kb
Host smart-5565e43c-3896-4de9-89fe-c0a43f612856
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502877989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3502877989
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.998542200
Short name T366
Test name
Test status
Simulation time 230227266291 ps
CPU time 189.44 seconds
Started Mar 19 12:38:34 PM PDT 24
Finished Mar 19 12:41:44 PM PDT 24
Peak memory 182580 kb
Host smart-b210ffd6-3d4b-49b5-9c54-131f4508f41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998542200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.998542200
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.859130307
Short name T424
Test name
Test status
Simulation time 46764967601 ps
CPU time 34.94 seconds
Started Mar 19 12:38:34 PM PDT 24
Finished Mar 19 12:39:09 PM PDT 24
Peak memory 190740 kb
Host smart-fd1ef767-7f0c-43aa-a8a5-ebbf43705a21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859130307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.859130307
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.230061218
Short name T51
Test name
Test status
Simulation time 186079243824 ps
CPU time 85.36 seconds
Started Mar 19 12:38:34 PM PDT 24
Finished Mar 19 12:40:00 PM PDT 24
Peak memory 192992 kb
Host smart-ca275919-f312-45b6-bd01-666f52adbb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230061218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.230061218
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.4062716755
Short name T68
Test name
Test status
Simulation time 369036417332 ps
CPU time 300.01 seconds
Started Mar 19 12:38:36 PM PDT 24
Finished Mar 19 12:43:36 PM PDT 24
Peak memory 194244 kb
Host smart-60a76010-94bc-4fea-a00a-695fc6452bc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062716755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
4062716755
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.1989929908
Short name T415
Test name
Test status
Simulation time 56204375096 ps
CPU time 235.96 seconds
Started Mar 19 12:38:35 PM PDT 24
Finished Mar 19 12:42:32 PM PDT 24
Peak memory 205384 kb
Host smart-f8e8df38-f4cb-4b18-8188-da627eb7b5ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989929908 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.1989929908
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.2440180055
Short name T148
Test name
Test status
Simulation time 518249512376 ps
CPU time 574.33 seconds
Started Mar 19 12:39:11 PM PDT 24
Finished Mar 19 12:48:46 PM PDT 24
Peak memory 190740 kb
Host smart-6b6b0cf6-ee6a-4766-8262-b77764a6d3cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440180055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2440180055
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.1844125637
Short name T85
Test name
Test status
Simulation time 570147578131 ps
CPU time 2192.25 seconds
Started Mar 19 12:39:09 PM PDT 24
Finished Mar 19 01:15:42 PM PDT 24
Peak memory 190752 kb
Host smart-ad066655-6c60-46c3-a0f9-3604a3c87257
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844125637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1844125637
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.347129316
Short name T188
Test name
Test status
Simulation time 98261620283 ps
CPU time 992.02 seconds
Started Mar 19 12:39:08 PM PDT 24
Finished Mar 19 12:55:41 PM PDT 24
Peak memory 190752 kb
Host smart-f480611a-9a93-4b9f-a494-79d89644d9ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347129316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.347129316
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.4133147202
Short name T259
Test name
Test status
Simulation time 82981675420 ps
CPU time 590.16 seconds
Started Mar 19 12:39:12 PM PDT 24
Finished Mar 19 12:49:03 PM PDT 24
Peak memory 190764 kb
Host smart-4088c1ce-f62b-4522-8af1-890823fe138f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133147202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.4133147202
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1251433255
Short name T300
Test name
Test status
Simulation time 94589711374 ps
CPU time 132.98 seconds
Started Mar 19 12:39:09 PM PDT 24
Finished Mar 19 12:41:22 PM PDT 24
Peak memory 182540 kb
Host smart-ee7961e4-3970-4f92-ba46-15e73170518e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251433255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1251433255
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.1993860388
Short name T427
Test name
Test status
Simulation time 290593505667 ps
CPU time 144.81 seconds
Started Mar 19 12:39:06 PM PDT 24
Finished Mar 19 12:41:32 PM PDT 24
Peak memory 190740 kb
Host smart-a5277f61-b3e2-4ba9-9966-cecac2f70116
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993860388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1993860388
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.3673751842
Short name T185
Test name
Test status
Simulation time 84000330368 ps
CPU time 1545.42 seconds
Started Mar 19 12:39:07 PM PDT 24
Finished Mar 19 01:04:53 PM PDT 24
Peak memory 190756 kb
Host smart-a513f2c8-2f48-4c33-a19f-b25c4394ff17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673751842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3673751842
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.4277657853
Short name T114
Test name
Test status
Simulation time 200166976386 ps
CPU time 319.95 seconds
Started Mar 19 12:38:34 PM PDT 24
Finished Mar 19 12:43:55 PM PDT 24
Peak memory 182544 kb
Host smart-80d38bba-ecf8-4717-bb6a-6592ba8be8ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277657853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.4277657853
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.3080144532
Short name T435
Test name
Test status
Simulation time 86263667979 ps
CPU time 123.6 seconds
Started Mar 19 12:38:35 PM PDT 24
Finished Mar 19 12:40:39 PM PDT 24
Peak memory 182608 kb
Host smart-479b029a-aaf1-40c5-9c56-52173693e331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080144532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3080144532
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.2864793675
Short name T243
Test name
Test status
Simulation time 94607342556 ps
CPU time 313.31 seconds
Started Mar 19 12:38:40 PM PDT 24
Finished Mar 19 12:43:54 PM PDT 24
Peak memory 190740 kb
Host smart-624709d0-2377-4ab7-b509-17f093c64790
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864793675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2864793675
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1080503751
Short name T63
Test name
Test status
Simulation time 423298440 ps
CPU time 0.75 seconds
Started Mar 19 12:38:34 PM PDT 24
Finished Mar 19 12:38:35 PM PDT 24
Peak memory 182292 kb
Host smart-549764fb-3194-4ff1-a8ca-1bf091d18593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080503751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1080503751
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3246986239
Short name T129
Test name
Test status
Simulation time 140368467370 ps
CPU time 401.8 seconds
Started Mar 19 12:38:37 PM PDT 24
Finished Mar 19 12:45:19 PM PDT 24
Peak memory 190700 kb
Host smart-e85ea14c-8bae-4e38-bd7e-2df5a5295d4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246986239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3246986239
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/61.rv_timer_random.1946517396
Short name T446
Test name
Test status
Simulation time 196165995106 ps
CPU time 394.33 seconds
Started Mar 19 12:39:09 PM PDT 24
Finished Mar 19 12:45:44 PM PDT 24
Peak memory 182548 kb
Host smart-bf4db996-2b74-45e8-98d0-7accd60f006a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946517396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1946517396
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.3984444624
Short name T22
Test name
Test status
Simulation time 129936500510 ps
CPU time 347.69 seconds
Started Mar 19 12:39:10 PM PDT 24
Finished Mar 19 12:44:58 PM PDT 24
Peak memory 190740 kb
Host smart-dcde8905-4fcb-4ec1-9832-f0973ee06caa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984444624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3984444624
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1690580711
Short name T152
Test name
Test status
Simulation time 426812326956 ps
CPU time 199.01 seconds
Started Mar 19 12:39:11 PM PDT 24
Finished Mar 19 12:42:30 PM PDT 24
Peak memory 190756 kb
Host smart-4193b358-cb87-4af4-a806-d7a9db14cf4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690580711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1690580711
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.279720657
Short name T414
Test name
Test status
Simulation time 31593268198 ps
CPU time 32.55 seconds
Started Mar 19 12:39:12 PM PDT 24
Finished Mar 19 12:39:45 PM PDT 24
Peak memory 182464 kb
Host smart-a15220b2-8d50-4f34-b873-dd3293296cd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279720657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.279720657
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2914444219
Short name T267
Test name
Test status
Simulation time 77377040354 ps
CPU time 129.59 seconds
Started Mar 19 12:39:10 PM PDT 24
Finished Mar 19 12:41:20 PM PDT 24
Peak memory 190712 kb
Host smart-22b9972c-1c1b-47bb-8e8d-f6fcdfa36b1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914444219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2914444219
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.152491451
Short name T194
Test name
Test status
Simulation time 481652004414 ps
CPU time 496.12 seconds
Started Mar 19 12:39:08 PM PDT 24
Finished Mar 19 12:47:25 PM PDT 24
Peak memory 190740 kb
Host smart-3d2e0510-71d6-428a-b753-c389b9cf9de8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152491451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.152491451
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.878167252
Short name T258
Test name
Test status
Simulation time 10170676237 ps
CPU time 18.28 seconds
Started Mar 19 12:38:34 PM PDT 24
Finished Mar 19 12:38:52 PM PDT 24
Peak memory 182560 kb
Host smart-944ba38e-85e6-4a64-a87b-bb3613d38c9c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878167252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.rv_timer_cfg_update_on_fly.878167252
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.4229787228
Short name T60
Test name
Test status
Simulation time 85529706179 ps
CPU time 120.44 seconds
Started Mar 19 12:38:35 PM PDT 24
Finished Mar 19 12:40:36 PM PDT 24
Peak memory 182548 kb
Host smart-ccc27682-74ae-41a8-b929-abf5ddb986eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229787228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.4229787228
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2626545095
Short name T394
Test name
Test status
Simulation time 242419371 ps
CPU time 0.97 seconds
Started Mar 19 12:38:34 PM PDT 24
Finished Mar 19 12:38:35 PM PDT 24
Peak memory 182384 kb
Host smart-2341dade-dea4-4138-bcad-83dc70eee562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626545095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2626545095
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.794604952
Short name T14
Test name
Test status
Simulation time 31086272836 ps
CPU time 139.42 seconds
Started Mar 19 12:38:34 PM PDT 24
Finished Mar 19 12:40:54 PM PDT 24
Peak memory 197264 kb
Host smart-3ee08dbc-154f-4d50-91fd-c4f3fcce30db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794604952 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.794604952
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.358472739
Short name T162
Test name
Test status
Simulation time 306181199786 ps
CPU time 1165.09 seconds
Started Mar 19 12:39:09 PM PDT 24
Finished Mar 19 12:58:35 PM PDT 24
Peak memory 190752 kb
Host smart-bc9b1033-f191-4a73-93fc-58de27c54360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358472739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.358472739
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.2490211050
Short name T78
Test name
Test status
Simulation time 90235706117 ps
CPU time 56.16 seconds
Started Mar 19 12:39:12 PM PDT 24
Finished Mar 19 12:40:09 PM PDT 24
Peak memory 191664 kb
Host smart-87d99456-bf10-4937-b329-3846e3dd48cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490211050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2490211050
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3832539260
Short name T436
Test name
Test status
Simulation time 340073725982 ps
CPU time 506.97 seconds
Started Mar 19 12:39:08 PM PDT 24
Finished Mar 19 12:47:35 PM PDT 24
Peak memory 190748 kb
Host smart-2333d310-6964-4e96-80f7-e55a12ffa296
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832539260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3832539260
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.4025343743
Short name T9
Test name
Test status
Simulation time 150368455181 ps
CPU time 335.58 seconds
Started Mar 19 12:39:07 PM PDT 24
Finished Mar 19 12:44:43 PM PDT 24
Peak memory 182540 kb
Host smart-bfc0285e-6789-43ce-9554-5801bc03ba7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025343743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.4025343743
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.734127324
Short name T195
Test name
Test status
Simulation time 188441670448 ps
CPU time 2449.32 seconds
Started Mar 19 12:39:09 PM PDT 24
Finished Mar 19 01:19:59 PM PDT 24
Peak memory 190796 kb
Host smart-8c40d1f5-af03-4404-9e97-f2b5865cc76b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734127324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.734127324
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.1313072786
Short name T266
Test name
Test status
Simulation time 8925096393 ps
CPU time 14.75 seconds
Started Mar 19 12:39:08 PM PDT 24
Finished Mar 19 12:39:24 PM PDT 24
Peak memory 182560 kb
Host smart-075517c6-b4e2-45a1-ae84-807dbd7d8df1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313072786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1313072786
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3604697310
Short name T355
Test name
Test status
Simulation time 155889892208 ps
CPU time 382.1 seconds
Started Mar 19 12:39:10 PM PDT 24
Finished Mar 19 12:45:32 PM PDT 24
Peak memory 190712 kb
Host smart-1ca95772-7a4a-4950-b365-ab8fe27ffdc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604697310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3604697310
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.1200730566
Short name T447
Test name
Test status
Simulation time 55776064762 ps
CPU time 77.62 seconds
Started Mar 19 12:39:12 PM PDT 24
Finished Mar 19 12:40:30 PM PDT 24
Peak memory 190752 kb
Host smart-5141423a-0a35-43e3-bf54-a659799524c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200730566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1200730566
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.2473438963
Short name T284
Test name
Test status
Simulation time 593801671245 ps
CPU time 633.59 seconds
Started Mar 19 12:38:34 PM PDT 24
Finished Mar 19 12:49:08 PM PDT 24
Peak memory 182632 kb
Host smart-464b9c11-031c-49fc-a71c-72e5491d7cf1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473438963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.2473438963
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2844899168
Short name T379
Test name
Test status
Simulation time 167936286010 ps
CPU time 256.84 seconds
Started Mar 19 12:38:38 PM PDT 24
Finished Mar 19 12:42:55 PM PDT 24
Peak memory 182540 kb
Host smart-372ce6b0-8e1f-4f9b-bb33-10d6e9e88196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844899168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2844899168
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.2672452446
Short name T232
Test name
Test status
Simulation time 247858325437 ps
CPU time 191.83 seconds
Started Mar 19 12:38:34 PM PDT 24
Finished Mar 19 12:41:46 PM PDT 24
Peak memory 190748 kb
Host smart-6bab03b6-d049-4e22-8702-e0daa4ca4b8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672452446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2672452446
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.3785321981
Short name T84
Test name
Test status
Simulation time 114142862960 ps
CPU time 150.35 seconds
Started Mar 19 12:38:33 PM PDT 24
Finished Mar 19 12:41:03 PM PDT 24
Peak memory 190744 kb
Host smart-e8672a58-18d1-4e9a-8657-076cc0377916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785321981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3785321981
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.727799987
Short name T330
Test name
Test status
Simulation time 190497310185 ps
CPU time 93.81 seconds
Started Mar 19 12:38:38 PM PDT 24
Finished Mar 19 12:40:12 PM PDT 24
Peak memory 182532 kb
Host smart-62e58281-fbe5-4fb8-92f0-7e3e8c2e26ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727799987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.727799987
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.1902805994
Short name T15
Test name
Test status
Simulation time 161159954553 ps
CPU time 343.64 seconds
Started Mar 19 12:38:35 PM PDT 24
Finished Mar 19 12:44:19 PM PDT 24
Peak memory 205412 kb
Host smart-8225ed9d-c118-47fe-8cc9-bd86ad2b7513
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902805994 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.1902805994
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.2638935993
Short name T430
Test name
Test status
Simulation time 69339961760 ps
CPU time 60.08 seconds
Started Mar 19 12:39:14 PM PDT 24
Finished Mar 19 12:40:15 PM PDT 24
Peak memory 190748 kb
Host smart-dd27013d-de51-493b-92d7-31ed3bd1c42a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638935993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2638935993
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1990849327
Short name T146
Test name
Test status
Simulation time 190393962572 ps
CPU time 1237.49 seconds
Started Mar 19 12:39:17 PM PDT 24
Finished Mar 19 12:59:55 PM PDT 24
Peak memory 190692 kb
Host smart-9ce59cd8-7145-4cbe-82f1-b95f28a3bf21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990849327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1990849327
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.2244811924
Short name T28
Test name
Test status
Simulation time 593679638167 ps
CPU time 644.64 seconds
Started Mar 19 12:39:13 PM PDT 24
Finished Mar 19 12:49:58 PM PDT 24
Peak memory 190728 kb
Host smart-aea94f03-a8a3-4e56-8f3f-f17be075ac05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244811924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.2244811924
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.4174027086
Short name T123
Test name
Test status
Simulation time 99564787599 ps
CPU time 360.13 seconds
Started Mar 19 12:39:12 PM PDT 24
Finished Mar 19 12:45:13 PM PDT 24
Peak memory 190800 kb
Host smart-987c3e76-e2d6-4d84-b06f-5f3592ec81ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174027086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.4174027086
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.319952812
Short name T297
Test name
Test status
Simulation time 90620581468 ps
CPU time 145.49 seconds
Started Mar 19 12:39:16 PM PDT 24
Finished Mar 19 12:41:41 PM PDT 24
Peak memory 190744 kb
Host smart-dc5e20d7-7387-4bb2-8664-eeeae0f9e811
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319952812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.319952812
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3238204107
Short name T416
Test name
Test status
Simulation time 143468311776 ps
CPU time 98.47 seconds
Started Mar 19 12:39:14 PM PDT 24
Finished Mar 19 12:40:53 PM PDT 24
Peak memory 193032 kb
Host smart-6ed03444-839e-4410-ba34-1a577086e000
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238204107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3238204107
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.563997976
Short name T73
Test name
Test status
Simulation time 138502509867 ps
CPU time 75.83 seconds
Started Mar 19 12:39:15 PM PDT 24
Finished Mar 19 12:40:31 PM PDT 24
Peak memory 190752 kb
Host smart-400a40f7-5c77-46ec-af94-f62d49b29109
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563997976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.563997976
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.251831049
Short name T24
Test name
Test status
Simulation time 6765629820 ps
CPU time 11.86 seconds
Started Mar 19 12:38:33 PM PDT 24
Finished Mar 19 12:38:45 PM PDT 24
Peak memory 182584 kb
Host smart-32841479-17f3-4f63-a6bd-9400cbb0b913
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251831049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.rv_timer_cfg_update_on_fly.251831049
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.3181154251
Short name T81
Test name
Test status
Simulation time 288776329167 ps
CPU time 123.35 seconds
Started Mar 19 12:38:35 PM PDT 24
Finished Mar 19 12:40:39 PM PDT 24
Peak memory 182588 kb
Host smart-0dd69614-f9be-4d89-9a40-3396e82419b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181154251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.3181154251
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2673581603
Short name T233
Test name
Test status
Simulation time 496824363564 ps
CPU time 321.54 seconds
Started Mar 19 12:38:32 PM PDT 24
Finished Mar 19 12:43:54 PM PDT 24
Peak memory 190688 kb
Host smart-b8737654-2f31-4ff7-a6ca-2f8530e15671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673581603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2673581603
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1044932928
Short name T246
Test name
Test status
Simulation time 463066953505 ps
CPU time 965.38 seconds
Started Mar 19 12:38:34 PM PDT 24
Finished Mar 19 12:54:39 PM PDT 24
Peak memory 190728 kb
Host smart-1546782f-b14e-491d-9728-bc1eb8658cdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044932928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1044932928
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.1152316220
Short name T356
Test name
Test status
Simulation time 58162690607 ps
CPU time 92.61 seconds
Started Mar 19 12:39:13 PM PDT 24
Finished Mar 19 12:40:46 PM PDT 24
Peak memory 190752 kb
Host smart-12ee259f-4e9e-408a-90dc-e50193b29e9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152316220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1152316220
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.1254836246
Short name T348
Test name
Test status
Simulation time 57351158087 ps
CPU time 49.56 seconds
Started Mar 19 12:39:14 PM PDT 24
Finished Mar 19 12:40:04 PM PDT 24
Peak memory 182548 kb
Host smart-dce5d5b3-38b4-40ac-afb1-79e561bb59a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254836246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1254836246
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.1784184322
Short name T421
Test name
Test status
Simulation time 97477695141 ps
CPU time 164.29 seconds
Started Mar 19 12:39:14 PM PDT 24
Finished Mar 19 12:41:59 PM PDT 24
Peak memory 190796 kb
Host smart-a4f7113c-f9e2-4d81-bc13-0790ddf871a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784184322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1784184322
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2850862858
Short name T304
Test name
Test status
Simulation time 59633772316 ps
CPU time 64.35 seconds
Started Mar 19 12:39:12 PM PDT 24
Finished Mar 19 12:40:17 PM PDT 24
Peak memory 190816 kb
Host smart-e9afb1b5-251b-47f7-a8f3-4a4f7ce23494
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850862858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2850862858
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.387917025
Short name T339
Test name
Test status
Simulation time 112558281671 ps
CPU time 180.94 seconds
Started Mar 19 12:39:14 PM PDT 24
Finished Mar 19 12:42:15 PM PDT 24
Peak memory 190752 kb
Host smart-0471b74a-5167-4d15-b42c-8dd287ba050e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387917025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.387917025
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3731040267
Short name T322
Test name
Test status
Simulation time 283365189147 ps
CPU time 2447.48 seconds
Started Mar 19 12:39:17 PM PDT 24
Finished Mar 19 01:20:05 PM PDT 24
Peak memory 190724 kb
Host smart-bf746dfe-6a34-47b8-bd3a-9755a07f5572
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731040267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3731040267
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2204660504
Short name T254
Test name
Test status
Simulation time 634824842768 ps
CPU time 340.86 seconds
Started Mar 19 12:39:14 PM PDT 24
Finished Mar 19 12:44:55 PM PDT 24
Peak memory 190796 kb
Host smart-b24532df-0322-43b8-a97c-d98bf37e7156
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204660504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2204660504
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.3514083260
Short name T6
Test name
Test status
Simulation time 101825949395 ps
CPU time 151.59 seconds
Started Mar 19 12:39:13 PM PDT 24
Finished Mar 19 12:41:45 PM PDT 24
Peak memory 190788 kb
Host smart-4eb878f7-fc38-4c2f-a035-c96335858eba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514083260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3514083260
Directory /workspace/99.rv_timer_random/latest
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