Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.57 99.36 98.73 100.00 100.00 100.00 99.32


Total test records in report: 579
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T511 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1015455854 Mar 21 12:48:45 PM PDT 24 Mar 21 12:48:49 PM PDT 24 122787666 ps
T101 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.870770765 Mar 21 12:48:10 PM PDT 24 Mar 21 12:48:11 PM PDT 24 16498925 ps
T512 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3748122852 Mar 21 12:48:57 PM PDT 24 Mar 21 12:48:58 PM PDT 24 58654908 ps
T513 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3599018205 Mar 21 12:48:34 PM PDT 24 Mar 21 12:48:34 PM PDT 24 31421081 ps
T514 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2844947574 Mar 21 12:48:52 PM PDT 24 Mar 21 12:48:53 PM PDT 24 49145611 ps
T515 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1667458246 Mar 21 12:48:53 PM PDT 24 Mar 21 12:48:53 PM PDT 24 101071170 ps
T102 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2585961707 Mar 21 12:48:46 PM PDT 24 Mar 21 12:48:50 PM PDT 24 39554797 ps
T516 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.41592405 Mar 21 12:48:27 PM PDT 24 Mar 21 12:48:28 PM PDT 24 17251716 ps
T517 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3262141527 Mar 21 12:49:04 PM PDT 24 Mar 21 12:49:05 PM PDT 24 14081268 ps
T124 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.542939499 Mar 21 12:48:16 PM PDT 24 Mar 21 12:48:16 PM PDT 24 174841752 ps
T518 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3870280633 Mar 21 12:48:21 PM PDT 24 Mar 21 12:48:22 PM PDT 24 60042450 ps
T103 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.4197925299 Mar 21 12:48:15 PM PDT 24 Mar 21 12:48:16 PM PDT 24 28858712 ps
T519 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1078279715 Mar 21 12:48:34 PM PDT 24 Mar 21 12:48:35 PM PDT 24 23307217 ps
T520 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2259792743 Mar 21 12:47:59 PM PDT 24 Mar 21 12:48:02 PM PDT 24 1042212984 ps
T521 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2460831520 Mar 21 12:49:14 PM PDT 24 Mar 21 12:49:15 PM PDT 24 82405861 ps
T522 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.4181953259 Mar 21 12:48:53 PM PDT 24 Mar 21 12:48:55 PM PDT 24 266058648 ps
T523 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3036828645 Mar 21 12:48:46 PM PDT 24 Mar 21 12:48:52 PM PDT 24 417478879 ps
T104 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3496209393 Mar 21 12:48:16 PM PDT 24 Mar 21 12:48:19 PM PDT 24 948618072 ps
T524 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1395501898 Mar 21 12:48:44 PM PDT 24 Mar 21 12:48:48 PM PDT 24 161422069 ps
T525 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1480428770 Mar 21 12:48:25 PM PDT 24 Mar 21 12:48:27 PM PDT 24 62071751 ps
T526 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3015288839 Mar 21 12:49:04 PM PDT 24 Mar 21 12:49:05 PM PDT 24 19754561 ps
T527 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.918628936 Mar 21 12:49:05 PM PDT 24 Mar 21 12:49:05 PM PDT 24 31155086 ps
T528 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.376693788 Mar 21 12:48:35 PM PDT 24 Mar 21 12:48:36 PM PDT 24 60968917 ps
T105 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3963867532 Mar 21 12:48:15 PM PDT 24 Mar 21 12:48:16 PM PDT 24 26735049 ps
T529 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2230501764 Mar 21 12:48:26 PM PDT 24 Mar 21 12:48:27 PM PDT 24 18248429 ps
T530 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.4256358345 Mar 21 12:48:53 PM PDT 24 Mar 21 12:48:54 PM PDT 24 13074817 ps
T531 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2296846897 Mar 21 12:48:01 PM PDT 24 Mar 21 12:48:03 PM PDT 24 201489477 ps
T106 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.238549933 Mar 21 12:48:53 PM PDT 24 Mar 21 12:48:54 PM PDT 24 13073106 ps
T532 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.3349175929 Mar 21 12:48:47 PM PDT 24 Mar 21 12:48:51 PM PDT 24 29591737 ps
T533 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.792026461 Mar 21 12:48:27 PM PDT 24 Mar 21 12:48:28 PM PDT 24 49973338 ps
T534 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1135333502 Mar 21 12:48:16 PM PDT 24 Mar 21 12:48:17 PM PDT 24 63456270 ps
T535 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.4152783271 Mar 21 12:48:16 PM PDT 24 Mar 21 12:48:17 PM PDT 24 14426669 ps
T536 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2028099839 Mar 21 12:49:02 PM PDT 24 Mar 21 12:49:03 PM PDT 24 29055343 ps
T537 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.4001595056 Mar 21 12:49:13 PM PDT 24 Mar 21 12:49:13 PM PDT 24 12274489 ps
T538 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2232490334 Mar 21 12:48:51 PM PDT 24 Mar 21 12:48:53 PM PDT 24 11982958 ps
T539 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.324820810 Mar 21 12:49:03 PM PDT 24 Mar 21 12:49:05 PM PDT 24 165433901 ps
T107 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.936058342 Mar 21 12:48:44 PM PDT 24 Mar 21 12:48:49 PM PDT 24 15493848 ps
T540 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3413463814 Mar 21 12:48:51 PM PDT 24 Mar 21 12:48:53 PM PDT 24 105926261 ps
T541 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2695409284 Mar 21 12:48:53 PM PDT 24 Mar 21 12:48:55 PM PDT 24 194195812 ps
T108 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3513933240 Mar 21 12:48:34 PM PDT 24 Mar 21 12:48:35 PM PDT 24 17604318 ps
T542 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.4227353962 Mar 21 12:48:53 PM PDT 24 Mar 21 12:48:55 PM PDT 24 1348498553 ps
T543 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2152124093 Mar 21 12:48:15 PM PDT 24 Mar 21 12:48:18 PM PDT 24 843564295 ps
T544 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3784898554 Mar 21 12:48:40 PM PDT 24 Mar 21 12:48:43 PM PDT 24 25258310 ps
T545 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1991521873 Mar 21 12:48:54 PM PDT 24 Mar 21 12:48:55 PM PDT 24 45040867 ps
T546 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1183756356 Mar 21 12:48:21 PM PDT 24 Mar 21 12:48:23 PM PDT 24 160629764 ps
T547 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.312933865 Mar 21 12:49:04 PM PDT 24 Mar 21 12:49:05 PM PDT 24 14642975 ps
T548 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.910765852 Mar 21 12:49:18 PM PDT 24 Mar 21 12:49:19 PM PDT 24 35429276 ps
T549 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2433908034 Mar 21 12:48:45 PM PDT 24 Mar 21 12:48:49 PM PDT 24 27681630 ps
T550 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.4170220340 Mar 21 12:48:10 PM PDT 24 Mar 21 12:48:14 PM PDT 24 175450580 ps
T551 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.448854175 Mar 21 12:48:13 PM PDT 24 Mar 21 12:48:14 PM PDT 24 13817491 ps
T552 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.334836130 Mar 21 12:48:43 PM PDT 24 Mar 21 12:48:46 PM PDT 24 445350361 ps
T553 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2971997017 Mar 21 12:49:04 PM PDT 24 Mar 21 12:49:05 PM PDT 24 11624636 ps
T554 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2144398277 Mar 21 12:48:27 PM PDT 24 Mar 21 12:48:28 PM PDT 24 148215354 ps
T555 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.761798801 Mar 21 12:48:08 PM PDT 24 Mar 21 12:48:10 PM PDT 24 46235675 ps
T556 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2079402497 Mar 21 12:48:33 PM PDT 24 Mar 21 12:48:34 PM PDT 24 19545500 ps
T557 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3433377894 Mar 21 12:48:46 PM PDT 24 Mar 21 12:48:51 PM PDT 24 32544348 ps
T558 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1261081556 Mar 21 12:49:04 PM PDT 24 Mar 21 12:49:05 PM PDT 24 42801698 ps
T559 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.4099291076 Mar 21 12:49:04 PM PDT 24 Mar 21 12:49:04 PM PDT 24 54672968 ps
T560 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.620566203 Mar 21 12:49:16 PM PDT 24 Mar 21 12:49:17 PM PDT 24 14786719 ps
T561 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2093596617 Mar 21 12:48:17 PM PDT 24 Mar 21 12:48:18 PM PDT 24 102900282 ps
T562 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.4072721729 Mar 21 12:49:14 PM PDT 24 Mar 21 12:49:15 PM PDT 24 22531787 ps
T563 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.4154015322 Mar 21 12:49:04 PM PDT 24 Mar 21 12:49:05 PM PDT 24 13095381 ps
T564 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2528724526 Mar 21 12:48:46 PM PDT 24 Mar 21 12:48:51 PM PDT 24 159583605 ps
T565 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.265701113 Mar 21 12:48:33 PM PDT 24 Mar 21 12:48:34 PM PDT 24 25180897 ps
T566 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1161454688 Mar 21 12:49:04 PM PDT 24 Mar 21 12:49:04 PM PDT 24 141595079 ps
T567 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2906158994 Mar 21 12:48:26 PM PDT 24 Mar 21 12:48:28 PM PDT 24 72376415 ps
T568 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3266392274 Mar 21 12:49:03 PM PDT 24 Mar 21 12:49:04 PM PDT 24 25381536 ps
T569 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2468195847 Mar 21 12:48:53 PM PDT 24 Mar 21 12:48:54 PM PDT 24 15806887 ps
T109 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1736048465 Mar 21 12:48:27 PM PDT 24 Mar 21 12:48:28 PM PDT 24 52956527 ps
T570 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3648804897 Mar 21 12:48:17 PM PDT 24 Mar 21 12:48:18 PM PDT 24 38048925 ps
T571 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.4249857410 Mar 21 12:48:43 PM PDT 24 Mar 21 12:48:46 PM PDT 24 44263988 ps
T572 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1525688531 Mar 21 12:48:15 PM PDT 24 Mar 21 12:48:17 PM PDT 24 163851007 ps
T573 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.556499372 Mar 21 12:48:43 PM PDT 24 Mar 21 12:48:47 PM PDT 24 262552722 ps
T574 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3814889278 Mar 21 12:48:36 PM PDT 24 Mar 21 12:48:37 PM PDT 24 121120232 ps
T575 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.825874276 Mar 21 12:49:15 PM PDT 24 Mar 21 12:49:15 PM PDT 24 101255101 ps
T576 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2037780063 Mar 21 12:48:27 PM PDT 24 Mar 21 12:48:28 PM PDT 24 12920932 ps
T577 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3480567989 Mar 21 12:49:15 PM PDT 24 Mar 21 12:49:15 PM PDT 24 142490974 ps
T578 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2978558296 Mar 21 12:48:16 PM PDT 24 Mar 21 12:48:17 PM PDT 24 190422745 ps
T579 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3312315688 Mar 21 12:49:05 PM PDT 24 Mar 21 12:49:05 PM PDT 24 16142569 ps

Test location /workspace/coverage/default/139.rv_timer_random.76189681
Short name T9
Test name
Test status
Simulation time 453263041133 ps
CPU time 268.25 seconds
Started Mar 21 12:52:40 PM PDT 24
Finished Mar 21 12:57:08 PM PDT 24
Peak memory 190792 kb
Host smart-25986322-e0de-4145-8a35-c1dd7abc571f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76189681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.76189681
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.3063132961
Short name T13
Test name
Test status
Simulation time 36546153459 ps
CPU time 149.75 seconds
Started Mar 21 12:50:43 PM PDT 24
Finished Mar 21 12:53:13 PM PDT 24
Peak memory 197216 kb
Host smart-fff1e37b-5b96-4d74-b298-8e3b0e83e556
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063132961 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.3063132961
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.4059113151
Short name T30
Test name
Test status
Simulation time 220494936 ps
CPU time 0.82 seconds
Started Mar 21 12:48:15 PM PDT 24
Finished Mar 21 12:48:16 PM PDT 24
Peak memory 193720 kb
Host smart-0b205416-fa5e-4479-8093-ad113c73b241
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059113151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.4059113151
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.4221647291
Short name T71
Test name
Test status
Simulation time 682333117286 ps
CPU time 1319.41 seconds
Started Mar 21 12:50:44 PM PDT 24
Finished Mar 21 01:12:44 PM PDT 24
Peak memory 190772 kb
Host smart-aa6afd8c-caca-4a10-891d-f1a0b55e0713
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221647291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.4221647291
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1972815920
Short name T179
Test name
Test status
Simulation time 878115627683 ps
CPU time 2769.37 seconds
Started Mar 21 12:50:37 PM PDT 24
Finished Mar 21 01:36:47 PM PDT 24
Peak memory 196536 kb
Host smart-5a75cc79-3950-4e65-af55-32d39450b8f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972815920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1972815920
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.4213901816
Short name T168
Test name
Test status
Simulation time 1152328946860 ps
CPU time 1899.48 seconds
Started Mar 21 12:51:29 PM PDT 24
Finished Mar 21 01:23:10 PM PDT 24
Peak memory 190752 kb
Host smart-8e76d068-cc79-4cbc-9bad-b054a698bdc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213901816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.4213901816
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.2207473697
Short name T144
Test name
Test status
Simulation time 516884627812 ps
CPU time 1938.18 seconds
Started Mar 21 12:50:17 PM PDT 24
Finished Mar 21 01:22:37 PM PDT 24
Peak memory 190772 kb
Host smart-e3cdf80c-2189-480d-86ba-101a289b4f2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207473697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.2207473697
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.4003465522
Short name T211
Test name
Test status
Simulation time 766002911069 ps
CPU time 2371.64 seconds
Started Mar 21 12:51:04 PM PDT 24
Finished Mar 21 01:30:36 PM PDT 24
Peak memory 190800 kb
Host smart-36e781ef-8869-47d7-a325-37ab57a38146
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003465522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.4003465522
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.899642288
Short name T73
Test name
Test status
Simulation time 405046270472 ps
CPU time 847.23 seconds
Started Mar 21 12:50:11 PM PDT 24
Finished Mar 21 01:04:18 PM PDT 24
Peak memory 190812 kb
Host smart-d1aef560-0674-4936-bb3d-41a63876fec5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899642288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.899642288
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3396090868
Short name T46
Test name
Test status
Simulation time 2708707740807 ps
CPU time 3557.23 seconds
Started Mar 21 12:50:45 PM PDT 24
Finished Mar 21 01:50:03 PM PDT 24
Peak memory 190744 kb
Host smart-41bb5841-5970-4307-89bd-17e122b8a070
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396090868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3396090868
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2368853188
Short name T34
Test name
Test status
Simulation time 33895428 ps
CPU time 0.61 seconds
Started Mar 21 12:48:01 PM PDT 24
Finished Mar 21 12:48:03 PM PDT 24
Peak memory 182716 kb
Host smart-d3940b06-586e-4b66-87be-89dcb9a08b31
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368853188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2368853188
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.769307276
Short name T76
Test name
Test status
Simulation time 491564714886 ps
CPU time 1450.63 seconds
Started Mar 21 12:50:36 PM PDT 24
Finished Mar 21 01:14:47 PM PDT 24
Peak memory 190772 kb
Host smart-a8387bac-8c6c-451f-8726-2e4a9c0cf0f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769307276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.
769307276
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.2090813718
Short name T193
Test name
Test status
Simulation time 532483402006 ps
CPU time 1387.9 seconds
Started Mar 21 12:50:40 PM PDT 24
Finished Mar 21 01:13:48 PM PDT 24
Peak memory 190808 kb
Host smart-1318fea7-bdb1-4dcd-bbd9-0f316c141e87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090813718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.2090813718
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2246233690
Short name T161
Test name
Test status
Simulation time 684248261974 ps
CPU time 3030.47 seconds
Started Mar 21 12:50:36 PM PDT 24
Finished Mar 21 01:41:07 PM PDT 24
Peak memory 195480 kb
Host smart-f2c2972d-6776-4d31-927c-4f75d6121e91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246233690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2246233690
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2791470247
Short name T20
Test name
Test status
Simulation time 175074833 ps
CPU time 0.74 seconds
Started Mar 21 12:50:07 PM PDT 24
Finished Mar 21 12:50:09 PM PDT 24
Peak memory 213148 kb
Host smart-11b0eaf2-f0e1-4057-8644-98960b78fc4d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791470247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2791470247
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/41.rv_timer_random.1203759653
Short name T131
Test name
Test status
Simulation time 879220400329 ps
CPU time 893.18 seconds
Started Mar 21 12:51:03 PM PDT 24
Finished Mar 21 01:05:56 PM PDT 24
Peak memory 190776 kb
Host smart-d5119867-ee23-4905-90c6-ca1cc601f8e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203759653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1203759653
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2513525382
Short name T24
Test name
Test status
Simulation time 170414498020 ps
CPU time 500.64 seconds
Started Mar 21 12:52:51 PM PDT 24
Finished Mar 21 01:01:12 PM PDT 24
Peak memory 190764 kb
Host smart-033b9eb7-d994-41b8-9496-448e3f4ca91f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513525382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2513525382
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2877663295
Short name T182
Test name
Test status
Simulation time 383006127362 ps
CPU time 2845.08 seconds
Started Mar 21 12:50:57 PM PDT 24
Finished Mar 21 01:38:22 PM PDT 24
Peak memory 190748 kb
Host smart-3b094cee-03bc-4a33-a5b0-f81d8590759b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877663295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2877663295
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_random.1819187358
Short name T269
Test name
Test status
Simulation time 155999606144 ps
CPU time 246.73 seconds
Started Mar 21 12:50:55 PM PDT 24
Finished Mar 21 12:55:01 PM PDT 24
Peak memory 190784 kb
Host smart-b7cc9ac8-8afd-4a0f-a8a3-acd78ce6ce9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819187358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1819187358
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.1435376338
Short name T225
Test name
Test status
Simulation time 144189640934 ps
CPU time 463.22 seconds
Started Mar 21 12:51:49 PM PDT 24
Finished Mar 21 12:59:33 PM PDT 24
Peak memory 190756 kb
Host smart-01473c20-6cf8-4a08-9742-7fac2a54f637
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435376338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1435376338
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random.2563932185
Short name T33
Test name
Test status
Simulation time 192443597354 ps
CPU time 350.09 seconds
Started Mar 21 12:50:19 PM PDT 24
Finished Mar 21 12:56:10 PM PDT 24
Peak memory 190520 kb
Host smart-2e26489e-27a5-46b9-9a32-c91a35a6ba00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563932185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2563932185
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.930751732
Short name T50
Test name
Test status
Simulation time 145512073444 ps
CPU time 395.43 seconds
Started Mar 21 12:52:17 PM PDT 24
Finished Mar 21 12:58:53 PM PDT 24
Peak memory 190784 kb
Host smart-6c919261-1aff-4e7c-af56-286f910dbd86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930751732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.930751732
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.2409378419
Short name T234
Test name
Test status
Simulation time 423308011194 ps
CPU time 1541.18 seconds
Started Mar 21 12:50:26 PM PDT 24
Finished Mar 21 01:16:07 PM PDT 24
Peak memory 190748 kb
Host smart-76e807f0-af64-4c0d-bdf1-1b6f038ed1a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409378419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.2409378419
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1449196165
Short name T74
Test name
Test status
Simulation time 1204769133759 ps
CPU time 1090.22 seconds
Started Mar 21 12:50:10 PM PDT 24
Finished Mar 21 01:08:21 PM PDT 24
Peak memory 190844 kb
Host smart-cf992969-58ae-42c0-ab3e-b7d5f1478870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449196165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1449196165
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.2170036768
Short name T67
Test name
Test status
Simulation time 397238491531 ps
CPU time 346.9 seconds
Started Mar 21 12:50:18 PM PDT 24
Finished Mar 21 12:56:06 PM PDT 24
Peak memory 190560 kb
Host smart-e7514440-e45a-4dfd-975c-de45071c6538
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170036768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.2170036768
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/149.rv_timer_random.2801830856
Short name T22
Test name
Test status
Simulation time 131552789300 ps
CPU time 313.92 seconds
Started Mar 21 12:52:42 PM PDT 24
Finished Mar 21 12:57:56 PM PDT 24
Peak memory 191024 kb
Host smart-70e83d1d-1411-4177-9077-1ec547d75d1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801830856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2801830856
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1695835159
Short name T6
Test name
Test status
Simulation time 930131144515 ps
CPU time 751.08 seconds
Started Mar 21 12:50:57 PM PDT 24
Finished Mar 21 01:03:28 PM PDT 24
Peak memory 182628 kb
Host smart-e1208d8f-2280-430b-9d06-645ea2aa7e1e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695835159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1695835159
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/133.rv_timer_random.2109652216
Short name T433
Test name
Test status
Simulation time 1083128162357 ps
CPU time 1709.94 seconds
Started Mar 21 12:52:33 PM PDT 24
Finished Mar 21 01:21:03 PM PDT 24
Peak memory 190780 kb
Host smart-8fa09caf-e673-42c2-b458-cd19134c8cff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109652216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2109652216
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random.1107561730
Short name T277
Test name
Test status
Simulation time 809730739202 ps
CPU time 1037.89 seconds
Started Mar 21 12:50:29 PM PDT 24
Finished Mar 21 01:07:47 PM PDT 24
Peak memory 190720 kb
Host smart-8be2faa6-277d-44d8-830a-e824afe6b98b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107561730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1107561730
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1997679799
Short name T160
Test name
Test status
Simulation time 153061976974 ps
CPU time 1200.23 seconds
Started Mar 21 12:52:15 PM PDT 24
Finished Mar 21 01:12:15 PM PDT 24
Peak memory 190776 kb
Host smart-a150c3a6-b7f9-4fca-8390-1fecb9f97fe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997679799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1997679799
Directory /workspace/99.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random.1045932618
Short name T62
Test name
Test status
Simulation time 1016939554455 ps
CPU time 174.64 seconds
Started Mar 21 12:50:36 PM PDT 24
Finished Mar 21 12:53:31 PM PDT 24
Peak memory 190748 kb
Host smart-023de94d-8da2-4d10-ad9d-35c6e4d1bc91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045932618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1045932618
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.4207986254
Short name T242
Test name
Test status
Simulation time 103186218143 ps
CPU time 548.34 seconds
Started Mar 21 12:52:04 PM PDT 24
Finished Mar 21 01:01:13 PM PDT 24
Peak memory 190740 kb
Host smart-a7b9b2a7-831f-4010-aff2-945c93a0342d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207986254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.4207986254
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2267223638
Short name T122
Test name
Test status
Simulation time 613724729652 ps
CPU time 419.8 seconds
Started Mar 21 12:52:52 PM PDT 24
Finished Mar 21 12:59:53 PM PDT 24
Peak memory 190760 kb
Host smart-92b7629d-ffce-49b4-9528-549ab5586596
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267223638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2267223638
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.383979077
Short name T68
Test name
Test status
Simulation time 1065350876285 ps
CPU time 804.5 seconds
Started Mar 21 12:52:58 PM PDT 24
Finished Mar 21 01:06:23 PM PDT 24
Peak memory 190732 kb
Host smart-0fd6641b-9771-4937-a38f-12ad2682dd72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383979077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.383979077
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.723407748
Short name T165
Test name
Test status
Simulation time 560456542897 ps
CPU time 2472.62 seconds
Started Mar 21 12:50:35 PM PDT 24
Finished Mar 21 01:31:48 PM PDT 24
Peak memory 190764 kb
Host smart-65fc5cf9-f34b-4e84-941c-7aaf74a6766c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723407748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.
723407748
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.2531102635
Short name T339
Test name
Test status
Simulation time 686802796836 ps
CPU time 269.65 seconds
Started Mar 21 12:51:50 PM PDT 24
Finished Mar 21 12:56:21 PM PDT 24
Peak memory 190724 kb
Host smart-1e5fe839-c695-406a-a134-18eb870f84ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531102635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2531102635
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3270624017
Short name T97
Test name
Test status
Simulation time 21415682 ps
CPU time 0.56 seconds
Started Mar 21 12:49:02 PM PDT 24
Finished Mar 21 12:49:03 PM PDT 24
Peak memory 182636 kb
Host smart-84d71a31-b6b7-4ad4-a9c0-f9b71337cda8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270624017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.3270624017
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/123.rv_timer_random.3200502345
Short name T127
Test name
Test status
Simulation time 226555594231 ps
CPU time 808.21 seconds
Started Mar 21 12:52:26 PM PDT 24
Finished Mar 21 01:05:54 PM PDT 24
Peak memory 190760 kb
Host smart-451bd26d-ded3-4047-b5c9-a3a22be94abc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200502345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3200502345
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.2367611880
Short name T178
Test name
Test status
Simulation time 1075820372511 ps
CPU time 535.34 seconds
Started Mar 21 12:52:26 PM PDT 24
Finished Mar 21 01:01:21 PM PDT 24
Peak memory 190748 kb
Host smart-6c4c102e-fe78-4dab-bfa7-1f27264a4394
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367611880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2367611880
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1536420695
Short name T247
Test name
Test status
Simulation time 5074919610802 ps
CPU time 1604.62 seconds
Started Mar 21 12:50:23 PM PDT 24
Finished Mar 21 01:17:08 PM PDT 24
Peak memory 195092 kb
Host smart-84c8ff64-e8bd-4a75-b7f2-6c50f3a74088
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536420695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1536420695
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/188.rv_timer_random.1248560862
Short name T330
Test name
Test status
Simulation time 193502609441 ps
CPU time 174.06 seconds
Started Mar 21 12:52:58 PM PDT 24
Finished Mar 21 12:55:52 PM PDT 24
Peak memory 190764 kb
Host smart-76c7ae85-dd6a-4f31-bd05-f87d00e5aa89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248560862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1248560862
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.439555047
Short name T281
Test name
Test status
Simulation time 383709019176 ps
CPU time 691.47 seconds
Started Mar 21 12:53:10 PM PDT 24
Finished Mar 21 01:04:41 PM PDT 24
Peak memory 190708 kb
Host smart-d9ac010b-3891-4a9a-97fe-9af37b0ffbe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439555047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.439555047
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2210357915
Short name T129
Test name
Test status
Simulation time 443912346031 ps
CPU time 439.3 seconds
Started Mar 21 12:53:08 PM PDT 24
Finished Mar 21 01:00:28 PM PDT 24
Peak memory 194372 kb
Host smart-f859ec10-3638-403f-b254-dada4443f256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210357915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2210357915
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.2140762842
Short name T262
Test name
Test status
Simulation time 124317170124 ps
CPU time 210.94 seconds
Started Mar 21 12:50:36 PM PDT 24
Finished Mar 21 12:54:07 PM PDT 24
Peak memory 182848 kb
Host smart-ba521a3b-a432-4498-ad11-825674238708
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140762842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.2140762842
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/77.rv_timer_random.1938039184
Short name T28
Test name
Test status
Simulation time 488875893159 ps
CPU time 374.01 seconds
Started Mar 21 12:52:06 PM PDT 24
Finished Mar 21 12:58:20 PM PDT 24
Peak memory 190744 kb
Host smart-91ec75e1-ceaa-478e-8b63-01e68661bae9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938039184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1938039184
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.542939499
Short name T124
Test name
Test status
Simulation time 174841752 ps
CPU time 0.78 seconds
Started Mar 21 12:48:16 PM PDT 24
Finished Mar 21 12:48:16 PM PDT 24
Peak memory 183048 kb
Host smart-f5cef841-8941-43e8-a1bf-4118ac086460
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542939499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_int
g_err.542939499
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/109.rv_timer_random.2178610857
Short name T354
Test name
Test status
Simulation time 314074813495 ps
CPU time 419.28 seconds
Started Mar 21 12:52:15 PM PDT 24
Finished Mar 21 12:59:15 PM PDT 24
Peak memory 190764 kb
Host smart-039de6ea-f171-4830-8694-85afec0cb9fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178610857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2178610857
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.1726997791
Short name T316
Test name
Test status
Simulation time 469602863446 ps
CPU time 345.97 seconds
Started Mar 21 12:52:27 PM PDT 24
Finished Mar 21 12:58:13 PM PDT 24
Peak memory 192916 kb
Host smart-56b5b41d-c7ba-44e1-8b33-a0e4bf28d39c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726997791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1726997791
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.1620788560
Short name T199
Test name
Test status
Simulation time 142565950564 ps
CPU time 159.51 seconds
Started Mar 21 12:50:29 PM PDT 24
Finished Mar 21 12:53:09 PM PDT 24
Peak memory 190720 kb
Host smart-e599a0cb-8eb9-4b71-ae48-de1eb187c981
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620788560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1620788560
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.3601577503
Short name T188
Test name
Test status
Simulation time 153462251238 ps
CPU time 247.73 seconds
Started Mar 21 12:52:51 PM PDT 24
Finished Mar 21 12:56:59 PM PDT 24
Peak memory 190760 kb
Host smart-ff4a5a2b-340a-4455-9132-12ead610210a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601577503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3601577503
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.2618266654
Short name T214
Test name
Test status
Simulation time 618368360733 ps
CPU time 1956.5 seconds
Started Mar 21 12:52:51 PM PDT 24
Finished Mar 21 01:25:28 PM PDT 24
Peak memory 190816 kb
Host smart-fd3de2aa-5d60-47c0-8a4e-2f2227fc8ec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618266654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2618266654
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.832179262
Short name T140
Test name
Test status
Simulation time 92188614702 ps
CPU time 142.51 seconds
Started Mar 21 12:52:58 PM PDT 24
Finished Mar 21 12:55:21 PM PDT 24
Peak memory 193028 kb
Host smart-e34feb19-4000-44af-9421-73dfcf5a4a9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832179262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.832179262
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3941572122
Short name T10
Test name
Test status
Simulation time 2696981664088 ps
CPU time 1334.48 seconds
Started Mar 21 12:50:06 PM PDT 24
Finished Mar 21 01:12:21 PM PDT 24
Peak memory 182576 kb
Host smart-d2d73143-0d2e-41e1-a774-9bf6791b143f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941572122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3941572122
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_random.3119134148
Short name T222
Test name
Test status
Simulation time 1910750728724 ps
CPU time 1132.69 seconds
Started Mar 21 12:50:36 PM PDT 24
Finished Mar 21 01:09:29 PM PDT 24
Peak memory 190752 kb
Host smart-20ed9432-278b-4715-b5a3-39646b575c60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119134148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3119134148
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3912163293
Short name T361
Test name
Test status
Simulation time 313396910246 ps
CPU time 86.78 seconds
Started Mar 21 12:50:46 PM PDT 24
Finished Mar 21 12:52:13 PM PDT 24
Peak memory 195216 kb
Host smart-87acd931-a101-4d6c-a81d-039b3f39adb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912163293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3912163293
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.2439642974
Short name T132
Test name
Test status
Simulation time 3166183671132 ps
CPU time 2003.28 seconds
Started Mar 21 12:51:40 PM PDT 24
Finished Mar 21 01:25:03 PM PDT 24
Peak memory 190748 kb
Host smart-4110a0e7-5cf2-4696-9941-97d4c170d6c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439642974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.2439642974
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_random.3402495032
Short name T162
Test name
Test status
Simulation time 335385771586 ps
CPU time 264.38 seconds
Started Mar 21 12:50:16 PM PDT 24
Finished Mar 21 12:54:42 PM PDT 24
Peak memory 190780 kb
Host smart-703a2275-fed3-4024-a714-abad129197d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402495032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3402495032
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.192555012
Short name T298
Test name
Test status
Simulation time 2163445745799 ps
CPU time 1293.08 seconds
Started Mar 21 12:50:19 PM PDT 24
Finished Mar 21 01:11:53 PM PDT 24
Peak memory 182532 kb
Host smart-7de799db-3ccc-4140-a149-fdfb7d950381
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192555012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.rv_timer_cfg_update_on_fly.192555012
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.4015250229
Short name T52
Test name
Test status
Simulation time 310424781165 ps
CPU time 564.77 seconds
Started Mar 21 12:50:07 PM PDT 24
Finished Mar 21 12:59:32 PM PDT 24
Peak memory 182612 kb
Host smart-465e3eb6-feba-4b3a-bb4c-15ac3289ae26
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015250229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.4015250229
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/103.rv_timer_random.1208513484
Short name T205
Test name
Test status
Simulation time 204316229790 ps
CPU time 181.23 seconds
Started Mar 21 12:52:13 PM PDT 24
Finished Mar 21 12:55:14 PM PDT 24
Peak memory 190744 kb
Host smart-af95f6fa-c2a7-466d-a5de-e6c334455a3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208513484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1208513484
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.3198762644
Short name T275
Test name
Test status
Simulation time 229006185926 ps
CPU time 237.54 seconds
Started Mar 21 12:52:15 PM PDT 24
Finished Mar 21 12:56:12 PM PDT 24
Peak memory 190724 kb
Host smart-06531e89-240d-4a85-a83c-f7b9f4516e0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198762644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3198762644
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.2665268384
Short name T134
Test name
Test status
Simulation time 131409709887 ps
CPU time 974.41 seconds
Started Mar 21 12:52:25 PM PDT 24
Finished Mar 21 01:08:40 PM PDT 24
Peak memory 193868 kb
Host smart-1d4196b2-68c3-4f73-b1a5-f64843ab1c05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665268384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2665268384
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.1567102702
Short name T304
Test name
Test status
Simulation time 120960000862 ps
CPU time 319.27 seconds
Started Mar 21 12:53:00 PM PDT 24
Finished Mar 21 12:58:20 PM PDT 24
Peak memory 190716 kb
Host smart-f3a5f44d-d7cf-4a10-baad-14f0ae95e469
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567102702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1567102702
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.3529745166
Short name T332
Test name
Test status
Simulation time 133506350314 ps
CPU time 218.31 seconds
Started Mar 21 12:52:57 PM PDT 24
Finished Mar 21 12:56:35 PM PDT 24
Peak memory 193080 kb
Host smart-78b3aa29-4680-43c6-a993-2b8a0f37ce88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529745166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3529745166
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1591496024
Short name T353
Test name
Test status
Simulation time 57864961267 ps
CPU time 27.36 seconds
Started Mar 21 12:50:28 PM PDT 24
Finished Mar 21 12:50:55 PM PDT 24
Peak memory 182576 kb
Host smart-139a2462-4d8f-484d-9d37-6419735a599c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591496024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1591496024
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/176.rv_timer_random.2659436959
Short name T197
Test name
Test status
Simulation time 47738504169 ps
CPU time 133.24 seconds
Started Mar 21 12:52:59 PM PDT 24
Finished Mar 21 12:55:13 PM PDT 24
Peak memory 190820 kb
Host smart-e061ddb1-37aa-4a24-8d9b-68b3d43c96d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659436959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2659436959
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.1687911292
Short name T212
Test name
Test status
Simulation time 108279694718 ps
CPU time 240.15 seconds
Started Mar 21 12:52:59 PM PDT 24
Finished Mar 21 12:56:59 PM PDT 24
Peak memory 190736 kb
Host smart-d2d7852c-129e-481d-9e79-aa844a154ff9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687911292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1687911292
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.931240489
Short name T256
Test name
Test status
Simulation time 1536556819301 ps
CPU time 719.8 seconds
Started Mar 21 12:53:10 PM PDT 24
Finished Mar 21 01:05:10 PM PDT 24
Peak memory 190756 kb
Host smart-3aa5d796-8772-4af9-ac1e-0f2d597033da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931240489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.931240489
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1633139940
Short name T350
Test name
Test status
Simulation time 337663640132 ps
CPU time 193.45 seconds
Started Mar 21 12:51:39 PM PDT 24
Finished Mar 21 12:54:52 PM PDT 24
Peak memory 190700 kb
Host smart-898851ed-e413-49ab-83b6-b0c5c6376caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633139940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1633139940
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1143543831
Short name T267
Test name
Test status
Simulation time 166753498512 ps
CPU time 245.26 seconds
Started Mar 21 12:50:16 PM PDT 24
Finished Mar 21 12:54:23 PM PDT 24
Peak memory 182644 kb
Host smart-6d363f51-95bb-4a6f-93a6-10d518943036
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143543831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1143543831
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/63.rv_timer_random.556697470
Short name T190
Test name
Test status
Simulation time 494924068297 ps
CPU time 179.04 seconds
Started Mar 21 12:51:52 PM PDT 24
Finished Mar 21 12:54:51 PM PDT 24
Peak memory 192924 kb
Host smart-e89dd60c-0c83-40a0-beee-11efcf535ccd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556697470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.556697470
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.537941206
Short name T176
Test name
Test status
Simulation time 648245466151 ps
CPU time 1172.56 seconds
Started Mar 21 12:51:51 PM PDT 24
Finished Mar 21 01:11:25 PM PDT 24
Peak memory 190824 kb
Host smart-c76e6193-5d8b-4c31-bc6e-2ae111190ba9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537941206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.537941206
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.546083745
Short name T236
Test name
Test status
Simulation time 528803112773 ps
CPU time 1352.57 seconds
Started Mar 21 12:52:02 PM PDT 24
Finished Mar 21 01:14:35 PM PDT 24
Peak memory 190824 kb
Host smart-916a0884-f3e4-4376-ab75-f3ec74e436f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546083745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.546083745
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.2355492677
Short name T170
Test name
Test status
Simulation time 3444646406407 ps
CPU time 1357.48 seconds
Started Mar 21 12:52:05 PM PDT 24
Finished Mar 21 01:14:43 PM PDT 24
Peak memory 190772 kb
Host smart-d9fa85d2-9b78-4e07-a6fa-3410a55d6756
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355492677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.2355492677
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.2312684380
Short name T285
Test name
Test status
Simulation time 60206239198 ps
CPU time 203.39 seconds
Started Mar 21 12:52:16 PM PDT 24
Finished Mar 21 12:55:40 PM PDT 24
Peak memory 190764 kb
Host smart-f4df17ff-cf81-4113-b11a-5f9535e45e15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312684380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2312684380
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random.2732026018
Short name T133
Test name
Test status
Simulation time 104861600692 ps
CPU time 106.57 seconds
Started Mar 21 12:50:17 PM PDT 24
Finished Mar 21 12:52:05 PM PDT 24
Peak memory 190768 kb
Host smart-366d9afc-51d1-4ebc-af78-eed87cc2396c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732026018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2732026018
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.2279784701
Short name T203
Test name
Test status
Simulation time 222525766824 ps
CPU time 173.52 seconds
Started Mar 21 12:52:28 PM PDT 24
Finished Mar 21 12:55:22 PM PDT 24
Peak memory 190764 kb
Host smart-feee5de5-5dfe-4310-a07e-b59d6f904cc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279784701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2279784701
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.3351303033
Short name T317
Test name
Test status
Simulation time 86967574544 ps
CPU time 246.17 seconds
Started Mar 21 12:52:25 PM PDT 24
Finished Mar 21 12:56:31 PM PDT 24
Peak memory 190736 kb
Host smart-7f4f1f67-2f1c-4590-b5aa-0483c800015a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351303033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3351303033
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3816293618
Short name T121
Test name
Test status
Simulation time 56416694060 ps
CPU time 409.98 seconds
Started Mar 21 12:52:23 PM PDT 24
Finished Mar 21 12:59:13 PM PDT 24
Peak memory 190768 kb
Host smart-16c3a50b-63b5-4fb3-8113-4da730c42405
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816293618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3816293618
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.3896095909
Short name T137
Test name
Test status
Simulation time 163527394390 ps
CPU time 189.89 seconds
Started Mar 21 12:52:33 PM PDT 24
Finished Mar 21 12:55:43 PM PDT 24
Peak memory 190800 kb
Host smart-73fdce78-4520-427d-911b-91adfa760862
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896095909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3896095909
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1030076338
Short name T342
Test name
Test status
Simulation time 79584476821 ps
CPU time 136.96 seconds
Started Mar 21 12:52:41 PM PDT 24
Finished Mar 21 12:54:58 PM PDT 24
Peak memory 194236 kb
Host smart-87378e84-c502-4609-bea3-eb275e2a2431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030076338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1030076338
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.2170009743
Short name T314
Test name
Test status
Simulation time 33088435384 ps
CPU time 121.69 seconds
Started Mar 21 12:52:40 PM PDT 24
Finished Mar 21 12:54:42 PM PDT 24
Peak memory 182624 kb
Host smart-a7735222-3647-41d4-97f0-e6e368616523
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170009743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.2170009743
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1206684754
Short name T82
Test name
Test status
Simulation time 294598261860 ps
CPU time 269.69 seconds
Started Mar 21 12:52:42 PM PDT 24
Finished Mar 21 12:57:12 PM PDT 24
Peak memory 190848 kb
Host smart-5a2588ad-e40f-4e66-910d-bb581faeae92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206684754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1206684754
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.2224307660
Short name T141
Test name
Test status
Simulation time 85866745958 ps
CPU time 326.82 seconds
Started Mar 21 12:52:51 PM PDT 24
Finished Mar 21 12:58:19 PM PDT 24
Peak memory 190744 kb
Host smart-18fd29d9-9533-47e7-8c4f-46b0de287824
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224307660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2224307660
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3338359836
Short name T328
Test name
Test status
Simulation time 2878217176011 ps
CPU time 1898.58 seconds
Started Mar 21 12:50:27 PM PDT 24
Finished Mar 21 01:22:05 PM PDT 24
Peak memory 190756 kb
Host smart-1bf8317d-2d4f-4600-8a6e-67d52e3d9b20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338359836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3338359836
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/164.rv_timer_random.1383568462
Short name T163
Test name
Test status
Simulation time 222890694688 ps
CPU time 124.78 seconds
Started Mar 21 12:52:54 PM PDT 24
Finished Mar 21 12:54:59 PM PDT 24
Peak memory 192784 kb
Host smart-eafd1978-4dfe-40f3-8464-3466282dba8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383568462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1383568462
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.3085820703
Short name T439
Test name
Test status
Simulation time 392584212859 ps
CPU time 96.55 seconds
Started Mar 21 12:53:01 PM PDT 24
Finished Mar 21 12:54:38 PM PDT 24
Peak memory 190716 kb
Host smart-6931d884-86b2-4181-baa1-2a63ada52f76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085820703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3085820703
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.2952182458
Short name T5
Test name
Test status
Simulation time 491277683037 ps
CPU time 601.81 seconds
Started Mar 21 12:50:29 PM PDT 24
Finished Mar 21 01:00:31 PM PDT 24
Peak memory 190712 kb
Host smart-337cc5a2-034b-48e0-89f1-15e18b5187be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952182458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2952182458
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.2837595367
Short name T271
Test name
Test status
Simulation time 13187674681 ps
CPU time 5.51 seconds
Started Mar 21 12:50:28 PM PDT 24
Finished Mar 21 12:50:33 PM PDT 24
Peak memory 182556 kb
Host smart-8547f31c-294a-493f-8ad4-bfa79396a221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837595367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2837595367
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/171.rv_timer_random.4137248211
Short name T276
Test name
Test status
Simulation time 1003344807340 ps
CPU time 341.84 seconds
Started Mar 21 12:52:58 PM PDT 24
Finished Mar 21 12:58:40 PM PDT 24
Peak memory 190736 kb
Host smart-87aea16e-3665-4823-9cda-b5aec4882327
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137248211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.4137248211
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3471371605
Short name T240
Test name
Test status
Simulation time 862800894830 ps
CPU time 321.37 seconds
Started Mar 21 12:53:03 PM PDT 24
Finished Mar 21 12:58:24 PM PDT 24
Peak memory 190840 kb
Host smart-046ffbb4-b321-41da-84be-2d9d98eb8a9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471371605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3471371605
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.2664100435
Short name T221
Test name
Test status
Simulation time 553246316536 ps
CPU time 558.71 seconds
Started Mar 21 12:53:01 PM PDT 24
Finished Mar 21 01:02:19 PM PDT 24
Peak memory 190784 kb
Host smart-136ded19-6031-4da5-8f8f-f7b3a1fb49b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664100435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2664100435
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1907326721
Short name T159
Test name
Test status
Simulation time 266743754753 ps
CPU time 621.51 seconds
Started Mar 21 12:52:59 PM PDT 24
Finished Mar 21 01:03:21 PM PDT 24
Peak memory 190764 kb
Host smart-5846c4f2-65ad-428b-ac2d-75b4586c92ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907326721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1907326721
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.2998109199
Short name T327
Test name
Test status
Simulation time 57180033812 ps
CPU time 91.3 seconds
Started Mar 21 12:50:27 PM PDT 24
Finished Mar 21 12:51:58 PM PDT 24
Peak memory 190756 kb
Host smart-00d92458-621c-4fe9-9397-41c194cb388a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998109199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2998109199
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.1649111229
Short name T358
Test name
Test status
Simulation time 292837755458 ps
CPU time 174.13 seconds
Started Mar 21 12:52:59 PM PDT 24
Finished Mar 21 12:55:54 PM PDT 24
Peak memory 190776 kb
Host smart-df25cea9-fd13-4004-9d2f-ff91e76b6a2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649111229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1649111229
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.634383481
Short name T86
Test name
Test status
Simulation time 398417279566 ps
CPU time 675.38 seconds
Started Mar 21 12:53:09 PM PDT 24
Finished Mar 21 01:04:25 PM PDT 24
Peak memory 190844 kb
Host smart-2601ba1a-88ef-4b1c-be3d-c481de30690e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634383481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.634383481
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2526381346
Short name T239
Test name
Test status
Simulation time 789698409343 ps
CPU time 685.65 seconds
Started Mar 21 12:50:54 PM PDT 24
Finished Mar 21 01:02:20 PM PDT 24
Peak memory 195172 kb
Host smart-b4473126-704e-474a-aefe-199f2aca0c0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526381346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2526381346
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.2523020637
Short name T230
Test name
Test status
Simulation time 65421523990 ps
CPU time 108.62 seconds
Started Mar 21 12:51:21 PM PDT 24
Finished Mar 21 12:53:10 PM PDT 24
Peak memory 190752 kb
Host smart-8db7b54e-b21e-475a-a2e9-df0b49214203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523020637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2523020637
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/55.rv_timer_random.1594078208
Short name T288
Test name
Test status
Simulation time 31715465219 ps
CPU time 28.41 seconds
Started Mar 21 12:51:50 PM PDT 24
Finished Mar 21 12:52:19 PM PDT 24
Peak memory 182500 kb
Host smart-ebfab92c-4042-47f4-aeff-b0f0749bb02e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594078208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1594078208
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.160998058
Short name T297
Test name
Test status
Simulation time 22143448287 ps
CPU time 38.7 seconds
Started Mar 21 12:51:50 PM PDT 24
Finished Mar 21 12:52:30 PM PDT 24
Peak memory 182488 kb
Host smart-90ae3300-f61e-4be0-a35a-00ee5a0fa78f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160998058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.160998058
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/70.rv_timer_random.3817856359
Short name T252
Test name
Test status
Simulation time 299869049643 ps
CPU time 624.47 seconds
Started Mar 21 12:51:52 PM PDT 24
Finished Mar 21 01:02:17 PM PDT 24
Peak memory 190760 kb
Host smart-144bda37-d02a-4fdf-8f9f-bddabf025fa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817856359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3817856359
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2978558296
Short name T578
Test name
Test status
Simulation time 190422745 ps
CPU time 0.85 seconds
Started Mar 21 12:48:16 PM PDT 24
Finished Mar 21 12:48:17 PM PDT 24
Peak memory 192444 kb
Host smart-10710955-e31b-418c-ae2d-748084c80cd7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978558296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.2978558296
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2296846897
Short name T531
Test name
Test status
Simulation time 201489477 ps
CPU time 2.55 seconds
Started Mar 21 12:48:01 PM PDT 24
Finished Mar 21 12:48:03 PM PDT 24
Peak memory 193796 kb
Host smart-e008fb1f-a7bf-4444-b590-cfea6e0407cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296846897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.2296846897
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2204050141
Short name T484
Test name
Test status
Simulation time 18017652 ps
CPU time 0.66 seconds
Started Mar 21 12:48:09 PM PDT 24
Finished Mar 21 12:48:11 PM PDT 24
Peak memory 193560 kb
Host smart-08823586-1343-4ff3-95c5-8e9897568654
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204050141 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2204050141
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.426179769
Short name T507
Test name
Test status
Simulation time 11769919 ps
CPU time 0.6 seconds
Started Mar 21 12:48:01 PM PDT 24
Finished Mar 21 12:48:03 PM PDT 24
Peak memory 182628 kb
Host smart-17f3178b-8f50-423a-9c01-7607ce50e3d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426179769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.426179769
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1786278570
Short name T466
Test name
Test status
Simulation time 28868475 ps
CPU time 0.62 seconds
Started Mar 21 12:48:02 PM PDT 24
Finished Mar 21 12:48:03 PM PDT 24
Peak memory 182576 kb
Host smart-89fd1098-37fa-4943-85a2-aa2f126d7e41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786278570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1786278570
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1215665118
Short name T112
Test name
Test status
Simulation time 64524125 ps
CPU time 0.83 seconds
Started Mar 21 12:48:09 PM PDT 24
Finished Mar 21 12:48:11 PM PDT 24
Peak memory 191612 kb
Host smart-a8256345-a355-4a16-87a5-d61940726c7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215665118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1215665118
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2395929451
Short name T468
Test name
Test status
Simulation time 54700362 ps
CPU time 1.33 seconds
Started Mar 21 12:48:03 PM PDT 24
Finished Mar 21 12:48:04 PM PDT 24
Peak memory 197396 kb
Host smart-eea0a23c-669a-4ec7-91e2-4d8e8bfeae90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395929451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2395929451
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2259792743
Short name T520
Test name
Test status
Simulation time 1042212984 ps
CPU time 0.92 seconds
Started Mar 21 12:47:59 PM PDT 24
Finished Mar 21 12:48:02 PM PDT 24
Peak memory 193608 kb
Host smart-d0c35d04-d892-485e-9cd1-9cb554774f31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259792743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2259792743
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2890600756
Short name T99
Test name
Test status
Simulation time 120089991 ps
CPU time 0.72 seconds
Started Mar 21 12:48:16 PM PDT 24
Finished Mar 21 12:48:17 PM PDT 24
Peak memory 182588 kb
Host smart-a638ca10-6438-45a9-825c-4ac4660bd74f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890600756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.2890600756
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.4076687806
Short name T95
Test name
Test status
Simulation time 74507956 ps
CPU time 2.32 seconds
Started Mar 21 12:48:09 PM PDT 24
Finished Mar 21 12:48:12 PM PDT 24
Peak memory 193704 kb
Host smart-6f3bc357-b7fe-470b-918d-db4a69cf6dcf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076687806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.4076687806
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.761798801
Short name T555
Test name
Test status
Simulation time 46235675 ps
CPU time 0.55 seconds
Started Mar 21 12:48:08 PM PDT 24
Finished Mar 21 12:48:10 PM PDT 24
Peak memory 182612 kb
Host smart-668db205-7dd9-4e3f-9e8b-568157bbdff8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761798801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re
set.761798801
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3974280887
Short name T55
Test name
Test status
Simulation time 98836088 ps
CPU time 0.83 seconds
Started Mar 21 12:48:18 PM PDT 24
Finished Mar 21 12:48:19 PM PDT 24
Peak memory 195676 kb
Host smart-e488eb91-c58f-47ff-ad25-23276ee6b1f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974280887 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3974280887
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.870770765
Short name T101
Test name
Test status
Simulation time 16498925 ps
CPU time 0.58 seconds
Started Mar 21 12:48:10 PM PDT 24
Finished Mar 21 12:48:11 PM PDT 24
Peak memory 182624 kb
Host smart-00c76677-0da6-47f6-864d-f635349d18fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870770765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.870770765
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.448854175
Short name T551
Test name
Test status
Simulation time 13817491 ps
CPU time 0.56 seconds
Started Mar 21 12:48:13 PM PDT 24
Finished Mar 21 12:48:14 PM PDT 24
Peak memory 182464 kb
Host smart-134fe79f-396b-4c71-b52d-63842e9e42ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448854175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.448854175
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.158958254
Short name T96
Test name
Test status
Simulation time 70123272 ps
CPU time 0.7 seconds
Started Mar 21 12:48:06 PM PDT 24
Finished Mar 21 12:48:08 PM PDT 24
Peak memory 193164 kb
Host smart-202ba416-ecdf-45d5-bc3f-e0027bce05ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158958254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_tim
er_same_csr_outstanding.158958254
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.4170220340
Short name T550
Test name
Test status
Simulation time 175450580 ps
CPU time 3.54 seconds
Started Mar 21 12:48:10 PM PDT 24
Finished Mar 21 12:48:14 PM PDT 24
Peak memory 197452 kb
Host smart-0ca5ebee-a618-4de9-860d-7ad0c20c0bad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170220340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.4170220340
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2796082063
Short name T57
Test name
Test status
Simulation time 117704923 ps
CPU time 1.34 seconds
Started Mar 21 12:48:08 PM PDT 24
Finished Mar 21 12:48:11 PM PDT 24
Peak memory 195408 kb
Host smart-f5e18111-9e44-4721-bc39-95308c2bc861
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796082063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.2796082063
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2433908034
Short name T549
Test name
Test status
Simulation time 27681630 ps
CPU time 0.73 seconds
Started Mar 21 12:48:45 PM PDT 24
Finished Mar 21 12:48:49 PM PDT 24
Peak memory 195412 kb
Host smart-e7ae9bd6-6ee7-498f-b6ef-bf73c16b3e60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433908034 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2433908034
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.936058342
Short name T107
Test name
Test status
Simulation time 15493848 ps
CPU time 0.55 seconds
Started Mar 21 12:48:44 PM PDT 24
Finished Mar 21 12:48:49 PM PDT 24
Peak memory 182624 kb
Host smart-41b9392e-db36-484c-8d74-1a279e1bd645
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936058342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.936058342
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1015455854
Short name T511
Test name
Test status
Simulation time 122787666 ps
CPU time 0.53 seconds
Started Mar 21 12:48:45 PM PDT 24
Finished Mar 21 12:48:49 PM PDT 24
Peak memory 182400 kb
Host smart-e9c429f9-6ff4-41b2-8db1-ef4b23f3e172
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015455854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1015455854
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3433377894
Short name T557
Test name
Test status
Simulation time 32544348 ps
CPU time 0.76 seconds
Started Mar 21 12:48:46 PM PDT 24
Finished Mar 21 12:48:51 PM PDT 24
Peak memory 191728 kb
Host smart-c75891b6-7ab7-48ad-882c-a1f2031eb897
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433377894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3433377894
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2528724526
Short name T564
Test name
Test status
Simulation time 159583605 ps
CPU time 1.95 seconds
Started Mar 21 12:48:46 PM PDT 24
Finished Mar 21 12:48:51 PM PDT 24
Peak memory 197476 kb
Host smart-02a37751-9006-458f-860d-02329f43c76f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528724526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.2528724526
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2234954078
Short name T70
Test name
Test status
Simulation time 174422567 ps
CPU time 1.1 seconds
Started Mar 21 12:48:44 PM PDT 24
Finished Mar 21 12:48:48 PM PDT 24
Peak memory 195156 kb
Host smart-b9dd61a1-ede0-4ff3-9f9f-6c793a236eb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234954078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.2234954078
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1659580813
Short name T480
Test name
Test status
Simulation time 109216680 ps
CPU time 0.73 seconds
Started Mar 21 12:48:47 PM PDT 24
Finished Mar 21 12:48:51 PM PDT 24
Peak memory 194992 kb
Host smart-1b656dba-e117-44a3-8c80-fc1f53d3466c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659580813 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1659580813
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.226559295
Short name T100
Test name
Test status
Simulation time 13673139 ps
CPU time 0.55 seconds
Started Mar 21 12:48:44 PM PDT 24
Finished Mar 21 12:48:48 PM PDT 24
Peak memory 182620 kb
Host smart-32eae3cc-8517-49ea-8f46-c7d16897fe8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226559295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.226559295
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2198666848
Short name T485
Test name
Test status
Simulation time 89090614 ps
CPU time 0.52 seconds
Started Mar 21 12:48:47 PM PDT 24
Finished Mar 21 12:48:51 PM PDT 24
Peak memory 182100 kb
Host smart-82274153-3c67-4e6b-992f-8eaaa990c28b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198666848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2198666848
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2640309178
Short name T505
Test name
Test status
Simulation time 126930561 ps
CPU time 0.83 seconds
Started Mar 21 12:48:44 PM PDT 24
Finished Mar 21 12:48:48 PM PDT 24
Peak memory 193280 kb
Host smart-0cef6220-f29c-4d61-9a60-7d70fb30d90f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640309178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2640309178
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1631471714
Short name T459
Test name
Test status
Simulation time 25287772 ps
CPU time 1.04 seconds
Started Mar 21 12:48:45 PM PDT 24
Finished Mar 21 12:48:50 PM PDT 24
Peak memory 197292 kb
Host smart-3fafba9d-9d89-4944-bc70-5c70f27e997e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631471714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1631471714
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3114784580
Short name T498
Test name
Test status
Simulation time 297100853 ps
CPU time 1.06 seconds
Started Mar 21 12:48:44 PM PDT 24
Finished Mar 21 12:48:48 PM PDT 24
Peak memory 183164 kb
Host smart-e7394cf5-0016-4c7a-bbf2-d18a2d3bf891
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114784580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3114784580
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3431739496
Short name T488
Test name
Test status
Simulation time 23249037 ps
CPU time 0.71 seconds
Started Mar 21 12:48:44 PM PDT 24
Finished Mar 21 12:48:45 PM PDT 24
Peak memory 195576 kb
Host smart-c24e2f13-35b3-46ec-8c49-0db2de526a2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431739496 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3431739496
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.3349175929
Short name T532
Test name
Test status
Simulation time 29591737 ps
CPU time 0.62 seconds
Started Mar 21 12:48:47 PM PDT 24
Finished Mar 21 12:48:51 PM PDT 24
Peak memory 182592 kb
Host smart-8cb10efb-a9b4-4b9d-8474-285bd39e15db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349175929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.3349175929
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.4249857410
Short name T571
Test name
Test status
Simulation time 44263988 ps
CPU time 0.53 seconds
Started Mar 21 12:48:43 PM PDT 24
Finished Mar 21 12:48:46 PM PDT 24
Peak memory 182532 kb
Host smart-2e1ac4f8-c94e-45b3-899d-a7569f8ea37c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249857410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.4249857410
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1395501898
Short name T524
Test name
Test status
Simulation time 161422069 ps
CPU time 0.71 seconds
Started Mar 21 12:48:44 PM PDT 24
Finished Mar 21 12:48:48 PM PDT 24
Peak memory 191660 kb
Host smart-e338becc-8995-4627-a355-6f44057f967c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395501898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1395501898
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2356932469
Short name T476
Test name
Test status
Simulation time 41334436 ps
CPU time 1.35 seconds
Started Mar 21 12:48:45 PM PDT 24
Finished Mar 21 12:48:50 PM PDT 24
Peak memory 197360 kb
Host smart-23d0e075-172f-492f-b8c7-76a58806fcdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356932469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2356932469
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.334836130
Short name T552
Test name
Test status
Simulation time 445350361 ps
CPU time 1.31 seconds
Started Mar 21 12:48:43 PM PDT 24
Finished Mar 21 12:48:46 PM PDT 24
Peak memory 194948 kb
Host smart-2d433f26-2119-4ce2-a172-cd2f6682abce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334836130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_in
tg_err.334836130
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1193183870
Short name T501
Test name
Test status
Simulation time 32461101 ps
CPU time 0.92 seconds
Started Mar 21 12:48:54 PM PDT 24
Finished Mar 21 12:48:55 PM PDT 24
Peak memory 197448 kb
Host smart-b8fd9e1b-b7a4-4754-98a1-b506779e747d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193183870 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.1193183870
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2585961707
Short name T102
Test name
Test status
Simulation time 39554797 ps
CPU time 0.63 seconds
Started Mar 21 12:48:46 PM PDT 24
Finished Mar 21 12:48:50 PM PDT 24
Peak memory 182748 kb
Host smart-df3b99ca-9441-4c84-8368-47b595ef4f07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585961707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2585961707
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2910013309
Short name T479
Test name
Test status
Simulation time 24825343 ps
CPU time 0.53 seconds
Started Mar 21 12:48:44 PM PDT 24
Finished Mar 21 12:48:48 PM PDT 24
Peak memory 182572 kb
Host smart-b468fc1e-5e44-45f7-b489-33866192781c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910013309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2910013309
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3716006689
Short name T510
Test name
Test status
Simulation time 24565998 ps
CPU time 0.63 seconds
Started Mar 21 12:48:51 PM PDT 24
Finished Mar 21 12:48:53 PM PDT 24
Peak memory 191472 kb
Host smart-4666832a-8d40-4bd1-be99-e7e927310bb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716006689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.3716006689
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3036828645
Short name T523
Test name
Test status
Simulation time 417478879 ps
CPU time 2.34 seconds
Started Mar 21 12:48:46 PM PDT 24
Finished Mar 21 12:48:52 PM PDT 24
Peak memory 197600 kb
Host smart-47cd1ef1-0414-4f4c-b4de-c35e50640edc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036828645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3036828645
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.556499372
Short name T573
Test name
Test status
Simulation time 262552722 ps
CPU time 1.24 seconds
Started Mar 21 12:48:43 PM PDT 24
Finished Mar 21 12:48:47 PM PDT 24
Peak memory 183348 kb
Host smart-e4e15c00-42ab-4eab-974f-4e3b61b3d48a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556499372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_in
tg_err.556499372
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.883191061
Short name T509
Test name
Test status
Simulation time 29745105 ps
CPU time 0.82 seconds
Started Mar 21 12:48:55 PM PDT 24
Finished Mar 21 12:48:55 PM PDT 24
Peak memory 195776 kb
Host smart-55788259-3a08-4dee-87af-9518df84be6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883191061 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.883191061
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.383027709
Short name T98
Test name
Test status
Simulation time 11600561 ps
CPU time 0.51 seconds
Started Mar 21 12:49:09 PM PDT 24
Finished Mar 21 12:49:10 PM PDT 24
Peak memory 182352 kb
Host smart-4f086ae5-059e-4d6f-97fa-5d241a7c58ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383027709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.383027709
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.698980012
Short name T493
Test name
Test status
Simulation time 38218304 ps
CPU time 0.54 seconds
Started Mar 21 12:48:53 PM PDT 24
Finished Mar 21 12:48:54 PM PDT 24
Peak memory 182452 kb
Host smart-29688a1a-0e41-4802-82eb-c19f5425fd72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698980012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.698980012
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2312617418
Short name T111
Test name
Test status
Simulation time 20846701 ps
CPU time 0.6 seconds
Started Mar 21 12:48:50 PM PDT 24
Finished Mar 21 12:48:53 PM PDT 24
Peak memory 191992 kb
Host smart-687221fe-85e5-4711-80e1-6f19d9e5f775
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312617418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.2312617418
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2695409284
Short name T541
Test name
Test status
Simulation time 194195812 ps
CPU time 1.07 seconds
Started Mar 21 12:48:53 PM PDT 24
Finished Mar 21 12:48:55 PM PDT 24
Peak memory 196796 kb
Host smart-f61449ee-4765-4532-9867-b149be12d604
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695409284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2695409284
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3413463814
Short name T540
Test name
Test status
Simulation time 105926261 ps
CPU time 1.32 seconds
Started Mar 21 12:48:51 PM PDT 24
Finished Mar 21 12:48:53 PM PDT 24
Peak memory 195276 kb
Host smart-be054470-2d66-46bd-9004-bf93d9d3b3d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413463814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.3413463814
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3636443087
Short name T495
Test name
Test status
Simulation time 71608590 ps
CPU time 0.62 seconds
Started Mar 21 12:48:54 PM PDT 24
Finished Mar 21 12:48:55 PM PDT 24
Peak memory 194108 kb
Host smart-e50945ab-ebe3-45fb-aac8-0b1d57359b0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636443087 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3636443087
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.4256358345
Short name T530
Test name
Test status
Simulation time 13074817 ps
CPU time 0.58 seconds
Started Mar 21 12:48:53 PM PDT 24
Finished Mar 21 12:48:54 PM PDT 24
Peak memory 182656 kb
Host smart-edea7a54-7196-480f-b2ec-9cae09fe28dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256358345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.4256358345
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2232490334
Short name T538
Test name
Test status
Simulation time 11982958 ps
CPU time 0.53 seconds
Started Mar 21 12:48:51 PM PDT 24
Finished Mar 21 12:48:53 PM PDT 24
Peak memory 182180 kb
Host smart-0a1fbc92-ec28-44ce-82fd-2fb131e8981a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232490334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2232490334
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3748122852
Short name T512
Test name
Test status
Simulation time 58654908 ps
CPU time 0.64 seconds
Started Mar 21 12:48:57 PM PDT 24
Finished Mar 21 12:48:58 PM PDT 24
Peak memory 191752 kb
Host smart-9b352040-7b6b-4229-98b7-d2ee1aca4b65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748122852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3748122852
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.4181953259
Short name T522
Test name
Test status
Simulation time 266058648 ps
CPU time 1.58 seconds
Started Mar 21 12:48:53 PM PDT 24
Finished Mar 21 12:48:55 PM PDT 24
Peak memory 197500 kb
Host smart-168cb49b-181c-4863-9cdb-b0e035a1c070
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181953259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.4181953259
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.4227353962
Short name T542
Test name
Test status
Simulation time 1348498553 ps
CPU time 1.43 seconds
Started Mar 21 12:48:53 PM PDT 24
Finished Mar 21 12:48:55 PM PDT 24
Peak memory 195072 kb
Host smart-5b181cc7-94c4-4403-a0b3-4c1a143972c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227353962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.4227353962
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1039558008
Short name T489
Test name
Test status
Simulation time 21397419 ps
CPU time 0.71 seconds
Started Mar 21 12:48:52 PM PDT 24
Finished Mar 21 12:48:53 PM PDT 24
Peak memory 195348 kb
Host smart-e054212e-c3a4-4bfc-922e-63ad1f7ffcaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039558008 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.1039558008
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.238549933
Short name T106
Test name
Test status
Simulation time 13073106 ps
CPU time 0.54 seconds
Started Mar 21 12:48:53 PM PDT 24
Finished Mar 21 12:48:54 PM PDT 24
Peak memory 182616 kb
Host smart-741d87a0-a2b4-408d-a52a-79fb06dfa3f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238549933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.238549933
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2844947574
Short name T514
Test name
Test status
Simulation time 49145611 ps
CPU time 0.52 seconds
Started Mar 21 12:48:52 PM PDT 24
Finished Mar 21 12:48:53 PM PDT 24
Peak memory 182516 kb
Host smart-34902ea7-61a0-41c5-969a-aabfd5510513
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844947574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2844947574
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1991521873
Short name T545
Test name
Test status
Simulation time 45040867 ps
CPU time 0.69 seconds
Started Mar 21 12:48:54 PM PDT 24
Finished Mar 21 12:48:55 PM PDT 24
Peak memory 192912 kb
Host smart-cdd787e7-05fe-43a7-97f1-8c6a941b0fb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991521873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1991521873
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2653951303
Short name T502
Test name
Test status
Simulation time 122510588 ps
CPU time 3.07 seconds
Started Mar 21 12:48:55 PM PDT 24
Finished Mar 21 12:48:58 PM PDT 24
Peak memory 197548 kb
Host smart-ca79e24d-205a-4713-b4cf-7fa46a34c5c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653951303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2653951303
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1611694566
Short name T482
Test name
Test status
Simulation time 47738608 ps
CPU time 0.8 seconds
Started Mar 21 12:48:55 PM PDT 24
Finished Mar 21 12:48:56 PM PDT 24
Peak memory 193696 kb
Host smart-ee05dc06-3dcc-40f7-b7b7-57a7e5b3a10b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611694566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.1611694566
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.453309576
Short name T467
Test name
Test status
Simulation time 22557940 ps
CPU time 0.95 seconds
Started Mar 21 12:49:02 PM PDT 24
Finished Mar 21 12:49:03 PM PDT 24
Peak memory 197320 kb
Host smart-44bd2ecb-47bd-4725-b776-40830ff182fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453309576 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.453309576
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2375143458
Short name T457
Test name
Test status
Simulation time 14318675 ps
CPU time 0.54 seconds
Started Mar 21 12:48:53 PM PDT 24
Finished Mar 21 12:48:54 PM PDT 24
Peak memory 182500 kb
Host smart-2b564d89-a39d-4cdd-aabd-4425605aa359
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375143458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2375143458
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2468195847
Short name T569
Test name
Test status
Simulation time 15806887 ps
CPU time 0.52 seconds
Started Mar 21 12:48:53 PM PDT 24
Finished Mar 21 12:48:54 PM PDT 24
Peak memory 181988 kb
Host smart-7d7f0a34-57f5-4eb4-8bfd-e46e5969a4ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468195847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.2468195847
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1667458246
Short name T515
Test name
Test status
Simulation time 101071170 ps
CPU time 0.67 seconds
Started Mar 21 12:48:53 PM PDT 24
Finished Mar 21 12:48:53 PM PDT 24
Peak memory 192192 kb
Host smart-75b1e858-cd84-42aa-ac1e-5db6b64e0ea6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667458246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.1667458246
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.629319384
Short name T508
Test name
Test status
Simulation time 104264883 ps
CPU time 1.87 seconds
Started Mar 21 12:48:55 PM PDT 24
Finished Mar 21 12:48:57 PM PDT 24
Peak memory 197532 kb
Host smart-9ab3328d-b3cb-4824-b968-3d3cb135a0d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629319384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.629319384
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2728481855
Short name T483
Test name
Test status
Simulation time 463066311 ps
CPU time 1.42 seconds
Started Mar 21 12:48:53 PM PDT 24
Finished Mar 21 12:48:55 PM PDT 24
Peak memory 194340 kb
Host smart-65a674de-232a-4725-a6be-28f013f1390a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728481855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2728481855
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2552388804
Short name T462
Test name
Test status
Simulation time 22975338 ps
CPU time 0.74 seconds
Started Mar 21 12:49:02 PM PDT 24
Finished Mar 21 12:49:03 PM PDT 24
Peak memory 195076 kb
Host smart-c9cb18f2-ab3c-44c6-ab03-f582de1f5cfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552388804 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.2552388804
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.881403719
Short name T470
Test name
Test status
Simulation time 33517842 ps
CPU time 0.59 seconds
Started Mar 21 12:49:05 PM PDT 24
Finished Mar 21 12:49:06 PM PDT 24
Peak memory 182696 kb
Host smart-425de96b-5c55-4dcc-bd12-0e4f87da8f38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881403719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.881403719
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.381877172
Short name T461
Test name
Test status
Simulation time 58231961 ps
CPU time 0.55 seconds
Started Mar 21 12:49:02 PM PDT 24
Finished Mar 21 12:49:02 PM PDT 24
Peak memory 182660 kb
Host smart-2e0cf8f1-2007-4023-91ca-bc6032786f22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381877172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.381877172
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1881343389
Short name T487
Test name
Test status
Simulation time 20189000 ps
CPU time 0.63 seconds
Started Mar 21 12:49:04 PM PDT 24
Finished Mar 21 12:49:05 PM PDT 24
Peak memory 191452 kb
Host smart-07379228-e867-4941-8523-480987a8f6e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881343389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1881343389
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2882121256
Short name T500
Test name
Test status
Simulation time 766712835 ps
CPU time 2.54 seconds
Started Mar 21 12:49:03 PM PDT 24
Finished Mar 21 12:49:06 PM PDT 24
Peak memory 197524 kb
Host smart-ef66b189-bc3f-49ed-bbfc-0c94db224525
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882121256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2882121256
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1261081556
Short name T558
Test name
Test status
Simulation time 42801698 ps
CPU time 0.79 seconds
Started Mar 21 12:49:04 PM PDT 24
Finished Mar 21 12:49:05 PM PDT 24
Peak memory 193556 kb
Host smart-d98de4c1-d45e-4bd4-bf9f-e92044210425
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261081556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1261081556
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.4099291076
Short name T559
Test name
Test status
Simulation time 54672968 ps
CPU time 0.69 seconds
Started Mar 21 12:49:04 PM PDT 24
Finished Mar 21 12:49:04 PM PDT 24
Peak memory 193376 kb
Host smart-27ee4673-291f-44bd-8832-5249a0025fe6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099291076 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.4099291076
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.918628936
Short name T527
Test name
Test status
Simulation time 31155086 ps
CPU time 0.55 seconds
Started Mar 21 12:49:05 PM PDT 24
Finished Mar 21 12:49:05 PM PDT 24
Peak memory 182572 kb
Host smart-a753b981-0b18-44af-bf8c-4971ba8d10a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918628936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.918628936
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3015288839
Short name T526
Test name
Test status
Simulation time 19754561 ps
CPU time 0.67 seconds
Started Mar 21 12:49:04 PM PDT 24
Finished Mar 21 12:49:05 PM PDT 24
Peak memory 191724 kb
Host smart-49c31078-eb08-4a7d-b00c-21f9cbb7512b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015288839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3015288839
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.324820810
Short name T539
Test name
Test status
Simulation time 165433901 ps
CPU time 1.94 seconds
Started Mar 21 12:49:03 PM PDT 24
Finished Mar 21 12:49:05 PM PDT 24
Peak memory 197532 kb
Host smart-92286818-b59f-49db-9981-cd051d0cc47e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324820810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.324820810
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.901667115
Short name T56
Test name
Test status
Simulation time 2810922224 ps
CPU time 1.99 seconds
Started Mar 21 12:49:03 PM PDT 24
Finished Mar 21 12:49:05 PM PDT 24
Peak memory 183436 kb
Host smart-530c5f67-fdec-42b3-aa2a-8c1f17c51e7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901667115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_in
tg_err.901667115
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1845626475
Short name T93
Test name
Test status
Simulation time 162669049 ps
CPU time 0.81 seconds
Started Mar 21 12:48:17 PM PDT 24
Finished Mar 21 12:48:18 PM PDT 24
Peak memory 192528 kb
Host smart-d7abb04f-5d08-4327-9cd5-27e24b7673b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845626475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1845626475
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3496209393
Short name T104
Test name
Test status
Simulation time 948618072 ps
CPU time 3.05 seconds
Started Mar 21 12:48:16 PM PDT 24
Finished Mar 21 12:48:19 PM PDT 24
Peak memory 192700 kb
Host smart-47fb6d24-c086-414a-829d-83f647b2a162
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496209393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.3496209393
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.4197925299
Short name T103
Test name
Test status
Simulation time 28858712 ps
CPU time 0.58 seconds
Started Mar 21 12:48:15 PM PDT 24
Finished Mar 21 12:48:16 PM PDT 24
Peak memory 182796 kb
Host smart-fce7ab9b-bb63-4a81-b22d-cdcbfa3e1c37
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197925299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.4197925299
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3870280633
Short name T518
Test name
Test status
Simulation time 60042450 ps
CPU time 0.65 seconds
Started Mar 21 12:48:21 PM PDT 24
Finished Mar 21 12:48:22 PM PDT 24
Peak memory 193752 kb
Host smart-60e11ede-3a37-4fe1-b8b0-f69f369dd6ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870280633 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3870280633
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.504283567
Short name T478
Test name
Test status
Simulation time 14086442 ps
CPU time 0.56 seconds
Started Mar 21 12:48:17 PM PDT 24
Finished Mar 21 12:48:18 PM PDT 24
Peak memory 182708 kb
Host smart-8758f6d4-ceae-417a-af3e-d3ddac3f0e15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504283567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.504283567
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2699559719
Short name T496
Test name
Test status
Simulation time 14446667 ps
CPU time 0.53 seconds
Started Mar 21 12:48:14 PM PDT 24
Finished Mar 21 12:48:15 PM PDT 24
Peak memory 182492 kb
Host smart-c8ffeb30-839d-45fd-9903-c47c470df32c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699559719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2699559719
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.185155455
Short name T91
Test name
Test status
Simulation time 32846182 ps
CPU time 0.67 seconds
Started Mar 21 12:48:15 PM PDT 24
Finished Mar 21 12:48:16 PM PDT 24
Peak memory 191964 kb
Host smart-a308515b-b40a-4bbf-bb5a-287a37e19d35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185155455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_tim
er_same_csr_outstanding.185155455
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1525688531
Short name T572
Test name
Test status
Simulation time 163851007 ps
CPU time 2.04 seconds
Started Mar 21 12:48:15 PM PDT 24
Finished Mar 21 12:48:17 PM PDT 24
Peak memory 197520 kb
Host smart-2850d14c-9b19-4bf4-bf01-e6a3536911a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525688531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1525688531
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3312315688
Short name T579
Test name
Test status
Simulation time 16142569 ps
CPU time 0.56 seconds
Started Mar 21 12:49:05 PM PDT 24
Finished Mar 21 12:49:05 PM PDT 24
Peak memory 182572 kb
Host smart-089e6802-908d-4ba8-bf37-3789b4de82d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312315688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3312315688
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2971997017
Short name T553
Test name
Test status
Simulation time 11624636 ps
CPU time 0.52 seconds
Started Mar 21 12:49:04 PM PDT 24
Finished Mar 21 12:49:05 PM PDT 24
Peak memory 182616 kb
Host smart-5b6bde59-034c-4d42-842f-287c2224ca65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971997017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.2971997017
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.4154015322
Short name T563
Test name
Test status
Simulation time 13095381 ps
CPU time 0.53 seconds
Started Mar 21 12:49:04 PM PDT 24
Finished Mar 21 12:49:05 PM PDT 24
Peak memory 182552 kb
Host smart-ff2b9915-a65a-4625-95ad-5f1bf53be5f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154015322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.4154015322
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2028099839
Short name T536
Test name
Test status
Simulation time 29055343 ps
CPU time 0.63 seconds
Started Mar 21 12:49:02 PM PDT 24
Finished Mar 21 12:49:03 PM PDT 24
Peak memory 182584 kb
Host smart-e81dde9c-3e75-4730-95b3-b0975c9ffa0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028099839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2028099839
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3262141527
Short name T517
Test name
Test status
Simulation time 14081268 ps
CPU time 0.53 seconds
Started Mar 21 12:49:04 PM PDT 24
Finished Mar 21 12:49:05 PM PDT 24
Peak memory 182144 kb
Host smart-bbe7e1ee-be15-47bf-9389-b94952ca2449
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262141527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3262141527
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.4201849697
Short name T463
Test name
Test status
Simulation time 24262454 ps
CPU time 0.59 seconds
Started Mar 21 12:49:02 PM PDT 24
Finished Mar 21 12:49:02 PM PDT 24
Peak memory 182612 kb
Host smart-2e3a6207-52fb-4519-b040-53aeedcae081
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201849697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.4201849697
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1161454688
Short name T566
Test name
Test status
Simulation time 141595079 ps
CPU time 0.56 seconds
Started Mar 21 12:49:04 PM PDT 24
Finished Mar 21 12:49:04 PM PDT 24
Peak memory 182612 kb
Host smart-64ce31ac-3d3b-41a4-a091-c8e496bcd869
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161454688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1161454688
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.312933865
Short name T547
Test name
Test status
Simulation time 14642975 ps
CPU time 0.56 seconds
Started Mar 21 12:49:04 PM PDT 24
Finished Mar 21 12:49:05 PM PDT 24
Peak memory 182668 kb
Host smart-96b3c251-4135-4a9b-8818-8259cdcb9802
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312933865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.312933865
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.825874276
Short name T575
Test name
Test status
Simulation time 101255101 ps
CPU time 0.55 seconds
Started Mar 21 12:49:15 PM PDT 24
Finished Mar 21 12:49:15 PM PDT 24
Peak memory 182468 kb
Host smart-e89006ad-0740-43bf-a657-ccd732eec69e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825874276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.825874276
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3266392274
Short name T568
Test name
Test status
Simulation time 25381536 ps
CPU time 0.53 seconds
Started Mar 21 12:49:03 PM PDT 24
Finished Mar 21 12:49:04 PM PDT 24
Peak memory 182060 kb
Host smart-cfceaf48-2ad9-46e7-ac27-03542aad97f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266392274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3266392274
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3963867532
Short name T105
Test name
Test status
Simulation time 26735049 ps
CPU time 0.78 seconds
Started Mar 21 12:48:15 PM PDT 24
Finished Mar 21 12:48:16 PM PDT 24
Peak memory 192420 kb
Host smart-c7acde26-ebd7-4b8f-a23a-0f2c276103e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963867532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3963867532
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2152124093
Short name T543
Test name
Test status
Simulation time 843564295 ps
CPU time 2.63 seconds
Started Mar 21 12:48:15 PM PDT 24
Finished Mar 21 12:48:18 PM PDT 24
Peak memory 191036 kb
Host smart-69d7ca80-d916-4ff4-9990-2ccd2b4fc0b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152124093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2152124093
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3648804897
Short name T570
Test name
Test status
Simulation time 38048925 ps
CPU time 0.55 seconds
Started Mar 21 12:48:17 PM PDT 24
Finished Mar 21 12:48:18 PM PDT 24
Peak memory 182644 kb
Host smart-d00635e3-ef98-4733-8003-23bc51158704
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648804897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3648804897
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1183756356
Short name T546
Test name
Test status
Simulation time 160629764 ps
CPU time 1.04 seconds
Started Mar 21 12:48:21 PM PDT 24
Finished Mar 21 12:48:23 PM PDT 24
Peak memory 197276 kb
Host smart-d9ce6862-0d94-4438-8a6b-2b7d8335e76e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183756356 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1183756356
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1135333502
Short name T534
Test name
Test status
Simulation time 63456270 ps
CPU time 0.55 seconds
Started Mar 21 12:48:16 PM PDT 24
Finished Mar 21 12:48:17 PM PDT 24
Peak memory 182632 kb
Host smart-84ac63ec-df9b-4020-bcb8-831a060c7318
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135333502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1135333502
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.4152783271
Short name T535
Test name
Test status
Simulation time 14426669 ps
CPU time 0.56 seconds
Started Mar 21 12:48:16 PM PDT 24
Finished Mar 21 12:48:17 PM PDT 24
Peak memory 182440 kb
Host smart-dea009e2-471f-4958-baf9-970ba8309683
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152783271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.4152783271
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2093596617
Short name T561
Test name
Test status
Simulation time 102900282 ps
CPU time 0.8 seconds
Started Mar 21 12:48:17 PM PDT 24
Finished Mar 21 12:48:18 PM PDT 24
Peak memory 193444 kb
Host smart-e48ab93e-07b0-4b69-ba80-3c1de64ca580
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093596617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.2093596617
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2160518316
Short name T53
Test name
Test status
Simulation time 82574244 ps
CPU time 1.56 seconds
Started Mar 21 12:48:17 PM PDT 24
Finished Mar 21 12:48:18 PM PDT 24
Peak memory 197524 kb
Host smart-7348f383-015f-4be0-b156-8600cef1f788
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160518316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2160518316
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1851892534
Short name T31
Test name
Test status
Simulation time 87724535 ps
CPU time 0.79 seconds
Started Mar 21 12:48:16 PM PDT 24
Finished Mar 21 12:48:18 PM PDT 24
Peak memory 183048 kb
Host smart-a00a1b7e-d91b-4a4e-a00e-f5f5bd3af352
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851892534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.1851892534
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3574417809
Short name T456
Test name
Test status
Simulation time 47701774 ps
CPU time 0.56 seconds
Started Mar 21 12:49:14 PM PDT 24
Finished Mar 21 12:49:15 PM PDT 24
Peak memory 182572 kb
Host smart-becb1d51-cbd3-40d6-b5ef-87577171e843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574417809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3574417809
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.435119252
Short name T473
Test name
Test status
Simulation time 16568083 ps
CPU time 0.58 seconds
Started Mar 21 12:49:15 PM PDT 24
Finished Mar 21 12:49:16 PM PDT 24
Peak memory 182564 kb
Host smart-9f29ade6-43b8-46f1-a36c-ca0ec19c42d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435119252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.435119252
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3985619830
Short name T497
Test name
Test status
Simulation time 41077617 ps
CPU time 0.58 seconds
Started Mar 21 12:49:16 PM PDT 24
Finished Mar 21 12:49:17 PM PDT 24
Peak memory 182564 kb
Host smart-f6887d1f-71fa-471b-9a96-27328bdba933
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985619830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.3985619830
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2460831520
Short name T521
Test name
Test status
Simulation time 82405861 ps
CPU time 0.57 seconds
Started Mar 21 12:49:14 PM PDT 24
Finished Mar 21 12:49:15 PM PDT 24
Peak memory 182720 kb
Host smart-a8814e51-3ea2-48ac-8721-57ddb8f92983
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460831520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.2460831520
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1253304817
Short name T465
Test name
Test status
Simulation time 15992091 ps
CPU time 0.54 seconds
Started Mar 21 12:49:15 PM PDT 24
Finished Mar 21 12:49:15 PM PDT 24
Peak memory 182148 kb
Host smart-5e8e1ade-996d-417c-a996-b13b75c36a35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253304817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.1253304817
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2622241040
Short name T469
Test name
Test status
Simulation time 33675205 ps
CPU time 0.51 seconds
Started Mar 21 12:49:16 PM PDT 24
Finished Mar 21 12:49:16 PM PDT 24
Peak memory 182200 kb
Host smart-15225309-5150-4c33-9f5b-4e6bf9cc5211
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622241040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2622241040
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.4254765137
Short name T474
Test name
Test status
Simulation time 10676708 ps
CPU time 0.54 seconds
Started Mar 21 12:49:16 PM PDT 24
Finished Mar 21 12:49:17 PM PDT 24
Peak memory 182428 kb
Host smart-1ecb3ee1-61b5-4dec-8eba-11932e9b26c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254765137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.4254765137
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.865070277
Short name T504
Test name
Test status
Simulation time 29527872 ps
CPU time 0.54 seconds
Started Mar 21 12:49:14 PM PDT 24
Finished Mar 21 12:49:15 PM PDT 24
Peak memory 181980 kb
Host smart-ae6daa57-dc58-4cdc-967c-de9e4e1c5fba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865070277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.865070277
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.620566203
Short name T560
Test name
Test status
Simulation time 14786719 ps
CPU time 0.54 seconds
Started Mar 21 12:49:16 PM PDT 24
Finished Mar 21 12:49:17 PM PDT 24
Peak memory 181944 kb
Host smart-3e589672-c214-4197-8d1b-af208253aeb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620566203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.620566203
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.4072721729
Short name T562
Test name
Test status
Simulation time 22531787 ps
CPU time 0.52 seconds
Started Mar 21 12:49:14 PM PDT 24
Finished Mar 21 12:49:15 PM PDT 24
Peak memory 181972 kb
Host smart-fe803431-4edf-4d35-9557-bb127752bd02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072721729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.4072721729
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1736048465
Short name T109
Test name
Test status
Simulation time 52956527 ps
CPU time 0.71 seconds
Started Mar 21 12:48:27 PM PDT 24
Finished Mar 21 12:48:28 PM PDT 24
Peak memory 192416 kb
Host smart-f65ce987-8272-420f-841d-97b129267940
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736048465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1736048465
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1214182482
Short name T58
Test name
Test status
Simulation time 128413716 ps
CPU time 1.61 seconds
Started Mar 21 12:48:26 PM PDT 24
Finished Mar 21 12:48:28 PM PDT 24
Peak memory 193412 kb
Host smart-c9bc902b-6431-4d75-a2a0-4bffc76c6bcb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214182482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.1214182482
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2037780063
Short name T576
Test name
Test status
Simulation time 12920932 ps
CPU time 0.56 seconds
Started Mar 21 12:48:27 PM PDT 24
Finished Mar 21 12:48:28 PM PDT 24
Peak memory 182272 kb
Host smart-b9bb3c37-7fa1-45ad-8be7-249d6f2b937f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037780063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2037780063
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.41592405
Short name T516
Test name
Test status
Simulation time 17251716 ps
CPU time 0.67 seconds
Started Mar 21 12:48:27 PM PDT 24
Finished Mar 21 12:48:28 PM PDT 24
Peak memory 193320 kb
Host smart-d8f33e22-3feb-4b31-914d-7c21f3a131c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41592405 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.41592405
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.792026461
Short name T533
Test name
Test status
Simulation time 49973338 ps
CPU time 0.57 seconds
Started Mar 21 12:48:27 PM PDT 24
Finished Mar 21 12:48:28 PM PDT 24
Peak memory 182628 kb
Host smart-bc365ab4-a5ee-468d-9d5d-9862699fe7b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792026461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.792026461
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2982365222
Short name T492
Test name
Test status
Simulation time 107434121 ps
CPU time 0.55 seconds
Started Mar 21 12:48:17 PM PDT 24
Finished Mar 21 12:48:18 PM PDT 24
Peak memory 182568 kb
Host smart-ce47bc24-9f4f-4dac-95d1-b7fa27f68ca5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982365222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2982365222
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3084400197
Short name T92
Test name
Test status
Simulation time 18920844 ps
CPU time 0.69 seconds
Started Mar 21 12:48:26 PM PDT 24
Finished Mar 21 12:48:27 PM PDT 24
Peak memory 191628 kb
Host smart-89844479-3d3d-4a2d-b8dd-228c22b31954
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084400197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.3084400197
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3874139056
Short name T454
Test name
Test status
Simulation time 347929111 ps
CPU time 2.38 seconds
Started Mar 21 12:48:16 PM PDT 24
Finished Mar 21 12:48:19 PM PDT 24
Peak memory 197552 kb
Host smart-f79f844e-2ba3-475e-9949-3c975c4f15f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874139056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3874139056
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3480567989
Short name T577
Test name
Test status
Simulation time 142490974 ps
CPU time 0.56 seconds
Started Mar 21 12:49:15 PM PDT 24
Finished Mar 21 12:49:15 PM PDT 24
Peak memory 182548 kb
Host smart-67868416-b995-4b79-9114-ecd27b454920
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480567989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3480567989
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3723657323
Short name T486
Test name
Test status
Simulation time 51607643 ps
CPU time 0.51 seconds
Started Mar 21 12:49:18 PM PDT 24
Finished Mar 21 12:49:19 PM PDT 24
Peak memory 181992 kb
Host smart-8a1efc57-f80e-4e0e-8f49-8a20d1224db4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723657323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3723657323
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.274863992
Short name T458
Test name
Test status
Simulation time 14138422 ps
CPU time 0.54 seconds
Started Mar 21 12:49:14 PM PDT 24
Finished Mar 21 12:49:15 PM PDT 24
Peak memory 182564 kb
Host smart-c01cc490-d2a8-434e-8b01-4410a04f0f31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274863992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.274863992
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2218369946
Short name T460
Test name
Test status
Simulation time 65772796 ps
CPU time 0.5 seconds
Started Mar 21 12:49:12 PM PDT 24
Finished Mar 21 12:49:13 PM PDT 24
Peak memory 182180 kb
Host smart-d2d0faec-3371-4b19-9693-8c85914f2f21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218369946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2218369946
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3011186707
Short name T490
Test name
Test status
Simulation time 39653374 ps
CPU time 0.54 seconds
Started Mar 21 12:49:12 PM PDT 24
Finished Mar 21 12:49:13 PM PDT 24
Peak memory 182100 kb
Host smart-6b71f215-64bd-4638-8cb5-879aebc9f770
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011186707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3011186707
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.910765852
Short name T548
Test name
Test status
Simulation time 35429276 ps
CPU time 0.49 seconds
Started Mar 21 12:49:18 PM PDT 24
Finished Mar 21 12:49:19 PM PDT 24
Peak memory 181984 kb
Host smart-90738b1e-4e1e-4aea-9e29-e38176d16e35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910765852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.910765852
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1630781372
Short name T491
Test name
Test status
Simulation time 31046810 ps
CPU time 0.55 seconds
Started Mar 21 12:49:14 PM PDT 24
Finished Mar 21 12:49:15 PM PDT 24
Peak memory 182500 kb
Host smart-8849530d-372d-472d-b5bd-0e5600ac4068
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630781372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1630781372
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.4001595056
Short name T537
Test name
Test status
Simulation time 12274489 ps
CPU time 0.59 seconds
Started Mar 21 12:49:13 PM PDT 24
Finished Mar 21 12:49:13 PM PDT 24
Peak memory 182568 kb
Host smart-59345f0f-01b7-4033-89ed-2f6a08799434
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001595056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.4001595056
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3126329407
Short name T472
Test name
Test status
Simulation time 24733259 ps
CPU time 0.54 seconds
Started Mar 21 12:49:14 PM PDT 24
Finished Mar 21 12:49:14 PM PDT 24
Peak memory 182500 kb
Host smart-b5db76eb-ee74-47ea-b67e-1f5046c991eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126329407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3126329407
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1503405792
Short name T475
Test name
Test status
Simulation time 12691240 ps
CPU time 0.56 seconds
Started Mar 21 12:49:15 PM PDT 24
Finished Mar 21 12:49:16 PM PDT 24
Peak memory 181960 kb
Host smart-fa48de25-7ae7-41c9-ab1f-6408fd3d2580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503405792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1503405792
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2830810607
Short name T503
Test name
Test status
Simulation time 23254002 ps
CPU time 0.68 seconds
Started Mar 21 12:48:27 PM PDT 24
Finished Mar 21 12:48:28 PM PDT 24
Peak memory 194564 kb
Host smart-82271afc-9028-46da-a9dc-64b8f14a7227
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830810607 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2830810607
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1480428770
Short name T525
Test name
Test status
Simulation time 62071751 ps
CPU time 0.53 seconds
Started Mar 21 12:48:25 PM PDT 24
Finished Mar 21 12:48:27 PM PDT 24
Peak memory 182796 kb
Host smart-71e4ab7f-fef0-4ce3-8726-2065ed22be8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480428770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1480428770
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1890551042
Short name T471
Test name
Test status
Simulation time 106283224 ps
CPU time 0.51 seconds
Started Mar 21 12:48:25 PM PDT 24
Finished Mar 21 12:48:27 PM PDT 24
Peak memory 182276 kb
Host smart-90056c6b-4cfa-4dd7-a946-72fd833a3ec5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890551042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1890551042
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2381227993
Short name T59
Test name
Test status
Simulation time 32278252 ps
CPU time 0.74 seconds
Started Mar 21 12:48:28 PM PDT 24
Finished Mar 21 12:48:29 PM PDT 24
Peak memory 191612 kb
Host smart-f2a542fc-23f5-4686-bbd5-4bb93b538ed0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381227993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2381227993
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.4053827183
Short name T499
Test name
Test status
Simulation time 43731336 ps
CPU time 1.23 seconds
Started Mar 21 12:48:27 PM PDT 24
Finished Mar 21 12:48:28 PM PDT 24
Peak memory 197536 kb
Host smart-c74b6bcb-3be1-40e2-b5f9-0b479d8bd137
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053827183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.4053827183
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2223725043
Short name T32
Test name
Test status
Simulation time 83995514 ps
CPU time 1.05 seconds
Started Mar 21 12:48:26 PM PDT 24
Finished Mar 21 12:48:27 PM PDT 24
Peak memory 195004 kb
Host smart-56223ff2-4c82-45e2-ad32-408584ec2176
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223725043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.2223725043
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.265701113
Short name T565
Test name
Test status
Simulation time 25180897 ps
CPU time 1.01 seconds
Started Mar 21 12:48:33 PM PDT 24
Finished Mar 21 12:48:34 PM PDT 24
Peak memory 197260 kb
Host smart-0685a33f-7b8a-48fd-a1b5-24fa8f2dc9e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265701113 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.265701113
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1123661958
Short name T94
Test name
Test status
Simulation time 66846274 ps
CPU time 0.55 seconds
Started Mar 21 12:48:33 PM PDT 24
Finished Mar 21 12:48:34 PM PDT 24
Peak memory 182564 kb
Host smart-1036301f-455a-4de7-beb4-138566393c00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123661958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1123661958
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.301730748
Short name T506
Test name
Test status
Simulation time 13992050 ps
CPU time 0.56 seconds
Started Mar 21 12:48:33 PM PDT 24
Finished Mar 21 12:48:34 PM PDT 24
Peak memory 182464 kb
Host smart-8bf2dde4-32c2-4112-bd07-a9a539741717
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301730748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.301730748
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2140750547
Short name T69
Test name
Test status
Simulation time 32278770 ps
CPU time 0.73 seconds
Started Mar 21 12:48:34 PM PDT 24
Finished Mar 21 12:48:34 PM PDT 24
Peak memory 193136 kb
Host smart-7ebdbb22-e4ea-492e-aacf-b0f7c1dddfcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140750547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.2140750547
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2906158994
Short name T567
Test name
Test status
Simulation time 72376415 ps
CPU time 1.82 seconds
Started Mar 21 12:48:26 PM PDT 24
Finished Mar 21 12:48:28 PM PDT 24
Peak memory 197500 kb
Host smart-1b71b72b-dbed-4c4e-993a-1fcc384ad4b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906158994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2906158994
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2218381670
Short name T455
Test name
Test status
Simulation time 215158213 ps
CPU time 0.82 seconds
Started Mar 21 12:48:27 PM PDT 24
Finished Mar 21 12:48:28 PM PDT 24
Peak memory 193768 kb
Host smart-5d9a3055-ac6c-49af-bed5-b115206fc4ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218381670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2218381670
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3784898554
Short name T544
Test name
Test status
Simulation time 25258310 ps
CPU time 0.75 seconds
Started Mar 21 12:48:40 PM PDT 24
Finished Mar 21 12:48:43 PM PDT 24
Peak memory 195284 kb
Host smart-f016c475-4d92-4af5-8008-d17ee4df0ecd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784898554 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3784898554
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2144398277
Short name T554
Test name
Test status
Simulation time 148215354 ps
CPU time 0.61 seconds
Started Mar 21 12:48:27 PM PDT 24
Finished Mar 21 12:48:28 PM PDT 24
Peak memory 182524 kb
Host smart-9745e3d2-c310-4078-b53a-0dea91e9655b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144398277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2144398277
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2230501764
Short name T529
Test name
Test status
Simulation time 18248429 ps
CPU time 0.57 seconds
Started Mar 21 12:48:26 PM PDT 24
Finished Mar 21 12:48:27 PM PDT 24
Peak memory 182532 kb
Host smart-9cd40d1a-1606-49c9-94c9-14255c9c5316
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230501764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2230501764
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3599018205
Short name T513
Test name
Test status
Simulation time 31421081 ps
CPU time 0.65 seconds
Started Mar 21 12:48:34 PM PDT 24
Finished Mar 21 12:48:34 PM PDT 24
Peak memory 191876 kb
Host smart-a53ad79f-e8cd-4bc4-b471-6e515861b3fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599018205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3599018205
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.72285565
Short name T464
Test name
Test status
Simulation time 117420098 ps
CPU time 1.28 seconds
Started Mar 21 12:48:27 PM PDT 24
Finished Mar 21 12:48:29 PM PDT 24
Peak memory 197480 kb
Host smart-7ecec7fc-a5c2-4359-a626-9198753741b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72285565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.72285565
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.393357102
Short name T125
Test name
Test status
Simulation time 241568726 ps
CPU time 1.08 seconds
Started Mar 21 12:48:27 PM PDT 24
Finished Mar 21 12:48:29 PM PDT 24
Peak memory 194824 kb
Host smart-8d93335b-198e-4b11-9dff-526d2b3bb1e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393357102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int
g_err.393357102
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.376693788
Short name T528
Test name
Test status
Simulation time 60968917 ps
CPU time 0.83 seconds
Started Mar 21 12:48:35 PM PDT 24
Finished Mar 21 12:48:36 PM PDT 24
Peak memory 196640 kb
Host smart-4f144283-c6aa-47a0-a5dc-bad6ad49f56c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376693788 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.376693788
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2953160969
Short name T113
Test name
Test status
Simulation time 35719287 ps
CPU time 0.59 seconds
Started Mar 21 12:48:35 PM PDT 24
Finished Mar 21 12:48:35 PM PDT 24
Peak memory 182636 kb
Host smart-0eb1589e-91e8-4320-a2e3-624a2043a512
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953160969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2953160969
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3814889278
Short name T574
Test name
Test status
Simulation time 121120232 ps
CPU time 0.52 seconds
Started Mar 21 12:48:36 PM PDT 24
Finished Mar 21 12:48:37 PM PDT 24
Peak memory 181952 kb
Host smart-8c1d98d8-b4ef-4d74-9cde-4ccdaabf820e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814889278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3814889278
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3022288985
Short name T494
Test name
Test status
Simulation time 13460435 ps
CPU time 0.62 seconds
Started Mar 21 12:48:36 PM PDT 24
Finished Mar 21 12:48:37 PM PDT 24
Peak memory 191536 kb
Host smart-f7f5b37b-257e-4324-a15f-adc2991a0677
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022288985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.3022288985
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1143542643
Short name T54
Test name
Test status
Simulation time 533550417 ps
CPU time 2.19 seconds
Started Mar 21 12:48:36 PM PDT 24
Finished Mar 21 12:48:39 PM PDT 24
Peak memory 197572 kb
Host smart-0602c95b-e38e-4b1a-8d25-dab2173455f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143542643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1143542643
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2970620018
Short name T477
Test name
Test status
Simulation time 120849231 ps
CPU time 1.35 seconds
Started Mar 21 12:48:35 PM PDT 24
Finished Mar 21 12:48:37 PM PDT 24
Peak memory 195344 kb
Host smart-28268a9d-834d-450d-9c66-a238577f6a2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970620018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2970620018
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1078279715
Short name T519
Test name
Test status
Simulation time 23307217 ps
CPU time 0.91 seconds
Started Mar 21 12:48:34 PM PDT 24
Finished Mar 21 12:48:35 PM PDT 24
Peak memory 196300 kb
Host smart-424150f3-0f5a-4a68-9825-fb7302eaee53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078279715 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1078279715
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3513933240
Short name T108
Test name
Test status
Simulation time 17604318 ps
CPU time 0.57 seconds
Started Mar 21 12:48:34 PM PDT 24
Finished Mar 21 12:48:35 PM PDT 24
Peak memory 182604 kb
Host smart-f5d08cff-7b44-4dc8-88ad-26e8a6cf7906
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513933240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3513933240
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.4216951598
Short name T481
Test name
Test status
Simulation time 40654984 ps
CPU time 0.5 seconds
Started Mar 21 12:48:34 PM PDT 24
Finished Mar 21 12:48:34 PM PDT 24
Peak memory 182460 kb
Host smart-e6acddc1-73f7-4a51-a70a-6a91a612c85b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216951598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.4216951598
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1884724938
Short name T110
Test name
Test status
Simulation time 41949095 ps
CPU time 0.62 seconds
Started Mar 21 12:48:33 PM PDT 24
Finished Mar 21 12:48:34 PM PDT 24
Peak memory 191948 kb
Host smart-45e1cd34-6db7-45d7-8f41-fc4f1b2e6654
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884724938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1884724938
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2079402497
Short name T556
Test name
Test status
Simulation time 19545500 ps
CPU time 0.96 seconds
Started Mar 21 12:48:33 PM PDT 24
Finished Mar 21 12:48:34 PM PDT 24
Peak memory 197416 kb
Host smart-cefed5f9-5d3c-49fc-baad-9744162a531b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079402497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2079402497
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1457146198
Short name T123
Test name
Test status
Simulation time 132224120 ps
CPU time 1.31 seconds
Started Mar 21 12:48:35 PM PDT 24
Finished Mar 21 12:48:36 PM PDT 24
Peak memory 195328 kb
Host smart-135df5c2-7ec4-4e5d-bbb2-85df5fba1099
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457146198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1457146198
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2014956754
Short name T386
Test name
Test status
Simulation time 84928350855 ps
CPU time 126.92 seconds
Started Mar 21 12:50:10 PM PDT 24
Finished Mar 21 12:52:17 PM PDT 24
Peak memory 182620 kb
Host smart-c0868c86-e49f-4ea6-a3a9-177bc42568d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014956754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2014956754
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.2184975924
Short name T397
Test name
Test status
Simulation time 123909394951 ps
CPU time 446.98 seconds
Started Mar 21 12:50:05 PM PDT 24
Finished Mar 21 12:57:32 PM PDT 24
Peak memory 182568 kb
Host smart-4ae34d37-b6ca-4fcf-8288-2ffa019d4d33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184975924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2184975924
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3728348433
Short name T311
Test name
Test status
Simulation time 5831283775 ps
CPU time 32.26 seconds
Started Mar 21 12:50:06 PM PDT 24
Finished Mar 21 12:50:39 PM PDT 24
Peak memory 182556 kb
Host smart-a7fb4a17-e3c7-418b-83a6-c2d1ae2a6221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728348433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3728348433
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.3463303102
Short name T213
Test name
Test status
Simulation time 654400516874 ps
CPU time 334.18 seconds
Started Mar 21 12:50:05 PM PDT 24
Finished Mar 21 12:55:40 PM PDT 24
Peak memory 182564 kb
Host smart-fea6ca5a-8698-4d25-89e5-cfed25f29ca1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463303102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.3463303102
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.1216970682
Short name T392
Test name
Test status
Simulation time 61479243353 ps
CPU time 92.75 seconds
Started Mar 21 12:50:04 PM PDT 24
Finished Mar 21 12:51:37 PM PDT 24
Peak memory 182676 kb
Host smart-fa371cb2-5421-4d3a-a094-0a30c570aa33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216970682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1216970682
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.861956960
Short name T274
Test name
Test status
Simulation time 42758965119 ps
CPU time 23.49 seconds
Started Mar 21 12:50:07 PM PDT 24
Finished Mar 21 12:50:31 PM PDT 24
Peak memory 182564 kb
Host smart-bebb8094-3e8c-4128-94d4-53d524a38a14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861956960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.861956960
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2058758926
Short name T419
Test name
Test status
Simulation time 155033321021 ps
CPU time 141.03 seconds
Started Mar 21 12:50:02 PM PDT 24
Finished Mar 21 12:52:23 PM PDT 24
Peak memory 182516 kb
Host smart-da1432c6-a861-403f-9595-358ff35b7b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058758926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2058758926
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.334648292
Short name T17
Test name
Test status
Simulation time 103892947 ps
CPU time 0.85 seconds
Started Mar 21 12:50:07 PM PDT 24
Finished Mar 21 12:50:08 PM PDT 24
Peak memory 213020 kb
Host smart-279b4608-aba0-4a36-8400-8a917678ef9f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334648292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.334648292
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3702653944
Short name T337
Test name
Test status
Simulation time 10670811402 ps
CPU time 19.33 seconds
Started Mar 21 12:50:18 PM PDT 24
Finished Mar 21 12:50:39 PM PDT 24
Peak memory 182652 kb
Host smart-2263c017-61a2-44b9-8e64-b877652b097c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702653944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3702653944
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.1725775568
Short name T372
Test name
Test status
Simulation time 59465453244 ps
CPU time 47.27 seconds
Started Mar 21 12:50:19 PM PDT 24
Finished Mar 21 12:51:07 PM PDT 24
Peak memory 182560 kb
Host smart-9e764bbb-a855-4e01-8e4d-23244a27751c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725775568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1725775568
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1278991386
Short name T260
Test name
Test status
Simulation time 46288791529 ps
CPU time 70.91 seconds
Started Mar 21 12:50:16 PM PDT 24
Finished Mar 21 12:51:29 PM PDT 24
Peak memory 194260 kb
Host smart-5be81336-a463-4298-9278-5ded598ea219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278991386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1278991386
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.1401107756
Short name T40
Test name
Test status
Simulation time 56678598466 ps
CPU time 446.87 seconds
Started Mar 21 12:50:20 PM PDT 24
Finished Mar 21 12:57:48 PM PDT 24
Peak memory 205476 kb
Host smart-45e70605-e399-4398-a364-c910291b9744
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401107756 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.1401107756
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.1896270193
Short name T278
Test name
Test status
Simulation time 46125456490 ps
CPU time 34.66 seconds
Started Mar 21 12:52:16 PM PDT 24
Finished Mar 21 12:52:51 PM PDT 24
Peak memory 182556 kb
Host smart-323a59c4-1b2f-4cd8-bbe5-743ab09f2187
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896270193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1896270193
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.1017544348
Short name T128
Test name
Test status
Simulation time 61617760049 ps
CPU time 144.53 seconds
Started Mar 21 12:52:15 PM PDT 24
Finished Mar 21 12:54:40 PM PDT 24
Peak memory 190812 kb
Host smart-8a79f0dd-2ca4-4b39-bb3e-4bf43428c8bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017544348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1017544348
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.203807033
Short name T450
Test name
Test status
Simulation time 29301628304 ps
CPU time 317.57 seconds
Started Mar 21 12:52:16 PM PDT 24
Finished Mar 21 12:57:34 PM PDT 24
Peak memory 182584 kb
Host smart-b85148f3-9514-46f6-a87d-74d44c9a0ab2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203807033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.203807033
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.2678641918
Short name T336
Test name
Test status
Simulation time 14904204061 ps
CPU time 24.22 seconds
Started Mar 21 12:52:15 PM PDT 24
Finished Mar 21 12:52:39 PM PDT 24
Peak memory 182600 kb
Host smart-f5b5341b-41f7-4822-8386-35384780771b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678641918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2678641918
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2276222599
Short name T232
Test name
Test status
Simulation time 151237710359 ps
CPU time 600.12 seconds
Started Mar 21 12:52:16 PM PDT 24
Finished Mar 21 01:02:16 PM PDT 24
Peak memory 190764 kb
Host smart-557ff4d5-01f7-4d8a-be39-d20aff3a66d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276222599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2276222599
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.964255984
Short name T175
Test name
Test status
Simulation time 360811709583 ps
CPU time 351.77 seconds
Started Mar 21 12:52:15 PM PDT 24
Finished Mar 21 12:58:07 PM PDT 24
Peak memory 190816 kb
Host smart-99cb8e69-f3fe-4404-9c6e-10256c11bbe6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964255984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.964255984
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3105251767
Short name T305
Test name
Test status
Simulation time 111892186531 ps
CPU time 113.72 seconds
Started Mar 21 12:50:19 PM PDT 24
Finished Mar 21 12:52:13 PM PDT 24
Peak memory 182580 kb
Host smart-6080c5b4-3834-48b7-b136-05fdac95cc32
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105251767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3105251767
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.3942285765
Short name T27
Test name
Test status
Simulation time 210973759690 ps
CPU time 318.07 seconds
Started Mar 21 12:50:16 PM PDT 24
Finished Mar 21 12:55:35 PM PDT 24
Peak memory 182584 kb
Host smart-9b281f92-b827-4b43-b3ea-1fba176a45cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942285765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.3942285765
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.1304233921
Short name T126
Test name
Test status
Simulation time 604837725206 ps
CPU time 466.93 seconds
Started Mar 21 12:50:18 PM PDT 24
Finished Mar 21 12:58:06 PM PDT 24
Peak memory 194188 kb
Host smart-d7749246-9ac3-4391-accb-675e90ecc175
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304233921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1304233921
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2334705691
Short name T12
Test name
Test status
Simulation time 18356722598 ps
CPU time 24.45 seconds
Started Mar 21 12:50:17 PM PDT 24
Finished Mar 21 12:50:44 PM PDT 24
Peak memory 192864 kb
Host smart-71619ad3-f203-4200-9dac-5dc6986add0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334705691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2334705691
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.3142074089
Short name T115
Test name
Test status
Simulation time 8298503559 ps
CPU time 13.51 seconds
Started Mar 21 12:52:16 PM PDT 24
Finished Mar 21 12:52:29 PM PDT 24
Peak memory 182684 kb
Host smart-e6dc447c-873e-4a89-bd55-30e962c3ae45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142074089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3142074089
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.3810506882
Short name T253
Test name
Test status
Simulation time 108570284678 ps
CPU time 1906.44 seconds
Started Mar 21 12:52:16 PM PDT 24
Finished Mar 21 01:24:03 PM PDT 24
Peak memory 190776 kb
Host smart-fcbb7afc-3526-4001-92c5-a38e8e363eae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810506882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3810506882
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.1772205661
Short name T177
Test name
Test status
Simulation time 231200332370 ps
CPU time 189.28 seconds
Started Mar 21 12:52:25 PM PDT 24
Finished Mar 21 12:55:35 PM PDT 24
Peak memory 190836 kb
Host smart-8947c29f-0afc-436d-9fbc-42932a8dbb11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772205661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1772205661
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.3282459865
Short name T49
Test name
Test status
Simulation time 274666233172 ps
CPU time 266.73 seconds
Started Mar 21 12:52:23 PM PDT 24
Finished Mar 21 12:56:50 PM PDT 24
Peak memory 190780 kb
Host smart-743dde74-b38f-4ed9-bac5-8a1645ff5ab9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282459865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3282459865
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3419893966
Short name T344
Test name
Test status
Simulation time 144225207940 ps
CPU time 1171.37 seconds
Started Mar 21 12:52:23 PM PDT 24
Finished Mar 21 01:11:55 PM PDT 24
Peak memory 182580 kb
Host smart-df4ef728-1a5c-4bbd-ae74-d1f47392957c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419893966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3419893966
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2593275655
Short name T427
Test name
Test status
Simulation time 431899586993 ps
CPU time 416.95 seconds
Started Mar 21 12:52:26 PM PDT 24
Finished Mar 21 12:59:23 PM PDT 24
Peak memory 190748 kb
Host smart-485281c4-7368-47e8-90a3-f13ab107a7c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593275655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2593275655
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.2137977506
Short name T270
Test name
Test status
Simulation time 136361879326 ps
CPU time 204.16 seconds
Started Mar 21 12:52:26 PM PDT 24
Finished Mar 21 12:55:50 PM PDT 24
Peak memory 190800 kb
Host smart-6c01d5cc-1963-4e13-8351-9ad688a317c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137977506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2137977506
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3873717804
Short name T169
Test name
Test status
Simulation time 83561673268 ps
CPU time 37.29 seconds
Started Mar 21 12:50:19 PM PDT 24
Finished Mar 21 12:50:57 PM PDT 24
Peak memory 182588 kb
Host smart-bad76167-caa4-4334-a500-35c27b3bbee3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873717804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3873717804
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.2166189674
Short name T378
Test name
Test status
Simulation time 83471165807 ps
CPU time 132.83 seconds
Started Mar 21 12:50:21 PM PDT 24
Finished Mar 21 12:52:34 PM PDT 24
Peak memory 182616 kb
Host smart-d55eabe5-0a97-4d45-bff3-8854814c76bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166189674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.2166189674
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.3286545983
Short name T45
Test name
Test status
Simulation time 69469043655 ps
CPU time 201.5 seconds
Started Mar 21 12:50:16 PM PDT 24
Finished Mar 21 12:53:40 PM PDT 24
Peak memory 190744 kb
Host smart-47513cbf-8705-47ce-977b-3f3d593e45b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286545983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3286545983
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1389910298
Short name T396
Test name
Test status
Simulation time 30007038 ps
CPU time 0.54 seconds
Started Mar 21 12:50:19 PM PDT 24
Finished Mar 21 12:50:20 PM PDT 24
Peak memory 182408 kb
Host smart-5e25ba36-9416-4c23-8100-7961cdec9d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389910298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1389910298
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.1775247991
Short name T434
Test name
Test status
Simulation time 303406664983 ps
CPU time 374.91 seconds
Started Mar 21 12:50:18 PM PDT 24
Finished Mar 21 12:56:34 PM PDT 24
Peak memory 182632 kb
Host smart-7dc21472-ebda-4650-98f0-907ed009474a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775247991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.1775247991
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.3328834326
Short name T266
Test name
Test status
Simulation time 137342367258 ps
CPU time 403.86 seconds
Started Mar 21 12:52:25 PM PDT 24
Finished Mar 21 12:59:09 PM PDT 24
Peak memory 190768 kb
Host smart-0b756b97-c365-4874-a7c3-8bac4b7b25d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328834326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3328834326
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.1766687005
Short name T80
Test name
Test status
Simulation time 152650576304 ps
CPU time 300.34 seconds
Started Mar 21 12:52:25 PM PDT 24
Finished Mar 21 12:57:26 PM PDT 24
Peak memory 190824 kb
Host smart-3c7c367a-a76a-4cd7-a974-03312ffbe9c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766687005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1766687005
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.2678211703
Short name T233
Test name
Test status
Simulation time 271328206574 ps
CPU time 287.7 seconds
Started Mar 21 12:52:28 PM PDT 24
Finished Mar 21 12:57:16 PM PDT 24
Peak memory 190764 kb
Host smart-78e55aed-0935-4cff-9269-981614bab111
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678211703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2678211703
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1433071237
Short name T431
Test name
Test status
Simulation time 83654380142 ps
CPU time 46.15 seconds
Started Mar 21 12:52:33 PM PDT 24
Finished Mar 21 12:53:19 PM PDT 24
Peak memory 182544 kb
Host smart-54051ab0-17ec-4305-bb65-216f4beb43f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433071237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1433071237
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1645352517
Short name T319
Test name
Test status
Simulation time 193542420579 ps
CPU time 328.1 seconds
Started Mar 21 12:52:47 PM PDT 24
Finished Mar 21 12:58:15 PM PDT 24
Peak memory 190676 kb
Host smart-2becd622-d16a-4d3e-a883-416cd0b39d31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645352517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1645352517
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.1215096471
Short name T255
Test name
Test status
Simulation time 46835318438 ps
CPU time 39.69 seconds
Started Mar 21 12:52:33 PM PDT 24
Finished Mar 21 12:53:13 PM PDT 24
Peak memory 190736 kb
Host smart-d2aca9c9-d32c-45e3-82a6-9eee0c13beac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215096471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1215096471
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2607690153
Short name T248
Test name
Test status
Simulation time 710794414228 ps
CPU time 318.16 seconds
Started Mar 21 12:50:16 PM PDT 24
Finished Mar 21 12:55:35 PM PDT 24
Peak memory 182660 kb
Host smart-4c931942-5190-492e-b470-919f6c9deb89
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607690153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2607690153
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2341386145
Short name T422
Test name
Test status
Simulation time 114614710598 ps
CPU time 155.02 seconds
Started Mar 21 12:50:15 PM PDT 24
Finished Mar 21 12:52:51 PM PDT 24
Peak memory 182548 kb
Host smart-634d100b-3818-4eae-af11-34798544cd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341386145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2341386145
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.446434964
Short name T303
Test name
Test status
Simulation time 43031568317 ps
CPU time 69.73 seconds
Started Mar 21 12:50:16 PM PDT 24
Finished Mar 21 12:51:28 PM PDT 24
Peak memory 182624 kb
Host smart-e2172d49-2d71-42aa-9d5f-78bab49506d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446434964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.446434964
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.535876149
Short name T406
Test name
Test status
Simulation time 174118578 ps
CPU time 0.59 seconds
Started Mar 21 12:50:29 PM PDT 24
Finished Mar 21 12:50:30 PM PDT 24
Peak memory 182292 kb
Host smart-77f8db81-02de-40da-ae07-04f5ac1d06fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535876149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.535876149
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.2668638909
Short name T385
Test name
Test status
Simulation time 1680318033057 ps
CPU time 452.31 seconds
Started Mar 21 12:50:29 PM PDT 24
Finished Mar 21 12:58:01 PM PDT 24
Peak memory 182328 kb
Host smart-ae1c25ce-a367-4a32-b4a5-08fe52876cc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668638909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.2668638909
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.912421999
Short name T264
Test name
Test status
Simulation time 191671607971 ps
CPU time 103.42 seconds
Started Mar 21 12:52:33 PM PDT 24
Finished Mar 21 12:54:16 PM PDT 24
Peak memory 190772 kb
Host smart-635ec12f-4175-4a73-8aa6-02aee2219c31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912421999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.912421999
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.659117962
Short name T220
Test name
Test status
Simulation time 46583502333 ps
CPU time 20.29 seconds
Started Mar 21 12:52:45 PM PDT 24
Finished Mar 21 12:53:06 PM PDT 24
Peak memory 182472 kb
Host smart-9f97d714-fe58-4ee7-9af4-9323f45c829f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659117962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.659117962
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.1128372632
Short name T251
Test name
Test status
Simulation time 250903127442 ps
CPU time 1512.47 seconds
Started Mar 21 12:52:42 PM PDT 24
Finished Mar 21 01:17:56 PM PDT 24
Peak memory 190676 kb
Host smart-5f1f258d-698b-4e47-80bb-86233710701f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128372632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1128372632
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.2884939562
Short name T265
Test name
Test status
Simulation time 241191612298 ps
CPU time 130.03 seconds
Started Mar 21 12:52:32 PM PDT 24
Finished Mar 21 12:54:43 PM PDT 24
Peak memory 190776 kb
Host smart-cb7e0732-9125-4b9e-a523-1e8bcf48437c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884939562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.2884939562
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3601659763
Short name T61
Test name
Test status
Simulation time 92919340024 ps
CPU time 157.28 seconds
Started Mar 21 12:52:47 PM PDT 24
Finished Mar 21 12:55:25 PM PDT 24
Peak memory 190676 kb
Host smart-c1b8a807-f03b-4e6b-bdcd-ca5478353639
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601659763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3601659763
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1737790116
Short name T25
Test name
Test status
Simulation time 58850814657 ps
CPU time 43.11 seconds
Started Mar 21 12:52:47 PM PDT 24
Finished Mar 21 12:53:30 PM PDT 24
Peak memory 182456 kb
Host smart-13c6ef70-bea5-4227-be64-5424636860ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737790116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1737790116
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.1065324522
Short name T312
Test name
Test status
Simulation time 291285045180 ps
CPU time 154.04 seconds
Started Mar 21 12:50:29 PM PDT 24
Finished Mar 21 12:53:03 PM PDT 24
Peak memory 182480 kb
Host smart-9eb34b2d-042f-43c2-a361-17051bc69eb5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065324522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.1065324522
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3617126733
Short name T365
Test name
Test status
Simulation time 126155860329 ps
CPU time 193.94 seconds
Started Mar 21 12:50:29 PM PDT 24
Finished Mar 21 12:53:43 PM PDT 24
Peak memory 182276 kb
Host smart-722b7f36-834b-4cf2-a25c-727467340509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617126733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3617126733
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3096842841
Short name T384
Test name
Test status
Simulation time 308584484 ps
CPU time 1.05 seconds
Started Mar 21 12:50:18 PM PDT 24
Finished Mar 21 12:50:21 PM PDT 24
Peak memory 182320 kb
Host smart-b621d3db-12c5-4750-9ab8-6354eae4dcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096842841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3096842841
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.3614451533
Short name T218
Test name
Test status
Simulation time 2200703602421 ps
CPU time 842.63 seconds
Started Mar 21 12:50:16 PM PDT 24
Finished Mar 21 01:04:21 PM PDT 24
Peak memory 190764 kb
Host smart-a9c99a4d-3de9-44d3-aa42-2f303f2e2540
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614451533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.3614451533
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/141.rv_timer_random.3701863994
Short name T355
Test name
Test status
Simulation time 144883512398 ps
CPU time 106.36 seconds
Started Mar 21 12:52:42 PM PDT 24
Finished Mar 21 12:54:28 PM PDT 24
Peak memory 182620 kb
Host smart-33a0ebf3-9116-47ea-8c51-da393a488ef7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701863994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3701863994
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.4052607720
Short name T183
Test name
Test status
Simulation time 49311589246 ps
CPU time 774.78 seconds
Started Mar 21 12:52:41 PM PDT 24
Finished Mar 21 01:05:36 PM PDT 24
Peak memory 190752 kb
Host smart-b638f8ac-8d02-4acd-abc6-6c526e213d79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052607720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.4052607720
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1815200693
Short name T424
Test name
Test status
Simulation time 39100509399 ps
CPU time 423.73 seconds
Started Mar 21 12:52:46 PM PDT 24
Finished Mar 21 12:59:51 PM PDT 24
Peak memory 182468 kb
Host smart-1eca0343-3d8c-40c9-8b7a-f47eff1e4831
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815200693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1815200693
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1226494993
Short name T85
Test name
Test status
Simulation time 225379940495 ps
CPU time 243.61 seconds
Started Mar 21 12:52:45 PM PDT 24
Finished Mar 21 12:56:49 PM PDT 24
Peak memory 190720 kb
Host smart-cd9216b1-0d18-43d2-8270-c37645732260
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226494993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1226494993
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2573742180
Short name T207
Test name
Test status
Simulation time 241191271000 ps
CPU time 203.71 seconds
Started Mar 21 12:52:40 PM PDT 24
Finished Mar 21 12:56:04 PM PDT 24
Peak memory 190748 kb
Host smart-517be786-62d9-470c-92f8-df4979c341f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573742180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2573742180
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3324807271
Short name T117
Test name
Test status
Simulation time 93014660086 ps
CPU time 202.47 seconds
Started Mar 21 12:52:45 PM PDT 24
Finished Mar 21 12:56:08 PM PDT 24
Peak memory 190716 kb
Host smart-06e41765-2f46-4f89-9dd8-2b2fe55f44bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324807271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3324807271
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2848320082
Short name T149
Test name
Test status
Simulation time 23986499893 ps
CPU time 23.91 seconds
Started Mar 21 12:52:47 PM PDT 24
Finished Mar 21 12:53:11 PM PDT 24
Peak memory 182464 kb
Host smart-30fa6c6c-8e9b-4d09-8144-5e4440dd4f6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848320082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2848320082
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.3460293560
Short name T359
Test name
Test status
Simulation time 486824033683 ps
CPU time 271.84 seconds
Started Mar 21 12:50:26 PM PDT 24
Finished Mar 21 12:54:58 PM PDT 24
Peak memory 182572 kb
Host smart-7a8510c6-3c1a-428b-af11-86fdee57d53a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460293560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.3460293560
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1926210576
Short name T383
Test name
Test status
Simulation time 113663378822 ps
CPU time 42.33 seconds
Started Mar 21 12:50:27 PM PDT 24
Finished Mar 21 12:51:10 PM PDT 24
Peak memory 182640 kb
Host smart-04d2208b-e842-46f0-871f-b35ae33d9b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926210576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1926210576
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.4193415117
Short name T307
Test name
Test status
Simulation time 278464149065 ps
CPU time 547.36 seconds
Started Mar 21 12:50:25 PM PDT 24
Finished Mar 21 12:59:32 PM PDT 24
Peak memory 182572 kb
Host smart-e802572f-04a3-4a56-a439-84b039ada4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193415117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.4193415117
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.241531377
Short name T189
Test name
Test status
Simulation time 402736160815 ps
CPU time 220.74 seconds
Started Mar 21 12:52:52 PM PDT 24
Finished Mar 21 12:56:34 PM PDT 24
Peak memory 190824 kb
Host smart-7fbee22a-3df6-4adf-b998-5283d22eb788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241531377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.241531377
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.1267672440
Short name T452
Test name
Test status
Simulation time 1802359198855 ps
CPU time 1717.49 seconds
Started Mar 21 12:53:01 PM PDT 24
Finished Mar 21 01:21:38 PM PDT 24
Peak memory 190720 kb
Host smart-cd926541-7c41-4185-b3db-fd9fb1b25bcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267672440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1267672440
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3811674241
Short name T446
Test name
Test status
Simulation time 39738283941 ps
CPU time 65.45 seconds
Started Mar 21 12:52:51 PM PDT 24
Finished Mar 21 12:53:57 PM PDT 24
Peak memory 182504 kb
Host smart-388f3415-b347-428f-9937-220644108335
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811674241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3811674241
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.1202146808
Short name T64
Test name
Test status
Simulation time 1298121473378 ps
CPU time 1803.23 seconds
Started Mar 21 12:52:52 PM PDT 24
Finished Mar 21 01:22:56 PM PDT 24
Peak memory 190776 kb
Host smart-5a6086ff-279f-4923-8430-ed60f706e06c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202146808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1202146808
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1344192287
Short name T119
Test name
Test status
Simulation time 268580947673 ps
CPU time 161.81 seconds
Started Mar 21 12:52:53 PM PDT 24
Finished Mar 21 12:55:35 PM PDT 24
Peak memory 194456 kb
Host smart-b8bd50f0-3b42-47d8-9eb4-df1359542757
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344192287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1344192287
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.293379856
Short name T318
Test name
Test status
Simulation time 435292434619 ps
CPU time 323.3 seconds
Started Mar 21 12:52:51 PM PDT 24
Finished Mar 21 12:58:15 PM PDT 24
Peak memory 190784 kb
Host smart-31897283-b6ab-4e69-bb62-c5a7932e6936
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293379856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.293379856
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.877648265
Short name T81
Test name
Test status
Simulation time 166765548026 ps
CPU time 279.12 seconds
Started Mar 21 12:50:26 PM PDT 24
Finished Mar 21 12:55:05 PM PDT 24
Peak memory 182652 kb
Host smart-eaa73cbd-a398-46f6-9db1-fd600db124e0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877648265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.rv_timer_cfg_update_on_fly.877648265
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2040718344
Short name T421
Test name
Test status
Simulation time 48564982542 ps
CPU time 67.89 seconds
Started Mar 21 12:50:25 PM PDT 24
Finished Mar 21 12:51:33 PM PDT 24
Peak memory 182548 kb
Host smart-77e6d285-b099-49ac-ad23-f97743e70ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040718344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2040718344
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.1798647198
Short name T286
Test name
Test status
Simulation time 81852847183 ps
CPU time 148.5 seconds
Started Mar 21 12:50:27 PM PDT 24
Finished Mar 21 12:52:56 PM PDT 24
Peak memory 182564 kb
Host smart-312d3e1a-8648-4dc5-83d6-0d49e2a4757c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798647198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.1798647198
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1690017577
Short name T87
Test name
Test status
Simulation time 33322643387 ps
CPU time 56.23 seconds
Started Mar 21 12:50:27 PM PDT 24
Finished Mar 21 12:51:23 PM PDT 24
Peak memory 193808 kb
Host smart-6c13ad9c-9840-4b3f-b323-3b5d53a6e796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690017577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1690017577
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.2154308505
Short name T237
Test name
Test status
Simulation time 70817496262 ps
CPU time 110.01 seconds
Started Mar 21 12:52:54 PM PDT 24
Finished Mar 21 12:54:45 PM PDT 24
Peak memory 190740 kb
Host smart-a53b0535-281c-4c52-9bbf-94f54d8de393
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154308505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.2154308505
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.933623444
Short name T322
Test name
Test status
Simulation time 57512531574 ps
CPU time 132.5 seconds
Started Mar 21 12:53:01 PM PDT 24
Finished Mar 21 12:55:13 PM PDT 24
Peak memory 182524 kb
Host smart-8a2178e2-79ff-4838-853d-78ff4d68e5f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933623444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.933623444
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.2686283794
Short name T273
Test name
Test status
Simulation time 775454607372 ps
CPU time 365.04 seconds
Started Mar 21 12:52:51 PM PDT 24
Finished Mar 21 12:58:56 PM PDT 24
Peak memory 190804 kb
Host smart-7eeffbc8-f040-4880-a1f6-23b100265277
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686283794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2686283794
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.84810558
Short name T387
Test name
Test status
Simulation time 224166064782 ps
CPU time 51.22 seconds
Started Mar 21 12:52:53 PM PDT 24
Finished Mar 21 12:53:44 PM PDT 24
Peak memory 182636 kb
Host smart-4a4a93e9-0b15-4ece-8e6d-9d3d24a2589a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84810558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.84810558
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.1807156925
Short name T198
Test name
Test status
Simulation time 53461355719 ps
CPU time 97.7 seconds
Started Mar 21 12:52:52 PM PDT 24
Finished Mar 21 12:54:31 PM PDT 24
Peak memory 190768 kb
Host smart-1e426062-7d30-4ad0-b8f7-719f5592b863
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807156925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.1807156925
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.131369825
Short name T26
Test name
Test status
Simulation time 5062563631 ps
CPU time 2.94 seconds
Started Mar 21 12:52:51 PM PDT 24
Finished Mar 21 12:52:55 PM PDT 24
Peak memory 182608 kb
Host smart-474b8dd7-3f57-48e9-ba37-0466e20caa5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131369825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.131369825
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3742243185
Short name T382
Test name
Test status
Simulation time 143874268244 ps
CPU time 19.95 seconds
Started Mar 21 12:50:26 PM PDT 24
Finished Mar 21 12:50:47 PM PDT 24
Peak memory 182612 kb
Host smart-2fcae185-2eb0-4d6c-9712-01704cacc46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742243185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3742243185
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.203684514
Short name T282
Test name
Test status
Simulation time 112655462410 ps
CPU time 609.12 seconds
Started Mar 21 12:50:25 PM PDT 24
Finished Mar 21 01:00:34 PM PDT 24
Peak memory 190868 kb
Host smart-d8351796-8ec2-407b-a551-dc8eec713977
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203684514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.
203684514
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/173.rv_timer_random.279278904
Short name T153
Test name
Test status
Simulation time 33542048725 ps
CPU time 53.46 seconds
Started Mar 21 12:52:59 PM PDT 24
Finished Mar 21 12:53:53 PM PDT 24
Peak memory 190756 kb
Host smart-f26cf7e4-ae43-4289-9c96-e07482d043db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279278904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.279278904
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.4280455077
Short name T287
Test name
Test status
Simulation time 579886672970 ps
CPU time 322.72 seconds
Started Mar 21 12:52:59 PM PDT 24
Finished Mar 21 12:58:22 PM PDT 24
Peak memory 190744 kb
Host smart-c332fb1a-ce5d-4ff0-87fd-3f09b57dcffd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280455077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.4280455077
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.3979402897
Short name T321
Test name
Test status
Simulation time 197948498009 ps
CPU time 1219.53 seconds
Started Mar 21 12:53:03 PM PDT 24
Finished Mar 21 01:13:22 PM PDT 24
Peak memory 190848 kb
Host smart-cba1cd91-64a5-45f7-99c7-564f75b906d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979402897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3979402897
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2671821460
Short name T147
Test name
Test status
Simulation time 37112568188 ps
CPU time 289.21 seconds
Started Mar 21 12:53:00 PM PDT 24
Finished Mar 21 12:57:50 PM PDT 24
Peak memory 191828 kb
Host smart-078a9565-87cd-4c83-9b1c-93ca7cfc20d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671821460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2671821460
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.502714361
Short name T4
Test name
Test status
Simulation time 631996675220 ps
CPU time 874.81 seconds
Started Mar 21 12:52:59 PM PDT 24
Finished Mar 21 01:07:34 PM PDT 24
Peak memory 190708 kb
Host smart-4a0114b4-bf56-4e79-8f70-6f2436b08a09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502714361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.502714361
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.54693077
Short name T360
Test name
Test status
Simulation time 304219670013 ps
CPU time 160.26 seconds
Started Mar 21 12:50:23 PM PDT 24
Finished Mar 21 12:53:04 PM PDT 24
Peak memory 182556 kb
Host smart-ab417883-ec2e-45e9-93cd-1ef4b897f7df
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54693077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.rv_timer_cfg_update_on_fly.54693077
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1688118940
Short name T425
Test name
Test status
Simulation time 37359265140 ps
CPU time 56.45 seconds
Started Mar 21 12:50:27 PM PDT 24
Finished Mar 21 12:51:23 PM PDT 24
Peak memory 182580 kb
Host smart-a974449e-22e3-4659-96bf-de2840d37f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688118940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1688118940
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.4144900272
Short name T195
Test name
Test status
Simulation time 348462879115 ps
CPU time 114.35 seconds
Started Mar 21 12:50:28 PM PDT 24
Finished Mar 21 12:52:22 PM PDT 24
Peak memory 190816 kb
Host smart-92f98106-996c-4771-8419-c48fd258947e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144900272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.4144900272
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.188953366
Short name T292
Test name
Test status
Simulation time 62198596174 ps
CPU time 113.65 seconds
Started Mar 21 12:50:29 PM PDT 24
Finished Mar 21 12:52:23 PM PDT 24
Peak memory 182528 kb
Host smart-93e30577-25ea-4acd-9e9d-58ec99efd3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188953366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.188953366
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1628125137
Short name T48
Test name
Test status
Simulation time 563848087546 ps
CPU time 1718.24 seconds
Started Mar 21 12:50:25 PM PDT 24
Finished Mar 21 01:19:03 PM PDT 24
Peak memory 182584 kb
Host smart-1a6a70c4-441a-4dd6-86ac-664667633c05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628125137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1628125137
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.1129414599
Short name T200
Test name
Test status
Simulation time 74203937686 ps
CPU time 327.65 seconds
Started Mar 21 12:52:57 PM PDT 24
Finished Mar 21 12:58:26 PM PDT 24
Peak memory 191852 kb
Host smart-e9bbab0e-ed29-4234-893b-6c9b163a5d80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129414599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1129414599
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.270272691
Short name T142
Test name
Test status
Simulation time 171984957363 ps
CPU time 163.23 seconds
Started Mar 21 12:52:59 PM PDT 24
Finished Mar 21 12:55:42 PM PDT 24
Peak memory 190764 kb
Host smart-56b83b4d-ce12-4b1a-b361-334ed3be8a61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270272691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.270272691
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.982867548
Short name T47
Test name
Test status
Simulation time 443131671997 ps
CPU time 128.13 seconds
Started Mar 21 12:53:06 PM PDT 24
Finished Mar 21 12:55:15 PM PDT 24
Peak memory 190756 kb
Host smart-b462a06c-ab09-4a54-a8a3-8ad10b7b013c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982867548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.982867548
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2995946740
Short name T145
Test name
Test status
Simulation time 126804083903 ps
CPU time 1875.53 seconds
Started Mar 21 12:52:59 PM PDT 24
Finished Mar 21 01:24:15 PM PDT 24
Peak memory 190828 kb
Host smart-f16b659e-bbd5-4c9a-993e-4092b1b80871
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995946740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2995946740
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3592622579
Short name T432
Test name
Test status
Simulation time 30644331653 ps
CPU time 13.26 seconds
Started Mar 21 12:52:59 PM PDT 24
Finished Mar 21 12:53:13 PM PDT 24
Peak memory 182604 kb
Host smart-8f9440f8-6210-4df2-aef1-f5595ef92b4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592622579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3592622579
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.3402298151
Short name T323
Test name
Test status
Simulation time 895015042023 ps
CPU time 549.88 seconds
Started Mar 21 12:50:24 PM PDT 24
Finished Mar 21 12:59:34 PM PDT 24
Peak memory 182624 kb
Host smart-0f1ab59f-58fd-45db-81ac-7ce3094c82a0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402298151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.3402298151
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.838608532
Short name T416
Test name
Test status
Simulation time 299702965818 ps
CPU time 128.56 seconds
Started Mar 21 12:50:26 PM PDT 24
Finished Mar 21 12:52:34 PM PDT 24
Peak memory 182572 kb
Host smart-2e280a8b-efb3-46e2-b079-f2869ce3446e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838608532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.838608532
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.2101749096
Short name T204
Test name
Test status
Simulation time 41756338217 ps
CPU time 64.62 seconds
Started Mar 21 12:50:27 PM PDT 24
Finished Mar 21 12:51:32 PM PDT 24
Peak memory 182568 kb
Host smart-a7af32f2-1973-416d-be1a-07a44bf7bd51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101749096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2101749096
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.2384038188
Short name T51
Test name
Test status
Simulation time 118497453732 ps
CPU time 136.19 seconds
Started Mar 21 12:53:00 PM PDT 24
Finished Mar 21 12:55:17 PM PDT 24
Peak memory 190724 kb
Host smart-e6e834cd-74ac-418d-9c0c-a018413e4220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384038188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.2384038188
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.2744017103
Short name T300
Test name
Test status
Simulation time 65722586464 ps
CPU time 255.38 seconds
Started Mar 21 12:53:00 PM PDT 24
Finished Mar 21 12:57:16 PM PDT 24
Peak memory 190832 kb
Host smart-c70bd879-b946-4aa8-b47c-d513a20c8bc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744017103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2744017103
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.448256967
Short name T437
Test name
Test status
Simulation time 321650871021 ps
CPU time 2024.07 seconds
Started Mar 21 12:53:09 PM PDT 24
Finished Mar 21 01:26:54 PM PDT 24
Peak memory 190740 kb
Host smart-4efe2a48-2065-4e6b-9feb-2f60a269c2f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448256967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.448256967
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.4164482303
Short name T216
Test name
Test status
Simulation time 245846109751 ps
CPU time 158.29 seconds
Started Mar 21 12:53:08 PM PDT 24
Finished Mar 21 12:55:47 PM PDT 24
Peak memory 182684 kb
Host smart-9f7baeba-a706-41de-b2b0-3981cd042ab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164482303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.4164482303
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.2886272220
Short name T187
Test name
Test status
Simulation time 115939086303 ps
CPU time 94.02 seconds
Started Mar 21 12:53:09 PM PDT 24
Finished Mar 21 12:54:43 PM PDT 24
Peak memory 190664 kb
Host smart-bf6f3194-17cc-4bd1-8130-becdb296aedd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886272220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2886272220
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.3423961964
Short name T447
Test name
Test status
Simulation time 224913779425 ps
CPU time 159.51 seconds
Started Mar 21 12:50:04 PM PDT 24
Finished Mar 21 12:52:44 PM PDT 24
Peak memory 182544 kb
Host smart-5649f22f-49d6-4de5-b04c-532254db2281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423961964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3423961964
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3589832851
Short name T238
Test name
Test status
Simulation time 1197681164179 ps
CPU time 308.23 seconds
Started Mar 21 12:50:03 PM PDT 24
Finished Mar 21 12:55:12 PM PDT 24
Peak memory 190752 kb
Host smart-4d50c993-b2db-4742-a19b-9ae4117680c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589832851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3589832851
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.2119477863
Short name T309
Test name
Test status
Simulation time 113117944044 ps
CPU time 135.21 seconds
Started Mar 21 12:50:08 PM PDT 24
Finished Mar 21 12:52:24 PM PDT 24
Peak memory 190792 kb
Host smart-1f49a5fc-6790-43cd-a566-eda796a7be55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119477863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2119477863
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.2413333702
Short name T19
Test name
Test status
Simulation time 156815467 ps
CPU time 0.9 seconds
Started Mar 21 12:50:07 PM PDT 24
Finished Mar 21 12:50:08 PM PDT 24
Peak memory 214120 kb
Host smart-fa4a9631-01ef-40b6-894f-afc06c987e79
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413333702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.2413333702
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.960502686
Short name T36
Test name
Test status
Simulation time 952251415915 ps
CPU time 1773.85 seconds
Started Mar 21 12:50:05 PM PDT 24
Finished Mar 21 01:19:40 PM PDT 24
Peak memory 194556 kb
Host smart-08376d37-8122-4cfa-960a-b3a3fe35c482
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960502686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.960502686
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.584265956
Short name T114
Test name
Test status
Simulation time 3564506969 ps
CPU time 6.52 seconds
Started Mar 21 12:50:25 PM PDT 24
Finished Mar 21 12:50:32 PM PDT 24
Peak memory 182588 kb
Host smart-b0ad736e-5e3e-4447-bd27-bff86bd8a94f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584265956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.rv_timer_cfg_update_on_fly.584265956
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.2235403626
Short name T429
Test name
Test status
Simulation time 398528804904 ps
CPU time 169.48 seconds
Started Mar 21 12:51:18 PM PDT 24
Finished Mar 21 12:54:08 PM PDT 24
Peak memory 182592 kb
Host smart-8ffdee47-cc1c-457e-a1e6-27569f2ba24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235403626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.2235403626
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.4216737231
Short name T280
Test name
Test status
Simulation time 1318364324311 ps
CPU time 1822.01 seconds
Started Mar 21 12:50:27 PM PDT 24
Finished Mar 21 01:20:49 PM PDT 24
Peak memory 190732 kb
Host smart-fa9a450a-263f-40a6-a4cd-2dc5c8725aec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216737231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.4216737231
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3287201544
Short name T333
Test name
Test status
Simulation time 6277655908 ps
CPU time 11.48 seconds
Started Mar 21 12:50:24 PM PDT 24
Finished Mar 21 12:50:37 PM PDT 24
Peak memory 194580 kb
Host smart-3e9d6402-a7a6-46e4-82e1-33480e125110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287201544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3287201544
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.1547944744
Short name T341
Test name
Test status
Simulation time 3640215289677 ps
CPU time 1612.09 seconds
Started Mar 21 12:50:27 PM PDT 24
Finished Mar 21 01:17:19 PM PDT 24
Peak memory 190844 kb
Host smart-3667d7ae-bc5b-48bf-bb3c-9ed68e1cbe28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547944744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.1547944744
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.706573312
Short name T268
Test name
Test status
Simulation time 250352859776 ps
CPU time 449.95 seconds
Started Mar 21 12:50:26 PM PDT 24
Finished Mar 21 12:57:56 PM PDT 24
Peak memory 182584 kb
Host smart-453e1a01-1514-4438-b72a-e861b1f574bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706573312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.rv_timer_cfg_update_on_fly.706573312
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1172216693
Short name T453
Test name
Test status
Simulation time 350256191592 ps
CPU time 159.67 seconds
Started Mar 21 12:50:23 PM PDT 24
Finished Mar 21 12:53:03 PM PDT 24
Peak memory 182520 kb
Host smart-d330c4e7-dcef-4f45-8a54-ca75c6879d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172216693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1172216693
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.1605271390
Short name T334
Test name
Test status
Simulation time 191252425318 ps
CPU time 108.12 seconds
Started Mar 21 12:50:29 PM PDT 24
Finished Mar 21 12:52:18 PM PDT 24
Peak memory 190720 kb
Host smart-3ee702bb-48a8-40e9-a100-3e65e6202082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605271390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1605271390
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3943848631
Short name T279
Test name
Test status
Simulation time 69174131347 ps
CPU time 40.26 seconds
Started Mar 21 12:50:27 PM PDT 24
Finished Mar 21 12:51:07 PM PDT 24
Peak memory 190724 kb
Host smart-3bca73af-178e-4a4b-bdac-d0532cde8c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943848631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3943848631
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.861390064
Short name T118
Test name
Test status
Simulation time 724225609631 ps
CPU time 108.84 seconds
Started Mar 21 12:50:38 PM PDT 24
Finished Mar 21 12:52:27 PM PDT 24
Peak memory 182544 kb
Host smart-da87485e-2c5b-47e9-b830-da8f12f8f56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861390064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.861390064
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.2532346831
Short name T3
Test name
Test status
Simulation time 118691827207 ps
CPU time 196.15 seconds
Started Mar 21 12:50:39 PM PDT 24
Finished Mar 21 12:53:55 PM PDT 24
Peak memory 190784 kb
Host smart-d9cc1535-da95-41c2-b7ae-94f5b0493a7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532346831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2532346831
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1523375429
Short name T351
Test name
Test status
Simulation time 174771684726 ps
CPU time 183.17 seconds
Started Mar 21 12:50:35 PM PDT 24
Finished Mar 21 12:53:38 PM PDT 24
Peak memory 194564 kb
Host smart-7b81fea9-3f36-466c-9580-572193cb750f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523375429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1523375429
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.42644004
Short name T296
Test name
Test status
Simulation time 203590396697 ps
CPU time 181.03 seconds
Started Mar 21 12:50:37 PM PDT 24
Finished Mar 21 12:53:38 PM PDT 24
Peak memory 182584 kb
Host smart-6218c2aa-bfbe-488c-b891-f02e3bfbf34f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42644004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.rv_timer_cfg_update_on_fly.42644004
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.260807318
Short name T428
Test name
Test status
Simulation time 60557172149 ps
CPU time 90.03 seconds
Started Mar 21 12:50:36 PM PDT 24
Finished Mar 21 12:52:06 PM PDT 24
Peak memory 182820 kb
Host smart-5c68200b-2da9-471b-8629-b00290e3d18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260807318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.260807318
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.4033520790
Short name T196
Test name
Test status
Simulation time 397647521099 ps
CPU time 2609.36 seconds
Started Mar 21 12:50:38 PM PDT 24
Finished Mar 21 01:34:08 PM PDT 24
Peak memory 190748 kb
Host smart-ebe3207b-aa0d-46d1-a6e5-6da636f61a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033520790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.4033520790
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.2545647017
Short name T14
Test name
Test status
Simulation time 23061156688 ps
CPU time 252.17 seconds
Started Mar 21 12:50:37 PM PDT 24
Finished Mar 21 12:54:49 PM PDT 24
Peak memory 197276 kb
Host smart-b12390e6-3390-4e51-b6ec-f87a8714cf56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545647017 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.2545647017
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2830101617
Short name T215
Test name
Test status
Simulation time 1628241323 ps
CPU time 3.54 seconds
Started Mar 21 12:50:35 PM PDT 24
Finished Mar 21 12:50:39 PM PDT 24
Peak memory 182488 kb
Host smart-402d017b-3591-4332-9def-093c8e5cb4fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830101617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2830101617
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.838631765
Short name T403
Test name
Test status
Simulation time 395142561835 ps
CPU time 155.73 seconds
Started Mar 21 12:50:37 PM PDT 24
Finished Mar 21 12:53:12 PM PDT 24
Peak memory 182508 kb
Host smart-0b0a8c4b-ff58-4fef-96a2-7ee31b85f71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838631765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.838631765
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.3230393751
Short name T340
Test name
Test status
Simulation time 33931254777 ps
CPU time 58.64 seconds
Started Mar 21 12:50:37 PM PDT 24
Finished Mar 21 12:51:36 PM PDT 24
Peak memory 190796 kb
Host smart-edd64f74-a3b6-4c08-81c9-10f22435dbce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230393751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3230393751
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1195468551
Short name T436
Test name
Test status
Simulation time 773835400713 ps
CPU time 550.03 seconds
Started Mar 21 12:50:38 PM PDT 24
Finished Mar 21 12:59:48 PM PDT 24
Peak memory 194296 kb
Host smart-ea61c8dc-f75d-41af-80bd-92a1a8ed3ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195468551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1195468551
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.929114246
Short name T75
Test name
Test status
Simulation time 183571546145 ps
CPU time 295.3 seconds
Started Mar 21 12:50:38 PM PDT 24
Finished Mar 21 12:55:33 PM PDT 24
Peak memory 190828 kb
Host smart-838bbef3-1bf7-4f48-acec-c36f4b0b55b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929114246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
929114246
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.381520607
Short name T235
Test name
Test status
Simulation time 707456349073 ps
CPU time 432.13 seconds
Started Mar 21 12:50:37 PM PDT 24
Finished Mar 21 12:57:49 PM PDT 24
Peak memory 182588 kb
Host smart-e4b3f673-cf49-4cb0-aaa6-964c958015b8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381520607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.381520607
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.3965808744
Short name T367
Test name
Test status
Simulation time 167237462843 ps
CPU time 92.08 seconds
Started Mar 21 12:50:37 PM PDT 24
Finished Mar 21 12:52:09 PM PDT 24
Peak memory 182660 kb
Host smart-a7eb83f0-a3f4-46d9-a2de-d10ddb9f275d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965808744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3965808744
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.1481774331
Short name T445
Test name
Test status
Simulation time 166280348198 ps
CPU time 121.97 seconds
Started Mar 21 12:50:36 PM PDT 24
Finished Mar 21 12:52:38 PM PDT 24
Peak memory 190764 kb
Host smart-8095a97f-a93b-45c3-8856-e697743b721c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481774331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1481774331
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.3193967068
Short name T356
Test name
Test status
Simulation time 130692270218 ps
CPU time 57.09 seconds
Started Mar 21 12:50:36 PM PDT 24
Finished Mar 21 12:51:33 PM PDT 24
Peak memory 190792 kb
Host smart-b2a20611-4378-4f8c-9cfb-8b9c0d5c7453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193967068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3193967068
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3592587038
Short name T294
Test name
Test status
Simulation time 1489294152976 ps
CPU time 745.92 seconds
Started Mar 21 12:50:36 PM PDT 24
Finished Mar 21 01:03:02 PM PDT 24
Peak memory 182600 kb
Host smart-f0d92153-ff56-48bb-8087-f562cda0a160
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592587038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3592587038
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.3546762687
Short name T405
Test name
Test status
Simulation time 107399752524 ps
CPU time 178.46 seconds
Started Mar 21 12:50:36 PM PDT 24
Finished Mar 21 12:53:34 PM PDT 24
Peak memory 182632 kb
Host smart-f69530ae-d7b8-4205-a126-d945970553a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546762687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3546762687
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2226745887
Short name T404
Test name
Test status
Simulation time 8429996719 ps
CPU time 8.86 seconds
Started Mar 21 12:50:36 PM PDT 24
Finished Mar 21 12:50:45 PM PDT 24
Peak memory 182544 kb
Host smart-ec1f55c7-3e0c-4b65-b75a-dd45a8e1adb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226745887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2226745887
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.3943364141
Short name T43
Test name
Test status
Simulation time 87930491976 ps
CPU time 709.96 seconds
Started Mar 21 12:50:35 PM PDT 24
Finished Mar 21 01:02:25 PM PDT 24
Peak memory 207312 kb
Host smart-9773b4d6-b4f3-458e-8cfe-1bd3df140821
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943364141 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.3943364141
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1054790070
Short name T310
Test name
Test status
Simulation time 229912598943 ps
CPU time 361.89 seconds
Started Mar 21 12:50:39 PM PDT 24
Finished Mar 21 12:56:41 PM PDT 24
Peak memory 182588 kb
Host smart-fcc1bb42-6b3e-4ed7-ae4c-e284f0de93d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054790070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1054790070
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_random.1420725137
Short name T146
Test name
Test status
Simulation time 167565734651 ps
CPU time 738.93 seconds
Started Mar 21 12:50:36 PM PDT 24
Finished Mar 21 01:02:55 PM PDT 24
Peak memory 190752 kb
Host smart-f5d5baad-5c5f-4dac-9363-ba5c59093409
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420725137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1420725137
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2916717545
Short name T364
Test name
Test status
Simulation time 1311889661 ps
CPU time 2.68 seconds
Started Mar 21 12:50:45 PM PDT 24
Finished Mar 21 12:50:48 PM PDT 24
Peak memory 193744 kb
Host smart-8fca9c0d-aab3-44ff-8255-8596e97d50a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916717545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2916717545
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.953043538
Short name T289
Test name
Test status
Simulation time 3743831771094 ps
CPU time 2036.77 seconds
Started Mar 21 12:50:36 PM PDT 24
Finished Mar 21 01:24:33 PM PDT 24
Peak memory 190808 kb
Host smart-6c67f828-9f14-4706-adb1-cee16e7ea2c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953043538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
953043538
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1083661612
Short name T335
Test name
Test status
Simulation time 137138549527 ps
CPU time 41.33 seconds
Started Mar 21 12:50:37 PM PDT 24
Finished Mar 21 12:51:18 PM PDT 24
Peak memory 182580 kb
Host smart-e4482dc2-1201-4157-8cc3-3d7056cff2b6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083661612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1083661612
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.1110431335
Short name T415
Test name
Test status
Simulation time 186554969724 ps
CPU time 140.77 seconds
Started Mar 21 12:50:39 PM PDT 24
Finished Mar 21 12:52:59 PM PDT 24
Peak memory 182536 kb
Host smart-3f91f681-14e7-4d62-931b-a07f5aa8d7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110431335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1110431335
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.2921911503
Short name T174
Test name
Test status
Simulation time 67547496642 ps
CPU time 122.38 seconds
Started Mar 21 12:50:37 PM PDT 24
Finished Mar 21 12:52:40 PM PDT 24
Peak memory 190848 kb
Host smart-fe8b147d-1a1e-43c2-973d-b5bd2a9ba682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921911503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2921911503
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.504539779
Short name T257
Test name
Test status
Simulation time 149541878047 ps
CPU time 74.82 seconds
Started Mar 21 12:50:35 PM PDT 24
Finished Mar 21 12:51:50 PM PDT 24
Peak memory 190744 kb
Host smart-da7d61a4-b200-41bc-b6d3-2c44db3b1a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504539779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.504539779
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.3337546957
Short name T407
Test name
Test status
Simulation time 97596185 ps
CPU time 0.58 seconds
Started Mar 21 12:50:40 PM PDT 24
Finished Mar 21 12:50:40 PM PDT 24
Peak memory 182332 kb
Host smart-937059bf-c03f-4131-b035-e3c43a80c9b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337546957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.3337546957
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.896111220
Short name T308
Test name
Test status
Simulation time 219957095329 ps
CPU time 343.18 seconds
Started Mar 21 12:50:45 PM PDT 24
Finished Mar 21 12:56:28 PM PDT 24
Peak memory 182536 kb
Host smart-6058aabe-50e1-4c78-8188-11eb63da5f21
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896111220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.rv_timer_cfg_update_on_fly.896111220
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.4240684110
Short name T373
Test name
Test status
Simulation time 96179105682 ps
CPU time 131.88 seconds
Started Mar 21 12:50:38 PM PDT 24
Finished Mar 21 12:52:50 PM PDT 24
Peak memory 182520 kb
Host smart-3a713848-ce52-42e5-b860-a105042d0416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240684110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.4240684110
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.910974012
Short name T79
Test name
Test status
Simulation time 108992314880 ps
CPU time 92.42 seconds
Started Mar 21 12:50:37 PM PDT 24
Finished Mar 21 12:52:09 PM PDT 24
Peak memory 190824 kb
Host smart-78416607-9a24-45a3-aaf0-96d69eb3a62c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910974012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.910974012
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.814102375
Short name T444
Test name
Test status
Simulation time 21612427760 ps
CPU time 33.05 seconds
Started Mar 21 12:50:36 PM PDT 24
Finished Mar 21 12:51:09 PM PDT 24
Peak memory 182524 kb
Host smart-6f072cb7-e7ba-4843-9a4d-af9d3576dc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814102375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.814102375
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1804673597
Short name T290
Test name
Test status
Simulation time 176318982749 ps
CPU time 248.89 seconds
Started Mar 21 12:50:40 PM PDT 24
Finished Mar 21 12:54:49 PM PDT 24
Peak memory 195788 kb
Host smart-b07bc6b6-77ca-48f3-8935-f36ca83d6f11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804673597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1804673597
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.2489507909
Short name T15
Test name
Test status
Simulation time 31709357646 ps
CPU time 255.01 seconds
Started Mar 21 12:50:37 PM PDT 24
Finished Mar 21 12:54:52 PM PDT 24
Peak memory 205404 kb
Host smart-745de443-83c1-4f54-91ae-fd6cc981d70a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489507909 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.2489507909
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.479474099
Short name T156
Test name
Test status
Simulation time 919460845991 ps
CPU time 463.96 seconds
Started Mar 21 12:50:07 PM PDT 24
Finished Mar 21 12:57:52 PM PDT 24
Peak memory 182632 kb
Host smart-d7e7c284-9fff-454e-badc-cf2af644a193
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479474099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.479474099
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2178235610
Short name T375
Test name
Test status
Simulation time 92572108440 ps
CPU time 68.69 seconds
Started Mar 21 12:50:07 PM PDT 24
Finished Mar 21 12:51:17 PM PDT 24
Peak memory 182572 kb
Host smart-a1ed9553-d4c6-43d9-b639-8db7d514df7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178235610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2178235610
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.2502818148
Short name T443
Test name
Test status
Simulation time 134929717403 ps
CPU time 65.71 seconds
Started Mar 21 12:50:11 PM PDT 24
Finished Mar 21 12:51:17 PM PDT 24
Peak memory 182632 kb
Host smart-8dcf407e-c97c-4dd8-bf97-5e79a907c5b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502818148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.2502818148
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2478063948
Short name T362
Test name
Test status
Simulation time 31494000122 ps
CPU time 15.03 seconds
Started Mar 21 12:50:03 PM PDT 24
Finished Mar 21 12:50:19 PM PDT 24
Peak memory 194364 kb
Host smart-4ef563ab-523d-49c5-bf74-dfd8ba025064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478063948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2478063948
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.1115208763
Short name T18
Test name
Test status
Simulation time 94521788 ps
CPU time 0.89 seconds
Started Mar 21 12:50:07 PM PDT 24
Finished Mar 21 12:50:08 PM PDT 24
Peak memory 214172 kb
Host smart-855ca346-2e94-4668-802b-78aeacf376dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115208763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1115208763
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.1143118446
Short name T430
Test name
Test status
Simulation time 1190003259884 ps
CPU time 2436.49 seconds
Started Mar 21 12:50:03 PM PDT 24
Finished Mar 21 01:30:40 PM PDT 24
Peak memory 190808 kb
Host smart-147e8755-5bdf-4b61-bbe6-d3df81b8563a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143118446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
1143118446
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.509577017
Short name T244
Test name
Test status
Simulation time 145833161482 ps
CPU time 245.43 seconds
Started Mar 21 12:50:45 PM PDT 24
Finished Mar 21 12:54:51 PM PDT 24
Peak memory 182536 kb
Host smart-44c58a41-6054-42a7-aa89-9bc47ee5f7da
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509577017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.rv_timer_cfg_update_on_fly.509577017
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.925838387
Short name T451
Test name
Test status
Simulation time 729686270930 ps
CPU time 278.59 seconds
Started Mar 21 12:50:39 PM PDT 24
Finished Mar 21 12:55:17 PM PDT 24
Peak memory 182568 kb
Host smart-7cf7cc8c-4cec-46ca-aa7b-7afd18719fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925838387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.925838387
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2026885346
Short name T152
Test name
Test status
Simulation time 35392362290 ps
CPU time 54.3 seconds
Started Mar 21 12:50:39 PM PDT 24
Finished Mar 21 12:51:34 PM PDT 24
Peak memory 182380 kb
Host smart-f684a158-b809-4d53-8551-dbd8ac00c775
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026885346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2026885346
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.3674573075
Short name T77
Test name
Test status
Simulation time 980841035890 ps
CPU time 439.94 seconds
Started Mar 21 12:50:45 PM PDT 24
Finished Mar 21 12:58:05 PM PDT 24
Peak memory 190856 kb
Host smart-bb5568a2-6d4d-48c3-a783-a73265f6a1cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674573075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.3674573075
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.372652681
Short name T343
Test name
Test status
Simulation time 1005729165391 ps
CPU time 348.23 seconds
Started Mar 21 12:50:44 PM PDT 24
Finished Mar 21 12:56:33 PM PDT 24
Peak memory 182644 kb
Host smart-9cc87a24-dfc6-47dc-ba76-77b4dffaa582
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372652681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.rv_timer_cfg_update_on_fly.372652681
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.341513248
Short name T398
Test name
Test status
Simulation time 130693396948 ps
CPU time 54.56 seconds
Started Mar 21 12:50:46 PM PDT 24
Finished Mar 21 12:51:40 PM PDT 24
Peak memory 182612 kb
Host smart-ecd925a8-1bb0-4bc8-8a33-32f43d5b579e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341513248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.341513248
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.1319941813
Short name T164
Test name
Test status
Simulation time 90475570076 ps
CPU time 327.82 seconds
Started Mar 21 12:50:46 PM PDT 24
Finished Mar 21 12:56:14 PM PDT 24
Peak memory 190752 kb
Host smart-98b86e11-be5e-4ee7-9eef-441982220964
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319941813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1319941813
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2356848003
Short name T155
Test name
Test status
Simulation time 44644226751 ps
CPU time 81.06 seconds
Started Mar 21 12:50:44 PM PDT 24
Finished Mar 21 12:52:05 PM PDT 24
Peak memory 190768 kb
Host smart-c84274a4-5f3f-4902-842e-e3337b55de27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356848003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2356848003
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2483489457
Short name T148
Test name
Test status
Simulation time 1070757724390 ps
CPU time 561.4 seconds
Started Mar 21 12:50:44 PM PDT 24
Finished Mar 21 01:00:06 PM PDT 24
Peak memory 182556 kb
Host smart-6bc7db9b-e618-47ea-bd06-994895296008
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483489457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2483489457
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.28680919
Short name T402
Test name
Test status
Simulation time 606558527809 ps
CPU time 229.31 seconds
Started Mar 21 12:50:45 PM PDT 24
Finished Mar 21 12:54:35 PM PDT 24
Peak memory 182548 kb
Host smart-e230099e-8ea0-464a-a273-ad371672a02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28680919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.28680919
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1884936379
Short name T210
Test name
Test status
Simulation time 58624282871 ps
CPU time 305.34 seconds
Started Mar 21 12:50:45 PM PDT 24
Finished Mar 21 12:55:51 PM PDT 24
Peak memory 190808 kb
Host smart-640c1093-2d47-4d91-ad7b-af42e60c3276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884936379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1884936379
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.3646386730
Short name T380
Test name
Test status
Simulation time 623188797 ps
CPU time 1.97 seconds
Started Mar 21 12:50:46 PM PDT 24
Finished Mar 21 12:50:49 PM PDT 24
Peak memory 182532 kb
Host smart-426b4004-b7d1-4fc9-b824-204ad666a6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646386730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3646386730
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.3429125518
Short name T90
Test name
Test status
Simulation time 140958041665 ps
CPU time 642.8 seconds
Started Mar 21 12:50:45 PM PDT 24
Finished Mar 21 01:01:28 PM PDT 24
Peak memory 205420 kb
Host smart-b8c3eb58-638c-4f13-a93b-0796b01fa850
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429125518 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.3429125518
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3790249515
Short name T348
Test name
Test status
Simulation time 49877364680 ps
CPU time 44.54 seconds
Started Mar 21 12:50:46 PM PDT 24
Finished Mar 21 12:51:31 PM PDT 24
Peak memory 182552 kb
Host smart-56af04f1-4a9d-4c27-97da-036e970a2878
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790249515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.3790249515
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.2585699221
Short name T393
Test name
Test status
Simulation time 42194883623 ps
CPU time 22.37 seconds
Started Mar 21 12:50:43 PM PDT 24
Finished Mar 21 12:51:06 PM PDT 24
Peak memory 182568 kb
Host smart-518be80e-4c86-4f64-aec6-954de7cae08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585699221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2585699221
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1058190967
Short name T250
Test name
Test status
Simulation time 749535539296 ps
CPU time 1808.69 seconds
Started Mar 21 12:50:44 PM PDT 24
Finished Mar 21 01:20:53 PM PDT 24
Peak memory 190724 kb
Host smart-1f2dac8c-1434-45d8-948c-1e47e4e50897
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058190967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1058190967
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2779185663
Short name T366
Test name
Test status
Simulation time 869236293 ps
CPU time 1.63 seconds
Started Mar 21 12:50:46 PM PDT 24
Finished Mar 21 12:50:47 PM PDT 24
Peak memory 182288 kb
Host smart-eb9ba6ec-3da5-402f-a910-7c77f3e6e6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779185663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2779185663
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1218691281
Short name T302
Test name
Test status
Simulation time 65426061478 ps
CPU time 96.19 seconds
Started Mar 21 12:50:55 PM PDT 24
Finished Mar 21 12:52:31 PM PDT 24
Peak memory 182636 kb
Host smart-a469d9ff-5dcb-4252-b893-447da47f1a77
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218691281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.1218691281
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.1058710636
Short name T400
Test name
Test status
Simulation time 523627029415 ps
CPU time 237.22 seconds
Started Mar 21 12:50:56 PM PDT 24
Finished Mar 21 12:54:54 PM PDT 24
Peak memory 182608 kb
Host smart-f43960e6-d1a2-4a7f-8f9b-52e82234452d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058710636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1058710636
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.1877062793
Short name T370
Test name
Test status
Simulation time 693542643 ps
CPU time 1.32 seconds
Started Mar 21 12:50:55 PM PDT 24
Finished Mar 21 12:50:56 PM PDT 24
Peak memory 192448 kb
Host smart-b09aac4a-ef4b-4955-9336-7713a6d2b22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877062793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.1877062793
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.2099403258
Short name T72
Test name
Test status
Simulation time 127667861868 ps
CPU time 135.22 seconds
Started Mar 21 12:50:55 PM PDT 24
Finished Mar 21 12:53:10 PM PDT 24
Peak memory 182640 kb
Host smart-ea4d08a0-fb86-4d80-90aa-1449648843f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099403258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.2099403258
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1864877971
Short name T116
Test name
Test status
Simulation time 190593514928 ps
CPU time 339.16 seconds
Started Mar 21 12:50:57 PM PDT 24
Finished Mar 21 12:56:36 PM PDT 24
Peak memory 182628 kb
Host smart-f30f41f2-5deb-43bf-ab0b-708161d12d44
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864877971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1864877971
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1127585249
Short name T44
Test name
Test status
Simulation time 185873954574 ps
CPU time 244.1 seconds
Started Mar 21 12:50:53 PM PDT 24
Finished Mar 21 12:54:57 PM PDT 24
Peak memory 182520 kb
Host smart-9b53ec6f-bc07-45b0-b445-86556f48ad4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127585249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1127585249
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.401271651
Short name T166
Test name
Test status
Simulation time 2491663923065 ps
CPU time 870.63 seconds
Started Mar 21 12:50:55 PM PDT 24
Finished Mar 21 01:05:25 PM PDT 24
Peak memory 190828 kb
Host smart-ca586dbd-7e84-40d6-bdd2-60699592d057
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401271651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.401271651
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1156588796
Short name T338
Test name
Test status
Simulation time 159112278179 ps
CPU time 97.67 seconds
Started Mar 21 12:50:57 PM PDT 24
Finished Mar 21 12:52:34 PM PDT 24
Peak memory 190796 kb
Host smart-df0c0ca4-b411-43c1-9186-3c19b99c772b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156588796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1156588796
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1313224154
Short name T391
Test name
Test status
Simulation time 21232572 ps
CPU time 0.56 seconds
Started Mar 21 12:50:56 PM PDT 24
Finished Mar 21 12:50:56 PM PDT 24
Peak memory 182308 kb
Host smart-d60bc076-515d-494f-bca0-1418af603c1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313224154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1313224154
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1169964569
Short name T284
Test name
Test status
Simulation time 1111385815400 ps
CPU time 647.94 seconds
Started Mar 21 12:50:58 PM PDT 24
Finished Mar 21 01:01:46 PM PDT 24
Peak memory 182528 kb
Host smart-9bd96103-7224-4adc-a7a2-00a814925e84
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169964569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1169964569
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1209094057
Short name T410
Test name
Test status
Simulation time 112591981360 ps
CPU time 158.94 seconds
Started Mar 21 12:50:57 PM PDT 24
Finished Mar 21 12:53:36 PM PDT 24
Peak memory 182536 kb
Host smart-4305bc3f-80d2-4e1b-b3ba-aee4815b0859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209094057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1209094057
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.1603622879
Short name T349
Test name
Test status
Simulation time 383278711211 ps
CPU time 414.49 seconds
Started Mar 21 12:50:56 PM PDT 24
Finished Mar 21 12:57:50 PM PDT 24
Peak memory 190764 kb
Host smart-9c4ad0a1-f375-496a-a76e-b440e08149ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603622879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1603622879
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.1756355631
Short name T258
Test name
Test status
Simulation time 64712661856 ps
CPU time 120.26 seconds
Started Mar 21 12:50:55 PM PDT 24
Finished Mar 21 12:52:55 PM PDT 24
Peak memory 193700 kb
Host smart-016c2251-c15c-45e4-8c1a-7cd52e6fa8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756355631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.1756355631
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.532698799
Short name T78
Test name
Test status
Simulation time 240374610406 ps
CPU time 356.45 seconds
Started Mar 21 12:50:57 PM PDT 24
Finished Mar 21 12:56:53 PM PDT 24
Peak memory 190744 kb
Host smart-6f6fb504-4ffb-499b-889a-4d7a45efa053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532698799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.
532698799
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2813707532
Short name T395
Test name
Test status
Simulation time 124868522267 ps
CPU time 196.49 seconds
Started Mar 21 12:50:53 PM PDT 24
Finished Mar 21 12:54:10 PM PDT 24
Peak memory 182568 kb
Host smart-7beeff6d-7d14-4919-b798-a22e0cba0fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813707532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2813707532
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.3532469862
Short name T228
Test name
Test status
Simulation time 59657099453 ps
CPU time 425.66 seconds
Started Mar 21 12:50:56 PM PDT 24
Finished Mar 21 12:58:02 PM PDT 24
Peak memory 194336 kb
Host smart-6d210b86-5766-495d-b43d-f612b1bbee80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532469862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3532469862
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.600245074
Short name T158
Test name
Test status
Simulation time 42000434276 ps
CPU time 46.63 seconds
Started Mar 21 12:50:53 PM PDT 24
Finished Mar 21 12:51:40 PM PDT 24
Peak memory 182612 kb
Host smart-6e3a487b-091f-4803-98a8-4ba7870f3fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600245074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.600245074
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.2743936256
Short name T41
Test name
Test status
Simulation time 222960708319 ps
CPU time 1147.71 seconds
Started Mar 21 12:50:54 PM PDT 24
Finished Mar 21 01:10:02 PM PDT 24
Peak memory 213604 kb
Host smart-6beefb52-1169-4676-aad3-e8f255329043
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743936256 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.2743936256
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1767393888
Short name T246
Test name
Test status
Simulation time 84083980101 ps
CPU time 134.32 seconds
Started Mar 21 12:50:55 PM PDT 24
Finished Mar 21 12:53:09 PM PDT 24
Peak memory 182584 kb
Host smart-c311de6e-84a9-42cc-b120-e467dcd5d4e7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767393888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1767393888
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2134300298
Short name T399
Test name
Test status
Simulation time 176918837774 ps
CPU time 125.75 seconds
Started Mar 21 12:50:56 PM PDT 24
Finished Mar 21 12:53:02 PM PDT 24
Peak memory 182636 kb
Host smart-3de8a137-2258-4dc1-93de-2db0f19f4b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134300298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2134300298
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.848287489
Short name T420
Test name
Test status
Simulation time 95132583398 ps
CPU time 172.05 seconds
Started Mar 21 12:50:53 PM PDT 24
Finished Mar 21 12:53:46 PM PDT 24
Peak memory 190768 kb
Host smart-dfdd2f22-e83f-4cff-a827-3a4267d5ef4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848287489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.848287489
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2579853352
Short name T11
Test name
Test status
Simulation time 127590897 ps
CPU time 0.76 seconds
Started Mar 21 12:50:56 PM PDT 24
Finished Mar 21 12:50:57 PM PDT 24
Peak memory 182380 kb
Host smart-d478caee-1b18-4b7f-97f8-66a24a28e8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579853352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2579853352
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.2945503997
Short name T412
Test name
Test status
Simulation time 4910797345115 ps
CPU time 771.68 seconds
Started Mar 21 12:51:04 PM PDT 24
Finished Mar 21 01:03:55 PM PDT 24
Peak memory 194916 kb
Host smart-415c5088-988e-4cf2-80c4-733465a27fad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945503997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.2945503997
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3890528905
Short name T231
Test name
Test status
Simulation time 34985806002 ps
CPU time 27.6 seconds
Started Mar 21 12:51:02 PM PDT 24
Finished Mar 21 12:51:29 PM PDT 24
Peak memory 182624 kb
Host smart-7052236a-7082-4a1f-9bc1-ea9bf6268a32
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890528905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3890528905
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.705878246
Short name T374
Test name
Test status
Simulation time 530399999067 ps
CPU time 218.88 seconds
Started Mar 21 12:51:03 PM PDT 24
Finished Mar 21 12:54:42 PM PDT 24
Peak memory 182568 kb
Host smart-35059289-1541-446d-8aed-e00a080a7b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705878246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.705878246
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.2080498073
Short name T272
Test name
Test status
Simulation time 1565660198576 ps
CPU time 756.7 seconds
Started Mar 21 12:51:05 PM PDT 24
Finished Mar 21 01:03:42 PM PDT 24
Peak memory 190732 kb
Host smart-3e80097b-dbf0-4c11-9f39-f84ca77c9c45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080498073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2080498073
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.839448848
Short name T377
Test name
Test status
Simulation time 430641767 ps
CPU time 0.85 seconds
Started Mar 21 12:51:04 PM PDT 24
Finished Mar 21 12:51:05 PM PDT 24
Peak memory 182320 kb
Host smart-4a993b56-15cb-48ca-8938-7f8c71f1e5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839448848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.839448848
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3656509371
Short name T352
Test name
Test status
Simulation time 67743294102 ps
CPU time 29.2 seconds
Started Mar 21 12:50:17 PM PDT 24
Finished Mar 21 12:50:47 PM PDT 24
Peak memory 182584 kb
Host smart-7888b227-f1b6-45ec-ba74-6ca8cbd8ec6b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656509371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3656509371
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3888455020
Short name T435
Test name
Test status
Simulation time 134359883270 ps
CPU time 112.07 seconds
Started Mar 21 12:50:17 PM PDT 24
Finished Mar 21 12:52:12 PM PDT 24
Peak memory 182612 kb
Host smart-153b6103-2a5c-4251-a1bf-34f4d069fdbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888455020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3888455020
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.3303249094
Short name T259
Test name
Test status
Simulation time 145556823913 ps
CPU time 155.26 seconds
Started Mar 21 12:50:04 PM PDT 24
Finished Mar 21 12:52:40 PM PDT 24
Peak memory 182532 kb
Host smart-ee9f37be-8044-414c-9a46-5cc7e0475800
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303249094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3303249094
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1417047759
Short name T2
Test name
Test status
Simulation time 229271645890 ps
CPU time 121.09 seconds
Started Mar 21 12:50:17 PM PDT 24
Finished Mar 21 12:52:21 PM PDT 24
Peak memory 190708 kb
Host smart-e6f42ff9-6791-4b33-b331-c6511a65abf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417047759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1417047759
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2081154759
Short name T16
Test name
Test status
Simulation time 87926183 ps
CPU time 0.91 seconds
Started Mar 21 12:50:16 PM PDT 24
Finished Mar 21 12:50:17 PM PDT 24
Peak memory 214188 kb
Host smart-dff2e3f6-1492-4a68-a61d-f3cf69d8953a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081154759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2081154759
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1919620391
Short name T63
Test name
Test status
Simulation time 66962221126 ps
CPU time 102.3 seconds
Started Mar 21 12:50:21 PM PDT 24
Finished Mar 21 12:52:03 PM PDT 24
Peak memory 190728 kb
Host smart-3d44ff8d-597d-4117-9dbd-d4eb02ec249b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919620391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1919620391
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.171823605
Short name T283
Test name
Test status
Simulation time 36324430491 ps
CPU time 18.15 seconds
Started Mar 21 12:51:09 PM PDT 24
Finished Mar 21 12:51:27 PM PDT 24
Peak memory 182496 kb
Host smart-fad1b402-3333-4f06-8679-a926bab8b750
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171823605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.rv_timer_cfg_update_on_fly.171823605
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.1845569540
Short name T388
Test name
Test status
Simulation time 119915700184 ps
CPU time 170.75 seconds
Started Mar 21 12:51:03 PM PDT 24
Finished Mar 21 12:53:54 PM PDT 24
Peak memory 182528 kb
Host smart-855dd910-215f-44d7-91c8-9db119241311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845569540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1845569540
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3986912912
Short name T88
Test name
Test status
Simulation time 167108948022 ps
CPU time 376.27 seconds
Started Mar 21 12:51:01 PM PDT 24
Finished Mar 21 12:57:17 PM PDT 24
Peak memory 190732 kb
Host smart-5317c3e4-3a76-4ca9-9430-37da1160b4a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986912912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3986912912
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.622672338
Short name T136
Test name
Test status
Simulation time 299878714578 ps
CPU time 1178.64 seconds
Started Mar 21 12:51:02 PM PDT 24
Finished Mar 21 01:10:41 PM PDT 24
Peak memory 190740 kb
Host smart-0085e6e7-c6af-49e9-829b-ca8f3ac5d494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622672338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.622672338
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2511541121
Short name T423
Test name
Test status
Simulation time 143428888221 ps
CPU time 232.25 seconds
Started Mar 21 12:51:02 PM PDT 24
Finished Mar 21 12:54:54 PM PDT 24
Peak memory 190684 kb
Host smart-119545f8-c2a3-40d6-8bd4-a1eb820729fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511541121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2511541121
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.1207509100
Short name T37
Test name
Test status
Simulation time 176269179270 ps
CPU time 648.51 seconds
Started Mar 21 12:51:03 PM PDT 24
Finished Mar 21 01:01:52 PM PDT 24
Peak memory 206684 kb
Host smart-1ecc9d9e-0f25-426d-a14c-6a62d82b3326
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207509100 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.1207509100
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1067804141
Short name T7
Test name
Test status
Simulation time 1712659544137 ps
CPU time 473.27 seconds
Started Mar 21 12:51:14 PM PDT 24
Finished Mar 21 12:59:08 PM PDT 24
Peak memory 182556 kb
Host smart-c226ceac-8610-4bd1-b1ab-abadfba588af
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067804141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1067804141
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3040653517
Short name T120
Test name
Test status
Simulation time 817466897873 ps
CPU time 331.78 seconds
Started Mar 21 12:51:04 PM PDT 24
Finished Mar 21 12:56:36 PM PDT 24
Peak memory 182556 kb
Host smart-9870ffad-812a-4b38-b2f8-db9aa515ac75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040653517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3040653517
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.1836664937
Short name T369
Test name
Test status
Simulation time 13073600567 ps
CPU time 57.68 seconds
Started Mar 21 12:51:10 PM PDT 24
Finished Mar 21 12:52:08 PM PDT 24
Peak memory 182556 kb
Host smart-4bee85ad-c4fd-4926-81cd-8678ad3b6c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836664937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1836664937
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.1281177184
Short name T194
Test name
Test status
Simulation time 134561338570 ps
CPU time 332.28 seconds
Started Mar 21 12:51:11 PM PDT 24
Finished Mar 21 12:56:44 PM PDT 24
Peak memory 190808 kb
Host smart-cecb9d04-e1b3-4926-b7b7-029f60035745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281177184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.1281177184
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1728634966
Short name T306
Test name
Test status
Simulation time 118280123277 ps
CPU time 28.22 seconds
Started Mar 21 12:51:10 PM PDT 24
Finished Mar 21 12:51:39 PM PDT 24
Peak memory 182576 kb
Host smart-3cb504d8-41f4-4079-962e-35263b0e803e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728634966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1728634966
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2784633703
Short name T418
Test name
Test status
Simulation time 460963525107 ps
CPU time 184.03 seconds
Started Mar 21 12:51:11 PM PDT 24
Finished Mar 21 12:54:15 PM PDT 24
Peak memory 182528 kb
Host smart-cc9eaee1-3bf4-41ce-b7ec-2ec1403732e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784633703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2784633703
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.1709739889
Short name T241
Test name
Test status
Simulation time 248302538141 ps
CPU time 226.88 seconds
Started Mar 21 12:51:14 PM PDT 24
Finished Mar 21 12:55:01 PM PDT 24
Peak memory 190768 kb
Host smart-caee7c7e-c900-4cd2-aa06-6bde6a4b5cbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709739889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1709739889
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2415383152
Short name T224
Test name
Test status
Simulation time 13649934097 ps
CPU time 24.12 seconds
Started Mar 21 12:51:14 PM PDT 24
Finished Mar 21 12:51:39 PM PDT 24
Peak memory 182512 kb
Host smart-bd952d1b-2fac-48e2-9982-b671345d13be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415383152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2415383152
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1572423917
Short name T379
Test name
Test status
Simulation time 641511488088 ps
CPU time 244.91 seconds
Started Mar 21 12:51:14 PM PDT 24
Finished Mar 21 12:55:19 PM PDT 24
Peak memory 182564 kb
Host smart-98e29815-83a3-4e0b-8cd7-9ab18852df5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572423917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1572423917
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.4116159301
Short name T42
Test name
Test status
Simulation time 21235064283 ps
CPU time 227.32 seconds
Started Mar 21 12:51:09 PM PDT 24
Finished Mar 21 12:54:56 PM PDT 24
Peak memory 197216 kb
Host smart-ed451fe3-ac20-4da3-9c42-44c05491c8b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116159301 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.4116159301
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2942878386
Short name T150
Test name
Test status
Simulation time 1271340351416 ps
CPU time 712.91 seconds
Started Mar 21 12:51:20 PM PDT 24
Finished Mar 21 01:03:14 PM PDT 24
Peak memory 182524 kb
Host smart-426a6dec-49e1-4779-813e-b97044dd466d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942878386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2942878386
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.2157266114
Short name T401
Test name
Test status
Simulation time 167691967535 ps
CPU time 115.09 seconds
Started Mar 21 12:51:14 PM PDT 24
Finished Mar 21 12:53:10 PM PDT 24
Peak memory 182540 kb
Host smart-f8f3f8fb-faf3-407d-8c11-7ccd498e30eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157266114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2157266114
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.2878178292
Short name T21
Test name
Test status
Simulation time 115415987501 ps
CPU time 206.02 seconds
Started Mar 21 12:51:12 PM PDT 24
Finished Mar 21 12:54:39 PM PDT 24
Peak memory 190824 kb
Host smart-b755e717-ab29-43c3-bad0-9a188c1ff280
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878178292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2878178292
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.2980718067
Short name T301
Test name
Test status
Simulation time 206056970484 ps
CPU time 86.35 seconds
Started Mar 21 12:51:20 PM PDT 24
Finished Mar 21 12:52:47 PM PDT 24
Peak memory 190816 kb
Host smart-9fa27852-3bc4-4a47-8433-2570efd7e8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980718067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2980718067
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.3112672857
Short name T23
Test name
Test status
Simulation time 452613560212 ps
CPU time 216.14 seconds
Started Mar 21 12:51:21 PM PDT 24
Finished Mar 21 12:54:57 PM PDT 24
Peak memory 194180 kb
Host smart-1908888f-02df-4906-836f-1ec20e131bdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112672857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.3112672857
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3382929442
Short name T345
Test name
Test status
Simulation time 155331213797 ps
CPU time 274.92 seconds
Started Mar 21 12:51:19 PM PDT 24
Finished Mar 21 12:55:54 PM PDT 24
Peak memory 182568 kb
Host smart-314dfe61-7424-4da6-b6a4-0819698b826e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382929442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3382929442
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3736500817
Short name T381
Test name
Test status
Simulation time 292387179828 ps
CPU time 72.01 seconds
Started Mar 21 12:51:20 PM PDT 24
Finished Mar 21 12:52:32 PM PDT 24
Peak memory 182508 kb
Host smart-ce2991c9-6477-456f-bcb1-1e2d051dad7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736500817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3736500817
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.795185943
Short name T202
Test name
Test status
Simulation time 209576641916 ps
CPU time 120.74 seconds
Started Mar 21 12:51:19 PM PDT 24
Finished Mar 21 12:53:20 PM PDT 24
Peak memory 190824 kb
Host smart-40a4976d-649f-45c7-b012-8b8c44ba09f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795185943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.795185943
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.959157917
Short name T139
Test name
Test status
Simulation time 515898446017 ps
CPU time 817.46 seconds
Started Mar 21 12:51:20 PM PDT 24
Finished Mar 21 01:04:58 PM PDT 24
Peak memory 190756 kb
Host smart-35545831-8755-46cf-9c1f-dad514d78a46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959157917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
959157917
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.400341682
Short name T38
Test name
Test status
Simulation time 73724351310 ps
CPU time 567.32 seconds
Started Mar 21 12:51:20 PM PDT 24
Finished Mar 21 01:00:47 PM PDT 24
Peak memory 205796 kb
Host smart-7e44e2d9-bd4d-437b-9350-2d2cdd8a01e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400341682 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.400341682
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1809047166
Short name T171
Test name
Test status
Simulation time 186022601721 ps
CPU time 290.04 seconds
Started Mar 21 12:51:20 PM PDT 24
Finished Mar 21 12:56:10 PM PDT 24
Peak memory 182576 kb
Host smart-35dc0f24-a03a-4472-a7fb-a8ed08f03e01
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809047166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1809047166
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2538441238
Short name T413
Test name
Test status
Simulation time 484661934588 ps
CPU time 192.61 seconds
Started Mar 21 12:51:20 PM PDT 24
Finished Mar 21 12:54:33 PM PDT 24
Peak memory 182620 kb
Host smart-04c1b63d-2e1a-4984-99e5-2c559ded8ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538441238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2538441238
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.3844775319
Short name T143
Test name
Test status
Simulation time 154984643908 ps
CPU time 761.6 seconds
Started Mar 21 12:51:21 PM PDT 24
Finished Mar 21 01:04:03 PM PDT 24
Peak memory 190828 kb
Host smart-34456d48-768c-42af-8409-326db4ae09c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844775319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3844775319
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3283822677
Short name T441
Test name
Test status
Simulation time 75592913 ps
CPU time 0.55 seconds
Started Mar 21 12:51:30 PM PDT 24
Finished Mar 21 12:51:31 PM PDT 24
Peak memory 182344 kb
Host smart-26c40b4e-f3d8-4945-96a6-3695f911492f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283822677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3283822677
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2721644580
Short name T35
Test name
Test status
Simulation time 22460126 ps
CPU time 0.63 seconds
Started Mar 21 12:51:31 PM PDT 24
Finished Mar 21 12:51:32 PM PDT 24
Peak memory 182296 kb
Host smart-c9ca6e30-abfb-4fae-8783-1d18f391a139
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721644580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2721644580
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.905217975
Short name T357
Test name
Test status
Simulation time 586298160769 ps
CPU time 320.4 seconds
Started Mar 21 12:51:29 PM PDT 24
Finished Mar 21 12:56:49 PM PDT 24
Peak memory 182580 kb
Host smart-d05c57bb-a23c-4871-ad2b-d40c0fb3b784
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905217975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.905217975
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.4013995448
Short name T390
Test name
Test status
Simulation time 157598730733 ps
CPU time 125.73 seconds
Started Mar 21 12:51:29 PM PDT 24
Finished Mar 21 12:53:35 PM PDT 24
Peak memory 182532 kb
Host smart-1ba11941-a86b-4b82-8306-6c9b6d3dc5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013995448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.4013995448
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.3658466504
Short name T83
Test name
Test status
Simulation time 639734921172 ps
CPU time 162.05 seconds
Started Mar 21 12:51:30 PM PDT 24
Finished Mar 21 12:54:12 PM PDT 24
Peak memory 190796 kb
Host smart-79bdb8dc-f42b-4fb4-b129-f2bc073ada8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658466504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3658466504
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3217531651
Short name T29
Test name
Test status
Simulation time 99296907662 ps
CPU time 84.63 seconds
Started Mar 21 12:51:29 PM PDT 24
Finished Mar 21 12:52:54 PM PDT 24
Peak memory 190744 kb
Host smart-97953000-f296-4de5-8af9-888430414d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217531651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3217531651
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.3725455496
Short name T39
Test name
Test status
Simulation time 220946327833 ps
CPU time 434.86 seconds
Started Mar 21 12:51:29 PM PDT 24
Finished Mar 21 12:58:44 PM PDT 24
Peak memory 209060 kb
Host smart-f4ea9596-2255-4bff-ae18-c5b437a3e331
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725455496 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.3725455496
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1962787452
Short name T209
Test name
Test status
Simulation time 479352532516 ps
CPU time 275.71 seconds
Started Mar 21 12:51:40 PM PDT 24
Finished Mar 21 12:56:16 PM PDT 24
Peak memory 182588 kb
Host smart-ac3a4b50-e005-408c-a612-8589ea1f9b08
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962787452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1962787452
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.3459607397
Short name T66
Test name
Test status
Simulation time 54765814556 ps
CPU time 76.27 seconds
Started Mar 21 12:51:27 PM PDT 24
Finished Mar 21 12:52:44 PM PDT 24
Peak memory 182568 kb
Host smart-ad008ad1-8242-4beb-93f7-d7f0a49c6cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459607397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3459607397
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.2452886975
Short name T201
Test name
Test status
Simulation time 337739228471 ps
CPU time 227.46 seconds
Started Mar 21 12:51:29 PM PDT 24
Finished Mar 21 12:55:16 PM PDT 24
Peak memory 190756 kb
Host smart-ff345626-cc02-4790-a221-ed73cc6087a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452886975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2452886975
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.892559415
Short name T263
Test name
Test status
Simulation time 498356144693 ps
CPU time 95.19 seconds
Started Mar 21 12:51:41 PM PDT 24
Finished Mar 21 12:53:17 PM PDT 24
Peak memory 182648 kb
Host smart-3f708c07-af36-43f4-be37-e18bd9e4d838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892559415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.892559415
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.988149405
Short name T449
Test name
Test status
Simulation time 2983996563206 ps
CPU time 613.44 seconds
Started Mar 21 12:51:40 PM PDT 24
Finished Mar 21 01:01:54 PM PDT 24
Peak memory 190820 kb
Host smart-8c054aff-3af9-4701-ab35-b47555974b41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988149405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
988149405
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.365268893
Short name T417
Test name
Test status
Simulation time 114467338260 ps
CPU time 212.95 seconds
Started Mar 21 12:51:41 PM PDT 24
Finished Mar 21 12:55:14 PM PDT 24
Peak memory 182616 kb
Host smart-94340395-0a14-4c50-82fa-14b6d1d40da8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365268893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.365268893
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_random.1065114741
Short name T229
Test name
Test status
Simulation time 39742893524 ps
CPU time 17.83 seconds
Started Mar 21 12:51:39 PM PDT 24
Finished Mar 21 12:51:57 PM PDT 24
Peak memory 182560 kb
Host smart-7982a94d-b2b1-40a7-9fcb-9ab248481089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065114741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1065114741
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.258965270
Short name T315
Test name
Test status
Simulation time 189397094271 ps
CPU time 94.23 seconds
Started Mar 21 12:51:40 PM PDT 24
Finished Mar 21 12:53:14 PM PDT 24
Peak memory 194224 kb
Host smart-547bd825-e3cf-4aa0-a49a-632a4ddd5387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258965270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.258965270
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3059559962
Short name T442
Test name
Test status
Simulation time 1047359417847 ps
CPU time 2030.79 seconds
Started Mar 21 12:51:40 PM PDT 24
Finished Mar 21 01:25:31 PM PDT 24
Peak memory 190764 kb
Host smart-184bb769-fc8c-4d75-b786-fe31e8a4f7ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059559962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3059559962
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1096855118
Short name T157
Test name
Test status
Simulation time 291832116191 ps
CPU time 535.86 seconds
Started Mar 21 12:51:40 PM PDT 24
Finished Mar 21 01:00:36 PM PDT 24
Peak memory 182652 kb
Host smart-8f0a51bb-d7eb-40f9-8c52-88dca4cc841c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096855118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.1096855118
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.2165843590
Short name T389
Test name
Test status
Simulation time 305050664633 ps
CPU time 127.62 seconds
Started Mar 21 12:51:43 PM PDT 24
Finished Mar 21 12:53:52 PM PDT 24
Peak memory 182560 kb
Host smart-c70cee08-1e37-4e3f-8d41-dd5f5701848c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165843590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.2165843590
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.1708146509
Short name T186
Test name
Test status
Simulation time 178285548068 ps
CPU time 790.82 seconds
Started Mar 21 12:51:40 PM PDT 24
Finished Mar 21 01:04:51 PM PDT 24
Peak memory 190820 kb
Host smart-07f31406-b329-4d2d-a7fe-4a7cb94bae50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708146509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1708146509
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.4267880060
Short name T245
Test name
Test status
Simulation time 1346680424118 ps
CPU time 732.86 seconds
Started Mar 21 12:50:21 PM PDT 24
Finished Mar 21 01:02:34 PM PDT 24
Peak memory 182644 kb
Host smart-002ffd0a-864a-4f20-907e-6943ba6cfb5e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267880060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.4267880060
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3083591604
Short name T448
Test name
Test status
Simulation time 32315480638 ps
CPU time 22.86 seconds
Started Mar 21 12:50:15 PM PDT 24
Finished Mar 21 12:50:39 PM PDT 24
Peak memory 182524 kb
Host smart-a7a20e72-b5f7-49e9-a8cd-c69fbd875117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083591604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3083591604
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2450413597
Short name T376
Test name
Test status
Simulation time 252130676 ps
CPU time 0.88 seconds
Started Mar 21 12:50:19 PM PDT 24
Finished Mar 21 12:50:21 PM PDT 24
Peak memory 182012 kb
Host smart-eb2128d3-3c8f-424f-aa45-0df0ebbe037c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450413597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2450413597
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.2001023227
Short name T426
Test name
Test status
Simulation time 517331339594 ps
CPU time 202.37 seconds
Started Mar 21 12:50:16 PM PDT 24
Finished Mar 21 12:53:39 PM PDT 24
Peak memory 194196 kb
Host smart-0de33fca-b8a8-4107-afa3-b8b0adb516ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001023227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
2001023227
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.3569880467
Short name T8
Test name
Test status
Simulation time 68485671045 ps
CPU time 63.03 seconds
Started Mar 21 12:51:38 PM PDT 24
Finished Mar 21 12:52:41 PM PDT 24
Peak memory 182532 kb
Host smart-32d10d6d-564b-4d75-99ea-5a9b05755cd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569880467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3569880467
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.783053068
Short name T261
Test name
Test status
Simulation time 45893513542 ps
CPU time 104.01 seconds
Started Mar 21 12:51:40 PM PDT 24
Finished Mar 21 12:53:24 PM PDT 24
Peak memory 190756 kb
Host smart-8ac62a7d-9034-4a3b-a9fb-6d333bf9e35d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783053068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.783053068
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.825609746
Short name T329
Test name
Test status
Simulation time 18120618210 ps
CPU time 29.7 seconds
Started Mar 21 12:51:39 PM PDT 24
Finished Mar 21 12:52:09 PM PDT 24
Peak memory 182556 kb
Host smart-996edf01-06e4-4ce5-84b1-fd24c229c2d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825609746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.825609746
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1004704894
Short name T243
Test name
Test status
Simulation time 78828577229 ps
CPU time 700.23 seconds
Started Mar 21 12:51:49 PM PDT 24
Finished Mar 21 01:03:30 PM PDT 24
Peak memory 190764 kb
Host smart-67c25c73-07c1-4d25-bcd6-701b62c6ed75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004704894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1004704894
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.1499666545
Short name T409
Test name
Test status
Simulation time 54530642643 ps
CPU time 170.71 seconds
Started Mar 21 12:51:50 PM PDT 24
Finished Mar 21 12:54:42 PM PDT 24
Peak memory 190768 kb
Host smart-bdf183bb-d239-4fa1-a5b4-22ede1e18382
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499666545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1499666545
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.78625314
Short name T326
Test name
Test status
Simulation time 124207522841 ps
CPU time 231.85 seconds
Started Mar 21 12:51:49 PM PDT 24
Finished Mar 21 12:55:42 PM PDT 24
Peak memory 190780 kb
Host smart-a50e8a55-3176-4dfe-ab02-84b5b2fede5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78625314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.78625314
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.251481678
Short name T217
Test name
Test status
Simulation time 76459327681 ps
CPU time 130.45 seconds
Started Mar 21 12:51:50 PM PDT 24
Finished Mar 21 12:54:02 PM PDT 24
Peak memory 194392 kb
Host smart-86cec559-f802-4260-8bac-9bcfff4f128a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251481678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.251481678
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3799892042
Short name T135
Test name
Test status
Simulation time 372498261477 ps
CPU time 305.98 seconds
Started Mar 21 12:51:51 PM PDT 24
Finished Mar 21 12:56:58 PM PDT 24
Peak memory 193048 kb
Host smart-65d18d8a-2c29-4de4-b490-d4163a7bd570
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799892042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3799892042
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.965069556
Short name T291
Test name
Test status
Simulation time 22030076150 ps
CPU time 45.79 seconds
Started Mar 21 12:51:51 PM PDT 24
Finished Mar 21 12:52:38 PM PDT 24
Peak memory 182488 kb
Host smart-84ee6c16-6755-4589-a555-4d8a56293ece
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965069556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.965069556
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.2307449218
Short name T394
Test name
Test status
Simulation time 92683033332 ps
CPU time 154.28 seconds
Started Mar 21 12:50:17 PM PDT 24
Finished Mar 21 12:52:52 PM PDT 24
Peak memory 182184 kb
Host smart-55e3e51d-5167-4e73-85c0-5130161b0555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307449218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2307449218
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2622043865
Short name T411
Test name
Test status
Simulation time 279258494 ps
CPU time 0.85 seconds
Started Mar 21 12:50:23 PM PDT 24
Finished Mar 21 12:50:24 PM PDT 24
Peak memory 191012 kb
Host smart-116ded5a-d942-45f1-a309-0bd03b4a62b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622043865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2622043865
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3352428640
Short name T438
Test name
Test status
Simulation time 25643838406 ps
CPU time 41.82 seconds
Started Mar 21 12:50:20 PM PDT 24
Finished Mar 21 12:51:02 PM PDT 24
Peak memory 194280 kb
Host smart-47e8bca2-6b3e-4a37-8da6-d69238bde888
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352428640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3352428640
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/61.rv_timer_random.915929551
Short name T173
Test name
Test status
Simulation time 219427102865 ps
CPU time 310.5 seconds
Started Mar 21 12:51:50 PM PDT 24
Finished Mar 21 12:57:02 PM PDT 24
Peak memory 194344 kb
Host smart-439e45cc-2d44-48bc-85e1-867915c31eb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915929551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.915929551
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.2709966020
Short name T184
Test name
Test status
Simulation time 234191703868 ps
CPU time 706.09 seconds
Started Mar 21 12:51:52 PM PDT 24
Finished Mar 21 01:03:39 PM PDT 24
Peak memory 193876 kb
Host smart-b190ee8d-7e18-4d7d-8b05-e4b7618d658d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709966020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2709966020
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2644692031
Short name T299
Test name
Test status
Simulation time 43504377727 ps
CPU time 82.66 seconds
Started Mar 21 12:51:51 PM PDT 24
Finished Mar 21 12:53:15 PM PDT 24
Peak memory 182544 kb
Host smart-3b0d9acf-1f77-4441-a064-1c185995f71a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644692031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2644692031
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.290006851
Short name T295
Test name
Test status
Simulation time 46871653179 ps
CPU time 21.58 seconds
Started Mar 21 12:51:53 PM PDT 24
Finished Mar 21 12:52:15 PM PDT 24
Peak memory 182556 kb
Host smart-653a9442-d8e4-477f-9536-54ea119fdafc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290006851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.290006851
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.1033985652
Short name T363
Test name
Test status
Simulation time 77834350841 ps
CPU time 863.76 seconds
Started Mar 21 12:51:52 PM PDT 24
Finished Mar 21 01:06:17 PM PDT 24
Peak memory 190772 kb
Host smart-8da6a76a-15d0-4fb8-8e44-dbdc8a1ec342
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033985652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1033985652
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.527656833
Short name T191
Test name
Test status
Simulation time 69302360644 ps
CPU time 104.86 seconds
Started Mar 21 12:50:18 PM PDT 24
Finished Mar 21 12:52:04 PM PDT 24
Peak memory 182664 kb
Host smart-a6500952-a6db-4dc9-9e32-6d34d468b62a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527656833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.rv_timer_cfg_update_on_fly.527656833
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.305925918
Short name T371
Test name
Test status
Simulation time 257031031744 ps
CPU time 361.81 seconds
Started Mar 21 12:50:16 PM PDT 24
Finished Mar 21 12:56:18 PM PDT 24
Peak memory 182552 kb
Host smart-ca7308f9-dd66-4857-b6f1-69ecbf621e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305925918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.305925918
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.922640149
Short name T223
Test name
Test status
Simulation time 137439927243 ps
CPU time 213.47 seconds
Started Mar 21 12:50:18 PM PDT 24
Finished Mar 21 12:53:53 PM PDT 24
Peak memory 190720 kb
Host smart-70a033d6-0fee-4a17-a99d-5b2f9c7a776d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922640149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.922640149
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2457887826
Short name T293
Test name
Test status
Simulation time 135732063231 ps
CPU time 702.9 seconds
Started Mar 21 12:50:16 PM PDT 24
Finished Mar 21 01:01:59 PM PDT 24
Peak memory 190772 kb
Host smart-80092740-8afa-477a-a890-e9698e79bb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457887826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2457887826
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1749750830
Short name T1
Test name
Test status
Simulation time 348426404030 ps
CPU time 508.16 seconds
Started Mar 21 12:50:17 PM PDT 24
Finished Mar 21 12:58:46 PM PDT 24
Peak memory 194916 kb
Host smart-0bdd0a32-df8c-4983-9953-d1ee5f944242
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749750830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1749750830
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/71.rv_timer_random.1117391696
Short name T65
Test name
Test status
Simulation time 30019453296 ps
CPU time 42.36 seconds
Started Mar 21 12:51:49 PM PDT 24
Finished Mar 21 12:52:32 PM PDT 24
Peak memory 182628 kb
Host smart-9269ede9-958f-433c-b209-09ebf1d8fbe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117391696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1117391696
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3778158539
Short name T130
Test name
Test status
Simulation time 38623308919 ps
CPU time 266.29 seconds
Started Mar 21 12:52:03 PM PDT 24
Finished Mar 21 12:56:30 PM PDT 24
Peak memory 190824 kb
Host smart-c4591ae4-0485-4bfc-8605-42a2c64a544b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778158539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3778158539
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3726736347
Short name T227
Test name
Test status
Simulation time 106950755761 ps
CPU time 164.19 seconds
Started Mar 21 12:52:06 PM PDT 24
Finished Mar 21 12:54:50 PM PDT 24
Peak memory 190728 kb
Host smart-69d63e52-eda2-41d1-bfcf-3b1a0ef6407e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726736347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3726736347
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.4042439566
Short name T185
Test name
Test status
Simulation time 129220170424 ps
CPU time 1101.35 seconds
Started Mar 21 12:52:02 PM PDT 24
Finished Mar 21 01:10:24 PM PDT 24
Peak memory 190860 kb
Host smart-67c0e60a-4f46-4050-a2a8-7d93b9a0d3f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042439566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.4042439566
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.763142877
Short name T325
Test name
Test status
Simulation time 1728294930694 ps
CPU time 597.89 seconds
Started Mar 21 12:52:04 PM PDT 24
Finished Mar 21 01:02:02 PM PDT 24
Peak memory 190764 kb
Host smart-552afa5e-cf56-470a-b019-09d7dffc3b7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763142877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.763142877
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.1244491909
Short name T408
Test name
Test status
Simulation time 269595235388 ps
CPU time 239.6 seconds
Started Mar 21 12:50:14 PM PDT 24
Finished Mar 21 12:54:14 PM PDT 24
Peak memory 182580 kb
Host smart-ee01b241-9a9f-4175-ba50-068473402e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244491909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.1244491909
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.2111640029
Short name T249
Test name
Test status
Simulation time 20940726696 ps
CPU time 7.49 seconds
Started Mar 21 12:50:16 PM PDT 24
Finished Mar 21 12:50:24 PM PDT 24
Peak memory 182556 kb
Host smart-bd3e7ae0-feb0-406e-909a-a80ff8f07dd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111640029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2111640029
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.714454054
Short name T138
Test name
Test status
Simulation time 138634585191 ps
CPU time 927.59 seconds
Started Mar 21 12:50:17 PM PDT 24
Finished Mar 21 01:05:46 PM PDT 24
Peak memory 182532 kb
Host smart-3f75c4d7-915e-4c05-ab25-fa5c891ec75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714454054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.714454054
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.4255343306
Short name T192
Test name
Test status
Simulation time 1463153962420 ps
CPU time 687.47 seconds
Started Mar 21 12:50:15 PM PDT 24
Finished Mar 21 01:01:43 PM PDT 24
Peak memory 190788 kb
Host smart-de6a47f9-b508-4cdf-8600-5d9d3acc7dd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255343306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
4255343306
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.2530800703
Short name T346
Test name
Test status
Simulation time 122301414318 ps
CPU time 461.19 seconds
Started Mar 21 12:52:04 PM PDT 24
Finished Mar 21 12:59:45 PM PDT 24
Peak memory 190764 kb
Host smart-d4a89432-2578-4144-b00a-4c24dd454f3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530800703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2530800703
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.2406183183
Short name T331
Test name
Test status
Simulation time 1596433941222 ps
CPU time 455.56 seconds
Started Mar 21 12:52:03 PM PDT 24
Finished Mar 21 12:59:39 PM PDT 24
Peak memory 190764 kb
Host smart-9e9fed6d-6278-43bd-9cd4-9ad1ae166d48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406183183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2406183183
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1358727725
Short name T440
Test name
Test status
Simulation time 94512292057 ps
CPU time 608.19 seconds
Started Mar 21 12:52:04 PM PDT 24
Finished Mar 21 01:02:12 PM PDT 24
Peak memory 190796 kb
Host smart-3715f878-cfff-4daf-8173-5e031009d737
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358727725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1358727725
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.36819523
Short name T181
Test name
Test status
Simulation time 180497298765 ps
CPU time 1040.38 seconds
Started Mar 21 12:52:02 PM PDT 24
Finished Mar 21 01:09:23 PM PDT 24
Peak memory 190848 kb
Host smart-8f7f1c34-97ed-462c-9e67-ee20259c3b1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36819523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.36819523
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.124268914
Short name T254
Test name
Test status
Simulation time 303121090392 ps
CPU time 166.77 seconds
Started Mar 21 12:52:04 PM PDT 24
Finished Mar 21 12:54:52 PM PDT 24
Peak memory 190768 kb
Host smart-57925dca-5c52-42e9-88ba-1bd80d41c8a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124268914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.124268914
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.695720261
Short name T84
Test name
Test status
Simulation time 95168169144 ps
CPU time 53.76 seconds
Started Mar 21 12:52:05 PM PDT 24
Finished Mar 21 12:52:59 PM PDT 24
Peak memory 190776 kb
Host smart-5e6a9648-8bbf-4edf-b533-551e4094647c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695720261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.695720261
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3184274438
Short name T172
Test name
Test status
Simulation time 2983735352659 ps
CPU time 563 seconds
Started Mar 21 12:52:17 PM PDT 24
Finished Mar 21 01:01:40 PM PDT 24
Peak memory 190764 kb
Host smart-ce1c2121-26f3-40fe-a980-57b57cc666a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184274438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3184274438
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2783402351
Short name T219
Test name
Test status
Simulation time 613763036141 ps
CPU time 874.15 seconds
Started Mar 21 12:52:16 PM PDT 24
Finished Mar 21 01:06:50 PM PDT 24
Peak memory 190772 kb
Host smart-1fea62fc-739e-4b6a-b709-9e2c421d05cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783402351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2783402351
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.2963672625
Short name T206
Test name
Test status
Simulation time 434532249585 ps
CPU time 1532.23 seconds
Started Mar 21 12:52:16 PM PDT 24
Finished Mar 21 01:17:48 PM PDT 24
Peak memory 190760 kb
Host smart-4bec4453-d94b-4df5-a502-d582723e78de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963672625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2963672625
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.3278730131
Short name T60
Test name
Test status
Simulation time 416669373928 ps
CPU time 100.16 seconds
Started Mar 21 12:52:14 PM PDT 24
Finished Mar 21 12:53:55 PM PDT 24
Peak memory 190740 kb
Host smart-67b89bc7-3e2e-4f2f-bba1-9adefbf9e0cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278730131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3278730131
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.4021014164
Short name T151
Test name
Test status
Simulation time 257653452604 ps
CPU time 212.7 seconds
Started Mar 21 12:50:16 PM PDT 24
Finished Mar 21 12:53:50 PM PDT 24
Peak memory 182572 kb
Host smart-a8e79c1f-5622-42f1-9a05-d29d7dd4b28c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021014164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.4021014164
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.3320356279
Short name T368
Test name
Test status
Simulation time 13201120346 ps
CPU time 20.2 seconds
Started Mar 21 12:50:18 PM PDT 24
Finished Mar 21 12:50:40 PM PDT 24
Peak memory 182536 kb
Host smart-aa3b018c-56db-4315-b9a4-6e8814f69bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320356279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.3320356279
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.705863520
Short name T180
Test name
Test status
Simulation time 213057842404 ps
CPU time 232.88 seconds
Started Mar 21 12:50:19 PM PDT 24
Finished Mar 21 12:54:13 PM PDT 24
Peak memory 190820 kb
Host smart-5c6021c8-d241-4bf8-b250-54c936fefd4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705863520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.705863520
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3351958466
Short name T347
Test name
Test status
Simulation time 51013636673 ps
CPU time 136.45 seconds
Started Mar 21 12:50:21 PM PDT 24
Finished Mar 21 12:52:37 PM PDT 24
Peak memory 194288 kb
Host smart-15fda5ac-d50d-4dfe-a051-17ea13a0fd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351958466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3351958466
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1094054916
Short name T414
Test name
Test status
Simulation time 772387312314 ps
CPU time 547.19 seconds
Started Mar 21 12:50:17 PM PDT 24
Finished Mar 21 12:59:26 PM PDT 24
Peak memory 195208 kb
Host smart-5145cc86-e97b-4cb9-982a-5377cf38a3e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094054916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1094054916
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.2051874709
Short name T226
Test name
Test status
Simulation time 912249296364 ps
CPU time 537.73 seconds
Started Mar 21 12:52:16 PM PDT 24
Finished Mar 21 01:01:14 PM PDT 24
Peak memory 190748 kb
Host smart-f6924ff2-a1bb-48ac-9e90-65268c9a4dcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051874709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2051874709
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.94070088
Short name T313
Test name
Test status
Simulation time 154588116870 ps
CPU time 1579.94 seconds
Started Mar 21 12:52:13 PM PDT 24
Finished Mar 21 01:18:33 PM PDT 24
Peak memory 190808 kb
Host smart-bcc14868-2eb9-4fb9-b612-6e6a71aaa966
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94070088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.94070088
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.2808076690
Short name T320
Test name
Test status
Simulation time 15013884235 ps
CPU time 24.52 seconds
Started Mar 21 12:52:16 PM PDT 24
Finished Mar 21 12:52:41 PM PDT 24
Peak memory 190888 kb
Host smart-dc76019c-86f8-4d72-8f95-e3f83de87c91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808076690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2808076690
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.1010682361
Short name T89
Test name
Test status
Simulation time 507478881894 ps
CPU time 457.83 seconds
Started Mar 21 12:52:17 PM PDT 24
Finished Mar 21 12:59:55 PM PDT 24
Peak memory 190760 kb
Host smart-8e2ea0d9-291b-48a7-acd0-84646884c97e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010682361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1010682361
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.689622118
Short name T167
Test name
Test status
Simulation time 115042884397 ps
CPU time 317.99 seconds
Started Mar 21 12:52:15 PM PDT 24
Finished Mar 21 12:57:33 PM PDT 24
Peak memory 190720 kb
Host smart-59acfdff-5b36-4ab3-aec2-cdc9574d9011
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689622118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.689622118
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.2952264852
Short name T324
Test name
Test status
Simulation time 70782958877 ps
CPU time 1112.09 seconds
Started Mar 21 12:52:16 PM PDT 24
Finished Mar 21 01:10:48 PM PDT 24
Peak memory 182556 kb
Host smart-0ce6471f-17df-4dc6-889d-ec5aa36f37fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952264852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.2952264852
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.509028436
Short name T154
Test name
Test status
Simulation time 1496077208451 ps
CPU time 298.7 seconds
Started Mar 21 12:52:15 PM PDT 24
Finished Mar 21 12:57:14 PM PDT 24
Peak memory 190804 kb
Host smart-29f08849-8b6d-477f-a811-f4e82fc8b0d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509028436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.509028436
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2103553255
Short name T208
Test name
Test status
Simulation time 55008682982 ps
CPU time 44.95 seconds
Started Mar 21 12:52:15 PM PDT 24
Finished Mar 21 12:53:00 PM PDT 24
Peak memory 194200 kb
Host smart-973f9225-d6a0-4c46-80a4-6c11e4f80c64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103553255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2103553255
Directory /workspace/98.rv_timer_random/latest
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